* sim/cris/asm/x1-v10.ms, sim/cris/asm/x3-v10.ms,

	sim/cris/asm/x7-v10.ms: Update expected cycle output.

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 20c2c520ffdca17230796b78bf6e02925a3c817f..b775c983da2ee7f743b64d86e997027df33bf1ca 100644 (file)
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2006-01-10  Hans-Peter Nilsson  <hp@axis.com>
+
+       * sim/cris/asm/x1-v10.ms, sim/cris/asm/x3-v10.ms,
+       sim/cris/asm/x7-v10.ms: Update expected cycle output.
+
 2005-12-06  Hans-Peter Nilsson  <hp@axis.com>
 
        * sim/cris/asm/movmp8.ms, sim/cris/asm/pcplus.ms: New tests.

diff --git a/sim/testsuite/sim/cris/asm/x1-v10.ms b/sim/testsuite/sim/cris/asm/x1-v10.ms
index e1a87c1053cf0db6a7080fc4c56cf1f6b6531216..bfc48590bcffeb1993468cd507ff86b51a2e958e 100644 (file)
--- a/sim/testsuite/sim/cris/asm/x1-v10.ms
+++ b/sim/testsuite/sim/cris/asm/x1-v10.ms
@@ -2,7 +2,9 @@
 #ld: --section-start=.text=0
 #output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
 #output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
-#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 3\n
+#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 2\n
 #sim: --cris-trace=basic
 
+; With a "--cris-trace=all", cycles for the last line would be 3.
+
  .include "movect10.ms"

diff --git a/sim/testsuite/sim/cris/asm/x3-v10.ms b/sim/testsuite/sim/cris/asm/x3-v10.ms
index 113e18db491f9b4d05699547af9f86c13019c5dd..fc54f3c358ba023a42712397809d8173bd8bed03 100644 (file)
--- a/sim/testsuite/sim/cris/asm/x3-v10.ms
+++ b/sim/testsuite/sim/cris/asm/x3-v10.ms
@@ -2,9 +2,11 @@
 #ld: --section-start=.text=0
 #output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
 #output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
-#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 3\n
+#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n
 #output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1\n
 #output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n
 #sim: --cris-trace=basic
 
+; With a "--cris-trace=all", cycles for the third line would be 3.
+
  .include "tjsrcv10.ms"

diff --git a/sim/testsuite/sim/cris/asm/x7-v10.ms b/sim/testsuite/sim/cris/asm/x7-v10.ms
index f465143f504811e85199d8e21dffea5155132648..8b548ff1ea56513139c9705ef81fa57e82f1ffcb 100644 (file)
--- a/sim/testsuite/sim/cris/asm/x7-v10.ms
+++ b/sim/testsuite/sim/cris/asm/x7-v10.ms
@@ -2,14 +2,16 @@
 #ld: --section-start=.text=0
 #output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
 #output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
-#output: c 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 5\n
+#output: c 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 4\n
 #output: e 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
 #output: 10 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n
 #output: 14 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n
 #output: 18 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n
-#output: 20 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 5\n
+#output: 20 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 4\n
 #sim: --cris-trace=basic
 
+; With a "--cris-trace=all", cycles for the third and last line would be 5.
+
 ; Check that prefix+insn are traced as one.
 
  .include "testutils.inc"