Move $dffe to dffs.{v,ys}

diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
index af7022c7944e426a1766944dd728c40de2d82ed8..972184cfa29e4713f29cea8b717e1e8fd38e98bd 100644 (file)
--- a/tests/ice40/adffs.v
+++ b/tests/ice40/adffs.v
@@ -22,16 +22,6 @@ module adffn
             q <= d;
 endmodule
 
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-       always @( posedge clk )
-               if ( en )
-                       q <= d;
-endmodule
-
 module dffsr
     ( input d, clk, pre, clr, output reg q );
     initial begin

diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index aee8cd6b466ed63c11679c9a99dbc27758914bd1..d58ce1a82d4e3cbef66a784b644c75550beb2fa1 100644 (file)
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -1,8 +1,11 @@
 read_verilog adffs.v
 proc
-dff2dffe
-synth_ice40
-select -assert-count 2 t:SB_DFFR
+async2sync
+synth -flatten -run coarse # technology-independent coarse grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFF
 select -assert-count 1 t:SB_DFFE
 select -assert-count 4 t:SB_LUT4
 #select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D

diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v
index d57c8c97cd6e898377312f5d0413c27c66b3d99f..d97840c439411c0c63b3df766a1798b5fc9caad8 100644 (file)
--- a/tests/ice40/dffs.v
+++ b/tests/ice40/dffs.v
@@ -1,5 +1,37 @@
-module top
+module dff
     ( input d, clk, output reg q );
        always @( posedge clk )
             q <= d;
 endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+       always @( posedge clk )
+               if ( en )
+                       q <= d;
+endmodule
+
+module top (
+input clk,
+input en,
+input a,
+output b,b1,
+);
+
+dff u_dff (
+        .clk (clk ),
+        .d (a ),
+        .q (b )
+    );
+
+dffe u_ndffe (
+        .clk (clk ),
+        .en (en),
+        .d (a ),
+        .q (b1 )
+    );
+
+endmodule

diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys
index 0fa0bc3eb2977663fa40dd159e71815951e68c80..ddd8e5734946f4b3b28e72f3d2db2303fdcbe31e 100644 (file)
--- a/tests/ice40/dffs.ys
+++ b/tests/ice40/dffs.ys
@@ -1,11 +1,9 @@
 read_verilog dffs.v
-proc
-flatten
-dff2dffe
 hierarchy -top top
 synth -flatten -run coarse # technology-independent coarse grained synthesis
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFF
-select -assert-none t:SB_DFF %% t:* %D
+select -assert-count 1 t:SB_DFFE
+select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D