[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Tue, 26 May 2020 10:01:25 +0000 (10:01 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Tue, 26 May 2020 10:01:27 +0000 (11:01 +0100)
7c/6264c1ffe1bf99df1e187f7c35ce22d3f6d865 [new file with mode: 0644]

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+Date: Tue, 26 May 2020 10:01:25 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
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+Message-ID: <bug-336-13-c4VXTTgL5p@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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