fix DDR3 on arty

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index bec4f81a02ebd1fa0f347a0c3441708ea16be4b5..c3e5dd70eb1090451d42b2e9fa28bf4c4ee05425 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -108,6 +108,8 @@ class BaseSoC(SoCSDRAM):
 
         # sdram
         self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
+        self.add_constant("READ_LEVELING_BITSLIP", 3)
+        self.add_constant("READ_LEVELING_DELAY", 14)
         sdram_module = MT41K128M16(self.clk_freq, "1:4")
         self.register_sdram(self.ddrphy,
                             sdram_module.geom_settings,