[ARC] Deprecate q-class option.

This option was used to control the short instruction selection.  However,
there is no difference in cycles if we use or not a short instruction,
and always someone wants a smaller program.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
	R12-R15 are always in ARCOMPACT16_REGS register class.
	* config/arc/arc.opt (mq-class): Deprecate.
	* config/arc/constraint.md ("q"): Remove dependency on mq-class
	option.
	* doc/invoke.texi (mq-class): Update text.
	* common/config/arc/arc-common.c (arc_option_optimization_table):
	Update list.

testsuite/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/nps400-1.c: Update test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 96a6b8037d56f613e7b086370c5b045e0d051bb3..dc5e403637b48d390017011d8f8c2275b55915b5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-02-13  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
+       R12-R15 are always in ARCOMPACT16_REGS register class.
+       * config/arc/arc.opt (mq-class): Deprecate.
+       * config/arc/constraint.md ("q"): Remove dependency on mq-class
+       option.
+       * doc/invoke.texi (mq-class): Update text.
+       * common/config/arc/arc-common.c (arc_option_optimization_table):
+       Update list.
+
 2020-02-13  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * config/arc/arc.c (arc_insn_cost): New function.

diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c
index f1e2d055285334a5fc0e24d29c46b32bae0d37e4..082aa09283df62ae4abbe74b1d886d3825c2e5e5 100644 (file)
--- a/gcc/common/config/arc/arc-common.c
+++ b/gcc/common/config/arc/arc-common.c
@@ -56,7 +56,6 @@ static const struct default_options arc_option_optimization_table[] =
     { OPT_LEVELS_SIZE, OPT_fbranch_count_reg, NULL, 0},
     { OPT_LEVELS_SIZE, OPT_fdelayed_branch, NULL, 0 },
     { OPT_LEVELS_SIZE, OPT_fsection_anchors, NULL, 1 },
-    { OPT_LEVELS_SIZE, OPT_mq_class, NULL, 1 },
     { OPT_LEVELS_SIZE, OPT_mcase_vector_pcrel, NULL, 1 },
     { OPT_LEVELS_SIZE, OPT_msize_level_, NULL, 3 },
     { OPT_LEVELS_SIZE, OPT_mmillicode, NULL, 1 },

diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 7a9fe08f31dfcfd721fab9f4acba299465063537..fe9077ab665369db1d7a7eaaa0b6deca4625557d 100644 (file)
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1427,9 +1427,6 @@ arc_override_options (void)
   if (flag_no_common == 255)
     flag_no_common = !TARGET_NO_SDATA_SET;
 
-  if (TARGET_MIXED_CODE)
-    TARGET_Q_CLASS = 1;
-
   /* Check for small data option */
   if (!global_options_set.x_g_switch_value && !TARGET_NO_SDATA_SET)
     g_switch_value = TARGET_LL64 ? 8 : 4;
@@ -1956,8 +1953,7 @@ arc_conditional_register_usage (void)
   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
     if (i < ILINK1_REG)
       {
-       if ((TARGET_Q_CLASS || TARGET_RRQ_CLASS)
-           && ((i <= R3_REG) || ((i >= R12_REG) && (i <= R15_REG))))
+       if ((i <= R3_REG) || ((i >= R12_REG) && (i <= R15_REG)))
          arc_regno_reg_class[i] = ARCOMPACT16_REGS;
        else
          arc_regno_reg_class[i] = GENERAL_REGS;

diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
index 94c6f5403e1d480024f6ce51125c5f6f9ddac6e2..7b994236a514b8e61f2dd229db0ffe2da20ae00c 100644 (file)
--- a/gcc/config/arc/arc.opt
+++ b/gcc/config/arc/arc.opt
@@ -335,7 +335,7 @@ Target Warn(%qs is deprecated)
 Enable compact casesi pattern.
 
 mq-class
-Target Var(TARGET_Q_CLASS)
+Target Warn(%qs is deprecated)
 Enable 'q' instruction alternatives.
 
 mexpand-adddi

diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md
index 3be2a8abab04ac5b695dc3e267d4c2e94a2b6b41..b7a563a72ada533c226f96d8a124b97fdc7ac559 100644 (file)
--- a/gcc/config/arc/constraints.md
+++ b/gcc/config/arc/constraints.md
@@ -53,7 +53,7 @@
 (define_register_constraint "x" "R0_REGS"
   "@code{R0} register.")
 
-(define_register_constraint "q" "TARGET_Q_CLASS ? ARCOMPACT16_REGS : NO_REGS"
+(define_register_constraint "q" "ARCOMPACT16_REGS"
   "Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
    @code{r12}-@code{r15}")
 

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index fa98e2f23f74db2fb1a97239c46240cb77631e2d..bd9ecebf1030190bf0e9a14862e3d5fad9c544e3 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17845,7 +17845,7 @@ while increasing the instruction count.
 
 @item -mq-class
 @opindex mq-class
-Enable @samp{q} instruction alternatives.
+Ths option is deprecated.  Enable @samp{q} instruction alternatives.
 This is the default for @option{-Os}.
 
 @item -mRcq

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 572042662d6cac697833481bc03795cea58f8813..5ac858efb1b7748a1629a320fa933c17a57b2b81 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2020-02-13  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * gcc.target/arc/nps400-1.c: Update test.
+
 2020-02-13  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * gcc.target/arc/or-cnst-size2.c: Update test.

diff --git a/gcc/testsuite/gcc.target/arc/nps400-1.c b/gcc/testsuite/gcc.target/arc/nps400-1.c
index 504aad734ccba8ec78a595c84ca1ee4cad702cbc..29486a30ee932df5da3e5696681de911f22b85bc 100644 (file)
--- a/gcc/testsuite/gcc.target/arc/nps400-1.c
+++ b/gcc/testsuite/gcc.target/arc/nps400-1.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-skip-if "" { ! { clmcpu } } } */
-/* { dg-options "-mcpu=nps400 -mq-class -mbitops -munaligned-access -mcmem -O2 -fno-strict-aliasing" } */
+/* { dg-options "-mcpu=nps400 -mbitops -munaligned-access -mcmem -O2 -fno-strict-aliasing" } */
 
 enum npsdp_mem_space_type {
   NPSDP_EXTERNAL_MS = 1