[AArch64][Patch 4/5] Support HINT aliases taking operands.

The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds support for aliases
of HINT which take an operand, adding a table to store operand names and
their matching hint number as well as encoding and decoding functions
for such operands. Parsing and printing the operands are deferred to any
support added for aliases with such operands.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_hint_options): Declare.
	(aarch64_opnd_info): Add field hint_option.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm.c (aarch64_ins_hint): New.
	* aarch64-asm.h (aarch64_ins_hint): Declare.
	* aarch64-dis.c (aarch64_ext_hint): New.
	* aarch64-dis.h (aarch64_ext_hint): Declare.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (aarch64_hint_options): New.
	* aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.

Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index c4c478408f6216a8c8b2fee0b9e76322f1ddb418..603bdb99bf680cbb280ebb848bfaff4bb7b753fa 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (aarch64_hint_options): Declare.
+       (aarch64_opnd_info): Add field hint_option.
+
 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 
        * aarch64.h (AARCH64_FEATURE_PROFILE): New.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 27509dadfd70fef310c7964adcffbeb768336530..70486c9d3605eaaefe4f53e77bcb15732349455f 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -653,6 +653,7 @@ struct aarch64_name_value_pair
 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 extern const struct aarch64_name_value_pair aarch64_prfops [32];
+extern const struct aarch64_name_value_pair aarch64_hint_options [];
 
 typedef struct
 {
@@ -786,6 +787,7 @@ struct aarch64_opnd_info
       aarch64_insn pstatefield;
       const aarch64_sys_ins_reg *sysins_op;
       const struct aarch64_name_value_pair *barrier;
+      const struct aarch64_name_value_pair *hint_option;
       const struct aarch64_name_value_pair *prfop;
     };
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ace1392874af557f066036219e60bf3bfc37403c..3fdf63b0172f64fafcd877a5aa3555a43c0021ff 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm.c (aarch64_ins_hint): New.
+       * aarch64-asm.h (aarch64_ins_hint): Declare.
+       * aarch64-dis.c (aarch64_ext_hint): New.
+       * aarch64-dis.h (aarch64_ext_hint): Declare.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-opc.c (aarch64_hint_options): New.
+       * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
+
 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 
        * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index ef645014cb2f56f698ec900c3c03309b82965727..cf4e440f5991abca60d72464bd913069a47c3acf 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -667,6 +667,19 @@ aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
   return NULL;
 }
 
+/* Encode the hint number for instructions that alias HINT but take an
+   operand.  */
+
+const char *
+aarch64_ins_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
+                 const aarch64_opnd_info *info, aarch64_insn *code,
+                 const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+  /* CRm:op2.  */
+  insert_fields (code, info->hint_option->value, 0, 2, FLD_op2, FLD_CRm);
+  return NULL;
+}
+
 /* Encode the extended register operand for e.g.
      STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
 const char *

diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index 386b2a3705462a02c77a2f752ff3befe17761687..64361eb727e816ed8dc64391e64ba26cd1d7f975 100644 (file)
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -64,6 +64,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sysreg);
 AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
 AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
 AARCH64_DECL_OPD_INSERTER (ins_barrier);
+AARCH64_DECL_OPD_INSERTER (ins_hint);
 AARCH64_DECL_OPD_INSERTER (ins_prfop);
 AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
 AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 631f076f0f86bf852720dd2a0b210781eb5e98a6..6763c360596e996dbfce489520f9ee5606d8afbf 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1067,6 +1067,33 @@ aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
   return 1;
 }
 
+/* Decode the hint number for an alias taking an operand.  Set info->hint_option
+   to the matching name/value pair in aarch64_hint_options.  */
+
+int
+aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
+                 aarch64_opnd_info *info,
+                 aarch64_insn code,
+                 const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+  /* CRm:op2.  */
+  unsigned hint_number;
+  int i;
+
+  hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2);
+
+  for (i = 0; aarch64_hint_options[i].name != NULL; i++)
+    {
+      if (hint_number == aarch64_hint_options[i].value)
+       {
+         info->hint_option = &(aarch64_hint_options[i]);
+         return 1;
+       }
+    }
+
+  return 0;
+}
+
 /* Decode the extended register operand for e.g.
      STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
 int

diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index 767191cc68d24cbf11386c32761dd6b2fc85e1ec..3704f5352c31293dc3199f3d5c32f36c7c14c90d 100644 (file)
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -86,6 +86,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sysreg);
 AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield);
 AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op);
 AARCH64_DECL_OPD_EXTRACTOR (ext_barrier);
+AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
 AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
 AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
 AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 968e99c91cdda88b00a281fe50f1e087a8d76f8c..ef7e0a4403527f7f69615205539a74cf12cba7b5 100644 (file)
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -107,11 +107,11 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a PSTATE field name"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address translation operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a data cache maintenance operation specifier"},
-  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instructin cache maintenance operation specifier"},
+  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instruction cache maintenance operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
   {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
-  {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an prefetch operation specifier"},
+  {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
   {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
 };
 

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a75c415cf92e6c3b2788b77de5b80e93044255cf..5f65f8ce7dac088ed36f27e818a53c69cc3b53b3 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -335,6 +335,18 @@ const struct aarch64_name_value_pair aarch64_barrier_options[16] =
     { "sy",    0xf },
 };
 
+/* Table describing the operands supported by the aliases of the HINT
+   instruction.
+
+   The name column is the operand that is accepted for the alias.  The value
+   column is the hint number of the alias.  The list of operands is terminated
+   by NULL in the name column.  */
+
+const struct aarch64_name_value_pair aarch64_hint_options[] =
+{
+  { NULL, 0x0 },
+};
+
 /* op -> op:       load = 0 instruction = 1 store = 2
    l  -> level:    1-3
    t  -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1   */

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 91d8dcf103540156828d157bf0789c6b7740fc8d..9e743db6b4b976acefb03fef6bebe306977f1c8f 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2654,7 +2654,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
     Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(),                          \
       "a data cache maintenance operation specifier")                  \
     Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(),                          \
-      "an instructin cache maintenance operation specifier")           \
+      "an instruction cache maintenance operation specifier")          \
     Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(),                                \
       "a TBL invalidation operation specifier")                                \
     Y(SYSTEM, barrier, "BARRIER", 0, F(),                              \
@@ -2662,4 +2662,4 @@ struct aarch64_opcode aarch64_opcode_table[] =
     Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(),                          \
       "the ISB option name SY or an optional 4-bit unsigned immediate")        \
     Y(SYSTEM, prfop, "PRFOP", 0, F(),                                  \
-      "an prefetch operation specifier")
+      "a prefetch operation specifier")