vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals.

Fixes #88.

diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py
index c02e370203614c4eb2e7e0ac6e6dfa8b00f0fd56..f4e7d38f5137b1fe4cdde4db5baeae7bd4bb2fa4 100644 (file)
--- a/nmigen/vendor/lattice_ecp5.py
+++ b/nmigen/vendor/lattice_ecp5.py
@@ -121,7 +121,7 @@ class LatticeECP5Platform(TemplatedPlatform):
                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
             {% endfor %}
             {% for signal, frequency in platform.iter_clock_constraints() -%}
-                FREQUENCY PORT "{{signal.name}}" {{frequency}} HZ;
+                FREQUENCY NET "{{signal|hierarchy(".")}}" {{frequency}} HZ;
             {% endfor %}
         """
     }
@@ -203,7 +203,7 @@ class LatticeECP5Platform(TemplatedPlatform):
                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
             {% endfor %}
             {% for signal, frequency in platform.iter_clock_constraints() -%}
-                FREQUENCY PORT "{{signal.name}}" {{frequency/1000000}} MHZ;
+                FREQUENCY NET "{{signal|hierarchy("/")}}" {{frequency/1000000}} MHZ;
             {% endfor %}
             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
         """,

diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py
index e403341f4af0f4e62dd497330a81dfebdbe52439..e4b2a80dae81fa1bb456727f3977de5b8844d75b 100644 (file)
--- a/nmigen/vendor/lattice_ice40.py
+++ b/nmigen/vendor/lattice_ice40.py
@@ -97,7 +97,7 @@ class LatticeICE40Platform(TemplatedPlatform):
             # {{autogenerated}}
             {% for signal, frequency in platform.iter_clock_constraints() -%}
             {# Clock in MHz #}
-            ctx.addClock("{{signal.name}}", {{frequency/1000000}})
+            ctx.addClock("{{signal|hierarchy(".")}}", {{frequency/1000000}})
             {% endfor%}
         """,
     }