Better word error messages.
authorAndrew Cagney <cagney@redhat.com>
Tue, 9 Sep 1997 10:38:39 +0000 (10:38 +0000)
committerAndrew Cagney <cagney@redhat.com>
Tue, 9 Sep 1997 10:38:39 +0000 (10:38 +0000)
sim/mips/ChangeLog
sim/mips/interp.c

index 56bf29176430cabc71ad8c7418404e230f6bb1c1..a69ac32d114affb2cd763d2fced66b905ddb9b0d 100644 (file)
@@ -1,3 +1,8 @@
+Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
+       MFC0.
+
 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * gencode.c (build_instruction): Use SIGNED64 for 64 bit
index 6ace9e3149c886e9b7d97faa6c77b5b79a6b49c1..9336ce3a0e96ad1d0fc48dce05ba3c40eb3ed095 100644 (file)
@@ -4127,9 +4127,9 @@ decode_coproc(instruction)
                /* CPR[0,rd] = GPR[rt]; */
              default:
                if (code == 0x00)
-                 callback->printf_filtered(callback,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
+                 callback->printf_filtered(callback,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
                else
-                 callback->printf_filtered(callback,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
+                 callback->printf_filtered(callback,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
              }
          }
        else if (code == 0x10 && (instruction & 0x3f) == 0x18)