Re: [libre-riscv-dev] effects of powered-off chip sections on current leakage

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+From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date: Sun, 14 Jun 2020 12:30:21 +0100
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+To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
+Subject: Re: [libre-riscv-dev] effects of powered-off chip sections on
+ current leakage
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