change name of 2nd switch_cpu so that ckpt recovery with multiple cpus doens't get...

--HG--
extra : convert_revision : 16c710c4196c520d03c1993a26f38cf1f04ab637

diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index a05e36bd12d8e4223119c0e9d2fffd059fcb2eaa..a2b1d84d253774df0c9121edfcca4c0c6ce9961a 100644 (file)
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -53,25 +53,27 @@ def run(options, root, testsys):
     if options.standard_switch:
         switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
                        for i in xrange(np)]
-        switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
+        switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
                         for i in xrange(np)]
+
         for i in xrange(np):
             switch_cpus[i].system =  testsys
-            switch_cpus1[i].system =  testsys
+            switch_cpus_1[i].system =  testsys
             if not m5.build_env['FULL_SYSTEM']:
                 switch_cpus[i].workload = testsys.cpu[i].workload
-                switch_cpus1[i].workload = testsys.cpu[i].workload
+                switch_cpus_1[i].workload = testsys.cpu[i].workload
             switch_cpus[i].clock = testsys.cpu[0].clock
-            switch_cpus1[i].clock = testsys.cpu[0].clock
+            switch_cpus_1[i].clock = testsys.cpu[0].clock
             if options.caches:
                 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                        L1Cache(size = '64kB'))
 
             switch_cpus[i].connectMemPorts(testsys.membus)
+
             root.switch_cpus = switch_cpus
-            root.switch_cpus1 = switch_cpus1
+            root.switch_cpus_1 = switch_cpus_1
             switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
-            switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)]
+            switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
 
     m5.instantiate(root)