gallium/radeon: query the CPU accessible size of VRAM
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Wed, 25 Jan 2017 15:56:45 +0000 (16:56 +0100)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Thu, 26 Jan 2017 18:40:14 +0000 (19:40 +0100)
R600_DEBUG="info" can be used to display that size, as well as
the total amount of VRAM/GTT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeon/r600_pipe_common.c
src/gallium/drivers/radeon/radeon_winsys.h
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

index 51137655faef8ae400f990ede147224eca41708b..7c8fe786156fdd438f6474f1574b6c7bcd5bbad9 100644 (file)
@@ -1279,6 +1279,7 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
                printf("chip_class = %i\n", rscreen->info.chip_class);
                printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
                printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
+               printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
                printf("max_alloc_size = %i MB\n",
                       (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
                printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
index 476f0647ddeed9e67bbb66dbbf861dad3b77372e..e373e2f0a13cb9c10370886ea715571516463917 100644 (file)
@@ -184,6 +184,7 @@ struct radeon_info {
     uint32_t                    gart_page_size;
     uint64_t                    gart_size;
     uint64_t                    vram_size;
+    uint64_t                    vram_vis_size;
     uint64_t                    max_alloc_size;
     uint32_t                    min_alloc_size;
     bool                        has_dedicated_vram;
index 501f6f980dbc4010033bf5f94784da16b74b80b2..ea4d25476fcc523d5d9c15f26aeb6f6bd5c49655 100644 (file)
@@ -100,7 +100,7 @@ static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
 static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
 {
    struct amdgpu_buffer_size_alignments alignment_info = {};
-   struct amdgpu_heap_info vram, gtt;
+   struct amdgpu_heap_info vram, vram_vis, gtt;
    struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
    uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
    uint32_t unused_feature;
@@ -138,6 +138,14 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
       goto fail;
    }
 
+   r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
+                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
+                              &vram_vis);
+   if (r) {
+      fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
+      goto fail;
+   }
+
    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
    if (r) {
       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
@@ -322,6 +330,7 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
    /* Set hardware information. */
    ws->info.gart_size = gtt.heap_size;
    ws->info.vram_size = vram.heap_size;
+   ws->info.vram_vis_size = vram_vis.heap_size;
    /* The kernel can split large buffers, so we can do large allocations. */
    ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.9;
    /* convert the shader clock from KHz to MHz */
index f5de66e8bddacd1ace323bc0cffd7f9faef3bc54..ce5b7ffef1f4107748a3241d5ff66b7d331df3cd 100644 (file)
@@ -372,6 +372,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     }
     ws->info.gart_size = gem_info.gart_size;
     ws->info.vram_size = gem_info.vram_size;
+    ws->info.vram_vis_size = gem_info.vram_visible;
 
     /* Radeon allocates all buffers as contigous, which makes large allocations
      * unlikely to succeed. */