[arm] Fix gcc.target/arm/pr40956.c

The scan-assembler tests here check for MOVS for Thumb1 and MOV for Thumb2,
but in fact there's no reason why we wouldn't generate MOVS for Thumb2 as well,
it really depends on a lot of optimisation decisions.
The only behaviour we want to test is that we move a 0 constant into a register
only once, which can be achieved with either MOV or MOVS.
Simplify the check by always checking for either MOV or MOVS.

      * gcc.target/arm/pr40956.c: Adjust scan-assembler pattern.

From-SVN: r256880

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d86316ee909e3b5e154b3dec45871856c0a48e5a..a0000cd70ad47365f2d9a0c3706fe45e96395f27 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2018-01-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * gcc.target/arm/pr40956.c: Adjust scan-assembler pattern.
+
 2018-01-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * gcc.target/arm/pr79058.c: Add arm_arm_ok check and -marm to options.

diff --git a/gcc/testsuite/gcc.target/arm/pr40956.c b/gcc/testsuite/gcc.target/arm/pr40956.c
index 4fefa49a5878a90e3a78db7d3df1015a36d0897f..7429272a8c26a00ed40ead45d8d5737986e4bb0a 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/pr40956.c
+++ b/gcc/testsuite/gcc.target/arm/pr40956.c
@@ -1,8 +1,7 @@
 /* { dg-options "-Os -fpic" }  */
 /* { dg-require-effective-target fpic } */
 /* Make sure the constant "0" is loaded into register only once.  */
-/* { dg-final { scan-assembler-times "movs\[\\t \]*r., #0" 1 { target arm_thumb1 } } } */
-/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 { target { ! arm_thumb1 } } } } */
+/* { dg-final { scan-assembler-times "movs?\[\\t \]*r., #0" 1 } } */
 
 int foo(int p, int* q)
 {