boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/projects/pd/randd/dist/binaries/console
+console=/gem5/dist/binaries/console
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux
+kernel=/gem5/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/projects/pd/randd/dist/binaries/ts_osfpal
+pal=/gem5/dist/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
[system.disk0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.iocache]
type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
assoc=8
block_size=64
clock=1000
forward_snoops=false
-hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[system.terminal]
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 13:40:49
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:09:21
+gem5 started Jan 4 2013 21:41:13
+gem5 executing on u200540
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /gem5/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 107840000
sim_ticks 1897857556000 # Number of ticks simulated
final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 131170 # Simulator instruction rate (inst/s)
-host_op_rate 131170 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4437782045 # Simulator tick rate (ticks/s)
-host_mem_usage 332328 # Number of bytes of host memory used
-host_seconds 427.66 # Real time elapsed on the host
+host_inst_rate 54087 # Simulator instruction rate (inst/s)
+host_op_rate 54087 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1829896991 # Simulator tick rate (ticks/s)
+host_mem_usage 335972 # Number of bytes of host memory used
+host_seconds 1037.14 # Real time elapsed on the host
sim_insts 56096024 # Number of instructions simulated
sim_ops 56096024 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory
system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes
system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads
system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1561000 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 765601 # number of misc regfile writes
+system.cpu0.misc_regfile_reads 1567878 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 765605 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.cpu0.dcache.overall_misses::total 3066244 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31388896500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 31388896500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591366614 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 67591366614 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591367114 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 67591367114 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251807000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 251807000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4105000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 4105000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263114 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 98980263114 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263114 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 98980263114 # number of overall miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4104500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 4104500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263614 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 98980263614 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263614 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 98980263614 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.overall_miss_rate::total 0.251872 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.533997 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.533997 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.534296 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.534296 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6108.630952 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6108.630952 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 32280.621866 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 32280.621866 # average overall miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6107.886905 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6107.886905 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 32280.622029 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 32280.622029 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 2359081 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 46623 # number of cycles access was blocked
system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225287 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225287 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225787 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225787 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2761000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2761000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275728787 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 29275728787 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275728787 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 29275728787 # number of overall MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2760500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275729287 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 29275729287 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275729287 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 29275729287 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.378365 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.378365 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.380304 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.380304 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4108.630952 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4108.630952 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4107.886905 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4107.886905 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 17895154 # Number of instructions fetch has processed
+system.cpu1.fetch.Insts 17895150 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 3257696 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.Cycles 3257695 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 9888413 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.BlockedCycles 9888414 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 2125846 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 78174 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.CacheLines 2125845 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 78173 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 18634782 85.12% 85.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 18634783 85.12% 85.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 494265 2.26% 91.27% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 494264 2.26% 91.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total)
system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 8509917 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 2827279 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 6300793 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 2835389 # Number of cycles rename is running
+system.cpu1.rename.IdleCycles 8509918 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 2827280 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 6300792 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 2835388 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 16406077 # Number of instructions processed by rename
+system.cpu1.rename.RenamedInsts 16406070 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 10874639 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 19629758 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 19484069 # Number of integer rename lookups
+system.cpu1.rename.RenamedOperands 10874634 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 19629751 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 19484062 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1710467 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.UndoneMaps 1710462 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer
system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 2193720 # Number of cycles IEW is blocking
+system.cpu1.iew.iewBlockCycles 2193721 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 185768 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispSquashedInsts 185761 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions
system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes
system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads
system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 586782 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 255768 # number of misc regfile writes
+system.cpu1.misc_regfile_reads 592079 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 255780 # number of misc regfile writes
system.cpu1.icache.replacements 297472 # number of replacements
system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use
-system.cpu1.icache.total_refs 1814154 # Total number of references to valid blocks.
+system.cpu1.icache.total_refs 1814153 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 6.088092 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 6.088089 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 1814154 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 1814154 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 1814154 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 1814154 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 1814154 # number of overall hits
-system.cpu1.icache.overall_hits::total 1814154 # number of overall hits
+system.cpu1.icache.ReadReq_hits::cpu1.inst 1814153 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 1814153 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 1814153 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 1814153 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 1814153 # number of overall hits
+system.cpu1.icache.overall_hits::total 1814153 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses
system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125846 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 2125846 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 2125846 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 2125846 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 2125846 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 2125846 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125845 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 2125845 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 2125845 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 2125845 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 2125845 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 2125845 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses
system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 719 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 719 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 718 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 718 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses
system.cpu1.dcache.overall_misses::total 774607 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736451500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 6736451500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736455500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 6736455500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 20256376174 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 20256376174 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 20256376174 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 20256376174 # number of overall miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 20256380174 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 20256380174 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 20256380174 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 20256380174 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2469035 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2469035 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1516715 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1516715 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 47099 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 47099 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43242 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 43242 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43241 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 43241 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 3985750 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 3985750 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 3985750 # number of overall (read+write) accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.225055 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149366 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149366 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016627 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016627 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016605 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016605 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.216783 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.216783 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.226016 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.226016 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14506.183369 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14506.183369 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7059.805285 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7059.805285 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 26150.520424 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 26150.520424 # average overall miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7069.637883 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7069.637883 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 26150.525588 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 26150.525588 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 473544 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 3 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 7013 # number of cycles access was blocked
system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123298500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123298500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123299000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123299000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152410804 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 5152410804 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152410804 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 5152410804 # number of overall MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152411304 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 5152411304 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152411304 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 5152411304 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016604 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016604 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016605 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016605 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.997390 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.997390 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.999478 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.999478 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/projects/pd/randd/dist/binaries/console
+console=/gem5/dist/binaries/console
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux
+kernel=/gem5/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/projects/pd/randd/dist/binaries/ts_osfpal
+pal=/gem5/dist/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
[system.disk0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.iocache]
type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
assoc=8
block_size=64
clock=1000
forward_snoops=false
-hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.membus]
type=CoherentBus
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[system.terminal]
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 13:34:06
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:09:21
+gem5 started Jan 4 2013 21:39:46
+gem5 executing on u200540
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /gem5/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1854349611000 because m5_exit instruction encountered
sim_ticks 1854349611000 # Number of ticks simulated
final_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 135035 # Simulator instruction rate (inst/s)
-host_op_rate 135035 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4724741522 # Simulator tick rate (ticks/s)
-host_mem_usage 327760 # Number of bytes of host memory used
-host_seconds 392.48 # Real time elapsed on the host
+host_inst_rate 55480 # Simulator instruction rate (inst/s)
+host_op_rate 55480 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1941178876 # Simulator tick rate (ticks/s)
+host_mem_usage 331452 # Number of bytes of host memory used
+host_seconds 955.27 # Real time elapsed on the host
sim_insts 52998188 # Number of instructions simulated
sim_ops 52998188 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory
system.cpu.int_regfile_writes 40347354 # number of integer regfile writes
system.cpu.fp_regfile_reads 166024 # number of floating regfile reads
system.cpu.fp_regfile_writes 167429 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1993125 # number of misc regfile reads
+system.cpu.misc_regfile_reads 1994989 # number of misc regfile reads
system.cpu.misc_regfile_writes 947074 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
+mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
-midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=DerivO3CPU
-children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer
+children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
[system.cpu.checker]
type=O3Checker
-children=dtb itb tracer
+children=dtb isa itb tracer
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=Null
+isa=system.cpu.checker.isa
itb=system.cpu.checker.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.checker.tracer
updateOnError=true
sys=system
port=system.cpu.toL2Bus.slave[5]
+[system.cpu.checker.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.checker.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
clock=1000
forward_snoops=false
-hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.membus]
type=CoherentBus
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
-warn: 5946987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
-warn: 5954355500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 5963229500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 5999905500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 6015449500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 5947838000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
+warn: 5955222500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 5964126500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 6000836500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 6016396500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
warn: LCD dual screen mode not supported
-warn: 51801575500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: 51807341500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
-warn: 2473940227500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
-warn: 2487729164500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2488940395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
-warn: 2503139484500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
-warn: 2510001697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2510516362000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2516240346500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2516753495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
-warn: 2517315503000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2517316610000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
-warn: 2517867351500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
+warn: 2473965329500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
+warn: 2487749656500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2488961741500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
+warn: 2510016165000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2510533208500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2516263747000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
+warn: 2516773890500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
+warn: 2517336143500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
+warn: 2517337246000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
+warn: 2517887293500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 1 2012 15:18:10
-gem5 started Nov 2 2012 01:09:00
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 01:50:21
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2523500318000 because m5_exit instruction encountered
+Exiting @ tick 2523517846500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.523500 # Number of seconds simulated
-sim_ticks 2523500318000 # Number of ticks simulated
-final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.523518 # Number of seconds simulated
+sim_ticks 2523517846500 # Number of ticks simulated
+final_tick 2523517846500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 64209 # Simulator instruction rate (inst/s)
-host_op_rate 82591 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2673913922 # Simulator tick rate (ticks/s)
-host_mem_usage 441476 # Number of bytes of host memory used
-host_seconds 943.75 # Real time elapsed on the host
-sim_insts 60596849 # Number of instructions simulated
-sim_ops 77944928 # Number of ops (including micro ops) simulated
+host_inst_rate 18924 # Simulator instruction rate (inst/s)
+host_op_rate 24341 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 788054860 # Simulator tick rate (ticks/s)
+host_mem_usage 403628 # Number of bytes of host memory used
+host_seconds 3202.21 # Real time elapsed on the host
+sim_insts 60597240 # Number of instructions simulated
+sim_ops 77945362 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 798272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129432080 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 798272 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 798272 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799176 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12473 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096842 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813129 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47369455 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1040 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 316333 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3603459 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51290337 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 316333 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 316333 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499139 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1195186 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2694325 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1499139 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47369455 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1040 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096860 # Total number of read requests seen
-system.physmem.writeReqs 813144 # Total number of write requests seen
-system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966199040 # Total number of bytes read from memory
-system.physmem.bytesWritten 52041216 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis
+system.physmem.bw_total::cpu.inst 316333 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4798644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53984661 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096842 # Total number of read requests seen
+system.physmem.writeReqs 813129 # Total number of write requests seen
+system.physmem.cpureqs 218393 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966197888 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040256 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129432080 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799176 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 355 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943949 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943429 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943244 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943101 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943294 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943633 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943702 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::13 943617 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 943644 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943223 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50104 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50365 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 49969 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50029 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50827 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51125 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51357 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51177 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51291 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2523499110500 # Total gap between requests
+system.physmem.numWrRetry 1183132 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2523516727500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154616 # Categorize read packet sizes
+system.physmem.readPktSize::6 154598 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1907897 # categorize write packet sizes
+system.physmem.writePktSize::2 1937150 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59126 # categorize write packet sizes
+system.physmem.writePktSize::6 59111 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1042834 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 981659 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 938516 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 972890 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2730387 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2738053 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5375105 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 45255 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 30596 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 30326 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 30339 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 57584 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 37998 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 64788 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 17179 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2831 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 20 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2912 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3008 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3102 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3240 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3424 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3580 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 3721 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 3875 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32552 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32442 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32346 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32252 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32114 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 31930 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 31774 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31633 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31479 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests
-system.physmem.totBusLat 60386104000 # Total cycles spent in databus access
-system.physmem.totBankLat 210282128000 # Total cycles spent in bank access
-system.physmem.avgQLat 3116.78 # Average queueing delay per request
-system.physmem.avgBankLat 13929.17 # Average bank access latency per request
+system.physmem.totQLat 328143428340 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 404872878340 # Sum of mem lat for all requests
+system.physmem.totBusLat 60385948000 # Total cycles spent in databus access
+system.physmem.totBankLat 16343502000 # Total cycles spent in bank access
+system.physmem.avgQLat 21736.41 # Average queueing delay per request
+system.physmem.avgBankLat 1082.60 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 21045.95 # Average memory access latency
+system.physmem.avgMemAccLat 26819.01 # Average memory access latency
system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.52 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.13 # Average read queue length over time
-system.physmem.avgWrQLen 11.37 # Average write queue length over time
-system.physmem.readRowHits 15049962 # Number of row buffer hits during reads
-system.physmem.writeRowHits 784769 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes
-system.physmem.avgGap 158610.84 # Average gap between requests
+system.physmem.avgRdQLen 0.16 # Average read queue length over time
+system.physmem.avgWrQLen 11.85 # Average write queue length over time
+system.physmem.readRowHits 15052691 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784814 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 96.52 # Row buffer hit rate for writes
+system.physmem.avgGap 158612.28 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 15048842 # DTB read hits
-system.cpu.checker.dtb.read_misses 7308 # DTB read misses
-system.cpu.checker.dtb.write_hits 11294147 # DTB write hits
+system.cpu.checker.dtb.read_hits 15048937 # DTB read hits
+system.cpu.checker.dtb.read_misses 7310 # DTB read misses
+system.cpu.checker.dtb.write_hits 11294198 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15056150 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11296336 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 15056247 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11296387 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26342989 # DTB hits
-system.cpu.checker.dtb.misses 9497 # DTB misses
-system.cpu.checker.dtb.accesses 26352486 # DTB accesses
-system.cpu.checker.itb.inst_hits 61775601 # ITB inst hits
+system.cpu.checker.dtb.hits 26343135 # DTB hits
+system.cpu.checker.dtb.misses 9499 # DTB misses
+system.cpu.checker.dtb.accesses 26352634 # DTB accesses
+system.cpu.checker.itb.inst_hits 61775993 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61780072 # ITB inst accesses
-system.cpu.checker.itb.hits 61775601 # DTB hits
+system.cpu.checker.itb.inst_accesses 61780464 # ITB inst accesses
+system.cpu.checker.itb.hits 61775993 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61780072 # DTB accesses
-system.cpu.checker.numCycles 78235487 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61780464 # DTB accesses
+system.cpu.checker.numCycles 78235922 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51279526 # DTB read hits
-system.cpu.dtb.read_misses 73667 # DTB read misses
-system.cpu.dtb.write_hits 11753863 # DTB write hits
-system.cpu.dtb.write_misses 17234 # DTB write misses
+system.cpu.dtb.read_hits 51295505 # DTB read hits
+system.cpu.dtb.read_misses 73548 # DTB read misses
+system.cpu.dtb.write_hits 11769416 # DTB write hits
+system.cpu.dtb.write_misses 17308 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7683 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 7698 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2384 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 485 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51353193 # DTB read accesses
-system.cpu.dtb.write_accesses 11771097 # DTB write accesses
+system.cpu.dtb.perms_faults 1341 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51369053 # DTB read accesses
+system.cpu.dtb.write_accesses 11786724 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63033389 # DTB hits
-system.cpu.dtb.misses 90901 # DTB misses
-system.cpu.dtb.accesses 63124290 # DTB accesses
-system.cpu.itb.inst_hits 11603865 # ITB inst hits
-system.cpu.itb.inst_misses 11359 # ITB inst misses
+system.cpu.dtb.hits 63064921 # DTB hits
+system.cpu.dtb.misses 90856 # DTB misses
+system.cpu.dtb.accesses 63155777 # DTB accesses
+system.cpu.itb.inst_hits 11599470 # ITB inst hits
+system.cpu.itb.inst_misses 11387 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5142 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 5136 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2925 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 11615224 # ITB inst accesses
-system.cpu.itb.hits 11603865 # DTB hits
-system.cpu.itb.misses 11359 # DTB misses
-system.cpu.itb.accesses 11615224 # DTB accesses
-system.cpu.numCycles 470951029 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11610857 # ITB inst accesses
+system.cpu.itb.hits 11599470 # DTB hits
+system.cpu.itb.misses 11387 # DTB misses
+system.cpu.itb.accesses 11610857 # DTB accesses
+system.cpu.numCycles 470965317 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits
+system.cpu.BPredUnit.lookups 14487364 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11552940 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 711872 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 9478925 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7718754 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1413170 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 72913 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 29863213 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 90950612 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14487364 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9131924 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20302505 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4756883 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 122119 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 96718680 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 94285 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 205383 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11595815 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 694954 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5716 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150585846 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.753226 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.110122 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130298669 86.53% 86.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1345087 0.89% 87.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1687300 1.12% 88.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2309882 1.53% 90.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2120076 1.41% 91.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1117365 0.74% 92.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2592055 1.72% 93.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 766865 0.51% 94.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8348547 5.54% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150585846 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030761 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.193115 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31645642 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96356331 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18440866 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1036174 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3106833 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1972079 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 172496 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 107972230 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 569848 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3106833 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33398103 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36860235 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 53381295 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17668341 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6171039 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 103073979 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21323 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1016179 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4134721 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 29043 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 106845782 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 470577676 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 470486821 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90855 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 28114572 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 880520 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 786795 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12341610 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19847152 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13390380 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1964070 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2407797 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95636460 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2047932 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 123412976 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 169796 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 19147761 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 47762380 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 503425 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150585846 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.819552 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.531798 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106411056 70.66% 70.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13811108 9.17% 79.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7031286 4.67% 84.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5838601 3.88% 88.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12442775 8.26% 96.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2756258 1.83% 98.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1722165 1.14% 99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 442663 0.29% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 129934 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150585846 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 60097 0.68% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 3 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8367175 94.63% 95.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 414340 4.69% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57952199 46.96% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93294 0.08% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52612072 42.63% 89.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12389576 10.04% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued
-system.cpu.iq.rate 0.261997 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 123412976 # Type of FU issued
+system.cpu.iq.rate 0.262043 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8841615 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071643 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 406490722 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 116848589 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85936823 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 22982 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12524 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131878765 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12160 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 623393 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4131120 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30077 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1591861 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107803 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 700236 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3106833 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27952249 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 439003 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 97906020 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 205363 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19847152 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13390380 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1460347 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 117327 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3551 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30077 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 353051 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 272581 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 625632 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121337067 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51981447 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2075909 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 220747 # number of nop insts executed
-system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11527542 # Number of branches executed
-system.cpu.iew.exec_stores 12265452 # Number of stores executed
-system.cpu.iew.exec_rate 0.257499 # Inst execution rate
-system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47162688 # num instructions producing a value
-system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value
+system.cpu.iew.exec_nop 221628 # number of nop insts executed
+system.cpu.iew.exec_refs 64262784 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11537560 # Number of branches executed
+system.cpu.iew.exec_stores 12281337 # Number of stores executed
+system.cpu.iew.exec_rate 0.257635 # Inst execution rate
+system.cpu.iew.wb_sent 120375089 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85947111 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47183541 # num instructions producing a value
+system.cpu.iew.wb_consumers 88082196 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182491 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535676 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 18905107 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1544507 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 541940 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147479013 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.529538 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.516870 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 119767946 81.21% 81.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13521242 9.17% 90.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3932347 2.67% 93.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2139837 1.45% 94.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1947041 1.32% 95.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 981141 0.67% 96.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1580635 1.07% 97.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 757975 0.51% 98.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2850849 1.93% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60747230 # Number of instructions committed
-system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 147479013 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60747621 # Number of instructions committed
+system.cpu.commit.committedOps 78095743 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27514399 # Number of memory references committed
-system.cpu.commit.loads 15715935 # Number of loads committed
-system.cpu.commit.membars 413101 # Number of memory barriers committed
-system.cpu.commit.branches 10023041 # Number of branches committed
+system.cpu.commit.refs 27514551 # Number of memory references committed
+system.cpu.commit.loads 15716032 # Number of loads committed
+system.cpu.commit.membars 413105 # Number of memory barriers committed
+system.cpu.commit.branches 10023101 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69133795 # Number of committed integer instructions.
-system.cpu.commit.function_calls 995976 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 69134175 # Number of committed integer instructions.
+system.cpu.commit.function_calls 995982 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2850849 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 239806361 # The number of ROB reads
-system.cpu.rob.rob_writes 197293644 # The number of ROB writes
-system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60596849 # Number of Instructions Simulated
-system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated
-system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 549353820 # number of integer regfile reads
-system.cpu.int_regfile_writes 87979072 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8318 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2932 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912865 # number of misc regfile writes
-system.cpu.icache.replacements 980837 # number of replacements
-system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use
-system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor
+system.cpu.rob.rob_reads 239713879 # The number of ROB reads
+system.cpu.rob.rob_writes 197204165 # The number of ROB writes
+system.cpu.timesIdled 1775890 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320379471 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575982354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60597240 # Number of Instructions Simulated
+system.cpu.committedOps 77945362 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60597240 # Number of Instructions Simulated
+system.cpu.cpi 7.772059 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.772059 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.128666 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.128666 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 549724993 # number of integer regfile reads
+system.cpu.int_regfile_writes 88045460 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8276 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2926 # number of floating regfile writes
+system.cpu.misc_regfile_reads 30431218 # number of misc regfile reads
+system.cpu.misc_regfile_writes 912900 # number of misc regfile writes
+system.cpu.icache.replacements 981280 # number of replacements
+system.cpu.icache.tagsinuse 511.007424 # Cycle average of tags in use
+system.cpu.icache.total_refs 10533801 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 981792 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 10.729157 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6666221000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.007424 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits
-system.cpu.icache.overall_hits::total 10539450 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses
-system.cpu.icache.overall_misses::total 1060605 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11600055 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11600055 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11600055 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11600055 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091431 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.091431 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.091431 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.091431 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.091431 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.091431 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13163.622169 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_hits::cpu.inst 10533801 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 10533801 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 10533801 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 10533801 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 10533801 # number of overall hits
+system.cpu.icache.overall_hits::total 10533801 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1061888 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1061888 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1061888 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1061888 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1061888 # number of overall misses
+system.cpu.icache.overall_misses::total 1061888 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 13967491489 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 13967491489 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 13967491489 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 13967491489 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 13967491489 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 13967491489 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11595689 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11595689 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11595689 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11595689 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11595689 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11595689 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091576 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.091576 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.091576 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.091576 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.091576 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.091576 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13153.450730 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13153.450730 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13153.450730 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13153.450730 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 5396 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 1220 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 17.808581 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 610 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79214 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 79214 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 79214 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 79214 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 79214 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 79214 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981391 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 981391 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 981391 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 981391 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 981391 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 981391 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11354795991 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11354795991 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11354795991 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11354795991 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11354795991 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11354795991 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80057 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 80057 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 80057 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 80057 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 80057 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 80057 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981831 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 981831 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 981831 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 981831 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 981831 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 981831 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11353310491 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11353310491 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11353310491 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11353310491 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11353310491 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11353310491 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084602 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.084602 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.084602 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11570.104057 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11570.104057 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084672 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.084672 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.084672 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.406015 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.406015 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 643459 # number of replacements
-system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
-system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits
-system.cpu.dcache.overall_hits::total 21094791 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses
-system.cpu.dcache.overall_misses::total 3692032 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks
-system.cpu.dcache.writebacks::total 607749 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 64388 # number of replacements
-system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 129780 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 14.728779 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 2488431429000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 36915.014302 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 29.696477 # Average occupied blocks per requestor
+system.cpu.l2cache.replacements 64370 # number of replacements
+system.cpu.l2cache.tagsinuse 51358.666800 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1910788 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 129761 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 14.725441 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 2488452468500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 36927.008868 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker 28.274765 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 8183.272105 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6245.619403 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.563278 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000453 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 8177.411143 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 6225.971675 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.563461 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000431 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.124867 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.095301 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.783899 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79304 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10595 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 967765 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 387173 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1444837 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 607749 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 607749 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 112887 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 112887 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 79304 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 10595 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 967765 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 500060 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1557724 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 79304 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 10595 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 967765 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 500060 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1557724 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 43 # number of ReadReq misses
+system.cpu.l2cache.occ_percent::cpu.inst 0.124777 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.095001 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.783671 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 78622 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10599 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 968211 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 387222 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1444654 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 607832 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 607832 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 112968 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 112968 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 78622 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 10599 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 968211 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 500190 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1557622 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 78622 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 10599 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 968211 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 500190 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1557622 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 10735 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 23152 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 12367 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 10717 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133176 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133176 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 43 # number of demand (read+write) misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 12372 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 143911 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 156328 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 43 # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst 12367 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143903 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 12372 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 143911 # number of overall misses
-system.cpu.l2cache.overall_misses::total 156328 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2913500 # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst 12367 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143903 # number of overall misses
+system.cpu.l2cache.overall_misses::total 156313 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2982500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 660133000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590903498 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1254067998 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 477000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 477000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6777740498 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6777740498 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2913500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 653684500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590050498 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1246835498 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 431500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 431500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6675201498 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6675201498 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2982500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 660133000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7368643996 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 8031808496 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2913500 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 653684500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7265251996 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 7922036996 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2982500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 660133000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7368643996 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 8031808496 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 79347 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10597 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 980137 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 397908 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1467989 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 607749 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 607749 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 246063 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 246063 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 79347 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 10597 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 980137 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 643971 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1714052 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 79347 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 10597 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 980137 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 643971 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1714052 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000542 # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_miss_latency::cpu.inst 653684500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7265251996 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 7922036996 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 78663 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10601 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 980578 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 397939 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1467781 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 607832 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 607832 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 246154 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 246154 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 78663 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 10601 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 980578 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 644093 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1713935 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 78663 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 10601 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 980578 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 644093 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1713935 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000521 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012623 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.015771 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985478 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985478 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541227 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.541227 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000542 # miss rate for demand accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012612 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026931 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.015756 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986158 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986158 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541068 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.541068 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000521 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012623 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.223474 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.091204 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000542 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012612 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.223420 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.091201 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000521 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012623 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.223474 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.091204 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 67755.813953 # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012612 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.223420 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.091201 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72743.902439 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53357.015842 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55044.573638 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 54166.724171 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.468129 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.468129 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50893.107602 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50893.107602 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52857.160184 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55057.431931 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 53912.548017 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 147.723382 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 147.723382 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50119.393164 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50119.393164 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72743.902439 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51377.926513 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52857.160184 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50487.147565 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 50680.602356 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72743.902439 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51377.926513 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52857.160184 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50487.147565 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 50680.602356 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 59126 # number of writebacks
-system.cpu.l2cache.writebacks::total 59126 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 59111 # number of writebacks
+system.cpu.l2cache.writebacks::total 59111 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 43 # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12360 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10675 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 23080 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2918 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12355 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 23054 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133176 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 133176 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 43 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 12360 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 143851 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 156256 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 43 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 12355 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143842 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 156240 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 12360 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 143851 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 156256 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2368082 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12355 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143842 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 156240 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2461077 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93002 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 503399135 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 452451368 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 958311587 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29209900 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29209900 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 497040130 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 451732824 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 951327033 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5125972608 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5125972608 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2368082 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5024401862 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5024401862 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2461077 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93002 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503399135 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578423976 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 6084284195 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2368082 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 497040130 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5476134686 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 5975728895 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2461077 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93002 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503399135 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578423976 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 6084284195 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 497040130 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5476134686 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 5975728895 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963877530 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166968222685 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18087556027 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18087556027 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167008598530 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167012943685 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18318853408 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18318853408 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185051433557 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185055778712 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185327451938 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185331797093 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026778 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015707 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986158 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986158 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541068 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541068 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.091162 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.091159 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.091162 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.091159 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40728.085356 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42384.203091 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41521.299263 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.246744 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.246744 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40229.876973 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42392.344595 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41265.161490 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38490.213011 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38490.213011 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37724.699758 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37724.699758 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 643581 # number of replacements
+system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
+system.cpu.dcache.total_refs 21676734 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 644093 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 33.654665 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 13816029 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13816029 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7289413 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7289413 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 282441 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 282441 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 285740 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 285740 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21105442 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21105442 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21105442 # number of overall hits
+system.cpu.dcache.overall_hits::total 21105442 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 731834 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 731834 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2961255 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2961255 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13603 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13603 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3693089 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3693089 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3693089 # number of overall misses
+system.cpu.dcache.overall_misses::total 3693089 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 9564740000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 9564740000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 104026861731 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 104026861731 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180604500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 180604500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 244000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 244000 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 113591601731 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 113591601731 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 113591601731 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 113591601731 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14547863 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14547863 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10250668 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10250668 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296044 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 296044 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 285756 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 285756 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24798531 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24798531 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24798531 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24798531 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050305 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050305 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288884 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.288884 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045949 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045949 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.148924 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.148924 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.148924 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.148924 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.548559 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.548559 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35129.315689 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35129.315689 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13276.813938 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13276.813938 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15250 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15250 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30757.883639 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30757.883639 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 32046 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 14482 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.377752 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 57.697211 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks
+system.cpu.dcache.writebacks::total 607832 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345983 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 345983 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712226 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2712226 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1428 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1428 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3058209 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3058209 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3058209 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3058209 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385851 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385851 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249029 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249029 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634880 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634880 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634880 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634880 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768256000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768256000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8126256417 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8126256417 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140756500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140756500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 212000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 212000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12894512417 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12894512417 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12894512417 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12894512417 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182401837500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182401837500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28201633550 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28201633550 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210603471050 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 210603471050 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041126 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041126 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025602 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025602 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12357.765044 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12357.765044 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32631.767453 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32631.767453 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11561.108830 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11561.108830 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13250 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13250 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1148123553642 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1148123553642 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88023 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
+mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
-midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb tracer
+children=dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
[system.cpu0.interrupts]
type=ArmInterrupts
+[system.cpu0.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu0.itb]
type=ArmTLB
children=walker
[system.cpu1]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb tracer
+children=dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
[system.cpu1.interrupts]
type=ArmInterrupts
+[system.cpu1.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu1.itb]
type=ArmTLB
children=walker
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
clock=1000
forward_snoops=false
-hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 21:14:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 02:00:26
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2593146078000 because m5_exit instruction encountered
+Exiting @ tick 2603185215000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.593146 # Number of seconds simulated
-sim_ticks 2593146078000 # Number of ticks simulated
-final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.603185 # Number of seconds simulated
+sim_ticks 2603185215000 # Number of ticks simulated
+final_tick 2603185215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 77303 # Simulator instruction rate (inst/s)
-host_op_rate 99505 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3178225665 # Simulator tick rate (ticks/s)
-host_mem_usage 449664 # Number of bytes of host memory used
-host_seconds 815.91 # Real time elapsed on the host
-sim_insts 63072130 # Number of instructions simulated
-sim_ops 81187111 # Number of ops (including micro ops) simulated
+host_inst_rate 24146 # Simulator instruction rate (inst/s)
+host_op_rate 31077 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 996702828 # Simulator tick rate (ticks/s)
+host_mem_usage 410224 # Number of bytes of host memory used
+host_seconds 2611.80 # Real time elapsed on the host
+sim_insts 63063952 # Number of instructions simulated
+sim_ops 81166306 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 395328 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4376500 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 426752 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5261232 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131572388 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 395328 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 426752 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 822080 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4282048 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 396288 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4383412 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5252400 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131570212 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 396288 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 821824 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4280832 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7311184 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7309968 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6177 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 68455 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 82233 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15302381 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66907 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6192 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 68563 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 82095 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15302347 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66888 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 824191 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46704090 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 346 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 152451 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1687718 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 370 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 164569 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 2028899 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50738518 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 152451 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 164569 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 317020 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1651295 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6556 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 1161576 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2819426 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1651295 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46704090 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 152451 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1694274 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 370 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 164569 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 3190475 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53557944 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15302381 # Total number of read requests seen
-system.physmem.writeReqs 824191 # Total number of write requests seen
-system.physmem.cpureqs 284713 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 979352384 # Total number of bytes read from memory
-system.physmem.bytesWritten 52748224 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 131572388 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7311184 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 335 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 14131 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 956528 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 956655 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 956404 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 956499 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 956473 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 956086 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 956080 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 957009 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 956354 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 956393 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 956606 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 956350 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 956542 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 956247 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 955941 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50875 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 51001 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50801 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50933 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51869 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51569 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51383 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51546 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 52151 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51788 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51664 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51769 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51735 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51864 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51697 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51546 # Track writes on a per bank basis
+system.physmem.num_writes::total 824172 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 46523977 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 152232 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1683865 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 163467 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2017682 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50542010 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 152232 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 163467 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315699 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1644459 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 1157096 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2808086 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1644459 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 46523977 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 152232 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1690395 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 163467 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 3174778 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53350096 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15302347 # Total number of read requests seen
+system.physmem.writeReqs 824172 # Total number of write requests seen
+system.physmem.cpureqs 284728 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 979350208 # Total number of bytes read from memory
+system.physmem.bytesWritten 52747008 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 131570212 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7309968 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 346 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 14078 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 956479 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 956691 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 956370 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 956557 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 956475 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 956110 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 955970 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 956102 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 956952 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 956364 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 956322 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 956651 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 956317 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 956502 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 956203 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 955936 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 51032 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50766 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50996 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 51588 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 51566 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 52101 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51797 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51588 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51821 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51672 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51523 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1150487 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2593144762500 # Total gap between requests
+system.physmem.numWrRetry 1182222 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2603183939000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 105 # Categorize read packet sizes
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 163460 # Categorize read packet sizes
+system.physmem.readPktSize::6 163426 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1907771 # categorize write packet sizes
+system.physmem.writePktSize::2 1939506 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 66907 # categorize write packet sizes
+system.physmem.writePktSize::6 66888 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 14131 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 14078 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 15151641 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 94331 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 8809 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3486 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2848 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2557 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2313 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1993 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1407 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1368 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1369 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 6472 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 9621 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 13063 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 592 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 23 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1062295 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 996413 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 951405 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 986255 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2765519 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2772335 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5446641 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 44668 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 31245 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 30881 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 30868 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 58473 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 38578 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 65793 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 17450 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 3001 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 140 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 33 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3183 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3385 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3534 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3673 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4027 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4248 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4407 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4586 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3151 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3270 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3380 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3476 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3611 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3812 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4018 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4199 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4366 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32652 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32450 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32301 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32162 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 31587 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31428 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32683 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32564 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32454 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32358 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32223 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 32022 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 31816 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31635 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31468 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 47868619345 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 322210199345 # Sum of mem lat for all requests
-system.physmem.totBusLat 61208184000 # Total cycles spent in databus access
-system.physmem.totBankLat 213133396000 # Total cycles spent in bank access
-system.physmem.avgQLat 3128.25 # Average queueing delay per request
-system.physmem.avgBankLat 13928.42 # Average bank access latency per request
+system.physmem.totQLat 332610890470 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 410507230470 # Sum of mem lat for all requests
+system.physmem.totBusLat 61208004000 # Total cycles spent in databus access
+system.physmem.totBankLat 16688336000 # Total cycles spent in bank access
+system.physmem.avgQLat 21736.43 # Average queueing delay per request
+system.physmem.avgBankLat 1090.60 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 21056.67 # Average memory access latency
-system.physmem.avgRdBW 377.67 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.34 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 2.82 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 26827.03 # Average memory access latency
+system.physmem.avgRdBW 376.21 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 2.49 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.12 # Average read queue length over time
-system.physmem.avgWrQLen 10.88 # Average write queue length over time
-system.physmem.readRowHits 15253448 # Number of row buffer hits during reads
-system.physmem.writeRowHits 789566 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads
+system.physmem.busUtil 2.48 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.16 # Average read queue length over time
+system.physmem.avgWrQLen 12.97 # Average write queue length over time
+system.physmem.readRowHits 15255805 # Number of row buffer hits during reads
+system.physmem.writeRowHits 789541 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes
-system.physmem.avgGap 160799.50 # Average gap between requests
+system.physmem.avgGap 161422.56 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 173 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 173 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 173 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 73184 # number of replacements
-system.l2c.tagsinuse 53096.266008 # Cycle average of tags in use
-system.l2c.total_refs 1906265 # Total number of references to valid blocks.
-system.l2c.sampled_refs 138351 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.778469 # Average number of references to valid blocks.
+system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 73139 # number of replacements
+system.l2c.tagsinuse 53098.784053 # Cycle average of tags in use
+system.l2c.total_refs 1903330 # Total number of references to valid blocks.
+system.l2c.sampled_refs 138315 # Sample count of references to valid blocks.
+system.l2c.avg_refs 13.760836 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 37733.790025 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 7.219153 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4206.047810 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 2960.317078 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 11.178862 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.itb.walker 0.966447 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 4058.933416 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 4117.812877 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.575772 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000110 # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks 37803.409303 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker 5.317240 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker 0.004373 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4191.158517 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 2951.048787 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 13.024682 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 4037.185847 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 4097.635305 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.576834 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker 0.000081 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.064179 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.045171 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker 0.000171 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.061934 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.062833 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.810185 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 33579 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 4963 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 393016 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 165084 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 53008 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 6038 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 608232 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 201468 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1465388 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 583960 # number of Writeback hits
-system.l2c.Writeback_hits::total 583960 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 1107 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 848 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1955 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits
+system.l2c.occ_percent::cpu0.inst 0.063952 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.045029 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker 0.000199 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.061603 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.062525 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.810223 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker 33629 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 4816 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 393434 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 165508 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 53340 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 6018 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 607751 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 201341 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1465837 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 582635 # number of Writeback hits
+system.l2c.Writeback_hits::total 582635 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 1118 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 732 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 1850 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 368 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 47823 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 59123 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 106946 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 33579 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 4963 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 393016 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 212907 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 53008 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 6038 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 608232 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 260591 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1572334 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 33579 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 4963 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 393016 # number of overall hits
-system.l2c.overall_hits::cpu0.data 212907 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 53008 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 6038 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 608232 # number of overall hits
-system.l2c.overall_hits::cpu1.data 260591 # number of overall hits
-system.l2c.overall_hits::total 1572334 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 6056 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 6345 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 6633 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 6362 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 25428 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 5684 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 4404 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 10088 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 773 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 585 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1358 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 63519 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 77106 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 140625 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 6056 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 69864 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 6633 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 83468 # number of demand (read+write) misses
-system.l2c.demand_misses::total 166053 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 6056 # number of overall misses
-system.l2c.overall_misses::cpu0.data 69864 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 6633 # number of overall misses
-system.l2c.overall_misses::cpu1.data 83468 # number of overall misses
-system.l2c.overall_misses::total 166053 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1175500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst 320358500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 344253498 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1038500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker 122500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 371653000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 369594500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1408313998 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 9084989 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 12192500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 21277489 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2932000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 3523000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 3155374488 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 4272368491 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7427742979 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 1175500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 320358500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 3499627986 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 1038500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker 122500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 371653000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 4641962991 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 8836056977 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 1175500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 320358500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 3499627986 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 1038500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker 122500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 371653000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 4641962991 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 8836056977 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 33593 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 4965 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 399072 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 171429 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 53023 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 6039 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 614865 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 207830 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1490816 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 583960 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 583960 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 6791 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 5252 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 12043 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 982 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 744 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1726 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 111342 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 136229 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 247571 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 33593 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 4965 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 399072 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 282771 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 53023 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 6039 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 614865 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 344059 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1738387 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 33593 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 4965 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 399072 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 282771 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 53023 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 6039 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 614865 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 344059 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1738387 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000417 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000403 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.015175 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.037012 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000283 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000166 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.010788 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.030612 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.017056 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.836990 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.838538 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.837665 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787169 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.786290 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.786790 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.570486 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.566003 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.568019 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000417 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000403 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.015175 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.247069 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000283 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker 0.000166 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.010788 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.242598 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.095521 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000417 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000403 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.015175 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.247069 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000283 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker 0.000166 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.010788 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.242598 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.095521 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83964.285714 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52899.356011 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 54255.870449 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69233.333333 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 122500 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 56030.906076 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 58094.074191 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 55384.379346 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1598.344300 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2768.505904 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 2109.188045 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 764.553687 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5011.965812 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 2594.256259 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49676.073112 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55409.027715 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52819.505628 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83964.285714 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52899.356011 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 50092.007128 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69233.333333 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 122500 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 56030.906076 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 55613.684178 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 53212.269438 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83964.285714 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52899.356011 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 50092.007128 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69233.333333 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 122500 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 56030.906076 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 55613.684178 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53212.269438 # average overall miss latency
+system.l2c.SCUpgradeReq_hits::total 371 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 47631 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 59120 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 106751 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 33629 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 4816 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 393434 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 213139 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 53340 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 6018 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 607751 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 260461 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1572588 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 33629 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 4816 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 393434 # number of overall hits
+system.l2c.overall_hits::cpu0.data 213139 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 53340 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 6018 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 607751 # number of overall hits
+system.l2c.overall_hits::cpu1.data 260461 # number of overall hits
+system.l2c.overall_hits::total 1572588 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 6072 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 6358 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 6613 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 6308 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 25383 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 5670 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 4365 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 10035 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 766 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 584 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1350 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 63604 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 77038 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 140642 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 6072 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 69962 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 6613 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 83346 # number of demand (read+write) misses
+system.l2c.demand_misses::total 166025 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 6072 # number of overall misses
+system.l2c.overall_misses::cpu0.data 69962 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 6613 # number of overall misses
+system.l2c.overall_misses::cpu1.data 83346 # number of overall misses
+system.l2c.overall_misses::total 166025 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 932000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker 187000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 315446500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 349611000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1169000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 361021000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 360243500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1388610000 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 8984984 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 11919000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 20903984 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 502500 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3000500 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 3503000 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 3132047991 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 4232582992 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 7364630983 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker 932000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker 187000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 315446500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 3481658991 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 1169000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 361021000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 4592826492 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 8753240983 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker 932000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker 187000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 315446500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 3481658991 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 1169000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 361021000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 4592826492 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 8753240983 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 33641 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 4819 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 399506 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 171866 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 53357 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 6018 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 614364 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 207649 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1491220 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 582635 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 582635 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 6788 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 5097 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 11885 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 978 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 743 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1721 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 111235 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 136158 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 247393 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 33641 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 4819 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 399506 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 283101 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 53357 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 6018 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 614364 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 343807 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1738613 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 33641 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 4819 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 399506 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 283101 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 53357 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 6018 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 614364 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 343807 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1738613 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000357 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000623 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.015199 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.036994 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000319 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.010764 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.030378 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.017022 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.835298 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.856386 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.844342 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783231 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.786003 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.784428 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.571798 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.565799 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.568496 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000357 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000623 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.015199 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.247127 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000319 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.010764 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.242421 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.095493 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000357 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000623 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.015199 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.247127 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000319 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.010764 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.242421 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.095493 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 77666.666667 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 62333.333333 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51951.004611 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 54987.574709 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68764.705882 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54592.620596 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 57108.988586 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 54706.299492 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1584.653263 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2730.584192 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 2083.107524 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 656.005222 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5137.842466 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 2594.814815 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49242.940554 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54941.496301 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52364.378941 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 77666.666667 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 62333.333333 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 51951.004611 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 49765.000872 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68764.705882 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 54592.620596 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 55105.541862 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52722.427243 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 77666.666667 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 62333.333333 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 51951.004611 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 49765.000872 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68764.705882 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 54592.620596 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 55105.541862 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52722.427243 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 66907 # number of writebacks
-system.l2c.writebacks::total 66907 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst 6053 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 6306 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 6625 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 6337 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 25353 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 5684 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 4404 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 10088 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 773 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 585 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 1358 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 63519 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 77106 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 140625 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 6053 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 69825 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 6625 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 83443 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 165978 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 6053 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 69825 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 6625 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 83443 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 165978 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 998025 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93002 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 243809691 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 262215347 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 849526 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 109502 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 287575375 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 287912849 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1083563317 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57255976 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44756275 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 102012251 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7762758 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5877575 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 13640333 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2369346199 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3313598990 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5682945189 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 998025 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93002 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 243809691 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 2631561546 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 849526 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 109502 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 287575375 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 3601511839 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 6766508506 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 998025 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 243809691 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 2631561546 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 849526 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 109502 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 287575375 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 3601511839 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 6766508506 # number of overall MSHR miss cycles
+system.l2c.writebacks::writebacks 66888 # number of writebacks
+system.l2c.writebacks::total 66888 # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 12 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst 6068 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 6320 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 6606 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 6284 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 25310 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 5670 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 4365 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 10035 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 766 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 584 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 1350 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 63604 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 77038 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 140642 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 12 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 6068 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 69924 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 17 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 6606 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 83322 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 165952 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 12 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 6068 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 69924 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 6606 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 83322 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 165952 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 779021 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 149004 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 238620719 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 267423854 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 952034 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 277227882 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 279338276 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1064490790 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57153439 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44270770 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 101424209 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7709241 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5848580 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 13557821 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2345272692 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3275122771 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5620395463 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 779021 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 149004 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 238620719 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 2612696546 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 952034 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 277227882 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 3554461047 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 6684886253 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 779021 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 149004 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 238620719 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 2612696546 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 952034 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 277227882 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 3554461047 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 6684886253 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4558163 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12330302064 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1815064 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154912119500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167248794791 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1062521236 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17116054868 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 18178576104 # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12330828558 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1893563 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154946270000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167283550284 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1062643238 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17370101500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 18432744738 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4558163 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13392823300 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1815064 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172028174368 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 185427370895 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036785 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030491 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.017006 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.836990 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.838538 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.837665 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787169 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786290 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.786790 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570486 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.566003 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.568019 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.246931 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.242525 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.095478 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.246931 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.242525 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.095478 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41581.881859 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45433.619852 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 42739.057192 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.183673 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10162.641916 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.237411 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.377749 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.136752 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10044.427835 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37301.377525 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42974.593287 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40412.054677 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13393471796 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1893563 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172316371500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 185716295022 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036773 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030263 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.016973 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.835298 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.856386 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.844342 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783231 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786003 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784428 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.571798 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565799 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.568496 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.242351 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.095451 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.242351 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.095451 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42313.900949 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 44452.303628 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 42058.111023 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10079.971605 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10142.215349 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10107.046238 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10064.283290 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.691781 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.830370 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36873.037733 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42513.081479 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 39962.425613 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37364.803873 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42659.334233 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40282.046935 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37364.803873 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42659.334233 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40282.046935 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 9014303 # DTB read hits
-system.cpu0.dtb.read_misses 34965 # DTB read misses
-system.cpu0.dtb.write_hits 5253714 # DTB write hits
-system.cpu0.dtb.write_misses 6399 # DTB write misses
+system.cpu0.dtb.read_hits 9024363 # DTB read hits
+system.cpu0.dtb.read_misses 35062 # DTB read misses
+system.cpu0.dtb.write_hits 5257895 # DTB write hits
+system.cpu0.dtb.write_misses 6477 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2155 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1094 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 321 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 2160 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 9049268 # DTB read accesses
-system.cpu0.dtb.write_accesses 5260113 # DTB write accesses
+system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 9059425 # DTB read accesses
+system.cpu0.dtb.write_accesses 5264372 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14268017 # DTB hits
-system.cpu0.dtb.misses 41364 # DTB misses
-system.cpu0.dtb.accesses 14309381 # DTB accesses
-system.cpu0.itb.inst_hits 4294311 # ITB inst hits
-system.cpu0.itb.inst_misses 5261 # ITB inst misses
+system.cpu0.dtb.hits 14282258 # DTB hits
+system.cpu0.dtb.misses 41539 # DTB misses
+system.cpu0.dtb.accesses 14323797 # DTB accesses
+system.cpu0.itb.inst_hits 4307156 # ITB inst hits
+system.cpu0.itb.inst_misses 5205 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1385 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1360 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1364 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4299572 # ITB inst accesses
-system.cpu0.itb.hits 4294311 # DTB hits
-system.cpu0.itb.misses 5261 # DTB misses
-system.cpu0.itb.accesses 4299572 # DTB accesses
-system.cpu0.numCycles 69013505 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4312361 # ITB inst accesses
+system.cpu0.itb.hits 4307156 # DTB hits
+system.cpu0.itb.misses 5205 # DTB misses
+system.cpu0.itb.accesses 4312361 # DTB accesses
+system.cpu0.numCycles 69075583 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 6123831 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 4675790 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 298271 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 3798227 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 2989296 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 6134621 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 4681383 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 299233 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 3810859 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 2992358 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 685728 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 28375 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 11998527 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 32710943 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6123831 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3675024 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7667644 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1480146 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 66638 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 21758305 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 5862 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 53793 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 221 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4292744 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 155269 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2401 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 42704543 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.988603 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.369673 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 688987 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 28743 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 12013253 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 32740564 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6134621 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3681345 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7677557 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1482239 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 64559 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 21828282 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 5891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 53864 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 90312 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 236 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4305560 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 159104 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2370 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 42798314 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.987162 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.368020 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 35044149 82.06% 82.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 606065 1.42% 83.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 793528 1.86% 85.34% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 689319 1.61% 86.95% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 781424 1.83% 88.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 567584 1.33% 90.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 711320 1.67% 91.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 364019 0.85% 92.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3147135 7.37% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 35128127 82.08% 82.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 610328 1.43% 83.50% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 795353 1.86% 85.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 689183 1.61% 86.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 781372 1.83% 88.80% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 569733 1.33% 90.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 711695 1.66% 91.79% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 364225 0.85% 92.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3148298 7.36% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 42704543 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.088734 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.473979 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12497333 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 21726841 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6896095 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 584636 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 999638 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 951812 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 64726 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 40836330 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 213865 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 999638 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 13071648 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5812993 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 13759259 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6855374 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2205631 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 39711904 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 2173 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 427558 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1242268 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 68 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 40116309 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 179435830 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 179401258 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34572 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 31681024 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8435284 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 457771 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 414521 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5443309 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7819363 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5820332 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1146243 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1242216 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 37575405 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 946067 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 37951575 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 82274 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6366228 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13456450 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 257591 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 42704543 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.888701 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.500077 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 42798314 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.088810 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.473982 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12517044 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 21792466 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6901256 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 586970 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1000578 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 954803 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 64851 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 40861344 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 213562 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1000578 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 13092600 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5813788 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13806762 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6861684 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2222902 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 39740402 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 2257 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 444272 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1240471 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 77 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 40148585 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 179562690 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 179528337 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 34353 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 31678708 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8469876 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 458191 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 414927 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5465728 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7827563 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5820560 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1149873 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1213359 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 37598856 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 946637 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37967135 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 82667 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6387129 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 13438267 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 258027 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 42798314 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.887118 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.498670 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 27159670 63.60% 63.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 6000291 14.05% 77.65% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3232720 7.57% 85.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2489147 5.83% 91.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2132528 4.99% 96.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 950123 2.22% 98.27% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 497063 1.16% 99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 188710 0.44% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 54291 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 27228481 63.62% 63.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 6024200 14.08% 77.70% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3238541 7.57% 85.26% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2496476 5.83% 91.10% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2116280 4.94% 96.04% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 952748 2.23% 98.27% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 498209 1.16% 99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 188721 0.44% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 54658 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 42704543 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 42798314 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 24659 2.31% 2.31% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 467 0.04% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 838061 78.41% 80.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 205631 19.24% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 25719 2.40% 2.40% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 458 0.04% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 838558 78.31% 80.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 206136 19.25% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22793341 60.06% 60.20% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 48224 0.13% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22801553 60.06% 60.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 48143 0.13% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9480747 24.98% 85.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5576214 14.69% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9487186 24.99% 85.31% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5577397 14.69% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 37951575 # Type of FU issued
-system.cpu0.iq.rate 0.549915 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1068818 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028163 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 119791525 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 44895833 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 35071497 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8304 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3884 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 38963714 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4335 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 318123 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37967135 # Type of FU issued
+system.cpu0.iq.rate 0.549646 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1070871 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.028205 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 119919123 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 44940813 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 35094596 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 8245 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4688 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 3877 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 38981568 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 4289 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 319568 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1396327 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2506 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13403 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 544501 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1406645 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2495 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13426 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 546497 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2149359 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5385 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2149373 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5419 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 999638 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4184428 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 103741 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 38639126 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 85944 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7819363 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5820332 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 614711 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 41414 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 3290 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13403 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 151339 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 119425 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 270764 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 37563861 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9331167 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 387714 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1000578 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 4177293 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 102909 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 38663154 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 84882 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7827563 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5820560 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 615194 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 41110 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 3269 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13426 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 151880 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 119782 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 271662 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 37584827 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9341263 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 382308 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 117654 # number of nop insts executed
-system.cpu0.iew.exec_refs 14857557 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4958494 # Number of branches executed
-system.cpu0.iew.exec_stores 5526390 # Number of stores executed
-system.cpu0.iew.exec_rate 0.544297 # Inst execution rate
-system.cpu0.iew.wb_sent 37365472 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 35075381 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18655901 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35819655 # num instructions consuming a value
+system.cpu0.iew.exec_nop 117661 # number of nop insts executed
+system.cpu0.iew.exec_refs 14871823 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4965899 # Number of branches executed
+system.cpu0.iew.exec_stores 5530560 # Number of stores executed
+system.cpu0.iew.exec_rate 0.544112 # Inst execution rate
+system.cpu0.iew.wb_sent 37390069 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 35098473 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18662098 # num instructions producing a value
+system.cpu0.iew.wb_consumers 35837598 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.508239 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.520829 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.508117 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.520741 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6205381 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 688476 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 234604 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 41741265 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.766601 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.727877 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6206788 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 688610 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 235451 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 41797736 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.765444 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.723461 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 29720457 71.20% 71.20% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5963123 14.29% 85.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1948324 4.67% 90.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1002440 2.40% 92.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 789371 1.89% 94.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 520489 1.25% 95.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 393953 0.94% 96.64% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 216687 0.52% 97.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1186421 2.84% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 29752237 71.18% 71.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5970878 14.29% 85.47% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1965315 4.70% 90.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 999760 2.39% 92.56% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 803961 1.92% 94.48% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 518760 1.24% 95.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 395530 0.95% 96.67% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 220150 0.53% 97.20% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1171145 2.80% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 41741265 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 24264310 # Number of instructions committed
-system.cpu0.commit.committedOps 31998915 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 41797736 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 24265529 # Number of instructions committed
+system.cpu0.commit.committedOps 31993822 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 11698867 # Number of memory references committed
-system.cpu0.commit.loads 6423036 # Number of loads committed
-system.cpu0.commit.membars 234373 # Number of memory barriers committed
-system.cpu0.commit.branches 4346960 # Number of branches committed
+system.cpu0.commit.refs 11694981 # Number of memory references committed
+system.cpu0.commit.loads 6420918 # Number of loads committed
+system.cpu0.commit.membars 234476 # Number of memory barriers committed
+system.cpu0.commit.branches 4347395 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 28266871 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 499893 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1186421 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 28261624 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 500034 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1171145 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 77875275 # The number of ROB reads
-system.cpu0.rob.rob_writes 77410136 # The number of ROB writes
-system.cpu0.timesIdled 364830 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 26308962 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5117234895 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 24183568 # Number of Instructions Simulated
-system.cpu0.committedOps 31918173 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 24183568 # Number of Instructions Simulated
-system.cpu0.cpi 2.853735 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.853735 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.350418 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.350418 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 175323075 # number of integer regfile reads
-system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 906 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 13342715 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes
-system.cpu0.icache.replacements 399233 # number of replacements
-system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use
-system.cpu0.icache.total_refs 3861943 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 399745 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 9.661016 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 6802423000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.592262 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.999204 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.999204 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 3861943 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 3861943 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 3861943 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 3861943 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 3861943 # number of overall hits
-system.cpu0.icache.overall_hits::total 3861943 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 430668 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 430668 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 430668 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 430668 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 430668 # number of overall misses
-system.cpu0.icache.overall_misses::total 430668 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5857521993 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5857521993 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 5857521993 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5857521993 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 5857521993 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5857521993 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 4292611 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 4292611 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 4292611 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 4292611 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 4292611 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 4292611 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100328 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.100328 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100328 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.100328 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100328 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.100328 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13601.015151 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13601.015151 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13601.015151 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13601.015151 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 2687 # number of cycles access was blocked
+system.cpu0.rob.rob_reads 77942939 # The number of ROB reads
+system.cpu0.rob.rob_writes 77403720 # The number of ROB writes
+system.cpu0.timesIdled 364282 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 26277269 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 5137251054 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 24184787 # Number of Instructions Simulated
+system.cpu0.committedOps 31913080 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 24184787 # Number of Instructions Simulated
+system.cpu0.cpi 2.856158 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.856158 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.350121 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.350121 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 175453235 # number of integer regfile reads
+system.cpu0.int_regfile_writes 34873256 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 3235 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 908 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 13424511 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 527689 # number of misc regfile writes
+system.cpu0.icache.replacements 399628 # number of replacements
+system.cpu0.icache.tagsinuse 511.593033 # Cycle average of tags in use
+system.cpu0.icache.total_refs 3873847 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 400140 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 9.681229 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 6818802000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 511.593033 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.999205 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.999205 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 3873847 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 3873847 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 3873847 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 3873847 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 3873847 # number of overall hits
+system.cpu0.icache.overall_hits::total 3873847 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 431582 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 431582 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 431582 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 431582 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 431582 # number of overall misses
+system.cpu0.icache.overall_misses::total 431582 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5855735994 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5855735994 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 5855735994 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5855735994 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5855735994 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5855735994 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 4305429 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 4305429 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 4305429 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 4305429 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 4305429 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 4305429 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100241 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.100241 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100241 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.100241 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100241 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.100241 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13568.072797 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13568.072797 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13568.072797 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13568.072797 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13568.072797 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13568.072797 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 2448 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 157 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 142 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.114650 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.239437 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30901 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 30901 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 30901 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 30901 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 30901 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 30901 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399767 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 399767 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 399767 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 399767 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 399767 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 399767 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4790784994 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4790784994 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4790784994 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4790784994 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4790784994 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4790784994 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31419 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 31419 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 31419 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 31419 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 31419 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 31419 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400163 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 400163 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 400163 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 400163 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 400163 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 400163 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4791432494 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 4791432494 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4791432494 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 4791432494 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4791432494 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 4791432494 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093129 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.093129 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.093129 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11983.943132 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092944 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.092944 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.092944 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11973.701951 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11973.701951 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11973.701951 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 274937 # number of replacements
-system.cpu0.dcache.tagsinuse 481.181813 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 9516256 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 275449 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 34.548160 # Average number of references to valid blocks.
+system.cpu0.dcache.replacements 274722 # number of replacements
+system.cpu0.dcache.tagsinuse 476.919366 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 9525271 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 275234 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 34.607901 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 481.181813 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.939808 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.939808 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 5887183 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 5887183 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3238358 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 3238358 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173666 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 173666 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171542 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 171542 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 9125541 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 9125541 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 9125541 # number of overall hits
-system.cpu0.dcache.overall_hits::total 9125541 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 390766 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 390766 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1582021 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1582021 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8872 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 8872 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7743 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 7743 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1972787 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1972787 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1972787 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1972787 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5377265000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 5377265000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60881411847 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 60881411847 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88222500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 88222500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50475500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 50475500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 66258676847 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 66258676847 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 66258676847 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 66258676847 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 6277949 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 6277949 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820379 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 4820379 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182538 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 182538 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179285 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 179285 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 11098328 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 11098328 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 11098328 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 11098328 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062244 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.062244 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328194 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.328194 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048604 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048604 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043188 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043188 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.177755 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.177755 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177755 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.177755 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13760.831290 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13760.831290 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38483.314600 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38483.314600 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9943.924707 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9943.924707 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6518.855741 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6518.855741 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33586.330834 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33586.330834 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 8283 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 3369 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 596 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.897651 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 41.085366 # average number of cycles each access was blocked
+system.cpu0.dcache.occ_blocks::cpu0.data 476.919366 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.931483 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.931483 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 5895102 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 5895102 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3238989 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3238989 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174455 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 174455 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171581 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 171581 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 9134091 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 9134091 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 9134091 # number of overall hits
+system.cpu0.dcache.overall_hits::total 9134091 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 390587 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 390587 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1579573 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1579573 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8896 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 8896 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7728 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 7728 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 1970160 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1970160 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 1970160 # number of overall misses
+system.cpu0.dcache.overall_misses::total 1970160 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5389048500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 5389048500 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60454939374 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 60454939374 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88150000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 88150000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50211500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 50211500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 65843987874 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 65843987874 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 65843987874 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 65843987874 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 6285689 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 6285689 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818562 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 4818562 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183351 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 183351 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179309 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 179309 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 11104251 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 11104251 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 11104251 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 11104251 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062139 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.062139 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327810 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.327810 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048519 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048519 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043099 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043099 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.177424 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.177424 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177424 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.177424 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.306362 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.306362 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38272.963246 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 38272.963246 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9908.947842 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9908.947842 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6497.347308 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6497.347308 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33420.629733 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33420.629733 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33420.629733 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33420.629733 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 8059 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 2986 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 556 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.494604 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 37.325000 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 255577 # number of writebacks
-system.cpu0.dcache.writebacks::total 255577 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202032 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 202032 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450989 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1450989 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 498 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 498 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653021 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1653021 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653021 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1653021 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188734 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 188734 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131032 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 131032 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8374 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8374 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7739 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7739 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 319766 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 319766 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 319766 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 319766 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2333622500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2333622500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054127491 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054127491 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66245000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66245000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34997500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34997500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6387749991 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 6387749991 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6387749991 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 6387749991 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431600500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431600500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199905877 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199905877 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631506377 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631506377 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030063 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030063 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027183 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027183 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045875 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045875 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043166 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043166 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.028812 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.028812 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12364.611040 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12364.611040 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30939.980241 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30939.980241 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7910.795319 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7910.795319 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4522.225094 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4522.225094 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 255180 # number of writebacks
+system.cpu0.dcache.writebacks::total 255180 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202008 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 202008 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1448555 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1448555 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 484 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 484 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1650563 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1650563 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1650563 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1650563 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188579 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 188579 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131018 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 131018 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8412 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8412 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7726 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7726 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 319597 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 319597 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 319597 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 319597 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2343972000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2343972000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4029495991 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4029495991 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66259000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66259000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34759500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34759500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6373467991 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6373467991 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6373467991 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6373467991 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13432446000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13432446000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199878877 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199878877 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14632324877 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14632324877 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030001 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030001 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027190 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027190 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045879 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045879 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043088 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043088 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.028781 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.028781 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12429.655476 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12429.655476 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30755.285465 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30755.285465 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7876.723728 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7876.723728 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4499.029252 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4499.029252 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19942.202183 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19942.202183 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19942.202183 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19942.202183 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 43030291 # DTB read hits
-system.cpu1.dtb.read_misses 42638 # DTB read misses
-system.cpu1.dtb.write_hits 6991861 # DTB write hits
-system.cpu1.dtb.write_misses 11867 # DTB write misses
+system.cpu1.dtb.read_hits 43034108 # DTB read hits
+system.cpu1.dtb.read_misses 42641 # DTB read misses
+system.cpu1.dtb.write_hits 7001737 # DTB write hits
+system.cpu1.dtb.write_misses 11814 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2362 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2846 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.flush_entries 2370 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 2838 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 690 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 43072929 # DTB read accesses
-system.cpu1.dtb.write_accesses 7003728 # DTB write accesses
+system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 43076749 # DTB read accesses
+system.cpu1.dtb.write_accesses 7013551 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 50022152 # DTB hits
-system.cpu1.dtb.misses 54505 # DTB misses
-system.cpu1.dtb.accesses 50076657 # DTB accesses
-system.cpu1.itb.inst_hits 7786412 # ITB inst hits
-system.cpu1.itb.inst_misses 5635 # ITB inst misses
+system.cpu1.dtb.hits 50035845 # DTB hits
+system.cpu1.dtb.misses 54455 # DTB misses
+system.cpu1.dtb.accesses 50090300 # DTB accesses
+system.cpu1.itb.inst_hits 7783284 # ITB inst hits
+system.cpu1.itb.inst_misses 5669 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1584 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1542 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 7792047 # ITB inst accesses
-system.cpu1.itb.hits 7786412 # DTB hits
-system.cpu1.itb.misses 5635 # DTB misses
-system.cpu1.itb.accesses 7792047 # DTB accesses
-system.cpu1.numCycles 409024249 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 7788953 # ITB inst accesses
+system.cpu1.itb.hits 7783284 # DTB hits
+system.cpu1.itb.misses 5669 # DTB misses
+system.cpu1.itb.accesses 7788953 # DTB accesses
+system.cpu1.numCycles 409060969 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 9020667 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 7346445 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 421687 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 5902094 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 5066087 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 9019142 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 7341577 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 421290 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 5896961 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 5059614 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 810235 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 44717 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 19548819 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 61628162 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9020667 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 5876322 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 13445282 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3432135 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 71958 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 78159434 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 5756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 48212 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 140837 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 7784486 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 545452 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3066 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 113770833 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.663645 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.994153 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 812166 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 44802 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 19538569 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 61710735 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9019142 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 5871780 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 13457716 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3440559 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 72159 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 78167878 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 5662 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 49809 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 140998 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 150 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 7781352 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 538014 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3102 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 113786982 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.664391 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.995438 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 100333102 88.19% 88.19% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 820750 0.72% 88.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 967014 0.85% 89.76% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1722421 1.51% 91.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1420935 1.25% 92.52% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 598048 0.53% 93.05% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1962596 1.73% 94.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 435893 0.38% 95.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 5510074 4.84% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 100336589 88.18% 88.18% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 821334 0.72% 88.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 966420 0.85% 89.75% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1725152 1.52% 91.27% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1418529 1.25% 92.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 601242 0.53% 93.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1958088 1.72% 94.76% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 436465 0.38% 95.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5523163 4.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 113770833 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.022054 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.150671 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 20932611 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 77783544 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 12260401 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 543319 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2250958 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1146967 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 100968 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 71503765 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 336196 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2250958 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 22152530 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 32126143 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 41276446 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11489660 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4475096 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 67542275 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 19496 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 697256 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3178756 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 32684 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 70870880 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 310023883 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 309964693 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 59190 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 50213421 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 20657459 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 473589 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 413624 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 8131877 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 12919526 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8160199 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1076421 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1515550 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 62172086 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1201080 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 89161848 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 100982 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 13762748 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 36926540 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 280453 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 113770833 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.783697 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.520241 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 113786982 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.022048 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.150860 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 20926147 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 77797918 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 12266013 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 542191 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2254713 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1149115 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 100993 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 71511004 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 338807 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2254713 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 22129407 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 32117603 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 41299485 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 11510444 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4475330 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 67658360 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 19594 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 697706 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3178110 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 32539 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 70993653 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 310596355 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 310537273 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 59082 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 50200074 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 20793579 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 474201 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 414075 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 8134070 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 12921007 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 8155176 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1083797 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1589261 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 62166896 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1195329 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 89153414 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 99788 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 13746763 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 36760953 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 275268 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 113786982 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.783512 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.519359 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 83205809 73.13% 73.13% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 8622127 7.58% 80.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4341809 3.82% 84.53% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3750529 3.30% 87.83% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10472490 9.20% 97.03% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1973623 1.73% 98.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1061651 0.93% 99.70% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 265825 0.23% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 76970 0.07% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 83183185 73.10% 73.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8664055 7.61% 80.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 4355929 3.83% 84.55% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3746204 3.29% 87.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10471181 9.20% 97.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1956933 1.72% 98.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1074012 0.94% 99.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 258436 0.23% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 77047 0.07% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 113770833 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 113786982 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 29803 0.38% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 992 0.01% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7572506 95.90% 96.29% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 293239 3.71% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 29283 0.37% 0.37% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 991 0.01% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7571422 95.88% 96.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 294824 3.73% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 37491969 42.05% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 61148 0.07% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.47% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 43923048 49.26% 91.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7369892 8.27% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 37493479 42.06% 42.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 61246 0.07% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 43910750 49.25% 91.73% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7372221 8.27% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 89161848 # Type of FU issued
-system.cpu1.iq.rate 0.217987 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7896540 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.088564 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 300131429 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 77144913 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 54450273 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 14948 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8092 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6814 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 96736439 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7887 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 357826 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 89153414 # Type of FU issued
+system.cpu1.iq.rate 0.217947 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7896520 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.088572 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 300129512 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 77117892 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 54483079 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 14896 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8093 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 96728092 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7845 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 354516 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2919371 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 4089 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1133342 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2925065 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 4096 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17562 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1131401 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31965401 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 692354 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31964883 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 695794 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2250958 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 24192691 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 367138 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 63477454 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 113697 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 12919526 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8160199 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 893697 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 68960 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3858 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 17660 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 208465 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 159370 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 367835 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 87401818 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43412086 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1760030 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2254713 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 24187633 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 367329 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 63466208 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 114663 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 12921007 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 8155176 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 887376 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 69283 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3741 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17562 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 208254 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 160111 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 368365 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 87428231 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43415449 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1725183 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 104288 # number of nop insts executed
-system.cpu1.iew.exec_refs 50709476 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 7088545 # Number of branches executed
-system.cpu1.iew.exec_stores 7297390 # Number of stores executed
-system.cpu1.iew.exec_rate 0.213684 # Inst execution rate
-system.cpu1.iew.wb_sent 86601126 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 54457087 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 30364436 # num instructions producing a value
-system.cpu1.iew.wb_consumers 54295656 # num instructions consuming a value
+system.cpu1.iew.exec_nop 103983 # number of nop insts executed
+system.cpu1.iew.exec_refs 50722611 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 7090027 # Number of branches executed
+system.cpu1.iew.exec_stores 7307162 # Number of stores executed
+system.cpu1.iew.exec_rate 0.213729 # Inst execution rate
+system.cpu1.iew.wb_sent 86641966 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 54489882 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 30361493 # num instructions producing a value
+system.cpu1.iew.wb_consumers 54263873 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.133139 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.559242 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.133207 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.559516 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 13692554 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 920627 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 322274 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 111568344 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.442227 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.413238 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 13678793 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 920061 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 321962 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 111532269 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.442230 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.412276 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 94375668 84.59% 84.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8446118 7.57% 92.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2197127 1.97% 94.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1290727 1.16% 95.29% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1277171 1.14% 96.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 591366 0.53% 96.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1009730 0.91% 97.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 541366 0.49% 98.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1839071 1.65% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 94330377 84.58% 84.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8440609 7.57% 92.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2214130 1.99% 94.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1297536 1.16% 95.29% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1275593 1.14% 96.44% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 591609 0.53% 96.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 995873 0.89% 97.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 566603 0.51% 98.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1819939 1.63% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 111568344 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38958201 # Number of instructions committed
-system.cpu1.commit.committedOps 49338577 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 111532269 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38948804 # Number of instructions committed
+system.cpu1.commit.committedOps 49322865 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 17027012 # Number of memory references committed
-system.cpu1.commit.loads 10000155 # Number of loads committed
-system.cpu1.commit.membars 202531 # Number of memory barriers committed
-system.cpu1.commit.branches 6139960 # Number of branches committed
+system.cpu1.commit.refs 17019717 # Number of memory references committed
+system.cpu1.commit.loads 9995942 # Number of loads committed
+system.cpu1.commit.membars 202353 # Number of memory barriers committed
+system.cpu1.commit.branches 6138218 # Number of branches committed
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 43727423 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 556605 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1839071 # number cycles where commit BW limit reached
+system.cpu1.commit.int_insts 43713249 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 556359 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1819939 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 171645222 # The number of ROB reads
-system.cpu1.rob.rob_writes 128401309 # The number of ROB writes
-system.cpu1.timesIdled 1423775 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 295253416 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 4776625618 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 38888562 # Number of Instructions Simulated
-system.cpu1.committedOps 49268938 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 38888562 # Number of Instructions Simulated
-system.cpu1.cpi 10.517855 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 10.517855 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.095076 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.095076 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 391481129 # number of integer regfile reads
-system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 18962770 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes
-system.cpu1.icache.replacements 614989 # number of replacements
-system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use
-system.cpu1.icache.total_refs 7122851 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 615501 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 11.572444 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 74507010000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 498.619037 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.973865 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.973865 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 7122851 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 7122851 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 7122851 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 7122851 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 7122851 # number of overall hits
-system.cpu1.icache.overall_hits::total 7122851 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 661583 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 661583 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 661583 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 661583 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 661583 # number of overall misses
-system.cpu1.icache.overall_misses::total 661583 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8883357995 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 8883357995 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 8883357995 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 8883357995 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 8883357995 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 8883357995 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 7784434 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 7784434 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 7784434 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 7784434 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 7784434 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 7784434 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084988 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.084988 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084988 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.084988 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084988 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.084988 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.427844 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13427.427844 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13427.427844 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13427.427844 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 3547 # number of cycles access was blocked
+system.cpu1.rob.rob_reads 171599349 # The number of ROB reads
+system.cpu1.rob.rob_writes 128350222 # The number of ROB writes
+system.cpu1.timesIdled 1423694 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 295273987 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 4796667155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 38879165 # Number of Instructions Simulated
+system.cpu1.committedOps 49253226 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 38879165 # Number of Instructions Simulated
+system.cpu1.cpi 10.521341 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 10.521341 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.095045 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.095045 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 391632222 # number of integer regfile reads
+system.cpu1.int_regfile_writes 56613239 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 4857 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 2306 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 19006571 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 429961 # number of misc regfile writes
+system.cpu1.icache.replacements 614526 # number of replacements
+system.cpu1.icache.tagsinuse 498.795598 # Cycle average of tags in use
+system.cpu1.icache.total_refs 7119619 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 615038 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 11.575901 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 74541182500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 498.795598 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.974210 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.974210 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 7119619 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 7119619 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 7119619 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 7119619 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 7119619 # number of overall hits
+system.cpu1.icache.overall_hits::total 7119619 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 661683 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 661683 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 661683 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 661683 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 661683 # number of overall misses
+system.cpu1.icache.overall_misses::total 661683 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8857903496 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 8857903496 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 8857903496 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 8857903496 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 8857903496 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 8857903496 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 7781302 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 7781302 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 7781302 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 7781302 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 7781302 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 7781302 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085035 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.085035 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085035 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.085035 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085035 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.085035 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13386.929233 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13386.929233 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13386.929233 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13386.929233 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13386.929233 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13386.929233 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 2804 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 182 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 188 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.489011 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.914894 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46050 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 46050 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 46050 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 46050 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 46050 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 46050 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615533 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 615533 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 615533 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 615533 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 615533 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 615533 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7269169496 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 7269169496 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7269169496 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 7269169496 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7269169496 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 7269169496 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079072 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.079072 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.079072 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11809.552853 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46618 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 46618 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 46618 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 46618 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 46618 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 46618 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615065 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 615065 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 615065 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 615065 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 615065 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 615065 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7253593996 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 7253593996 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7253593996 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 7253593996 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7253593996 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 7253593996 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2902500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2902500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2902500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 2902500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079044 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.079044 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.079044 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11793.215345 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11793.215345 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11793.215345 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 363437 # number of replacements
-system.cpu1.dcache.tagsinuse 485.666262 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 13086846 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 363802 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 35.972441 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 70623957000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 485.666262 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.948567 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.948567 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 8551806 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 8551806 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 4291461 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 4291461 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103521 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 103521 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100890 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 100890 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 12843267 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 12843267 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 12843267 # number of overall hits
-system.cpu1.dcache.overall_hits::total 12843267 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 401802 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 401802 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1565358 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1565358 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14225 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 14225 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10942 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 10942 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 1967160 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 1967160 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 1967160 # number of overall misses
-system.cpu1.dcache.overall_misses::total 1967160 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6026246000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 6026246000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64613580018 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 64613580018 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131651000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 131651000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58881000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 58881000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 70639826018 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 70639826018 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 70639826018 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 70639826018 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 8953608 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 8953608 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 5856819 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 5856819 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 117746 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 117746 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111832 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 111832 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 14810427 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 14810427 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 14810427 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 14810427 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044876 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.044876 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267271 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.267271 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120811 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120811 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097843 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097843 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132823 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.132823 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132823 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.132823 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14998.048790 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14998.048790 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41277.190277 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 41277.190277 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9254.903339 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9254.903339 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5381.191738 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5381.191738 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 35909.547784 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 35909.547784 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 28351 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 15005 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 3227 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.785559 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 89.315476 # average number of cycles each access was blocked
+system.cpu1.dcache.replacements 363115 # number of replacements
+system.cpu1.dcache.tagsinuse 487.216470 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 13089737 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 363478 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 36.012460 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 70648399000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 487.216470 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.951595 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.951595 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 8556277 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 8556277 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 4290501 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 4290501 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104307 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 104307 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100808 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 100808 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 12846778 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 12846778 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 12846778 # number of overall hits
+system.cpu1.dcache.overall_hits::total 12846778 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 401782 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 401782 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1563319 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1563319 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14178 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 14178 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10904 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 10904 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 1965101 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 1965101 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 1965101 # number of overall misses
+system.cpu1.dcache.overall_misses::total 1965101 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6025006500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 6025006500 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64041163497 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 64041163497 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131124500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 131124500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58523500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 58523500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 70066169997 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 70066169997 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 70066169997 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 70066169997 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 8958059 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 8958059 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 5853820 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 5853820 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 118485 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 118485 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111712 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 111712 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 14811879 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 14811879 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 14811879 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 14811879 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044851 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.044851 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267060 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.267060 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119661 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119661 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097608 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097608 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132671 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.132671 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132671 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.132671 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14995.710360 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14995.710360 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40964.872491 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 40964.872491 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9248.448300 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9248.448300 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5367.158841 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5367.158841 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35655.251306 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 35655.251306 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35655.251306 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 35655.251306 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 28539 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 15177 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 3269 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.730193 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 91.427711 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 328383 # number of writebacks
-system.cpu1.dcache.writebacks::total 328383 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170419 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 170419 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402227 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 1402227 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572646 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 1572646 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572646 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1572646 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231383 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 231383 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163131 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 163131 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10936 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10936 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 394514 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 394514 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 394514 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 394514 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870368000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870368000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5301094210 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5301094210 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90117500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90117500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37009000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37009000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8171462210 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 8171462210 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8171462210 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 8171462210 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263515000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263515000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26947906394 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26947906394 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196211421394 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196211421394 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025842 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025842 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108496 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108496 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097790 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097790 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026638 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.026638 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12405.267457 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12405.267457 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32495.934004 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32495.934004 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7054.207436 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7054.207436 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3384.144111 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3384.144111 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 327455 # number of writebacks
+system.cpu1.dcache.writebacks::total 327455 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170587 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 170587 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1400204 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 1400204 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1432 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1432 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 1570791 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 1570791 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570791 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 1570791 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231195 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 231195 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163115 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 163115 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10902 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10902 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 394310 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 394310 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 394310 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 394310 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2860496500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2860496500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5258978708 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5258978708 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89750500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89750500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36721500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36721500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8119475208 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 8119475208 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8119475208 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 8119475208 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169298302500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169298302500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 27190030960 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 27190030960 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196488333460 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196488333460 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025809 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025809 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027865 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027865 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107575 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107575 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097590 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097590 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026621 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026621 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026621 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.026621 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12372.657281 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12372.657281 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32240.926389 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32240.926389 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7041.463989 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7041.463989 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3368.326912 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3368.326912 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20591.603581 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20591.603581 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20591.603581 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20591.603581 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1082174693399 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1082174693399 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1162989936366 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1162989936366 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1162989936366 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1162989936366 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 43757 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 43794 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 53969 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 53929 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
+mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
-midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
clock=1000
forward_snoops=false
-hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.membus]
type=CoherentBus
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 21:11:31
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 01:42:51
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2523500318000 because m5_exit instruction encountered
+Exiting @ tick 2523517846500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.523500 # Number of seconds simulated
-sim_ticks 2523500318000 # Number of ticks simulated
-final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.523518 # Number of seconds simulated
+sim_ticks 2523517846500 # Number of ticks simulated
+final_tick 2523517846500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 76318 # Simulator instruction rate (inst/s)
-host_op_rate 98167 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3178196363 # Simulator tick rate (ticks/s)
-host_mem_usage 441472 # Number of bytes of host memory used
-host_seconds 794.00 # Real time elapsed on the host
-sim_insts 60596849 # Number of instructions simulated
-sim_ops 77944928 # Number of ops (including micro ops) simulated
+host_inst_rate 24932 # Simulator instruction rate (inst/s)
+host_op_rate 32070 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1038273503 # Simulator tick rate (ticks/s)
+host_mem_usage 403456 # Number of bytes of host memory used
+host_seconds 2430.49 # Real time elapsed on the host
+sim_insts 60597240 # Number of instructions simulated
+sim_ops 77945362 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 798272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129432080 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 798272 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 798272 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799176 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12473 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096842 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813129 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47369455 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1040 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 316333 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3603459 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51290337 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 316333 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 316333 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499139 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1195186 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2694325 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1499139 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47369455 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1040 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096860 # Total number of read requests seen
-system.physmem.writeReqs 813144 # Total number of write requests seen
-system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966199040 # Total number of bytes read from memory
-system.physmem.bytesWritten 52041216 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis
+system.physmem.bw_total::cpu.inst 316333 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4798644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53984661 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096842 # Total number of read requests seen
+system.physmem.writeReqs 813129 # Total number of write requests seen
+system.physmem.cpureqs 218393 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966197888 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040256 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129432080 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799176 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 355 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943949 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943429 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943244 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943101 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943294 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943633 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943702 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::13 943617 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 943644 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943223 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50104 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50365 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 49969 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50029 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50827 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51125 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51357 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51177 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51291 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2523499110500 # Total gap between requests
+system.physmem.numWrRetry 1183132 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2523516727500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154616 # Categorize read packet sizes
+system.physmem.readPktSize::6 154598 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1907897 # categorize write packet sizes
+system.physmem.writePktSize::2 1937150 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59126 # categorize write packet sizes
+system.physmem.writePktSize::6 59111 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1042834 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 981659 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 938516 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 972890 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2730387 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2738053 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5375105 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 45255 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 30596 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 30326 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 30339 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 57584 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 37998 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 64788 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 17179 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2831 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 20 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2912 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3008 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3102 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3240 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3424 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3580 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 3721 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 3875 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32552 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32442 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32346 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32252 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32114 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 31930 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 31774 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31633 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31479 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests
-system.physmem.totBusLat 60386104000 # Total cycles spent in databus access
-system.physmem.totBankLat 210282128000 # Total cycles spent in bank access
-system.physmem.avgQLat 3116.78 # Average queueing delay per request
-system.physmem.avgBankLat 13929.17 # Average bank access latency per request
+system.physmem.totQLat 328143428340 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 404872878340 # Sum of mem lat for all requests
+system.physmem.totBusLat 60385948000 # Total cycles spent in databus access
+system.physmem.totBankLat 16343502000 # Total cycles spent in bank access
+system.physmem.avgQLat 21736.41 # Average queueing delay per request
+system.physmem.avgBankLat 1082.60 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 21045.95 # Average memory access latency
+system.physmem.avgMemAccLat 26819.01 # Average memory access latency
system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.52 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.13 # Average read queue length over time
-system.physmem.avgWrQLen 11.37 # Average write queue length over time
-system.physmem.readRowHits 15049962 # Number of row buffer hits during reads
-system.physmem.writeRowHits 784769 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes
-system.physmem.avgGap 158610.84 # Average gap between requests
+system.physmem.avgRdQLen 0.16 # Average read queue length over time
+system.physmem.avgWrQLen 11.85 # Average write queue length over time
+system.physmem.readRowHits 15052691 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784814 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 96.52 # Row buffer hit rate for writes
+system.physmem.avgGap 158612.28 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51279526 # DTB read hits
-system.cpu.dtb.read_misses 73667 # DTB read misses
-system.cpu.dtb.write_hits 11753863 # DTB write hits
-system.cpu.dtb.write_misses 17234 # DTB write misses
+system.cpu.dtb.read_hits 51295505 # DTB read hits
+system.cpu.dtb.read_misses 73548 # DTB read misses
+system.cpu.dtb.write_hits 11769416 # DTB write hits
+system.cpu.dtb.write_misses 17308 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4224 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4227 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2384 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 485 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51353193 # DTB read accesses
-system.cpu.dtb.write_accesses 11771097 # DTB write accesses
+system.cpu.dtb.perms_faults 1341 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51369053 # DTB read accesses
+system.cpu.dtb.write_accesses 11786724 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63033389 # DTB hits
-system.cpu.dtb.misses 90901 # DTB misses
-system.cpu.dtb.accesses 63124290 # DTB accesses
-system.cpu.itb.inst_hits 11603865 # ITB inst hits
-system.cpu.itb.inst_misses 11359 # ITB inst misses
+system.cpu.dtb.hits 63064921 # DTB hits
+system.cpu.dtb.misses 90856 # DTB misses
+system.cpu.dtb.accesses 63155777 # DTB accesses
+system.cpu.itb.inst_hits 11599470 # ITB inst hits
+system.cpu.itb.inst_misses 11387 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2573 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2571 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2925 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 11615224 # ITB inst accesses
-system.cpu.itb.hits 11603865 # DTB hits
-system.cpu.itb.misses 11359 # DTB misses
-system.cpu.itb.accesses 11615224 # DTB accesses
-system.cpu.numCycles 470951029 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11610857 # ITB inst accesses
+system.cpu.itb.hits 11599470 # DTB hits
+system.cpu.itb.misses 11387 # DTB misses
+system.cpu.itb.accesses 11610857 # DTB accesses
+system.cpu.numCycles 470965317 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits
+system.cpu.BPredUnit.lookups 14487364 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11552940 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 711872 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 9478925 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7718754 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1413170 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 72913 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 29863213 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 90950612 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14487364 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9131924 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20302505 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4756883 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 122119 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 96718680 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 94285 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 205383 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11595815 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 694954 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5716 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150585846 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.753226 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.110122 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130298669 86.53% 86.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1345087 0.89% 87.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1687300 1.12% 88.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2309882 1.53% 90.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2120076 1.41% 91.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1117365 0.74% 92.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2592055 1.72% 93.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 766865 0.51% 94.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8348547 5.54% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150585846 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030761 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.193115 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31645642 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96356331 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18440866 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1036174 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3106833 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1972079 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 172496 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 107972230 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 569848 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3106833 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33398103 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36860235 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 53381295 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17668341 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6171039 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 103073979 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21323 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1016179 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4134721 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 29043 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 106845782 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 470577676 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 470486821 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90855 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 28114572 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 880520 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 786795 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12341610 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19847152 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13390380 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1964070 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2407797 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95636460 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2047932 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 123412976 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 169796 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 19147761 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 47762380 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 503425 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150585846 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.819552 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.531798 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106411056 70.66% 70.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13811108 9.17% 79.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7031286 4.67% 84.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5838601 3.88% 88.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12442775 8.26% 96.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2756258 1.83% 98.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1722165 1.14% 99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 442663 0.29% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 129934 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150585846 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 60097 0.68% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 3 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8367175 94.63% 95.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 414340 4.69% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57952199 46.96% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93294 0.08% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52612072 42.63% 89.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12389576 10.04% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued
-system.cpu.iq.rate 0.261997 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 123412976 # Type of FU issued
+system.cpu.iq.rate 0.262043 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8841615 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071643 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 406490722 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 116848589 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85936823 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 22982 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12524 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131878765 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12160 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 623393 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4131120 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30077 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1591861 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107803 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 700236 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3106833 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27952249 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 439003 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 97906020 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 205363 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19847152 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13390380 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1460347 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 117327 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3551 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30077 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 353051 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 272581 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 625632 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121337067 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51981447 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2075909 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 220747 # number of nop insts executed
-system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11527542 # Number of branches executed
-system.cpu.iew.exec_stores 12265452 # Number of stores executed
-system.cpu.iew.exec_rate 0.257499 # Inst execution rate
-system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47162688 # num instructions producing a value
-system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value
+system.cpu.iew.exec_nop 221628 # number of nop insts executed
+system.cpu.iew.exec_refs 64262784 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11537560 # Number of branches executed
+system.cpu.iew.exec_stores 12281337 # Number of stores executed
+system.cpu.iew.exec_rate 0.257635 # Inst execution rate
+system.cpu.iew.wb_sent 120375089 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85947111 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47183541 # num instructions producing a value
+system.cpu.iew.wb_consumers 88082196 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182491 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535676 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 18905107 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1544507 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 541940 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147479013 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.529538 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.516870 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 119767946 81.21% 81.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13521242 9.17% 90.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3932347 2.67% 93.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2139837 1.45% 94.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1947041 1.32% 95.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 981141 0.67% 96.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1580635 1.07% 97.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 757975 0.51% 98.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2850849 1.93% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60747230 # Number of instructions committed
-system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 147479013 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60747621 # Number of instructions committed
+system.cpu.commit.committedOps 78095743 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27514399 # Number of memory references committed
-system.cpu.commit.loads 15715935 # Number of loads committed
-system.cpu.commit.membars 413101 # Number of memory barriers committed
-system.cpu.commit.branches 10023041 # Number of branches committed
+system.cpu.commit.refs 27514551 # Number of memory references committed
+system.cpu.commit.loads 15716032 # Number of loads committed
+system.cpu.commit.membars 413105 # Number of memory barriers committed
+system.cpu.commit.branches 10023101 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69133795 # Number of committed integer instructions.
-system.cpu.commit.function_calls 995976 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 69134175 # Number of committed integer instructions.
+system.cpu.commit.function_calls 995982 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2850849 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 239806361 # The number of ROB reads
-system.cpu.rob.rob_writes 197293644 # The number of ROB writes
-system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60596849 # Number of Instructions Simulated
-system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated
-system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 549353817 # number of integer regfile reads
-system.cpu.int_regfile_writes 87979071 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8318 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2932 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912865 # number of misc regfile writes
-system.cpu.icache.replacements 980837 # number of replacements
-system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use
-system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor
+system.cpu.rob.rob_reads 239713879 # The number of ROB reads
+system.cpu.rob.rob_writes 197204165 # The number of ROB writes
+system.cpu.timesIdled 1775890 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320379471 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575982354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60597240 # Number of Instructions Simulated
+system.cpu.committedOps 77945362 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60597240 # Number of Instructions Simulated
+system.cpu.cpi 7.772059 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.772059 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.128666 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.128666 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 549724990 # number of integer regfile reads
+system.cpu.int_regfile_writes 88045459 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8276 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2926 # number of floating regfile writes
+system.cpu.misc_regfile_reads 30431218 # number of misc regfile reads
+system.cpu.misc_regfile_writes 912900 # number of misc regfile writes
+system.cpu.icache.replacements 981280 # number of replacements
+system.cpu.icache.tagsinuse 511.007424 # Cycle average of tags in use
+system.cpu.icache.total_refs 10533801 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 981792 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 10.729157 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6666221000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.007424 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits
-system.cpu.icache.overall_hits::total 10539450 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses
-system.cpu.icache.overall_misses::total 1060605 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11600055 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11600055 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11600055 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11600055 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091431 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.091431 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.091431 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.091431 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.091431 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.091431 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13163.622169 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_hits::cpu.inst 10533801 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 10533801 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 10533801 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 10533801 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 10533801 # number of overall hits
+system.cpu.icache.overall_hits::total 10533801 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1061888 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1061888 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1061888 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1061888 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1061888 # number of overall misses
+system.cpu.icache.overall_misses::total 1061888 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 13967491489 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 13967491489 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 13967491489 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 13967491489 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 13967491489 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 13967491489 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11595689 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11595689 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11595689 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11595689 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11595689 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11595689 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091576 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.091576 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.091576 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.091576 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.091576 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.091576 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13153.450730 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13153.450730 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13153.450730 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13153.450730 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 5396 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 1220 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 17.808581 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 610 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79214 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 79214 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 79214 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 79214 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 79214 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 79214 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981391 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 981391 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 981391 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 981391 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 981391 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 981391 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11354795991 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11354795991 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11354795991 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11354795991 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11354795991 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11354795991 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80057 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 80057 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 80057 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 80057 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 80057 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 80057 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981831 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 981831 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 981831 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 981831 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 981831 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 981831 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11353310491 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11353310491 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11353310491 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11353310491 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11353310491 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11353310491 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084602 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.084602 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.084602 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11570.104057 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11570.104057 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084672 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.084672 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.084672 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.406015 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.406015 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 643459 # number of replacements
-system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
-system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits
-system.cpu.dcache.overall_hits::total 21094791 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses
-system.cpu.dcache.overall_misses::total 3692032 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks
-system.cpu.dcache.writebacks::total 607749 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 64388 # number of replacements
-system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 129780 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 14.728779 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 2488431429000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 36915.014302 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 29.696477 # Average occupied blocks per requestor
+system.cpu.l2cache.replacements 64370 # number of replacements
+system.cpu.l2cache.tagsinuse 51358.666800 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1910788 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 129761 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 14.725441 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 2488452468500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 36927.008868 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker 28.274765 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 8183.272105 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6245.619403 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.563278 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000453 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 8177.411143 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 6225.971675 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.563461 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000431 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.124867 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.095301 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.783899 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79304 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10595 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 967765 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 387173 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1444837 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 607749 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 607749 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 112887 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 112887 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 79304 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 10595 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 967765 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 500060 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1557724 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 79304 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 10595 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 967765 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 500060 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1557724 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 43 # number of ReadReq misses
+system.cpu.l2cache.occ_percent::cpu.inst 0.124777 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.095001 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.783671 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 78622 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10599 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 968211 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 387222 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1444654 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 607832 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 607832 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 112968 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 112968 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 78622 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 10599 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 968211 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 500190 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1557622 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 78622 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 10599 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 968211 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 500190 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1557622 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 10735 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 23152 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 12367 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 10717 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133176 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133176 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 43 # number of demand (read+write) misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 12372 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 143911 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 156328 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 43 # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst 12367 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143903 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 12372 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 143911 # number of overall misses
-system.cpu.l2cache.overall_misses::total 156328 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2913500 # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst 12367 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143903 # number of overall misses
+system.cpu.l2cache.overall_misses::total 156313 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2982500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 660133000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590903498 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1254067998 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 477000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 477000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6777740498 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6777740498 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2913500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 653684500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590050498 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1246835498 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 431500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 431500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6675201498 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6675201498 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2982500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 660133000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7368643996 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 8031808496 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2913500 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 653684500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7265251996 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 7922036996 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2982500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 660133000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7368643996 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 8031808496 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 79347 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10597 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 980137 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 397908 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1467989 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 607749 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 607749 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 246063 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 246063 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 79347 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 10597 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 980137 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 643971 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1714052 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 79347 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 10597 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 980137 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 643971 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1714052 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000542 # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_miss_latency::cpu.inst 653684500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7265251996 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 7922036996 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 78663 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10601 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 980578 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 397939 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1467781 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 607832 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 607832 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 246154 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 246154 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 78663 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 10601 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 980578 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 644093 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1713935 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 78663 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 10601 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 980578 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 644093 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1713935 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000521 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012623 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.015771 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985478 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985478 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541227 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.541227 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000542 # miss rate for demand accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012612 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026931 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.015756 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986158 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986158 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541068 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.541068 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000521 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012623 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.223474 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.091204 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000542 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012612 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.223420 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.091201 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000521 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012623 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.223474 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.091204 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 67755.813953 # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012612 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.223420 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.091201 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72743.902439 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53357.015842 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55044.573638 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 54166.724171 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.468129 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.468129 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50893.107602 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50893.107602 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52857.160184 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55057.431931 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 53912.548017 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 147.723382 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 147.723382 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50119.393164 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50119.393164 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72743.902439 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51377.926513 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52857.160184 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50487.147565 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 50680.602356 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72743.902439 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51377.926513 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52857.160184 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50487.147565 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 50680.602356 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 59126 # number of writebacks
-system.cpu.l2cache.writebacks::total 59126 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 59111 # number of writebacks
+system.cpu.l2cache.writebacks::total 59111 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 43 # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12360 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10675 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 23080 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2918 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12355 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 23054 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133176 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 133176 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 43 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 12360 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 143851 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 156256 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 43 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 12355 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143842 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 156240 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 12360 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 143851 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 156256 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2368082 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12355 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143842 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 156240 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2461077 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93002 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 503399135 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 452451368 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 958311587 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29209900 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29209900 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 497040130 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 451732824 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 951327033 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5125972608 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5125972608 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2368082 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5024401862 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5024401862 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2461077 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93002 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503399135 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578423976 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 6084284195 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2368082 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 497040130 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5476134686 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 5975728895 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2461077 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93002 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503399135 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578423976 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 6084284195 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 497040130 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5476134686 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 5975728895 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963877530 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166968222685 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18087556027 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18087556027 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167008598530 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167012943685 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18318853408 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18318853408 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185051433557 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185055778712 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185327451938 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185331797093 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026778 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015707 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986158 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986158 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541068 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541068 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.091162 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.091159 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.091162 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.091159 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40728.085356 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42384.203091 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41521.299263 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.246744 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.246744 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40229.876973 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42392.344595 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41265.161490 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38490.213011 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38490.213011 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37724.699758 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37724.699758 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 643581 # number of replacements
+system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
+system.cpu.dcache.total_refs 21676734 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 644093 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 33.654665 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 13816029 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13816029 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7289413 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7289413 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 282441 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 282441 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 285740 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 285740 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21105442 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21105442 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21105442 # number of overall hits
+system.cpu.dcache.overall_hits::total 21105442 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 731834 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 731834 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2961255 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2961255 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13603 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13603 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3693089 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3693089 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3693089 # number of overall misses
+system.cpu.dcache.overall_misses::total 3693089 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 9564740000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 9564740000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 104026861731 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 104026861731 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180604500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 180604500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 244000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 244000 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 113591601731 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 113591601731 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 113591601731 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 113591601731 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14547863 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14547863 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10250668 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10250668 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296044 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 296044 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 285756 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 285756 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24798531 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24798531 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24798531 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24798531 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050305 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050305 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288884 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.288884 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045949 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045949 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.148924 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.148924 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.148924 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.148924 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.548559 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.548559 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35129.315689 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35129.315689 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13276.813938 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13276.813938 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15250 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15250 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30757.883639 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30757.883639 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 32046 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 14482 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.377752 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 57.697211 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks
+system.cpu.dcache.writebacks::total 607832 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345983 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 345983 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712226 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2712226 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1428 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1428 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3058209 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3058209 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3058209 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3058209 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385851 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385851 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249029 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249029 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634880 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634880 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634880 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634880 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768256000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768256000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8126256417 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8126256417 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140756500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140756500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 212000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 212000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12894512417 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12894512417 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12894512417 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12894512417 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182401837500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182401837500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28201633550 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28201633550 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210603471050 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 210603471050 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041126 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041126 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025602 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025602 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12357.765044 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12357.765044 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32631.767453 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32631.767453 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11561.108830 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11561.108830 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13250 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13250 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1148123553642 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1148123553642 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88023 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
-panic_on_oops=true
-panic_on_panic=true
readfile=tests/halt.sh
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
-image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 11 2012 16:28:23
-gem5 started Dec 11 2012 16:28:35
-gem5 executing on e103721-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 02:09:50
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Switching CPUs...
sim_ticks 2401421439000 # Number of ticks simulated
final_tick 2401421439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 170882 # Simulator instruction rate (inst/s)
-host_op_rate 219406 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6786575645 # Simulator tick rate (ticks/s)
-host_mem_usage 393972 # Number of bytes of host memory used
-host_seconds 353.85 # Real time elapsed on the host
+host_inst_rate 75201 # Simulator instruction rate (inst/s)
+host_op_rate 96555 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2986582566 # Simulator tick rate (ticks/s)
+host_mem_usage 393856 # Number of bytes of host memory used
+host_seconds 804.07 # Real time elapsed on the host
sim_insts 60466509 # Number of instructions simulated
sim_ops 77636591 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.readRowHitRate 99.77 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.24 # Row buffer hit rate for writes
system.physmem.avgGap 182850.04 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 63371 # number of replacements
system.l2c.tagsinuse 50440.930838 # Cycle average of tags in use
system.l2c.total_refs 1764263 # Total number of references to valid blocks.
system.cpu2.int_regfile_writes 30194860 # number of integer regfile writes
system.cpu2.fp_regfile_reads 22317 # number of floating regfile reads
system.cpu2.fp_regfile_writes 20822 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 41979427 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 9419199 # number of misc regfile reads
system.cpu2.misc_regfile_writes 278833 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
-panic_on_oops=true
-panic_on_panic=true
readfile=tests/halt.sh
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
-image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 11 2012 16:28:23
-gem5 started Dec 11 2012 16:28:35
-gem5 executing on e103721-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 02:15:48
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Switching CPUs...
sim_ticks 2540587123500 # Number of ticks simulated
final_tick 2540587123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 67374 # Simulator instruction rate (inst/s)
-host_op_rate 86663 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2824409714 # Simulator tick rate (ticks/s)
-host_mem_usage 407052 # Number of bytes of host memory used
-host_seconds 899.51 # Real time elapsed on the host
+host_inst_rate 28859 # Simulator instruction rate (inst/s)
+host_op_rate 37121 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1209803028 # Simulator tick rate (ticks/s)
+host_mem_usage 406188 # Number of bytes of host memory used
+host_seconds 2100.00 # Real time elapsed on the host
sim_insts 60603607 # Number of instructions simulated
sim_ops 77954043 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.readRowHitRate 99.72 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.67 # Row buffer hit rate for writes
system.physmem.avgGap 157735.86 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 64360 # number of replacements
system.l2c.tagsinuse 51403.610979 # Cycle average of tags in use
system.l2c.total_refs 1940230 # Total number of references to valid blocks.
system.cpu0.int_regfile_writes 46365180 # number of integer regfile writes
system.cpu0.fp_regfile_reads 22828 # number of floating regfile reads
system.cpu0.fp_regfile_writes 19904 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 64493667 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 16064067 # number of misc regfile reads
system.cpu0.misc_regfile_writes 471303 # number of misc regfile writes
system.cpu0.icache.replacements 986601 # number of replacements
system.cpu0.icache.tagsinuse 511.585602 # Cycle average of tags in use
system.cpu1.int_regfile_writes 41743183 # number of integer regfile writes
system.cpu1.fp_regfile_reads 22037 # number of floating regfile reads
system.cpu1.fp_regfile_writes 19620 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 56567930 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 14602821 # number of misc regfile reads
system.cpu1.misc_regfile_writes 442325 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
readfile=tests/halt.sh
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dtb.walker.port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
pio_addr=2305843009213693952
pio_latency=100000
system=system
-int_master=system.membus.slave[4]
+int_master=system.membus.slave[3]
int_slave=system.membus.master[3]
pio=system.membus.master[2]
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.itb.walker.port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[3]
+mem_side=system.membus.slave[2]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
forward_snoops=false
-hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[18]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[4]
[system.membus]
type=CoherentBus
width=8
default=system.membus.badaddr_responder.pio
master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
-slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
+slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-x86.img
+image_file=/gem5/dist/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:14:29
-gem5 started Oct 30 2012 18:26:17
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:20:54
+gem5 started Jan 4 2013 23:13:25
+gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5132789913000 because m5_exit instruction encountered
+Exiting @ tick 5136797077000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.132790 # Number of seconds simulated
-sim_ticks 5132789913000 # Number of ticks simulated
-final_tick 5132789913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.136797 # Number of seconds simulated
+sim_ticks 5136797077000 # Number of ticks simulated
+final_tick 5136797077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 148899 # Simulator instruction rate (inst/s)
-host_op_rate 294332 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1873578722 # Simulator tick rate (ticks/s)
-host_mem_usage 406892 # Number of bytes of host memory used
-host_seconds 2739.56 # Real time elapsed on the host
-sim_insts 407917143 # Number of instructions simulated
-sim_ops 806342485 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2491072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1075264 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10835456 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14405312 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1075264 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1075264 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9578880 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9578880 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38923 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16801 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 169304 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 225083 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149670 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149670 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 485325 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 209489 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2111027 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2806527 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 209489 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 209489 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1866213 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1866213 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1866213 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 485325 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 599 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 209489 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2111027 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4672740 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 225083 # Total number of read requests seen
-system.physmem.writeReqs 149670 # Total number of write requests seen
-system.physmem.cpureqs 388719 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 14405312 # Total number of bytes read from memory
-system.physmem.bytesWritten 9578880 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 14405312 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9578880 # bytesWritten derated as per pkt->getSize()
+host_inst_rate 59794 # Simulator instruction rate (inst/s)
+host_op_rate 118197 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 752889080 # Simulator tick rate (ticks/s)
+host_mem_usage 765888 # Number of bytes of host memory used
+host_seconds 6822.78 # Real time elapsed on the host
+sim_insts 407963976 # Number of instructions simulated
+sim_ops 806432115 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2490112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1077440 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10840448 # Number of bytes read from this memory
+system.physmem.bytes_read::total 14411520 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1077440 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1077440 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9595008 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9595008 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38908 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 16835 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 169382 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 225180 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 149922 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149922 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 484760 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 209749 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2110352 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2805546 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 209749 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 209749 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1867897 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1867897 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1867897 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 484760 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 209749 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2110352 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4673443 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 225180 # Total number of read requests seen
+system.physmem.writeReqs 149922 # Total number of write requests seen
+system.physmem.cpureqs 389082 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 14411520 # Total number of bytes read from memory
+system.physmem.bytesWritten 9595008 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 14411520 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 9595008 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4102 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 13654 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 14948 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 12919 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 15106 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 13327 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 14545 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 13326 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 14277 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 13582 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 14874 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 14098 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 14962 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 13282 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 14549 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 12658 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 14901 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 8775 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 10390 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 8311 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 10526 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 8491 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 9845 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8546 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 9654 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 8818 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 10118 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 9236 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 10295 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 8519 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 9932 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 8008 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 10206 # Track writes on a per bank basis
+system.physmem.neitherReadNorWrite 4150 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 13684 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 14849 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 12992 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 15044 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 13538 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 14702 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 13271 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 14556 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 13423 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 14638 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 13867 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 14842 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 13112 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 14582 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 12817 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 15188 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 8767 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 10396 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 8323 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 10488 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 8797 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 10117 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 8482 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 9956 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 8780 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 9930 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 9138 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 10179 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 8298 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 9881 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 8122 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 10268 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 49 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5132789860500 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5136797025000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 225083 # Categorize read packet sizes
+system.physmem.readPktSize::6 225180 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 149719 # categorize write packet sizes
+system.physmem.writePktSize::6 149922 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4102 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4150 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 176543 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 21526 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 8299 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2898 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2824 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2164 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1517 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1378 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1195 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1112 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 176541 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 21572 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 8228 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2861 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2837 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2184 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1343 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1492 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1352 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1282 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1193 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1108 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 826 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 390 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 237 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 445 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 257 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 173 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 5656 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 6362 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 6464 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 6500 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 6503 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 6505 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 6506 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 6506 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 852 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 5678 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 6373 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 6463 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 6497 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 6506 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 6513 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 6514 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 6514 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 6516 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 841 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 146 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3269589754 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 7518085754 # Sum of mem lat for all requests
-system.physmem.totBusLat 900032000 # Total cycles spent in databus access
-system.physmem.totBankLat 3348464000 # Total cycles spent in bank access
-system.physmem.avgQLat 14530.99 # Average queueing delay per request
-system.physmem.avgBankLat 14881.53 # Average bank access latency per request
+system.physmem.totQLat 3390959114 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7646017114 # Sum of mem lat for all requests
+system.physmem.totBusLat 900420000 # Total cycles spent in databus access
+system.physmem.totBankLat 3354638000 # Total cycles spent in bank access
+system.physmem.avgQLat 15063.90 # Average queueing delay per request
+system.physmem.avgBankLat 14902.55 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 33412.53 # Average memory access latency
+system.physmem.avgMemAccLat 33966.45 # Average memory access latency
system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 11.37 # Average write queue length over time
-system.physmem.readRowHits 198566 # Number of row buffer hits during reads
-system.physmem.writeRowHits 87960 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 58.77 # Row buffer hit rate for writes
-system.physmem.avgGap 13696461.03 # Average gap between requests
-system.iocache.replacements 47576 # number of replacements
-system.iocache.tagsinuse 0.103964 # Cycle average of tags in use
+system.physmem.avgWrQLen 11.93 # Average write queue length over time
+system.physmem.readRowHits 198524 # Number of row buffer hits during reads
+system.physmem.writeRowHits 88099 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 88.19 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes
+system.physmem.avgGap 13694400.52 # Average gap between requests
+system.iocache.replacements 47577 # number of replacements
+system.iocache.tagsinuse 0.116411 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47592 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47593 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4991828572000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.103964 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.006498 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.006498 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
+system.iocache.warmup_cycle 4991829125000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.116411 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.007276 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.007276 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 912 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
-system.iocache.overall_misses::total 47631 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146267932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 146267932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8962382160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 8962382160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 9108650092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 9108650092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 9108650092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 9108650092 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47632 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses
+system.iocache.overall_misses::total 47632 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146446932 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 146446932 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9011912160 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 9011912160 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 9158359092 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 9158359092 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 9158359092 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 9158359092 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160557.554336 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 160557.554336 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191831.809932 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 191831.809932 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 191233.652285 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 191233.652285 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 51554 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160577.776316 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 160577.776316 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192891.955479 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 192891.955479 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192273.242610 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 192273.242610 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192273.242610 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 192273.242610 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 57584 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 7256 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 7533 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 7.105017 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 7.644232 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98865990 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 98865990 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6530591975 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 6530591975 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 6629457965 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 6629457965 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98991992 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 98991992 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6580127962 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 6580127962 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6679119954 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 6679119954 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6679119954 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 6679119954 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108524.687157 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 108524.687157 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139781.506314 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 139781.506314 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108543.850877 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 108543.850877 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140841.780009 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 140841.780009 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140223.378275 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 140223.378275 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140223.378275 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 140223.378275 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 447650408 # number of cpu cycles simulated
+system.cpu.numCycles 447871414 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 86252473 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 86252473 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1112360 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 81440812 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 79250759 # Number of BTB hits
+system.cpu.BPredUnit.lookups 86248524 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 86248524 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1109719 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 81324372 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 79248318 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 27455337 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 426133339 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86252473 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79250759 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 163637491 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4749598 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 117040 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 62764723 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 36355 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 51011 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 275 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9043493 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 487667 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 3497 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 257661797 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.265027 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.418216 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27555812 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 426098303 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86248524 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79248318 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 163629889 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4731856 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 116400 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 62921622 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 35870 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 52533 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 368 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9034264 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 488269 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3183 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 257896503 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.261731 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.418044 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 94448905 36.66% 36.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1567012 0.61% 37.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71922195 27.91% 65.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 935544 0.36% 65.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1602565 0.62% 66.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2433530 0.94% 67.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1078893 0.42% 67.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1381790 0.54% 68.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 82291363 31.94% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 94692515 36.72% 36.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1566812 0.61% 37.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71928839 27.89% 65.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 936780 0.36% 65.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1600320 0.62% 66.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2427387 0.94% 67.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1078261 0.42% 67.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1378215 0.53% 68.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 82287374 31.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 257661797 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192678 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.951933 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31146269 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 60227421 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 159444515 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3244027 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3599565 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 838112106 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3599565 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33887749 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37302672 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 10848429 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159621170 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12402212 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834448767 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20383 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5810954 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4749020 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 7935 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 996003699 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1811552283 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1811551779 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964308271 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 31695421 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 457655 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 465271 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 28736743 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17096853 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10140380 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1243307 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 975146 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 828306292 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1248163 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 823283697 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 148415 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 22289625 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33892420 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 195525 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 257661797 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.195211 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.383294 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 257896503 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192574 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.951385 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31239529 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 60388203 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 159435692 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3249070 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3584009 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 838053376 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 983 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3584009 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33976924 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37367105 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 10941861 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 159620502 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 12406102 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 834408692 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19434 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5810292 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4754441 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 7847 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 995994396 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1811420133 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1811419405 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 728 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964426992 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 31567397 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 458567 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 466421 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 28739056 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17094362 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10134243 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1234841 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 965780 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 828292865 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1249354 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 823298492 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 149694 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 22192286 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 33736795 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 196434 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 257896503 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.192360 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.384089 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 71201357 27.63% 27.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15459797 6.00% 33.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10286150 3.99% 37.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7472850 2.90% 40.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75924697 29.47% 69.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3857138 1.50% 71.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72522119 28.15% 99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 785654 0.30% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 152035 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 71417814 27.69% 27.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15473003 6.00% 33.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10302554 3.99% 37.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7467952 2.90% 40.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75909427 29.43% 70.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3864522 1.50% 71.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72522780 28.12% 99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 788081 0.31% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 150370 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 257661797 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 257896503 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 364358 34.12% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 552545 51.74% 85.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 150975 14.14% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 363959 34.09% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 552647 51.76% 85.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 151055 14.15% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 312887 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795710532 96.65% 96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 310624 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 795733525 96.65% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 17869782 2.17% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9390496 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 17867181 2.17% 98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9387162 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 823283697 # Type of FU issued
-system.cpu.iq.rate 1.839122 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1067878 # FU busy when requested
+system.cpu.iq.FU_type_0::total 823298492 # Type of FU issued
+system.cpu.iq.rate 1.838247 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1067661 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1905576298 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 851854038 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 818789401 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 824038596 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1642479 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_inst_queue_reads 1905840686 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 851744345 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 818819585 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 303 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 346 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 824055392 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 137 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1644579 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3121524 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 22243 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11430 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1726583 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3112367 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 23963 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11499 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1716857 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1932632 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 11779 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1932401 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 11954 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3599565 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26096083 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2112224 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 829554455 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 302739 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17096853 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10140380 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 717341 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1614771 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11695 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11430 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 654771 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 594016 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1248787 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 821389011 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17449263 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1894685 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3584009 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 26166561 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2112396 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 829542219 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 307602 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17094362 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10134243 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 718774 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1614614 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11947 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11499 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 653687 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 591965 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1245652 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 821416518 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 17449825 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1881973 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26607287 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83217289 # Number of branches executed
-system.cpu.iew.exec_stores 9158024 # Number of stores executed
-system.cpu.iew.exec_rate 1.834889 # Inst execution rate
-system.cpu.iew.wb_sent 820925784 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 818789455 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 639951171 # num instructions producing a value
-system.cpu.iew.wb_consumers 1045809475 # num instructions consuming a value
+system.cpu.iew.exec_refs 26604955 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83223788 # Number of branches executed
+system.cpu.iew.exec_stores 9155130 # Number of stores executed
+system.cpu.iew.exec_rate 1.834045 # Inst execution rate
+system.cpu.iew.wb_sent 820955265 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 818819659 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 639977790 # num instructions producing a value
+system.cpu.iew.wb_consumers 1045837145 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.829082 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.828247 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.611929 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 23105687 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1052636 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1116569 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 254077625 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.173607 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.854352 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 23003299 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1052918 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1114308 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 254312494 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 3.171028 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.854625 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 82352974 32.41% 32.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11796837 4.64% 37.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3872314 1.52% 38.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74949594 29.50% 68.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2433419 0.96% 69.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1479159 0.58% 69.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 902635 0.36% 69.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70918587 27.91% 97.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5372106 2.11% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 82565112 32.47% 32.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11801317 4.64% 37.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3875007 1.52% 38.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74957575 29.47% 68.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2434316 0.96% 69.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1480794 0.58% 69.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 899910 0.35% 70.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70920339 27.89% 97.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5378124 2.11% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 254077625 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407917143 # Number of instructions committed
-system.cpu.commit.committedOps 806342485 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 254312494 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407963976 # Number of instructions committed
+system.cpu.commit.committedOps 806432115 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22389123 # Number of memory references committed
-system.cpu.commit.loads 13975326 # Number of loads committed
-system.cpu.commit.membars 473463 # Number of memory barriers committed
-system.cpu.commit.branches 82187715 # Number of branches committed
+system.cpu.commit.refs 22399378 # Number of memory references committed
+system.cpu.commit.loads 13981992 # Number of loads committed
+system.cpu.commit.membars 473513 # Number of memory barriers committed
+system.cpu.commit.branches 82199908 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735283087 # Number of committed integer instructions.
+system.cpu.commit.int_insts 735371295 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5372106 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5378124 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1078075497 # The number of ROB reads
-system.cpu.rob.rob_writes 1662514782 # The number of ROB writes
-system.cpu.timesIdled 1218897 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 189988611 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9817926834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407917143 # Number of Instructions Simulated
-system.cpu.committedOps 806342485 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 407917143 # Number of Instructions Simulated
-system.cpu.cpi 1.097405 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.097405 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.911240 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.911240 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1506960736 # number of integer regfile reads
-system.cpu.int_regfile_writes 976968921 # number of integer regfile writes
-system.cpu.fp_regfile_reads 54 # number of floating regfile reads
-system.cpu.misc_regfile_reads 264713842 # number of misc regfile reads
-system.cpu.misc_regfile_writes 402218 # number of misc regfile writes
-system.cpu.icache.replacements 1046081 # number of replacements
-system.cpu.icache.tagsinuse 510.992308 # Cycle average of tags in use
-system.cpu.icache.total_refs 7932749 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1046593 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7.579593 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 1078291467 # The number of ROB reads
+system.cpu.rob.rob_writes 1662473587 # The number of ROB writes
+system.cpu.timesIdled 1221266 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 189974911 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9825720160 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407963976 # Number of Instructions Simulated
+system.cpu.committedOps 806432115 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 407963976 # Number of Instructions Simulated
+system.cpu.cpi 1.097821 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.097821 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.910895 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.910895 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1507038080 # number of integer regfile reads
+system.cpu.int_regfile_writes 977032757 # number of integer regfile writes
+system.cpu.fp_regfile_reads 74 # number of floating regfile reads
+system.cpu.misc_regfile_reads 264726295 # number of misc regfile reads
+system.cpu.misc_regfile_writes 402502 # number of misc regfile writes
+system.cpu.icache.replacements 1052817 # number of replacements
+system.cpu.icache.tagsinuse 510.984184 # Cycle average of tags in use
+system.cpu.icache.total_refs 7916649 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1053329 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 7.515837 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 55992087000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.992308 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.998032 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.998032 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 7932749 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7932749 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7932749 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7932749 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7932749 # number of overall hits
-system.cpu.icache.overall_hits::total 7932749 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1110744 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1110744 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1110744 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1110744 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1110744 # number of overall misses
-system.cpu.icache.overall_misses::total 1110744 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 15035266490 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 15035266490 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 15035266490 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 15035266490 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 15035266490 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 15035266490 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 9043493 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 9043493 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 9043493 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 9043493 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 9043493 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 9043493 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122822 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.122822 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.122822 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.122822 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.122822 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.122822 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13536.212206 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13536.212206 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13536.212206 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13536.212206 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 5934 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 510.984184 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.998016 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.998016 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 7916649 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 7916649 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 7916649 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 7916649 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 7916649 # number of overall hits
+system.cpu.icache.overall_hits::total 7916649 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1117614 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1117614 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1117614 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1117614 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1117614 # number of overall misses
+system.cpu.icache.overall_misses::total 1117614 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 15123913488 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 15123913488 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 15123913488 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 15123913488 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 15123913488 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 15123913488 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 9034263 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 9034263 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 9034263 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 9034263 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 9034263 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 9034263 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123708 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.123708 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.123708 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.123708 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.123708 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.123708 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13532.322866 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13532.322866 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13532.322866 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13532.322866 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13532.322866 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13532.322866 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 274 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 267 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 21.656934 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 25.737828 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61679 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 61679 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 61679 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 61679 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 61679 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 61679 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1049065 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1049065 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1049065 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1049065 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1049065 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1049065 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12388903990 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12388903990 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12388903990 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12388903990 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12388903990 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12388903990 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116002 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.116002 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.116002 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11809.472235 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11809.472235 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11809.472235 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11809.472235 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11809.472235 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11809.472235 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61803 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 61803 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 61803 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 61803 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 61803 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 61803 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1055811 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1055811 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1055811 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1055811 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1055811 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1055811 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12467027488 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 12467027488 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12467027488 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 12467027488 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12467027488 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 12467027488 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116867 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.116867 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.116867 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.010608 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.010608 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.010608 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.010608 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.010608 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.010608 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements 9937 # number of replacements
-system.cpu.itb_walker_cache.tagsinuse 6.006130 # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs 26086 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs 9951 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs 2.621445 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5106893785000 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.006130 # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375383 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total 0.375383 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26219 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 26219 # number of ReadReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26222 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 26222 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26222 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 26222 # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10817 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 10817 # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10817 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 10817 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10817 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 10817 # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116537500 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116537500 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116537500 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total 116537500 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116537500 # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total 116537500 # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37036 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 37036 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37039 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 37039 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37039 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 37039 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.292067 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.292067 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.292044 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total 0.292044 # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.292044 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total 0.292044 # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10773.550892 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10773.550892 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10773.550892 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10773.550892 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10773.550892 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10773.550892 # average overall miss latency
+system.cpu.itb_walker_cache.replacements 9172 # number of replacements
+system.cpu.itb_walker_cache.tagsinuse 6.015892 # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs 26549 # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs 9185 # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs 2.890474 # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5104159763000 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.015892 # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375993 # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total 0.375993 # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26666 # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total 26666 # number of ReadReq hits
+system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
+system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26668 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total 26668 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26668 # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total 26668 # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10048 # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total 10048 # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10048 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total 10048 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10048 # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total 10048 # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 111185500 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total 111185500 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 111185500 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total 111185500 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 111185500 # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total 111185500 # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36714 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total 36714 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
+system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36716 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total 36716 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36716 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total 36716 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.273683 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.273683 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.273668 # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total 0.273668 # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.273668 # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total 0.273668 # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11065.435908 # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11065.435908 # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11065.435908 # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11065.435908 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11065.435908 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11065.435908 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10817 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10817 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10817 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total 10817 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10817 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 10817 # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94903500 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94903500 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94903500 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94903500 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94903500 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94903500 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.292067 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.292067 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.292044 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.292044 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8773.550892 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks 1844 # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total 1844 # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10048 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10048 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10048 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total 10048 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10048 # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total 10048 # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 91089500 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 91089500 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 91089500 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 91089500 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 91089500 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 91089500 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.273683 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.273683 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.273668 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.273668 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.273668 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.273668 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9065.435908 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9065.435908 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9065.435908 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements 113923 # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse 12.921985 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 130116 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs 113938 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs 1.141990 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5100448688500 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.921985 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.807624 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total 0.807624 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130138 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 130138 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130138 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 130138 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130138 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 130138 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 114896 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 114896 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 114896 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 114896 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 114896 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 114896 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1427497500 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1427497500 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1427497500 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total 1427497500 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1427497500 # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total 1427497500 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245034 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 245034 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245034 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 245034 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245034 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 245034 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.468898 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.468898 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.468898 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.468898 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.468898 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.468898 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.257589 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.257589 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.257589 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.257589 # average overall miss latency
+system.cpu.dtb_walker_cache.replacements 111590 # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse 11.995325 # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs 130038 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs 111605 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs 1.165163 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5100439779500 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.995325 # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749708 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total 0.749708 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130049 # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total 130049 # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130049 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total 130049 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130049 # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total 130049 # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 112651 # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total 112651 # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 112651 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total 112651 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 112651 # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total 112651 # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1400311500 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1400311500 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1400311500 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total 1400311500 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1400311500 # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total 1400311500 # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 242700 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total 242700 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 242700 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total 242700 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 242700 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 242700 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.464157 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.464157 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.464157 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total 0.464157 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.464157 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total 0.464157 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12430.528801 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12430.528801 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12430.528801 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12430.528801 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12430.528801 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12430.528801 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 35555 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 35555 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 114896 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 114896 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 114896 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total 114896 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 114896 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 114896 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1197705500 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1197705500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1197705500 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.468898 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.468898 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.468898 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10424.257589 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks 35078 # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total 35078 # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 112651 # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 112651 # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 112651 # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total 112651 # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 112651 # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total 112651 # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1175009500 # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1175009500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1175009500 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.464157 # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.464157 # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.464157 # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10430.528801 # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10430.528801 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10430.528801 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1657882 # number of replacements
-system.cpu.dcache.tagsinuse 511.998105 # Cycle average of tags in use
-system.cpu.dcache.total_refs 19102953 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1658394 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 11.518947 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 27815000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.998105 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 11010989 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 11010989 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 8086819 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8086819 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 19097808 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 19097808 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 19097808 # number of overall hits
-system.cpu.dcache.overall_hits::total 19097808 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2233987 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2233987 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 317747 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 317747 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2551734 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2551734 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2551734 # number of overall misses
-system.cpu.dcache.overall_misses::total 2551734 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 31818004500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 31818004500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 9564256493 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 9564256493 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 41382260993 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 41382260993 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 41382260993 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 41382260993 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 13244976 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13244976 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 8404566 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8404566 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 21649542 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21649542 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 21649542 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21649542 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168667 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.168667 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037806 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.037806 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.117865 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.117865 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.117865 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.117865 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14242.699040 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14242.699040 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30100.225944 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30100.225944 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16217.309874 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16217.309874 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 396326 # number of cycles access was blocked
+system.cpu.dcache.replacements 1661569 # number of replacements
+system.cpu.dcache.tagsinuse 511.994847 # Cycle average of tags in use
+system.cpu.dcache.total_refs 19098471 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1662081 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 11.490698 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.994847 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 11004011 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 11004011 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 8089317 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 8089317 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 19093328 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 19093328 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 19093328 # number of overall hits
+system.cpu.dcache.overall_hits::total 19093328 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2239016 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2239016 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 318822 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 318822 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2557838 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2557838 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2557838 # number of overall misses
+system.cpu.dcache.overall_misses::total 2557838 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 31972900500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 31972900500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 9624592994 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 9624592994 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 41597493494 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 41597493494 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 41597493494 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 41597493494 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 13243027 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13243027 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 8408139 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 8408139 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 21651166 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 21651166 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 21651166 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 21651166 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169071 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.169071 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037918 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.037918 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.118139 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.118139 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.118139 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.118139 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14279.889246 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14279.889246 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30187.982617 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30187.982617 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16262.755301 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16262.755301 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16262.755301 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16262.755301 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 404649 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 42512 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 42429 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.322685 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.537085 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1559612 # number of writebacks
-system.cpu.dcache.writebacks::total 1559612 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862458 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 862458 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26265 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 26265 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 888723 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 888723 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 888723 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 888723 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371529 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1371529 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291482 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 291482 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1663011 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1663011 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1663011 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1663011 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17298488500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 17298488500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8726866493 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8726866493 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26025354993 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 26025354993 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26025354993 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 26025354993 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296677500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296677500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469996000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469996000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766673500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766673500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103551 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103551 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034681 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034681 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076815 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.076815 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076815 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.076815 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12612.557591 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12612.557591 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29939.641189 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29939.641189 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15649.538694 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15649.538694 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15649.538694 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15649.538694 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 1562908 # number of writebacks
+system.cpu.dcache.writebacks::total 1562908 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864676 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 864676 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26384 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 26384 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 891060 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 891060 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 891060 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 891060 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1374340 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1374340 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292438 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 292438 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1666778 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1666778 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1666778 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1666778 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17366494500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 17366494500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8784809994 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8784809994 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26151304494 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 26151304494 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26151304494 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 26151304494 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97298090500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97298090500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2473113000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2473113000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99771203500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 99771203500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103778 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103778 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034780 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034780 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076983 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.076983 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076983 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.076983 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12636.243215 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12636.243215 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30039.905874 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30039.905874 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15689.734622 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15689.734622 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15689.734622 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15689.734622 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 113761 # number of replacements
-system.cpu.l2cache.tagsinuse 64829.122340 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3920006 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 178006 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 22.021763 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 114048 # number of replacements
+system.cpu.l2cache.tagsinuse 64828.781789 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3943145 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 178083 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 22.142175 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 50212.838916 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 12.458733 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.160012 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 3172.410316 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 11431.254363 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.766187 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000190 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 50215.061729 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker 7.199221 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133392 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 3209.208803 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 11397.178643 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.766221 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000110 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.048407 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.174427 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.989214 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 105856 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7867 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 1029751 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1333713 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2477187 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1597039 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1597039 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 343 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 343 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 153883 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 153883 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 105856 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 7867 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 1029751 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1487596 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2631070 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 105856 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 7867 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 1029751 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1487596 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2631070 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 48 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 16802 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 36729 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 53586 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 3829 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 3829 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133517 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133517 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 48 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 16802 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 170246 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 187103 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 48 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 16802 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 170246 # number of overall misses
-system.cpu.l2cache.overall_misses::total 187103 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3370500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 483000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 989785000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2361474498 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 3355112998 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17665999 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 17665999 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6803302500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6803302500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3370500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 483000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 989785000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 9164776998 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 10158415498 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3370500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 483000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 989785000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 9164776998 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 10158415498 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 105904 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7874 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1046553 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1370442 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2530773 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1597039 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1597039 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4172 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 4172 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 287400 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 287400 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 105904 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 7874 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 1046553 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1657842 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2818173 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 105904 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 7874 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1046553 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1657842 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2818173 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000453 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000889 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016055 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026801 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.021174 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.917785 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.917785 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464569 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.464569 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000453 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000889 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016055 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.102691 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.066392 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000453 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000889 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016055 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.102691 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.066392 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70218.750000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58908.760862 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64294.549212 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 62611.745568 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4613.737007 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4613.737007 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50954.578818 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50954.578818 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70218.750000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58908.760862 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53832.554057 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 54293.172734 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70218.750000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58908.760862 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53832.554057 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 54293.172734 # average overall miss latency
+system.cpu.l2cache.occ_percent::cpu.inst 0.048969 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.173907 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.989209 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 103777 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7654 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 1036447 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1336423 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2484301 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1599830 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1599830 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 336 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 336 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 154761 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 154761 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 103777 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 7654 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 1036447 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1491184 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2639062 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 103777 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 7654 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 1036447 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1491184 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2639062 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 49 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 16836 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 36777 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 53668 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 3876 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 3876 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133549 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133549 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 49 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 16836 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 170326 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 187217 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 49 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 16836 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 170326 # number of overall misses
+system.cpu.l2cache.overall_misses::total 187217 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3729000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 431500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 993413500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2399373497 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 3396947497 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17629499 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 17629499 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6849048000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6849048000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3729000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 431500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 993413500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 9248421497 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 10245995497 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3729000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 431500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 993413500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 9248421497 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 10245995497 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103826 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7660 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 1053283 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1373200 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 2537969 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1599830 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1599830 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4212 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 4212 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 288310 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 288310 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103826 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 7660 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 1053283 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1661510 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2826279 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103826 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 7660 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1053283 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1661510 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2826279 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000472 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000783 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015984 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.021146 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.920228 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.920228 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463213 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.463213 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000472 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000783 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015984 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.102513 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.066242 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000472 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000783 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015984 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.102513 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.066242 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 76102.040816 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 71916.666667 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 59005.315990 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65241.142480 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 63295.585768 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4548.374355 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4548.374355 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51284.906663 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51284.906663 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 76102.040816 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 71916.666667 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59005.315990 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54298.354315 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54727.911979 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 76102.040816 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 71916.666667 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59005.315990 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54298.354315 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54727.911979 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 103003 # number of writebacks
-system.cpu.l2cache.writebacks::total 103003 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 103255 # number of writebacks
+system.cpu.l2cache.writebacks::total 103255 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16801 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36728 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 53584 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3829 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 3829 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133517 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 133517 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 16801 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 170245 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 187101 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 16801 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 170245 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 187101 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2762092 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 393014 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 777293164 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1899198022 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2679646292 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39323307 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39323307 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5078674654 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5078674654 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2762092 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 393014 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 777293164 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6977872676 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 7758320946 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2762092 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 393014 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 777293164 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6977872676 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 7758320946 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187395500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187395500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308293000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308293000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495688500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495688500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000453 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000889 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016054 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026800 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021173 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.917785 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.917785 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464569 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464569 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000453 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000889 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016054 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102691 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.066391 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000453 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000889 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016054 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102691 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.066391 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 57543.583333 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46264.696387 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51709.813276 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50008.328830 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10269.863411 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10269.863411 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38037.663024 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38037.663024 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 57543.583333 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46264.696387 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40987.240013 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41465.951256 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 57543.583333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46264.696387 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40987.240013 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41465.951256 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16835 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36776 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 53666 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3876 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 3876 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133549 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133549 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 49 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 16835 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 170325 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 187215 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 49 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 16835 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 170325 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 187215 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3103591 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 354011 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 780431313 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936463138 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2720352053 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39875852 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39875852 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5124017116 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5124017116 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3103591 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 354011 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 780431313 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7060480254 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 7844369169 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3103591 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 354011 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 780431313 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7060480254 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 7844369169 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89188692000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89188692000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2310744000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2310744000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91499436000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91499436000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000472 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000783 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026781 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021145 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.920228 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.920228 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463213 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463213 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000472 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000783 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102512 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.066241 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000472 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000783 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102512 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.066241 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 63338.591837 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 59001.833333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46357.666350 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52655.621547 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50690.419502 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10287.887513 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10287.887513 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38368.068020 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38368.068020 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 63338.591837 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 59001.833333 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46357.666350 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41452.988428 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41900.324061 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 63338.591837 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 59001.833333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46357.666350 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41452.988428 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41900.324061 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/gem5/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 18:59:47
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:34:09
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 164568389500 # Number of ticks simulated
final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 195675 # Simulator instruction rate (inst/s)
-host_op_rate 206765 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56489453 # Simulator tick rate (ticks/s)
-host_mem_usage 277972 # Number of bytes of host memory used
-host_seconds 2913.26 # Real time elapsed on the host
+host_inst_rate 61098 # Simulator instruction rate (inst/s)
+host_op_rate 64561 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17638362 # Simulator tick rate (ticks/s)
+host_mem_usage 233000 # Number of bytes of host memory used
+host_seconds 9330.14 # Real time elapsed on the host
sim_insts 570052720 # Number of instructions simulated
sim_ops 602360926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 164568371500 # Total gap between requests
+system.physmem.totGap 164568372500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 953340995 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1657962995 # Sum of mem lat for all requests
+system.physmem.totQLat 953339495 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1657961495 # Sum of mem lat for all requests
system.physmem.totBusLat 109328000 # Total cycles spent in databus access
system.physmem.totBankLat 595294000 # Total cycles spent in bank access
-system.physmem.avgQLat 34880.03 # Average queueing delay per request
+system.physmem.avgQLat 34879.98 # Average queueing delay per request
system.physmem.avgBankLat 21780.11 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 60660.14 # Average memory access latency
+system.physmem.avgMemAccLat 60660.09 # Average memory access latency
system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s
system.physmem.writeRowHits 1091 # Number of row buffer hits during writes
system.physmem.readRowHitRate 65.00 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 43.00 # Row buffer hit rate for writes
-system.physmem.avgGap 5509671.28 # Average gap between requests
+system.physmem.avgGap 5509671.31 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1427560 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1061 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 68501011 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 68501012 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 666829693 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85146783 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 48298586 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 129620938 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 13095502 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 119329475 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.BlockedCycles 119329476 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 67084220 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 755001 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 328178874 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 67084221 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 755002 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 328178875 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.165282 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.193965 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 198558185 60.50% 60.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 198558186 60.50% 60.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 20911289 6.37% 66.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 4967188 1.51% 68.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 14345258 4.37% 72.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 328178874 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 328178875 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.258697 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.025996 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 92947684 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96199178 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 96199179 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 107899614 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 20406722 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 10725676 # Number of cycles decode is squashing
system.cpu.rename.IdleCycles 107135136 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 14450172 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 44143 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 114043084 # Number of cycles rename is running
+system.cpu.rename.RunCycles 114043085 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 81780663 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 694816427 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 694816428 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 59310091 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 20339427 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 721301804 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3230529001 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3230528873 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 721301805 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3230529005 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3230528877 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 93882615 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 93882616 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2064 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2020 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 170675831 # count of insts added to the skid buffer
system.cpu.iq.iqSquashedInstsExamined 77447824 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 193234107 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 328178874 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 328178875 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.967223 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.725262 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 68164683 20.77% 20.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 68164684 20.77% 20.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 85309693 25.99% 46.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 75934594 23.14% 69.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 40814180 12.44% 82.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 328178874 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 328178875 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 216945 5.75% 5.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available
system.cpu.iq.rate 1.961498 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3772110 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005843 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1624523748 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 1624523749 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 757451010 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 637563052 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iew.iewBlockCycles 798492 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 92069 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 679994152 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 690727 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 690728 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 172202980 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 80458110 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1965 # Number of dispatched non-speculative instructions
system.cpu.rob.rob_reads 977035801 # The number of ROB reads
system.cpu.rob.rob_writes 1370761733 # The number of ROB writes
system.cpu.timesIdled 41126 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 957906 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 957905 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 570052720 # Number of Instructions Simulated
system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated
system.cpu.icache.demand_hits::total 67083066 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 67083066 # number of overall hits
system.cpu.icache.overall_hits::total 67083066 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses
-system.cpu.icache.overall_misses::total 1154 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 51351999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 51351999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 51351999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 51351999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 51351999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 51351999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 67084220 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 67084220 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 67084220 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 67084220 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 67084220 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 67084220 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 1155 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1155 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1155 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1155 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1155 # number of overall misses
+system.cpu.icache.overall_misses::total 1155 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 51421999 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 51421999 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 51421999 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 51421999 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 51421999 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 51421999 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 67084221 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 67084221 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 67084221 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 67084221 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 67084221 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 67084221 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44499.132582 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 44499.132582 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 44499.132582 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 44499.132582 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44521.211255 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 44521.211255 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 44521.211255 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 44521.211255 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 334 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 335 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 335 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 335 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 335 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 335 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38657999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 38657999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38657999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 38657999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38657999 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 38657999 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38656999 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 38656999 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38656999 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 38656999 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38656999 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 38656999 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47143.901220 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47143.901220 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47142.681707 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47142.681707 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 440681 # number of replacements
-system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use
-system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 444777 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 444.191033 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 320845000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4091.500678 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.998902 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.998902 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 131517978 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 131517978 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 66044747 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 66044747 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 1676 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 1676 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 197562725 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 197562725 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 197562725 # number of overall hits
-system.cpu.dcache.overall_hits::total 197562725 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 342017 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 342017 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3372784 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3372784 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses
-system.cpu.dcache.overall_misses::total 3714801 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159651000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5159651000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250551202 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 40250551202 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 45410202202 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 45410202202 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 45410202202 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 45410202202 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 131859995 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 131859995 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1698 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.018456 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.018456 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.018456 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.948944 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.948944 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.924972 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.924972 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12224.127807 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12224.127807 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks
-system.cpu.dcache.writebacks::total 421636 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060483756 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060483756 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.145796 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.629975 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2559 # number of replacements
-system.cpu.l2cache.tagsinuse 22365.188889 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 22365.188888 # Cycle average of tags in use
system.cpu.l2cache.total_refs 517231 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 24170 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.399710 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20763.498620 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 646.825200 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 646.825199 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 954.865069 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.633652 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.019740 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 739 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 26604 # number of overall misses
system.cpu.l2cache.overall_misses::total 27343 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37001500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 728778000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 765779500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1545376000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 1545376000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 37001500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37000500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 728777500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 765778000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1545376500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1545376500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 37000500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2274154000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 2311155500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 37001500 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total 2311154500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 37000500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2274154000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 2311155500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 2311154500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 197619 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 198439 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.901220 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059814 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.061362 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50069.688769 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151387.203988 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 137903.745723 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70921.340064 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70921.340064 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50069.688769 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50068.335589 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151387.100125 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 137903.475599 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70921.363011 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70921.363011 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50068.335589 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 84524.576674 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50069.688769 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 84524.540102 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50068.335589 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 84524.576674 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 84524.540102 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 736 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26596 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27332 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27342673 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668140562 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695483235 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273790796 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273790796 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27342673 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941931358 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 1969274031 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27342673 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941931358 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 1969274031 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27342173 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668139562 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695481735 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273791296 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273791296 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27342173 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941930858 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 1969273031 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27342173 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941930858 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 1969273031 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024320 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027928 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061338 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37150.370924 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139022.172701 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125493.185673 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.585865 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.585865 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37150.370924 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37150.370924 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37149.691576 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139021.964628 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125492.915013 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.608811 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.608811 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37149.691576 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73015.899308 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72050.088943 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37149.691576 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.899308 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.088943 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 440681 # number of replacements
+system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use
+system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 444777 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 444.191033 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 320845000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4091.500678 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.998902 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.998902 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 131517978 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 131517978 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 66044747 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 66044747 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 1676 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 1676 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 197562725 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 197562725 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 197562725 # number of overall hits
+system.cpu.dcache.overall_hits::total 197562725 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 342017 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 342017 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3372784 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3372784 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses
+system.cpu.dcache.overall_misses::total 3714801 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159649500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5159649500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250552202 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 40250552202 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 45410201702 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 45410201702 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 45410201702 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 45410201702 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 131859995 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 131859995 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1698 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.018456 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.018456 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.018456 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.944558 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.944558 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.925268 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.925268 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12224.127673 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12224.127673 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks
+system.cpu.dcache.writebacks::total 421636 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060484256 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060484256 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.143266 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.143266 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.631998 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.631998 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip
+executable=/gem5/dist/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:11:57
-gem5 started Oct 30 2012 14:00:44
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:16:54
+gem5 started Jan 4 2013 22:00:02
+gem5 executing on u200540
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 387281648500 because target called exit()
+Exiting @ tick 387279743500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.387282 # Number of seconds simulated
-sim_ticks 387281648500 # Number of ticks simulated
-final_tick 387281648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.387280 # Number of seconds simulated
+sim_ticks 387279743500 # Number of ticks simulated
+final_tick 387279743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 171377 # Simulator instruction rate (inst/s)
-host_op_rate 171918 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47367883 # Simulator tick rate (ticks/s)
-host_mem_usage 224920 # Number of bytes of host memory used
-host_seconds 8176.04 # Real time elapsed on the host
+host_inst_rate 70741 # Simulator instruction rate (inst/s)
+host_op_rate 70964 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19552386 # Simulator tick rate (ticks/s)
+host_mem_usage 225936 # Number of bytes of host memory used
+host_seconds 19807.29 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 76608 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1678464 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 76608 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 76608 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 76416 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1678400 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1754816 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 76416 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 76416 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory
system.physmem.bytes_written::total 162112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1197 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26226 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 1194 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26225 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27419 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 197810 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4333962 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4531772 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 197810 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 197810 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 418589 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 418589 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 418589 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 197810 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4333962 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4950361 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 27424 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 197315 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 4333818 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4531133 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 197315 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 197315 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 418591 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 418591 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 418591 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 197315 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4333818 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4949724 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27420 # Total number of read requests seen
system.physmem.writeReqs 2533 # Total number of write requests seen
-system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1755072 # Total number of bytes read from memory
+system.physmem.cpureqs 29953 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1754816 # Total number of bytes read from memory
system.physmem.bytesWritten 162112 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 1754816 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1698 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1721 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1715 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1714 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1805 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1769 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1697 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1667 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1745 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1755 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1712 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1621 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 387281620500 # Total gap between requests
+system.physmem.totGap 387279715500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 27424 # Categorize read packet sizes
+system.physmem.readPktSize::6 27420 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 8242 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 13042 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5223 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 13029 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5215 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 916 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 722664308 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1404176308 # Sum of mem lat for all requests
-system.physmem.totBusLat 109696000 # Total cycles spent in databus access
-system.physmem.totBankLat 571816000 # Total cycles spent in bank access
-system.physmem.avgQLat 26351.53 # Average queueing delay per request
-system.physmem.avgBankLat 20850.93 # Average bank access latency per request
+system.physmem.totQLat 724473296 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1405549296 # Sum of mem lat for all requests
+system.physmem.totBusLat 109680000 # Total cycles spent in databus access
+system.physmem.totBankLat 571396000 # Total cycles spent in bank access
+system.physmem.avgQLat 26421.35 # Average queueing delay per request
+system.physmem.avgBankLat 20838.66 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 51202.46 # Average memory access latency
+system.physmem.avgMemAccLat 51260.00 # Average memory access latency
system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 17.43 # Average write queue length over time
-system.physmem.readRowHits 18322 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1102 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 43.51 # Row buffer hit rate for writes
-system.physmem.avgGap 12927917.36 # Average gap between requests
+system.physmem.avgWrQLen 17.06 # Average write queue length over time
+system.physmem.readRowHits 18324 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1098 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 66.83 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 43.35 # Row buffer hit rate for writes
+system.physmem.avgGap 12929580.19 # Average gap between requests
system.cpu.workload.num_syscalls 49 # Number of system calls
-system.cpu.numCycles 774563298 # number of cpu cycles simulated
+system.cpu.numCycles 774559488 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 97756783 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 88046378 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 3616115 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 65822232 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 65492473 # Number of BTB hits
+system.cpu.BPredUnit.lookups 97757265 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 88048400 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 3615880 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 65812942 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 65493412 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1334 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 164852368 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1642212446 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 97756783 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 65493807 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 329195647 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 20823123 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 263322100 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2527 # Number of stall cycles due to pending traps
+system.cpu.BPredUnit.usedRAS 1346 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 164857001 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1642241879 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 97757265 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 65494758 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 329201347 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 20830567 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 263300608 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2484 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 161933661 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 734964 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 774355546 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.126740 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.146682 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 161939590 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 736919 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 774350695 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.126792 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.146705 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 445159899 57.49% 57.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 74061304 9.56% 67.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 37898461 4.89% 71.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 9077519 1.17% 73.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 28105677 3.63% 76.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18773272 2.42% 79.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 11484924 1.48% 80.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3792333 0.49% 81.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 146002157 18.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 445149348 57.49% 57.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 74062635 9.56% 67.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 37899346 4.89% 71.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 9077460 1.17% 73.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 28106060 3.63% 76.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18772938 2.42% 79.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 11486101 1.48% 80.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3791039 0.49% 81.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 146005768 18.86% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 774355546 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.126209 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.120178 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 215883064 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 214466469 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 284208572 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 42814616 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 16982825 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 1636500589 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 16982825 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 239715972 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36727743 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52434063 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 302057850 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 126437093 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1625611071 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 30924044 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 73480825 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 3128707 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1356294088 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2746297990 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 2712224165 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 34073825 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 774350695 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.120227 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 215923264 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 214411776 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 284212483 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 42813992 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 16989180 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 1636523306 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 16989180 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 239767996 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36725834 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52426044 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 302047092 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 126394549 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1625641256 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 163 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 30927570 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 73422293 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 3124815 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1356325471 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2746325758 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 2712253189 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 34072569 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 111523649 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2645349 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2664178 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 271657434 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 436922066 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 179745095 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 254298230 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 83339884 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1512454597 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2610820 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1459325981 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 53748 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 109158045 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 130052751 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 367149 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 774355546 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.884568 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.432012 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 111555032 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2644888 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2664020 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 271706062 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 436927389 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 179744218 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 254493315 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 83217297 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1512489363 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2610612 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1459355655 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 53704 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 109193723 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 130058810 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 366941 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 774350695 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.884619 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.431536 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 145671235 18.81% 18.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 184692846 23.85% 42.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 209497548 27.05% 69.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 131299597 16.96% 86.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 70722781 9.13% 95.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 20304331 2.62% 98.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8026000 1.04% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3959195 0.51% 99.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 182013 0.02% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 145647727 18.81% 18.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 184570267 23.84% 42.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 209695290 27.08% 69.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 131219118 16.95% 86.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 70710319 9.13% 95.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 20417492 2.64% 98.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8005951 1.03% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3903236 0.50% 99.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 181295 0.02% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 774355546 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 774350695 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 90752 5.46% 5.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 95014 5.72% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1160014 69.81% 80.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 315922 19.01% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 116724 6.93% 6.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 95410 5.66% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1152580 68.43% 81.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 319525 18.97% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 866438962 59.37% 59.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 866464141 59.37% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2644873 0.18% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2644770 0.18% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 419117163 28.72% 88.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 171124983 11.73% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 419120072 28.72% 88.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 171126672 11.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1459325981 # Type of FU issued
-system.cpu.iq.rate 1.884063 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1661702 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 3676896998 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1615267495 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1443201042 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 17825960 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 9193607 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 8546616 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1451866721 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 9120962 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 215450617 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1459355655 # Type of FU issued
+system.cpu.iq.rate 1.884110 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1684239 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001154 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 3676971209 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1615339802 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1443231270 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 17828739 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 9193054 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 8547507 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1451917046 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 9122848 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 215321036 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 34409223 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 57798 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 244556 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 12896953 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 34414546 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 58846 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 246003 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 12896076 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 91608 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3349 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 91624 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 16982825 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3082295 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 247112 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1608751818 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 4125389 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 436922066 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 179745095 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2527727 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 148822 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1680 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 244556 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 2270064 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1474247 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3744311 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1454009970 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 416570645 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 5316011 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 16989180 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 3081240 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 246114 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1608786135 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 4123964 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 436927389 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 179744218 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2527628 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 148187 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1651 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 246003 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 2270880 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1473539 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3744419 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1454037467 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 416573795 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 5318188 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 93686401 # number of nop insts executed
-system.cpu.iew.exec_refs 587021920 # number of memory reference insts executed
-system.cpu.iew.exec_branches 89037548 # Number of branches executed
-system.cpu.iew.exec_stores 170451275 # Number of stores executed
-system.cpu.iew.exec_rate 1.877200 # Inst execution rate
-system.cpu.iew.wb_sent 1452636193 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1451747658 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1153420359 # num instructions producing a value
-system.cpu.iew.wb_consumers 1204679279 # num instructions consuming a value
+system.cpu.iew.exec_nop 93686160 # number of nop insts executed
+system.cpu.iew.exec_refs 587024674 # number of memory reference insts executed
+system.cpu.iew.exec_branches 89036390 # Number of branches executed
+system.cpu.iew.exec_stores 170450879 # Number of stores executed
+system.cpu.iew.exec_rate 1.877244 # Inst execution rate
+system.cpu.iew.wb_sent 1452666848 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1451778777 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1153445523 # num instructions producing a value
+system.cpu.iew.wb_consumers 1204705379 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.874279 # insts written-back per cycle
+system.cpu.iew.wb_rate 1.874328 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.957450 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 119133058 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 119167265 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 3616115 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 757373332 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.966696 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.509453 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 3615880 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 757361515 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.966727 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.509795 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 239955150 31.68% 31.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 275777678 36.41% 68.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 42556583 5.62% 73.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 54728215 7.23% 80.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 19718156 2.60% 83.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 13293088 1.76% 85.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 30577311 4.04% 89.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10491345 1.39% 90.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 70275806 9.28% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 240009654 31.69% 31.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 275743732 36.41% 68.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 42570119 5.62% 73.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 54687779 7.22% 80.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 19671272 2.60% 83.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13286277 1.75% 85.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 30573058 4.04% 89.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10535838 1.39% 90.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 70283786 9.28% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 757373332 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 757361515 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1485108088 # Number of instructions committed
system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions.
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 70275806 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 70283786 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2295688996 # The number of ROB reads
-system.cpu.rob.rob_writes 3234318218 # The number of ROB writes
-system.cpu.timesIdled 25993 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 207752 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2295703406 # The number of ROB reads
+system.cpu.rob.rob_writes 3234392884 # The number of ROB writes
+system.cpu.timesIdled 26078 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 208793 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1401188945 # Number of Instructions Simulated
system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated
-system.cpu.cpi 0.552790 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.552790 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.809005 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.809005 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1979115545 # number of integer regfile reads
-system.cpu.int_regfile_writes 1275157860 # number of integer regfile writes
-system.cpu.fp_regfile_reads 16963296 # number of floating regfile reads
-system.cpu.fp_regfile_writes 10491838 # number of floating regfile writes
-system.cpu.misc_regfile_reads 592677531 # number of misc regfile reads
+system.cpu.cpi 0.552787 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.552787 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.809014 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.809014 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1979140277 # number of integer regfile reads
+system.cpu.int_regfile_writes 1275189089 # number of integer regfile writes
+system.cpu.fp_regfile_reads 16965348 # number of floating regfile reads
+system.cpu.fp_regfile_writes 10491584 # number of floating regfile writes
+system.cpu.misc_regfile_reads 592679771 # number of misc regfile reads
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
-system.cpu.icache.replacements 190 # number of replacements
-system.cpu.icache.tagsinuse 1035.892325 # Cycle average of tags in use
-system.cpu.icache.total_refs 161931728 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1331 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 121661.703982 # Average number of references to valid blocks.
+system.cpu.icache.replacements 200 # number of replacements
+system.cpu.icache.tagsinuse 1035.695786 # Cycle average of tags in use
+system.cpu.icache.total_refs 161937647 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 121029.631540 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1035.892325 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.505807 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.505807 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 161931728 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 161931728 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 161931728 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 161931728 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 161931728 # number of overall hits
-system.cpu.icache.overall_hits::total 161931728 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1933 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1933 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1933 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1933 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1933 # number of overall misses
-system.cpu.icache.overall_misses::total 1933 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 80019500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 80019500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 80019500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 80019500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 80019500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 80019500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 161933661 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 161933661 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 161933661 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 161933661 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 161933661 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 161933661 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 1035.695786 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.505711 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.505711 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 161937647 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 161937647 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 161937647 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 161937647 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 161937647 # number of overall hits
+system.cpu.icache.overall_hits::total 161937647 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses
+system.cpu.icache.overall_misses::total 1943 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 81333500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 81333500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 81333500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 81333500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 81333500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 81333500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 161939590 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 161939590 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 161939590 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 161939590 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 161939590 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 161939590 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41396.533885 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 41396.533885 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 41396.533885 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 41396.533885 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 41396.533885 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 41396.533885 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41859.752959 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 41859.752959 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 41859.752959 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 41859.752959 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 41859.752959 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 41859.752959 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 32.250000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 601 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 601 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 601 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 601 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 601 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 601 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1332 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1332 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1332 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1332 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1332 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1332 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58461000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 58461000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58461000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 58461000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58461000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 58461000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59309500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 59309500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59309500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 59309500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59309500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 59309500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43889.639640 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43889.639640 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43889.639640 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 43889.639640 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43889.639640 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 43889.639640 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44293.876027 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44293.876027 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44293.876027 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 44293.876027 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44293.876027 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 44293.876027 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2556 # number of replacements
-system.cpu.l2cache.tagsinuse 22450.499541 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 550174 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 24271 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 22.667958 # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 22451.919806 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 550398 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 24266 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 22.681859 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20742.731551 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 1060.708507 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 647.059483 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.633018 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.032370 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.019747 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.685135 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 134 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 196304 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 196438 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 443776 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 443776 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 240583 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 240583 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 134 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 436887 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 437021 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 134 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 436887 # number of overall hits
-system.cpu.l2cache.overall_hits::total 437021 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 1198 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 4435 # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::writebacks 20744.013315 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1060.728994 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 647.177496 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.633057 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.032371 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.019750 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.685178 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 144 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 196423 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 196567 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 443928 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 443928 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 240651 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 240651 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 144 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 437074 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 437218 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 144 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 437074 # number of overall hits
+system.cpu.l2cache.overall_hits::total 437218 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 1195 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 4438 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 5633 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 21791 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 21791 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 1198 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 26226 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 27424 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 1198 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 26226 # number of overall misses
-system.cpu.l2cache.overall_misses::total 27424 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55773000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 468174000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 523947000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1550343500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 1550343500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 55773000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 2018517500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 2074290500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 55773000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 2018517500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 2074290500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1332 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 200739 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 202071 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 443776 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 443776 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 262374 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 262374 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 1332 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 463113 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 464445 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1332 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 463113 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 464445 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.899399 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022093 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.027876 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083053 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.083053 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.899399 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.056630 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.059047 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.899399 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.056630 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.059047 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46555.091820 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 105563.472379 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 93013.846973 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71146.046533 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71146.046533 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46555.091820 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76966.273927 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75637.780776 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46555.091820 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76966.273927 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75637.780776 # average overall miss latency
+system.cpu.l2cache.ReadExReq_misses::cpu.data 21787 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 21787 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 1195 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 26225 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 27420 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 1195 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 26225 # number of overall misses
+system.cpu.l2cache.overall_misses::total 27420 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 56513500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 468623000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 525136500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1550357500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1550357500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 56513500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 2018980500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 2075494000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 56513500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 2018980500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 2075494000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 1339 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 200861 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 202200 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 443928 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 443928 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 262438 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 262438 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 1339 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 463299 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 464638 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1339 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 463299 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 464638 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.892457 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022095 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.027859 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083018 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.083018 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.892457 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.056605 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.059014 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.892457 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.056605 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.059014 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47291.631799 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 105593.285264 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 93225.013314 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71159.751228 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71159.751228 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47291.631799 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76986.863680 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75692.706054 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47291.631799 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76986.863680 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75692.706054 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks
system.cpu.l2cache.writebacks::total 2533 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1198 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4435 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1195 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4438 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5633 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 21791 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1198 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 26226 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 27424 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1198 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 26226 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 27424 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40693954 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 412667734 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 453361688 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1276994111 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1276994111 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40693954 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1689661845 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 1730355799 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40693954 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1689661845 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 1730355799 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.899399 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022093 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027876 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083053 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083053 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899399 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056630 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.059047 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899399 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056630 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.059047 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33968.242070 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93047.967080 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80483.168472 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58601.904961 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58601.904961 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33968.242070 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64426.974949 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63096.404573 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33968.242070 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64426.974949 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63096.404573 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21787 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 21787 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1195 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 26225 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 27420 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1195 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 26225 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 27420 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41471942 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413076738 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 454548680 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1277066596 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1277066596 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41471942 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1690143334 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 1731615276 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41471942 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1690143334 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 1731615276 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.892457 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022095 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027859 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083018 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083018 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.892457 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056605 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.059014 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.892457 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056605 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.059014 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34704.553975 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93077.228031 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80693.889579 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58615.991004 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58615.991004 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34704.553975 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64447.791573 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63151.541794 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34704.553975 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64447.791573 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63151.541794 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 459017 # number of replacements
-system.cpu.dcache.tagsinuse 4093.828969 # Cycle average of tags in use
-system.cpu.dcache.total_refs 365038721 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 463113 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 788.228188 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 459203 # number of replacements
+system.cpu.dcache.tagsinuse 4093.828957 # Cycle average of tags in use
+system.cpu.dcache.total_refs 365170885 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 463299 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 788.197007 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 342772000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4093.828969 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 4093.828957 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999470 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999470 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 200081459 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 200081459 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 164955943 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 164955943 # number of WriteReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 200214093 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 200214093 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 164955473 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 164955473 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 365037402 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 365037402 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 365037402 # number of overall hits
-system.cpu.dcache.overall_hits::total 365037402 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 927524 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 927524 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1890873 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1890873 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 365169566 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 365169566 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 365169566 # number of overall hits
+system.cpu.dcache.overall_hits::total 365169566 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 927691 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 927691 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1891343 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1891343 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 2818397 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2818397 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2818397 # number of overall misses
-system.cpu.dcache.overall_misses::total 2818397 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988914500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 14988914500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 31918196457 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 31918196457 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 2819034 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2819034 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2819034 # number of overall misses
+system.cpu.dcache.overall_misses::total 2819034 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988091500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 14988091500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 31927965942 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 31927965942 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 46907110957 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 46907110957 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 46907110957 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 46907110957 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 201008983 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 201008983 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 46916057442 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 46916057442 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 46916057442 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 46916057442 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 201141784 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 201141784 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 367855799 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 367855799 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 367855799 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 367855799 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004614 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004614 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011333 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.011333 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 367988600 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 367988600 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 367988600 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 367988600 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004612 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004612 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.007662 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.007662 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.007662 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.007662 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16160.136557 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16160.136557 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16880.137617 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16880.137617 # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.007661 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.007661 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.007661 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.007661 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16156.340312 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16156.340312 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16881.108261 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16881.108261 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16643.187939 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16643.187939 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 574305 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 10 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 35651 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.109085 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16642.600778 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16642.600778 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 573681 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 35664 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.085717 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 443776 # number of writebacks
-system.cpu.dcache.writebacks::total 443776 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726784 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 726784 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628507 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1628507 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2355291 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2355291 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2355291 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2355291 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200740 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 200740 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262366 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 262366 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 443928 # number of writebacks
+system.cpu.dcache.writebacks::total 443928 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726830 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 726830 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628912 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1628912 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2355742 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2355742 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2355742 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2355742 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200861 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 200861 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262431 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 262431 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 463106 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 463106 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 463106 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 463106 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2634282500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2634282500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319277500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319277500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 463292 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 463292 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 463292 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 463292 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2635998000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2635998000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319921000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319921000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6953560000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6953560000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6953560000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6953560000 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6955919000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6955919000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6955919000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6955919000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001572 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001572 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13122.857926 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13122.857926 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16462.794341 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16462.794341 # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13123.493361 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13123.493361 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16461.168841 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16461.168841 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/gem5/dist/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:30
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 4 2013 21:20:54
+gem5 started Jan 4 2013 22:11:32
+gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 607445544000 # Number of ticks simulated
final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 57635 # Simulator instruction rate (inst/s)
-host_op_rate 106195 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39782943 # Simulator tick rate (ticks/s)
-host_mem_usage 279268 # Number of bytes of host memory used
-host_seconds 15268.99 # Real time elapsed on the host
+host_inst_rate 35384 # Simulator instruction rate (inst/s)
+host_op_rate 65197 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24424271 # Simulator tick rate (ticks/s)
+host_mem_usage 239876 # Number of bytes of host memory used
+host_seconds 24870.57 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 607445529000 # Total gap between requests
+system.physmem.totGap 607445530000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 68456169 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 822256169 # Sum of mem lat for all requests
+system.physmem.totQLat 68456669 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 822256669 # Sum of mem lat for all requests
system.physmem.totBusLat 109436000 # Total cycles spent in databus access
system.physmem.totBankLat 644364000 # Total cycles spent in bank access
-system.physmem.avgQLat 2502.14 # Average queueing delay per request
+system.physmem.avgQLat 2502.16 # Average queueing delay per request
system.physmem.avgBankLat 23552.18 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30054.32 # Average memory access latency
+system.physmem.avgMemAccLat 30054.34 # Average memory access latency
system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s
system.physmem.writeRowHits 1084 # Number of row buffer hits during writes
system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes
-system.physmem.avgGap 20320661.33 # Average gap between requests
+system.physmem.avgGap 20320661.36 # Average gap between requests
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1214891089 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 179135724 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed
system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 84079165 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 399080479 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 88232216 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 574634439 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.BlockedCycles 574634441 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 187842502 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 11743850 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1214538068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 187842503 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11743851 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1214538070 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.059666 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.253312 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 822675210 67.74% 67.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 822675212 67.74% 67.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 26883309 2.21% 69.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 13192065 1.09% 71.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 20566257 1.69% 72.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1214538068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 1214538070 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.130370 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.200462 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 288247470 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 497953946 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 497953948 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 274080522 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 92569137 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 61686993 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2343830219 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 61686993 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 336887109 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 124143934 # Number of cycles rename is blocking
+system.cpu.rename.BlockCycles 124143936 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2487 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 304057721 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 387759824 # Number of cycles rename is unblocking
system.cpu.iq.iqSquashedInstsExamined 372613756 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 761627172 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 239 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1214538068 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 1214538070 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.468938 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.421549 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 360345167 29.67% 29.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 360345169 29.67% 29.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 364336445 30.00% 59.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 234287346 19.29% 78.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 141446603 11.65% 90.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1214538068 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1214538070 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 437572 15.09% 15.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 15.09% # attempts to use FU when none available
system.cpu.iq.rate 1.468511 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2900605 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4785843295 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 4785843297 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2367295034 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1724820361 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 350 # Number of floating instruction queue reads
system.cpu.iew.lsq.thread0.cacheBlocked 68 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 61686993 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1142263 # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles 1142265 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 110648 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1994506717 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 63004482 # Number of squashed instructions skipped by dispatch
system.cpu.commit.commitSquashedInsts 373014217 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 26390469 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1152851075 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 1152851077 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.406508 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.830012 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 418199685 36.28% 36.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 418199687 36.28% 36.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 415017727 36.00% 72.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 87014149 7.55% 79.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 122172880 10.60% 90.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1152851075 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1152851077 # Number of insts commited each cycle
system.cpu.commit.committedInsts 880025277 # Number of instructions committed
system.cpu.commit.committedOps 1621493926 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 32432091 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3114927127 # The number of ROB reads
+system.cpu.rob.rob_reads 3114927129 # The number of ROB reads
system.cpu.rob.rob_writes 4050738571 # The number of ROB writes
system.cpu.timesIdled 58873 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 353021 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 353019 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 880025277 # Number of Instructions Simulated
system.cpu.committedOps 1621493926 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated
system.cpu.icache.demand_hits::total 187841119 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 187841119 # number of overall hits
system.cpu.icache.overall_hits::total 187841119 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses
-system.cpu.icache.overall_misses::total 1383 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 64282500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 64282500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 64282500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 64282500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 64282500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 64282500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 187842502 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 187842502 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 187842502 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 187842502 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 187842502 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 187842502 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 1384 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1384 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1384 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1384 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1384 # number of overall misses
+system.cpu.icache.overall_misses::total 1384 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 64353500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 64353500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 64353500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 64353500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 64353500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 64353500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 187842503 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 187842503 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 187842503 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 187842503 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 187842503 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 187842503 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46480.477223 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 46480.477223 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 46480.477223 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 46480.477223 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 46480.477223 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 46480.477223 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46498.193642 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 46498.193642 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 46498.193642 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 46498.193642 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 465 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 465 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 465 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 465 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 465 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 466 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 466 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 466 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 466 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 466 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 466 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 918 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 918 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 918 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50259.259259 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50259.259259 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 446019 # number of replacements
-system.cpu.dcache.tagsinuse 4092.902027 # Cycle average of tags in use
-system.cpu.dcache.total_refs 452395605 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 450115 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 1005.066716 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 828955000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4092.902027 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999244 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999244 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 264455973 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 264455973 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 187939624 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 187939624 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 452395597 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 452395597 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 452395597 # number of overall hits
-system.cpu.dcache.overall_hits::total 452395597 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 211135 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 211135 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 246434 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 246434 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 457569 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 457569 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 457569 # number of overall misses
-system.cpu.dcache.overall_misses::total 457569 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3016076500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3016076500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4063848999 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4063848999 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7079925499 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7079925499 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7079925499 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7079925499 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 264667108 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 264667108 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 452853166 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 452853166 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 452853166 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 452853166 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.001310 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14285.061690 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14285.061690 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16490.618174 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.618174 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.913373 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15472.913373 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.913373 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15472.913373 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks
-system.cpu.dcache.writebacks::total 428963 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523541000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523541000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570237499 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570237499 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778499 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6093778499 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778499 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6093778499 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.018570 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.018570 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.541096 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.541096 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13537.999527 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13537.999527 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13537.999527 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13537.999527 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2556 # number of replacements
system.cpu.l2cache.tagsinuse 22259.528577 # Cycle average of tags in use
system.cpu.l2cache.total_refs 531228 # Total number of references to valid blocks.
system.cpu.l2cache.avg_refs 21.959737 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20782.488903 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 799.212801 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 799.212802 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 677.826873 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.634231 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.024390 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.data 26457 # number of overall misses
system.cpu.l2cache.overall_misses::total 27359 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45120000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325819500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 370939500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079318500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 1079318500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325819000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 370939000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079319500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1079319500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 45120000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 1405138000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 1450258000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 1405138500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 1450258500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 45120000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 1405138000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 1450258000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 1405138500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 1450258500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 910 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 203769 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 204679 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.data 0.058778 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060659 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50022.172949 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71451.644737 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67912.760893 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49290.701923 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49290.701923 # average ReadExReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71451.535088 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67912.669352 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49290.747591 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49290.747591 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50022.172949 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53110.254375 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 53008.443291 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53110.273274 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 53008.461567 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50022.172949 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53110.254375 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 53008.443291 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53110.273274 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 53008.461567 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 902 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26457 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27359 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33761933 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267685448 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301447381 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 796656102 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 796656102 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33761933 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064341550 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33761433 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267684948 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301446381 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 796657102 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 796657102 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33761433 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064342050 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1098103483 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33761933 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064341550 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33761433 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064342050 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1098103483 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991209 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022378 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991209 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058778 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060659 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37430.080931 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58702.949123 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55189.926950 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36381.974791 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36381.974791 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37430.080931 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40229.109498 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37429.526608 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58702.839474 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55189.743867 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36382.020459 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36382.020459 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37429.526608 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40229.128397 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40136.828210 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37430.080931 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40229.109498 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37429.526608 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40229.128397 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40136.828210 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 446019 # number of replacements
+system.cpu.dcache.tagsinuse 4092.902027 # Cycle average of tags in use
+system.cpu.dcache.total_refs 452395605 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 450115 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 1005.066716 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 828955000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4092.902027 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999244 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999244 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 264455973 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 264455973 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 187939624 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 187939624 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 452395597 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 452395597 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 452395597 # number of overall hits
+system.cpu.dcache.overall_hits::total 452395597 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 211135 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 211135 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 246434 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 246434 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 457569 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 457569 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 457569 # number of overall misses
+system.cpu.dcache.overall_misses::total 457569 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3016076000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3016076000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4063849999 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4063849999 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7079925999 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7079925999 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7079925999 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7079925999 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 264667108 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 264667108 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 452853166 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 452853166 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 452853166 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 452853166 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.001310 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14285.059322 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14285.059322 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16490.622232 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.622232 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15472.914465 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15472.914465 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks
+system.cpu.dcache.writebacks::total 428963 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523540500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523540500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570238499 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570238499 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778999 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6093778999 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778999 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6093778999 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.016116 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.016116 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.545155 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.545155 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/gem5/dist/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 19:23:29
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:47:37
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 26786364500 # Number of ticks simulated
final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 184396 # Simulator instruction rate (inst/s)
-host_op_rate 185720 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 54518089 # Simulator tick rate (ticks/s)
-host_mem_usage 410024 # Number of bytes of host memory used
-host_seconds 491.33 # Real time elapsed on the host
+host_inst_rate 55091 # Simulator instruction rate (inst/s)
+host_op_rate 55487 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16288150 # Simulator tick rate (ticks/s)
+host_mem_usage 365372 # Number of bytes of host memory used
+host_seconds 1644.53 # Real time elapsed on the host
sim_insts 90599358 # Number of instructions simulated
sim_ops 91249911 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 26786185500 # Total gap between requests
+system.physmem.totGap 26786186500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 45050979 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 279102979 # Sum of mem lat for all requests
+system.physmem.totQLat 45051479 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 279103479 # Sum of mem lat for all requests
system.physmem.totBusLat 62048000 # Total cycles spent in databus access
system.physmem.totBankLat 172004000 # Total cycles spent in bank access
-system.physmem.avgQLat 2904.27 # Average queueing delay per request
+system.physmem.avgQLat 2904.30 # Average queueing delay per request
system.physmem.avgBankLat 11088.45 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 17992.71 # Average memory access latency
+system.physmem.avgMemAccLat 17992.75 # Average memory access latency
system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1726804.12 # Average gap between requests
+system.physmem.avgGap 1726804.18 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 14169802 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 14169803 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed
system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 11256916 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.BlockedCycles 11256917 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13841949 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 329938 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 53360207 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 13841950 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 53360208 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29366337 55.03% 55.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 29366338 55.03% 55.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53360207 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 53360208 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9104448 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 9104449 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing
system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21547168 # Number of cycles rename is running
+system.cpu.rename.RunCycles 21547169 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123140443 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 123140444 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 143600920 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536395589 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 536390601 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 143600921 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 536395593 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 536390605 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36171438 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 36171439 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer
system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 53360207 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 53360208 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15336122 28.74% 28.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 15336123 28.74% 28.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 53360207 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 53360208 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available
system.cpu.iq.rate 1.962950 # Inst issue rate
system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 264421445 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 264421446 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads
system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 309093 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 309094 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions
system.cpu.rob.rob_reads 162359257 # The number of ROB reads
system.cpu.rob.rob_writes 240263976 # The number of ROB writes
system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 212523 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 212522 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90599358 # Number of Instructions Simulated
system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated
system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits
system.cpu.icache.overall_hits::total 13840965 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses
-system.cpu.icache.overall_misses::total 983 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 48291499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 48291499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 48291499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 48291499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 48291499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 48291499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13841948 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13841948 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13841948 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13841948 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13841948 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13841948 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses
+system.cpu.icache.overall_misses::total 984 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 48362499 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 48362499 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 48362499 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 48362499 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 48362499 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 48362499 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 13841949 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 13841949 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 13841949 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 13841949 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 13841949 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 13841949 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49126.652085 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49126.652085 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49126.652085 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49126.652085 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49148.881098 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 49148.881098 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 49148.881098 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 49148.881098 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 943495 # number of replacements
-system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
-system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
-system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
-system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
-system.cpu.dcache.writebacks::total 942892 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks.
system.cpu.l2cache.overall_misses::cpu.data 14815 # number of overall misses
system.cpu.l2cache.overall_misses::total 15523 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35741000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14541500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 50282500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14542000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 50283000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 602811500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 602811500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 35741000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 617353000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 653094000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 617353500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 653094500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 35741000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 617353000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 653094000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 617353500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 653094500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 904075 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 904810 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016369 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50481.638418 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52496.389892 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.223350 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52498.194946 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.730964 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41464.541202 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41464.541202 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 42072.666366 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 42072.698576 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 42072.666366 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 42072.698576 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15512 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819084 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819584 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10783379 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602463 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602963 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 420800342 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 420800342 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819084 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819584 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 431583721 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 458402805 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819084 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 458403305 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819584 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 431583721 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 458402805 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 458403305 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016357 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37933.640736 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37934.347949 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40387.187266 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.224846 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.738193 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28944.857752 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 943495 # number of replacements
+system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
+system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
+system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
+system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880184000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 13880184000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 19250281404 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 19250281404 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 19250281404 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 19250281404 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782919 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782919 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14043.038478 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14043.038478 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
+system.cpu.dcache.writebacks::total 942892 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989578000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989578000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120952 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10947120952 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120952 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10947120952 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.342542 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.342542 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/gem5/dist/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
-Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:30
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 4 2013 21:20:54
+gem5 started Jan 4 2013 22:18:55
+gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 65982862500 # Number of ticks simulated
final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71115 # Simulator instruction rate (inst/s)
-host_op_rate 125222 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 29700736 # Simulator tick rate (ticks/s)
-host_mem_usage 413360 # Number of bytes of host memory used
-host_seconds 2221.59 # Real time elapsed on the host
+host_inst_rate 39069 # Simulator instruction rate (inst/s)
+host_op_rate 68794 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16316772 # Simulator tick rate (ticks/s)
+host_mem_usage 376348 # Number of bytes of host memory used
+host_seconds 4043.87 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192463 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 65982842000 # Total gap between requests
+system.physmem.totGap 65982843000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 10444357 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 571602357 # Sum of mem lat for all requests
+system.physmem.totQLat 10445857 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 571603857 # Sum of mem lat for all requests
system.physmem.totBusLat 121544000 # Total cycles spent in databus access
system.physmem.totBankLat 439614000 # Total cycles spent in bank access
-system.physmem.avgQLat 343.72 # Average queueing delay per request
+system.physmem.avgQLat 343.77 # Average queueing delay per request
system.physmem.avgBankLat 14467.65 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 18811.37 # Average memory access latency
+system.physmem.avgMemAccLat 18811.42 # Average memory access latency
system.physmem.avgRdBW 29.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 29.53 # Average consumed read bandwidth in MB/s
system.physmem.writeRowHits 45 # Number of row buffer hits during writes
system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
-system.physmem.avgGap 2155034.36 # Average gap between requests
+system.physmem.avgGap 2155034.39 # Average gap between requests
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 131965726 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 26601820 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed
system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 24642661 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 56492855 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6109576 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 43628030 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 25952050 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 188970 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.CacheLines 25952051 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 188971 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 131886743 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.485312 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.326723 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_writes 78 # number of floating regfile writes
system.cpu.misc_regfile_reads 192690356 # number of misc regfile reads
system.cpu.icache.replacements 68 # number of replacements
-system.cpu.icache.tagsinuse 836.141366 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 836.141368 # Cycle average of tags in use
system.cpu.icache.total_refs 25950700 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1039 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 24976.612127 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 836.141366 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 836.141368 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.408272 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.408272 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25950700 # number of ReadReq hits
system.cpu.icache.demand_hits::total 25950700 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25950700 # number of overall hits
system.cpu.icache.overall_hits::total 25950700 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1350 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1350 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1350 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1350 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1350 # number of overall misses
-system.cpu.icache.overall_misses::total 1350 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 65277000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 65277000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 65277000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 65277000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 65277000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 65277000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 25952050 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 25952050 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 25952050 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 25952050 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 25952050 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 25952050 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 1351 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1351 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1351 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1351 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1351 # number of overall misses
+system.cpu.icache.overall_misses::total 1351 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 65349000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 65349000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 65349000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 65349000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 65349000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 65349000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 25952051 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 25952051 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 25952051 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 25952051 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 25952051 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 25952051 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48353.333333 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 48353.333333 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 48353.333333 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 48353.333333 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48370.836417 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48370.836417 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48370.836417 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48370.836417 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 311 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1040 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1040 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1040 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1040 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1040 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1040 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52080000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 52080000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52080000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 52080000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52080000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 52080000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52081000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 52081000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52081000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 52081000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52081000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 52081000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50076.923077 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50076.923077 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50077.884615 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50077.884615 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2072071 # number of replacements
-system.cpu.dcache.tagsinuse 4072.565348 # Cycle average of tags in use
-system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4072.565348 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits
-system.cpu.dcache.overall_hits::total 71946748 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses
-system.cpu.dcache.overall_misses::total 2723462 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321017500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 31321017500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 33409125998 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 33409125998 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 33409125998 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 33409125998 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.970796 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.970796 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.153350 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12267.153350 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.153350 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12267.153350 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks
-system.cpu.dcache.writebacks::total 2066432 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983433500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983433500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 23796285498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285498 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 23796285498 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531267 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531267 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621176 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621176 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621176 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621176 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 488 # number of replacements
-system.cpu.l2cache.tagsinuse 20806.359939 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 20806.359941 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4028768 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 30421 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 132.433779 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 19869.947946 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 692.491885 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 692.491887 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 243.920108 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.606383 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.021133 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses
system.cpu.l2cache.overall_misses::total 30444 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50832500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21222500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 72055000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50833500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21223000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 72056500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199120000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1199120000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 50832500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 1220342500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 1271175000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 50832500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 1220342500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 1271175000 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 50833500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 1220343000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 1271176500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 50833500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 1220343000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 1271176500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1039 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1993942 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1994981 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980751 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014173 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.014656 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49884.690873 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50053.066038 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 49934.164934 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49885.672228 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50054.245283 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 49935.204435 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41347.539740 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41347.539740 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 41754.532913 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 41754.532913 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 41754.582184 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 41754.582184 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 29425 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 30444 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37999583 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880149 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53879732 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38000083 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880649 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53880732 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824195395 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824195395 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37999583 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840075544 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 878075127 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37999583 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840075544 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 878075127 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38000083 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840076044 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 878076127 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38000083 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840076044 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 878076127 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000723 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014656 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.052993 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37453.181604 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37338.691615 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.543670 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37454.360849 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37339.384615 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28419.550878 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28419.550878 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2072071 # number of replacements
+system.cpu.dcache.tagsinuse 4072.565350 # Cycle average of tags in use
+system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4072.565350 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits
+system.cpu.dcache.overall_hits::total 71946748 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses
+system.cpu.dcache.overall_misses::total 2723462 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321024000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 31321024000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 33409132498 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 33409132498 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 33409132498 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 33409132498 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.973272 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.973272 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12267.155737 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12267.155737 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks
+system.cpu.dcache.writebacks::total 2066432 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983434000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983434000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285998 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 23796285998 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285998 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 23796285998 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531518 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531518 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/gem5/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
-warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7]
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 19:35:49
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:51:04
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 206019870500 because target called exit()
+Exiting @ tick 206006891000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.206025 # Number of seconds simulated
-sim_ticks 206024606500 # Number of ticks simulated
-final_tick 206024606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.206007 # Number of seconds simulated
+sim_ticks 206006891000 # Number of ticks simulated
+final_tick 206006891000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 152686 # Simulator instruction rate (inst/s)
-host_op_rate 172002 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 61807337 # Simulator tick rate (ticks/s)
-host_mem_usage 303988 # Number of bytes of host memory used
-host_seconds 3333.34 # Real time elapsed on the host
-sim_insts 508955238 # Number of instructions simulated
-sim_ops 573341798 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9266560 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9483840 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6249216 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6249216 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 144790 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 148185 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 97644 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 97644 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1054631 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 44977928 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 46032560 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1054631 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1054631 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 30332377 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 30332377 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 30332377 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1054631 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 44977928 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 76364937 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 148186 # Total number of read requests seen
-system.physmem.writeReqs 97644 # Total number of write requests seen
-system.physmem.cpureqs 245841 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 9483840 # Total number of bytes read from memory
-system.physmem.bytesWritten 6249216 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 9483840 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6249216 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 83 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 9219 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 9199 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 9344 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 8811 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 9228 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 8973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 9239 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 9440 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 9127 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 10272 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 9693 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 9714 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 9129 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 8954 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 8756 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 5972 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 6125 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 5945 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 6129 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 5951 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 6023 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 6373 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 5964 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 6647 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6322 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 6045 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 6065 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 5899 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 5778 # Track writes on a per bank basis
+host_inst_rate 48397 # Simulator instruction rate (inst/s)
+host_op_rate 54519 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19589283 # Simulator tick rate (ticks/s)
+host_mem_usage 261836 # Number of bytes of host memory used
+host_seconds 10516.31 # Real time elapsed on the host
+sim_insts 508955198 # Number of instructions simulated
+sim_ops 573341758 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 216256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9272640 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9488896 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 216256 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 216256 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6250240 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6250240 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3379 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 144885 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 148264 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 97660 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 97660 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1049751 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 45011310 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 46061061 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1049751 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1049751 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 30339956 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 30339956 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 30339956 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1049751 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 45011310 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 76401017 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 148265 # Total number of read requests seen
+system.physmem.writeReqs 97660 # Total number of write requests seen
+system.physmem.cpureqs 245934 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 9488896 # Total number of bytes read from memory
+system.physmem.bytesWritten 6250240 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 9488896 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6250240 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 9228 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 9341 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 8794 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 9227 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 8981 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 9254 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 9466 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 9155 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 10302 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 9694 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 9707 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 9134 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 8959 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 9019 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 8746 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 5978 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 6111 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6105 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 5940 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6130 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 5961 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6031 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6368 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6669 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6289 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6316 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 6051 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 6056 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 5913 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 5774 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 206024585500 # Total gap between requests
+system.physmem.totGap 206006873500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 148186 # Categorize read packet sizes
+system.physmem.readPktSize::6 148265 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 97644 # categorize write packet sizes
+system.physmem.writePktSize::6 97660 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 11 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 9 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 138148 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9303 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 576 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 138270 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 9286 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4240 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4241 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4247 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1634901672 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 4710633672 # Sum of mem lat for all requests
-system.physmem.totBusLat 592412000 # Total cycles spent in databus access
-system.physmem.totBankLat 2483320000 # Total cycles spent in bank access
-system.physmem.avgQLat 11038.95 # Average queueing delay per request
-system.physmem.avgBankLat 16767.52 # Average bank access latency per request
+system.physmem.totQLat 1631933240 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4708845240 # Sum of mem lat for all requests
+system.physmem.totBusLat 592780000 # Total cycles spent in databus access
+system.physmem.totBankLat 2484132000 # Total cycles spent in bank access
+system.physmem.avgQLat 11012.07 # Average queueing delay per request
+system.physmem.avgBankLat 16762.59 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31806.47 # Average memory access latency
-system.physmem.avgRdBW 46.03 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 30.33 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 46.03 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 30.33 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 31774.66 # Average memory access latency
+system.physmem.avgRdBW 46.06 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 30.34 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 46.06 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 30.34 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.48 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
-system.physmem.avgWrQLen 8.63 # Average write queue length over time
-system.physmem.readRowHits 128528 # Number of row buffer hits during reads
-system.physmem.writeRowHits 35061 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.78 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 35.91 # Row buffer hit rate for writes
-system.physmem.avgGap 838077.47 # Average gap between requests
+system.physmem.avgWrQLen 8.58 # Average write queue length over time
+system.physmem.readRowHits 128622 # Number of row buffer hits during reads
+system.physmem.writeRowHits 35037 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.79 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 35.88 # Row buffer hit rate for writes
+system.physmem.avgGap 837681.71 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 412049214 # number of cpu cycles simulated
+system.cpu.numCycles 412013783 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 182068030 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 142371650 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 7270692 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 93491623 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 88706856 # Number of BTB hits
+system.cpu.BPredUnit.lookups 182073557 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 142374329 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 7271583 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 93640941 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 88714986 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 12684721 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 116337 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 117167260 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 763059580 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 182068030 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 101391577 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 170902348 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 35691223 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 89206735 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 447 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 113060023 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2443326 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 404896941 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.113484 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.961332 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 12682930 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 115717 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 117168420 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 763090504 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 182073557 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 101397916 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 170904146 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 35690489 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 89173012 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 387 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 113064693 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2443926 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 404864320 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.113664 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.961425 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 234007224 57.79% 57.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 14183787 3.50% 61.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22898202 5.66% 66.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22746913 5.62% 72.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 20897614 5.16% 77.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 13086335 3.23% 80.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13059349 3.23% 84.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 11995905 2.96% 87.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 52021612 12.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 233972788 57.79% 57.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 14182494 3.50% 61.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22907477 5.66% 66.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22746192 5.62% 72.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 20892499 5.16% 77.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 13088798 3.23% 80.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13051042 3.22% 84.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 11993527 2.96% 87.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 52029503 12.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 404896941 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.441860 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.851865 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 127568061 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 83247236 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 161078099 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 5457696 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 27545849 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 26128375 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 76880 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 833033782 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 297363 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 27545849 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 135637511 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 9603466 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 58001862 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158291644 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 15816609 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 804360707 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1150 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3056892 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8825253 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 274 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 960209661 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3520079656 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3520077996 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 672200315 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 288009346 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3037560 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 3037556 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 48985402 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 170961044 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 74192431 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 27929541 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 15655992 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 757955551 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 4467760 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 669035735 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1391656 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 187243555 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 479554620 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 746625 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 404896941 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.652361 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.728633 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 404864320 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.441911 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.852099 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 127567795 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 83214346 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 161081773 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 5456100 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 27544306 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 26131693 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 76746 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 833046476 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 293832 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 27544306 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 135636368 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 9592122 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 57998215 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 158294561 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 15798748 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 804356889 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 3056071 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8809517 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 236 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 960228219 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3520047664 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3520046036 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1628 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 672200251 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 288027968 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 3037400 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 3037395 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 48984020 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 170948465 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 74181775 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 27930048 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 15662241 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 757938362 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4467556 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 669004170 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1390745 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 187223839 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 479595431 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 746429 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 404864320 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.652416 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.728625 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 145342748 35.90% 35.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 75751868 18.71% 54.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 69103679 17.07% 71.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 53697004 13.26% 84.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 30880919 7.63% 92.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 16180758 4.00% 96.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 9302044 2.30% 98.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3357601 0.83% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1280320 0.32% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 145294997 35.89% 35.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 75803785 18.72% 54.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 69074812 17.06% 71.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 53696610 13.26% 84.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 30882442 7.63% 92.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16155264 3.99% 96.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 9314791 2.30% 98.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3366855 0.83% 99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1274764 0.31% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 404896941 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 404864320 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 478504 4.99% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 478550 4.99% 4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6546722 68.33% 73.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2556023 26.68% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6548662 68.24% 73.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2569141 26.77% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 449967918 67.26% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 383484 0.06% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 154140670 23.04% 90.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 64543544 9.65% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 449957502 67.26% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 383513 0.06% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 114 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 154129801 23.04% 90.35% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 64533237 9.65% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 669035735 # Type of FU issued
-system.cpu.iq.rate 1.623679 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9581249 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014321 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1753941049 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 950473417 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 649676758 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 669004170 # Type of FU issued
+system.cpu.iq.rate 1.623742 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9596353 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014344 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1753859495 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 950436200 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 649651296 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 358 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 678616849 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8574736 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 678600390 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 8560025 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 44187986 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 40720 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 810577 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 16588451 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 44175415 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 40342 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 810510 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 16577803 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19568 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4004 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19533 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 4184 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 27545849 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 4988149 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 372803 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 763982304 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1114436 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 170961044 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 74192431 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2979014 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 218503 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11510 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 810577 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4341639 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4005453 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8347092 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 659537182 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 150855099 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9498553 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 27544306 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 4979953 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 372702 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 763965600 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1116680 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 170948465 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 74181775 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2978814 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 218949 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11431 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 810510 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4004049 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8346983 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 659511571 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 150841037 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 9492599 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1558993 # number of nop insts executed
-system.cpu.iew.exec_refs 214102413 # number of memory reference insts executed
-system.cpu.iew.exec_branches 139198797 # Number of branches executed
-system.cpu.iew.exec_stores 63247314 # Number of stores executed
-system.cpu.iew.exec_rate 1.600627 # Inst execution rate
-system.cpu.iew.wb_sent 654653382 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 649676774 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 375457821 # num instructions producing a value
-system.cpu.iew.wb_consumers 646369335 # num instructions consuming a value
+system.cpu.iew.exec_nop 1559682 # number of nop insts executed
+system.cpu.iew.exec_refs 214084743 # number of memory reference insts executed
+system.cpu.iew.exec_branches 139192858 # Number of branches executed
+system.cpu.iew.exec_stores 63243706 # Number of stores executed
+system.cpu.iew.exec_rate 1.600703 # Inst execution rate
+system.cpu.iew.wb_sent 654626894 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 649651312 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 375421754 # num instructions producing a value
+system.cpu.iew.wb_consumers 646280118 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.576697 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.580872 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.576771 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.580896 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 189322511 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 3721135 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7196542 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 377351093 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.522947 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.207142 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 189306245 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 3721127 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 7197604 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 377320014 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.523072 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.207570 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 165639440 43.90% 43.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 102355544 27.12% 71.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 34004026 9.01% 80.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 18854456 5.00% 85.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 16118319 4.27% 89.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7599031 2.01% 91.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6941679 1.84% 93.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3068571 0.81% 93.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22770027 6.03% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 165631141 43.90% 43.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 102377769 27.13% 71.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 33965417 9.00% 80.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 18834681 4.99% 85.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 16120892 4.27% 89.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7588494 2.01% 91.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6947007 1.84% 93.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3071988 0.81% 93.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22782625 6.04% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 377351093 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 510299122 # Number of instructions committed
-system.cpu.commit.committedOps 574685682 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 377320014 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 510299082 # Number of instructions committed
+system.cpu.commit.committedOps 574685642 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 184377038 # Number of memory references committed
-system.cpu.commit.loads 126773058 # Number of loads committed
+system.cpu.commit.refs 184377022 # Number of memory references committed
+system.cpu.commit.loads 126773050 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
-system.cpu.commit.branches 122291804 # Number of branches committed
+system.cpu.commit.branches 122291796 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 473701705 # Number of committed integer instructions.
+system.cpu.commit.int_insts 473701673 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 22770027 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22782625 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1118582121 # The number of ROB reads
-system.cpu.rob.rob_writes 1555682986 # The number of ROB writes
-system.cpu.timesIdled 306922 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7152273 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 508955238 # Number of Instructions Simulated
-system.cpu.committedOps 573341798 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 508955238 # Number of Instructions Simulated
-system.cpu.cpi 0.809598 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.809598 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.235181 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.235181 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3078487600 # number of integer regfile reads
-system.cpu.int_regfile_writes 757812476 # number of integer regfile writes
+system.cpu.rob.rob_reads 1118522138 # The number of ROB reads
+system.cpu.rob.rob_writes 1555649058 # The number of ROB writes
+system.cpu.timesIdled 306506 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7149463 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 508955198 # Number of Instructions Simulated
+system.cpu.committedOps 573341758 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 508955198 # Number of Instructions Simulated
+system.cpu.cpi 0.809529 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.809529 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.235287 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.235287 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3078340491 # number of integer regfile reads
+system.cpu.int_regfile_writes 757780607 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 213834943 # number of misc regfile reads
-system.cpu.misc_regfile_writes 4464090 # number of misc regfile writes
-system.cpu.icache.replacements 14939 # number of replacements
-system.cpu.icache.tagsinuse 1085.691077 # Cycle average of tags in use
-system.cpu.icache.total_refs 113039002 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 16794 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 6730.915922 # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads 213817535 # number of misc regfile reads
+system.cpu.misc_regfile_writes 4464074 # number of misc regfile writes
+system.cpu.icache.replacements 15034 # number of replacements
+system.cpu.icache.tagsinuse 1084.596639 # Cycle average of tags in use
+system.cpu.icache.total_refs 113043631 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 16888 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 6693.725189 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1085.691077 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.530123 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.530123 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 113039002 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 113039002 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 113039002 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 113039002 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 113039002 # number of overall hits
-system.cpu.icache.overall_hits::total 113039002 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 21020 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 21020 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 21020 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 21020 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 21020 # number of overall misses
-system.cpu.icache.overall_misses::total 21020 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 467898499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 467898499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 467898499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 467898499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 467898499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 467898499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 113060022 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 113060022 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 113060022 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 113060022 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 113060022 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 113060022 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 1084.596639 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.529588 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.529588 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 113043631 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 113043631 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 113043631 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 113043631 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 113043631 # number of overall hits
+system.cpu.icache.overall_hits::total 113043631 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 21062 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 21062 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 21062 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 21062 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 21062 # number of overall misses
+system.cpu.icache.overall_misses::total 21062 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 460496000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 460496000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 460496000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 460496000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 460496000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 460496000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 113064693 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 113064693 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 113064693 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 113064693 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 113064693 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 113064693 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22259.681208 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22259.681208 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22259.681208 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22259.681208 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22259.681208 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22259.681208 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21863.830595 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21863.830595 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21863.830595 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21863.830595 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1088 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 44.071429 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 90.666667 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4142 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 4142 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 4142 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 4142 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 4142 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 4142 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16878 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 16878 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 16878 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 16878 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 16878 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 16878 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 345467499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 345467499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 345467499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 345467499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 345467499 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 345467499 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20468.509243 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20468.509243 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20468.509243 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20468.509243 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20468.509243 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20468.509243 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4099 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 4099 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 4099 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 4099 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 4099 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 4099 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16963 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 16963 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 16963 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 16963 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 16963 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 16963 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340828000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 340828000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340828000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 340828000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340828000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 340828000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000150 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000150 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000150 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20092.436479 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20092.436479 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1192636 # number of replacements
-system.cpu.dcache.tagsinuse 4054.758730 # Cycle average of tags in use
-system.cpu.dcache.total_refs 191679858 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1196732 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 160.169410 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4054.758730 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.989931 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.989931 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 136223332 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 136223332 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 50991136 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 50991136 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233077 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 2233077 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 2232044 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 2232044 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 187214468 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 187214468 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 187214468 # number of overall hits
-system.cpu.dcache.overall_hits::total 187214468 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1695528 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1695528 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3248170 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3248170 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 4943698 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4943698 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4943698 # number of overall misses
-system.cpu.dcache.overall_misses::total 4943698 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 25996744000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 25996744000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 58872632949 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 58872632949 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 602000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 602000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 84869376949 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 84869376949 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 84869376949 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 84869376949 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 137918860 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 137918860 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233117 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 2233117 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232044 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 2232044 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 192158166 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 192158166 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 192158166 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 192158166 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012294 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012294 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059886 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.059886 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025727 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025727 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025727 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025727 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15332.535942 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15332.535942 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18124.861984 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 18124.861984 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15050 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15050 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17167.184757 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17167.184757 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 14786 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 14311 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1668 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 602 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.864508 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 23.772425 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1110847 # number of writebacks
-system.cpu.dcache.writebacks::total 1110847 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847136 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 847136 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899743 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2899743 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3746879 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3746879 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3746879 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3746879 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848392 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 848392 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348427 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 348427 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1196819 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1196819 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1196819 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1196819 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11475027500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 11475027500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8270144996 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8270144996 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19745172496 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 19745172496 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19745172496 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 19745172496 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13525.619643 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13525.619643 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23735.660543 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23735.660543 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16498.043978 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16498.043978 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16498.043978 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16498.043978 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 115436 # number of replacements
-system.cpu.l2cache.tagsinuse 26914.677594 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1781438 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 146695 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 12.143822 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 106786835500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 22885.911087 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 362.909713 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 3665.856794 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.698423 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.011075 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.111873 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.821371 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 13377 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 804311 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 817688 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1110847 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1110847 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 76 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 76 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 247608 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 247608 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 13377 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1051919 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1065296 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 13377 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1051919 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1065296 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3401 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 43520 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 46921 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3401 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 144813 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 148214 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3401 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 144813 # number of overall misses
-system.cpu.l2cache.overall_misses::total 148214 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 194270000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2545313000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 2739583000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5395902500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 5395902500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 194270000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7941215500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 8135485500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 194270000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7941215500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 8135485500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 16778 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 847831 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 864609 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1110847 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1110847 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 87 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 87 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 348901 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 348901 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 16778 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1196732 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1213510 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 16778 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1196732 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1213510 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.202706 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051331 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.054268 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.126437 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.126437 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290320 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.290320 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.202706 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.121007 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.122137 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.202706 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.121007 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.122137 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57121.434872 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58486.052390 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 58387.140087 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53270.240787 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53270.240787 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57121.434872 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54837.725204 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 54890.128463 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57121.434872 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54837.725204 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 54890.128463 # average overall miss latency
+system.cpu.l2cache.replacements 115524 # number of replacements
+system.cpu.l2cache.tagsinuse 26913.844111 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1781016 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 146770 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 12.134741 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 106794042500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 22881.724629 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 362.646179 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 3669.473303 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.698295 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.011067 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.111983 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.821345 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 13496 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 804094 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 817590 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1110621 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1110621 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 66 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 66 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 247478 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 247478 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 13496 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1051572 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1065068 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 13496 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1051572 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1065068 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3384 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 43623 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 47007 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 101285 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 101285 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3384 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 144908 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 148292 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3384 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 144908 # number of overall misses
+system.cpu.l2cache.overall_misses::total 148292 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188319500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2550766500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 2739086000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5396872000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5396872000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 188319500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7947638500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 8135958000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 188319500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7947638500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 8135958000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 16880 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 847717 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 864597 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1110621 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1110621 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 75 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 348763 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 348763 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 16880 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1196480 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1213360 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 16880 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1196480 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1213360 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200474 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051459 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.054369 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.120000 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.120000 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290412 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.290412 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200474 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.121112 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.122216 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200474 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.121112 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.122216 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55649.970449 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58472.972973 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 58269.747059 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53284.020339 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53284.020339 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55649.970449 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54846.098904 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54864.443126 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55649.970449 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54846.098904 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54864.443126 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 97644 # number of writebacks
-system.cpu.l2cache.writebacks::total 97644 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 97660 # number of writebacks
+system.cpu.l2cache.writebacks::total 97660 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3396 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43497 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 46893 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3396 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 144790 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 148186 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3396 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 144790 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 148186 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 150961260 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1989439233 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2140400493 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 110011 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 110011 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4107848419 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4107848419 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 150961260 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6097287652 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 6248248912 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 150961260 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6097287652 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 6248248912 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051304 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.126437 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.126437 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290320 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290320 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120988 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.122114 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120988 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.122114 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44452.667845 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45737.389544 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45644.349754 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3379 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43601 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 46980 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101285 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 101285 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3379 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 144886 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 148265 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3379 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 144886 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 148265 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 144900235 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1993232927 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2138133162 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4109014892 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4109014892 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 144900235 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6102247819 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6247148054 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 144900235 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6102247819 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6247148054 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051433 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054337 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.120000 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.120000 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290412 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290412 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121094 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.122194 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121094 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.122194 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42882.579165 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45715.303021 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45511.561558 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40554.119426 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40554.119426 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40568.839335 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40568.839335 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42882.579165 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42117.580850 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42135.015371 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42882.579165 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42117.580850 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42135.015371 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1192383 # number of replacements
+system.cpu.dcache.tagsinuse 4054.755183 # Cycle average of tags in use
+system.cpu.dcache.total_refs 191684453 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1196479 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 160.207119 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4054.755183 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.989930 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.989930 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 136225611 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 136225611 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 50993519 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 50993519 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233068 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 2233068 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 2232036 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 2232036 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 187219130 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 187219130 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 187219130 # number of overall hits
+system.cpu.dcache.overall_hits::total 187219130 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1694816 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1694816 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3245787 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3245787 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 4940603 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 4940603 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 4940603 # number of overall misses
+system.cpu.dcache.overall_misses::total 4940603 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 25904626000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 25904626000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 58849421949 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 58849421949 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 574000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 574000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 84754047949 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 84754047949 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 84754047949 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 84754047949 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 137920427 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 137920427 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233106 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 2233106 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232036 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 2232036 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 192159733 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 192159733 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 192159733 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 192159733 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012288 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.012288 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059842 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.059842 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000017 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000017 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025711 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025711 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025711 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025711 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15284.624408 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15284.624408 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18131.017824 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 18131.017824 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15105.263158 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15105.263158 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17154.595896 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17154.595896 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17154.595896 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17154.595896 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 17486 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 15854 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1635 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 605 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.694801 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 26.204959 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 1110621 # number of writebacks
+system.cpu.dcache.writebacks::total 1110621 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 846554 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 846554 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2897494 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2897494 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3744048 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3744048 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3744048 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3744048 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848262 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 848262 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348293 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 348293 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1196555 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1196555 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1196555 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1196555 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11478175000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 11478175000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269727997 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269727997 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19747902997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 19747902997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19747902997 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 19747902997 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13531.403033 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13531.403033 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23743.595183 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23743.595183 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/gem5/dist/cpu2000/binaries/x86/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
-Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:06:22
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 4 2013 21:20:54
+gem5 started Jan 4 2013 22:32:47
+gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 434474519000 # Number of ticks simulated
final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 64407 # Simulator instruction rate (inst/s)
-host_op_rate 119096 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 33842135 # Simulator tick rate (ticks/s)
-host_mem_usage 385848 # Number of bytes of host memory used
-host_seconds 12838.27 # Real time elapsed on the host
+host_inst_rate 38128 # Simulator instruction rate (inst/s)
+host_op_rate 70503 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20033995 # Simulator tick rate (ticks/s)
+host_mem_usage 425632 # Number of bytes of host memory used
+host_seconds 21686.86 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988700 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 18435 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 434474501000 # Total gap between requests
+system.physmem.totGap 434474502000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.neitherpktsize::6 213431 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 380876 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4272 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 53 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 380877 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4271 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 383 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3519471180 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11592783180 # Sum of mem lat for all requests
+system.physmem.totQLat 3519643685 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11592955685 # Sum of mem lat for all requests
system.physmem.totBusLat 1542368000 # Total cycles spent in databus access
system.physmem.totBankLat 6530944000 # Total cycles spent in bank access
-system.physmem.avgQLat 9127.45 # Average queueing delay per request
+system.physmem.avgQLat 9127.90 # Average queueing delay per request
system.physmem.avgBankLat 16937.45 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30064.90 # Average memory access latency
+system.physmem.avgMemAccLat 30065.34 # Average memory access latency
system.physmem.avgRdBW 56.82 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 56.82 # Average consumed read bandwidth in MB/s
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 180614780 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 180614847 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed
system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 147901505 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 371277896 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 83426833 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 232782957 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 33410 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.BlockedCycles 232782979 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 33409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 326127 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 173495456 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 3828583 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 855065189 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 173495457 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 3828584 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 855065277 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.591332 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.388123 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.388122 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 488192448 57.09% 57.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 488192536 57.09% 57.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 24710241 2.89% 59.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 27337259 3.20% 63.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 28858306 3.37% 66.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 855065189 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 855065277 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.247441 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.373225 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 236982201 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 189423350 # Number of cycles decode is blocked
+system.cpu.decode.IdleCycles 236982267 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 189423372 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 313528776 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 45100886 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 70029976 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2167023894 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 70029976 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 270449019 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 55242457 # Number of cycles rename is blocking
+system.cpu.rename.IdleCycles 270449085 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 55242479 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 16336 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 322681638 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 136645763 # Number of cycles rename is unblocking
system.cpu.iq.iqSquashedInstsExamined 499602168 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 818314817 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 22641 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 855065189 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 855065277 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.114825 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.887939 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 234637640 27.44% 27.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 145403734 17.00% 44.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 138360213 16.18% 60.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 132907886 15.54% 76.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 234637728 27.44% 27.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 145403732 17.00% 44.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 138360216 16.18% 60.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 132907885 15.54% 76.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 96033162 11.23% 87.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 58823756 6.88% 94.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 34984723 4.09% 98.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 58823757 6.88% 94.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 34984722 4.09% 98.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 12006815 1.40% 99.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1907260 0.22% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 855065189 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 855065277 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 4945166 32.31% 32.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available
system.cpu.iq.rate 2.081035 # Inst issue rate
system.cpu.iq.fu_busy_cnt 15304879 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008464 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4487818661 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 4487818749 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2533909829 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1768767082 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 22466 # Number of floating instruction queue reads
system.cpu.iew.wb_sent 1775473697 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1768772258 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1341647639 # num instructions producing a value
-system.cpu.iew.wb_consumers 1964496611 # num instructions consuming a value
+system.cpu.iew.wb_consumers 1964496615 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.035530 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.682947 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 505138383 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 13172358 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 785035213 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 785035301 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.947669 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.458282 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 291749690 37.16% 37.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 195656651 24.92% 62.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 62029976 7.90% 69.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 291749780 37.16% 37.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 195656650 24.92% 62.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 62029975 7.90% 69.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 92178611 11.74% 81.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25075018 3.19% 84.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 25075017 3.19% 84.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 28259306 3.60% 88.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 9351525 1.19% 89.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10844976 1.38% 91.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10844977 1.38% 91.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 69889460 8.90% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 785035213 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 785035301 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 69889460 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2749272836 # The number of ROB reads
+system.cpu.rob.rob_reads 2749272924 # The number of ROB reads
system.cpu.rob.rob_writes 4138465929 # The number of ROB writes
system.cpu.timesIdled 341987 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13883850 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 13883762 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
system.cpu.fp_regfile_writes 5 # number of floating regfile writes
system.cpu.misc_regfile_reads 980297933 # number of misc regfile reads
system.cpu.icache.replacements 5393 # number of replacements
-system.cpu.icache.tagsinuse 1034.711161 # Cycle average of tags in use
-system.cpu.icache.total_refs 173255659 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1034.711169 # Cycle average of tags in use
+system.cpu.icache.total_refs 173255660 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 6985 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 24803.959771 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 24803.959914 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1034.711161 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1034.711169 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.505230 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.505230 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 173271213 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 173271213 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 173271213 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 173271213 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 173271213 # number of overall hits
-system.cpu.icache.overall_hits::total 173271213 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 173271214 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 173271214 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 173271214 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 173271214 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 173271214 # number of overall hits
+system.cpu.icache.overall_hits::total 173271214 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 224243 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 224243 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 224243 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 224243 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 224243 # number of overall misses
system.cpu.icache.overall_misses::total 224243 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1407047499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1407047499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1407047499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1407047499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1407047499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1407047499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 173495456 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 173495456 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 173495456 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 173495456 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 173495456 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 173495456 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1406797999 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 1406797999 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 1406797999 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 1406797999 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 1406797999 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 1406797999 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 173495457 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 173495457 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 173495457 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 173495457 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 173495457 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 173495457 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001293 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001293 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001293 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001293 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001293 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001293 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6274.655169 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 6274.655169 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 6274.655169 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 6274.655169 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 6274.655169 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 6274.655169 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6273.542536 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 6273.542536 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 6273.542536 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 6273.542536 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 221942 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 221942 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 221942 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 897816999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 897816999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 897816999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 897816999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 897816999 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 897816999 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 897728499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 897728499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 897728499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 897728499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 897728499 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 897728499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001279 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001279 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001279 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4045.277591 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4045.277591 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4045.277591 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 4045.277591 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4045.277591 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 4045.277591 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4044.878838 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4044.878838 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4044.878838 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 4044.878838 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4044.878838 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 4044.878838 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2529684 # number of replacements
-system.cpu.dcache.tagsinuse 4087.842109 # Cycle average of tags in use
-system.cpu.dcache.total_refs 405350413 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2533780 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 159.978535 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4087.842109 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 256614449 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 256614449 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148157374 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148157374 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 404771823 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 404771823 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 404771823 # number of overall hits
-system.cpu.dcache.overall_hits::total 404771823 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2894004 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2894004 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1002828 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1002828 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3896832 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3896832 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3896832 # number of overall misses
-system.cpu.dcache.overall_misses::total 3896832 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 50112496000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 50112496000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 24443364500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 24443364500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 74555860500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 74555860500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 74555860500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 74555860500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 259508453 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 259508453 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17315.973302 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17315.973302 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.433602 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.433602 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.428727 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19132.428727 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.428727 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19132.428727 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks
-system.cpu.dcache.writebacks::total 2331225 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924620000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924620000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273932000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273932000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198552000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 49198552000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198552000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 49198552000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.036805 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.036805 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.461600 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.461600 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17898.928470 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17898.928470 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17898.928470 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17898.928470 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 353060 # number of replacements
-system.cpu.l2cache.tagsinuse 29622.342662 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 29622.342672 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3697189 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 385414 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 9.592773 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 201829074500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21058.164970 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 233.252125 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 8330.925568 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 233.252133 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 8330.925570 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.642644 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.007118 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.254240 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 3263 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 382518 # number of overall misses
system.cpu.l2cache.overall_misses::total 385781 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183141000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9258521455 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 9441662455 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183052500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9258735955 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 9441788455 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7420500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 7420500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10977669000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 10977669000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 183141000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 20236190455 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 20419331455 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 183141000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 20236190455 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 20419331455 # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10977713000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 10977713000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 183052500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 20236448955 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 20419501455 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 183052500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 20236448955 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 20419501455 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6941 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1762382 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1769323 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470105 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150967 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.151839 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56126.570641 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52679.465696 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52742.297880 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56099.448360 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52680.686166 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52743.001732 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.773379 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.773379 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53092.234700 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53092.234700 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56126.570641 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52902.583552 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52929.852572 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56126.570641 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52902.583552 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52929.852572 # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53092.447501 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53092.447501 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56099.448360 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52903.259337 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52930.293236 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56099.448360 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52903.259337 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52930.293236 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3263 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 382518 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 141900442 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6995851441 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7137751883 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 141813443 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6996065941 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7137879384 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2139624153 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2139624153 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8343850802 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8343850802 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141900442 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15339702243 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 15481602685 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141900442 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15339702243 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 15481602685 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8343894304 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8343894304 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141813443 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15339960245 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 15481773688 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141813443 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15339960245 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 15481773688 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099724 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101177 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150967 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151839 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43487.723567 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39805.245124 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39872.367584 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43461.061293 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39806.465594 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39873.079820 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.542920 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.542920 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.075631 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.075631 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.286024 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.286024 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2529684 # number of replacements
+system.cpu.dcache.tagsinuse 4087.842112 # Cycle average of tags in use
+system.cpu.dcache.total_refs 405350413 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2533780 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 159.978535 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4087.842112 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 256614449 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 256614449 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 148157374 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 148157374 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 404771823 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 404771823 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 404771823 # number of overall hits
+system.cpu.dcache.overall_hits::total 404771823 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2894004 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2894004 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1002828 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1002828 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 3896832 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3896832 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3896832 # number of overall misses
+system.cpu.dcache.overall_misses::total 3896832 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 50112721500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 50112721500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 24443408500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 24443408500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 74556130000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 74556130000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 74556130000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 74556130000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 259508453 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 259508453 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17316.051222 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17316.051222 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.477478 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.477478 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19132.497885 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19132.497885 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks
+system.cpu.dcache.writebacks::total 2331225 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924834500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924834500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273976000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273976000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198810500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 49198810500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198810500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 49198810500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.158497 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.158497 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.506223 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.506223 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/gem5/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 19:45:28
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 00:06:54
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 68267465500 # Number of ticks simulated
final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 160764 # Simulator instruction rate (inst/s)
-host_op_rate 205527 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40194170 # Simulator tick rate (ticks/s)
-host_mem_usage 285344 # Number of bytes of host memory used
-host_seconds 1698.44 # Real time elapsed on the host
+host_inst_rate 47859 # Simulator instruction rate (inst/s)
+host_op_rate 61184 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11965597 # Simulator tick rate (ticks/s)
+host_mem_usage 240720 # Number of bytes of host memory used
+host_seconds 5705.31 # Real time elapsed on the host
sim_insts 273048375 # Number of instructions simulated
sim_ops 349076099 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 68267282000 # Total gap between requests
+system.physmem.totGap 68267283000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 9355527.20 # Average gap between requests
+system.physmem.avgGap 9355527.34 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 6736138 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 7270 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 38860071 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 38860072 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 317518566 # Number of instructions fetch has processed
system.cpu.fetch.Branches 41739250 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 23471784 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 70794265 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6760095 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 21559516 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.BlockedCycles 21559517 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 37487912 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 519564 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 136324280 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 37487913 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 519565 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 136324281 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.989165 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.456365 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 66156807 48.53% 48.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 66156808 48.53% 48.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 6761816 4.96% 53.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 5641032 4.14% 57.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6022575 4.42% 62.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 136324280 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 136324281 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.305704 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.325548 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 45389084 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 16729555 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 16729556 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 66615921 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 2549925 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 5039795 # Number of cycles decode is squashing
system.cpu.rename.IdleCycles 50891753 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1911896 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 347462 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 63595531 # Number of cycles rename is running
+system.cpu.rename.RunCycles 63595532 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 14537843 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 393365757 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 393365758 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1668272 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 10291112 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 1086 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 431881386 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2329985493 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1257436076 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 431881387 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2329985497 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1257436080 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1072549417 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384584833 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 47296553 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 47296554 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 14334 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 14333 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 36353497 # count of insts added to the skid buffer
system.cpu.iq.iqSquashedInstsExamined 34098402 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 84823076 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 961 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 136324280 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 136324281 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.743078 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.023492 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24852306 18.23% 18.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24852307 18.23% 18.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 19962410 14.64% 32.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 20554570 15.08% 47.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 18105177 13.28% 61.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 136324280 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 136324281 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 8956 0.05% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available
system.cpu.iq.rate 2.738846 # Inst issue rate
system.cpu.iq.fu_busy_cnt 17797690 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.047594 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 653530496 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 653530497 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 287597541 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 249877083 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 249712453 # Number of floating instruction queue reads
system.cpu.iew.iewBlockCycles 281091 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 41482 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 383923458 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 951525 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 951526 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 103432229 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 91356063 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 14236 # Number of dispatched non-speculative instructions
system.cpu.rob.rob_reads 500559121 # The number of ROB reads
system.cpu.rob.rob_writes 772890927 # The number of ROB writes
system.cpu.timesIdled 6411 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 210652 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 210651 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273048375 # Number of Instructions Simulated
system.cpu.committedOps 349076099 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 273048375 # Number of Instructions Simulated
system.cpu.icache.demand_hits::total 37470862 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 37470862 # number of overall hits
system.cpu.icache.overall_hits::total 37470862 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 17049 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 17049 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 17049 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 17049 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 17049 # number of overall misses
-system.cpu.icache.overall_misses::total 17049 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 356549497 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 356549497 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 356549497 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 356549497 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 356549497 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 356549497 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 37487911 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 37487911 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 37487911 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 37487911 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 37487911 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 37487911 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 17050 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 17050 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 17050 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 17050 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 17050 # number of overall misses
+system.cpu.icache.overall_misses::total 17050 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 356620497 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 356620497 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 356620497 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 356620497 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 356620497 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 356620497 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 37487912 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 37487912 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 37487912 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 37487912 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 37487912 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 37487912 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000455 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000455 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000455 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000455 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000455 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000455 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20913.220541 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20913.220541 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20916.158182 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20916.158182 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20916.158182 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20916.158182 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 585 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1254 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1254 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1254 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1254 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1254 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1254 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1255 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1255 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1255 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1255 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1255 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1255 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15795 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15795 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15795 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1414 # number of replacements
-system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use
-system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
-system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
-system.cpu.dcache.overall_misses::total 25149 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
-system.cpu.dcache.writebacks::total 1040 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 3959.582107 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 3959.582108 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13162 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 5412 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.432003 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 367.644751 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 2774.541574 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 2774.541575 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 817.395782 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.011220 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.084672 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.data 4307 # number of overall misses
system.cpu.l2cache.overall_misses::total 7349 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 148332000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74801500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 223133500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74802000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 223134000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128955500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 128955500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 148332000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 203757000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 352089000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 203757500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 352089500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 148332000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 203757000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 352089000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 203757500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 352089500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15795 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1811 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 17606 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931445 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.359910 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48761.341223 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49471.891534 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.255160 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49472.222222 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.364954 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46137.924866 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46137.924866 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 47909.783644 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 47909.851681 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 47909.783644 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 47909.851681 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1414 # number of replacements
+system.cpu.dcache.tagsinuse 3122.405384 # Cycle average of tags in use
+system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3122.405384 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
+system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
+system.cpu.dcache.overall_misses::total 25149 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 164690500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 996644664 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 996644664 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 996644664 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 996644664 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.522986 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.522986 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39629.594179 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39629.594179 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
+system.cpu.dcache.writebacks::total 1040 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211724000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 211724000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211724000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 211724000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.280353 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.280353 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/gem5/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 20:00:53
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 00:23:14
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 624867585500 # Number of ticks simulated
final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 118271 # Simulator instruction rate (inst/s)
-host_op_rate 161069 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53384157 # Simulator tick rate (ticks/s)
-host_mem_usage 298364 # Number of bytes of host memory used
-host_seconds 11705.11 # Real time elapsed on the host
+host_inst_rate 53257 # Simulator instruction rate (inst/s)
+host_op_rate 72528 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24038469 # Simulator tick rate (ticks/s)
+host_mem_usage 255596 # Number of bytes of host memory used
+host_seconds 25994.48 # Real time elapsed on the host
sim_insts 1384379060 # Number of instructions simulated
sim_ops 1885333812 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 624867513500 # Total gap between requests
+system.physmem.totGap 624867514500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3316258619 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 18090208619 # Sum of mem lat for all requests
+system.physmem.totQLat 3316258119 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 18090208119 # Sum of mem lat for all requests
system.physmem.totBusLat 1899312000 # Total cycles spent in databus access
system.physmem.totBankLat 12874638000 # Total cycles spent in bank access
system.physmem.avgQLat 6984.13 # Average queueing delay per request
system.physmem.avgBankLat 27114.32 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 38098.45 # Average memory access latency
+system.physmem.avgMemAccLat 38098.44 # Average memory access latency
system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 354123352 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 354123353 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed
system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 133000859 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.BlockedCycles 133000861 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 564 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 333825475 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10767149 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1215073364 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 333825476 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 10767150 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1215073366 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 614410423 50.57% 50.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 614410425 50.57% 50.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1215073364 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 1215073366 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 105461627 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 105461629 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing
system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 540789818 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 71593101 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2966286071 # Number of instructions processed by rename
+system.cpu.rename.RunCycles 540789819 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 71593102 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2966286080 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2940514356 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14121260893 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13550785312 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 2940514359 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14121260922 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13550785341 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 947360714 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 947360717 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer
system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1215073364 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 1215073366 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 379121475 31.20% 31.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 379121477 31.20% 31.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1215073364 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1215073366 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available
system.cpu.iq.rate 1.949510 # Inst issue rate
system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6066277406 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 6066277408 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads
system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1409393 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 1409402 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions
system.cpu.rob.rob_reads 3801294955 # The number of ROB reads
system.cpu.rob.rob_writes 5735909866 # The number of ROB writes
system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 34661808 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 34661806 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384379060 # Number of Instructions Simulated
system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated
system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits
system.cpu.icache.overall_hits::total 333794637 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 30836 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 30836 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 30836 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 30836 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 30836 # number of overall misses
-system.cpu.icache.overall_misses::total 30836 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 469688998 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 469688998 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 469688998 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 469688998 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 469688998 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 469688998 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 333825473 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 333825473 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 333825473 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 333825473 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 333825473 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 333825473 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 30837 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 30837 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 30837 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 30837 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 30837 # number of overall misses
+system.cpu.icache.overall_misses::total 30837 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 469758998 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 469758998 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 469758998 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 469758998 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 469758998 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 469758998 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 333825474 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 333825474 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 333825474 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 333825474 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 333825474 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 333825474 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15231.839344 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15231.839344 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15231.839344 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15231.839344 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15233.615397 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15233.615397 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15233.615397 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15233.615397 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2272 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2272 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2272 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2272 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2272 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2272 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2273 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2273 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2273 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2273 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2273 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2273 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379117998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 379117998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379117998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 379117998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379117998 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 379117998 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379116998 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 379116998 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379116998 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 379116998 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379116998 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 379116998 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.580801 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.580801 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.545792 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.545792 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1532987 # number of replacements
-system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
-system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
-system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
-system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369161000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 67369161000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954942470 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 39954942470 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 107324103470 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 107324103470 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 107324103470 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 107324103470 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38495.250319 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38495.250319 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
-system.cpu.dcache.writebacks::total 96322 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884239500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884239500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478488500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478488500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 442193 # number of replacements
system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks.
system.cpu.l2cache.overall_misses::cpu.inst 2433 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 472565 # number of overall misses
system.cpu.l2cache.overall_misses::total 474998 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128014500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837930500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128013500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837931500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 25965945000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242870000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 3242870000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 128014500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242869000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3242869000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 128013500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 29080800500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 29208815000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 128014500 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total 29208814000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 128013500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 29080800500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 29208815000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 29208814000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 24232 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1464568 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1488800 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100404 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.307443 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.304229 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.906289 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.351956 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.495273 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.354416 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 63498.217273 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.365560 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.365560 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.350425 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.350425 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 61492.501021 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 61492.498916 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 61492.501021 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 61492.498916 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.data 472543 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97294812 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693796850 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791091662 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693797350 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791092162 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43304330 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43304330 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390499504 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390499504 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390498504 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390498504 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97294812 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084296354 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 23181591166 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084295854 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 23181590666 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97294812 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084296354 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 23181591166 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084295854 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 23181590666 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277535 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.304214 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.547100 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.131845 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.396826 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.133075 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.398048 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.124981 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.124981 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.109847 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.109847 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1532987 # number of replacements
+system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
+system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
+system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
+system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369162000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 67369162000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954940470 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 39954940470 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 107324102470 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 107324102470 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 107324102470 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 107324102470 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.508124 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.508124 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.989278 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.989278 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38495.249960 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38495.249960 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
+system.cpu.dcache.writebacks::total 96322 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884240500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884240500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478487500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478487500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.142233 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.142233 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.693725 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.693725 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/gem5/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 20:20:38
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 00:36:17
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 26292466000 # Number of ticks simulated
final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 139577 # Simulator instruction rate (inst/s)
-host_op_rate 198063 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51742306 # Simulator tick rate (ticks/s)
-host_mem_usage 305460 # Number of bytes of host memory used
-host_seconds 508.14 # Real time elapsed on the host
+host_inst_rate 43892 # Simulator instruction rate (inst/s)
+host_op_rate 62284 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16271073 # Simulator tick rate (ticks/s)
+host_mem_usage 263196 # Number of bytes of host memory used
+host_seconds 1615.90 # Real time elapsed on the host
sim_insts 70925094 # Number of instructions simulated
sim_ops 100644341 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 26292446500 # Total gap between requests
+system.physmem.totGap 26292447500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 4868161034 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 6756433034 # Sum of mem lat for all requests
+system.physmem.totQLat 4868163034 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 6756435034 # Sum of mem lat for all requests
system.physmem.totBusLat 515096000 # Total cycles spent in databus access
system.physmem.totBankLat 1373176000 # Total cycles spent in bank access
-system.physmem.avgQLat 37803.91 # Average queueing delay per request
+system.physmem.avgQLat 37803.93 # Average queueing delay per request
system.physmem.avgBankLat 10663.46 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 52467.37 # Average memory access latency
+system.physmem.avgMemAccLat 52467.38 # Average memory access latency
system.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 12549160 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 12549163 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 10606958 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.BlockedCycles 10606959 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11672224 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 180779 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 46048900 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.587178 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 11672225 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 180780 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 46048903 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.587177 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24897026 54.07% 54.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24897029 54.07% 54.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46048900 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 46048903 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8956467 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 8956470 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 19461806 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing
system.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 926852 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19086495 # Number of cycles rename is running
+system.cpu.rename.serializeStallCycles 926854 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19086496 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 114852318 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 114852319 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115176508 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 529186359 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 529181674 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 115176509 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 529186363 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 529181678 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 16015892 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 16015893 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 24809 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer
system.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 46048900 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 46048903 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10795987 23.44% 23.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10795990 23.44% 23.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 46048900 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 46048903 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available
system.cpu.iq.rate 2.038690 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 263189734 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 263189737 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads
system.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 290951 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 290952 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions
system.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 44431401 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 44431403 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 15343377 34.53% 34.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 15343379 34.53% 34.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 44431401 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 44431403 # Number of insts commited each cycle
system.cpu.commit.committedInsts 70930646 # Number of instructions committed
system.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
system.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 149890854 # The number of ROB reads
+system.cpu.rob.rob_reads 149890856 # The number of ROB reads
system.cpu.rob.rob_writes 224611140 # The number of ROB writes
system.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 6536033 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 6536030 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70925094 # Number of Instructions Simulated
system.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 70925094 # Number of Instructions Simulated
system.cpu.misc_regfile_reads 49170129 # number of misc regfile reads
system.cpu.misc_regfile_writes 38826 # number of misc regfile writes
system.cpu.icache.replacements 30543 # number of replacements
-system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1820.333458 # Cycle average of tags in use
system.cpu.icache.total_refs 11635566 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1820.333452 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1820.333458 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits
system.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits
system.cpu.icache.overall_hits::total 11635567 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 36657 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 36657 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 36657 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 36657 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 36657 # number of overall misses
-system.cpu.icache.overall_misses::total 36657 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 709011999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 709011999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 709011999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 709011999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 709011999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 709011999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11672224 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11672224 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11672224 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11672224 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11672224 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11672224 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 36658 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 36658 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 36658 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 36658 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 36658 # number of overall misses
+system.cpu.icache.overall_misses::total 36658 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 709083999 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 709083999 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 709083999 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 709083999 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 709083999 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 709083999 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11672225 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11672225 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11672225 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11672225 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11672225 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11672225 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003141 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.003141 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.003141 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.003141 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.003141 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.003141 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19341.790081 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19341.790081 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19341.790081 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19341.790081 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19343.226554 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19343.226554 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19343.226554 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19343.226554 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32884 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 32884 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 32884 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 32884 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 32884 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 32884 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580604499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 580604499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580604499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 580604499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580604499 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 580604499 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580605499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 580605499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580605499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 580605499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580605499 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 580605499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002817 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.002817 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.139734 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.139734 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.170144 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.170144 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 158306 # number of replacements
-system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use
-system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
-system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
-system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
-system.cpu.dcache.writebacks::total 129052 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 95650 # number of replacements
-system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 30136.955699 # Cycle average of tags in use
system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.709468 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 26880.895911 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 1379.489976 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 1876.569805 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1379.489982 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1876.569807 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.820340 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.042099 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.057268 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 124171 # number of overall misses
system.cpu.l2cache.overall_misses::total 128851 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269870000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664898500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1934768500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269871000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664900000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1934771000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8091962000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8091962000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 269870000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 9756860500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 10026730500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 269870000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 9756860500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 10026730500 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 269871000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 9756862000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 10026733000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 269871000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 9756862000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 10026733000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 32373 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55368 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 87741 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144565 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.764590 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.661538 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.529915 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.727812 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.332581 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.743590 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.796258 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.426584 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 77.181208 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 77.181208 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79134.349085 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79134.349085 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77816.474067 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77816.474067 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77816.493469 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77816.493469 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 124113 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 128777 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210181444 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210183444 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1389842080 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600023524 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600025524 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2980298 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2980298 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6821241683 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6821241683 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210181444 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210183444 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8211083763 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 8421265207 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210181444 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 8421267207 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210183444 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8211083763 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 8421265207 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 8421267207 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394759 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.302265 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.661158 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45064.632075 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45065.060892 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63587.961751 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.437163 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.512575 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66707.495726 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66707.495726 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 158306 # number of replacements
+system.cpu.dcache.tagsinuse 4072.986678 # Cycle average of tags in use
+system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4072.986678 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
+system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
+system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670086500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4670086500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 124709259481 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 124709259481 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 124709259481 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 124709259481 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.307299 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.307299 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72956.568898 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72956.568898 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
+system.cpu.dcache.writebacks::total 129052 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060279000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060279000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313871492 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10313871492 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313871492 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10313871492 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.809104 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.809104 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/gem5/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 20:33:15
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 00:51:58
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 506342716000 because target called exit()
+Exiting @ tick 506577346000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.506343 # Number of seconds simulated
-sim_ticks 506342716000 # Number of ticks simulated
-final_tick 506342716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.506577 # Number of seconds simulated
+sim_ticks 506577346000 # Number of ticks simulated
+final_tick 506577346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 168217 # Simulator instruction rate (inst/s)
-host_op_rate 187658 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 55145312 # Simulator tick rate (ticks/s)
-host_mem_usage 540496 # Number of bytes of host memory used
-host_seconds 9181.97 # Real time elapsed on the host
-sim_insts 1544563043 # Number of instructions simulated
-sim_ops 1723073855 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 143751360 # Number of bytes read from this memory
-system.physmem.bytes_read::total 143799104 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 70435456 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70435456 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2246115 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2246861 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1100554 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1100554 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 94292 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 283901309 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 283995601 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 94292 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 94292 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 139106289 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 139106289 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 139106289 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 94292 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 283901309 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 423101890 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 2246861 # Total number of read requests seen
-system.physmem.writeReqs 1100554 # Total number of write requests seen
-system.physmem.cpureqs 3347415 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 143799104 # Total number of bytes read from memory
-system.physmem.bytesWritten 70435456 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 143799104 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 70435456 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 613 # Number of read reqs serviced by write Q
+host_inst_rate 78526 # Simulator instruction rate (inst/s)
+host_op_rate 87602 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 25754624 # Simulator tick rate (ticks/s)
+host_mem_usage 525748 # Number of bytes of host memory used
+host_seconds 19669.37 # Real time elapsed on the host
+sim_insts 1544563048 # Number of instructions simulated
+sim_ops 1723073860 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 47872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 143709504 # Number of bytes read from this memory
+system.physmem.bytes_read::total 143757376 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 47872 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 47872 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 70427136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 70427136 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 748 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2245461 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2246209 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1100424 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1100424 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 94501 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 283687190 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 283781691 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 94501 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 94501 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 139025435 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 139025435 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 139025435 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 94501 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 283687190 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 422807126 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2246209 # Total number of read requests seen
+system.physmem.writeReqs 1100424 # Total number of write requests seen
+system.physmem.cpureqs 3346633 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 143757376 # Total number of bytes read from memory
+system.physmem.bytesWritten 70427136 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 143757376 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 70427136 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 648 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 139880 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 143856 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 141905 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 140877 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 137960 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 140233 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 141491 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 140982 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 141233 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 139496 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 140455 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 140890 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 137116 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 141034 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 138952 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 139888 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 69217 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 70379 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 69592 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 68832 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 67727 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 68464 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 68713 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 68501 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 68243 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 68230 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 68643 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 68550 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 67188 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 70321 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 69053 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 68901 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 139859 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 143718 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 141709 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 141024 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 137951 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 140151 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 141411 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 141047 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 141131 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 139616 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 140441 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 140596 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 136994 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 141023 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 138860 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 140030 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 69285 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 70316 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 69579 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 68829 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 67740 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 68386 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 68704 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 68489 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 68246 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 68330 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 68656 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 68488 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 67093 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 70319 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 69051 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 68913 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 506342647500 # Total gap between requests
+system.physmem.totGap 506577272500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 2246861 # Categorize read packet sizes
+system.physmem.readPktSize::6 2246209 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 1100554 # categorize write packet sizes
+system.physmem.writePktSize::6 1100424 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1577627 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 446326 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 156341 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 65934 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1577632 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 445457 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 156427 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 66028 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 45498 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 47479 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 47800 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 47843 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 45454 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 47483 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 47799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 47836 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 47845 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 47845 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 47845 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 47845 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 47845 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 47845 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 47845 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 47844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 2391 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 362 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 27053022176 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 102785772176 # Sum of mem lat for all requests
-system.physmem.totBusLat 8984992000 # Total cycles spent in databus access
-system.physmem.totBankLat 66747758000 # Total cycles spent in bank access
-system.physmem.avgQLat 12043.65 # Average queueing delay per request
-system.physmem.avgBankLat 29715.22 # Average bank access latency per request
+system.physmem.totQLat 27034566792 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 102738360792 # Sum of mem lat for all requests
+system.physmem.totBusLat 8982244000 # Total cycles spent in databus access
+system.physmem.totBankLat 66721550000 # Total cycles spent in bank access
+system.physmem.avgQLat 12039.11 # Average queueing delay per request
+system.physmem.avgBankLat 29712.64 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 45758.87 # Average memory access latency
-system.physmem.avgRdBW 284.00 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 139.11 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 284.00 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 139.11 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 45751.76 # Average memory access latency
+system.physmem.avgRdBW 283.78 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 139.03 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 283.78 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 139.03 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.64 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.20 # Average read queue length over time
-system.physmem.avgWrQLen 10.20 # Average write queue length over time
-system.physmem.readRowHits 914443 # Number of row buffer hits during reads
-system.physmem.writeRowHits 189193 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 17.19 # Row buffer hit rate for writes
-system.physmem.avgGap 151263.78 # Average gap between requests
+system.physmem.avgWrQLen 10.83 # Average write queue length over time
+system.physmem.readRowHits 914455 # Number of row buffer hits during reads
+system.physmem.writeRowHits 188951 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes
+system.physmem.avgGap 151369.23 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 1012685433 # number of cpu cycles simulated
+system.cpu.numCycles 1013154693 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 301954621 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 248216809 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 15201913 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 174080905 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 160275912 # Number of BTB hits
+system.cpu.BPredUnit.lookups 302078234 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 248282516 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 15228940 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 174133457 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 160366522 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 17543051 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 217 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 296171329 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2177000343 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 301954621 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 177818963 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 433079666 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 86445035 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 152984584 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 67 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 286733341 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5527590 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 951199831 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.533171 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.216208 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 17581353 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 196 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 296396923 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2177678223 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 302078234 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 177947875 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 433295900 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 86556891 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 152970163 # Number of cycles fetch has spent blocked
+system.cpu.fetch.PendingTrapStallCycles 65 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 286931136 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5530103 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 951710373 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.532755 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.215871 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 518120232 54.47% 54.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 25036737 2.63% 57.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 39011944 4.10% 61.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 48247673 5.07% 66.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 42552998 4.47% 70.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46316076 4.87% 75.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38402395 4.04% 79.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18552878 1.95% 81.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 174958898 18.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 518414544 54.47% 54.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 25023553 2.63% 57.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 39078902 4.11% 61.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 48295865 5.07% 66.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 42590853 4.48% 70.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46358394 4.87% 75.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38409844 4.04% 79.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 18541861 1.95% 81.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 174996557 18.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 951199831 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.298172 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.149730 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 327457175 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 131287653 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 403449648 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20041830 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 68963525 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46005772 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2358153457 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2386 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 68963525 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 350605393 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 61238175 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 13721 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 398828619 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 71550398 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2297300888 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 126992 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5036459 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 58395724 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2272291937 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10608987199 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 10608983762 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 3437 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 565971975 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 462 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 459 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 158423553 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 623142693 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 220479196 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 86005454 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 70775057 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2196663707 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 506 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2016028881 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3978647 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 469035072 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1108322137 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 332 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 951199831 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.119459 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.906333 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 951710373 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.298156 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.149403 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 327700398 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 131274030 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 403657963 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 20031323 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 69046659 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46033752 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2358943633 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2468 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 69046659 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 350846153 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 61254563 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 16168 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 399028257 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 71518573 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2298097948 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 126905 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5030989 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 58378290 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 21 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2273047323 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10612493947 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10612490107 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 3840 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1706319970 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 566727353 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 579 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 576 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 158294547 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 623264205 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 220545745 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 86083879 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 71111807 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2197176983 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 617 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2016362984 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3976433 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 469561245 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1109303126 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 442 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 951710373 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.118673 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.906088 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 271401880 28.53% 28.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 150954811 15.87% 44.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 160752249 16.90% 61.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 119324059 12.54% 73.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 124037458 13.04% 86.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 73914082 7.77% 94.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 38408733 4.04% 98.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 9827717 1.03% 99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2578842 0.27% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 271681104 28.55% 28.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 151029292 15.87% 44.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 160860951 16.90% 61.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 119423719 12.55% 73.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 124040655 13.03% 86.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 73844505 7.76% 94.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 38423887 4.04% 98.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 9837914 1.03% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2568346 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 951199831 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 951710373 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 872713 3.66% 3.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5800 0.02% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 18252533 76.46% 80.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4741041 19.86% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 884251 3.71% 3.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5803 0.02% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 18260912 76.52% 80.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4713024 19.75% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1235530867 61.29% 61.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 926678 0.05% 61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1235730188 61.29% 61.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 925294 0.05% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 64 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 25 0.00% 61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 11 0.00% 61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 27 0.00% 61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 13 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 586539458 29.09% 90.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193031781 9.57% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 586669934 29.10% 90.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193037461 9.57% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2016028881 # Type of FU issued
-system.cpu.iq.rate 1.990775 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 23872087 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011841 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5011107955 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2665888919 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1956633156 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 668 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 148 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2039900782 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 186 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 64729425 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2016362984 # Type of FU issued
+system.cpu.iq.rate 1.990183 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 23863990 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.011835 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5012276382 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2666928163 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1956898360 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 382 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 744 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2040226783 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 191 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 64738379 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 137215920 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 273705 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 192829 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 45632147 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 137337431 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 268034 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 192473 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 45698695 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 3804190 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 3808296 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 68963525 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27139108 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1495868 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2196664320 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 6096220 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 623142693 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 220479196 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 440 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 474677 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 89373 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 192829 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8139641 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 9611816 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 17751457 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1986428018 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 573006458 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 29600863 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 69046659 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27170871 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1494320 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2197177695 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 6112052 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 623264205 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 220545745 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 552 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 473344 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 89494 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 192473 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 8164015 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 9611639 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 17775654 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1986719031 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 573114745 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 29643953 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 107 # number of nop insts executed
-system.cpu.iew.exec_refs 763162577 # number of memory reference insts executed
-system.cpu.iew.exec_branches 238305506 # Number of branches executed
-system.cpu.iew.exec_stores 190156119 # Number of stores executed
-system.cpu.iew.exec_rate 1.961545 # Inst execution rate
-system.cpu.iew.wb_sent 1965069993 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1956633304 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1295741844 # num instructions producing a value
-system.cpu.iew.wb_consumers 2060291868 # num instructions consuming a value
+system.cpu.iew.exec_nop 95 # number of nop insts executed
+system.cpu.iew.exec_refs 763276448 # number of memory reference insts executed
+system.cpu.iew.exec_branches 238352176 # Number of branches executed
+system.cpu.iew.exec_stores 190161703 # Number of stores executed
+system.cpu.iew.exec_rate 1.960924 # Inst execution rate
+system.cpu.iew.wb_sent 1965347769 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1956898514 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1295796153 # num instructions producing a value
+system.cpu.iew.wb_consumers 2060480328 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.932123 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.628912 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.931490 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.628881 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 473688675 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 15201254 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 882236307 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.953075 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.733441 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 474201695 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 175 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 15228277 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 882663714 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.952130 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.732822 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 395033936 44.78% 44.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 192005187 21.76% 66.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 72432268 8.21% 74.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35243986 3.99% 78.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18949129 2.15% 80.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30789454 3.49% 84.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 20064460 2.27% 86.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 11401450 1.29% 87.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106316437 12.05% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 395325741 44.79% 44.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 192113195 21.77% 66.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 72479892 8.21% 74.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 35250909 3.99% 78.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 18971392 2.15% 80.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 30754959 3.48% 84.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 20068273 2.27% 86.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 11416653 1.29% 87.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106282700 12.04% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 882236307 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 1544563061 # Number of instructions committed
-system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 882663714 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 1544563066 # Number of instructions committed
+system.cpu.commit.committedOps 1723073878 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 660773822 # Number of memory references committed
-system.cpu.commit.loads 485926773 # Number of loads committed
+system.cpu.commit.refs 660773824 # Number of memory references committed
+system.cpu.commit.loads 485926774 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
-system.cpu.commit.branches 213462430 # Number of branches committed
+system.cpu.commit.branches 213462431 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1536941861 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106316437 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106282700 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2972681819 # The number of ROB reads
-system.cpu.rob.rob_writes 4462636284 # The number of ROB writes
-system.cpu.timesIdled 1007749 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 61485602 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1544563043 # Number of Instructions Simulated
-system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated
-system.cpu.cpi 0.655645 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.655645 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.525215 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.525215 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 9949187154 # number of integer regfile reads
-system.cpu.int_regfile_writes 1936551418 # number of integer regfile writes
-system.cpu.fp_regfile_reads 155 # number of floating regfile reads
-system.cpu.fp_regfile_writes 154 # number of floating regfile writes
-system.cpu.misc_regfile_reads 737521382 # number of misc regfile reads
-system.cpu.misc_regfile_writes 132 # number of misc regfile writes
-system.cpu.icache.replacements 22 # number of replacements
-system.cpu.icache.tagsinuse 625.107966 # Cycle average of tags in use
-system.cpu.icache.total_refs 286732187 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 775 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 369977.015484 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 2973655988 # The number of ROB reads
+system.cpu.rob.rob_writes 4463745378 # The number of ROB writes
+system.cpu.timesIdled 1007703 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 61444320 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 1544563048 # Number of Instructions Simulated
+system.cpu.committedOps 1723073860 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1544563048 # Number of Instructions Simulated
+system.cpu.cpi 0.655949 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.655949 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.524509 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.524509 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 9950552971 # number of integer regfile reads
+system.cpu.int_regfile_writes 1936868290 # number of integer regfile writes
+system.cpu.fp_regfile_reads 164 # number of floating regfile reads
+system.cpu.fp_regfile_writes 170 # number of floating regfile writes
+system.cpu.misc_regfile_reads 737621516 # number of misc regfile reads
+system.cpu.misc_regfile_writes 134 # number of misc regfile writes
+system.cpu.icache.replacements 23 # number of replacements
+system.cpu.icache.tagsinuse 625.920238 # Cycle average of tags in use
+system.cpu.icache.total_refs 286929961 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 368331.143774 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 625.107966 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.305228 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.305228 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 286732187 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 286732187 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 286732187 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 286732187 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 286732187 # number of overall hits
-system.cpu.icache.overall_hits::total 286732187 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses
-system.cpu.icache.overall_misses::total 1154 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 59543000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 59543000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 59543000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 59543000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 59543000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 59543000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 286733341 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 286733341 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 286733341 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 286733341 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 286733341 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 286733341 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 625.920238 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.305625 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.305625 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 286929961 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 286929961 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 286929961 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 286929961 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 286929961 # number of overall hits
+system.cpu.icache.overall_hits::total 286929961 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1175 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1175 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1175 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1175 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1175 # number of overall misses
+system.cpu.icache.overall_misses::total 1175 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 61332500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 61332500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 61332500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 61332500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 61332500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 61332500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 286931136 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 286931136 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 286931136 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 286931136 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 286931136 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 286931136 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51597.053726 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 51597.053726 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 51597.053726 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 51597.053726 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 51597.053726 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 51597.053726 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52197.872340 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 52197.872340 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 52197.872340 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 52197.872340 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 52197.872340 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 52197.872340 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 379 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 379 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 379 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 379 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 379 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41824000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 41824000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41824000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 41824000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41824000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 41824000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42649000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 42649000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42649000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 42649000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42649000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 42649000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53966.451613 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53966.451613 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54748.395379 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54748.395379 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54748.395379 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54748.395379 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54748.395379 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54748.395379 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9598051 # number of replacements
-system.cpu.dcache.tagsinuse 4087.935978 # Cycle average of tags in use
-system.cpu.dcache.total_refs 655966956 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9602147 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 68.314613 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 3423729000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4087.935978 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 488912900 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 488912900 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 167053904 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 167053904 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 87 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 87 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 655966804 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 655966804 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 655966804 # number of overall hits
-system.cpu.dcache.overall_hits::total 655966804 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 11479195 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 11479195 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5532143 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5532143 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 17011338 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 17011338 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 17011338 # number of overall misses
-system.cpu.dcache.overall_misses::total 17011338 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 299504228000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 299504228000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 217114926916 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 217114926916 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 516619154916 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 516619154916 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 516619154916 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 516619154916 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 500392095 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 500392095 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 90 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 90 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 672978142 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 672978142 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 672978142 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 672978142 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022940 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.022940 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032054 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.032054 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025278 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025278 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025278 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025278 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26091.048022 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26091.048022 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39246.080030 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39246.080030 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30369.107646 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30369.107646 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 19754018 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 992148 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1171998 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.854993 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 15.371892 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3781955 # number of writebacks
-system.cpu.dcache.writebacks::total 3781955 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3770552 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3770552 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638638 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3638638 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7409190 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7409190 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7409190 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7409190 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708643 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7708643 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893505 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1893505 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9602148 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9602148 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9602148 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9602148 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170578712500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 170578712500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71843645589 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 71843645589 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242422358089 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 242422358089 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242422358089 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 242422358089 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22128.241313 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22128.241313 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.147282 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.147282 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 2214170 # number of replacements
-system.cpu.l2cache.tagsinuse 31523.647608 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 9246689 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 2243948 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 4.120723 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 20415148502 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14433.962078 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 20.520835 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 17069.164694 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.440490 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.000626 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.520910 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.962025 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 6288951 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 6288979 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 3781955 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 3781955 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 1067075 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 1067075 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 7356026 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 7356054 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 7356026 # number of overall hits
-system.cpu.l2cache.overall_hits::total 7356054 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 747 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 1419691 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1420438 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 826431 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 826431 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 747 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 2246122 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 2246869 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 747 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 2246122 # number of overall misses
-system.cpu.l2cache.overall_misses::total 2246869 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40761000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98155765500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 98196526500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58740659000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 58740659000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 40761000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 156896424500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 156937185500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 40761000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 156896424500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 156937185500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 7708642 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 7709417 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 3781955 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 3781955 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893506 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1893506 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 9602148 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 9602923 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 9602148 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 9602923 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963871 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184169 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.184247 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436455 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.436455 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963871 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.233919 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.233978 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963871 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.233919 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.233978 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54566.265060 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69138.823519 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69131.159896 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71077.511613 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71077.511613 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54566.265060 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69852.138263 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69847.056281 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54566.265060 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69852.138263 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69847.056281 # average overall miss latency
+system.cpu.l2cache.replacements 2213514 # number of replacements
+system.cpu.l2cache.tagsinuse 31523.929913 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 9246342 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2243293 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.121772 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 20414306502 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14436.839849 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 20.727036 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 17066.363028 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.440577 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.000633 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.520824 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.962034 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 6288773 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 6288803 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 3781738 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 3781738 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 1067182 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 1067182 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 7355955 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 7355985 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 7355955 # number of overall hits
+system.cpu.l2cache.overall_hits::total 7355985 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 749 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1419078 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1419827 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 826390 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 826390 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 749 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 2245468 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 2246217 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 749 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 2245468 # number of overall misses
+system.cpu.l2cache.overall_misses::total 2246217 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41559000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98096930500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 98138489500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58737447000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 58737447000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 41559000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 156834377500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 156875936500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 41559000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 156834377500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 156875936500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 779 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 7707851 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 7708630 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 3781738 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 3781738 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893572 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1893572 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 779 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 9601423 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 9602202 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 779 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 9601423 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 9602202 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961489 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184108 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.184187 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436419 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.436419 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961489 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.233868 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.233927 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961489 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.233868 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.233927 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55485.981308 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69127.229441 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69120.033286 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71077.151224 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71077.151224 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55485.981308 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69844.850828 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69840.062870 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55485.981308 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69844.850828 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69840.062870 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1100554 # number of writebacks
-system.cpu.l2cache.writebacks::total 1100554 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 1100424 # number of writebacks
+system.cpu.l2cache.writebacks::total 1100424 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419684 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1420430 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826431 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 826431 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 2246115 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 2246861 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 2246115 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 2246861 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31288684 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80209878843 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80241167527 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48317396987 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48317396987 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31288684 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128527275830 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 128558564514 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31288684 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128527275830 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 128558564514 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962581 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184168 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184246 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436455 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436455 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962581 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233918 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.233977 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962581 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233918 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.233977 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41941.935657 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56498.403055 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56490.758099 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58465.131375 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58465.131375 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41941.935657 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57222.037086 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57216.963806 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41941.935657 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57222.037086 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57216.963806 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 748 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419071 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1419819 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826390 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 826390 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 748 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2245461 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 2246209 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 748 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2245461 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 2246209 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32066173 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80158804465 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80190870638 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48314626333 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48314626333 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32066173 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128473430798 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 128505496971 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32066173 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128473430798 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 128505496971 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960205 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184107 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184186 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436419 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436419 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960205 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233868 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.233926 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960205 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233868 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.233926 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42869.215241 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56486.817407 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56479.643277 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58464.679308 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58464.679308 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42869.215241 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57214.723746 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57209.946613 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42869.215241 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57214.723746 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57209.946613 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9597327 # number of replacements
+system.cpu.dcache.tagsinuse 4087.938249 # Cycle average of tags in use
+system.cpu.dcache.total_refs 656067317 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9601423 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 68.330217 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 3424422000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4087.938249 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.998032 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.998032 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 489013498 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 489013498 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 167053663 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 167053663 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 90 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 90 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 66 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 66 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 656067161 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 656067161 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 656067161 # number of overall hits
+system.cpu.dcache.overall_hits::total 656067161 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 11472935 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 11472935 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 5532384 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 5532384 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 17005319 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 17005319 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 17005319 # number of overall misses
+system.cpu.dcache.overall_misses::total 17005319 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 299507112500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 299507112500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 217112545758 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 217112545758 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 516619658258 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 516619658258 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 516619658258 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 516619658258 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 500486433 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 500486433 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 93 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 93 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 66 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 66 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 673072480 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 673072480 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 673072480 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 673072480 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022924 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.022924 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032056 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.032056 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032258 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.032258 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025265 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025265 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025265 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025265 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26105.535550 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26105.535550 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39243.940001 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39243.940001 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30379.886332 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30379.886332 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30379.886332 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30379.886332 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 19797443 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 993226 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1172557 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.883992 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 15.388594 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 3781738 # number of writebacks
+system.cpu.dcache.writebacks::total 3781738 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3765084 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3765084 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638812 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3638812 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7403896 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7403896 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7403896 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7403896 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707851 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7707851 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893572 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1893572 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9601423 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9601423 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9601423 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9601423 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170518232500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 170518232500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71841286448 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 71841286448 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242359518948 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 242359518948 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242359518948 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 242359518948 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22122.668497 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22122.668497 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37939.558912 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37939.558912 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.041617 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.041617 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.041617 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.041617 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/gem5/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 20:48:26
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 01:10:37
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 74245032000 # Number of ticks simulated
final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 131550 # Simulator instruction rate (inst/s)
-host_op_rate 144033 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56674428 # Simulator tick rate (ticks/s)
-host_mem_usage 280244 # Number of bytes of host memory used
-host_seconds 1310.03 # Real time elapsed on the host
+host_inst_rate 44193 # Simulator instruction rate (inst/s)
+host_op_rate 48386 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19039219 # Simulator tick rate (ticks/s)
+host_mem_usage 236076 # Number of bytes of host memory used
+host_seconds 3899.58 # Real time elapsed on the host
sim_insts 172333441 # Number of instructions simulated
sim_ops 188686923 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 74245012500 # Total gap between requests
+system.physmem.totGap 74245013500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 12366785 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests
+system.physmem.totQLat 12368785 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 86368785 # Sum of mem lat for all requests
system.physmem.totBusLat 15172000 # Total cycles spent in databus access
system.physmem.totBankLat 58828000 # Total cycles spent in bank access
-system.physmem.avgQLat 3260.42 # Average queueing delay per request
+system.physmem.avgQLat 3260.95 # Average queueing delay per request
system.physmem.avgBankLat 15509.62 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 22770.05 # Average memory access latency
+system.physmem.avgMemAccLat 22770.57 # Average memory access latency
system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 19574218.96 # Average gap between requests
+system.physmem.avgGap 19574219.22 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 39671705 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed
system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.BlockedCycles 7321257 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 36859861 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1828380 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 148388374 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 68164461 45.94% 45.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 148388374 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 5988329 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing
system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running
+system.cpu.rename.RunCycles 70572281 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 371457493 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 631852669 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1582346871 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1565037380 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 333759858 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer
system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 148388374 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56153946 37.84% 37.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 148388374 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available
system.cpu.iq.rate 1.680459 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 647013012 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads
system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 786986 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions
system.cpu.rob.rob_reads 449048801 # The number of ROB reads
system.cpu.rob.rob_writes 679713725 # The number of ROB writes
system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 101691 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 172333441 # Number of Instructions Simulated
system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated
system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads
system.cpu.misc_regfile_writes 832204 # number of misc regfile writes
system.cpu.icache.replacements 2508 # number of replacements
-system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1347.136600 # Cycle average of tags in use
system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1347.136600 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits
system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits
system.cpu.icache.overall_hits::total 36854521 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses
-system.cpu.icache.overall_misses::total 5339 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 36859860 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 36859860 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 36859860 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 5340 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 5340 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 5340 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 5340 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 5340 # number of overall misses
+system.cpu.icache.overall_misses::total 5340 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 158697499 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 158697499 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 158697499 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 158697499 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 158697499 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 158697499 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 36859861 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 36859861 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 36859861 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 36859861 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 36859861 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 36859861 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29710.900730 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29710.900730 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29710.900730 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29710.900730 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29718.632772 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 29718.632772 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 29718.632772 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 29718.632772 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1102 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1102 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1102 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1102 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1102 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1102 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1103 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1103 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1103 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1103 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1103 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1103 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4237 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4237 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4237 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 57 # number of replacements
-system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use
-system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
-system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
-system.cpu.dcache.overall_misses::total 9552 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
-system.cpu.dcache.writebacks::total 18 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 1961.084990 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2727 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.834250 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 4.022996 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 1424.044648 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 533.017329 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1424.044661 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 533.017333 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.043458 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses
system.cpu.l2cache.overall_misses::total 3807 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96653500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35087500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 131741000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35089000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 131742500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46197000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 46197000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 96653500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 81284500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 177938000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 81286000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 177939500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 96653500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 81284500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 177938000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 81286000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 177939500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4235 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 771 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 5006 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.data 0.947141 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.625226 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47125.060946 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51523.494860 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.449488 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51525.697504 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.998536 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42973.953488 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42973.953488 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 46739.690045 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 46740.084056 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 46739.690045 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 46740.084056 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2048 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3793 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70387399 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26266459 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96653858 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70388399 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26267459 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96655858 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32716158 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32716158 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70387399 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58982617 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 129370016 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70387399 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58982617 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 129370016 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70388399 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58983617 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 129372016 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70388399 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58983617 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 129372016 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869001 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.542948 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.622927 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34368.847168 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39203.670149 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35560.654157 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34369.335449 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39205.162687 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35561.389993 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30433.635349 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30433.635349 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 57 # number of replacements
+system.cpu.dcache.tagsinuse 1406.445410 # Cycle average of tags in use
+system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1406.445410 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
+system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
+system.cpu.dcache.overall_misses::total 9552 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 82599500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 82599500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 375319996 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 375319996 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 375319996 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 375319996 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45062.465903 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 45062.465903 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39292.294389 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39292.294389 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
+system.cpu.dcache.writebacks::total 18 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36782500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 36782500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84192998 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 84192998 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84192998 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 84192998 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47707.522698 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47707.522698 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/gem5/dist/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:48:42
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 4 2013 21:20:54
+gem5 started Jan 4 2013 23:04:52
+gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
-Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
-Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 82648140000 # Number of ticks simulated
final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 58118 # Simulator instruction rate (inst/s)
-host_op_rate 97410 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36369167 # Simulator tick rate (ticks/s)
-host_mem_usage 286740 # Number of bytes of host memory used
-host_seconds 2272.48 # Real time elapsed on the host
+host_inst_rate 31465 # Simulator instruction rate (inst/s)
+host_op_rate 52738 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19690094 # Simulator tick rate (ticks/s)
+host_mem_usage 268216 # Number of bytes of host memory used
+host_seconds 4197.45 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221362961 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 82648108000 # Total gap between requests
+system.physmem.totGap 82648109000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 16873322 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 122447322 # Sum of mem lat for all requests
+system.physmem.totQLat 16873822 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests
system.physmem.totBusLat 21392000 # Total cycles spent in databus access
system.physmem.totBankLat 84182000 # Total cycles spent in bank access
-system.physmem.avgQLat 3155.07 # Average queueing delay per request
+system.physmem.avgQLat 3155.16 # Average queueing delay per request
system.physmem.avgBankLat 15740.84 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 22895.91 # Average memory access latency
+system.physmem.avgMemAccLat 22896.00 # Average memory access latency
system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 15454021.69 # Average gap between requests
+system.physmem.avgGap 15454021.88 # Average gap between requests
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 165296281 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 25830999 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed
system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 24446052 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 431778 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total)
system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
system.cpu.icache.replacements 4732 # number of replacements
-system.cpu.icache.tagsinuse 1624.168421 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use
system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1624.168421 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits
system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits
system.cpu.icache.overall_hits::total 24437101 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 8951 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 8951 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 8951 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 8951 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 8951 # number of overall misses
-system.cpu.icache.overall_misses::total 8951 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 259393998 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 259393998 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 259393998 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 259393998 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 259393998 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 259393998 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 24446052 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 24446052 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 24446052 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 24446052 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 24446052 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 24446052 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses
+system.cpu.icache.overall_misses::total 8952 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28979.331695 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28979.331695 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28979.331695 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28979.331695 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 676 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2096 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2096 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2096 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2096 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2096 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2096 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2097 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2097 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2097 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2097 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2097 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2097 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6855 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 6855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 6855 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 6855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 6855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 6855 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198301998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 198301998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198301998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 198301998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198301998 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 198301998 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000280 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.081400 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.081400 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.227279 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.227279 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 55 # number of replacements
-system.cpu.dcache.tagsinuse 1411.367255 # Cycle average of tags in use
-system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1411.367255 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits
-system.cpu.dcache.overall_hits::total 67560798 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses
-system.cpu.dcache.overall_misses::total 2513 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 37144500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 113997500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 113997500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 113997500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 113997500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.912769 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.912769 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45363.111819 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45363.111819 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 14 # number of writebacks
-system.cpu.dcache.writebacks::total 14 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95774000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 95774000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95774000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 95774000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53895.683453 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53895.683453 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 2509.913634 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2509.913640 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3332 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3792 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.878692 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 0.902701 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 2234.774408 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 274.236525 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 2234.774413 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 274.236526 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000028 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.068200 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.008369 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 3402 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1946 # number of overall misses
system.cpu.l2cache.overall_misses::total 5348 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158303000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 179980500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158304000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 179981000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68234000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 68234000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 158303000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 89911500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 248214500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 158303000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 89911500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 248214500 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 158304000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 89911000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 248215000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 158304000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 89911000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 248215000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6701 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 416 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7117 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.507685 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.981341 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.615845 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.333921 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56159.326425 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.331573 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.627866 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56158.031088 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.463569 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43739.743590 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43739.743590 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 46412.584144 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 46412.584144 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 46412.677636 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 46412.677636 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3402 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1946 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5348 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394483 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844598 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394983 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844098 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132239081 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1540154 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1540154 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48432493 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48432493 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394483 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65277091 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394983 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65276591 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 180671574 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394483 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65277091 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394983 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65276591 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 180671574 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927885 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.615845 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.601117 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43638.854922 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.748089 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43637.559585 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34910.000264 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31046.469872 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31046.469872 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 55 # number of replacements
+system.cpu.dcache.tagsinuse 1411.367257 # Cycle average of tags in use
+system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits
+system.cpu.dcache.overall_hits::total 67560798 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses
+system.cpu.dcache.overall_misses::total 2513 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 37144000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 113997000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 113997000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 113997000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 113997000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 14 # number of writebacks
+system.cpu.dcache.writebacks::total 14 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1
+clock=1000
dtb_filename=
early_kernel_symbols=false
+enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
-memories=system.physmem system.realview.nvmem
-midr_regval=890224640
+mem_ranges=0:134217727
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.bridge]
type=Bridge
-clock=1
+clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu0.tracer
width=1
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
[system.cpu0.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
[system.cpu0.interrupts]
type=ArmInterrupts
+[system.cpu0.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu0.itb]
type=ArmTLB
children=walker
[system.cpu0.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu1.tracer
width=1
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
[system.cpu1.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[7]
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
[system.cpu1.interrupts]
type=ArmInterrupts
+[system.cpu1.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu1.itb]
type=ArmTLB
children=walker
[system.cpu1.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[6]
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
-clock=1
+clock=1000
forward_snoops=false
-hash_delay=1
-hit_latency=50000
-is_top_level=false
+hit_latency=50
+is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=50000
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=92
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=4194304
-subblock_size=0
system=system
-tgts_per_mshr=16
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=true
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[2]
[system.realview.a9scu]
type=A9SCU
-clock=1
+clock=1000
pio_addr=520093696
pio_latency=100000
system=system
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
-clock=1
+clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
[system.realview.flash_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
[system.realview.gic]
type=Gic
-clock=1
+clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
[system.realview.kmi0]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
[system.realview.kmi1]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
[system.realview.l2x0_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
[system.realview.realview_io]
type=RealViewCtrl
-clock=1
+clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
[system.realview.rtc]
type=PL031
amba_id=3412017
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
[system.realview.timer0]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
[system.realview.timer1]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
[system.realview.uart]
type=Pl011
-clock=1
+clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
[system.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
width=8
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:07
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:29:32
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 912096763500 because m5_exit instruction encountered
sim_ticks 912096763500 # Number of ticks simulated
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1752000 # Simulator instruction rate (inst/s)
-host_op_rate 2255696 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25930494646 # Simulator tick rate (ticks/s)
-host_mem_usage 382232 # Number of bytes of host memory used
-host_seconds 35.17 # Real time elapsed on the host
+host_inst_rate 599236 # Simulator instruction rate (inst/s)
+host_op_rate 771515 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8869004975 # Simulator tick rate (ticks/s)
+host_mem_usage 384344 # Number of bytes of host memory used
+host_seconds 102.84 # Real time elapsed on the host
sim_insts 61625970 # Number of instructions simulated
sim_ops 79343340 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 6234996 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory
-system.physmem.bytes_read::total 49638308 # Number of bytes read from this memory
+system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 97494 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5082797 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 6835893 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 54422195 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 6854532 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 70662 # number of replacements
-system.l2c.tagsinuse 51560.217790 # Cycle average of tags in use
-system.l2c.total_refs 1623342 # Total number of references to valid blocks.
-system.l2c.sampled_refs 135814 # Sample count of references to valid blocks.
-system.l2c.avg_refs 11.952685 # Average number of references to valid blocks.
+system.l2c.replacements 70658 # number of replacements
+system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use
+system.l2c.total_refs 1623339 # Total number of references to valid blocks.
+system.l2c.sampled_refs 135810 # Sample count of references to valid blocks.
+system.l2c.avg_refs 11.953015 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 39276.104351 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4360.752038 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 2483.307369 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.599306 # Average percentage of cache occupancy
+system.l2c.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.066540 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.037892 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.786746 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.786745 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 58151 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 108363 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 233339 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1317469 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits
system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits
-system.l2c.overall_hits::cpu0.data 233339 # number of overall hits
+system.l2c.overall_hits::cpu0.data 233336 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits
system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits
system.l2c.overall_hits::cpu1.data 219723 # number of overall hits
-system.l2c.overall_hits::total 1317469 # number of overall hits
+system.l2c.overall_hits::total 1317466 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 92461 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 140833 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 98853 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses
-system.l2c.demand_misses::total 163287 # number of demand (read+write) misses
+system.l2c.demand_misses::total 163290 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses
-system.l2c.overall_misses::cpu0.data 98853 # number of overall misses
+system.l2c.overall_misses::cpu0.data 98856 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses
system.l2c.overall_misses::cpu1.data 53648 # number of overall misses
-system.l2c.overall_misses::total 163287 # number of overall misses
+system.l2c.overall_misses::total 163290 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses)
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.613902 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.565150 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.297578 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.110273 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.297578 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.110273 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed
-system.cpu0.icache.replacements 428547 # number of replacements
-system.cpu0.icache.tagsinuse 511.020000 # Cycle average of tags in use
+system.cpu0.icache.replacements 428546 # number of replacements
+system.cpu0.icache.tagsinuse 511.015216 # Cycle average of tags in use
system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 429059 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 69.480223 # Average number of references to valid blocks.
+system.cpu0.icache.sampled_refs 429058 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 69.480385 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.020000 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.998086 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.998086 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.998077 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1
+clock=1000
dtb_filename=
early_kernel_symbols=false
+enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
-memories=system.physmem system.realview.nvmem
-midr_regval=890224640
+mem_ranges=0:134217727
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.bridge]
type=Bridge
-clock=1
+clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu0.tracer
workload=
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
[system.cpu0.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
[system.cpu0.interrupts]
type=ArmInterrupts
+[system.cpu0.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu0.itb]
type=ArmTLB
children=walker
[system.cpu0.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu1.tracer
workload=
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
[system.cpu1.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[7]
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
[system.cpu1.interrupts]
type=ArmInterrupts
+[system.cpu1.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu1.itb]
type=ArmTLB
children=walker
[system.cpu1.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[6]
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
-clock=1
+clock=1000
forward_snoops=false
-hash_delay=1
-hit_latency=50000
-is_top_level=false
+hit_latency=50
+is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=50000
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=92
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=4194304
-subblock_size=0
system=system
-tgts_per_mshr=16
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=true
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[2]
[system.realview.a9scu]
type=A9SCU
-clock=1
+clock=1000
pio_addr=520093696
pio_latency=100000
system=system
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
-clock=1
+clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
[system.realview.flash_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
[system.realview.gic]
type=Gic
-clock=1
+clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
[system.realview.kmi0]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
[system.realview.kmi1]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
[system.realview.l2x0_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
[system.realview.realview_io]
type=RealViewCtrl
-clock=1
+clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
[system.realview.rtc]
type=PL031
amba_id=3412017
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
[system.realview.timer0]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
[system.realview.timer1]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
[system.realview.uart]
type=Pl011
-clock=1
+clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
[system.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
width=8
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:18
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:31:36
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1207290627000 because m5_exit instruction encountered
+Exiting @ tick 1182882156500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 1.182883 # Number of seconds simulated
-sim_ticks 1182883275000 # Number of ticks simulated
-final_tick 1182883275000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.182882 # Number of seconds simulated
+sim_ticks 1182882156500 # Number of ticks simulated
+final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 656929 # Simulator instruction rate (inst/s)
-host_op_rate 837075 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12645375755 # Simulator tick rate (ticks/s)
-host_mem_usage 400812 # Number of bytes of host memory used
-host_seconds 93.54 # Real time elapsed on the host
-sim_insts 61450949 # Number of instructions simulated
-sim_ops 78302298 # Number of ops (including micro ops) simulated
+host_inst_rate 184229 # Simulator instruction rate (inst/s)
+host_op_rate 234741 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3546252898 # Simulator tick rate (ticks/s)
+host_mem_usage 402168 # Number of bytes of host memory used
+host_seconds 333.56 # Real time elapsed on the host
+sim_insts 61450993 # Number of instructions simulated
+sim_ops 78299715 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4708212 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4780336 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62110052 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4085888 # Number of bytes written to this memory
+system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7113232 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 73638 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 74719 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6653924 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 63842 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 820678 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43879657 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3980285 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4041258 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52507338 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3454177 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6013469 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3454177 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43879657 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3994656 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 6586178 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 58520807 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6653924 # Total number of read requests seen
-system.physmem.writeReqs 820678 # Total number of write requests seen
-system.physmem.cpureqs 271841 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 425851136 # Total number of bytes read from memory
-system.physmem.bytesWritten 52523392 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62110052 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7113232 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6654451 # Total number of read requests seen
+system.physmem.writeReqs 821128 # Total number of write requests seen
+system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 425884864 # Total number of bytes read from memory
+system.physmem.bytesWritten 52552192 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 11752 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 415464 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50650 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1182878800500 # Total gap between requests
+system.physmem.totGap 1182877668000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6825 # Categorize read packet sizes
system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 159035 # Categorize read packet sizes
+system.physmem.readPktSize::6 159562 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 63842 # categorize write packet sizes
+system.physmem.writePktSize::6 64292 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 11752 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 6596894 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 41002 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 11213 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1803 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 662 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 504 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 410 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 308 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 169 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 127 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 108 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 67 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 40 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 574129 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 411417 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 411845 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 427327 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1182593 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1193140 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2312606 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 25343 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 15031 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 14611 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 14622 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 26114 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 14563 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 25574 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 2767 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2575 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 35697 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 35702 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 35702 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 35702 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3569461684 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 123099843684 # Sum of mem lat for all requests
-system.physmem.totBusLat 26615168000 # Total cycles spent in databus access
-system.physmem.totBankLat 92915214000 # Total cycles spent in bank access
-system.physmem.avgQLat 536.46 # Average queueing delay per request
-system.physmem.avgBankLat 13964.25 # Average bank access latency per request
+system.physmem.totQLat 123719908904 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 159121708904 # Sum of mem lat for all requests
+system.physmem.totBusLat 26617276000 # Total cycles spent in databus access
+system.physmem.totBankLat 8784524000 # Total cycles spent in bank access
+system.physmem.avgQLat 18592.42 # Average queueing delay per request
+system.physmem.avgBankLat 1320.12 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 18500.71 # Average memory access latency
-system.physmem.avgRdBW 360.01 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.01 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 23912.55 # Average memory access latency
+system.physmem.avgRdBW 360.04 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 52.54 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.53 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.10 # Average read queue length over time
-system.physmem.avgWrQLen 15.10 # Average write queue length over time
-system.physmem.readRowHits 6624970 # Number of row buffer hits during reads
-system.physmem.writeRowHits 788587 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.09 # Row buffer hit rate for writes
-system.physmem.avgGap 158253.08 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 68922 # number of replacements
-system.l2c.tagsinuse 53038.398444 # Cycle average of tags in use
-system.l2c.total_refs 1676342 # Total number of references to valid blocks.
-system.l2c.sampled_refs 134082 # Sample count of references to valid blocks.
-system.l2c.avg_refs 12.502364 # Average number of references to valid blocks.
+system.physmem.avgRdQLen 0.13 # Average read queue length over time
+system.physmem.avgWrQLen 15.12 # Average write queue length over time
+system.physmem.readRowHits 6628163 # Number of row buffer hits during reads
+system.physmem.writeRowHits 789308 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.61 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 96.12 # Row buffer hit rate for writes
+system.physmem.avgGap 158232.25 # Average gap between requests
+system.l2c.replacements 69442 # number of replacements
+system.l2c.tagsinuse 53039.972087 # Cycle average of tags in use
+system.l2c.total_refs 1672967 # Total number of references to valid blocks.
+system.l2c.sampled_refs 134589 # Sample count of references to valid blocks.
+system.l2c.avg_refs 12.430191 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 40183.482743 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 40188.045356 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000405 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.001414 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 3728.899373 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 4237.689144 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 2.742166 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 2823.942801 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 2061.640399 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.613151 # Average percentage of cache occupancy
+system.l2c.occ_blocks::cpu0.inst 3727.182104 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 4237.001170 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 2.742163 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 2823.633866 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 2061.365608 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.613221 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.056898 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.064662 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.056872 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.064652 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.043090 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.031458 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.809302 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 4216 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 1874 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 419651 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 206094 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 5524 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 1914 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 464156 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 143505 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1246934 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 571634 # number of Writeback hits
-system.l2c.Writeback_hits::total 571634 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 1136 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1711 # number of UpgradeReq hits
+system.l2c.occ_percent::cpu1.inst 0.043085 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.031454 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.809326 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker 4055 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 1843 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 419673 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 206158 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 5342 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 1844 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 464150 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 143311 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1246376 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 571308 # number of Writeback hits
+system.l2c.Writeback_hits::total 571308 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 1277 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 1841 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 215 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 99 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 314 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 56997 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 52866 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 109863 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 4216 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 1874 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 419651 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 263091 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 5524 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 1914 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 464156 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 196371 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1356797 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 4216 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 1874 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 419651 # number of overall hits
-system.l2c.overall_hits::cpu0.data 263091 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 5524 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 1914 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 464156 # number of overall hits
-system.l2c.overall_hits::cpu1.data 196371 # number of overall hits
-system.l2c.overall_hits::total 1356797 # number of overall hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 319 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 56678 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 52482 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 109160 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 4055 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 1843 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 419673 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 262836 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 5342 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 1844 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 464150 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 195793 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1355536 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 4055 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 1843 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 419673 # number of overall hits
+system.l2c.overall_hits::cpu0.data 262836 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 5342 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 1844 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 464150 # number of overall hits
+system.l2c.overall_hits::cpu1.data 195793 # number of overall hits
+system.l2c.overall_hits::total 1355536 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 7859 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 5736 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 7863 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 3621 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 22264 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 4681 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 3591 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 8272 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 561 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 470 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1031 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 67060 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 72161 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 139221 # number of ReadExReq misses
+system.l2c.ReadReq_misses::total 22271 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 4685 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 3595 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 8280 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 469 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1033 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 67153 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 72577 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 139730 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 74919 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 5736 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 75016 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 75782 # number of demand (read+write) misses
-system.l2c.demand_misses::total 161485 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 76198 # number of demand (read+write) misses
+system.l2c.demand_misses::total 162001 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses
-system.l2c.overall_misses::cpu0.data 74919 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 5736 # number of overall misses
+system.l2c.overall_misses::cpu0.data 75016 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses
-system.l2c.overall_misses::cpu1.data 75782 # number of overall misses
-system.l2c.overall_misses::total 161485 # number of overall misses
+system.l2c.overall_misses::cpu1.data 76198 # number of overall misses
+system.l2c.overall_misses::total 162001 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 67500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst 285527000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 405599500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 282793000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 402090500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 259776000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 211385500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1162672000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 12888997 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 11730499 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 24619496 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1705500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2384500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 4090000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 2999097972 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 3428190491 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 6427288463 # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 256949000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 210391000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1152607500 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 12566496 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 11726999 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 24293495 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1712000 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2362500 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 4074500 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 2978330461 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 3439869494 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 6418199955 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 67500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 285527000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 3404697472 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 282793000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 3380420961 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 259776000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 3639575991 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 7589960463 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 256949000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 3650260494 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 7570807455 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 67500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 285527000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 3404697472 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 282793000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 3380420961 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 259776000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 3639575991 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 7589960463 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 4217 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 1876 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 425384 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 213953 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 5528 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 1914 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 469200 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 147126 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1269198 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 571634 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 571634 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 5817 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 4166 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 9983 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1345 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 124057 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 125027 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 249084 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 4217 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 1876 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 425384 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 338010 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 5528 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 1914 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 469200 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 272153 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1518282 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 4217 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 1876 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 425384 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 338010 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 5528 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 1914 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 469200 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 272153 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1518282 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001066 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.013477 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.036732 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for ReadReq accesses
+system.l2c.overall_miss_latency::cpu1.inst 256949000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 3650260494 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 7570807455 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 4056 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 1845 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 425409 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 214021 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 5346 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 1844 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 469194 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 146932 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1268647 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 571308 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 571308 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 5962 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 4159 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 10121 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 573 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1352 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 123831 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 125059 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 248890 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 4056 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 1845 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 425409 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 337852 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 5346 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 1844 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 469194 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 271991 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1517537 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 4056 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 1845 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 425409 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 337852 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 5346 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 1844 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 469194 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 271991 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1517537 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000247 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001084 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.013483 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.036739 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000748 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010750 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.024612 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.017542 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.804710 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.861978 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.828609 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.722938 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826011 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.766543 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.540558 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.577163 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.558932 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.001066 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.013477 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.221647 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for demand accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.024644 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.017555 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785810 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.864390 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.818101 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.724005 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.818499 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.764053 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.542296 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.580342 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.561413 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000247 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.001084 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.013483 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.222038 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000748 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.010750 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.278454 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.106360 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.001066 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.013477 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.221647 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for overall accesses
+system.l2c.demand_miss_rate::cpu1.data 0.280149 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.106753 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000247 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.001084 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.013483 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.222038 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000748 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.010750 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.278454 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.106360 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.280149 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.106753 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 33750 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49804.116518 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 51609.555923 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49301.429568 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 51137.034211 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51501.982554 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 58377.658105 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52222.062522 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2753.470840 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3266.638541 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 2976.244681 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3040.106952 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5073.404255 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 3967.022308 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44722.606203 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47507.524716 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 46166.084592 # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 50941.514671 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 58103.010218 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 51753.738045 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2682.283031 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3262.030320 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 2933.996981 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3035.460993 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5037.313433 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 3944.336883 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44351.413355 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47396.137812 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 45932.870214 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 49804.116518 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 45445.046944 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 49301.429568 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 45062.666111 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 51501.982554 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 48026.919202 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 47001.024634 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 50941.514671 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 47904.938371 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 46733.090876 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 49804.116518 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 45445.046944 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 49301.429568 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 45062.666111 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 51501.982554 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 48026.919202 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 47001.024634 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 50941.514671 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 47904.938371 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 46733.090876 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 63842 # number of writebacks
-system.l2c.writebacks::total 63842 # number of writebacks
+system.l2c.writebacks::writebacks 64292 # number of writebacks
+system.l2c.writebacks::total 64292 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst 5732 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 7859 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst 5735 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 7863 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 3621 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 22263 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 4681 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 3591 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 8272 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 561 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 470 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 1031 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 67060 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 72161 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 139221 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 22270 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 4685 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 3595 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 8280 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 564 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 469 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 1033 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 67153 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 72577 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 139730 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 5732 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 74919 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 5735 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 75016 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 75782 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 161484 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 76198 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 162000 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 74919 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 5735 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 75016 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 75782 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 161484 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 76198 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 162000 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56002 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 42004 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 212718377 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 304840627 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 209968387 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 301307132 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 196008 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 195716490 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 165149154 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 878718662 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 46986078 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 35996056 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 82982134 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5623056 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4727457 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 10350513 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2155048026 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2506935370 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 4661983396 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 192920490 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 164158147 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 868648170 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47014106 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36048563 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 83062669 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5661057 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4707461 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 10368518 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2133484234 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2513381312 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 4646865546 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56002 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 42004 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 212718377 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 2459888653 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 209968387 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 2434791366 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 196008 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 195716490 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 2672084524 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 5540702058 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 192920490 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 2677539459 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 5515513716 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56002 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 42004 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 212718377 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 2459888653 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 209968387 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 2434791366 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 196008 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 195716490 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 2672084524 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 5540702058 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 192920490 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 2677539459 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 5515513716 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 197971583 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12452500109 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12453767609 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3031674 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154310795041 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 166964298407 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000517750 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209233939 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 9209751689 # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154319820043 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166974590909 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000478250 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214527645 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 9215005895 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 197971583 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13453017859 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13454245859 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3031674 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162520028980 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 176174050096 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036732 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162534347688 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 176189596804 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036739 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024612 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.804710 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.861978 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.828609 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.722938 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826011 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.766543 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540558 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577163 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.558932 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for demand accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024644 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.017554 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785810 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.864390 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.818101 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724005 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.818499 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764053 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542296 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.580342 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.561413 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.222038 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.278454 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.106360 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.280149 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.106752 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.222038 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.278454 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.106360 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.280149 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.106752 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38788.729737 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38319.614905 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45608.714167 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 39469.912501 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.615467 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.964355 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.689313 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10023.272727 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.419149 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.294859 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.117298 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34740.862377 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 33486.208230 # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45335.030931 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 39005.306242 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.027962 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.416690 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.723309 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.335106 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.230277 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10037.287512 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31770.497729 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34630.548411 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 33256.033393 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7072907 # DTB read hits
-system.cpu0.dtb.read_misses 3765 # DTB read misses
-system.cpu0.dtb.write_hits 5658426 # DTB write hits
-system.cpu0.dtb.write_misses 809 # DTB write misses
+system.cpu0.dtb.read_hits 7070111 # DTB read hits
+system.cpu0.dtb.read_misses 3764 # DTB read misses
+system.cpu0.dtb.write_hits 5656042 # DTB write hits
+system.cpu0.dtb.write_misses 804 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7076672 # DTB read accesses
-system.cpu0.dtb.write_accesses 5659235 # DTB write accesses
+system.cpu0.dtb.read_accesses 7073875 # DTB read accesses
+system.cpu0.dtb.write_accesses 5656846 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 12731333 # DTB hits
-system.cpu0.dtb.misses 4574 # DTB misses
-system.cpu0.dtb.accesses 12735907 # DTB accesses
-system.cpu0.itb.inst_hits 29570611 # ITB inst hits
+system.cpu0.dtb.hits 12726153 # DTB hits
+system.cpu0.dtb.misses 4568 # DTB misses
+system.cpu0.dtb.accesses 12730721 # DTB accesses
+system.cpu0.itb.inst_hits 29570310 # ITB inst hits
system.cpu0.itb.inst_misses 2205 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 29572816 # ITB inst accesses
-system.cpu0.itb.hits 29570611 # DTB hits
+system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses
+system.cpu0.itb.hits 29570310 # DTB hits
system.cpu0.itb.misses 2205 # DTB misses
-system.cpu0.itb.accesses 29572816 # DTB accesses
-system.cpu0.numCycles 2365766550 # number of cpu cycles simulated
+system.cpu0.itb.accesses 29572515 # DTB accesses
+system.cpu0.numCycles 2365764313 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 28872677 # Number of instructions committed
-system.cpu0.committedOps 37219640 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 33106294 # Number of integer alu accesses
+system.cpu0.committedInsts 28872367 # Number of instructions committed
+system.cpu0.committedOps 37211047 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 33098187 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
-system.cpu0.num_func_calls 1241693 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4373343 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 33106294 # number of integer instructions
+system.cpu0.num_func_calls 1241715 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4373222 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 33098187 # number of integer instructions
system.cpu0.num_fp_insts 3860 # number of float instructions
-system.cpu0.num_int_register_reads 190095681 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 36231150 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 190047206 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 36225366 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
-system.cpu0.num_mem_refs 13399479 # number of memory refs
-system.cpu0.num_load_insts 7410420 # Number of load instructions
-system.cpu0.num_store_insts 5989059 # Number of store instructions
-system.cpu0.num_idle_cycles 2224930438.354119 # Number of idle cycles
-system.cpu0.num_busy_cycles 140836111.645881 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles
+system.cpu0.num_mem_refs 13394441 # number of memory refs
+system.cpu0.num_load_insts 7407672 # Number of load instructions
+system.cpu0.num_store_insts 5986769 # Number of store instructions
+system.cpu0.num_idle_cycles 2224997657.358119 # Number of idle cycles
+system.cpu0.num_busy_cycles 140766655.641881 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.059502 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.940498 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 46695 # number of quiesce instructions executed
-system.cpu0.icache.replacements 425420 # number of replacements
-system.cpu0.icache.tagsinuse 509.627794 # Cycle average of tags in use
-system.cpu0.icache.total_refs 29144662 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 425932 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 68.425622 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed
+system.cpu0.icache.replacements 425445 # number of replacements
+system.cpu0.icache.tagsinuse 509.616014 # Cycle average of tags in use
+system.cpu0.icache.total_refs 29144335 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 425957 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 68.420838 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.627794 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.995367 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.995367 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 29144662 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 29144662 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 29144662 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 29144662 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 29144662 # number of overall hits
-system.cpu0.icache.overall_hits::total 29144662 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 425932 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 425932 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 425932 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 425932 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 425932 # number of overall misses
-system.cpu0.icache.overall_misses::total 425932 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794628000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5794628000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 5794628000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5794628000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 5794628000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5794628000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570594 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 29570594 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 29570594 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 29570594 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 29570594 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 29570594 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014404 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.014404 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014404 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.014404 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014404 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.014404 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.584769 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.584769 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13604.584769 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13604.584769 # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst 509.616014 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.995344 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.995344 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 29144335 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 29144335 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 29144335 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 29144335 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 29144335 # number of overall hits
+system.cpu0.icache.overall_hits::total 29144335 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses
+system.cpu0.icache.overall_misses::total 425958 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5792188000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5792188000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 5792188000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5792188000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5792188000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5792188000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570293 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 29570293 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 29570293 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 29570293 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 29570293 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 29570293 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.026096 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13598.026096 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13598.026096 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13598.026096 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425932 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 425932 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 425932 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 425932 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 425932 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 425932 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4942764000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4942764000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4942764000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4942764000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4942764000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4942764000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425958 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 425958 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 425958 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 425958 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 425958 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 425958 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4940272000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 4940272000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4940272000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 4940272000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4940272000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 4940272000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288882000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288882000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288882000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 288882000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014404 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.014404 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.014404 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11604.584769 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11598.026096 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 330832 # number of replacements
-system.cpu0.dcache.tagsinuse 453.835370 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 12275735 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 331344 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 37.048309 # Average number of references to valid blocks.
+system.cpu0.dcache.replacements 330355 # number of replacements
+system.cpu0.dcache.tagsinuse 453.331528 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 12270860 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 330867 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 37.086987 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 462692000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 453.835370 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.886397 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.886397 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 6602660 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 6602660 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 5353299 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5353299 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147927 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 147927 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149680 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 149680 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 11955959 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 11955959 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 11955959 # number of overall hits
-system.cpu0.dcache.overall_hits::total 11955959 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 227931 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 227931 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 141702 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 141702 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9328 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 9328 # number of LoadLockedReq misses
+system.cpu0.dcache.occ_blocks::cpu0.data 453.331528 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.885413 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.885413 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 6599943 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 6599943 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 5351121 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 5351121 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147941 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 147941 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149661 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 149661 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 11951064 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 11951064 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 11951064 # number of overall hits
+system.cpu0.dcache.overall_hits::total 11951064 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 227863 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 227863 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 141515 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 141515 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9301 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 9301 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 369633 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 369633 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 369633 # number of overall misses
-system.cpu0.dcache.overall_misses::total 369633 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3133125500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 3133125500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4126730000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 4126730000 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88286000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 88286000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44416500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 44416500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 7259855500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 7259855500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 7259855500 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 7259855500 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 6830591 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 6830591 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495001 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5495001 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157255 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 157255 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157172 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 157172 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 12325592 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 12325592 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 12325592 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 12325592 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033369 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.033369 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025787 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.025787 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059318 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059318 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047668 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047668 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029989 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.029989 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029989 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.029989 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13745.938464 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13745.938464 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29122.595306 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 29122.595306 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9464.622642 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9464.622642 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5928.523759 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5928.523759 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19640.712545 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 19640.712545 # average overall miss latency
+system.cpu0.dcache.demand_misses::cpu0.data 369378 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 369378 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 369378 # number of overall misses
+system.cpu0.dcache.overall_misses::total 369378 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3130112000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 3130112000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4103795500 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 4103795500 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87984000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 87984000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44508500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 44508500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 7233907500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 7233907500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 7233907500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 7233907500 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827806 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 6827806 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 5492636 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 5492636 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157242 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 157242 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157153 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 157153 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 12320442 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 12320442 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 12320442 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 12320442 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033373 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.033373 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025764 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.025764 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059151 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059151 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047673 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047673 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029981 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.029981 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029981 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.029981 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13736.815543 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13736.815543 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28999.014239 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 28999.014239 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9459.627997 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9459.627997 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5940.803524 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5940.803524 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19584.023683 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19584.023683 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19584.023683 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 19584.023683 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 306514 # number of writebacks
-system.cpu0.dcache.writebacks::total 306514 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227931 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 227931 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141702 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 141702 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9328 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9328 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks 306206 # number of writebacks
+system.cpu0.dcache.writebacks::total 306206 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227863 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 227863 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141515 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 141515 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9301 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9301 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 369633 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 369633 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 369633 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 369633 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2677263500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2677263500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3843326000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3843326000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69630000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69630000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29442500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29442500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6520589500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 6520589500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6520589500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 6520589500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13560077000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13560077000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128521500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128521500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688598500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688598500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033369 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033369 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025787 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025787 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059318 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059318 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047648 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047648 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.029989 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.029989 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.938464 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.938464 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27122.595306 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27122.595306 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7464.622642 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7464.622642 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3931.432768 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3931.432768 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 369378 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 369378 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 369378 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 369378 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2674386000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2674386000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3820765500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3820765500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69382000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69382000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29532500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29532500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6495151500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6495151500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6495151500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6495151500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13561363000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13561363000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128479500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128479500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14689842500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059151 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059151 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047654 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047654 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029981 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029981 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 8308581 # DTB read hits
+system.cpu1.dtb.read_hits 8310545 # DTB read hits
system.cpu1.dtb.read_misses 3643 # DTB read misses
-system.cpu1.dtb.write_hits 5825594 # DTB write hits
-system.cpu1.dtb.write_misses 1436 # DTB write misses
+system.cpu1.dtb.write_hits 5827351 # DTB write hits
+system.cpu1.dtb.write_misses 1434 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 8312224 # DTB read accesses
-system.cpu1.dtb.write_accesses 5827030 # DTB write accesses
+system.cpu1.dtb.read_accesses 8314188 # DTB read accesses
+system.cpu1.dtb.write_accesses 5828785 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 14134175 # DTB hits
-system.cpu1.dtb.misses 5079 # DTB misses
-system.cpu1.dtb.accesses 14139254 # DTB accesses
-system.cpu1.itb.inst_hits 33188757 # ITB inst hits
+system.cpu1.dtb.hits 14137896 # DTB hits
+system.cpu1.dtb.misses 5077 # DTB misses
+system.cpu1.dtb.accesses 14142973 # DTB accesses
+system.cpu1.itb.inst_hits 33189113 # ITB inst hits
system.cpu1.itb.inst_misses 2171 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 33190928 # ITB inst accesses
-system.cpu1.itb.hits 33188757 # DTB hits
+system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses
+system.cpu1.itb.hits 33189113 # DTB hits
system.cpu1.itb.misses 2171 # DTB misses
-system.cpu1.itb.accesses 33190928 # DTB accesses
-system.cpu1.numCycles 2364324282 # number of cpu cycles simulated
+system.cpu1.itb.accesses 33191284 # DTB accesses
+system.cpu1.numCycles 2364318212 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 32578272 # Number of instructions committed
-system.cpu1.committedOps 41082658 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 37307259 # Number of integer alu accesses
+system.cpu1.committedInsts 32578626 # Number of instructions committed
+system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
-system.cpu1.num_func_calls 961975 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3732574 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 37307259 # number of integer instructions
+system.cpu1.num_func_calls 962009 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3732639 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 37313171 # number of integer instructions
system.cpu1.num_fp_insts 6793 # number of float instructions
-system.cpu1.num_int_register_reads 213628675 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 39450611 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 213663418 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 39454743 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
-system.cpu1.num_mem_refs 14671912 # number of memory refs
-system.cpu1.num_load_insts 8630468 # Number of load instructions
-system.cpu1.num_store_insts 6041444 # Number of store instructions
-system.cpu1.num_idle_cycles 1868307269.461274 # Number of idle cycles
-system.cpu1.num_busy_cycles 496017012.538726 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.209792 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.790208 # Percentage of idle cycles
+system.cpu1.num_mem_refs 14675641 # number of memory refs
+system.cpu1.num_load_insts 8632449 # Number of load instructions
+system.cpu1.num_store_insts 6043192 # Number of store instructions
+system.cpu1.num_idle_cycles 1868258895.232782 # Number of idle cycles
+system.cpu1.num_busy_cycles 496059316.767218 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.209811 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.790189 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 43897 # number of quiesce instructions executed
-system.cpu1.icache.replacements 469210 # number of replacements
-system.cpu1.icache.tagsinuse 478.783126 # Cycle average of tags in use
-system.cpu1.icache.total_refs 32719031 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 469722 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 69.656160 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 92024110500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 478.783126 # Average occupied blocks per requestor
+system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed
+system.cpu1.icache.replacements 469194 # number of replacements
+system.cpu1.icache.tagsinuse 478.783096 # Cycle average of tags in use
+system.cpu1.icache.total_refs 32719403 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 469706 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 69.659325 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 92023963500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 478.783096 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 32719031 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 32719031 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 32719031 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 32719031 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 32719031 # number of overall hits
-system.cpu1.icache.overall_hits::total 32719031 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 469722 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 469722 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 469722 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 469722 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 469722 # number of overall misses
-system.cpu1.icache.overall_misses::total 469722 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6346616500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 6346616500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 6346616500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 6346616500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 6346616500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 6346616500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188753 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 33188753 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 33188753 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 33188753 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 33188753 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 33188753 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13511.431230 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13511.431230 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13511.431230 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13511.431230 # average overall miss latency
+system.cpu1.icache.ReadReq_hits::cpu1.inst 32719403 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 32719403 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 32719403 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 32719403 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 32719403 # number of overall hits
+system.cpu1.icache.overall_hits::total 32719403 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 469706 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 469706 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 469706 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 469706 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 469706 # number of overall misses
+system.cpu1.icache.overall_misses::total 469706 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6343605000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 6343605000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 6343605000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 6343605000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 6343605000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 6343605000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189109 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 33189109 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 33189109 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 33189109 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 33189109 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 33189109 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014152 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.014152 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014152 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.014152 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014152 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.014152 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.480024 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.480024 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13505.480024 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13505.480024 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469722 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 469722 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 469722 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 469722 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 469722 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 469722 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5407172500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 5407172500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5407172500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 5407172500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5407172500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 5407172500 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469706 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 469706 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 469706 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 469706 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 469706 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 469706 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5404193000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 5404193000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5404193000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 5404193000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5404193000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 5404193000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11511.431230 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014152 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.014152 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.014152 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11505.480024 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 291698 # number of replacements
-system.cpu1.dcache.tagsinuse 472.096881 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 11957476 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 292067 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 40.940866 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 83625331000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 472.096881 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.922064 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.922064 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 6944335 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 6944335 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 4825513 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 4825513 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81763 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 81763 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82710 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 82710 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 11769848 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 11769848 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 11769848 # number of overall hits
-system.cpu1.dcache.overall_hits::total 11769848 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 170295 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 170295 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 149789 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 149789 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11069 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 11069 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10034 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 10034 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 320084 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 320084 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 320084 # number of overall misses
-system.cpu1.dcache.overall_misses::total 320084 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2151167000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2151167000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4518557500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 4518557500 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92001000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 92001000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51654000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 51654000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 6669724500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 6669724500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 6669724500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 6669724500 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114630 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 7114630 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975302 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 4975302 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92832 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 92832 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92744 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 92744 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 12089932 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 12089932 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 12089932 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 12089932 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023936 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.023936 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030107 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.030107 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119237 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119237 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108190 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108190 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026475 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.026475 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026475 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.026475 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12632.003288 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12632.003288 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30166.150385 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 30166.150385 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8311.590930 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8311.590930 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5147.897150 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5147.897150 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20837.419240 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20837.419240 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20837.419240 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 20837.419240 # average overall miss latency
+system.cpu1.dcache.replacements 292054 # number of replacements
+system.cpu1.dcache.tagsinuse 471.972808 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 11961234 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 292426 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 40.903456 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 83625409000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 471.972808 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.921822 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.921822 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 6946091 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 6946091 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 4827134 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 4827134 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81752 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 81752 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82714 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 82714 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 11773225 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 11773225 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 11773225 # number of overall hits
+system.cpu1.dcache.overall_hits::total 11773225 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 170515 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 170515 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 149924 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 149924 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11068 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 11068 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10031 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 10031 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 320439 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 320439 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 320439 # number of overall misses
+system.cpu1.dcache.overall_misses::total 320439 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2149232000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 2149232000 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4527081500 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 4527081500 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92245500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 92245500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51683000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 51683000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 6676313500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 6676313500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 6676313500 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 6676313500 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 7116606 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 7116606 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977058 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 4977058 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92820 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 92820 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92745 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 92745 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 12093664 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 12093664 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 12093664 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 12093664 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023960 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.023960 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030123 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.030123 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119242 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119242 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108157 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108157 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026496 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.026496 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026496 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.026496 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12604.357388 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12604.357388 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30195.842560 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 30195.842560 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8334.432598 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8334.432598 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5152.327784 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5152.327784 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20834.896813 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20834.896813 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 265120 # number of writebacks
-system.cpu1.dcache.writebacks::total 265120 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170295 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 170295 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149789 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 149789 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11069 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11069 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10028 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10028 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 320084 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 320084 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 320084 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 320084 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1810577000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1810577000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4218979500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4218979500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69863000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69863000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31600000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.writebacks::writebacks 265102 # number of writebacks
+system.cpu1.dcache.writebacks::total 265102 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170515 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 170515 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149924 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 149924 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11068 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11068 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10026 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10026 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 320439 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 320439 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 320439 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 320439 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1808202000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1808202000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4227233500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4227233500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70109500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70109500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31633000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31633000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6029556500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 6029556500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6029556500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 6029556500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168626695000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168626695000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666887000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666887000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186293582000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186293582000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023936 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023936 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030107 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030107 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119237 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119237 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108126 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108126 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026475 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.026475 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10632.003288 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10632.003288 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28166.150385 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28166.150385 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6311.590930 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6311.590930 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3151.176705 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3151.176705 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6035435500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 6035435500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6035435500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 6035435500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17673871500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17673871500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023960 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023960 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119242 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119242 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108103 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108103 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026496 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.026496 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446757532781 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 446757532781 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446757532781 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 446757532781 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
[system]
type=LinuxArmSystem
-children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1
+clock=1000
dtb_filename=
early_kernel_symbols=false
+enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
-memories=system.physmem system.realview.nvmem
-midr_regval=890224640
+mem_ranges=0:134217727
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.bridge]
type=Bridge
-clock=1
+clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
-clock=1
+clock=1000
forward_snoops=false
-hash_delay=1
-hit_latency=50000
-is_top_level=false
+hit_latency=50
+is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=50000
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
-
-[system.l2c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-clock=1
-forward_snoops=true
-hash_delay=1
-hit_latency=10000
-is_top_level=false
-max_miss_count=0
-mshrs=92
-prefetch_on_access=false
-prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
-size=4194304
-subblock_size=0
-system=system
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=true
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[2]
[system.realview.a9scu]
type=A9SCU
-clock=1
+clock=1000
pio_addr=520093696
pio_latency=100000
system=system
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
-clock=1
+clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
[system.realview.flash_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
[system.realview.gic]
type=Gic
-clock=1
+clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
[system.realview.kmi0]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
[system.realview.kmi1]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
[system.realview.l2x0_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
[system.realview.realview_io]
type=RealViewCtrl
-clock=1
+clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
[system.realview.rtc]
type=PL031
amba_id=3412017
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
[system.realview.timer0]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
[system.realview.timer1]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
[system.realview.uart]
type=Pl011
-clock=1
+clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
output=true
port=3456
-[system.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-use_default_range=false
-width=8
-master=system.l2c.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
[system.vncserver]
type=VncServer
frame_capture=false
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:18
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:31:27
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2629149747000 because m5_exit instruction encountered
+Exiting @ tick 2603634694000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.603636 # Number of seconds simulated
-sim_ticks 2603636076000 # Number of ticks simulated
-final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.603635 # Number of seconds simulated
+sim_ticks 2603634694000 # Number of ticks simulated
+final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 264193 # Simulator instruction rate (inst/s)
-host_op_rate 336182 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 11426847777 # Simulator tick rate (ticks/s)
-host_mem_usage 395692 # Number of bytes of host memory used
-host_seconds 227.85 # Real time elapsed on the host
-sim_insts 60197128 # Number of instructions simulated
-sim_ops 76599899 # Number of ops (including micro ops) simulated
+host_inst_rate 156094 # Simulator instruction rate (inst/s)
+host_op_rate 198627 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6751306864 # Simulator tick rate (ticks/s)
+host_mem_usage 397752 # Number of bytes of host memory used
+host_seconds 385.65 # Real time elapsed on the host
+sim_insts 60197457 # Number of instructions simulated
+sim_ops 76600355 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15494089 # Total number of read requests seen
-system.physmem.writeReqs 811479 # Total number of write requests seen
-system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 991621696 # Total number of bytes read from memory
-system.physmem.bytesWritten 51934656 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15494095 # Total number of read requests seen
+system.physmem.writeReqs 811481 # Total number of write requests seen
+system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 991622080 # Total number of bytes read from memory
+system.physmem.bytesWritten 51934784 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2603631716000 # Total gap between requests
+system.physmem.totGap 2603630334000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6652 # Categorize read packet sizes
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 152013 # Categorize read packet sizes
+system.physmem.readPktSize::6 152019 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 57461 # categorize write packet sizes
+system.physmem.writePktSize::6 57463 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 15419657 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 56436 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 11795 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2249 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1058 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 797 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 386 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 213 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 117 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 85 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 73 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 46 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3750171610 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 281910621610 # Sum of mem lat for all requests
-system.physmem.totBusLat 61975012000 # Total cycles spent in databus access
-system.physmem.totBankLat 216185438000 # Total cycles spent in bank access
-system.physmem.avgQLat 242.04 # Average queueing delay per request
-system.physmem.avgBankLat 13953.07 # Average bank access latency per request
+system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests
+system.physmem.totBusLat 61975036000 # Total cycles spent in databus access
+system.physmem.totBankLat 16863224000 # Total cycles spent in bank access
+system.physmem.avgQLat 18619.82 # Average queueing delay per request
+system.physmem.avgBankLat 1088.39 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 18195.12 # Average memory access latency
+system.physmem.avgMemAccLat 23708.21 # Average memory access latency
system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.51 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.11 # Average read queue length over time
-system.physmem.avgWrQLen 12.38 # Average write queue length over time
-system.physmem.readRowHits 15449450 # Number of row buffer hits during reads
-system.physmem.writeRowHits 784611 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes
-system.physmem.avgGap 159677.46 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.avgRdQLen 0.14 # Average read queue length over time
+system.physmem.avgWrQLen 12.40 # Average write queue length over time
+system.physmem.readRowHits 15451886 # Number of row buffer hits during reads
+system.physmem.writeRowHits 785061 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes
+system.physmem.avgGap 159677.30 # Average gap between requests
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14995523 # DTB read hits
-system.cpu.dtb.read_misses 7332 # DTB read misses
-system.cpu.dtb.write_hits 11230789 # DTB write hits
+system.cpu.dtb.read_hits 14995645 # DTB read hits
+system.cpu.dtb.read_misses 7331 # DTB read misses
+system.cpu.dtb.write_hits 11230857 # DTB write hits
system.cpu.dtb.write_misses 2203 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 15002855 # DTB read accesses
-system.cpu.dtb.write_accesses 11232992 # DTB write accesses
+system.cpu.dtb.read_accesses 15002976 # DTB read accesses
+system.cpu.dtb.write_accesses 11233060 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26226312 # DTB hits
-system.cpu.dtb.misses 9535 # DTB misses
-system.cpu.dtb.accesses 26235847 # DTB accesses
-system.cpu.itb.inst_hits 61491068 # ITB inst hits
+system.cpu.dtb.hits 26226502 # DTB hits
+system.cpu.dtb.misses 9534 # DTB misses
+system.cpu.dtb.accesses 26236036 # DTB accesses
+system.cpu.itb.inst_hits 61491397 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 61495539 # ITB inst accesses
-system.cpu.itb.hits 61491068 # DTB hits
+system.cpu.itb.inst_accesses 61495868 # ITB inst accesses
+system.cpu.itb.hits 61491397 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 61495539 # DTB accesses
-system.cpu.numCycles 5207272152 # number of cpu cycles simulated
+system.cpu.itb.accesses 61495868 # DTB accesses
+system.cpu.numCycles 5207269388 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60197128 # Number of instructions committed
-system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses
+system.cpu.committedInsts 60197457 # Number of instructions committed
+system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
-system.cpu.num_func_calls 2139710 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls
-system.cpu.num_int_insts 68867725 # number of integer instructions
+system.cpu.num_func_calls 2139722 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls
+system.cpu.num_int_insts 68868122 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read
-system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written
+system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read
+system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_mem_refs 27393681 # number of memory refs
-system.cpu.num_load_insts 15659530 # Number of load instructions
-system.cpu.num_store_insts 11734151 # Number of store instructions
-system.cpu.num_idle_cycles 4579080256.576241 # Number of idle cycles
-system.cpu.num_busy_cycles 628191895.423759 # Number of busy cycles
-system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.879363 # Percentage of idle cycles
+system.cpu.num_mem_refs 27393871 # number of memory refs
+system.cpu.num_load_insts 15659652 # Number of load instructions
+system.cpu.num_store_insts 11734219 # Number of store instructions
+system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles
+system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles
+system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.879373 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed
-system.cpu.icache.replacements 855500 # number of replacements
-system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use
-system.cpu.icache.total_refs 60635056 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 856012 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 70.834353 # Average number of references to valid blocks.
+system.cpu.icache.replacements 855485 # number of replacements
+system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use
+system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 60635056 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 60635056 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 60635056 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 60635056 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 60635056 # number of overall hits
-system.cpu.icache.overall_hits::total 60635056 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 856012 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 856012 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 856012 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 856012 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 856012 # number of overall misses
-system.cpu.icache.overall_misses::total 856012 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 11543876000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 11543876000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 11543876000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 11543876000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 11543876000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 11543876000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 60635400 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 60635400 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 60635400 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 60635400 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 60635400 # number of overall hits
+system.cpu.icache.overall_hits::total 60635400 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 855997 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 855997 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 855997 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 855997 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 855997 # number of overall misses
+system.cpu.icache.overall_misses::total 855997 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 11539684000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 11539684000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 11539684000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 11539684000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 11539684000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 11539684000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13485.647397 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13485.647397 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13485.647397 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13485.647397 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13480.986499 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13480.986499 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13480.986499 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13480.986499 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856012 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 856012 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 856012 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 856012 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 856012 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 856012 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831852000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 9831852000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831852000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 9831852000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831852000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 9831852000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855997 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 855997 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 855997 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 855997 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 855997 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 855997 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9827690000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 9827690000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9827690000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 9827690000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9827690000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 9827690000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles
system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11485.647397 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11485.647397 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11480.986499 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11480.986499 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11480.986499 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11480.986499 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11480.986499 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11480.986499 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 627255 # number of replacements
-system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use
-system.cpu.dcache.total_refs 23654861 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 627767 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 37.680956 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13195024 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13195024 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 9972994 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 9972994 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 236273 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 236273 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 247672 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 247672 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 23168018 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 23168018 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 23168018 # number of overall hits
-system.cpu.dcache.overall_hits::total 23168018 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 368763 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 368763 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 250502 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 250502 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 619265 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 619265 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 619265 # number of overall misses
-system.cpu.dcache.overall_misses::total 619265 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205933000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5205933000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061519000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8061519000 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154593000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 154593000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 13267452000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 13267452000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 13267452000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 13267452000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 13563787 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13563787 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10223496 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10223496 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247673 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 247673 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 247672 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 247672 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 23787283 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 23787283 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 23787283 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 23787283 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027187 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.027187 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046028 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046028 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.026033 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14117.286713 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14117.286713 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.455637 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.455637 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.789474 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.789474 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 21424.514545 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21424.514545 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 596013 # number of writebacks
-system.cpu.dcache.writebacks::total 596013 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368763 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 368763 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250502 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 250502 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 619265 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 619265 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 619265 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 619265 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468407000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468407000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560515000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560515000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131793000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131793000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028922000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12028922000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028922000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12028922000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182088074500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182088074500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708050000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708050000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200796124500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 200796124500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046028 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046028 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12117.286713 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12117.286713 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.455637 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.455637 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11560.789474 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11560.789474 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 61906 # number of replacements
-system.cpu.l2cache.tagsinuse 50893.840705 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1682733 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 127288 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 13.219887 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 2553095647000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 37868.665520 # Average occupied blocks per requestor
+system.cpu.l2cache.replacements 61912 # number of replacements
+system.cpu.l2cache.tagsinuse 50893.937876 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1682687 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 127293 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 13.219007 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 2553095791000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 37868.725267 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 6995.476581 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6025.811619 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.577830 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 6995.530011 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 6025.795614 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.577831 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.106743 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.091947 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8702 # number of ReadReq hits
+system.cpu.l2cache.occ_percent::cpu.data 0.091946 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.776580 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8699 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 843788 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 370305 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1226343 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 596013 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 596013 # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 843755 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 370324 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1226326 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 596029 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 596029 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 114418 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 114418 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 8702 # number of demand (read+write) hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 114426 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 114426 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 8699 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 843788 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 484723 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1340761 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 8702 # number of overall hits
+system.cpu.l2cache.demand_hits::cpu.inst 843755 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 484750 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1340752 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 8699 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 843788 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 484723 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1340761 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 843755 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 484750 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1340752 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 20471 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2875 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133183 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133183 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 143044 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 153651 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143042 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 153654 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 143044 # number of overall misses
-system.cpu.l2cache.overall_misses::total 153651 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143042 # number of overall misses
+system.cpu.l2cache.overall_misses::total 153654 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 536335000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 516987000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1053746500 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102367500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6102367500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 532505000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 512702000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1045631500 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 461000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 461000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6086440000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6086440000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 536335000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6619354500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 7156114000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 532505000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6599142000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 7132071500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 536335000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6619354500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 7156114000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8707 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_miss_latency::cpu.inst 532505000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6599142000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 7132071500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8704 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 854387 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 380163 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1246808 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 596013 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 596013 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 247604 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 247604 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8707 # number of demand (read+write) accesses
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 854359 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 380183 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1246797 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 596029 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 596029 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 247609 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 247609 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8704 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 854387 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 627767 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1494412 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8707 # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 854359 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 627792 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1494406 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8704 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 854387 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 627767 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1494412 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 854359 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 627792 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1494406 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012405 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025931 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537899 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.537899 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012412 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025932 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.016419 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537876 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.537876 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012405 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.227862 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.102817 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012412 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.227849 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.102819 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012405 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.227862 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.102817 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012412 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.227849 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.102819 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 57500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 45666.666667 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50602.415322 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52443.396226 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 51490.178353 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.167131 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.167131 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45818.385566 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45818.385566 # average ReadExReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50217.370803 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52003.448626 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51078.672268 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.347826 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.347826 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45699.826554 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45699.826554 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 46573.819891 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50217.370803 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46134.296221 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 46416.438882 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 46573.819891 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50217.370803 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46134.296221 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 46416.438882 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks
-system.cpu.l2cache.writebacks::total 57461 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 57463 # number of writebacks
+system.cpu.l2cache.writebacks::total 57463 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10604 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 20471 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133183 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133183 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 143044 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 153651 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 10604 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143042 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 153654 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 143044 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 153651 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 10604 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143042 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 153654 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398671075 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 388940100 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 787933191 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28807316 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28807316 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4371975723 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4371975723 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 394778574 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 384642089 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 779742679 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28851319 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28851319 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4356126157 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4356126157 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 224010 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 98006 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398671075 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4760915823 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 5159908914 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 394778574 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4740768246 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 5135868836 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398671075 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4760915823 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 5159908914 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 394778574 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4740768246 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 5135868836 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166694484565 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166891951116 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175103106 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175103106 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166684815565 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166882282116 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9180297506 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9180297506 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175869587671 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176067054222 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175865113071 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176062579622 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025931 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537899 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537899 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016419 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537876 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537876 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.102817 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227849 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.102819 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227849 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.102819 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37614.027267 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39454.260499 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38501.499682 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.402507 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.402507 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32826.090753 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32826.090753 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37229.212939 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39014.310681 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38090.111817 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10035.241391 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10035.241391 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32707.824249 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32707.824249 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 627280 # number of replacements
+system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use
+system.cpu.dcache.total_refs 23655026 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 627792 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 37.679719 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 13195122 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13195122 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 9973048 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9973048 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 23168170 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 23168170 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 23168170 # number of overall hits
+system.cpu.dcache.overall_hits::total 23168170 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 368781 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 368781 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 619291 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 619291 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 619291 # number of overall misses
+system.cpu.dcache.overall_misses::total 619291 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201704000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5201704000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 8045775500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 8045775500 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154787000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 154787000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 13247479500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 13247479500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 13247479500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 13247479500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027188 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.027188 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.026034 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.026034 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.026034 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.026034 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.130145 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.130145 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32117.582132 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 32117.582132 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.425364 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.425364 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21391.364480 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21391.364480 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 596029 # number of writebacks
+system.cpu.dcache.writebacks::total 596029 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368781 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 368781 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 619291 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 619291 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 619291 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 619291 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4464142000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4464142000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7544755500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7544755500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131983000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131983000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12008897500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12008897500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12008897500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12008897500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182078406500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182078406500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18714752000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18714752000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200793158500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 200793158500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027188 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027188 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.026034 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.026034 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.130145 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.130145 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30117.582132 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30117.582132 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11575.425364 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11575.425364 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1052665426345 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1052665426345 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1130504893187 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1130504893187 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
[drivesys]
type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami
-boot_cpu_frequency=1
+boot_cpu_frequency=250
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/gem5/dist/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/gem5/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=0:134217727
memories=drivesys.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
-readfile=/tmp/gem5.ali/configs/boot/netperf-server.rcS
+pal=/gem5/dist/binaries/ts_osfpal
+readfile=/gem5/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
[drivesys.bridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
-write_ack=false
master=drivesys.iobus.slave[0]
slave=drivesys.membus.master[0]
[drivesys.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer
+children=dtb interrupts isa itb tracer
checker=Null
-clock=1
+clock=250
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=drivesys.cpu.interrupts
+isa=drivesys.cpu.isa
itb=drivesys.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=drivesys
tracer=drivesys.cpu.tracer
width=1
[drivesys.cpu.interrupts]
type=AlphaInterrupts
+[drivesys.cpu.isa]
+type=AlphaISA
+
[drivesys.cpu.itb]
type=AlphaTLB
size=48
[drivesys.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[drivesys.disk2]
[drivesys.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/gem5/dist/disks/linux-bigswap2.img
read_only=true
[drivesys.intrctrl]
[drivesys.iobridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
-ranges=0:8589934592
+ranges=0:134217727
req_size=16
resp_size=16
-write_ack=false
master=drivesys.membus.slave[3]
slave=drivesys.iobus.master[29]
clock=1000
header_cycles=1
use_default_range=true
-width=64
+width=8
default=drivesys.tsunami.pciconfig.pio
master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ide.config drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.iobridge.slave
slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
default=drivesys.membus.badaddr_responder.pio
-master=drivesys.bridge.slave drivesys.physmem.port[0]
+master=drivesys.bridge.slave drivesys.physmem.port
slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master
[drivesys.membus.badaddr_responder]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=0
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
pio=drivesys.membus.default
[drivesys.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=drivesys.membus.master[1]
[drivesys.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[drivesys.terminal]
[drivesys.tsunami.backdoor]
type=AlphaBackdoor
+clock=1000
cpu=drivesys.cpu
disk=drivesys.simple_disk
pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
platform=drivesys.tsunami
system=drivesys
terminal=drivesys.terminal
[drivesys.tsunami.cchip]
type=TsunamiCChip
+clock=1000
pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
system=drivesys
tsunami=drivesys.tsunami
pio=drivesys.iobus.master[0]
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
dma_write_factor=0
hardware_address=00:90:00:00:00:02
intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=drivesys.tsunami
rss=false
rx_delay=1000000
[drivesys.tsunami.fake_OROM]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_ata0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_ata1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_pnp_addr]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_pnp_read0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_pnp_read1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_pnp_read2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_pnp_read3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_pnp_read4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_pnp_read5]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_pnp_read6]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_pnp_read7]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_pnp_write]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_ppc]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_sm_chip]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_uart1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_uart2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_uart3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fake_uart4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[drivesys.tsunami.fb]
type=BadDevice
+clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
system=drivesys
pio=drivesys.iobus.master[21]
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
+clock=1000
config_latency=20000
ctrl_offset=0
disks=drivesys.disk0 drivesys.disk2
io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=drivesys.tsunami
system=drivesys
config=drivesys.iobus.master[26]
[drivesys.tsunami.io]
type=TsunamiIO
+clock=1000
frequency=976562500
pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
system=drivesys
time=Thu Jan 1 00:00:00 2009
tsunami=drivesys.tsunami
[drivesys.tsunami.pchip]
type=TsunamiPChip
+clock=1000
pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
system=drivesys
tsunami=drivesys.tsunami
pio=drivesys.iobus.master[1]
[drivesys.tsunami.pciconfig]
type=PciConfigAll
bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
platform=drivesys.tsunami
size=16777216
system=drivesys
[drivesys.tsunami.uart]
type=Uart8250
+clock=1000
pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
platform=drivesys.tsunami
system=drivesys
terminal=drivesys.terminal
[testsys]
type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami
-boot_cpu_frequency=1
+boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/gem5/dist/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/gem5/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=0:134217727
memories=testsys.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
-readfile=/tmp/gem5.ali/configs/boot/netperf-stream-client.rcS
+pal=/gem5/dist/binaries/ts_osfpal
+readfile=/gem5/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
[testsys.bridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
-write_ack=false
master=testsys.iobus.slave[0]
slave=testsys.membus.master[0]
[testsys.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer
+children=dtb interrupts isa itb tracer
checker=Null
-clock=1
+clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=testsys.cpu.interrupts
+isa=testsys.cpu.isa
itb=testsys.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=testsys
tracer=testsys.cpu.tracer
width=1
[testsys.cpu.interrupts]
type=AlphaInterrupts
+[testsys.cpu.isa]
+type=AlphaISA
+
[testsys.cpu.itb]
type=AlphaTLB
size=48
[testsys.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[testsys.disk2]
[testsys.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/gem5/dist/disks/linux-bigswap2.img
read_only=true
[testsys.intrctrl]
[testsys.iobridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
-ranges=0:8589934592
+ranges=0:134217727
req_size=16
resp_size=16
-write_ack=false
master=testsys.membus.slave[3]
slave=testsys.iobus.master[29]
clock=1000
header_cycles=1
use_default_range=true
-width=64
+width=8
default=testsys.tsunami.pciconfig.pio
master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ide.config testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.iobridge.slave
slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
default=testsys.membus.badaddr_responder.pio
-master=testsys.bridge.slave testsys.physmem.port[0]
+master=testsys.bridge.slave testsys.physmem.port
slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master
[testsys.membus.badaddr_responder]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=0
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
pio=testsys.membus.default
[testsys.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=testsys.membus.master[1]
[testsys.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[testsys.terminal]
[testsys.tsunami.backdoor]
type=AlphaBackdoor
+clock=1000
cpu=testsys.cpu
disk=testsys.simple_disk
pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
platform=testsys.tsunami
system=testsys
terminal=testsys.terminal
[testsys.tsunami.cchip]
type=TsunamiCChip
+clock=1000
pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
system=testsys
tsunami=testsys.tsunami
pio=testsys.iobus.master[0]
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=testsys.tsunami
rss=false
rx_delay=1000000
[testsys.tsunami.fake_OROM]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_ata0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_ata1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_pnp_addr]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_pnp_read0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_pnp_read1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_pnp_read2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_pnp_read3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_pnp_read4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_pnp_read5]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_pnp_read6]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_pnp_read7]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_pnp_write]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_ppc]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_sm_chip]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_uart1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_uart2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_uart3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fake_uart4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[testsys.tsunami.fb]
type=BadDevice
+clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
system=testsys
pio=testsys.iobus.master[21]
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
+clock=1000
config_latency=20000
ctrl_offset=0
disks=testsys.disk0 testsys.disk2
io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=testsys.tsunami
system=testsys
config=testsys.iobus.master[26]
[testsys.tsunami.io]
type=TsunamiIO
+clock=1000
frequency=976562500
pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
system=testsys
time=Thu Jan 1 00:00:00 2009
tsunami=testsys.tsunami
[testsys.tsunami.pchip]
type=TsunamiPChip
+clock=1000
pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
system=testsys
tsunami=testsys.tsunami
pio=testsys.iobus.master[1]
[testsys.tsunami.pciconfig]
type=PciConfigAll
bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
platform=testsys.tsunami
size=16777216
system=testsys
[testsys.tsunami.uart]
type=Uart8250
+clock=1000
pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
platform=testsys.tsunami
system=testsys
terminal=testsys.terminal
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:20:01
-gem5 executing on zizzer
+gem5 compiled Jan 4 2013 21:09:21
+gem5 started Jan 4 2013 21:17:35
+gem5 executing on u200540
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /gem5/dist/binaries/vmlinux
0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /gem5/dist/binaries/vmlinux
0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 4300236804024 because checkpoint
+Exiting @ tick 4321612280500 because checkpoint
---------- Begin Simulation Statistics ----------
-sim_seconds 0.200392 # Number of seconds simulated
-sim_ticks 200392337000 # Number of ticks simulated
-final_tick 4320161528000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.200409 # Number of seconds simulated
+sim_ticks 200409284500 # Number of ticks simulated
+final_tick 4321205328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 90899186 # Simulator instruction rate (inst/s)
-host_op_rate 90898450 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 67078334403 # Simulator tick rate (ticks/s)
-host_mem_usage 463260 # Number of bytes of host memory used
-host_seconds 2.99 # Real time elapsed on the host
-sim_insts 271551386 # Number of instructions simulated
-sim_ops 271551386 # Number of ops (including micro ops) simulated
-testsys.physmem.bytes_read::cpu.inst 13230208 # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data 4514888 # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet 1464 # Number of bytes read from this memory
-testsys.physmem.bytes_read::total 17746560 # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst 13230208 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total 13230208 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data 3697656 # Number of bytes written to this memory
+host_inst_rate 7091560 # Simulator instruction rate (inst/s)
+host_op_rate 7091556 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2715554324 # Simulator tick rate (ticks/s)
+host_mem_usage 465632 # Number of bytes of host memory used
+host_seconds 73.80 # Real time elapsed on the host
+sim_insts 523360203 # Number of instructions simulated
+sim_ops 523360203 # Number of ops (including micro ops) simulated
+testsys.physmem.bytes_read::cpu.inst 80888044 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data 27771396 # Number of bytes read from this memory
+testsys.physmem.bytes_read::tsunami.ethernet 50103096 # Number of bytes read from this memory
+testsys.physmem.bytes_read::total 158762536 # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst 80888044 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total 80888044 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data 16575224 # Number of bytes written to this memory
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
-testsys.physmem.bytes_written::total 3698558 # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst 3307552 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data 615769 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet 43 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total 3923364 # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data 478513 # Number of write requests responded to by this memory
+testsys.physmem.bytes_written::total 16576126 # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst 20222011 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data 3834989 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::tsunami.ethernet 2087611 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::total 26144611 # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data 2254078 # Number of write requests responded to by this memory
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total 478544 # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst 66021527 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data 22530243 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet 7306 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total 88559075 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst 66021527 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total 66021527 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data 18452083 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.num_writes::total 2254109 # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst 403614255 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data 138573400 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::tsunami.ethernet 250003866 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total 792191521 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst 403614255 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total 403614255 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data 82706867 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total 18456584 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst 66021527 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data 40982326 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet 11807 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total 107015659 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_write::total 82711368 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst 403614255 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data 221280267 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::tsunami.ethernet 250008367 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total 874902889 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.readReqs 0 # Total number of read requests seen
testsys.physmem.writeReqs 0 # Total number of write requests seen
testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
-testsys.cpu.dtb.read_hits 611887 # DTB read hits
+testsys.cpu.dtb.read_hits 3909164 # DTB read hits
testsys.cpu.dtb.read_misses 3287 # DTB read misses
testsys.cpu.dtb.read_acv 80 # DTB read access violations
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
-testsys.cpu.dtb.write_hits 478329 # DTB write hits
+testsys.cpu.dtb.write_hits 2312434 # DTB write hits
testsys.cpu.dtb.write_misses 528 # DTB write misses
testsys.cpu.dtb.write_acv 81 # DTB write access violations
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
-testsys.cpu.dtb.data_hits 1090216 # DTB hits
+testsys.cpu.dtb.data_hits 6221598 # DTB hits
testsys.cpu.dtb.data_misses 3815 # DTB misses
testsys.cpu.dtb.data_acv 161 # DTB access violations
testsys.cpu.dtb.data_accesses 335402 # DTB accesses
-testsys.cpu.itb.fetch_hits 1215659 # ITB hits
+testsys.cpu.itb.fetch_hits 4045775 # ITB hits
testsys.cpu.itb.fetch_misses 1497 # ITB misses
testsys.cpu.itb.fetch_acv 69 # ITB acv
-testsys.cpu.itb.fetch_accesses 1217156 # ITB accesses
+testsys.cpu.itb.fetch_accesses 4047272 # ITB accesses
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 399134959 # number of cpu cycles simulated
+testsys.cpu.numCycles 400807419 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.committedInsts 3303576 # Number of instructions committed
-testsys.cpu.committedOps 3303576 # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses 3114478 # Number of integer alu accesses
+testsys.cpu.committedInsts 20218035 # Number of instructions committed
+testsys.cpu.committedOps 20218035 # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses 18800192 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
-testsys.cpu.num_func_calls 87508 # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts 347037 # number of instructions that are conditional controls
-testsys.cpu.num_int_insts 3114478 # number of integer instructions
+testsys.cpu.num_func_calls 1218514 # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts 1439639 # number of instructions that are conditional controls
+testsys.cpu.num_int_insts 18800192 # number of integer instructions
testsys.cpu.num_fp_insts 17380 # number of float instructions
-testsys.cpu.num_int_register_reads 4292532 # number of times the integer registers were read
-testsys.cpu.num_int_register_writes 2256656 # number of times the integer registers were written
+testsys.cpu.num_int_register_reads 24739164 # number of times the integer registers were read
+testsys.cpu.num_int_register_writes 14664877 # number of times the integer registers were written
testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
-testsys.cpu.num_mem_refs 1099900 # number of memory refs
-testsys.cpu.num_load_insts 619443 # Number of load instructions
-testsys.cpu.num_store_insts 480457 # Number of store instructions
-testsys.cpu.num_idle_cycles 395839458.060266 # Number of idle cycles
-testsys.cpu.num_busy_cycles 3295500.939734 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.008257 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.991743 # Percentage of idle cycles
+testsys.cpu.num_mem_refs 6250795 # number of memory refs
+testsys.cpu.num_load_insts 3936233 # Number of load instructions
+testsys.cpu.num_store_insts 2314562 # Number of store instructions
+testsys.cpu.num_idle_cycles 380584404.581032 # Number of idle cycles
+testsys.cpu.num_busy_cycles 20223014.418968 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.050456 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.949544 # Percentage of idle cycles
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce 213 # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei 16711 # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0 4122 40.56% 40.56% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21 54 0.53% 41.09% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22 205 2.02% 43.11% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31 5781 56.89% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total 10162 # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0 4116 48.47% 48.47% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21 54 0.64% 49.11% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22 205 2.41% 51.53% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31 4116 48.47% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total 8491 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0 199321108000 99.88% 99.88% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21 4521000 0.00% 99.88% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 99.88% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31 233256500 0.12% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total 199567700500 # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_used::0 0.998544 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.inst.quiesce 19525 # number of quiesce instructions executed
+testsys.cpu.kern.inst.hwrei 153371 # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0 62656 42.67% 42.67% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21 19578 13.33% 56.01% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::31 64383 43.85% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total 146822 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good::0 62650 43.18% 43.18% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::21 19578 13.49% 56.67% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::22 205 0.14% 56.81% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::31 62661 43.19% 100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::total 145094 # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks::0 194361437500 96.98% 96.98% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::21 1585244500 0.79% 97.78% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31 4448431000 2.22% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total 200403928000 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31 0.711988 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total 0.835564 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::31 0.973254 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total 0.988231 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
-testsys.cpu.kern.callpal::swpctx 438 4.01% 4.01% # number of callpals executed
-testsys.cpu.kern.callpal::tbi 20 0.18% 4.20% # number of callpals executed
-testsys.cpu.kern.callpal::swpipl 8992 82.42% 86.62% # number of callpals executed
-testsys.cpu.kern.callpal::rdps 359 3.29% 89.91% # number of callpals executed
-testsys.cpu.kern.callpal::wrusp 3 0.03% 89.94% # number of callpals executed
-testsys.cpu.kern.callpal::rdusp 3 0.03% 89.96% # number of callpals executed
-testsys.cpu.kern.callpal::rti 911 8.35% 98.31% # number of callpals executed
-testsys.cpu.kern.callpal::callsys 140 1.28% 99.60% # number of callpals executed
-testsys.cpu.kern.callpal::imb 44 0.40% 100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total 10910 # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel 1133 # number of protection mode switches
-testsys.cpu.kern.mode_switch::user 647 # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle 217 # number of protection mode switches
-testsys.cpu.kern.mode_good::kernel 652
-testsys.cpu.kern.mode_good::user 647
+testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed
+testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed
+testsys.cpu.kern.callpal::swpipl 106626 83.26% 83.62% # number of callpals executed
+testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed
+testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed
+testsys.cpu.kern.callpal::rdusp 3 0.00% 83.91% # number of callpals executed
+testsys.cpu.kern.callpal::rti 20424 15.95% 99.86% # number of callpals executed
+testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed
+testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed
+testsys.cpu.kern.callpal::total 128057 # number of callpals executed
+testsys.cpu.kern.mode_switch::kernel 1279 # number of protection mode switches
+testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle 19584 # number of protection mode switches
+testsys.cpu.kern.mode_good::kernel 707
+testsys.cpu.kern.mode_good::user 702
testsys.cpu.kern.mode_good::idle 5
-testsys.cpu.kern.mode_switch_good::kernel 0.575463 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::kernel 0.552776 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle 0.023041 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total 0.652979 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel 931596000 57.08% 57.08% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user 532793000 32.64% 89.72% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle 167721000 10.28% 100.00% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::total 0.065569 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks::kernel 993857000 59.77% 59.77% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::user 533068000 32.06% 91.82% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::idle 135946500 8.18% 100.00% # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
-testsys.tsunami.ethernet.descDMAReads 8 # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAReads 2087576 # Number of descriptors the device read w/ DMA
testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes 192 # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes 50101824 # number of descriptor bytes read w/ DMA
testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.totBandwidth 70182 # Total Bandwidth (bits/s)
+testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
testsys.tsunami.ethernet.totPackets 13 # Total Packets
testsys.tsunami.ethernet.totBytes 1758 # Total Bytes
testsys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s)
-testsys.tsunami.ethernet.txBandwidth 38325 # Transmit Bandwidth (bits/s)
-testsys.tsunami.ethernet.rxBandwidth 31858 # Receive Bandwidth (bits/s)
+testsys.tsunami.ethernet.txBandwidth 38322 # Transmit Bandwidth (bits/s)
+testsys.tsunami.ethernet.rxBandwidth 31855 # Receive Bandwidth (bits/s)
testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s)
testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s)
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle 7 # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxIdle 19525 # number of TxIdle interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle 8 # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.totalTxIdle 2087576 # total number of TxIdle written to ISR
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts 14 # number of posts to CPU
+testsys.tsunami.ethernet.postedInterrupts 2087594 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-drivesys.physmem.bytes_read::cpu.inst 7829376 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::cpu.data 2782760 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet 1230 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total 10613366 # Number of bytes read from this memory
-drivesys.physmem.bytes_inst_read::cpu.inst 7829376 # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_inst_read::total 7829376 # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_written::cpu.data 1606716 # Number of bytes written to this memory
+drivesys.physmem.bytes_read::cpu.inst 76121948 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::cpu.data 26255588 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::tsunami.ethernet 50103126 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::total 152480662 # Number of bytes read from this memory
+drivesys.physmem.bytes_inst_read::cpu.inst 76121948 # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_inst_read::total 76121948 # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_written::cpu.data 14603776 # Number of bytes written to this memory
drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory
-drivesys.physmem.bytes_written::total 1607780 # Number of bytes written to this memory
-drivesys.physmem.num_reads::cpu.inst 1957344 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::cpu.data 393865 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet 34 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total 2351243 # Number of read requests responded to by this memory
-drivesys.physmem.num_writes::cpu.data 230560 # Number of write requests responded to by this memory
+drivesys.physmem.bytes_written::total 14604840 # Number of bytes written to this memory
+drivesys.physmem.num_reads::cpu.inst 19030487 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::cpu.data 3643074 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::tsunami.ethernet 2087613 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::total 24761174 # Number of read requests responded to by this memory
+drivesys.physmem.num_writes::cpu.data 2022588 # Number of write requests responded to by this memory
drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::total 230597 # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst 39070237 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data 13886559 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet 6138 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total 52962933 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst 39070237 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total 39070237 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data 8017852 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::tsunami.ethernet 5310 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total 8023161 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst 39070237 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data 21904410 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet 11448 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total 60986094 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.num_writes::total 2022625 # Number of write requests responded to by this memory
+drivesys.physmem.bw_read::cpu.inst 379832442 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::cpu.data 131009839 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::tsunami.ethernet 250004016 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::total 760846297 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::cpu.inst 379832442 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::total 379832442 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::cpu.data 72869758 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::total 72875067 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.inst 379832442 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.data 203879596 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::tsunami.ethernet 250009325 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::total 833721364 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.readReqs 0 # Total number of read requests seen
drivesys.physmem.writeReqs 0 # Total number of write requests seen
drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
-drivesys.cpu.dtb.read_hits 393226 # DTB read hits
+drivesys.cpu.dtb.read_hits 3721202 # DTB read hits
drivesys.cpu.dtb.read_misses 487 # DTB read misses
drivesys.cpu.dtb.read_acv 30 # DTB read access violations
drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses
-drivesys.cpu.dtb.write_hits 230718 # DTB write hits
+drivesys.cpu.dtb.write_hits 2081819 # DTB write hits
drivesys.cpu.dtb.write_misses 82 # DTB write misses
drivesys.cpu.dtb.write_acv 10 # DTB write access violations
drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses
-drivesys.cpu.dtb.data_hits 623944 # DTB hits
+drivesys.cpu.dtb.data_hits 5803021 # DTB hits
drivesys.cpu.dtb.data_misses 569 # DTB misses
drivesys.cpu.dtb.data_acv 40 # DTB access violations
drivesys.cpu.dtb.data_accesses 401230 # DTB accesses
-drivesys.cpu.itb.fetch_hits 1338285 # ITB hits
+drivesys.cpu.itb.fetch_hits 4194101 # ITB hits
drivesys.cpu.itb.fetch_misses 194 # ITB misses
drivesys.cpu.itb.fetch_acv 22 # ITB acv
-drivesys.cpu.itb.fetch_accesses 1338479 # ITB accesses
+drivesys.cpu.itb.fetch_accesses 4194295 # ITB accesses
drivesys.cpu.itb.read_hits 0 # DTB read hits
drivesys.cpu.itb.read_misses 0 # DTB read misses
drivesys.cpu.itb.read_acv 0 # DTB read access violations
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
-drivesys.cpu.numCycles 800780792 # number of cpu cycles simulated
+drivesys.cpu.numCycles 801639056 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-drivesys.cpu.committedInsts 1956735 # Number of instructions committed
-drivesys.cpu.committedOps 1956735 # Number of ops (including micro ops) committed
-drivesys.cpu.num_int_alu_accesses 1888716 # Number of integer alu accesses
+drivesys.cpu.committedInsts 19029878 # Number of instructions committed
+drivesys.cpu.committedOps 19029878 # Number of ops (including micro ops) committed
+drivesys.cpu.num_int_alu_accesses 17721251 # Number of integer alu accesses
drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses
-drivesys.cpu.num_func_calls 121668 # number of times a function call or return occured
-drivesys.cpu.num_conditional_control_insts 160826 # number of instructions that are conditional controls
-drivesys.cpu.num_int_insts 1888716 # number of integer instructions
+drivesys.cpu.num_func_calls 1263632 # number of times a function call or return occured
+drivesys.cpu.num_conditional_control_insts 1263629 # number of instructions that are conditional controls
+drivesys.cpu.num_int_insts 17721251 # number of integer instructions
drivesys.cpu.num_fp_insts 1412 # number of float instructions
-drivesys.cpu.num_int_register_reads 2409464 # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes 1441433 # number of times the integer registers were written
+drivesys.cpu.num_int_register_reads 23047059 # number of times the integer registers were read
+drivesys.cpu.num_int_register_writes 13965767 # number of times the integer registers were written
drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read
drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written
-drivesys.cpu.num_mem_refs 625666 # number of memory refs
-drivesys.cpu.num_load_insts 394435 # Number of load instructions
-drivesys.cpu.num_store_insts 231231 # Number of store instructions
-drivesys.cpu.num_idle_cycles 798825150.814200 # Number of idle cycles
-drivesys.cpu.num_busy_cycles 1955641.185800 # Number of busy cycles
-drivesys.cpu.not_idle_fraction 0.002442 # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction 0.997558 # Percentage of idle cycles
+drivesys.cpu.num_mem_refs 5824433 # number of memory refs
+drivesys.cpu.num_load_insts 3742101 # Number of load instructions
+drivesys.cpu.num_store_insts 2082332 # Number of store instructions
+drivesys.cpu.num_idle_cycles 782608307.467164 # Number of idle cycles
+drivesys.cpu.num_busy_cycles 19030748.532836 # Number of busy cycles
+drivesys.cpu.not_idle_fraction 0.023740 # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction 0.976260 # Percentage of idle cycles
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
-drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed
-drivesys.cpu.kern.inst.hwrei 5510 # number of hwrei instructions executed
-drivesys.cpu.kern.ipl_count::0 1199 28.41% 28.41% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::21 12 0.28% 28.69% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::22 205 4.86% 33.55% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31 2805 66.45% 100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total 4221 # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0 1199 45.85% 45.85% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::21 12 0.46% 46.31% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::22 205 7.84% 54.15% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31 1199 45.85% 100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total 2615 # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0 200114646000 99.96% 99.96% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21 486000 0.00% 99.96% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 99.96% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31 75660250 0.04% 100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total 200195199750 # number of cycles we spent at this ipl
+drivesys.cpu.kern.inst.quiesce 19854 # number of quiesce instructions executed
+drivesys.cpu.kern.inst.hwrei 143418 # number of hwrei instructions executed
+drivesys.cpu.kern.ipl_count::0 60285 42.42% 42.42% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::21 19703 13.86% 56.28% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::31 61936 43.58% 100.00% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::total 142129 # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_good::0 60285 42.91% 42.91% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::21 19703 14.03% 56.94% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::31 60286 42.91% 100.00% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::total 140479 # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_ticks::0 197404825250 98.50% 98.50% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::21 797938750 0.40% 98.90% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::31 2202592500 1.10% 100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::total 200409764000 # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31 0.427451 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::total 0.619521 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::31 0.973360 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::total 0.988391 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed
drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed
drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed
drivesys.cpu.kern.syscall::118 2 9.09% 95.45% # number of syscalls executed
drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # number of syscalls executed
drivesys.cpu.kern.syscall::total 22 # number of syscalls executed
-drivesys.cpu.kern.callpal::swpctx 72 1.61% 1.61% # number of callpals executed
-drivesys.cpu.kern.callpal::tbi 5 0.11% 1.72% # number of callpals executed
-drivesys.cpu.kern.callpal::swpipl 3680 82.36% 84.09% # number of callpals executed
-drivesys.cpu.kern.callpal::rdps 354 7.92% 92.01% # number of callpals executed
-drivesys.cpu.kern.callpal::rdusp 1 0.02% 92.03% # number of callpals executed
-drivesys.cpu.kern.callpal::rti 324 7.25% 99.28% # number of callpals executed
-drivesys.cpu.kern.callpal::callsys 25 0.56% 99.84% # number of callpals executed
-drivesys.cpu.kern.callpal::imb 7 0.16% 100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total 4468 # number of callpals executed
-drivesys.cpu.kern.mode_switch::kernel 177 # number of protection mode switches
-drivesys.cpu.kern.mode_switch::user 107 # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle 219 # number of protection mode switches
-drivesys.cpu.kern.mode_good::kernel 111
-drivesys.cpu.kern.mode_good::user 107
+drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed
+drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed
+drivesys.cpu.kern.callpal::swpipl 102208 83.31% 83.37% # number of callpals executed
+drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed
+drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed
+drivesys.cpu.kern.callpal::rti 20014 16.31% 99.97% # number of callpals executed
+drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed
+drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed
+drivesys.cpu.kern.callpal::total 122686 # number of callpals executed
+drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches
+drivesys.cpu.kern.mode_switch::user 139 # number of protection mode switches
+drivesys.cpu.kern.mode_switch::idle 19872 # number of protection mode switches
+drivesys.cpu.kern.mode_good::kernel 143
+drivesys.cpu.kern.mode_good::user 139
drivesys.cpu.kern.mode_good::idle 4
-drivesys.cpu.kern.mode_switch_good::kernel 0.627119 # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::kernel 0.668224 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::idle 0.018265 # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total 0.441352 # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks::kernel 66889000 2.31% 2.31% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user 319585750 11.03% 13.34% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle 2511080250 86.66% 100.00% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::total 0.014141 # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_ticks::kernel 78132750 2.64% 2.64% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::user 319665750 10.81% 13.45% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::idle 2560362000 86.55% 100.00% # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
-drivesys.tsunami.ethernet.descDMAReads 5 # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAReads 2087584 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes 120 # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes 50102016 # number of descriptor bytes read w/ DMA
drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
-drivesys.tsunami.ethernet.totBandwidth 70182 # Total Bandwidth (bits/s)
+drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
drivesys.tsunami.ethernet.totPackets 13 # Total Packets
drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes
drivesys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s)
-drivesys.tsunami.ethernet.txBandwidth 31858 # Transmit Bandwidth (bits/s)
-drivesys.tsunami.ethernet.rxBandwidth 38325 # Receive Bandwidth (bits/s)
+drivesys.tsunami.ethernet.txBandwidth 31855 # Transmit Bandwidth (bits/s)
+drivesys.tsunami.ethernet.rxBandwidth 38322 # Receive Bandwidth (bits/s)
drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s)
drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s)
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-drivesys.tsunami.ethernet.postedRxDesc 7 # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxDesc 1 # average number of RxDesc's coalesced into each post
+drivesys.tsunami.ethernet.postedRxDesc 8 # number of RxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.postedTxIdle 5 # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle 5 # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.postedTxIdle 19702 # number of TxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
+drivesys.tsunami.ethernet.totalTxIdle 2087584 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts 14 # number of posts to CPU
+drivesys.tsunami.ethernet.postedInterrupts 2087605 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000390 # Number of seconds simulated
-sim_ticks 390393500 # Number of ticks simulated
-final_tick 4320551921500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000407 # Number of seconds simulated
+sim_ticks 406952000 # Number of ticks simulated
+final_tick 4321612280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 123937139701 # Simulator instruction rate (inst/s)
-host_op_rate 122659857960 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 174562814371 # Simulator tick rate (ticks/s)
-host_mem_usage 463260 # Number of bytes of host memory used
-host_seconds 0.00 # Real time elapsed on the host
-sim_insts 271554329 # Number of instructions simulated
-sim_ops 271554329 # Number of ops (including micro ops) simulated
-testsys.physmem.bytes_read::cpu.inst 5888 # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data 2272 # Number of bytes read from this memory
-testsys.physmem.bytes_read::total 8160 # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst 5888 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total 5888 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data 1288 # Number of bytes written to this memory
-testsys.physmem.bytes_written::total 1288 # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst 1472 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data 309 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total 1781 # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data 172 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total 172 # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst 15082218 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data 5819769 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total 20901987 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst 15082218 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total 15082218 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data 3299235 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total 3299235 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst 15082218 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total 24201223 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 3682675458 # Simulator instruction rate (inst/s)
+host_op_rate 3681807032 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2861829739 # Simulator tick rate (ticks/s)
+host_mem_usage 465632 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
+sim_insts 523432506 # Number of instructions simulated
+sim_ops 523432506 # Number of ops (including micro ops) simulated
+testsys.physmem.bytes_read::cpu.inst 144604 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory
+testsys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory
+testsys.physmem.bytes_read::total 296292 # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst 144604 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total 144604 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory
+testsys.physmem.bytes_written::total 27688 # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst 36151 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::total 47299 # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory
+testsys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst 355334290 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total 728076038 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst 355334290 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total 355334290 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst 355334290 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total 796113547 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.readReqs 0 # Total number of read requests seen
testsys.physmem.writeReqs 0 # Total number of write requests seen
testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
-testsys.cpu.dtb.read_hits 309 # DTB read hits
+testsys.cpu.dtb.read_hits 7069 # DTB read hits
testsys.cpu.dtb.read_misses 0 # DTB read misses
testsys.cpu.dtb.read_acv 0 # DTB read access violations
testsys.cpu.dtb.read_accesses 0 # DTB read accesses
-testsys.cpu.dtb.write_hits 173 # DTB write hits
+testsys.cpu.dtb.write_hits 3933 # DTB write hits
testsys.cpu.dtb.write_misses 0 # DTB write misses
testsys.cpu.dtb.write_acv 0 # DTB write access violations
testsys.cpu.dtb.write_accesses 0 # DTB write accesses
-testsys.cpu.dtb.data_hits 482 # DTB hits
+testsys.cpu.dtb.data_hits 11002 # DTB hits
testsys.cpu.dtb.data_misses 0 # DTB misses
testsys.cpu.dtb.data_acv 0 # DTB access violations
testsys.cpu.dtb.data_accesses 0 # DTB accesses
-testsys.cpu.itb.fetch_hits 192 # ITB hits
+testsys.cpu.itb.fetch_hits 5992 # ITB hits
testsys.cpu.itb.fetch_misses 0 # ITB misses
testsys.cpu.itb.fetch_acv 0 # ITB acv
-testsys.cpu.itb.fetch_accesses 192 # ITB accesses
+testsys.cpu.itb.fetch_accesses 5992 # ITB accesses
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 1953126 # number of cpu cycles simulated
+testsys.cpu.numCycles 821760 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.committedInsts 1472 # Number of instructions committed
-testsys.cpu.committedOps 1472 # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses 1356 # Number of integer alu accesses
+testsys.cpu.committedInsts 36151 # Number of instructions committed
+testsys.cpu.committedOps 36151 # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses 33514 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-testsys.cpu.num_func_calls 68 # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts 107 # number of instructions that are conditional controls
-testsys.cpu.num_int_insts 1356 # number of integer instructions
+testsys.cpu.num_func_calls 2388 # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts 2348 # number of instructions that are conditional controls
+testsys.cpu.num_int_insts 33514 # number of integer instructions
testsys.cpu.num_fp_insts 0 # number of float instructions
-testsys.cpu.num_int_register_reads 1852 # number of times the integer registers were read
-testsys.cpu.num_int_register_writes 1059 # number of times the integer registers were written
+testsys.cpu.num_int_register_reads 43768 # number of times the integer registers were read
+testsys.cpu.num_int_register_writes 26496 # number of times the integer registers were written
testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-testsys.cpu.num_mem_refs 483 # number of memory refs
-testsys.cpu.num_load_insts 309 # Number of load instructions
-testsys.cpu.num_store_insts 174 # Number of store instructions
-testsys.cpu.num_idle_cycles 1949443.815916 # Number of idle cycles
-testsys.cpu.num_busy_cycles 3682.184084 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.001885 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.998115 # Percentage of idle cycles
+testsys.cpu.num_mem_refs 11043 # number of memory refs
+testsys.cpu.num_load_insts 7109 # Number of load instructions
+testsys.cpu.num_store_insts 3934 # Number of store instructions
+testsys.cpu.num_idle_cycles 785260.061817 # Number of idle cycles
+testsys.cpu.num_busy_cycles 36499.938183 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.044417 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.955583 # Percentage of idle cycles
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce 1 # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei 15 # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0 3 21.43% 21.43% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22 1 7.14% 28.57% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31 10 71.43% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total 14 # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0 3 42.86% 42.86% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22 1 14.29% 57.14% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31 3 42.86% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total 7 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0 975901000 99.93% 99.93% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22 43000 0.00% 99.94% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31 619000 0.06% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total 976563000 # number of cycles we spent at this ipl
+testsys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed
+testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks::0 398338500 96.95% 96.95% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.74% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.75% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31 9258500 2.25% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total 410880000 # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31 0.300000 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total 0.500000 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.callpal::swpipl 12 85.71% 85.71% # number of callpals executed
-testsys.cpu.kern.callpal::rdps 1 7.14% 92.86% # number of callpals executed
-testsys.cpu.kern.callpal::rti 1 7.14% 100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total 14 # number of callpals executed
+testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed
+testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed
+testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed
+testsys.cpu.kern.callpal::total 254 # number of callpals executed
testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle 1 # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches
testsys.cpu.kern.mode_good::kernel 0
testsys.cpu.kern.mode_good::user 0
testsys.cpu.kern.mode_good::idle 0
testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
-testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA
testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
+testsys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
+testsys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-drivesys.physmem.bytes_read::cpu.inst 5884 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::cpu.data 2272 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total 8156 # Number of bytes read from this memory
-drivesys.physmem.bytes_inst_read::cpu.inst 5884 # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_inst_read::total 5884 # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_written::cpu.data 1288 # Number of bytes written to this memory
-drivesys.physmem.bytes_written::total 1288 # Number of bytes written to this memory
-drivesys.physmem.num_reads::cpu.inst 1471 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::cpu.data 309 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total 1780 # Number of read requests responded to by this memory
-drivesys.physmem.num_writes::cpu.data 172 # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::total 172 # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst 15071972 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data 5819769 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total 20891741 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst 15071972 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total 15071972 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data 3299235 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total 3299235 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst 15071972 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total 24190977 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::total 296296 # Number of bytes read from this memory
+drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory
+drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory
+drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::total 47300 # Number of read requests responded to by this memory
+drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory
+drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory
+drivesys.physmem.bw_read::cpu.inst 355344119 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::total 728085868 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::cpu.inst 355344119 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::total 355344119 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.inst 355344119 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::total 796123376 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.readReqs 0 # Total number of read requests seen
drivesys.physmem.writeReqs 0 # Total number of write requests seen
drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
-drivesys.cpu.dtb.read_hits 309 # DTB read hits
+drivesys.cpu.dtb.read_hits 7069 # DTB read hits
drivesys.cpu.dtb.read_misses 0 # DTB read misses
drivesys.cpu.dtb.read_acv 0 # DTB read access violations
drivesys.cpu.dtb.read_accesses 0 # DTB read accesses
-drivesys.cpu.dtb.write_hits 173 # DTB write hits
+drivesys.cpu.dtb.write_hits 3933 # DTB write hits
drivesys.cpu.dtb.write_misses 0 # DTB write misses
drivesys.cpu.dtb.write_acv 0 # DTB write access violations
drivesys.cpu.dtb.write_accesses 0 # DTB write accesses
-drivesys.cpu.dtb.data_hits 482 # DTB hits
+drivesys.cpu.dtb.data_hits 11002 # DTB hits
drivesys.cpu.dtb.data_misses 0 # DTB misses
drivesys.cpu.dtb.data_acv 0 # DTB access violations
drivesys.cpu.dtb.data_accesses 0 # DTB accesses
-drivesys.cpu.itb.fetch_hits 192 # ITB hits
+drivesys.cpu.itb.fetch_hits 5992 # ITB hits
drivesys.cpu.itb.fetch_misses 0 # ITB misses
drivesys.cpu.itb.fetch_acv 0 # ITB acv
-drivesys.cpu.itb.fetch_accesses 192 # ITB accesses
+drivesys.cpu.itb.fetch_accesses 5992 # ITB accesses
drivesys.cpu.itb.read_hits 0 # DTB read hits
drivesys.cpu.itb.read_misses 0 # DTB read misses
drivesys.cpu.itb.read_acv 0 # DTB read access violations
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
-drivesys.cpu.numCycles 3906249 # number of cpu cycles simulated
+drivesys.cpu.numCycles 1628160 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-drivesys.cpu.committedInsts 1471 # Number of instructions committed
-drivesys.cpu.committedOps 1471 # Number of ops (including micro ops) committed
-drivesys.cpu.num_int_alu_accesses 1354 # Number of integer alu accesses
+drivesys.cpu.committedInsts 36152 # Number of instructions committed
+drivesys.cpu.committedOps 36152 # Number of ops (including micro ops) committed
+drivesys.cpu.num_int_alu_accesses 33516 # Number of integer alu accesses
drivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-drivesys.cpu.num_func_calls 68 # number of times a function call or return occured
-drivesys.cpu.num_conditional_control_insts 108 # number of instructions that are conditional controls
-drivesys.cpu.num_int_insts 1354 # number of integer instructions
+drivesys.cpu.num_func_calls 2388 # number of times a function call or return occured
+drivesys.cpu.num_conditional_control_insts 2347 # number of instructions that are conditional controls
+drivesys.cpu.num_int_insts 33516 # number of integer instructions
drivesys.cpu.num_fp_insts 0 # number of float instructions
-drivesys.cpu.num_int_register_reads 1848 # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes 1056 # number of times the integer registers were written
+drivesys.cpu.num_int_register_reads 43772 # number of times the integer registers were read
+drivesys.cpu.num_int_register_writes 26499 # number of times the integer registers were written
drivesys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
drivesys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-drivesys.cpu.num_mem_refs 483 # number of memory refs
-drivesys.cpu.num_load_insts 309 # Number of load instructions
-drivesys.cpu.num_store_insts 174 # Number of store instructions
-drivesys.cpu.num_idle_cycles 3902569.320225 # Number of idle cycles
-drivesys.cpu.num_busy_cycles 3679.679775 # Number of busy cycles
-drivesys.cpu.not_idle_fraction 0.000942 # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction 0.999058 # Percentage of idle cycles
+drivesys.cpu.num_mem_refs 11043 # number of memory refs
+drivesys.cpu.num_load_insts 7109 # Number of load instructions
+drivesys.cpu.num_store_insts 3934 # Number of store instructions
+drivesys.cpu.num_idle_cycles 1592000.182518 # Number of idle cycles
+drivesys.cpu.num_busy_cycles 36159.817482 # Number of busy cycles
+drivesys.cpu.not_idle_fraction 0.022209 # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction 0.977791 # Percentage of idle cycles
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
-drivesys.cpu.kern.inst.quiesce 1 # number of quiesce instructions executed
-drivesys.cpu.kern.inst.hwrei 15 # number of hwrei instructions executed
-drivesys.cpu.kern.ipl_count::0 3 21.43% 21.43% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::22 1 7.14% 28.57% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31 10 71.43% 100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total 14 # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0 3 42.86% 42.86% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::22 1 14.29% 57.14% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31 3 42.86% 100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total 7 # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0 976231500 99.97% 99.97% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::22 21500 0.00% 99.97% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31 309250 0.03% 100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total 976562250 # number of cycles we spent at this ipl
+drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed
+drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
+drivesys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_ticks::0 400769000 98.46% 98.46% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::total 407040000 # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31 0.300000 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::total 0.500000 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.callpal::swpipl 12 85.71% 85.71% # number of callpals executed
-drivesys.cpu.kern.callpal::rdps 1 7.14% 92.86% # number of callpals executed
-drivesys.cpu.kern.callpal::rti 1 7.14% 100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total 14 # number of callpals executed
+drivesys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed
+drivesys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed
+drivesys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed
+drivesys.cpu.kern.callpal::total 254 # number of callpals executed
drivesys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
drivesys.cpu.kern.mode_switch::user 0 # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle 1 # number of protection mode switches
+drivesys.cpu.kern.mode_switch::idle 41 # number of protection mode switches
drivesys.cpu.kern.mode_good::kernel 0
drivesys.cpu.kern.mode_good::user 0
drivesys.cpu.kern.mode_good::idle 0
drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
-drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA
drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
+drivesys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
+drivesys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
[system.cpu.checker]
type=O3Checker
-children=dtb itb tracer
+children=dtb isa itb tracer
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=Null
+isa=system.cpu.checker.isa
itb=system.cpu.checker.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.checker.tracer
updateOnError=true
sys=system
port=system.cpu.toL2Bus.slave[5]
+[system.cpu.checker.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.checker.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 1 2012 15:18:10
-gem5 started Nov 1 2012 22:40:56
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:26:41
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 13371000 because target called exit()
+Exiting @ tick 13372000 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 13371000 # Number of ticks simulated
-final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 13372000 # Number of ticks simulated
+final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32987 # Simulator instruction rate (inst/s)
-host_op_rate 41149 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 95942804 # Simulator tick rate (ticks/s)
-host_mem_usage 272856 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_inst_rate 16216 # Simulator instruction rate (inst/s)
+host_op_rate 20228 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47166036 # Simulator tick rate (ticks/s)
+host_mem_usage 230800 # Number of bytes of host memory used
+host_seconds 0.28 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 394 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13312500 # Total gap between requests
+system.physmem.totGap 13314500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.avgBankLat 16558.38 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 26804.30 # Average memory access latency
-system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s
+system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 11.79 # Data bus utilization in percentage
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 33788.07 # Average gap between requests
+system.physmem.avgGap 33793.15 # Average gap between requests
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 26743 # number of cpu cycles simulated
+system.cpu.numCycles 26745 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2505 # Number of BP lookups
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2247 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename
+system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer
system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
-system.cpu.iq.rate 0.336088 # Inst issue rate
+system.cpu.iq.rate 0.336063 # Inst issue rate
system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
system.cpu.iew.exec_branches 1446 # Number of branches executed
system.cpu.iew.exec_stores 1164 # Number of stores executed
-system.cpu.iew.exec_rate 0.320233 # Inst execution rate
+system.cpu.iew.exec_rate 0.320209 # Inst execution rate
system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8109 # cumulative count of insts written-back
system.cpu.iew.wb_producers 3899 # num instructions producing a value
system.cpu.iew.wb_consumers 7837 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle
+system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit
system.cpu.rob.rob_reads 22988 # The number of ROB reads
system.cpu.rob.rob_writes 23599 # The number of ROB writes
system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4596 # Number of Instructions Simulated
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
-system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads
+system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 39369 # number of integer regfile reads
system.cpu.int_regfile_writes 8027 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use
system.cpu.icache.total_refs 1601 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits
system.cpu.icache.overall_hits::total 1601 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
-system.cpu.icache.overall_misses::total 359 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency
+system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
+system.cpu.icache.overall_misses::total 360 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
+system.cpu.l2cache.overall_hits::total 40 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
+system.cpu.l2cache.overall_misses::total 399 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use
system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
system.cpu.dcache.overall_misses::total 498 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
-system.cpu.l2cache.overall_hits::total 40 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
-system.cpu.l2cache.overall_misses::total 399 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13735000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4675000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 18410000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/arm/linux/hello
+executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 18:52:17
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:26:30
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 13371000 because target called exit()
+Exiting @ tick 13372000 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 13371000 # Number of ticks simulated
-final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 13372000 # Number of ticks simulated
+final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 36978 # Simulator instruction rate (inst/s)
-host_op_rate 46127 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 107546339 # Simulator tick rate (ticks/s)
-host_mem_usage 272728 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
+host_inst_rate 20879 # Simulator instruction rate (inst/s)
+host_op_rate 26045 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 60729168 # Simulator tick rate (ticks/s)
+host_mem_usage 230484 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 394 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13312500 # Total gap between requests
+system.physmem.totGap 13314500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.avgBankLat 16558.38 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 26804.30 # Average memory access latency
-system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s
+system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 11.79 # Data bus utilization in percentage
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 33788.07 # Average gap between requests
+system.physmem.avgGap 33793.15 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 26743 # number of cpu cycles simulated
+system.cpu.numCycles 26745 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2505 # Number of BP lookups
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2247 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename
+system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer
system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
-system.cpu.iq.rate 0.336088 # Inst issue rate
+system.cpu.iq.rate 0.336063 # Inst issue rate
system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
system.cpu.iew.exec_branches 1446 # Number of branches executed
system.cpu.iew.exec_stores 1164 # Number of stores executed
-system.cpu.iew.exec_rate 0.320233 # Inst execution rate
+system.cpu.iew.exec_rate 0.320209 # Inst execution rate
system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8109 # cumulative count of insts written-back
system.cpu.iew.wb_producers 3899 # num instructions producing a value
system.cpu.iew.wb_consumers 7837 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle
+system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit
system.cpu.rob.rob_reads 22988 # The number of ROB reads
system.cpu.rob.rob_writes 23599 # The number of ROB writes
system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4596 # Number of Instructions Simulated
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
-system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads
+system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 39369 # number of integer regfile reads
system.cpu.int_regfile_writes 8027 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use
system.cpu.icache.total_refs 1601 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits
system.cpu.icache.overall_hits::total 1601 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
-system.cpu.icache.overall_misses::total 359 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency
+system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
+system.cpu.icache.overall_misses::total 360 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
+system.cpu.l2cache.overall_hits::total 40 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
+system.cpu.l2cache.overall_misses::total 399 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use
system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
system.cpu.dcache.overall_misses::total 498 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
-system.cpu.l2cache.overall_hits::total 40 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
-system.cpu.l2cache.overall_misses::total 399 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13735000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4675000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 18410000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello
+executable=/gem5/dist/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:08:52
-gem5 started Oct 30 2012 13:57:41
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:13:46
+gem5 started Jan 4 2013 21:58:53
+gem5 executing on u200540
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 16532500 # Number of ticks simulated
final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 48770 # Simulator instruction rate (inst/s)
-host_op_rate 48763 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 156337427 # Simulator tick rate (ticks/s)
-host_mem_usage 215260 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 25568 # Simulator instruction rate (inst/s)
+host_op_rate 25564 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 81956278 # Simulator tick rate (ticks/s)
+host_mem_usage 217336 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 16452500 # Total gap between requests
+system.physmem.totGap 16453500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2527972 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13083972 # Sum of mem lat for all requests
+system.physmem.totQLat 2530972 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13086972 # Sum of mem lat for all requests
system.physmem.totBusLat 1904000 # Total cycles spent in databus access
system.physmem.totBankLat 8652000 # Total cycles spent in bank access
-system.physmem.avgQLat 5310.87 # Average queueing delay per request
+system.physmem.avgQLat 5317.17 # Average queueing delay per request
system.physmem.avgBankLat 18176.47 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27487.34 # Average memory access latency
+system.physmem.avgMemAccLat 27493.64 # Average memory access latency
system.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 34564.08 # Average gap between requests
+system.physmem.avgGap 34566.18 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 258 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 8641 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 8642 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.CacheLines 1949 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.misc_regfile_reads 147 # number of misc regfile reads
system.cpu.icache.replacements 17 # number of replacements
-system.cpu.icache.tagsinuse 163.149412 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 163.159030 # Cycle average of tags in use
system.cpu.icache.total_refs 1502 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 163.149412 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.079663 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.079663 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 163.159030 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.079667 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.079667 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits
system.cpu.icache.overall_hits::total 1502 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses
-system.cpu.icache.overall_misses::total 446 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 21402000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 21402000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 21402000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 21402000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 21402000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 21402000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47986.547085 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 47986.547085 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 47986.547085 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 47986.547085 # average overall miss latency
+system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses
+system.cpu.icache.overall_misses::total 447 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 21475500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 21475500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 21475500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 21475500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 21475500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 21475500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1949 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1949 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1949 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1949 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1949 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1949 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229348 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.229348 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.229348 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.229348 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.229348 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.229348 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48043.624161 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48043.624161 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48043.624161 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48043.624161 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 109 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 109 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 109 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 109 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 109 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16954500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 16954500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16954500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 16954500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16954500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 16954500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173511 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.173511 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.173511 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50161.242604 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50161.242604 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16956000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 16956000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16956000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 16956000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16956000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 16956000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173422 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.173422 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.173422 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50165.680473 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50165.680473 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50165.680473 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50165.680473 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50165.680473 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50165.680473 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 223.784369 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 223.797313 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 425 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.007059 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 165.662974 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 58.121395 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 165.672562 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 58.124752 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005056 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.006829 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006830 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
system.cpu.l2cache.overall_misses::total 476 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16586500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5449500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 22036000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16588000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5450000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 22038000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2702000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 16586500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 24738000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 16586500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 24738000 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 16588000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 8152000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 24740000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 16588000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 8152000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 24740000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49511.940299 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60550 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 51849.411765 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49516.417910 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60555.555556 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51854.117647 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52980.392157 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52980.392157 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49511.940299 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57812.056738 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51970.588235 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49511.940299 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57812.056738 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51970.588235 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49516.417910 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57815.602837 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51974.789916 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49516.417910 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57815.602837 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51974.789916 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12363045 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4340573 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16703618 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12365045 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4341573 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16706618 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12363045 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6411627 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 18774672 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12363045 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6411627 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 18774672 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12365045 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6412627 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18777672 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12365045 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6412627 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18777672 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36904.611940 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48228.588889 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39302.630588 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36910.582090 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48239.700000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.689412 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 92.011405 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 92.017211 # Cycle average of tags in use
system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 17.163121 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 92.011405 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.022464 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.022464 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data 92.017211 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.022465 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.022465 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1848 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1848 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits
system.cpu.dcache.demand_misses::total 504 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 504 # number of overall misses
system.cpu.dcache.overall_misses::total 504 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8901000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8901000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8905500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8905500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15603499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 15603499 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 24504499 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 24504499 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 24504499 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 24504499 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 24508999 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 24508999 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 24508999 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 24508999 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.172367 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.172367 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.172367 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58947.019868 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 58947.019868 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58976.821192 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 58976.821192 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44202.546742 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 44202.546742 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 48620.037698 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 48620.037698 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 48628.966270 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 48628.966270 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8296999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8296999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8296999 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8296999 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8297499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8297499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8297499 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8297499 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61588.888889 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61588.888889 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61594.444444 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61594.444444 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/power/linux/hello
+executable=/gem5/dist/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:09:52
-gem5 started Oct 30 2012 13:58:22
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:14:12
+gem5 started Jan 4 2013 21:59:04
+gem5 executing on u200540
command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 14065500 # Number of ticks simulated
final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 60799 # Simulator instruction rate (inst/s)
-host_op_rate 60790 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 147601989 # Simulator tick rate (ticks/s)
-host_mem_usage 210652 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 28037 # Simulator instruction rate (inst/s)
+host_op_rate 28032 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68062430 # Simulator tick rate (ticks/s)
+host_mem_usage 213288 # Number of bytes of host memory used
+host_seconds 0.21 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13957000 # Total gap between requests
+system.physmem.totGap 13958000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1923444 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11085444 # Sum of mem lat for all requests
+system.physmem.totQLat 1923944 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11085944 # Sum of mem lat for all requests
system.physmem.totBusLat 1784000 # Total cycles spent in databus access
system.physmem.totBankLat 7378000 # Total cycles spent in bank access
-system.physmem.avgQLat 4312.65 # Average queueing delay per request
+system.physmem.avgQLat 4313.78 # Average queueing delay per request
system.physmem.avgBankLat 16542.60 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 24855.26 # Average memory access latency
+system.physmem.avgMemAccLat 24856.38 # Average memory access latency
system.physmem.avgRdBW 2029.36 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2029.36 # Average consumed read bandwidth in MB/s
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 31293.72 # Average gap between requests
+system.physmem.avgGap 31295.96 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 198 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 7397 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 7398 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2267 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 1136 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 1812 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 306 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 11663 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.133328 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.550093 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 168.326699 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 168.326770 # Cycle average of tags in use
system.cpu.icache.total_refs 1375 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 3.917379 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 168.326699 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 168.326770 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.082191 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.082191 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1375 # number of ReadReq hits
system.cpu.icache.demand_hits::total 1375 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1375 # number of overall hits
system.cpu.icache.overall_hits::total 1375 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
-system.cpu.icache.overall_misses::total 437 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 20187000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 20187000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 20187000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 20187000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 20187000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 20187000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1812 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1812 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1812 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1812 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1812 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1812 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241170 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.241170 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.241170 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.241170 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.241170 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.241170 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46194.508009 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 46194.508009 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 46194.508009 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 46194.508009 # average overall miss latency
+system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses
+system.cpu.icache.overall_misses::total 438 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 20259000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 20259000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 20259000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 20259000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 20259000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 20259000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241589 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.241589 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.241589 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.241589 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.241589 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.241589 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.424658 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 46253.424658 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 46253.424658 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 46253.424658 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 87 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 87 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 87 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16769000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 16769000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16769000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 16769000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16769000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 16769000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193709 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.193709 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.193709 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47774.928775 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47774.928775 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16770000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 16770000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16770000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 16770000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16770000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 16770000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47777.777778 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47777.777778 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 198.645490 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 198.645596 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 167.286066 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 167.286173 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 31.359424 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005105 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16357500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2980500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 19338000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2765500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2765500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 16357500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 5746000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 22103500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 16357500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 5746000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 22103500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16358500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2981000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 19339500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2766000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2766000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 16358500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 5747000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 22105500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 16358500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 5747000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 22105500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47413.043478 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55194.444444 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 48466.165414 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58840.425532 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58840.425532 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47413.043478 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56891.089109 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 49559.417040 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47413.043478 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56891.089109 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 49559.417040 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47415.942029 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55203.703704 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 48469.924812 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58851.063830 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58851.063830 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47415.942029 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56900.990099 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 49563.901345 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47415.942029 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56900.990099 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 49563.901345 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12035015 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2314548 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14349563 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2186544 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2186544 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12035015 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4501092 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16536107 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12035015 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4501092 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16536107 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12035515 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2315048 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14350563 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2187044 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2187044 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12035515 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4502092 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16537607 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12035515 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4502092 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16537607 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34884.101449 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42862 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35963.817043 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46522.212766 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46522.212766 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34885.550725 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42871.259259 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35966.323308 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46532.851064 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46532.851064 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 63.407702 # Cycle average of tags in use
system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses
system.cpu.dcache.overall_misses::total 435 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5221500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5221500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 14127997 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 14127997 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 19349497 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 19349497 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 19349497 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 19349497 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5222000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 14128997 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 14128997 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 19350997 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 19350997 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 19350997 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 19350997 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1579 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1579 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.165714 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.165714 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.165714 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.730769 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.730769 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42682.770393 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 42682.770393 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 44481.602299 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 44481.602299 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50211.538462 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50211.538462 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42685.791541 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42685.791541 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 44485.050575 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 44485.050575 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 414 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2814999 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2814999 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5860999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 5860999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5860999 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 5860999 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2815499 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2815499 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5861999 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 5861999 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5861999 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 5861999 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034832 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034832 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.038857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.038857 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55381.818182 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55381.818182 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59893.595745 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59893.595745 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55390.909091 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55390.909091 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59904.234043 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59904.234043 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/gem5/dist/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:12:54
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 4 2013 21:20:54
+gem5 started Jan 4 2013 22:09:04
+gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 15014000 # Number of ticks simulated
final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 27939 # Simulator instruction rate (inst/s)
-host_op_rate 50607 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 77954156 # Simulator tick rate (ticks/s)
-host_mem_usage 273052 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 15963 # Simulator instruction rate (inst/s)
+host_op_rate 28915 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44538984 # Simulator tick rate (ticks/s)
+host_mem_usage 232848 # Number of bytes of host memory used
+host_seconds 0.34 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9746 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 14992500 # Total gap between requests
+system.physmem.totGap 14993500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 33316.67 # Average gap between requests
+system.physmem.avgGap 33318.89 # Average gap between requests
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 30029 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 8962 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 8963 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed
system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.CacheLines 1881 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
system.cpu.misc_regfile_reads 7157 # number of misc regfile reads
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 144.838495 # Cycle average of tags in use
system.cpu.icache.total_refs 1482 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 144.838361 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 144.838495 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits
system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits
system.cpu.icache.overall_hits::total 1482 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses
-system.cpu.icache.overall_misses::total 398 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 19300000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 19300000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 19300000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 19300000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 19300000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 19300000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1880 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1880 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1880 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1880 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1880 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1880 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.211702 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.211702 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.211702 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.211702 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.211702 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.211702 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48492.462312 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 48492.462312 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 48492.462312 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 48492.462312 # average overall miss latency
+system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses
+system.cpu.icache.overall_misses::total 399 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 19371000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 19371000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 19371000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 19371000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 19371000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 19371000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1881 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1881 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1881 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1881 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1881 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1881 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212121 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.212121 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.212121 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.212121 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.212121 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.212121 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48548.872180 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48548.872180 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48548.872180 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48548.872180 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161702 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.161702 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.161702 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161616 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.161616 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.161616 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits
-system.cpu.dcache.overall_hits::total 2284 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
-system.cpu.dcache.overall_misses::total 202 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 178.021458 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 144.985294 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 33.036031 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 144.985394 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 33.036064 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004425 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005433 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
system.cpu.l2cache.overall_misses::total 450 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15146500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 18957500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 18958000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3992500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15146500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7803500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 22950000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7804000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 22950500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15146500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7803500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 22950000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7804000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 22950500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 375 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997783 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49988.448845 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53676.056338 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 50688.502674 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53683.098592 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 50689.839572 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52532.894737 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51001.111111 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51001.111111 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336452 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336952 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2944072 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14280524 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14281024 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3029110 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3029110 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336452 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336952 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5973182 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 17309634 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336452 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17310134 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336952 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5973182 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 17309634 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17310134 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997333 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.033003 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.683168 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38183.219251 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38184.556150 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits
+system.cpu.dcache.overall_hits::total 2284 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
+system.cpu.dcache.overall_misses::total 202 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 6336500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 10557000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 10557000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 10557000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 10557000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50289.682540 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50289.682540 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 52262.376238 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 52262.376238 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7804000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7804000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7804000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7804000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52612.676056 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52612.676056 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=/gem5/dist/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:40
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:16:54
+gem5 started Jan 4 2013 21:59:36
+gem5 executing on u200540
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 23190500 because target called exit()
+Exiting @ tick 23180500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000023 # Number of seconds simulated
-sim_ticks 23190500 # Number of ticks simulated
-final_tick 23190500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 23180500 # Number of ticks simulated
+final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 24201 # Simulator instruction rate (inst/s)
-host_op_rate 24200 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38875523 # Simulator tick rate (ticks/s)
-host_mem_usage 222232 # Number of bytes of host memory used
-host_seconds 0.60 # Real time elapsed on the host
+host_inst_rate 21899 # Simulator instruction rate (inst/s)
+host_op_rate 21897 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 35159544 # Simulator tick rate (ticks/s)
+host_mem_usage 223288 # Number of bytes of host memory used
+host_seconds 0.66 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 927276255 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 405683362 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1332959617 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 927276255 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 927276255 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 927276255 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 405683362 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1332959617 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 927676280 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 405858372 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1333534652 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 927676280 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 927676280 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 927676280 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 405858372 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1333534652 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 483 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 23130500 # Total gap between requests
+system.physmem.totGap 23120500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2984483 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12938483 # Sum of mem lat for all requests
+system.physmem.totQLat 3040483 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12980483 # Sum of mem lat for all requests
system.physmem.totBusLat 1932000 # Total cycles spent in databus access
-system.physmem.totBankLat 8022000 # Total cycles spent in bank access
-system.physmem.avgQLat 6179.05 # Average queueing delay per request
-system.physmem.avgBankLat 16608.70 # Average bank access latency per request
+system.physmem.totBankLat 8008000 # Total cycles spent in bank access
+system.physmem.avgQLat 6295.00 # Average queueing delay per request
+system.physmem.avgBankLat 16579.71 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26787.75 # Average memory access latency
-system.physmem.avgRdBW 1332.96 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26874.71 # Average memory access latency
+system.physmem.avgRdBW 1333.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1332.96 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1333.53 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 8.33 # Data bus utilization in percentage
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 47889.23 # Average gap between requests
+system.physmem.avgGap 47868.53 # Average gap between requests
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 46382 # number of cpu cycles simulated
+system.cpu.numCycles 46362 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6758 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 4516 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 6759 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 4517 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1074 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 4657 # Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 4658 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 2448 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 31427 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6758 # Number of branches that fetch encountered
+system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 9180 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3075 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 8320 # Number of cycles fetch has spent blocked
+system.cpu.fetch.Cycles 9181 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3076 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 8341 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 5337 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 32520 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.966390 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.158060 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 5338 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 32543 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.965953 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.157796 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 23340 71.77% 71.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4525 13.91% 85.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 464 1.43% 87.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 371 1.14% 88.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 23362 71.79% 71.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4525 13.90% 85.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 464 1.43% 87.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 371 1.14% 88.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1896 5.83% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1897 5.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 32520 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.145703 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.677569 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::total 32543 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.145787 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.678034 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9195 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 8404 # Number of cycles decode is running
+system.cpu.decode.BlockedCycles 9216 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 8405 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 29366 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13469 # Number of cycles rename is idle
+system.cpu.decode.SquashCycles 1906 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 29374 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1906 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13470 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 8329 # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles 8350 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 8008 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename
system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 691 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2732 # count of insts added to the skid buffer
+system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 2330 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 2331 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 22740 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 22748 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21250 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 137 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8195 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 5897 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 21285 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 8188 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 5672 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 32520 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.653444 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.275128 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 32543 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.654058 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.275967 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 23284 71.60% 71.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3476 10.69% 82.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 913 2.81% 97.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 23299 71.59% 71.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3475 10.68% 82.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 922 2.83% 97.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 32520 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 32543 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 15763 74.18% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 3339 15.71% 89.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 2148 10.11% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 15766 74.07% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 3371 15.84% 89.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 2148 10.09% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 21250 # Type of FU issued
-system.cpu.iq.rate 0.458152 # Inst issue rate
+system.cpu.iq.FU_type_0::total 21285 # Type of FU issued
+system.cpu.iq.rate 0.459104 # Inst issue rate
system.cpu.iq.fu_busy_cnt 153 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007200 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 75310 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 31611 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19572 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.007188 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 75371 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 31612 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21403 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21438 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 883 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 1906 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 24529 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 387 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispatchedInsts 24537 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2330 # Number of dispatched store instructions
+system.cpu.iew.iewDispStoreInsts 2331 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20156 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 3213 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1094 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 20207 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 3221 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1078 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1139 # number of nop insts executed
-system.cpu.iew.exec_refs 5233 # number of memory reference insts executed
+system.cpu.iew.exec_refs 5276 # number of memory reference insts executed
system.cpu.iew.exec_branches 4247 # Number of branches executed
-system.cpu.iew.exec_stores 2020 # Number of stores executed
-system.cpu.iew.exec_rate 0.434565 # Inst execution rate
-system.cpu.iew.wb_sent 19807 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 19572 # cumulative count of insts written-back
+system.cpu.iew.exec_stores 2055 # Number of stores executed
+system.cpu.iew.exec_rate 0.435853 # Inst execution rate
+system.cpu.iew.wb_sent 19873 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 19647 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9210 # num instructions producing a value
system.cpu.iew.wb_consumers 11373 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.421974 # insts written-back per cycle
+system.cpu.iew.wb_rate 0.423774 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 9292 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9300 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 30632 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.494973 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.191764 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 30637 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.494892 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.191683 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 23334 76.18% 76.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 23339 76.18% 76.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1377 4.50% 93.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1377 4.49% 93.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 30632 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 30637 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 54149 # The number of ROB reads
-system.cpu.rob.rob_writes 50819 # The number of ROB writes
+system.cpu.rob.rob_reads 54162 # The number of ROB reads
+system.cpu.rob.rob_writes 50836 # The number of ROB writes
system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13862 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 13819 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
-system.cpu.cpi 3.212940 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.212940 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.311241 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.311241 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 32188 # number of integer regfile reads
-system.cpu.int_regfile_writes 17920 # number of integer regfile writes
-system.cpu.misc_regfile_reads 6865 # number of misc regfile reads
+system.cpu.cpi 3.211554 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.211554 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.311376 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.311376 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 32290 # number of integer regfile reads
+system.cpu.int_regfile_writes 17967 # number of integer regfile writes
+system.cpu.misc_regfile_reads 6967 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 191.561206 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 191.466325 # Cycle average of tags in use
system.cpu.icache.total_refs 4845 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14.334320 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 191.561206 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.093536 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.093536 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 191.466325 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.093489 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.093489 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4845 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4845 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4845 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4845 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4845 # number of overall hits
system.cpu.icache.overall_hits::total 4845 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 492 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 492 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 492 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 492 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 492 # number of overall misses
-system.cpu.icache.overall_misses::total 492 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 23061000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 23061000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 23061000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 23061000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 23061000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 23061000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5337 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5337 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5337 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5337 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5337 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5337 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092187 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.092187 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.092187 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.092187 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.092187 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.092187 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46871.951220 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 46871.951220 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 46871.951220 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 46871.951220 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 46871.951220 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 46871.951220 # average overall miss latency
+system.cpu.icache.ReadReq_misses::cpu.inst 493 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 493 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 493 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 493 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 493 # number of overall misses
+system.cpu.icache.overall_misses::total 493 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 23383000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 23383000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 23383000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 23383000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 23383000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 23383000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5338 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5338 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5338 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5338 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5338 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5338 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092357 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.092357 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.092357 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.092357 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.092357 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.092357 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47430.020284 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 47430.020284 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 47430.020284 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 47430.020284 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 154 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 154 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 154 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 154 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 155 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 155 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 155 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 155 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 155 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17056000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 17056000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17056000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 17056000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17056000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 17056000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063331 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063331 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063331 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.063331 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063331 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.063331 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50461.538462 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50461.538462 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50461.538462 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 50461.538462 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50461.538462 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 50461.538462 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17113500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 17113500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17113500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 17113500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17113500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 17113500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063320 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.063320 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.063320 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50631.656805 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50631.656805 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 99.978765 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4011 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 27.285714 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 99.978765 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.024409 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.024409 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 2972 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 2972 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 4005 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 4005 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 4005 # number of overall hits
-system.cpu.dcache.overall_hits::total 4005 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 130 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 130 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses
-system.cpu.dcache.overall_misses::total 539 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 6945000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 6945000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 19513974 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 19513974 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 26458974 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 26458974 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 26458974 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 26458974 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 3102 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 3102 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 4544 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 4544 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 4544 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 4544 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041908 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.041908 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.118618 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.118618 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.118618 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.118618 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53423.076923 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53423.076923 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47711.427873 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47711.427873 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 49089.005566 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 49089.005566 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 49089.005566 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 49089.005566 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3837000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3837000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4507500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4507500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8344500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8344500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8344500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8344500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020632 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020632 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032350 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.032350 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032350 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032350 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59953.125000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59953.125000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54307.228916 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54307.228916 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56765.306122 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 56765.306122 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56765.306122 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 56765.306122 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 225.876311 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 225.767373 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 190.966695 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 34.909617 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.005828 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 190.872097 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 34.895277 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.005825 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001065 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.006893 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006890 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
system.cpu.l2cache.overall_misses::total 483 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16698000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3772500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 20470500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4423500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 4423500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 16698000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 8196000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 24894000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 16698000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 8196000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 24894000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16755500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3772000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 20527500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4421500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 4421500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 16755500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 8193500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 24949000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 16755500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 8193500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 24949000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49696.428571 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58945.312500 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 51176.250000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53295.180723 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53295.180723 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49696.428571 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55755.102041 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51540.372671 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49696.428571 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55755.102041 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51540.372671 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49867.559524 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58937.500000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51318.750000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53271.084337 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53271.084337 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51654.244306 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51654.244306 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12468016 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12529012 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2980062 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15448078 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3402062 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3402062 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12468016 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6382124 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 18850140 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12468016 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6382124 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 18850140 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15509074 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3397062 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3397062 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12529012 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6377124 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18906136 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12529012 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6377124 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18906136 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37107.190476 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37288.726190 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38620.195000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40988.698795 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40988.698795 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37107.190476 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43415.809524 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39027.204969 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37107.190476 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43415.809524 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39027.204969 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38772.685000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40928.457831 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40928.457831 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 99.943036 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4019 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 27.340136 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 99.943036 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.024400 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.024400 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 2980 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 2980 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 4013 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 4013 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 4013 # number of overall hits
+system.cpu.dcache.overall_hits::total 4013 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 130 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 130 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses
+system.cpu.dcache.overall_misses::total 539 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 6943000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 6943000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 19544474 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 19544474 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 26487474 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 26487474 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 26487474 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 26487474 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 3110 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 3110 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 4552 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 4552 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 4552 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 4552 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041801 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.041801 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.118409 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.118409 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.118409 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.118409 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53407.692308 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53407.692308 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47786 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47786 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 49141.881262 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 49141.881262 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3836500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3836500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8342000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8342000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8342000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8342000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020579 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020579 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.032293 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.032293 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59945.312500 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59945.312500 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54283.132530 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54283.132530 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
kernel=
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu0]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb tracer workload
+children=dcache dtb fuPool icache interrupts isa itb tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
[system.cpu0.interrupts]
type=SparcInterrupts
+[system.cpu0.isa]
+type=SparcISA
+
[system.cpu0.itb]
type=SparcTLB
size=64
env=
errout=cerr
euid=100
-executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/gem5/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
[system.cpu1]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb tracer
+children=dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
[system.cpu1.interrupts]
type=SparcInterrupts
+[system.cpu1.isa]
+type=SparcISA
+
[system.cpu1.itb]
type=SparcTLB
size=64
[system.cpu2]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb tracer
+children=dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu2.interrupts
+isa=system.cpu2.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu2.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu2.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
[system.cpu2.interrupts]
type=SparcInterrupts
+[system.cpu2.isa]
+type=SparcISA
+
[system.cpu2.itb]
type=SparcTLB
size=64
[system.cpu3]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb tracer
+children=dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu3.interrupts
+isa=system.cpu3.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu3.itb
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu3.tracer
trapLatency=13
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
[system.cpu3.interrupts]
type=SparcInterrupts
+[system.cpu3.isa]
+type=SparcISA
+
[system.cpu3.itb]
type=SparcTLB
size=64
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:40
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:16:54
+gem5 started Jan 4 2013 21:59:48
+gem5 executing on u200540
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
Iteration 10 completed
PASSED :-)
-Exiting @ tick 104830500 because target called exit()
+Exiting @ tick 104832500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000105 # Number of seconds simulated
-sim_ticks 104830500 # Number of ticks simulated
-final_tick 104830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 104832500 # Number of ticks simulated
+final_tick 104832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 112424 # Simulator instruction rate (inst/s)
-host_op_rate 112424 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 11388036 # Simulator tick rate (ticks/s)
-host_mem_usage 275264 # Number of bytes of host memory used
-host_seconds 9.21 # Real time elapsed on the host
-sim_insts 1034897 # Number of instructions simulated
-sim_ops 1034897 # Number of ops (including micro ops) simulated
+host_inst_rate 49068 # Simulator instruction rate (inst/s)
+host_op_rate 49068 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4970400 # Simulator tick rate (ticks/s)
+host_mem_usage 237836 # Number of bytes of host memory used
+host_seconds 21.09 # Real time elapsed on the host
+sim_insts 1034907 # Number of instructions simulated
+sim_ops 1034907 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 5184 # Number of bytes read from this memory
system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 658 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 217341327 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 102565570 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 49451257 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 12210187 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 1831528 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 7936621 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 2442037 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7936621 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 401715150 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 217341327 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 49451257 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 1831528 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 2442037 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 271066150 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 217341327 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 102565570 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 49451257 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 12210187 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 1831528 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 7936621 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 2442037 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7936621 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 401715150 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 217337181 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 102563613 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 49450314 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 12209954 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 1831493 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 7936470 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 2441991 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7936470 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 401707486 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 217337181 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 49450314 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 1831493 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 2441991 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 271060978 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 217337181 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 102563613 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 49450314 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 12209954 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 1831493 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 7936470 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 2441991 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7936470 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 401707486 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 659 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 980 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 104802500 # Total gap between requests
+system.physmem.totGap 104804500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2987155 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 17761155 # Sum of mem lat for all requests
+system.physmem.totQLat 2976655 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 17750655 # Sum of mem lat for all requests
system.physmem.totBusLat 2636000 # Total cycles spent in databus access
system.physmem.totBankLat 12138000 # Total cycles spent in bank access
-system.physmem.avgQLat 4532.86 # Average queueing delay per request
+system.physmem.avgQLat 4516.93 # Average queueing delay per request
system.physmem.avgBankLat 18418.82 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26951.68 # Average memory access latency
-system.physmem.avgRdBW 401.72 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26935.74 # Average memory access latency
+system.physmem.avgRdBW 401.71 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 401.72 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 401.71 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.51 # Data bus utilization in percentage
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 159032.63 # Average gap between requests
+system.physmem.avgGap 159035.66 # Average gap between requests
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 209662 # number of cpu cycles simulated
+system.cpu0.numCycles 209666 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.BPredUnit.lookups 82004 # Number of BP lookups
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS 516 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 16907 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.icacheStallCycles 16910 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 159637 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 3804 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 12545 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.BlockedCycles 12561 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 1361 # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines 5871 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 192893 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.523176 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.215866 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.IcacheSquashes 483 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 192912 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.522928 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.215898 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 33256 17.24% 17.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 79042 40.98% 58.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 33275 17.25% 17.25% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 79042 40.97% 58.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 584 0.30% 58.52% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 987 0.51% 59.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 987 0.51% 59.04% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 454 0.24% 59.27% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 75108 38.94% 98.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 578 0.30% 98.50% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 75108 38.93% 98.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 578 0.30% 98.51% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 364 0.19% 98.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 2520 1.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 192893 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.391125 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.321370 # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist::total 192912 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.391117 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.321325 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 17503 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 14000 # Number of cycles decode is blocked
+system.cpu0.decode.BlockedCycles 14019 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 158668 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 284 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 2438 # Number of cycles decode is squashing
system.cpu0.rename.SquashCycles 2438 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 18159 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 648 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 12765 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.serializeStallCycles 12784 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 158332 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 551 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 480873 # Number of instructions processed by rename
system.cpu0.rename.UndoneMaps 13032 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 877 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 903 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 3587 # count of insts added to the skid buffer
+system.cpu0.rename.skidInsts 3595 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 153720 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 77689 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 74928 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 74758 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 402151 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 399521 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10786 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 9496 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqInstsIssued 399553 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10756 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 9264 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 192893 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.071205 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.088777 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::samples 192912 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.071167 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.088883 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 32269 16.73% 16.73% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 4844 2.51% 19.24% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 76822 39.83% 59.07% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 76327 39.57% 98.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1582 0.82% 99.46% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 687 0.36% 99.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 32280 16.73% 16.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 4842 2.51% 19.24% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 76824 39.82% 59.07% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 76328 39.57% 98.63% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1590 0.82% 99.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 686 0.36% 99.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 263 0.14% 99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 192893 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 192912 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 57 25.45% 25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 169105 42.33% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 153283 38.37% 80.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 77133 19.31% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 169105 42.32% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 153315 38.37% 80.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 77133 19.30% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 399521 # Type of FU issued
-system.cpu0.iq.rate 1.905548 # Inst issue rate
+system.cpu0.iq.FU_type_0::total 399553 # Type of FU issued
+system.cpu0.iq.rate 1.905664 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 224 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 992323 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 413903 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 397700 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.int_inst_queue_reads 992374 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 413873 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 397773 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 399745 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 399777 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 74515 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.predictedTakenIncorrect 327 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 1115 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 398429 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 152970 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1092 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecutedInsts 398478 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 152978 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1075 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 75469 # number of nop insts executed
-system.cpu0.iew.exec_refs 229968 # number of memory reference insts executed
+system.cpu0.iew.exec_refs 230010 # number of memory reference insts executed
system.cpu0.iew.exec_branches 79152 # Number of branches executed
-system.cpu0.iew.exec_stores 76998 # Number of stores executed
-system.cpu0.iew.exec_rate 1.900340 # Inst execution rate
-system.cpu0.iew.wb_sent 398024 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 397700 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 235727 # num instructions producing a value
-system.cpu0.iew.wb_consumers 238246 # num instructions consuming a value
+system.cpu0.iew.exec_stores 77032 # Number of stores executed
+system.cpu0.iew.exec_rate 1.900537 # Inst execution rate
+system.cpu0.iew.wb_sent 398087 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 397773 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 235728 # num instructions producing a value
+system.cpu0.iew.wb_consumers 238247 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 1.896863 # insts written-back per cycle
+system.cpu0.iew.wb_rate 1.897175 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.989427 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 190472 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 2.448360 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 2.135276 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::samples 190474 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 2.448334 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 2.135304 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 32802 17.22% 17.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 32805 17.22% 17.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 78740 41.34% 58.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2340 1.23% 59.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2339 1.23% 59.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 545 0.29% 60.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 74330 39.02% 99.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 74329 39.02% 99.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 456 0.24% 99.70% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 317 0.17% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 190472 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total 190474 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 466344 # Number of instructions committed
system.cpu0.commit.committedOps 466344 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.function_calls 223 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 317 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 667502 # The number of ROB reads
+system.cpu0.rob.rob_reads 667504 # The number of ROB reads
system.cpu0.rob.rob_writes 959472 # The number of ROB writes
system.cpu0.timesIdled 316 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 16769 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.idleCycles 16754 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts 391341 # Number of Instructions Simulated
system.cpu0.committedOps 391341 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 391341 # Number of Instructions Simulated
-system.cpu0.cpi 0.535753 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.535753 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.866533 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.866533 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 712669 # number of integer regfile reads
-system.cpu0.int_regfile_writes 321346 # number of integer regfile writes
+system.cpu0.cpi 0.535763 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.535763 # CPI: Total CPI of All Threads
+system.cpu0.ipc 1.866497 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.866497 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 712766 # number of integer regfile reads
+system.cpu0.int_regfile_writes 321389 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
-system.cpu0.misc_regfile_reads 231752 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 231850 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
system.cpu0.icache.replacements 297 # number of replacements
-system.cpu0.icache.tagsinuse 245.466325 # Cycle average of tags in use
+system.cpu0.icache.tagsinuse 245.463196 # Cycle average of tags in use
system.cpu0.icache.total_refs 5129 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 8.737649 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 245.466325 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.479426 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.479426 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::cpu0.inst 245.463196 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.479420 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.479420 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 5129 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 5129 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5129 # number of demand (read+write) hits
system.cpu0.icache.demand_misses::total 742 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 742 # number of overall misses
system.cpu0.icache.overall_misses::total 742 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25612000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 25612000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 25612000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 25612000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 25612000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 25612000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25596000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 25596000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 25596000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 25596000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 25596000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 25596000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5871 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 5871 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 5871 # number of demand (read+write) accesses
system.cpu0.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126384 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34517.520216 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 34517.520216 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 34517.520216 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 34517.520216 # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34495.956873 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 34495.956873 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 34495.956873 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 34495.956873 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20478500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 20478500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20478500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 20478500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20478500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 20478500 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20466000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 20466000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20466000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 20466000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20466000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 20466000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100153 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.100153 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.100153 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34827.380952 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 34827.380952 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 34827.380952 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34806.122449 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 2 # number of replacements
-system.cpu0.dcache.tagsinuse 143.868426 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 153554 # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse 143.865824 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 153562 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 903.258824 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 903.305882 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 143.868426 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.280993 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.280993 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 77923 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 77923 # number of ReadReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data 143.865824 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.280988 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.280988 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 77931 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 77931 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 75708 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 75708 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 153631 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 153631 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 153631 # number of overall hits
-system.cpu0.dcache.overall_hits::total 153631 # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data 153639 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 153639 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 153639 # number of overall hits
+system.cpu0.dcache.overall_hits::total 153639 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 471 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 471 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 550 # number of WriteReq misses
system.cpu0.dcache.overall_misses::total 1021 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11085500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 11085500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22991498 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 22991498 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23032998 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 23032998 # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390000 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total 390000 # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 34076998 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 34076998 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 34076998 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 34076998 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 78394 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 78394 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.demand_miss_latency::cpu0.data 34118498 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 34118498 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 34118498 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 34118498 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 78402 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 78402 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 76258 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 76258 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 154652 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 154652 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 154652 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 154652 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006008 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.006008 # miss rate for ReadReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data 154660 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 154660 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 154660 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 154660 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006007 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.006007 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007212 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.007212 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses
system.cpu0.dcache.overall_miss_rate::total 0.006602 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41802.723636 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 41802.723636 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41878.178182 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 41878.178182 # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19500 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 19500 # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33376.099902 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33376.099902 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33416.746327 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33416.746327 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4894000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5605500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5605500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5613000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5613000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 350000 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 350000 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 10499500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 10499500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002475 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002475 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10507000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 10507000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10507000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 10507000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002474 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002474 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002177 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002177 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002328 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33768.072289 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33768.072289 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33813.253012 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33813.253012 # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17500 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17500 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 174084 # number of cpu cycles simulated
+system.cpu1.numCycles 174086 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 52904 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 50238 # Number of conditional branches predicted
+system.cpu1.BPredUnit.lookups 52905 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 50239 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 1268 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 46828 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 46138 # Number of BTB hits
+system.cpu1.BPredUnit.BTBLookups 46829 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 46139 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS 659 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 297398 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 52904 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 46797 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 103835 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.Insts 297404 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 52905 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 46798 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 103837 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3694 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 29305 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.BlockedCycles 29303 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles 6116 # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.NoActiveThreadStallCycles 6120 # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles 727 # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines 18660 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 169680 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.752699 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.165176 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::samples 169684 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.752693 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.165174 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 65845 38.81% 38.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 52566 30.98% 69.78% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 65847 38.81% 38.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 52567 30.98% 69.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 5632 3.32% 73.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 3204 1.89% 74.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 655 0.39% 75.38% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 36566 21.55% 96.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 36567 21.55% 96.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1212 0.71% 97.64% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 766 0.45% 98.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 3234 1.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 169680 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.303899 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.708359 # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist::total 169684 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.303902 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.708374 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 31981 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 26240 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 98388 # Number of cycles decode is running
+system.cpu1.decode.BlockedCycles 26238 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 98390 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 4607 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 2348 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 293925 # Number of instructions handled by decode
+system.cpu1.decode.DecodedInsts 293931 # Number of instructions handled by decode
system.cpu1.rename.SquashCycles 2348 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 32683 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 13600 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 11858 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 94082 # Number of cycles rename is running
+system.cpu1.rename.serializeStallCycles 11856 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 94084 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 8993 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 291891 # Number of instructions processed by rename
+system.cpu1.rename.RenamedInsts 291897 # Number of instructions processed by rename
system.cpu1.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 205019 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 562522 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 562522 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 192184 # Number of HB maps that are committed
+system.cpu1.rename.RenamedOperands 205023 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 562534 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 562534 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 192188 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 12835 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1091 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1214 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 11554 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 83196 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 39822 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 39557 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 34785 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 242788 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.memDep0.insertedLoads 83198 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 39823 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 39558 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 34786 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 242793 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 5818 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 244431 # Number of instructions issued
+system.cpu1.iq.iqInstsIssued 244436 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 88 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10770 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedInstsExamined 10755 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 10381 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 573 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 169680 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.440541 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::samples 169684 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.440537 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.314007 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 63213 37.25% 37.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 63215 37.25% 37.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 21011 12.38% 49.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 39930 23.53% 73.17% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 40650 23.96% 97.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 39931 23.53% 73.17% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 40651 23.96% 97.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 3306 1.95% 99.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1205 0.71% 99.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 253 0.15% 99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 169680 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 169684 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 17 5.76% 5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 118248 48.38% 48.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 118250 48.38% 48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 87044 35.61% 83.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 39139 16.01% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 87046 35.61% 83.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 39140 16.01% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 244431 # Type of FU issued
-system.cpu1.iq.rate 1.404098 # Inst issue rate
+system.cpu1.iq.FU_type_0::total 244436 # Type of FU issued
+system.cpu1.iq.rate 1.404111 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 658925 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 259421 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 242675 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.int_inst_queue_reads 658939 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 259411 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 242683 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 244726 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 244731 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 34549 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 34550 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 2395 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 954 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 289058 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispatchedInsts 289064 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 83196 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 39822 # Number of dispatched store instructions
+system.cpu1.iew.iewDispLoadInsts 83198 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 39823 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 70 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 930 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 243269 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 82226 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1162 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewExecutedInsts 243277 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 82228 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1159 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 40452 # number of nop insts executed
-system.cpu1.iew.exec_refs 121286 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 49717 # Number of branches executed
-system.cpu1.iew.exec_stores 39060 # Number of stores executed
-system.cpu1.iew.exec_rate 1.397423 # Inst execution rate
-system.cpu1.iew.wb_sent 242942 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 242675 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 138073 # num instructions producing a value
-system.cpu1.iew.wb_consumers 142763 # num instructions consuming a value
+system.cpu1.iew.exec_nop 40453 # number of nop insts executed
+system.cpu1.iew.exec_refs 121292 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 49718 # Number of branches executed
+system.cpu1.iew.exec_stores 39064 # Number of stores executed
+system.cpu1.iew.exec_rate 1.397453 # Inst execution rate
+system.cpu1.iew.wb_sent 242950 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 242683 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 138076 # num instructions producing a value
+system.cpu1.iew.wb_consumers 142766 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.394011 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.967148 # average fanout of values written-back
+system.cpu1.iew.wb_rate 1.394041 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.967149 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 12362 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 5245 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 1268 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 161217 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.716302 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 2.045846 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::samples 161216 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.716349 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 2.045856 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 62248 38.61% 38.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 47764 29.63% 68.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 62245 38.61% 38.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 47765 29.63% 68.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6052 3.75% 71.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1571 0.97% 76.80% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 35062 21.75% 98.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 35063 21.75% 98.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 510 0.32% 98.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 1010 0.63% 99.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 821 0.51% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 161217 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 276697 # Number of instructions committed
-system.cpu1.commit.committedOps 276697 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 161216 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 276703 # Number of instructions committed
+system.cpu1.commit.committedOps 276703 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 119191 # Number of memory references committed
-system.cpu1.commit.loads 80801 # Number of loads committed
+system.cpu1.commit.refs 119194 # Number of memory references committed
+system.cpu1.commit.loads 80803 # Number of loads committed
system.cpu1.commit.membars 4532 # Number of memory barriers committed
-system.cpu1.commit.branches 48885 # Number of branches committed
+system.cpu1.commit.branches 48886 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 190199 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 190203 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 821 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 448868 # The number of ROB reads
-system.cpu1.rob.rob_writes 580470 # The number of ROB writes
+system.cpu1.rob.rob_reads 448873 # The number of ROB reads
+system.cpu1.rob.rob_writes 580482 # The number of ROB writes
system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 4404 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 35576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 232489 # Number of Instructions Simulated
-system.cpu1.committedOps 232489 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 232489 # Number of Instructions Simulated
-system.cpu1.cpi 0.748784 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.748784 # CPI: Total CPI of All Threads
-system.cpu1.ipc 1.335499 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.335499 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 422509 # number of integer regfile reads
-system.cpu1.int_regfile_writes 197149 # number of integer regfile writes
+system.cpu1.idleCycles 4402 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 35578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 232494 # Number of Instructions Simulated
+system.cpu1.committedOps 232494 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 232494 # Number of Instructions Simulated
+system.cpu1.cpi 0.748776 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.748776 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.335512 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.335512 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 422524 # number of integer regfile reads
+system.cpu1.int_regfile_writes 197153 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 122869 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 122878 # number of misc regfile reads
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.icache.replacements 317 # number of replacements
-system.cpu1.icache.tagsinuse 85.783317 # Cycle average of tags in use
+system.cpu1.icache.tagsinuse 85.782711 # Cycle average of tags in use
system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 42.771765 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 85.783317 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.167546 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.167546 # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::cpu1.inst 85.782711 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.167544 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.167544 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 18178 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 18178 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 18178 # number of demand (read+write) hits
system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses
system.cpu1.icache.overall_misses::total 482 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9898500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 9898500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 9898500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 9898500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 9898500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 9898500 # number of overall miss cycles
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9897000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 9897000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 9897000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 9897000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 9897000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 9897000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 18660 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 18660 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 18660 # number of demand (read+write) accesses
system.cpu1.icache.demand_miss_rate::total 0.025831 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025831 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.025831 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20536.307054 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 20536.307054 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 20536.307054 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 20536.307054 # average overall miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20533.195021 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 20533.195021 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 20533.195021 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 20533.195021 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8055000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 8055000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8055000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 8055000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8055000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 8055000 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8054000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 8054000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8054000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 8054000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8054000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 8054000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022776 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.022776 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.022776 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18952.941176 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18950.588235 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 0 # number of replacements
-system.cpu1.dcache.tagsinuse 27.224773 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 44406 # Total number of references to valid blocks.
+system.cpu1.dcache.tagsinuse 27.224520 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 44407 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 1585.928571 # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs 1585.964286 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 27.224773 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_blocks::cpu1.data 27.224520 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.053173 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.053173 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 47254 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 47254 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 38186 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 38186 # number of WriteReq hits
+system.cpu1.dcache.ReadReq_hits::cpu1.data 47255 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 47255 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 38187 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 38187 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 85440 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 85440 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 85440 # number of overall hits
-system.cpu1.dcache.overall_hits::total 85440 # number of overall hits
+system.cpu1.dcache.demand_hits::cpu1.data 85442 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 85442 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 85442 # number of overall hits
+system.cpu1.dcache.overall_hits::total 85442 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 407 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 407 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses
system.cpu1.dcache.overall_misses::total 544 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6159500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 6159500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2649500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 2649500 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2641000 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 2641000 # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 528500 # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total 528500 # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 8809000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 8809000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 8809000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 8809000 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 47661 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 47661 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 38323 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 38323 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.demand_miss_latency::cpu1.data 8800500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 8800500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 8800500 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 8800500 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 47662 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 47662 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 38324 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 38324 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 85984 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 85984 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 85984 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 85984 # number of overall (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data 85986 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 85986 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 85986 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 85986 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008539 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.008539 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003575 # miss rate for WriteReq accesses
system.cpu1.dcache.overall_miss_rate::total 0.006327 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15133.906634 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15133.906634 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19339.416058 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 19339.416058 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19277.372263 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 19277.372263 # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9971.698113 # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 9971.698113 # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16193.014706 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16193.014706 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16177.389706 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 16177.389706 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16177.389706 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16177.389706 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1383500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1383500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1381000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1381000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 422500 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 422500 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2913500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 2913500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2913500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 2913500 # number of overall MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2911000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2911000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2911000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2911000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003252 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003252 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002740 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.003024 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9870.967742 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9870.967742 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13176.190476 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13176.190476 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13152.380952 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13152.380952 # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7971.698113 # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7971.698113 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.numCycles 173759 # number of cpu cycles simulated
+system.cpu2.numCycles 173761 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.BPredUnit.lookups 43658 # Number of BP lookups
system.cpu2.fetch.predictedBranches 37372 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 88227 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 3786 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 41179 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.BlockedCycles 41181 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles 6107 # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.NoActiveThreadStallCycles 6111 # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles 690 # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines 25041 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 172022 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.367924 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.005612 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::samples 172028 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.367876 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.005593 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 83795 48.71% 48.71% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 83801 48.71% 48.71% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 46271 26.90% 75.61% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 8744 5.08% 80.69% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 3171 1.84% 82.54% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 172022 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.251256 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.354249 # Number of inst fetches per cycle
+system.cpu2.fetch.rateDist::total 172028 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.251253 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.354234 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 40935 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 35177 # Number of cycles decode is blocked
+system.cpu2.decode.BlockedCycles 35179 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 79843 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 7534 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 2426 # Number of cycles decode is squashing
system.cpu2.rename.SquashCycles 2426 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 41648 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 22387 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 11999 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.serializeStallCycles 12001 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 72579 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 14876 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 229374 # Number of instructions processed by rename
system.cpu2.iq.iqNonSpecInstsAdded 8963 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 190992 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 11074 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 10969 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedInstsExamined 11059 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 10957 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 172022 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.110277 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.273783 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::samples 172028 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.110238 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.273778 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 81441 47.34% 47.34% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 81447 47.35% 47.35% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 30126 17.51% 64.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 27409 15.93% 80.79% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 28202 16.39% 97.18% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 172022 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 172028 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 190992 # Type of FU issued
-system.cpu2.iq.rate 1.099178 # Inst issue rate
+system.cpu2.iq.rate 1.099165 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 287 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.001503 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 554402 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 206628 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 189208 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.int_inst_queue_reads 554408 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 206613 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 189211 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 1394 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 189816 # Number of executed instructions
+system.cpu2.iew.iewExecutedInsts 189819 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 60231 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewExecSquashedInsts 1173 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 31084 # number of nop insts executed
-system.cpu2.iew.exec_refs 86812 # number of memory reference insts executed
+system.cpu2.iew.exec_refs 86815 # number of memory reference insts executed
system.cpu2.iew.exec_branches 40244 # Number of branches executed
-system.cpu2.iew.exec_stores 26581 # Number of stores executed
-system.cpu2.iew.exec_rate 1.092410 # Inst execution rate
-system.cpu2.iew.wb_sent 189478 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 189208 # cumulative count of insts written-back
+system.cpu2.iew.exec_stores 26584 # Number of stores executed
+system.cpu2.iew.exec_rate 1.092414 # Inst execution rate
+system.cpu2.iew.wb_sent 189481 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 189211 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 103581 # num instructions producing a value
system.cpu2.iew.wb_consumers 108246 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.088911 # insts written-back per cycle
+system.cpu2.iew.wb_rate 1.088915 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.956904 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 12701 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 8313 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 1282 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 163490 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.308153 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.875243 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::samples 163491 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.308145 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.875240 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 83402 51.01% 51.01% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 83403 51.01% 51.01% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 38322 23.44% 74.45% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 6091 3.73% 78.18% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 9201 5.63% 83.81% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 163490 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::total 163491 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 213870 # Number of instructions committed
system.cpu2.commit.committedOps 213870 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.function_calls 322 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 388659 # The number of ROB reads
+system.cpu2.rob.rob_reads 388660 # The number of ROB reads
system.cpu2.rob.rob_writes 455572 # The number of ROB writes
system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1737 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 35901 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.idleCycles 1733 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 35903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 176057 # Number of Instructions Simulated
system.cpu2.committedOps 176057 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 176057 # Number of Instructions Simulated
-system.cpu2.cpi 0.986947 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.986947 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.013225 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.013225 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 319017 # number of integer regfile reads
+system.cpu2.cpi 0.986959 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.986959 # CPI: Total CPI of All Threads
+system.cpu2.ipc 1.013214 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.013214 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 319023 # number of integer regfile reads
system.cpu2.int_regfile_writes 150022 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 88362 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 88368 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
system.cpu2.icache.replacements 319 # number of replacements
-system.cpu2.icache.tagsinuse 80.119670 # Cycle average of tags in use
+system.cpu2.icache.tagsinuse 80.119801 # Cycle average of tags in use
system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 57.263403 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst 80.119670 # Average occupied blocks per requestor
+system.cpu2.icache.occ_blocks::cpu2.inst 80.119801 # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst 0.156484 # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total 0.156484 # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst 24566 # number of ReadReq hits
system.cpu2.icache.demand_misses::total 475 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 475 # number of overall misses
system.cpu2.icache.overall_misses::total 475 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6356500 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 6356500 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 6356500 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total 6356500 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst 6356500 # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total 6356500 # number of overall miss cycles
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6355000 # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total 6355000 # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst 6355000 # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total 6355000 # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst 6355000 # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total 6355000 # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst 25041 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 25041 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 25041 # number of demand (read+write) accesses
system.cpu2.icache.demand_miss_rate::total 0.018969 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018969 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.018969 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13382.105263 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 13382.105263 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 13382.105263 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 13382.105263 # average overall miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13378.947368 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 13378.947368 # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 13378.947368 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 13378.947368 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst 429 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total 429 # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5130000 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5130000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total 5130000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5130000 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total 5130000 # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5129000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total 5129000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5129000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total 5129000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5129000 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total 5129000 # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017132 # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total 0.017132 # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total 0.017132 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11958.041958 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 11958.041958 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 11958.041958 # average overall mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11955.710956 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 0 # number of replacements
-system.cpu2.dcache.tagsinuse 24.750979 # Cycle average of tags in use
+system.cpu2.dcache.tagsinuse 24.751060 # Cycle average of tags in use
system.cpu2.dcache.total_refs 32016 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 1104 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::cpu2.data 24.750979 # Average occupied blocks per requestor
+system.cpu2.dcache.occ_blocks::cpu2.data 24.751060 # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data 0.048342 # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total 0.048342 # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data 37788 # number of ReadReq hits
system.cpu2.dcache.demand_misses::total 530 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 530 # number of overall misses
system.cpu2.dcache.overall_misses::total 530 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5135500 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 5135500 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2343500 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 2343500 # number of WriteReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5134500 # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total 5134500 # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2352000 # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total 2352000 # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 565000 # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total 565000 # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 7479000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 7479000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data 7479000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total 7479000 # number of overall miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data 7486500 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total 7486500 # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data 7486500 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total 7486500 # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data 38185 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 38185 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 25814 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.demand_miss_rate::total 0.008281 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008281 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.008281 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12935.768262 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 12935.768262 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17620.300752 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 17620.300752 # average WriteReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12933.249370 # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 12933.249370 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17684.210526 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 17684.210526 # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9576.271186 # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 9576.271186 # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 14111.320755 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 14111.320755 # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 14125.471698 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 14125.471698 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1409000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1409000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1142500 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1142500 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1408000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1408000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1144000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1144000 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 447000 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 447000 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2551500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 2551500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2551500 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 2551500 # number of overall MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2552000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 2552000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2552000 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 2552000 # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004452 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004452 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003913 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::total 0.004234 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total 0.004234 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8288.235294 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8288.235294 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11311.881188 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11311.881188 # average WriteReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8282.352941 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8282.352941 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11326.732673 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11326.732673 # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7576.271186 # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7576.271186 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.numCycles 173449 # number of cpu cycles simulated
+system.cpu3.numCycles 173451 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.BPredUnit.lookups 53688 # Number of BP lookups
-system.cpu3.BPredUnit.condPredicted 50962 # Number of conditional branches predicted
+system.cpu3.BPredUnit.lookups 53689 # Number of BP lookups
+system.cpu3.BPredUnit.condPredicted 50963 # Number of conditional branches predicted
system.cpu3.BPredUnit.condIncorrect 1276 # Number of conditional branches incorrect
-system.cpu3.BPredUnit.BTBLookups 47521 # Number of BTB lookups
-system.cpu3.BPredUnit.BTBHits 46771 # Number of BTB hits
+system.cpu3.BPredUnit.BTBLookups 47522 # Number of BTB lookups
+system.cpu3.BPredUnit.BTBHits 46772 # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.usedRAS 661 # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 301358 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 53688 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 47432 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 105431 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.Insts 301364 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 53689 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 47433 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 105433 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 3739 # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles 29902 # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles 6125 # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.NoActiveThreadStallCycles 6129 # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines 19205 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 172027 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.751806 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.162661 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::samples 172033 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.751780 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.162655 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 66596 38.71% 38.71% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 53420 31.05% 69.77% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 66600 38.71% 38.71% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 53421 31.05% 69.77% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 5840 3.39% 73.16% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 3208 1.86% 75.03% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 724 0.42% 75.45% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 37059 21.54% 96.99% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 37060 21.54% 96.99% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 1114 0.65% 97.64% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 769 0.45% 98.08% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 3297 1.92% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 172027 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.309532 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 1.737444 # Number of inst fetches per cycle
+system.cpu3.fetch.rateDist::total 172033 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.309534 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.737459 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 32330 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 26595 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 99738 # Number of cycles decode is running
+system.cpu3.decode.RunCycles 99740 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 4852 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 2387 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 297869 # Number of instructions handled by decode
+system.cpu3.decode.DecodedInsts 297875 # Number of instructions handled by decode
system.cpu3.rename.SquashCycles 2387 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 33042 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 14161 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 11648 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 95158 # Number of cycles rename is running
+system.cpu3.rename.RunCycles 95160 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 9506 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 295495 # Number of instructions processed by rename
+system.cpu3.rename.RenamedInsts 295501 # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents 42 # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands 206972 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 568769 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 568769 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 194051 # Number of HB maps that are committed
+system.cpu3.rename.RenamedOperands 206976 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 568781 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 568781 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 194055 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 1213 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 12164 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 84321 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 40263 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 40233 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 35230 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 245462 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.memDep0.insertedLoads 84323 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 40264 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 40234 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 35231 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 245467 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 6061 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 247263 # Number of instructions issued
+system.cpu3.iq.iqInstsIssued 247268 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 10948 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 10583 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedInstsExamined 10933 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 10571 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 569 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 172027 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.437350 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.311410 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::samples 172033 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.437329 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.311411 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 63993 37.20% 37.20% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 63997 37.20% 37.20% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 21775 12.66% 49.86% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 40281 23.42% 73.27% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 41063 23.87% 97.14% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 40282 23.42% 73.27% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 41064 23.87% 97.14% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 3352 1.95% 99.09% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 1207 0.70% 99.79% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 253 0.15% 99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 172027 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 172033 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 119304 48.25% 48.25% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 119306 48.25% 48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.25% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 88373 35.74% 83.99% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 39586 16.01% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 88375 35.74% 83.99% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 39587 16.01% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 247263 # Type of FU issued
-system.cpu3.iq.rate 1.425566 # Inst issue rate
+system.cpu3.iq.FU_type_0::total 247268 # Type of FU issued
+system.cpu3.iq.rate 1.425578 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 287 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.001161 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 666924 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 262516 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 245480 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.int_inst_queue_reads 666940 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 262506 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 245488 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 247550 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 247555 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 34961 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 34962 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads 2463 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 786 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 292666 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispatchedInsts 292672 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 339 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 84321 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 40263 # Number of dispatched store instructions
+system.cpu3.iew.iewDispLoadInsts 84323 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 40264 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 246084 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 83306 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1179 # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewExecutedInsts 246092 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 83308 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 41143 # number of nop insts executed
-system.cpu3.iew.exec_refs 122808 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 50377 # Number of branches executed
-system.cpu3.iew.exec_stores 39502 # Number of stores executed
-system.cpu3.iew.exec_rate 1.418769 # Inst execution rate
-system.cpu3.iew.wb_sent 245746 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 245480 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 139608 # num instructions producing a value
-system.cpu3.iew.wb_consumers 144273 # num instructions consuming a value
+system.cpu3.iew.exec_nop 41144 # number of nop insts executed
+system.cpu3.iew.exec_refs 122814 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 50378 # Number of branches executed
+system.cpu3.iew.exec_stores 39506 # Number of stores executed
+system.cpu3.iew.exec_rate 1.418798 # Inst execution rate
+system.cpu3.iew.wb_sent 245754 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 245488 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 139611 # num instructions producing a value
+system.cpu3.iew.wb_consumers 144276 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.415286 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.967665 # average fanout of values written-back
+system.cpu3.iew.wb_rate 1.415316 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.967666 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts 12526 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 5492 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 1276 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 163516 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.713105 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 2.043722 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::samples 163517 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 1.713131 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 2.043728 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 63247 38.68% 38.68% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 48404 29.60% 68.28% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 63246 38.68% 38.68% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 48405 29.60% 68.28% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 6092 3.73% 72.01% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 6399 3.91% 75.92% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 1556 0.95% 76.87% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 35437 21.67% 98.54% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 35438 21.67% 98.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 553 0.34% 98.88% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 1016 0.62% 99.50% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 163516 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 280120 # Number of instructions committed
-system.cpu3.commit.committedOps 280120 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 163517 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 280126 # Number of instructions committed
+system.cpu3.commit.committedOps 280126 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 120652 # Number of memory references committed
-system.cpu3.commit.loads 81858 # Number of loads committed
+system.cpu3.commit.refs 120655 # Number of memory references committed
+system.cpu3.commit.loads 81860 # Number of loads committed
system.cpu3.commit.membars 4779 # Number of memory barriers committed
-system.cpu3.commit.branches 49540 # Number of branches committed
+system.cpu3.commit.branches 49541 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 192312 # Number of committed integer instructions.
+system.cpu3.commit.int_insts 192316 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads 454763 # The number of ROB reads
-system.cpu3.rob.rob_writes 587684 # The number of ROB writes
+system.cpu3.rob.rob_reads 454770 # The number of ROB reads
+system.cpu3.rob.rob_writes 587696 # The number of ROB writes
system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 1422 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 36211 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 235010 # Number of Instructions Simulated
-system.cpu3.committedOps 235010 # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total 235010 # Number of Instructions Simulated
-system.cpu3.cpi 0.738049 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.738049 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.354923 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.354923 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 427031 # number of integer regfile reads
-system.cpu3.int_regfile_writes 198982 # number of integer regfile writes
+system.cpu3.idleCycles 1418 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 36213 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 235015 # Number of Instructions Simulated
+system.cpu3.committedOps 235015 # Number of Ops (including micro ops) Simulated
+system.cpu3.committedInsts_total 235015 # Number of Instructions Simulated
+system.cpu3.cpi 0.738042 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 0.738042 # CPI: Total CPI of All Threads
+system.cpu3.ipc 1.354936 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 1.354936 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 427046 # number of integer regfile reads
+system.cpu3.int_regfile_writes 198986 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu3.misc_regfile_reads 124365 # number of misc regfile reads
+system.cpu3.misc_regfile_reads 124374 # number of misc regfile reads
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
system.cpu3.icache.replacements 318 # number of replacements
-system.cpu3.icache.tagsinuse 83.493816 # Cycle average of tags in use
+system.cpu3.icache.tagsinuse 83.494084 # Cycle average of tags in use
system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 428 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 43.764019 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst 83.493816 # Average occupied blocks per requestor
+system.cpu3.icache.occ_blocks::cpu3.inst 83.494084 # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst 0.163074 # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst 18731 # number of ReadReq hits
system.cpu3.icache.demand_misses::total 474 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 474 # number of overall misses
system.cpu3.icache.overall_misses::total 474 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6191000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total 6191000 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst 6191000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total 6191000 # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst 6191000 # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total 6191000 # number of overall miss cycles
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6189500 # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total 6189500 # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst 6189500 # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total 6189500 # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst 6189500 # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total 6189500 # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst 19205 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 19205 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 19205 # number of demand (read+write) accesses
system.cpu3.icache.demand_miss_rate::total 0.024681 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024681 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.024681 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13061.181435 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13061.181435 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 13061.181435 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13061.181435 # average overall miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13058.016878 # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 13058.016878 # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 13058.016878 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 13058.016878 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 428 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total 428 # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4970500 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total 4970500 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4970500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total 4970500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4970500 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total 4970500 # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4969500 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total 4969500 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4969500 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total 4969500 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4969500 # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total 4969500 # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022286 # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total 0.022286 # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total 0.022286 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11613.317757 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 11613.317757 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 11613.317757 # average overall mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11610.981308 # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 11610.981308 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 11610.981308 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 0 # number of replacements
-system.cpu3.dcache.tagsinuse 25.854093 # Cycle average of tags in use
-system.cpu3.dcache.total_refs 44811 # Total number of references to valid blocks.
+system.cpu3.dcache.tagsinuse 25.854191 # Cycle average of tags in use
+system.cpu3.dcache.total_refs 44812 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks.
-system.cpu3.dcache.avg_refs 1600.392857 # Average number of references to valid blocks.
+system.cpu3.dcache.avg_refs 1600.428571 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data 25.854093 # Average occupied blocks per requestor
+system.cpu3.dcache.occ_blocks::cpu3.data 25.854191 # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data 0.050496 # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total 0.050496 # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data 47901 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 47901 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 38585 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 38585 # number of WriteReq hits
+system.cpu3.dcache.ReadReq_hits::cpu3.data 47902 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total 47902 # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data 38586 # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total 38586 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 86486 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 86486 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 86486 # number of overall hits
-system.cpu3.dcache.overall_hits::total 86486 # number of overall hits
+system.cpu3.dcache.demand_hits::cpu3.data 86488 # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total 86488 # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data 86488 # number of overall hits
+system.cpu3.dcache.overall_hits::total 86488 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 426 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 426 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 142 # number of WriteReq misses
system.cpu3.dcache.demand_misses::total 568 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 568 # number of overall misses
system.cpu3.dcache.overall_misses::total 568 # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5342000 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total 5342000 # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2332500 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total 2332500 # number of WriteReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5341000 # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total 5341000 # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2325000 # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total 2325000 # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 555000 # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total 555000 # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data 7674500 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total 7674500 # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data 7674500 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total 7674500 # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 48327 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 48327 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 38727 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 38727 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.demand_miss_latency::cpu3.data 7666000 # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total 7666000 # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data 7666000 # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total 7666000 # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data 48328 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total 48328 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data 38728 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total 38728 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 87054 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 87054 # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data 87054 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total 87054 # number of overall (read+write) accesses
+system.cpu3.dcache.demand_accesses::cpu3.data 87056 # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total 87056 # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data 87056 # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total 87056 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008815 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.008815 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003667 # miss rate for WriteReq accesses
system.cpu3.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006525 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12539.906103 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 12539.906103 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16426.056338 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 16426.056338 # average WriteReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12537.558685 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 12537.558685 # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16373.239437 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 16373.239437 # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9910.714286 # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 9910.714286 # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 13511.443662 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 13511.443662 # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13496.478873 # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 13496.478873 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13496.478873 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 13496.478873 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1265000 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1265000 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1159500 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1159500 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1264000 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1264000 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1158000 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1158000 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 443000 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 443000 # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2424500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total 2424500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2424500 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total 2424500 # number of overall MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2422000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total 2422000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2422000 # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total 2422000 # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003166 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002815 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::total 0.003010 # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total 0.003010 # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8267.973856 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8267.973856 # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10637.614679 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10637.614679 # average WriteReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8261.437908 # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8261.437908 # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10623.853211 # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10623.853211 # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7910.714286 # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7910.714286 # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9253.816794 # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9253.816794 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9253.816794 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9253.816794 # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
-system.l2c.tagsinuse 425.296596 # Cycle average of tags in use
+system.l2c.tagsinuse 425.291959 # Cycle average of tags in use
system.l2c.total_refs 1448 # Total number of references to valid blocks.
system.l2c.sampled_refs 525 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.758095 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 0.828895 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 289.891501 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 59.268437 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 63.508816 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 5.639642 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst 2.310248 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data 0.728233 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst 2.354110 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data 0.766714 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 0.828889 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 289.887816 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 59.267955 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 63.508377 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 5.639601 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst 2.310233 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data 0.728238 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst 2.354132 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data 0.766718 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.000904 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst 0.000036 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.006490 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.006489 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits
system.l2c.overall_misses::cpu3.inst 4 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 668 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 17565000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 17552500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 4069000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 4146500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 4145500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 381000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 396000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 395000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst 233000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst 232000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 26927500 # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 5000500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 881000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 699500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data 661500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7242500 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 17565000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 9069500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 4146500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 1262000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 396000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 768000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst 233000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data 730000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 34170000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 17565000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 9069500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 4146500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 1262000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 396000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 768000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst 233000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data 730000 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 34170000 # number of overall miss cycles
+system.l2c.ReadReq_miss_latency::total 26912000 # number of ReadReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 5008000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 878500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 701000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data 660000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 7247500 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 17552500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 9077000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 4145500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 1259500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 395000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 769500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst 232000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data 728500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 34159500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 17552500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 9077000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 4145500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 1259500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 395000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 769500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst 232000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data 728500 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 34159500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses)
system.l2c.overall_miss_rate::cpu3.inst 0.009346 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.315690 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48927.576602 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48892.757660 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 54986.486486 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49957.831325 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49945.783133 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 54428.571429 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49500 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49375 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 68500 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 58250 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.inst 58000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data 68500 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 50144.320298 # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53196.808511 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67769.230769 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58291.666667 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 55125 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 55286.259542 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 48927.576602 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 53985.119048 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 49957.831325 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 63100 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 49500 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 59076.923077 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 58250 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 56153.846154 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 51152.694611 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 48927.576602 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 53985.119048 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 49957.831325 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 63100 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 49500 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 59076.923077 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 58250 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 56153.846154 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 51152.694611 # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::total 50115.456238 # average ReadReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53276.595745 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67576.923077 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58416.666667 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 55000 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 55324.427481 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 48892.757660 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 54029.761905 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 49945.783133 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 62975 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 49375 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 59192.307692 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 58000 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 56038.461538 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 51136.976048 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 48892.757660 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 54029.761905 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 49945.783133 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 62975 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 49375 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 59192.307692 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 58000 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 56038.461538 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 51136.976048 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 659 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13017059 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13005059 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3150576 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3026126 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 293010 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 103002 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56002 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 181507 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 180507 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56002 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 19883284 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 19870284 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 193013 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 181515 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 153009 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200519 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 728056 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3829610 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 719513 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 549018 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 511018 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5609159 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 13017059 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 6980186 # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3834610 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 717513 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 550018 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 510018 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5612159 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 13005059 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 6985186 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 3026126 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 1012523 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 1010523 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 103002 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 605020 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst 181507 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data 567020 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 25492443 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 13017059 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 6980186 # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 606020 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst 180507 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data 566020 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 25482443 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 13005059 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 6985186 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 3026126 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 1012523 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 1010523 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 103002 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 605020 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst 181507 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data 567020 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 25492443 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 606020 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst 180507 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data 566020 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 25482443 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for ReadReq accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.311437 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42575.351351 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41858.571429 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 34334 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56002 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56002 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 37657.734848 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 37633.113636 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.578947 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10084.166667 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10200.600000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10025.950000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.888889 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40740.531915 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55347.153846 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45751.500000 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42584.833333 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 42818.007634 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41548.726190 # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40793.723404 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55193.307692 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45834.833333 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42501.500000 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 42840.908397 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41578.488095 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50626.150000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50526.150000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46540 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41548.726190 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46616.923077 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43540 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 38668.350531 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41578.488095 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50626.150000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50526.150000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46540 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46616.923077 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43540 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 38668.350531 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff