for GTU/LEU in Thumb mode. */
if (mode == DImode)
{
- rtx tem;
if (*code == GT || *code == LE
|| (!TARGET_ARM && (*code == GTU || *code == LEU)))
/* If that did not work, reverse the condition. */
if (!op0_preserve_value)
{
- tem = *op0;
- *op0 = *op1;
- *op1 = tem;
+ std::swap (*op0, *op1);
*code = (int)swap_condition ((enum rtx_code)*code);
}
}
return CCmode;
if (swapped)
- {
- enum rtx_code temp = cond1;
- cond1 = cond2;
- cond2 = temp;
- }
+ std::swap (cond1, cond2);
switch (cond1)
{
/* Updating base_plus might destroy outval, see if we can
swap the scratch and base_plus. */
if (!reg_overlap_mentioned_p (scratch, outval))
- {
- rtx tmp = scratch;
- scratch = base_plus;
- base_plus = tmp;
- }
+ std::swap (scratch, base_plus);
else
{
rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
/* Updating base_plus might destroy outval, see if we
can swap the scratch and base_plus. */
if (!reg_overlap_mentioned_p (scratch, outval))
- {
- rtx tmp = scratch;
- scratch = base_plus;
- base_plus = tmp;
- }
+ std::swap (scratch, base_plus);
else
{
rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
return false;
}
-#define SWAP_RTX(x,y) do { rtx tmp = x; x = y; y = tmp; } while (0)
-
/* Called from a peephole2 to replace two word-size accesses with a
single LDRD/STRD instruction. Returns true iff we can generate a
new instruction sequence. That is, both accesses use the same base
offset = offsets[1];
/* Swap the instructions such that lower memory is accessed first. */
- SWAP_RTX (operands[0], operands[1]);
- SWAP_RTX (operands[2], operands[3]);
+ std::swap (operands[0], operands[1]);
+ std::swap (operands[2], operands[3]);
if (const_store)
- SWAP_RTX (operands[4], operands[5]);
+ std::swap (operands[4], operands[5]);
}
else
{
if (load && commute)
{
/* Try reordering registers. */
- SWAP_RTX (operands[0], operands[1]);
+ std::swap (operands[0], operands[1]);
if (operands_ok_ldrd_strd (operands[0], operands[1], base, offset,
false, load))
return true;
if (operands_ok_ldrd_strd (operands[1], operands[0], base, offset,
false, false))
{
- SWAP_RTX (operands[0], operands[1]);
+ std::swap (operands[0], operands[1]);
return true;
}
return false;
}
-#undef SWAP_RTX
if (reg_overlap_mentioned_p (operands[0],
otherops[2]))
{
- rtx tmp;
/* Swap base and index registers over to
avoid a conflict. */
- tmp = otherops[1];
- otherops[1] = otherops[2];
- otherops[2] = tmp;
+ std::swap (otherops[1], otherops[2]);
}
/* If both registers conflict, it will usually
have been fixed by a splitter. */
/* Ensure that BASE is a register. */
/* (one of them must be). */
/* Also ensure the SP is not used as in index register. */
- rtx temp = base;
- base = index;
- index = temp;
+ std::swap (base, index);
}
switch (GET_CODE (index))
{
case 3:
if (REGNO (operands[4]) > REGNO (operands[5]))
- {
- tmp = operands[4];
- operands[4] = operands[5];
- operands[5] = tmp;
- }
+ std::swap (operands[4], operands[5]);
if (REGNO (operands[5]) > REGNO (operands[6]))
- {
- tmp = operands[5];
- operands[5] = operands[6];
- operands[6] = tmp;
- }
+ std::swap (operands[5], operands[6]);
if (REGNO (operands[4]) > REGNO (operands[5]))
- {
- tmp = operands[4];
- operands[4] = operands[5];
- operands[5] = tmp;
- }
+ std::swap (operands[4], operands[5]);
output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
swap the order in which the loads are emitted. */
if (reg_overlap_mentioned_p (operands[0], operands[1]))
{
- rtx tmp = operands[1];
- operands[1] = operands[3];
- operands[3] = tmp;
- tmp = operands[0];
- operands[0] = operands[2];
- operands[2] = tmp;
+ std::swap (operands[1], operands[3]);
+ std::swap (operands[0], operands[2]);
}
}
[(set_attr "arch" "t2,any")
gcc_assert (!(mode == CCFPmode || mode == CCFPEmode));
if (REGNO (operands[2]) != REGNO (operands[0]))
rc = reverse_condition (rc);
- else
- {
- rtx tmp = operands[1];
- operands[1] = operands[2];
- operands[2] = tmp;
- }
+ else
+ std::swap (operands[1], operands[2]);
operands[6] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx);
}