aarch64: Re-implement vabal_high* intrinsics using builtins

This patch reimplements the vabal_high* intrinsics using RTL builtins.
It's straightforward, defining new unspecs and a new pattern.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd-builtins.def (sabal2): Define
	builtin.
	(uabal2): Likewise.
	* config/aarch64/aarch64-simd.md (aarch64_<sur>abal2<mode>): New
	pattern.
	* config/aarch64/aarch64.md (unspec): Add UNSPEC_SABAL2 and
	UNSPEC_UABAL2.
	* config/aarch64/arm_neon.h (vabal_high_s8): Reimplement using
	builtin.
	(vabal_high_s16): Likewise.
	(vabal_high_s32): Likewise.
	(vabal_high_u8): Likewise.
	(vabal_high_u16): Likewise.
	(vabal_high_u32): Likewise.
	* config/aarch64/iterators.md (ABAL2): New mode iterator.
	(sur): Handle UNSPEC_SABAL2, UNSPEC_UABAL2.

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 48936077bda032e434b20d661b817b122f9938eb..f3aace3857749ad0e621ff2dea370bd481c2ea28 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -168,6 +168,10 @@
   BUILTIN_VD_BHSI (TERNOP, sabal, 0, NONE)
   BUILTIN_VD_BHSI (TERNOPU, uabal, 0, NONE)
 
+  /* Implemented by aarch64_<sur>abal2<mode>.  */
+  BUILTIN_VQW (TERNOP, sabal2, 0, NONE)
+  BUILTIN_VQW (TERNOPU, uabal2, 0, NONE)
+
   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
   BUILTIN_VQN (BINOP, addhn, 0, NONE)
   BUILTIN_VQN (BINOP, subhn, 0, NONE)

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 9390eb2da24ab4ec44c5c570ca8fdb7ef0fdaa0c..98d510b6eb684244a56d569531595d8d3ec2ffb4 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -839,6 +839,17 @@
   [(set_attr "type" "neon_arith_acc<q>")]
 )
 
+(define_insn "aarch64_<sur>abal2<mode>"
+  [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+       (unspec:<VWIDE> [(match_operand:VQW 2 "register_operand" "w")
+                         (match_operand:VQW 3 "register_operand" "w")
+                        (match_operand:<VWIDE> 1 "register_operand" "0")]
+       ABAL2))]
+  "TARGET_SIMD"
+  "<sur>abal2\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>"
+  [(set_attr "type" "neon_arith_acc<q>")]
+)
+
 (define_insn "aarch64_<sur>adalp<mode>"
   [(set (match_operand:<VDBLW> 0 "register_operand" "=w")
        (unspec:<VDBLW> [(match_operand:VDQV_S 2 "register_operand" "w")

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index e5990765b270b692965f67f2b7390a4470c21bd1..16753c0d932bdf29d0f272ff6452eae2d5394663 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -197,6 +197,7 @@
     UNSPEC_REV
     UNSPEC_RBIT
     UNSPEC_SABAL
+    UNSPEC_SABAL2
     UNSPEC_SABDL2
     UNSPEC_SADALP
     UNSPEC_SCVTF
@@ -218,6 +219,7 @@
     UNSPEC_TLSLE32
     UNSPEC_TLSLE48
     UNSPEC_UABAL
+    UNSPEC_UABAL2
     UNSPEC_UABDL2
     UNSPEC_UADALP
     UNSPEC_UCVTF

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 8d5e0f409259cd17817dffaebee28ca9f62b1be9..66feec3cce0c60a471fc8133afe83b2e2717ebb8 100644 (file)
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -6663,72 +6663,42 @@ __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vabal_high_s8 (int16x8_t __a, int8x16_t __b, int8x16_t __c)
 {
-  int16x8_t __result;
-  __asm__ ("sabal2 %0.8h,%2.16b,%3.16b"
-           : "=w"(__result)
-           : "0"(__a), "w"(__b), "w"(__c)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sabal2v16qi (__a, __b, __c);
 }
 
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vabal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
 {
-  int32x4_t __result;
-  __asm__ ("sabal2 %0.4s,%2.8h,%3.8h"
-           : "=w"(__result)
-           : "0"(__a), "w"(__b), "w"(__c)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sabal2v8hi (__a, __b, __c);
 }
 
 __extension__ extern __inline int64x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vabal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
 {
-  int64x2_t __result;
-  __asm__ ("sabal2 %0.2d,%2.4s,%3.4s"
-           : "=w"(__result)
-           : "0"(__a), "w"(__b), "w"(__c)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sabal2v4si (__a, __b, __c);
 }
 
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vabal_high_u8 (uint16x8_t __a, uint8x16_t __b, uint8x16_t __c)
 {
-  uint16x8_t __result;
-  __asm__ ("uabal2 %0.8h,%2.16b,%3.16b"
-           : "=w"(__result)
-           : "0"(__a), "w"(__b), "w"(__c)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_uabal2v16qi_uuuu (__a, __b, __c);
 }
 
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vabal_high_u16 (uint32x4_t __a, uint16x8_t __b, uint16x8_t __c)
 {
-  uint32x4_t __result;
-  __asm__ ("uabal2 %0.4s,%2.8h,%3.8h"
-           : "=w"(__result)
-           : "0"(__a), "w"(__b), "w"(__c)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_uabal2v8hi_uuuu (__a, __b, __c);
 }
 
 __extension__ extern __inline uint64x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vabal_high_u32 (uint64x2_t __a, uint32x4_t __b, uint32x4_t __c)
 {
-  uint64x2_t __result;
-  __asm__ ("uabal2 %0.2d,%2.4s,%3.4s"
-           : "=w"(__result)
-           : "0"(__a), "w"(__b), "w"(__c)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_uabal2v4si_uuuu (__a, __b, __c);
 }
 
 __extension__ extern __inline int16x8_t

diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 2aa58c17a7fdac252c7aed8570c281ca8aa0f220..d57ec8479bc21f6526fb7242cd334ef172b0b240 100644 (file)
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2189,6 +2189,9 @@
 ;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
 (define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
 
+;; The unspec codes for the SABAL2, UABAL2 AdvancedSIMD instructions.
+(define_int_iterator ABAL2 [UNSPEC_SABAL2 UNSPEC_UABAL2])
+
 ;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
 (define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
 
@@ -2975,6 +2978,7 @@
                      (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
                      (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
                      (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
+                     (UNSPEC_SABAL2 "s") (UNSPEC_UABAL2 "u")
                      (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
                      (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
                      (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")