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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 56c96c78682d5875cb2220172f390d3be1af3749..57a3bca3fb53da5aa41bdec37390b976fd2ea10f 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -43,4 +43,17 @@ reviving Cray Vectors, has severe performance and imolementation
 limitations that are only really apparent to exceptionally experienced
 assembly-level developers with a wide, diverse depth in multiple ISAs:
 one of the best and clearest is a
-[ycombinator post](
+[ycombinator post](https://news.ycombinator.com/item?id=24459041)
+by adrian_b.
+
+Adrian logically and concisely points out that the fundamental
+design assumptions and
+simplifications that went into the RISC-V ISA have an
+irrevocably damaging effect
+on its viability for high performance use.  That is not to say that
+its use in low-performance embedded scenarios is not ideal: in
+private custom secretive commercial usage it is perfect. Ubiquitous
+and common everyday usage in scenarios currently occupied by ARM, Intel,
+AMD and IBM: not so much. Thus, even though RISC-V has Cray-style Vectors,
+the ISA is, unfortunately, fundamentally flawed.
+