Added LO to ICESTORM_LC for LUT cascade route.

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 17b6be9ce7d802b68bc89351d9aa32860c13fad1..f9404024555bdbcf021d6f7d515e7c7cb679106d 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -661,7 +661,7 @@ endmodule
 
 module ICESTORM_LC (
        input I0, I1, I2, I3, CIN, CLK, CEN, SR,
-       output O, COUT
+       output LO, O, COUT
 );
        parameter [15:0] LUT_INIT = 0;
 
@@ -678,6 +678,8 @@ module ICESTORM_LC (
        wire [1:0] lut_s1 = I1 ?   lut_s2[ 3:2] :   lut_s2[1:0];
        wire       lut_o  = I0 ?   lut_s1[   1] :   lut_s1[  0];
 
+       assign LO = lut_o;
+
        wire polarized_clk;
        assign polarized_clk = CLK ^ NEG_CLK;