write_verilog with *.v extension

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 6e57ab7f39b165ee4dd15e8f9f49fbaa59c64b6f..330361f65a4b8774671fdb53411714751bae1f06 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -435,7 +435,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                //              count_gates, GetSize(signal_list), count_input, count_output);
 
 #if 0
-               Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.xaig", tempdir_name.c_str()));
+               Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.v", tempdir_name.c_str()));
 #endif
                Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));