add comparison section

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index bd5c1502eda3310d506415b1b167433a7fc1098d..c9308e28f236d45d42a9853eb2e59305b355105d 100644 (file)
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1114,7 +1114,7 @@ RVV (as it stands, Draft 0.4 Section 17, RISC-V ISA V2.3-Draft)
   transferred out to memory, into standard regfiles, then back to memory,
   then back to the vector unit, this to occur potentially multiple times.
 * minus: will never fit into Compressed instruction space (as-is.  May
-  be able to do so if features of Simple-V are partially adopted).
+  be able to do so if "indirect" features of Simple-V are partially adopted).
 * plus-and-slight-minus: extended variants may address up to 256
   vectorised registers (requires 48/64-bit opcodes to do it).