intel_alm: M10K write-enable is negative-true

diff --git a/techlibs/intel_alm/Makefile.inc b/techlibs/intel_alm/Makefile.inc
index 614d5802ca9f0e1597d5dc1cac2c30a52eb114b6..b5f279a921cf6f877285445219cb5b61fd0b9574 100644 (file)
--- a/techlibs/intel_alm/Makefile.inc
+++ b/techlibs/intel_alm/Makefile.inc
@@ -19,6 +19,7 @@ $(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclone
 
 # RAM
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
+$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k_map.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k.txt))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k_map.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))

diff --git a/techlibs/intel_alm/common/bram_m10k.txt b/techlibs/intel_alm/common/bram_m10k.txt
index 0d9a49b7d4d997d514d8a156001b69e310d039ef..560711b658e94b3508808ca2db29b98d8ce5825c 100644 (file)
--- a/techlibs/intel_alm/common/bram_m10k.txt
+++ b/techlibs/intel_alm/common/bram_m10k.txt
@@ -1,4 +1,4 @@
-bram MISTRAL_M10K
+bram $__MISTRAL_M10K
     init   0   # TODO: Re-enable when I figure out how BRAM init works
     abits 13   @D8192x1
     dbits  1   @D8192x1
@@ -21,7 +21,7 @@ bram MISTRAL_M10K
 endbram
 
 
-match MISTRAL_M10K
+match $__MISTRAL_M10K
     min efficiency 5
     make_transp
 endmatch

diff --git a/techlibs/intel_alm/common/bram_m10k_map.v b/techlibs/intel_alm/common/bram_m10k_map.v
new file mode 100644 (file)
index 0000000..8f9d4a3
--- /dev/null
+++ b/techlibs/intel_alm/common/bram_m10k_map.v
@@ -0,0 +1,16 @@
+// Stub to invert M10K write-enable.
+
+module \$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+
+parameter CFG_ABITS = 10;
+parameter CFG_DBITS = 10;
+
+input CLK1;
+input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
+input [CFG_DBITS-1:0] A1DATA;
+input A1EN, B1EN;
+output reg [CFG_DBITS-1:0] B1DATA;
+
+MISTRAL_M10K #(.CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN));
+
+endmodule
\ No newline at end of file

diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v
index 370e17f27314d75e12118aee385bfd261e6f6da8..c9ba8c7f12965016f19485b6dde6e3c9a6ec1df8 100644 (file)
--- a/techlibs/intel_alm/common/mem_sim.v
+++ b/techlibs/intel_alm/common/mem_sim.v
@@ -145,7 +145,7 @@ endspecify
 `endif
 
 always @(posedge CLK1) begin
-    if (A1EN)
+    if (!A1EN)
         mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
 
     if (B1EN)

diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v
index 5850f6907eb9579b884a7ebc3918ca12e6783e53..217dc5de98bb904a78d7455056a2c3c68fa4260c 100644 (file)
--- a/techlibs/intel_alm/common/quartus_rename.v
+++ b/techlibs/intel_alm/common/quartus_rename.v
@@ -157,6 +157,11 @@ output [CFG_DBITS-1:0] B1DATA;
 // Much like the MLAB, the M10K has mem_init[01234] parameters which would let
 // you initialise the RAM cell via hex literals. If they were implemented.
 
+// Since the MISTRAL_M10K block has an inverted write-enable (like the real hardware)
+// but the Quartus primitive expects a normal write-enable, we add an inverter.
+wire A1EN_N;
+NOT wren_inv (.IN(A1EN), .OUT(A1EN_N));
+
 `RAM_BLOCK #(
     .operation_mode("dual_port"),
     .logical_ram_name(_TECHMAP_CELLNAME_),
@@ -176,10 +181,10 @@ output [CFG_DBITS-1:0] B1DATA;
     .port_b_first_bit_number(0),
     .port_b_address_clock("clock0"),
     .port_b_read_enable_clock("clock0")
-) _TECHMAP_REPLACE_ (
+) ram_block (
     .portaaddr(A1ADDR),
     .portadatain(A1DATA),
-    .portawe(A1EN),
+    .portawe(A1EN_N),
     .portbaddr(B1ADDR),
     .portbdataout(B1DATA),
     .portbre(B1EN),

diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index 34a5ffa5d9849ba00c2ee205ec70905febb3a374..43d3592d5a27d23e7d4cff352578ce4a872a9298 100644 (file)
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -262,8 +262,7 @@ struct SynthIntelALMPass : public ScriptPass {
 
                if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
                        run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type.c_str()));
-                       if (help_mode || bram_type != "m10k")
-                               run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
+                       run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
                }
 
                if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {

diff --git a/tests/arch/intel_alm/blockram.ys b/tests/arch/intel_alm/blockram.ys
index c157c31656ccdf814f2c03e730f0bdef5325f462..3b61b93390c8da3a3979e842ac27d82322a2f1e0 100644 (file)
--- a/tests/arch/intel_alm/blockram.ys
+++ b/tests/arch/intel_alm/blockram.ys
@@ -2,5 +2,6 @@ read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
 synth_intel_alm -family cyclonev -noiopad -noclkbuf
 cd sync_ram_sdp
+select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 1 t:MISTRAL_M10K
-select -assert-none t:MISTRAL_M10K %% t:* %D
+select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D