change sv/trans/svp64.py source/dest elwidth assembler naming

https://libre-soc.org/irclog/%23libre-soc.2022-09-18.log.html#t2022-09-18T09:40:40

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 7f0b880cb616d7dd9853dde588590690789c4faa..8ec257b9ca517c96c18d07ba5f2ec63f02585f05 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1089,9 +1089,14 @@ class SVP64Asm:
             # vec2/3/4
             elif encmode.startswith("vec"):
                 subvl = decode_subvl(encmode[3:])
-            # elwidth
-            elif encmode.startswith("ew="):
+            # elwidth (both src and dest, like mask)
+            elif encmode.startswith("w="):
+                destwid = decode_elwidth(encmode[2:])
+                srcwid = decode_elwidth(encmode[2:])
+            # just dest width
+            elif encmode.startswith("dw="):
                 destwid = decode_elwidth(encmode[3:])
+            # just src width
             elif encmode.startswith("sw="):
                 srcwid = decode_elwidth(encmode[3:])
             # element-strided LD/ST

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 99931be3e8d5c811e859a996fa595b3a8fa87a52..a373ecb80114fafafc330c9afe436f1c591b8eca 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -182,15 +182,18 @@ class SVSTATETestCase(unittest.TestCase):
 
     def test_11_elwidth(self):
         expected = [
-                    "sv.add./ew=8 *3,*7,*11",
-                    "sv.add./ew=16 *3,*7,*11",
-                    "sv.add./ew=32 *3,*7,*11",
+                    "sv.add./dw=8 *3,*7,*11",
+                    "sv.add./dw=16 *3,*7,*11",
+                    "sv.add./dw=32 *3,*7,*11",
                     "sv.add./sw=8 *3,*7,*11",
                     "sv.add./sw=16 *3,*7,*11",
                     "sv.add./sw=32 *3,*7,*11",
-                    "sv.add./ew=8/sw=16 *3,*7,*11",
-                    "sv.add./ew=16/sw=32 *3,*7,*11",
-                    "sv.add./ew=32/sw=8 *3,*7,*11",
+                    "sv.add./dw=8/sw=16 *3,*7,*11",
+                    "sv.add./dw=16/sw=32 *3,*7,*11",
+                    "sv.add./dw=32/sw=8 *3,*7,*11",
+                    "sv.add./w=32 *3,*7,*11",
+                    "sv.add./w=8 *3,*7,*11",
+                    "sv.add./w=16 *3,*7,*11",
                         ]
         self._do_tst(expected)