r600g: translate ARR instruction

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 1a0b35d9bf59a904963123b8b60c4d7fe722fdde..f6153c0e80fbc2140c72db6a6c563e393b19f9d1 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2663,7 +2663,18 @@ static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
        int r;
        memset(&alu, 0, sizeof(struct r600_bc_alu));
 
-       alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
+        switch (inst->Instruction.Opcode) {
+        case TGSI_OPCODE_ARL:
+           alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
+           break;
+        case TGSI_OPCODE_ARR:
+           alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
+           break;
+        default:
+           assert(0);
+           return -1;
+        }
+        
 
        r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
        if (r)
@@ -3070,7 +3081,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_UP4UB,     0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_X2D,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ARA,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_ARR,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ARR,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
        {TGSI_OPCODE_BRA,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_CAL,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_RET,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},