https://bugs.libre-soc.org/show_bug.cgi?id=730#c27

yep, the CR Field numbering has already been fixed so does not need
inverting with a 7-i

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index e709c9e44404eb1424e803422a0bbc3c4d9c8190..5f7e7ceacb2dae392f87cb98a3b7124089d5eec5 100644 (file)
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -52,9 +52,7 @@ class ALUTestCase(TestAccumulatorBase):
         e.intregs[1] = 0xc523e996a8ff6215
         e.intregs[2] = 0xe1e5b9cc9864c4a8
         e.intregs[3] = 0xa709a363416426bd
-        # XXX unexpected value, investigating
-        # e.crregs[0] = 0x8
-        e.crregs[0] = 0x0
+        e.crregs[0] = 0x8
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
         lst = [f"add 3, 1, 2"]
         initial_regs = [0] * 32

diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py
index 7995a8bcb65f1391168d84cc777cf2f50b06f073..852969860fa428aa14d277f5faec263d473fbcf5 100644 (file)
--- a/src/openpower/test/state.py
+++ b/src/openpower/test/state.py
@@ -235,9 +235,9 @@ class ExpectedState(State):
                 if(reg != 0):
                     msg = "%se.intregs[%d] = 0x%x\n"
                     sout.write( msg % (lindent, i, reg))
-            # cr
+            # CR fields
             for i in range(8):
-                cri = state.crregs[7 - i]
+                cri = state.crregs[i] # Power ISA numbering already sorted
                 if(cri != 0):
                     msg = "%se.crregs[%d] = 0x%x\n"
                     sout.write( msg % (lindent, i, cri))