void extract_cell(RTLIL::Cell *cell, bool keepff)
{
- if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
{
- if (clk_polarity != (cell->type == "$_DFF_P_"))
+ if (clk_polarity != (cell->type == ID($_DFF_P_)))
return;
if (clk_sig != assign_map(cell->getPort("\\C")))
return;
goto matching_dff;
}
- if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
+ if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
{
- if (clk_polarity != cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"))
+ if (clk_polarity != cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_)))
return;
- if (en_polarity != cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"))
+ if (en_polarity != cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
return;
if (clk_sig != assign_map(cell->getPort("\\C")))
return;
return;
}
- if (cell->type.in("$_BUF_", "$_NOT_"))
+ if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
assign_map.apply(sig_a);
assign_map.apply(sig_y);
- map_signal(sig_y, cell->type == "$_BUF_" ? G(BUF) : G(NOT), map_signal(sig_a));
+ map_signal(sig_y, cell->type == ID($_BUF_) ? G(BUF) : G(NOT), map_signal(sig_a));
module->remove(cell);
return;
}
- if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_"))
+ if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_b = cell->getPort("\\B");
int mapped_a = map_signal(sig_a);
int mapped_b = map_signal(sig_b);
- if (cell->type == "$_AND_")
+ if (cell->type == ID($_AND_))
map_signal(sig_y, G(AND), mapped_a, mapped_b);
- else if (cell->type == "$_NAND_")
+ else if (cell->type == ID($_NAND_))
map_signal(sig_y, G(NAND), mapped_a, mapped_b);
- else if (cell->type == "$_OR_")
+ else if (cell->type == ID($_OR_))
map_signal(sig_y, G(OR), mapped_a, mapped_b);
- else if (cell->type == "$_NOR_")
+ else if (cell->type == ID($_NOR_))
map_signal(sig_y, G(NOR), mapped_a, mapped_b);
- else if (cell->type == "$_XOR_")
+ else if (cell->type == ID($_XOR_))
map_signal(sig_y, G(XOR), mapped_a, mapped_b);
- else if (cell->type == "$_XNOR_")
+ else if (cell->type == ID($_XNOR_))
map_signal(sig_y, G(XNOR), mapped_a, mapped_b);
- else if (cell->type == "$_ANDNOT_")
+ else if (cell->type == ID($_ANDNOT_))
map_signal(sig_y, G(ANDNOT), mapped_a, mapped_b);
- else if (cell->type == "$_ORNOT_")
+ else if (cell->type == ID($_ORNOT_))
map_signal(sig_y, G(ORNOT), mapped_a, mapped_b);
else
log_abort();
return;
}
- if (cell->type.in("$_MUX_", "$_NMUX_"))
+ if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
{
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_b = cell->getPort("\\B");
int mapped_b = map_signal(sig_b);
int mapped_s = map_signal(sig_s);
- map_signal(sig_y, cell->type == "$_MUX_" ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
+ map_signal(sig_y, cell->type == ID($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
module->remove(cell);
return;
}
- if (cell->type.in("$_AOI3_", "$_OAI3_"))
+ if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
{
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_b = cell->getPort("\\B");
int mapped_b = map_signal(sig_b);
int mapped_c = map_signal(sig_c);
- map_signal(sig_y, cell->type == "$_AOI3_" ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
+ map_signal(sig_y, cell->type == ID($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
module->remove(cell);
return;
}
- if (cell->type.in("$_AOI4_", "$_OAI4_"))
+ if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
{
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_b = cell->getPort("\\B");
int mapped_c = map_signal(sig_c);
int mapped_d = map_signal(sig_d);
- map_signal(sig_y, cell->type == "$_AOI4_" ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
+ map_signal(sig_y, cell->type == ID($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
module->remove(cell);
return;
auto sig = signal_list.at(sid);
if (sig.bit.wire != nullptr)
{
- std::stringstream sstr;
- sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1);
+ std::string s = stringf("$abc$%d$%s", map_autoidx, sig.bit.wire->name.c_str()+1);
if (sig.bit.wire->width != 1)
- sstr << "[" << sig.bit.offset << "]";
+ s += stringf("[%d]", sig.bit.offset);
if (isnew)
- sstr << "_new";
- sstr << postfix;
+ s += "_new";
+ s += postfix;
if (orig_wire != nullptr)
*orig_wire = sig.bit.wire;
- return sstr.str();
+ return s;
}
}
}
}
- std::stringstream sstr;
- sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
- return sstr.str();
+ return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
}
void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std::set<int> &workpool, std::vector<int> &in_counts)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
fprintf(f, "GATE ONE 1 Y=CONST1;\n");
- fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_BUF_"));
- fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NOT_"));
+ fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
+ fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_)));
if (enabled_gates.count("AND"))
- fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_AND_"));
+ fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_AND_)));
if (enabled_gates.count("NAND"))
- fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NAND_"));
+ fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_)));
if (enabled_gates.count("OR"))
- fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_OR_"));
+ fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_OR_)));
if (enabled_gates.count("NOR"))
- fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NOR_"));
+ fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_)));
if (enabled_gates.count("XOR"))
- fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_XOR_"));
+ fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_)));
if (enabled_gates.count("XNOR"))
- fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_XNOR_"));
+ fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_)));
if (enabled_gates.count("ANDNOT"))
- fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_ANDNOT_"));
+ fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_)));
if (enabled_gates.count("ORNOT"))
- fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_ORNOT_"));
+ fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_)));
if (enabled_gates.count("AOI3"))
- fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_AOI3_"));
+ fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_)));
if (enabled_gates.count("OAI3"))
- fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_OAI3_"));
+ fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_)));
if (enabled_gates.count("AOI4"))
- fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_AOI4_"));
+ fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_)));
if (enabled_gates.count("OAI4"))
- fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_OAI4_"));
+ fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_)));
if (enabled_gates.count("MUX"))
- fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_MUX_"));
+ fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_)));
if (enabled_gates.count("NMUX"))
- fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_NMUX_"));
+ fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_)));
if (map_mux4)
- fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at("$_MUX_"));
+ fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_)));
if (map_mux8)
- fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at("$_MUX_"));
+ fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_)));
if (map_mux16)
- fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at("$_MUX_"));
+ fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_)));
fclose(f);
if (!lut_costs.empty()) {
continue;
}
if (c->type == "\\NOT") {
- RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_NOT_");
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
continue;
}
if (c->type.in("\\AND", "\\OR", "\\XOR", "\\NAND", "\\NOR", "\\XNOR", "\\ANDNOT", "\\ORNOT")) {
- RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
continue;
}
if (c->type.in("\\MUX", "\\NMUX")) {
- RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
continue;
}
if (c->type == "\\MUX4") {
- RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX4_");
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
continue;
}
if (c->type == "\\MUX8") {
- RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX8_");
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
continue;
}
if (c->type == "\\MUX16") {
- RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX16_");
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
continue;
}
if (c->type.in("\\AOI3", "\\OAI3")) {
- RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
continue;
}
if (c->type.in("\\AOI4", "\\OAI4")) {
- RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
log_assert(clk_sig.size() == 1);
RTLIL::Cell *cell;
if (en_sig.size() == 0) {
- cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
+ cell = module->addCell(remap_name(c->name), clk_polarity ? ID($_DFF_P_) : ID($_DFF_N_));
} else {
log_assert(en_sig.size() == 1);
cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
log_assert(clk_sig.size() == 1);
RTLIL::Cell *cell;
if (en_sig.size() == 0) {
- cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
+ cell = module->addCell(remap_name(c->name), clk_polarity ? ID($_DFF_P_) : ID($_DFF_N_));
} else {
log_assert(en_sig.size() == 1);
cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
continue;
}
- if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
+ if (c->type == ID($lut) && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
module->connect(my_y, my_a);
}
}
- if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
{
- key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
+ key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
}
else
- if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_" "$_DFFE_PN_", "$_DFFE_PP_"))
+ if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
{
- bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
- bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
+ bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
+ bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
}
else
bool clk_polarity, en_polarity;
RTLIL::SigSpec clk_sig, en_sig;
-std::string remap_name(RTLIL::IdString abc_name)
+inline std::string remap_name(RTLIL::IdString abc_name)
{
- std::stringstream sstr;
- sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
- return sstr.str();
+ return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
}
void handle_loops(RTLIL::Design *design)
if (ifs.fail())
log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
- log_assert(!design->module("$__abc9__"));
+ log_assert(!design->module(ID($__abc9__)));
{
- AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
+ AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
reader.parse_xaiger();
}
ifs.close();
Pass::call(design, stringf("write_verilog -noexpr -norename"));
- design->remove(design->module("$__abc9__"));
+ design->remove(design->module(ID($__abc9__)));
#endif
design->selection_stack.pop_back();
log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
- log_assert(!design->module("$__abc9__"));
+ log_assert(!design->module(ID($__abc9__)));
- AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
+ AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
reader.parse_xaiger(box_lookup);
ifs.close();
#endif
log_header(design, "Re-integrating ABC9 results.\n");
- RTLIL::Module *mapped_mod = design->module("$__abc9__");
+ RTLIL::Module *mapped_mod = design->module(ID($__abc9__));
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `$__abc9__'.\n");
vector<RTLIL::Cell*> boxes;
for (const auto &it : module->cells_) {
auto cell = it.second;
- if (cell->type.in("$_AND_", "$_NOT_")) {
+ if (cell->type.in(ID($_AND_), ID($_NOT_))) {
module->remove(cell);
continue;
}
dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
- std::map<std::string, int> cell_stats;
+ std::map<IdString, int> cell_stats;
for (auto c : mapped_mod->cells())
{
toposort.node(c->name);
RTLIL::Cell *cell = nullptr;
- if (c->type == "$_NOT_") {
+ if (c->type == ID($_NOT_)) {
RTLIL::SigBit a_bit = c->getPort("\\A");
RTLIL::SigBit y_bit = c->getPort("\\Y");
bit_users[a_bit].insert(c->name);
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
bit2sinks[cell->getPort("\\A")].push_back(cell);
- cell_stats["$lut"]++;
+ cell_stats[ID($lut)]++;
}
else
not2drivers[c] = driver_lut;
cell_stats[RTLIL::unescape_id(c->type)]++;
RTLIL::Cell *existing_cell = nullptr;
- if (c->type == "$lut") {
+ if (c->type == ID($lut)) {
if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT") == RTLIL::Const::from_string("01")) {
SigSpec my_a = module->wires_.at(remap_name(c->getPort("\\A").as_wire()->name));
SigSpec my_y = module->wires_.at(remap_name(c->getPort("\\Y").as_wire()->name));
for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
log_assert(not_cell);
- if (not_cell->type != "$_NOT_")
+ if (not_cell->type != ID($_NOT_))
continue;
auto it = not2drivers.find(not_cell);
if (it == not2drivers.end())
goto clone_lut;
for (auto sink_cell : jt->second)
- if (sink_cell->type != "$lut")
+ if (sink_cell->type != ID($lut))
goto clone_lut;
// Push downstream LUTs past inverter
}
}
- if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
{
- key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
+ key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
}
else
- if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
+ if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
{
- bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
- bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
+ bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
+ bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
}
else
{
Aig aig(cell);
- if (cell->type.in("$_AND_", "$_NOT_"))
+ if (cell->type.in(ID($_AND_), ID($_NOT_)))
aig.name.clear();
- if (nand_mode && cell->type == "$_NAND_")
+ if (nand_mode && cell->type == ID($_NAND_))
aig.name.clear();
if (aig.name.empty()) {
{
for (auto cell : module->selected_cells())
{
- if (!cell->type.in("$pos", "$neg", "$add", "$sub", "$mul"))
+ if (!cell->type.in(ID($pos), ID($neg), ID($add), ID($sub), ID($mul)))
continue;
log(" creating $macc model for %s (%s).\n", log_id(cell), log_id(cell->type));
for (auto bit : n->y)
n->users = max(n->users, bit_users.at(bit) - 1);
- if (cell->type.in("$pos", "$neg"))
+ if (cell->type.in(ID($pos), ID($neg)))
{
new_port.in_a = sigmap(cell->getPort("\\A"));
new_port.is_signed = cell->getParam("\\A_SIGNED").as_bool();
- new_port.do_subtract = cell->type == "$neg";
+ new_port.do_subtract = cell->type == ID($neg);
n->macc.ports.push_back(new_port);
}
- if (cell->type.in("$add", "$sub"))
+ if (cell->type.in(ID($add), ID($sub)))
{
new_port.in_a = sigmap(cell->getPort("\\A"));
new_port.is_signed = cell->getParam("\\A_SIGNED").as_bool();
new_port.in_a = sigmap(cell->getPort("\\B"));
new_port.is_signed = cell->getParam("\\B_SIGNED").as_bool();
- new_port.do_subtract = cell->type == "$sub";
+ new_port.do_subtract = cell->type == ID($sub);
n->macc.ports.push_back(new_port);
}
- if (cell->type.in("$mul"))
+ if (cell->type.in(ID($mul)))
{
new_port.in_a = sigmap(cell->getPort("\\A"));
new_port.in_b = sigmap(cell->getPort("\\B"));
for (auto &it : sig_macc)
{
auto n = it.second;
- auto cell = module->addCell(NEW_ID, "$macc");
+ auto cell = module->addCell(NEW_ID, ID($macc));
macc_counter++;
for (auto cell : module->selected_cells())
{
- if (cell->type.in("$lt", "$le", "$ge", "$gt"))
+ if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt)))
lge_cells.push_back(cell);
- if (cell->type.in("$eq", "$eqx", "$ne", "$nex"))
+ if (cell->type.in(ID($eq), ID($eqx), ID($ne), ID($nex)))
eq_cells.push_back(cell);
}
{
log(" creating $alu model for %s (%s):", log_id(cell), log_id(cell->type));
- bool cmp_less = cell->type.in("$lt", "$le");
- bool cmp_equal = cell->type.in("$le", "$ge");
+ bool cmp_less = cell->type.in(ID($lt), ID($le));
+ bool cmp_equal = cell->type.in(ID($le), ID($ge));
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort("\\A"));
for (auto cell : eq_cells)
{
- bool cmp_equal = cell->type.in("$eq", "$eqx");
+ bool cmp_equal = cell->type.in(ID($eq), ID($eqx));
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort("\\A"));
goto delete_node;
}
- n->alu_cell = module->addCell(NEW_ID, "$alu");
+ n->alu_cell = module->addCell(NEW_ID, ID($alu));
alu_counter++;
log(" creating $alu cell for ");
for (auto bit : sigmap(conn.second))
bits_used.insert(bit);
- if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf"))
+ if (conn.first == "\\Y" && cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_TBUF_), ID($tribuf)))
{
- bool tribuf = cell->type.in("$_TBUF_", "$tribuf");
+ bool tribuf = cell->type.in(ID($_TBUF_), ID($tribuf));
if (!tribuf) {
for (auto &c : cell->connections()) {
}
for (auto cell : module->cells()) {
- if (cell->type.in("$mux", "$pmux", "$_MUX_")) {
+ if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i);
}
if (direct_dict.empty()) {
- if (cell->type.in("$dff", "$_DFF_N_", "$_DFF_P_"))
+ if (cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_)))
dff_cells.push_back(cell);
} else {
if (direct_dict.count(cell->type))
dff_cell->setPort("\\E", make_patterns_logic(it.first, true));
dff_cell->type = direct_dict.at(dff_cell->type);
} else
- if (dff_cell->type == "$dff") {
+ if (dff_cell->type == ID($dff)) {
RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort("\\CLK"), make_patterns_logic(it.first, false),
new_sig_d, new_sig_q, dff_cell->getParam("\\CLK_POLARITY").as_bool(), true);
log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
} else {
RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort("\\C"), make_patterns_logic(it.first, true),
- new_sig_d, new_sig_q, dff_cell->type == "$_DFF_P_", true);
+ new_sig_d, new_sig_q, dff_cell->type == ID($_DFF_P_), true);
log(" created %s cell %s for %s -> %s.\n", log_id(new_cell->type), log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
}
}
if (args[argidx] == "-direct-match" && argidx + 1 < args.size()) {
bool found_match = false;
const char *pattern = args[++argidx].c_str();
- if (patmatch(pattern, "$_DFF_P_" )) found_match = true, direct_dict["$_DFF_P_" ] = "$_DFFE_PP_";
- if (patmatch(pattern, "$_DFF_N_" )) found_match = true, direct_dict["$_DFF_N_" ] = "$_DFFE_NP_";
- if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict["$_DFF_NN0_"] = "$__DFFE_NN0";
- if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict["$_DFF_NN1_"] = "$__DFFE_NN1";
- if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict["$_DFF_NP0_"] = "$__DFFE_NP0";
- if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict["$_DFF_NP1_"] = "$__DFFE_NP1";
- if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict["$_DFF_PN0_"] = "$__DFFE_PN0";
- if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict["$_DFF_PN1_"] = "$__DFFE_PN1";
- if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict["$_DFF_PP0_"] = "$__DFFE_PP0";
- if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict["$_DFF_PP1_"] = "$__DFFE_PP1";
-
- if (patmatch(pattern, "$__DFFS_NN0_")) found_match = true, direct_dict["$__DFFS_NN0_"] = "$__DFFSE_NN0";
- if (patmatch(pattern, "$__DFFS_NN1_")) found_match = true, direct_dict["$__DFFS_NN1_"] = "$__DFFSE_NN1";
- if (patmatch(pattern, "$__DFFS_NP0_")) found_match = true, direct_dict["$__DFFS_NP0_"] = "$__DFFSE_NP0";
- if (patmatch(pattern, "$__DFFS_NP1_")) found_match = true, direct_dict["$__DFFS_NP1_"] = "$__DFFSE_NP1";
- if (patmatch(pattern, "$__DFFS_PN0_")) found_match = true, direct_dict["$__DFFS_PN0_"] = "$__DFFSE_PN0";
- if (patmatch(pattern, "$__DFFS_PN1_")) found_match = true, direct_dict["$__DFFS_PN1_"] = "$__DFFSE_PN1";
- if (patmatch(pattern, "$__DFFS_PP0_")) found_match = true, direct_dict["$__DFFS_PP0_"] = "$__DFFSE_PP0";
- if (patmatch(pattern, "$__DFFS_PP1_")) found_match = true, direct_dict["$__DFFS_PP1_"] = "$__DFFSE_PP1";
+ if (patmatch(pattern, "$_DFF_P_" )) found_match = true, direct_dict[ID($_DFF_P_) ] = ID($_DFFE_PP_);
+ if (patmatch(pattern, "$_DFF_N_" )) found_match = true, direct_dict[ID($_DFF_N_) ] = ID($_DFFE_NP_);
+ if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict[ID($_DFF_NN0_)] = ID($__DFFE_NN0);
+ if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict[ID($_DFF_NN1_)] = ID($__DFFE_NN1);
+ if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict[ID($_DFF_NP0_)] = ID($__DFFE_NP0);
+ if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict[ID($_DFF_NP1_)] = ID($__DFFE_NP1);
+ if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict[ID($_DFF_PN0_)] = ID($__DFFE_PN0);
+ if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict[ID($_DFF_PN1_)] = ID($__DFFE_PN1);
+ if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict[ID($_DFF_PP0_)] = ID($__DFFE_PP0);
+ if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict[ID($_DFF_PP1_)] = ID($__DFFE_PP1);
+
+ if (patmatch(pattern, "$__DFFS_NN0_")) found_match = true, direct_dict[ID($__DFFS_NN0_)] = ID($__DFFSE_NN0);
+ if (patmatch(pattern, "$__DFFS_NN1_")) found_match = true, direct_dict[ID($__DFFS_NN1_)] = ID($__DFFSE_NN1);
+ if (patmatch(pattern, "$__DFFS_NP0_")) found_match = true, direct_dict[ID($__DFFS_NP0_)] = ID($__DFFSE_NP0);
+ if (patmatch(pattern, "$__DFFS_NP1_")) found_match = true, direct_dict[ID($__DFFS_NP1_)] = ID($__DFFSE_NP1);
+ if (patmatch(pattern, "$__DFFS_PN0_")) found_match = true, direct_dict[ID($__DFFS_PN0_)] = ID($__DFFSE_PN0);
+ if (patmatch(pattern, "$__DFFS_PN1_")) found_match = true, direct_dict[ID($__DFFS_PN1_)] = ID($__DFFSE_PN1);
+ if (patmatch(pattern, "$__DFFS_PP0_")) found_match = true, direct_dict[ID($__DFFS_PP0_)] = ID($__DFFSE_PP0);
+ if (patmatch(pattern, "$__DFFS_PP1_")) found_match = true, direct_dict[ID($__DFFS_PP1_)] = ID($__DFFSE_PP1);
if (!found_match)
log_cmd_error("No cell types matched pattern '%s'.\n", pattern);
continue;
if (unmap_mode) {
SigMap sigmap(mod);
for (auto cell : mod->selected_cells()) {
- if (cell->type == "$dffe") {
+ if (cell->type == ID($dffe)) {
if (min_ce_use >= 0) {
int ce_use = 0;
for (auto cell_other : mod->selected_cells()) {
extra_args(args, argidx, design);
pool<IdString> dff_types;
- dff_types.insert("$_DFF_N_");
- dff_types.insert("$_DFF_P_");
+ dff_types.insert(ID($_DFF_N_));
+ dff_types.insert(ID($_DFF_P_));
for (auto module : design->selected_modules())
{
continue;
}
- if (cell->type != "$_MUX_")
+ if (cell->type != ID($_MUX_))
continue;
SigBit bit_a = sigmap(cell->getPort("\\A"));
}
if (sr_val == State::S1) {
- if (cell->type == "$_DFF_N_") {
- if (invert_sr) cell->type = "$__DFFS_NN1_";
- else cell->type = "$__DFFS_NP1_";
+ if (cell->type == ID($_DFF_N_)) {
+ if (invert_sr) cell->type = ID($__DFFS_NN1_);
+ else cell->type = ID($__DFFS_NP1_);
} else {
- log_assert(cell->type == "$_DFF_P_");
- if (invert_sr) cell->type = "$__DFFS_PN1_";
- else cell->type = "$__DFFS_PP1_";
+ log_assert(cell->type == ID($_DFF_P_));
+ if (invert_sr) cell->type = ID($__DFFS_PN1_);
+ else cell->type = ID($__DFFS_PP1_);
}
} else {
- if (cell->type == "$_DFF_N_") {
- if (invert_sr) cell->type = "$__DFFS_NN0_";
- else cell->type = "$__DFFS_NP0_";
+ if (cell->type == ID($_DFF_N_)) {
+ if (invert_sr) cell->type = ID($__DFFS_NN0_);
+ else cell->type = ID($__DFFS_NP0_);
} else {
- log_assert(cell->type == "$_DFF_P_");
- if (invert_sr) cell->type = "$__DFFS_PN0_";
- else cell->type = "$__DFFS_PP0_";
+ log_assert(cell->type == ID($_DFF_P_));
+ if (invert_sr) cell->type = ID($__DFFS_PN0_);
+ else cell->type = ID($__DFFS_PP0_);
}
}
cell->setPort("\\R", sr_sig);
PRIVATE_NAMESPACE_BEGIN
struct cell_mapping {
- std::string cell_name;
- std::map<std::string, char> ports;
+ IdString cell_name;
+ std::map<IdString, char> ports;
};
static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
-static void logmap(std::string dff)
+static void logmap(IdString dff)
{
if (cell_mappings.count(dff) == 0) {
log(" unmapped dff cell: %s\n", dff.c_str());
static void logmap_all()
{
- logmap("$_DFF_N_");
- logmap("$_DFF_P_");
-
- logmap("$_DFF_NN0_");
- logmap("$_DFF_NN1_");
- logmap("$_DFF_NP0_");
- logmap("$_DFF_NP1_");
- logmap("$_DFF_PN0_");
- logmap("$_DFF_PN1_");
- logmap("$_DFF_PP0_");
- logmap("$_DFF_PP1_");
-
- logmap("$_DFFSR_NNN_");
- logmap("$_DFFSR_NNP_");
- logmap("$_DFFSR_NPN_");
- logmap("$_DFFSR_NPP_");
- logmap("$_DFFSR_PNN_");
- logmap("$_DFFSR_PNP_");
- logmap("$_DFFSR_PPN_");
- logmap("$_DFFSR_PPP_");
+ logmap(ID($_DFF_N_));
+ logmap(ID($_DFF_P_));
+
+ logmap(ID($_DFF_NN0_));
+ logmap(ID($_DFF_NN1_));
+ logmap(ID($_DFF_NP0_));
+ logmap(ID($_DFF_NP1_));
+ logmap(ID($_DFF_PN0_));
+ logmap(ID($_DFF_PN1_));
+ logmap(ID($_DFF_PP0_));
+ logmap(ID($_DFF_PP1_));
+
+ logmap(ID($_DFFSR_NNN_));
+ logmap(ID($_DFFSR_NNP_));
+ logmap(ID($_DFFSR_NPN_));
+ logmap(ID($_DFFSR_NPP_));
+ logmap(ID($_DFFSR_PNN_));
+ logmap(ID($_DFFSR_PNP_));
+ logmap(ID($_DFFSR_PPN_));
+ logmap(ID($_DFFSR_PPP_));
}
static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, bool &pin_pol)
return false;
}
-static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool prepare_mode)
+static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool prepare_mode)
{
LibertyAst *best_cell = NULL;
- std::map<std::string, char> best_cell_ports;
+ std::map<IdString, char> best_cell_ports;
int best_cell_pins = 0;
bool best_cell_noninv = false;
double best_cell_area = 0;
continue;
}
- std::map<std::string, char> this_cell_ports;
+ std::map<IdString, char> this_cell_ports;
this_cell_ports[cell_clk_pin] = 'C';
if (has_reset)
this_cell_ports[cell_rst_pin] = 'R';
}
}
-static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bool setpol, bool clrpol, bool prepare_mode)
+static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool prepare_mode)
{
LibertyAst *best_cell = NULL;
- std::map<std::string, char> best_cell_ports;
+ std::map<IdString, char> best_cell_ports;
int best_cell_pins = 0;
bool best_cell_noninv = false;
double best_cell_area = 0;
if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol) || cell_clr_pol != clrpol)
continue;
- std::map<std::string, char> this_cell_ports;
+ std::map<IdString, char> this_cell_ports;
this_cell_ports[cell_clk_pin] = 'C';
this_cell_ports[cell_set_pin] = 'S';
this_cell_ports[cell_clr_pin] = 'R';
return return_status;
}
-static void map_sr_to_arst(const char *from, const char *to)
+static void map_sr_to_arst(IdString from, IdString to)
{
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return;
log_assert(from_clk_pol == to_clk_pol);
log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol);
- log(" create mapping for %s from mapping for %s.\n", to, from);
+ log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
cell_mappings[to].cell_name = cell_mappings[from].cell_name;
cell_mappings[to].ports = cell_mappings[from].ports;
}
}
-static void map_adff_to_dff(const char *from, const char *to)
+static void map_adff_to_dff(IdString from, IdString to)
{
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return;
log_assert(from_clk_pol == to_clk_pol);
- log(" create mapping for %s from mapping for %s.\n", to, from);
+ log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
cell_mappings[to].cell_name = cell_mappings[from].cell_name;
cell_mappings[to].ports = cell_mappings[from].ports;
for (auto &it : module->cells_) {
if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
cell_list.push_back(it.second);
- if (it.second->type == "$_NOT_")
+ if (it.second->type == ID($_NOT_))
notmap[sigmap(it.second->getPort("\\A"))].insert(it.second);
}
module->remove(cell);
cell_mapping &cm = cell_mappings[cell_type];
- RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name);
+ RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name.str());
new_cell->set_src_attribute(src);
sig = module->addWire(NEW_ID);
} else
log_abort();
- new_cell->setPort("\\" + port.first, sig);
+ new_cell->setPort("\\" + port.first.str(), sig);
}
stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;
LibertyParser libparser(f);
f.close();
- find_cell(libparser.ast, "$_DFF_N_", false, false, false, false, prepare_mode);
- find_cell(libparser.ast, "$_DFF_P_", true, false, false, false, prepare_mode);
-
- find_cell(libparser.ast, "$_DFF_NN0_", false, true, false, false, prepare_mode);
- find_cell(libparser.ast, "$_DFF_NN1_", false, true, false, true, prepare_mode);
- find_cell(libparser.ast, "$_DFF_NP0_", false, true, true, false, prepare_mode);
- find_cell(libparser.ast, "$_DFF_NP1_", false, true, true, true, prepare_mode);
- find_cell(libparser.ast, "$_DFF_PN0_", true, true, false, false, prepare_mode);
- find_cell(libparser.ast, "$_DFF_PN1_", true, true, false, true, prepare_mode);
- find_cell(libparser.ast, "$_DFF_PP0_", true, true, true, false, prepare_mode);
- find_cell(libparser.ast, "$_DFF_PP1_", true, true, true, true, prepare_mode);
-
- find_cell_sr(libparser.ast, "$_DFFSR_NNN_", false, false, false, prepare_mode);
- find_cell_sr(libparser.ast, "$_DFFSR_NNP_", false, false, true, prepare_mode);
- find_cell_sr(libparser.ast, "$_DFFSR_NPN_", false, true, false, prepare_mode);
- find_cell_sr(libparser.ast, "$_DFFSR_NPP_", false, true, true, prepare_mode);
- find_cell_sr(libparser.ast, "$_DFFSR_PNN_", true, false, false, prepare_mode);
- find_cell_sr(libparser.ast, "$_DFFSR_PNP_", true, false, true, prepare_mode);
- find_cell_sr(libparser.ast, "$_DFFSR_PPN_", true, true, false, prepare_mode);
- find_cell_sr(libparser.ast, "$_DFFSR_PPP_", true, true, true, prepare_mode);
+ find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false, prepare_mode);
+ find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false, prepare_mode);
+
+ find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false, prepare_mode);
+ find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true, prepare_mode);
+ find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false, prepare_mode);
+ find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true, prepare_mode);
+ find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false, prepare_mode);
+ find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true, prepare_mode);
+ find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false, prepare_mode);
+ find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true, prepare_mode);
+
+ find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false, prepare_mode);
+ find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true, prepare_mode);
+ find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false, prepare_mode);
+ find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true, prepare_mode);
+ find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false, prepare_mode);
+ find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true, prepare_mode);
+ find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false, prepare_mode);
+ find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true, prepare_mode);
// try to implement as many cells as possible just by inverting
// the SET and RESET pins. If necessary, implement cell types
break;
}
- map_sr_to_arst("$_DFFSR_NNN_", "$_DFF_NN0_");
- map_sr_to_arst("$_DFFSR_NNN_", "$_DFF_NN1_");
- map_sr_to_arst("$_DFFSR_NPP_", "$_DFF_NP0_");
- map_sr_to_arst("$_DFFSR_NPP_", "$_DFF_NP1_");
- map_sr_to_arst("$_DFFSR_PNN_", "$_DFF_PN0_");
- map_sr_to_arst("$_DFFSR_PNN_", "$_DFF_PN1_");
- map_sr_to_arst("$_DFFSR_PPP_", "$_DFF_PP0_");
- map_sr_to_arst("$_DFFSR_PPP_", "$_DFF_PP1_");
-
- map_adff_to_dff("$_DFF_NN0_", "$_DFF_N_");
- map_adff_to_dff("$_DFF_NN1_", "$_DFF_N_");
- map_adff_to_dff("$_DFF_NP0_", "$_DFF_N_");
- map_adff_to_dff("$_DFF_NP1_", "$_DFF_N_");
- map_adff_to_dff("$_DFF_PN0_", "$_DFF_P_");
- map_adff_to_dff("$_DFF_PN1_", "$_DFF_P_");
- map_adff_to_dff("$_DFF_PP0_", "$_DFF_P_");
- map_adff_to_dff("$_DFF_PP1_", "$_DFF_P_");
+ map_sr_to_arst(ID($_DFFSR_NNN_), ID($_DFF_NN0_));
+ map_sr_to_arst(ID($_DFFSR_NNN_), ID($_DFF_NN1_));
+ map_sr_to_arst(ID($_DFFSR_NPP_), ID($_DFF_NP0_));
+ map_sr_to_arst(ID($_DFFSR_NPP_), ID($_DFF_NP1_));
+ map_sr_to_arst(ID($_DFFSR_PNN_), ID($_DFF_PN0_));
+ map_sr_to_arst(ID($_DFFSR_PNN_), ID($_DFF_PN1_));
+ map_sr_to_arst(ID($_DFFSR_PPP_), ID($_DFF_PP0_));
+ map_sr_to_arst(ID($_DFFSR_PPP_), ID($_DFF_PP1_));
+
+ map_adff_to_dff(ID($_DFF_NN0_), ID($_DFF_N_));
+ map_adff_to_dff(ID($_DFF_NN1_), ID($_DFF_N_));
+ map_adff_to_dff(ID($_DFF_NP0_), ID($_DFF_N_));
+ map_adff_to_dff(ID($_DFF_NP1_), ID($_DFF_N_));
+ map_adff_to_dff(ID($_DFF_PN0_), ID($_DFF_P_));
+ map_adff_to_dff(ID($_DFF_PN1_), ID($_DFF_P_));
+ map_adff_to_dff(ID($_DFF_PP0_), ID($_DFF_P_));
+ map_adff_to_dff(ID($_DFF_PP1_), ID($_DFF_P_));
log(" final dff cell mappings:\n");
logmap_all();
void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell)
{
- if (cell->type == "$dffsr")
+ if (cell->type == ID($dffsr))
{
int width = cell->getParam("\\WIDTH").as_int();
bool setpol = cell->getParam("\\SET_POLARITY").as_bool();
cell->setParam("\\ARST_POLARITY", clrpol);
}
- cell->type = "$adff";
+ cell->type = ID($adff);
cell->unsetPort("\\SET");
cell->unsetPort("\\CLR");
cell->setParam("\\ARST_VALUE", reset_val);
return;
}
- if (cell->type.in("$_DFFSR_NNN_", "$_DFFSR_NNP_", "$_DFFSR_NPN_", "$_DFFSR_NPP_",
- "$_DFFSR_PNN_", "$_DFFSR_PNP_", "$_DFFSR_PPN_", "$_DFFSR_PPP_"))
+ if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
+ ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
{
char clkpol = cell->type.c_str()[8];
char setpol = cell->type.c_str()[9];
void adff_worker(SigMap &sigmap, Module *module, Cell *cell)
{
- if (cell->type == "$adff")
+ if (cell->type == ID($adff))
{
bool rstpol = cell->getParam("\\ARST_POLARITY").as_bool();
SigBit rstunused = rstpol ? State::S0 : State::S1;
log("Converting %s cell %s.%s to $dff.\n", log_id(cell->type), log_id(module), log_id(cell));
- cell->type = "$dff";
+ cell->type = ID($dff);
cell->unsetPort("\\ARST");
cell->unsetParam("\\ARST_VALUE");
cell->unsetParam("\\ARST_POLARITY");
return;
}
- if (cell->type.in("$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
- "$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_"))
+ if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
{
char clkpol = cell->type.c_str()[6];
char rstpol = cell->type.c_str()[7];
return 9;
Cell* count_mux = *y_loads.begin();
extract.count_mux = count_mux;
- if(count_mux->type != "$mux")
+ if(count_mux->type != ID($mux))
return 10;
if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A"))
return 11;
Cell* underflow_inv = NULL;
for(auto c : muxsel_conns)
{
- if(c->type != "$logic_not")
+ if(c->type != ID($logic_not))
continue;
if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true))
continue;
Cell* count_reg = muxload;
Cell* cemux = NULL;
RTLIL::SigSpec cey;
- if(muxload->type == "$mux")
+ if(muxload->type == ID($mux))
{
//This mux is probably a clock enable mux.
//Find our count register (should be our only load)
extract.has_ce = false;
extract.count_reg = count_reg;
- if(count_reg->type == "$dff")
+ if(count_reg->type == ID($dff))
extract.has_reset = false;
- else if(count_reg->type == "$adff")
+ else if(count_reg->type == ID($adff))
{
extract.has_reset = true;
SigMap& sigmap = index.sigmap;
//Core of the counter must be an ALU
- if (cell->type != "$alu")
+ if (cell->type != ID($alu))
return;
//A input is the count value. Check if it has COUNT_EXTRACT set.
cell->unsetParam("\\Y_WIDTH");
//Change the cell type
- cell->type = "$__COUNT_";
+ cell->type = ID($__COUNT_);
//Hook up resets
if(extract.has_reset)
{
for (auto cell : module->selected_cells())
{
- if (cell->type.in( "$_BUF_", "$_NOT_", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_",
- "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_", "$_NMUX_",
- "$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_"))
+ if (cell->type.in( ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_),
+ ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
+ ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
{
SigBit y = sigmap(SigBit(cell->getPort("\\Y")));
log_assert(driver.count(y) == 0);
for (auto it : driver)
{
- if (it.second->type.in("$_BUF_", "$_NOT_"))
+ if (it.second->type.in(ID($_BUF_), ID($_NOT_)))
continue;
SigBit root = it.first;
}
else
{
- Cell *cell = module->addCell(NEW_ID, "$fa");
+ Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam("\\WIDTH", 1);
log(" Created $fa cell %s.\n", log_id(cell));
}
else
{
- Cell *cell = module->addCell(NEW_ID, "$fa");
+ Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam("\\WIDTH", 1);
log(" Created $fa cell %s.\n", log_id(cell));
inline bool IsRightType(Cell* cell, GateType gt)
{
- return (cell->type == "$_AND_" && gt == GateType::And) ||
- (cell->type == "$_OR_" && gt == GateType::Or) ||
- (cell->type == "$_XOR_" && gt == GateType::Xor);
+ return (cell->type == ID($_AND_) && gt == GateType::And) ||
+ (cell->type == ID($_OR_) && gt == GateType::Or) ||
+ (cell->type == ID($_XOR_) && gt == GateType::Xor);
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
GateType gt;
- if (cell->type == "$_AND_")
+ if (cell->type == ID($_AND_))
gt = GateType::And;
- else if (cell->type == "$_OR_")
+ else if (cell->type == ID($_OR_))
gt = GateType::Or;
- else if (cell->type == "$_XOR_")
+ else if (cell->type == ID($_XOR_))
gt = GateType::Xor;
else
continue;
SigBit output = sigmap(head_cell->getPort("\\Y")[0]);
auto new_reduce_cell = module->addCell(NEW_ID,
- gt == GateType::And ? "$reduce_and" :
- gt == GateType::Or ? "$reduce_or" :
- gt == GateType::Xor ? "$reduce_xor" : "");
+ gt == GateType::And ? ID($reduce_and) :
+ gt == GateType::Or ? ID($reduce_or) :
+ gt == GateType::Xor ? ID($reduce_xor) : "");
new_reduce_cell->setParam("\\A_SIGNED", 0);
new_reduce_cell->setParam("\\A_WIDTH", input.size());
new_reduce_cell->setParam("\\Y_WIDTH", 1);
}
else
{
- cell_types = {"$_NOT_", "$_AND_", "$_OR_", "$_XOR_", "$_MUX_"};
+ cell_types = {ID($_NOT_), ID($_AND_), ID($_OR_), ID($_XOR_), ID($_MUX_)};
}
const char *algo_r = relax ? "-r" : "";
SigMap rewrites;
for (auto cell : module->cells())
- if (cell->type == "$_TBUF_") {
+ if (cell->type == ID($_TBUF_)) {
SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
tbuf_bits[bit].first = cell->name;
}
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells()) {
- if (cell->type == "$lut") {
+ if (cell->type == ID($lut)) {
IdString cell_name = cell->name;
int count = lut2mux(cell);
log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count);
RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$fa");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam("\\WIDTH", width);
cell->setPort("\\A", in1);
cell->setPort("\\B", in2);
}
- RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
+ RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu));
c->setPort("\\A", summands.front());
c->setPort("\\B", summands.back());
c->setPort("\\CI", State::S0);
for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells())
- if (cell->type == "$macc") {
+ if (cell->type == ID($macc)) {
log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
maccmap(mod, cell, unmap_mode);
mod->remove(cell);
if (!cell->input(conn.first))
continue;
for (auto bit : sigmap(conn.second)) {
- if (used_once.count(bit) || cell->type != "$_MUX_" || conn.first == "\\S")
+ if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == "\\S")
roots.insert(bit);
used_once.insert(bit);
}
}
- if (cell->type == "$_MUX_")
+ if (cell->type == ID($_MUX_))
sig_to_mux[sigmap(cell->getPort("\\Y"))] = cell;
}
if (GetSize(mux.inputs) == 2) {
count_muxes_by_type[0]++;
- Cell *cell = module->addCell(NEW_ID, "$_MUX_");
+ Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
cell->setPort("\\A", mux.inputs[0]);
cell->setPort("\\B", mux.inputs[1]);
cell->setPort("\\S", mux.selects[0]);
if (GetSize(mux.inputs) == 4) {
count_muxes_by_type[1]++;
- Cell *cell = module->addCell(NEW_ID, "$_MUX4_");
+ Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
cell->setPort("\\A", mux.inputs[0]);
cell->setPort("\\B", mux.inputs[1]);
cell->setPort("\\C", mux.inputs[2]);
if (GetSize(mux.inputs) == 8) {
count_muxes_by_type[2]++;
- Cell *cell = module->addCell(NEW_ID, "$_MUX8_");
+ Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
cell->setPort("\\A", mux.inputs[0]);
cell->setPort("\\B", mux.inputs[1]);
cell->setPort("\\C", mux.inputs[2]);
if (GetSize(mux.inputs) == 16) {
count_muxes_by_type[3]++;
- Cell *cell = module->addCell(NEW_ID, "$_MUX16_");
+ Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
cell->setPort("\\A", mux.inputs[0]);
cell->setPort("\\B", mux.inputs[1]);
cell->setPort("\\C", mux.inputs[2]);
for (auto cell : module->cells())
{
- if (cell->type != "$lut" || mapped_cells.count(cell))
+ if (cell->type != ID($lut) || mapped_cells.count(cell))
continue;
if (GetSize(cell->getPort("\\A")) == lut_size || lut_size == 2)
if (config.assert_mode) {
for (auto cell : module->cells())
- if (cell->type == "$lut" && !mapped_cells.count(cell))
+ if (cell->type == ID($lut) && !mapped_cells.count(cell))
log_error("Insufficient number of LUTs to map all logic cells!\n");
}
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells())
{
- if (cell->type != "$pmux")
+ if (cell->type != ID($pmux))
continue;
SigSpec sig_data = cell->getPort("\\B");
{
for (const auto &i : module->cells_) {
auto cell = i.second;
- if (cell->type == "$shiftx") {
+ if (cell->type == ID($shiftx)) {
if (cell->getParam("\\Y_WIDTH") != 1) continue;
int j = 0;
for (auto bit : sigmap(cell->getPort("\\A")))
sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
log_assert(j == cell->getParam("\\A_WIDTH").as_int());
}
- else if (cell->type == "$mux") {
+ else if (cell->type == ID($mux)) {
int j = 0;
for (auto bit : sigmap(cell->getPort("\\A")))
sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
if (it == sigbit_to_shiftx_offset.end())
return;
if (cell) {
- if (cell->type == "$shiftx" && port == "\\A")
+ if (cell->type == ID($shiftx) && port == "\\A")
return;
- if (cell->type == "$mux" && port.in("\\A", "\\B"))
+ if (cell->type == ID($mux) && port.in("\\A", "\\B"))
return;
}
sigbit_to_shiftx_offset.erase(it);
log_assert(shiftx);
// Only map if $shiftx exclusively covers the shift register
- if (shiftx->type == "$shiftx") {
+ if (shiftx->type == ID($shiftx)) {
if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int())
return false;
// Due to padding the most significant bits of A may be 1'bx,
else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
return false;
}
- else if (shiftx->type == "$mux") {
+ else if (shiftx->type == ID($mux)) {
if (GetSize(taps) != 2)
return false;
}
auto it = sigbit_to_shiftx_offset.find(bit);
log_assert(it != sigbit_to_shiftx_offset.end());
- auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_");
+ auto newcell = cell->module->addCell(NEW_ID, ID($__XILINX_SHREG_));
newcell->set_src_attribute(cell->get_src_attribute());
newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
newcell->setParam("\\INIT", cell->getParam("\\INIT"));
Cell* shiftx = std::get<0>(it->second);
RTLIL::SigSpec l_wire, q_wire;
- if (shiftx->type == "$shiftx") {
+ if (shiftx->type == ID($shiftx)) {
l_wire = shiftx->getPort("\\B");
q_wire = shiftx->getPort("\\Y");
shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
}
- else if (shiftx->type == "$mux") {
+ else if (shiftx->type == ID($mux)) {
l_wire = shiftx->getPort("\\S");
q_wire = shiftx->getPort("\\Y");
shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
int param_clkpol = -1;
int param_enpol = 2;
- if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
- if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
+ if (first_cell->type == ID($_DFF_N_)) param_clkpol = 0;
+ if (first_cell->type == ID($_DFF_P_)) param_clkpol = 1;
- if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
- if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
- if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
- if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
+ if (first_cell->type == ID($_DFFE_NN_)) param_clkpol = 0, param_enpol = 0;
+ if (first_cell->type == ID($_DFFE_NP_)) param_clkpol = 0, param_enpol = 1;
+ if (first_cell->type == ID($_DFFE_PN_)) param_clkpol = 1, param_enpol = 0;
+ if (first_cell->type == ID($_DFFE_PP_)) param_clkpol = 1, param_enpol = 1;
log_assert(param_clkpol >= 0);
first_cell->setParam("\\CLKPOL", param_clkpol);
bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
if (clk_pos && en_none)
- opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+ opts.ffcells[ID($_DFF_P_)] = make_pair(IdString("\\D"), IdString("\\Q"));
if (clk_neg && en_none)
- opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+ opts.ffcells[ID($_DFF_N_)] = make_pair(IdString("\\D"), IdString("\\Q"));
if (clk_pos && en_pos)
- opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+ opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString("\\D"), IdString("\\Q"));
if (clk_pos && en_neg)
- opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+ opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString("\\D"), IdString("\\Q"));
if (clk_neg && en_pos)
- opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+ opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString("\\D"), IdString("\\Q"));
if (clk_neg && en_neg)
- opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+ opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString("\\D"), IdString("\\Q"));
if (en_pos || en_neg)
opts.ffe = true;
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\Y", sig_y[i]);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
- if (cell->type == "$xnor")
+ if (cell->type == ID($xnor))
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
for (int i = 0; i < GetSize(sig_y); i++) {
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
gate->setPort("\\A", sig_t[i]);
gate->setPort("\\Y", sig_y[i]);
sig_y = sig_t;
}
- std::string gate_type;
- if (cell->type == "$and") gate_type = "$_AND_";
- if (cell->type == "$or") gate_type = "$_OR_";
- if (cell->type == "$xor") gate_type = "$_XOR_";
- if (cell->type == "$xnor") gate_type = "$_XOR_";
+ IdString gate_type;
+ if (cell->type == ID($and)) gate_type = ID($_AND_);
+ if (cell->type == ID($or)) gate_type = ID($_OR_);
+ if (cell->type == ID($xor)) gate_type = ID($_XOR_);
+ if (cell->type == ID($xnor)) gate_type = ID($_XOR_);
log_assert(!gate_type.empty());
for (int i = 0; i < GetSize(sig_y); i++) {
return;
if (sig_a.size() == 0) {
- if (cell->type == "$reduce_and") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
- if (cell->type == "$reduce_or") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
- if (cell->type == "$reduce_xor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
- if (cell->type == "$reduce_xnor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
- if (cell->type == "$reduce_bool") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+ if (cell->type == ID($reduce_and)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
+ if (cell->type == ID($reduce_or)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+ if (cell->type == ID($reduce_xor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+ if (cell->type == ID($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
+ if (cell->type == ID($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
return;
}
sig_y = sig_y.extract(0, 1);
}
- std::string gate_type;
- if (cell->type == "$reduce_and") gate_type = "$_AND_";
- if (cell->type == "$reduce_or") gate_type = "$_OR_";
- if (cell->type == "$reduce_xor") gate_type = "$_XOR_";
- if (cell->type == "$reduce_xnor") gate_type = "$_XOR_";
- if (cell->type == "$reduce_bool") gate_type = "$_OR_";
+ IdString gate_type;
+ if (cell->type == ID($reduce_and)) gate_type = ID($_AND_);
+ if (cell->type == ID($reduce_or)) gate_type = ID($_OR_);
+ if (cell->type == ID($reduce_xor)) gate_type = ID($_XOR_);
+ if (cell->type == ID($reduce_xnor)) gate_type = ID($_XOR_);
+ if (cell->type == ID($reduce_bool)) gate_type = ID($_OR_);
log_assert(!gate_type.empty());
RTLIL::Cell *last_output_cell = NULL;
sig_a = sig_t;
}
- if (cell->type == "$reduce_xnor") {
+ if (cell->type == ID($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
gate->setPort("\\A", sig_a);
gate->setPort("\\Y", sig_t);
continue;
}
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
gate->setPort("\\A", sig[i]);
gate->setPort("\\B", sig[i+1]);
sig_y = sig_y.extract(0, 1);
}
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
gate->setPort("\\A", sig_a);
gate->setPort("\\Y", sig_y);
sig_y = sig_y.extract(0, 1);
}
- std::string gate_type;
- if (cell->type == "$logic_and") gate_type = "$_AND_";
- if (cell->type == "$logic_or") gate_type = "$_OR_";
+ IdString gate_type;
+ if (cell->type == ID($logic_and)) gate_type = ID($_AND_);
+ if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
- bool is_ne = cell->type.in("$ne", "$nex");
+ bool is_ne = cell->type.in(ID($ne), ID($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
for (int i = 0; i < GetSize(sig_y); i++) {
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\B", sig_b[i]);
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
for (int i = 0; i < GetSize(sig_y); i++) {
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_TBUF_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\E", sig_e);
SigSpec sig_s = lut_ctrl[idx];
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) {
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
gate->setPort("\\A", lut_data[i]);
gate->setPort("\\B", lut_data[i+1]);
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
- std::string gate_type = "$_FF_";
+ IdString gate_type = ID($_FF_);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
- std::string gate_type = stringf("$_DFF_%c_", clk_pol);
+ IdString gate_type = stringf("$_DFF_%c_", clk_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
- std::string gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol);
+ IdString gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
- std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
+ IdString gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
- std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
- std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
+ IdString gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
+ IdString gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
- std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
+ IdString gate_type = stringf("$_DLATCH_%c_", en_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
{
- mappers["$not"] = simplemap_not;
- mappers["$pos"] = simplemap_pos;
- mappers["$and"] = simplemap_bitop;
- mappers["$or"] = simplemap_bitop;
- mappers["$xor"] = simplemap_bitop;
- mappers["$xnor"] = simplemap_bitop;
- mappers["$reduce_and"] = simplemap_reduce;
- mappers["$reduce_or"] = simplemap_reduce;
- mappers["$reduce_xor"] = simplemap_reduce;
- mappers["$reduce_xnor"] = simplemap_reduce;
- mappers["$reduce_bool"] = simplemap_reduce;
- mappers["$logic_not"] = simplemap_lognot;
- mappers["$logic_and"] = simplemap_logbin;
- mappers["$logic_or"] = simplemap_logbin;
- mappers["$eq"] = simplemap_eqne;
- mappers["$eqx"] = simplemap_eqne;
- mappers["$ne"] = simplemap_eqne;
- mappers["$nex"] = simplemap_eqne;
- mappers["$mux"] = simplemap_mux;
- mappers["$tribuf"] = simplemap_tribuf;
- mappers["$lut"] = simplemap_lut;
- mappers["$sop"] = simplemap_sop;
- mappers["$slice"] = simplemap_slice;
- mappers["$concat"] = simplemap_concat;
- mappers["$sr"] = simplemap_sr;
- mappers["$ff"] = simplemap_ff;
- mappers["$dff"] = simplemap_dff;
- mappers["$dffe"] = simplemap_dffe;
- mappers["$dffsr"] = simplemap_dffsr;
- mappers["$adff"] = simplemap_adff;
- mappers["$dlatch"] = simplemap_dlatch;
+ mappers[ID($not)] = simplemap_not;
+ mappers[ID($pos)] = simplemap_pos;
+ mappers[ID($and)] = simplemap_bitop;
+ mappers[ID($or)] = simplemap_bitop;
+ mappers[ID($xor)] = simplemap_bitop;
+ mappers[ID($xnor)] = simplemap_bitop;
+ mappers[ID($reduce_and)] = simplemap_reduce;
+ mappers[ID($reduce_or)] = simplemap_reduce;
+ mappers[ID($reduce_xor)] = simplemap_reduce;
+ mappers[ID($reduce_xnor)] = simplemap_reduce;
+ mappers[ID($reduce_bool)] = simplemap_reduce;
+ mappers[ID($logic_not)] = simplemap_lognot;
+ mappers[ID($logic_and)] = simplemap_logbin;
+ mappers[ID($logic_or)] = simplemap_logbin;
+ mappers[ID($eq)] = simplemap_eqne;
+ mappers[ID($eqx)] = simplemap_eqne;
+ mappers[ID($ne)] = simplemap_eqne;
+ mappers[ID($nex)] = simplemap_eqne;
+ mappers[ID($mux)] = simplemap_mux;
+ mappers[ID($tribuf)] = simplemap_tribuf;
+ mappers[ID($lut)] = simplemap_lut;
+ mappers[ID($sop)] = simplemap_sop;
+ mappers[ID($slice)] = simplemap_slice;
+ mappers[ID($concat)] = simplemap_concat;
+ mappers[ID($sr)] = simplemap_sr;
+ mappers[ID($ff)] = simplemap_ff;
+ mappers[ID($dff)] = simplemap_dff;
+ mappers[ID($dffe)] = simplemap_dffe;
+ mappers[ID($dffsr)] = simplemap_dffsr;
+ mappers[ID($adff)] = simplemap_adff;
+ mappers[ID($dlatch)] = simplemap_dlatch;
}
void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
port_signal_map.apply(it2.second);
}
- if (c->type.in("$memrd", "$memwr", "$meminit")) {
+ if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
IdString memid = c->getParam("\\MEMID").decode_string();
log_assert(memory_renames.count(memid) != 0);
c->setParam("\\MEMID", Const(memory_renames[memid].str()));
}
- if (c->type == "$mem") {
+ if (c->type == ID($mem)) {
string memid = c->getParam("\\MEMID").decode_string();
apply_prefix(cell->name.str(), memid);
c->setParam("\\MEMID", Const(memid));
if (extmapper_name == "maccmap") {
log("Creating %s with maccmap.\n", log_id(extmapper_module));
- if (extmapper_cell->type != "$macc")
+ if (extmapper_cell->type != ID($macc))
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
maccmap(extmapper_module, extmapper_cell);
extmapper_module->remove(extmapper_cell);
}
if (extmapper_name == "maccmap") {
- if (cell->type != "$macc")
+ if (cell->type != ID($macc))
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
maccmap(module, cell);
}
for (auto cell : module->selected_cells())
{
- if (cell->type == "$tribuf")
+ if (cell->type == ID($tribuf))
tribuf_cells[sigmap(cell->getPort("\\Y"))].push_back(cell);
- if (cell->type == "$_TBUF_")
+ if (cell->type == ID($_TBUF_))
tribuf_cells[sigmap(cell->getPort("\\Y"))].push_back(cell);
- if (cell->type.in("$mux", "$_MUX_"))
+ if (cell->type.in(ID($mux), ID($_MUX_)))
{
- IdString en_port = cell->type == "$mux" ? "\\EN" : "\\E";
- IdString tri_type = cell->type == "$mux" ? "$tribuf" : "$_TBUF_";
+ IdString en_port = cell->type == ID($mux) ? "\\EN" : "\\E";
+ IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_);
if (is_all_z(cell->getPort("\\A")) && is_all_z(cell->getPort("\\B"))) {
module->remove(cell);
SigSpec pmux_b, pmux_s;
for (auto cell : it.second) {
- if (cell->type == "$tribuf")
+ if (cell->type == ID($tribuf))
pmux_s.append(cell->getPort("\\EN"));
else
pmux_s.append(cell->getPort("\\E"));
}
pool<IdString> dff_types = {
- "$ff", "$dff", "$dffe", "$dffsr", "$adff",
- "$_FF_", "$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_",
- "$_DFFSR_NNN_", "$_DFFSR_NNP_", "$_DFFSR_NPN_", "$_DFFSR_NPP_",
- "$_DFFSR_PNN_", "$_DFFSR_PNP_", "$_DFFSR_PPN_", "$_DFFSR_PPP_",
- "$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
- "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_"
+ ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($adff),
+ ID($_FF_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_),
+ ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
+ ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),
+ ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)
};
for (auto cell : module->selected_cells())
projects / yosys.git / commitdiff