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Merge pull request #1623 from YosysHQ/mmicko/edif_attr
authorMiodrag Milanović <mmicko@gmail.com>
Tue, 14 Jan 2020 18:19:32 +0000 (19:19 +0100)
committerGitHub <noreply@github.com>
Tue, 14 Jan 2020 18:19:32 +0000 (19:19 +0100)
Export wire properties in EDIF

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techlibs/xilinx/synth_xilinx.cc patch | diff1 | diff2 | blob | history

diff --cc techlibs/xilinx/synth_xilinx.cc
Simple merge