Add OP_SETB

diff --git a/libreriscv b/libreriscv
index 8ce5c394da962ed012895b6ca464888e45b695b9..22a4261eb9cd3becf61b0ad6fa8268ae7ac55043 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 8ce5c394da962ed012895b6ca464888e45b695b9
+Subproject commit 22a4261eb9cd3becf61b0ad6fa8268ae7ac55043

diff --git a/src/soc/decoder/isa/sprset.patch b/src/soc/decoder/isa/sprset.patch
index afc0d7f20a6696b24fd93ffe182584a6a7b719b8..edbe55dcda22ac662d5d8204681461256c67cbee 100644 (file)
--- a/src/soc/decoder/isa/sprset.patch
+++ b/src/soc/decoder/isa/sprset.patch
@@ -1,5 +1,5 @@
---- sprset.py.orig     2020-05-16 14:04:43.548374778 -0400
-+++ sprset.py  2020-05-16 14:34:05.369303775 -0400
+--- sprset.py.orig     2020-05-20 09:27:57.035248195 -0400
++++ sprset.py  2020-05-28 11:02:47.754983231 -0400
 @@ -54,7 +54,7 @@
                  n = i
                  count = count + 1
@@ -18,3 +18,15 @@
          return (RT, CR,)
  
      @inject()
+@@ -88,9 +88,9 @@
+ 
+     @inject()
+     def op_setb(self, CR):
+-        if eq(CR[4 * BFA + 32], 1):
++        if eq(CR.si[4 * BFA + 32], 1):
+             RT = SelectableInt(value=0xffffffffffffffff, bits=256)
+-        elif eq(CR[4 * BFA + 33], 1):
++        elif eq(CR.si[4 * BFA + 33], 1):
+             RT = SelectableInt(value=0x1, bits=256)
+         else:
+             RT = SelectableInt(value=0x0, bits=256)

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index e5aa0321f9c2a1a90a46bf5b59cbd1f0b06a22f0..53bb2e0f5745e7c504f345ab8160539ed6bb09fc 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -300,7 +300,7 @@ class DecodeCRIn(Elaboratable):
                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
                 comb += self.cr_bitfield.ok.eq(1)
             with m.Case(CRInSel.BFA):
-                comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA[0:-1])
+                comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
                 comb += self.cr_bitfield.ok.eq(1)
             with m.Case(CRInSel.BA_BB):
                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index f3a5ee49433c623ec85ed70c8144fa02908a71ff..14828577495e1a1d76cb2097ddb83ec7825f4469 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -150,6 +150,15 @@ class CRMainStage(PipeModBase):
                 comb += rt_o.eq(Mux(cr_bit, a, b))
                 comb += rt_o.ok.eq(1) # indicate "INT reg changed"
 
+            with m.Case(InternalOp.OP_SETB):
+                with m.If(cr_a[3]):
+                    comb += rt_o.data.eq(-1)
+                with m.Elif(cr_a[2]):
+                    comb += rt_o.data.eq(1)
+                with m.Else():
+                    comb += rt_o.data.eq(0)
+                comb += rt_o.ok.eq(1)
+
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index afe7745c69a074677268f65ca93392e9e5c28112..0575357a3571329f34effa3f291459eb5e1e3e7e 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -123,6 +123,12 @@ class CRTestCase(FHDLTestCase):
             initial_regs[3] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst),
                                  initial_regs=initial_regs, initial_cr=cr)
+
+    def test_setb(self):
+        for i in range(20):
+            bfa = random.randint(0, 7)
+            lst = [f"setb 1, {bfa}"]
+            cr = random.randint(0, (1<<32)-1)
             self.run_tst_program(Program(lst), initial_cr=cr)