Panic over. Model was elsewhere. Re-arrange for consistency

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 1f5b1cb6bd2c81367ecd7418fb1f9db9787862c1..67d2f483c37a0eda60c4d8f77aac025b96d0b6a7 100644 (file)
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -311,6 +311,7 @@ struct SynthEcp5Pass : public ScriptPass
                        run("techmap " + techmap_args);
 
                        if (abc9) {
+                               run("read_verilog -icells -lib +/ecp5/abc_model.v");
                                if (nowidelut)
                                        run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
                                else

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 92a9956ea429f608ce6230cc2871c41b50665310..0fbca903496b8fa6f8478b702d767d91e6bec4b9 100644 (file)
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,7 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_model.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))

diff --git a/techlibs/ice40/abc_model.v b/techlibs/ice40/abc_model.v
index 8e18270434ed2c8058bd44ac05c57272c7418955..fe31b881108aea5cf5499c96d8103756aa250c33 100644 (file)
--- a/techlibs/ice40/abc_model.v
+++ b/techlibs/ice40/abc_model.v
@@ -25,5 +25,3 @@ module \$__ICE40_CARRY_WRAPPER (
                .O(O)
        );
 endmodule
-
-

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 8e5e0358e33e0d80b9a3f7616ab1a1cd688eef79..16a893226a039530e653a2fd3b41ea468578955d 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -145,34 +145,6 @@ module SB_CARRY (output CO, input I0, I1, CI);
        assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-(* abc_box_id = 1, lib_whitebox *)
-module \$__ICE40_CARRY_WRAPPER (
-       (* abc_carry *)
-       output CO,
-       output O,
-       input A, B,
-       (* abc_carry *)
-       input CI,
-       input I0, I3
-);
-       parameter LUT = 0;
-       SB_CARRY carry (
-               .I0(A),
-               .I1(B),
-               .CI(CI),
-               .CO(CO)
-       );
-       SB_LUT4 #(
-               .LUT_INIT(LUT)
-       ) adder (
-               .I0(I0),
-               .I1(A),
-               .I2(B),
-               .I3(I3),
-               .O(O)
-       );
-endmodule
-
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 //                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
 //                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 841f10244ad691838bf70a13e2bf7af5f0769100..2e4684c19a3f79ca312399749d1715a3616aa49a 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass
                                define = "-D ICE40_U";
                        else
                                define = "-D ICE40_HX";
-                       run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
+                       run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
                        run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
                        run("proc");
                }
@@ -349,6 +349,7 @@ struct SynthIce40Pass : public ScriptPass
                        }
                        if (!noabc) {
                                if (abc == "abc9") {
+                                       run("read_verilog -icells -lib +/ice40/abc_model.v");
                                        int wire_delay;
                                        if (device_opt == "lp")
                                                wire_delay = 400;