test: generate examples to verilog as part of unit tests.

This is to make sure 806a62c2 doesn't happen again.

diff --git a/examples/basic/arst.py b/examples/basic/arst.py
index ef3ed5a45afca0d7ab5ae14c0c3772bbc01ca05c..58b401536dd93ced9fe905c7fb28d0e1736cd41b 100644 (file)
--- a/examples/basic/arst.py
+++ b/examples/basic/arst.py
@@ -15,7 +15,7 @@ class ClockDivisor(Elaboratable):
 
 
 if __name__ == "__main__":
-    ctr = ClockDivisor(factor=16)
-    m = ctr.elaborate(platform=None)
-    m.domains += ClockDomain("sync", async_reset=True)
-    main(m, ports=[ctr.o])
+    m = Module()
+    m.domains.sync = sync = ClockDomain("sync", async_reset=True)
+    m.submodules.ctr = ctr = ClockDivisor(factor=16)
+    main(m, ports=[ctr.o, sync.clk])

diff --git a/nmigen/test/test_examples.py b/nmigen/test/test_examples.py
new file mode 100644 (file)
index 0000000..735731a
--- /dev/null
+++ b/nmigen/test/test_examples.py
@@ -0,0 +1,28 @@
+import sys
+import subprocess
+from pathlib import Path
+
+from .tools import *
+
+
+def example_test(name):
+    path = (Path(__file__).parent / ".." / ".." / "examples" / name).resolve()
+    def test_function(self):
+        subprocess.check_call([sys.executable, path, "generate"], stdout=subprocess.DEVNULL)
+    return test_function
+
+
+class ExamplesTestCase(FHDLTestCase):
+    test_alu        = example_test("basic/alu.py")
+    test_alu_hier   = example_test("basic/alu_hier.py")
+    test_arst       = example_test("basic/arst.py")
+    test_cdc        = example_test("basic/cdc.py")
+    test_ctr        = example_test("basic/ctr.py")
+    test_ctr_ce     = example_test("basic/ctr_ce.py")
+    test_fsm        = example_test("basic/fsm.py")
+    test_gpio       = example_test("basic/gpio.py")
+    test_inst       = example_test("basic/inst.py")
+    test_mem        = example_test("basic/mem.py")
+    test_pmux       = example_test("basic/pmux.py")
+    test_por        = example_test("basic/por.py")
+    test_uart       = example_test("basic/uart.py")