mem: Clarify unit of DRAM controller buffer size

diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index 642e9d525013463c2bb7af4d043a58851af235ee..74fb7c7be8cc0558c0537ae6e6d7d4405c7912be 100644 (file)
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -71,7 +71,10 @@ class DRAMCtrl(AbstractMemory):
     # bus in front of the controller for multiple ports
     port = SlavePort("Slave port")
 
-    # the basic configuration of the controller architecture
+    # the basic configuration of the controller architecture, note
+    # that each entry corresponds to a burst for the specific DRAM
+    # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
+    # the cacheline size or request/packet size
     write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
     read_buffer_size = Param.Unsigned(32, "Number of read queue entries")