build/xilinx/vivado: move build_script generation

diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 5331d44733d1d7c7f4483d6d0a45e9b1200fa64d..01e1aca58985b2585c9c14b603c5f34625eb56ea 100644 (file)
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -298,13 +298,11 @@ class XilinxVivadoToolchain:
         # Generate design constraints (.xdc)
         tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
 
-        # Generate build script
-        script = _build_script(build_name, toolchain_path, source)
-
         # Run
         if run:
             if synth_mode == "yosys":
                 common._run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
+            script = _build_script(build_name, toolchain_path, source)
             _run_script(script)
 
         os.chdir(cwd)