aco: Set +wavefrontsize64 for LLVM disassembler in GFX10 wave64 mode.
authorTimur Kristóf <timur.kristof@gmail.com>
Sat, 21 Sep 2019 15:58:08 +0000 (17:58 +0200)
committerTimur Kristóf <timur.kristof@gmail.com>
Thu, 10 Oct 2019 07:57:52 +0000 (09:57 +0200)
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
src/amd/compiler/aco_instruction_selection_setup.cpp
src/amd/compiler/aco_interface.cpp
src/amd/compiler/aco_ir.h
src/amd/compiler/aco_print_asm.cpp

index 7505707d4bb904e1358a94dfa5a7daab2c4f034a..06c697ccdc470c70726a510d19ee562d3964dfca 100644 (file)
@@ -1241,6 +1241,7 @@ setup_isel_context(Program* program,
    program->info = info;
    program->chip_class = options->chip_class;
    program->family = options->family;
+   program->wave_size = options->wave_size;
    program->sgpr_limit = options->chip_class >= GFX8 ? 102 : 104;
    if (options->family == CHIP_TONGA || options->family == CHIP_ICELAND)
       program->sgpr_limit = 94; /* workaround hardware bug */
index 79dd33385dcc6e5a93062f7849cb3e7b801f4c48..ad18101eb8e434f8ae5936cb7b9a71a1179729b2 100644 (file)
@@ -147,7 +147,7 @@ void aco_compile_shader(unsigned shader_count,
    std::string disasm;
    if (get_disasm) {
       std::ostringstream stream;
-      aco::print_asm(program.get(), code, exec_size / 4u, options->family, stream);
+      aco::print_asm(program.get(), code, exec_size / 4u, stream);
       stream << '\0';
       disasm = stream.str();
       size += disasm.size();
index 24ff6a2b142ed6d3761c3083c71373502e1fb178..ac2bfebbcf0a9b39611d3fc0688ba3025fcf2a60 100644 (file)
@@ -1069,6 +1069,7 @@ public:
    struct radv_shader_info *info;
    enum chip_class chip_class;
    enum radeon_family family;
+   unsigned wave_size;
    Stage stage; /* Stage */
    bool needs_exact = false; /* there exists an instruction with disable_wqm = true */
    bool needs_wqm = false; /* there exists a p_wqm instruction */
@@ -1141,8 +1142,8 @@ void spill(Program* program, live& live_vars, const struct radv_nir_compiler_opt
 void insert_wait_states(Program* program);
 void insert_NOPs(Program* program);
 unsigned emit_program(Program* program, std::vector<uint32_t>& code);
-void print_asm(Program *program, std::vector<uint32_t>& binary, unsigned exec_size,
-               enum radeon_family family, std::ostream& out);
+void print_asm(Program *program, std::vector<uint32_t>& binary,
+               unsigned exec_size, std::ostream& out);
 void validate(Program* program, FILE *output);
 bool validate_ra(Program* program, const struct radv_nir_compiler_options *options, FILE *output);
 #ifndef NDEBUG
index d3f4c3cb40d4c02bb91721a5504c22c4a921ca35..deb15a8b2563848e832dc1295a2815d8b7395e90 100644 (file)
@@ -9,7 +9,7 @@
 namespace aco {
 
 void print_asm(Program *program, std::vector<uint32_t>& binary,
-               unsigned exec_size, enum radeon_family family, std::ostream& out)
+               unsigned exec_size, std::ostream& out)
 {
    std::vector<bool> referenced_blocks(program->blocks.size());
    referenced_blocks[0] = true;
@@ -30,9 +30,15 @@ void print_asm(Program *program, std::vector<uint32_t>& binary,
       symbols.emplace_back(block.offset * 4, llvm::StringRef(block_names[block_names.size() - 1].data()), 0);
    }
 
-   LLVMDisasmContextRef disasm = LLVMCreateDisasmCPU("amdgcn-mesa-mesa3d",
-                                                     ac_get_llvm_processor_name(family),
-                                                     &symbols, 0, NULL, NULL);
+   const char *features = "";
+   if (program->chip_class >= GFX10 && program->wave_size == 64) {
+      features = "+wavefrontsize64";
+   }
+
+   LLVMDisasmContextRef disasm = LLVMCreateDisasmCPUFeatures("amdgcn-mesa-mesa3d",
+                                                             ac_get_llvm_processor_name(program->family),
+                                                             features,
+                                                             &symbols, 0, NULL, NULL);
 
    char outline[1024];
    size_t pos = 0;