program->info = info;
program->chip_class = options->chip_class;
program->family = options->family;
+ program->wave_size = options->wave_size;
program->sgpr_limit = options->chip_class >= GFX8 ? 102 : 104;
if (options->family == CHIP_TONGA || options->family == CHIP_ICELAND)
program->sgpr_limit = 94; /* workaround hardware bug */
std::string disasm;
if (get_disasm) {
std::ostringstream stream;
- aco::print_asm(program.get(), code, exec_size / 4u, options->family, stream);
+ aco::print_asm(program.get(), code, exec_size / 4u, stream);
stream << '\0';
disasm = stream.str();
size += disasm.size();
struct radv_shader_info *info;
enum chip_class chip_class;
enum radeon_family family;
+ unsigned wave_size;
Stage stage; /* Stage */
bool needs_exact = false; /* there exists an instruction with disable_wqm = true */
bool needs_wqm = false; /* there exists a p_wqm instruction */
void insert_wait_states(Program* program);
void insert_NOPs(Program* program);
unsigned emit_program(Program* program, std::vector<uint32_t>& code);
-void print_asm(Program *program, std::vector<uint32_t>& binary, unsigned exec_size,
- enum radeon_family family, std::ostream& out);
+void print_asm(Program *program, std::vector<uint32_t>& binary,
+ unsigned exec_size, std::ostream& out);
void validate(Program* program, FILE *output);
bool validate_ra(Program* program, const struct radv_nir_compiler_options *options, FILE *output);
#ifndef NDEBUG
namespace aco {
void print_asm(Program *program, std::vector<uint32_t>& binary,
- unsigned exec_size, enum radeon_family family, std::ostream& out)
+ unsigned exec_size, std::ostream& out)
{
std::vector<bool> referenced_blocks(program->blocks.size());
referenced_blocks[0] = true;
symbols.emplace_back(block.offset * 4, llvm::StringRef(block_names[block_names.size() - 1].data()), 0);
}
- LLVMDisasmContextRef disasm = LLVMCreateDisasmCPU("amdgcn-mesa-mesa3d",
- ac_get_llvm_processor_name(family),
- &symbols, 0, NULL, NULL);
+ const char *features = "";
+ if (program->chip_class >= GFX10 && program->wave_size == 64) {
+ features = "+wavefrontsize64";
+ }
+
+ LLVMDisasmContextRef disasm = LLVMCreateDisasmCPUFeatures("amdgcn-mesa-mesa3d",
+ ac_get_llvm_processor_name(program->family),
+ features,
+ &symbols, 0, NULL, NULL);
char outline[1024];
size_t pos = 0;