(no commit message)

diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn
index 94dbc23e9fceb2f95f96089d05f89409961007af..7a60e21c9b82c21b49fe323827076a8a05b3d0bc 100644 (file)
--- a/nlnet_2023_svp64_riscv.mdwn
+++ b/nlnet_2023_svp64_riscv.mdwn
@@ -54,7 +54,7 @@ EUR 100,000.
 
 Key phases of this project are:
 
-* Assessment of the missing RISC-V instructions (RISC-V RV64GC is only 96 instructions whereas POWER ISA SFFS is 214) which are present in Power ISA 3.0
+* Assessment of the missing RISC-V instructions (RISC-V RV64GC is only 96 instructions whereas POWER ISA SFFS is 214) which are present in Power ISA 3.0 and required to enable comparable performance from RISC-V with Simple-V/SVP64
 
 * Implementation of the missing RISC-V instructions and instruction forms that makes is comparable with POWER ISA in the Scalar ISA space.
 
@@ -74,7 +74,7 @@ Key phases of this project are:
 
 * Research and assessment of ARM7 and i486 (both on opencores.org)as to their feasibility for applying Simple-V Prefixing in future development projects
 
-
+By far the largest element of the budget is attributed to labour costs of the team involved from RED Semiconductor and LibreSOC - the project is entirely software-based and no additional hardware requirements are anticipated. A small budget of €5k is allocated to travel for key project review meetings, as the team is geographically dispersed.
 
 # Does the project have other funding sources, both past and present?