[AArch64] Add support for GMID_EL1 register for +memtag

We're missing support for the GMID_EL1 system register from the Memory Tagging Extension in binutils.
This is specified at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/gmid_el1

This simple patch adds the support for this read-only register.
Tested make check on gas.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 19ca4644061c2d1fe1612a33ccf4299d9339d247..3c363cc65b16a57bd01815e52a2fb76744af1bf7 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * testsuite/gas/aarch64/sysreg-4.s: Test gmid_el1 read.
+       * testsuite/gas/aarch64/sysreg-4.d: Update expected output.
+       * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
+
 2019-07-23  Alan Modra  <amodra@gmail.com>
 
        * config/obj-elf.c (obj_elf_change_section): Don't emit a fatal

diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
index d431f9bfc57a1292cb2221f708e63d4e9d2ec401..590f20e107010a2e531ec6d43b9d2da8fa2ac340 100644 (file)
--- a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
@@ -23,6 +23,7 @@
 [^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el12'
 [^:]*:[0-9]+: Error: selected processor does not support system register name 'rgsr_el1'
 [^:]*:[0-9]+: Error: selected processor does not support system register name 'gcr_el1'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'gmid_el1'
 [^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'tco'
 [^:]*:[0-9]+: Error: selected processor does not support system register name 'tco'
 [^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'tco'

diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d
index ab6e217fc1beb0d59744eab987e537430f128d57..bc3d0bdb7f5d497f1d0729b50f95446184cbb359 100644 (file)
--- a/gas/testsuite/gas/aarch64/sysreg-4.d
+++ b/gas/testsuite/gas/aarch64/sysreg-4.d
@@ -28,6 +28,7 @@ Disassembly of section \.text:
 .*:    d53d660c        mrs     x12, tfsr_el12
 .*:    d53810a1        mrs     x1, rgsr_el1
 .*:    d53810c3        mrs     x3, gcr_el1
+.*:    d5390084        mrs     x4, gmid_el1
 .*:    d51b42e1        msr     tco, x1
 .*:    d51b42e2        msr     tco, x2
 .*:    d5186621        msr     tfsre0_el1, x1

diff --git a/gas/testsuite/gas/aarch64/sysreg-4.s b/gas/testsuite/gas/aarch64/sysreg-4.s
index 6c18b4a4e402827b960b058b45cb538c8e48cbe8..ace9803081f3651e664353308c60de7f89dc988e 100644 (file)
--- a/gas/testsuite/gas/aarch64/sysreg-4.s
+++ b/gas/testsuite/gas/aarch64/sysreg-4.s
@@ -24,6 +24,7 @@ func:
        mrs x12, TFSR_EL12
        mrs x1, rgsr_el1
        mrs x3, gcr_el1
+       mrs x4, gmid_el1
 
        # MSR (register)
        msr tco, x1

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 491c5f50d31842e7e7d57a51519b86e0143c22c6..3402ddb2aad43ae86caa1417f4ee0546a65e8ec4 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
+       (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
+
 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 
        * arm-dis.c (is_mve_unpredictable): Stop marking some MVE

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 7ffec2d87517328f1b54d20e922da992b892e85b..a0085698181ae072a5a28e45afda44915ae6ae3f 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3973,6 +3973,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "tfsr_el12",       CPENC(3,5,C6,C6,0), F_ARCHEXT },
   { "rgsr_el1",                CPENC(3,0,C1,C0,5), F_ARCHEXT },
   { "gcr_el1",         CPENC(3,0,C1,C0,6), F_ARCHEXT },
+  { "gmid_el1",                CPENC(3,1,C0,C0,4), F_ARCHEXT | F_REG_READ }, /* RO */
   { "tpidr_el0",        CPENC(3,3,C13,C0,2),   0 },
   { "tpidrro_el0",      CPENC(3,3,C13,C0,3),   0 }, /* RW */
   { "tpidr_el1",        CPENC(3,0,C13,C0,4),   0 },
@@ -4444,7 +4445,8 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
        || reg->value == CPENC (3, 6, C6, C6, 0)
        || reg->value == CPENC (3, 5, C6, C6, 0)
        || reg->value == CPENC (3, 0, C1, C0, 5)
-       || reg->value == CPENC (3, 0, C1, C0, 6))
+       || reg->value == CPENC (3, 0, C1, C0, 6)
+       || reg->value == CPENC (3, 1, C0, C0, 4))
       && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
     return FALSE;