Added onehot attribute

diff --git a/README b/README
index 476e5ce5411fe8feb9286c885416b8f80b8480dc..fbd92db363fc3a794a5496644e8603dd7c378849 100644 (file)
--- a/README
+++ b/README
@@ -268,6 +268,9 @@ Verilog Attributes and non-standard features
   temporary variable within an always block. This is mostly used internally
   by yosys to synthesize verilog functions and access arrays.
 
+- The "onehot" attribute on wires mark them as onehot state register. This
+  is used for example for memory port sharing and set by the fsm_map pass.
+
 - The "blackbox" attribute on modules is used to mark empty stub modules
   that have the same ports as the real thing but do not contain information
   on the internal configuration. This modules are only used by the synthesis

diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index a260653fbcf29ce26a92bfe419636425b8d1c6b9..155801a3a4365dcb49dc2e92d2b7f92930fd9fe5 100644 (file)
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -224,6 +224,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
                }
        }
 
+       if (encoding_is_onehot)
+               state_wire->set_bool_attribute("\\onehot");
+
        // generate next_state signal
 
        if (GetSize(fsm_data.state_table) == 1)

diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index ec8df75989c1ad4f0c47115ff8f423cdbf9d6935..a2f89f6d9e0895cc675e21f760165f9a0febbc94 100644 (file)
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -544,6 +544,7 @@ struct MemoryShareWorker
 
                // create SAT representation of common input cone of all considered EN signals
 
+               pool<Wire*> one_hot_wires;
                std::set<RTLIL::Cell*> sat_cells;
                std::set<RTLIL::SigBit> bits_queue;
                std::map<int, int> port_to_sat_variable;
@@ -560,6 +561,10 @@ struct MemoryShareWorker
 
                while (!bits_queue.empty())
                {
+                       for (auto bit : bits_queue)
+                               if (bit.wire && bit.wire->get_bool_attribute("\\onehot"))
+                                       one_hot_wires.insert(bit.wire);
+
                        pool<ModWalker::PortBit> portbits;
                        modwalker.get_drivers(portbits, bits_queue);
                        bits_queue.clear();
@@ -572,6 +577,14 @@ struct MemoryShareWorker
                                }
                }
 
+               for (auto wire : one_hot_wires) {
+                       log("  Adding one-hot constraint for wire %s.\n", log_id(wire));
+                       vector<int> ez_wire_bits = satgen.importSigSpec(wire);
+                       for (int i : ez_wire_bits)
+                       for (int j : ez_wire_bits)
+                               if (i != j) ez.assume(ez.NOT(i), j);
+               }
+
                log("  Common input cone for all EN signals: %d cells.\n", int(sat_cells.size()));
 
                for (auto cell : sat_cells)