Fix formal support in FHDLTestCase

diff --git a/gram/test/utils.py b/gram/test/utils.py
index 6b4ad4c66cbb620436369f52d7f7a1216413824d..67124296d3ca276ab4022a7782a2702dfe14b285 100644 (file)
--- a/gram/test/utils.py
+++ b/gram/test/utils.py
@@ -92,7 +92,6 @@ class FHDLTestCase(unittest.TestCase):
         """).format(
             mode=mode,
             depth=depth,
-            script=script,
             rtlil=rtlil.convert(Fragment.get(spec, platform="formal"))
         )
         with subprocess.Popen([require_tool("sby"), "-f", "-d", spec_name],