+2010-01-14 Andi Kleen <ak@linux.intel.com>
+
+ * config/i386/drivers-i386.c (detect_caches_intel):
+ Add l2sizekb parameter and fill in.
+ (host_detect_local_cpu): Add l2sizekb, fill in.
+ Add Atom small cache heuristic.
+
+2010-01-14 Andi Kleen <ak@linux.intel.com>
+
+ * config/i386/drivers-i386.c (detect_caches_cpuid4):
+ Add level3 parameter and fill in.
+ (detect_caches_intel): Handle level3 cache.
+
+2010-01-14 Andi Kleen <ak@linux.intel.com>
+
+ * config/i386/drivers-i386.c (host_detect_local_cpu):
+ Fix core duo detection.
+
+2010-01-14 Andi Kleen <ak@linux.intel.com>
+
+ * config/i386/drivers-i386.c (host_detect_local_cpu):
+ Fix Atom detection.
+
2010-01-14 Alexander Monakov <amonakov@ispras.ru>
* config/rs6000/rs6000.c (rs6000_variable_issue): Rename to...
2010-01-14 Alexander Monakov <amonakov@ispras.ru>
- * sel-sched-ir.c (sel_restore_other_notes): Rename to sel_restore_notes.
- Update all callers. Call reemit_notes for all insns.
+ * sel-sched-ir.c (sel_restore_other_notes): Rename to
+ sel_restore_notes. Update all callers. Call reemit_notes
+ for all insns.
2010-01-14 Andrey Belevantsev <abel@ispras.ru>
2010-01-14 Jakub Jelinek <jakub@redhat.com>
PR c/42721
- Port from no-undefined-overflow branch
+ Port from no-undefined-overflow branch:
2009-03-09 Richard Guenther <rguenther@suse.de>
- * fold-const.c (add_double_with_sign): Fix unsigned overflow
- detection.
+ * fold-const.c (add_double_with_sign): Fix unsigned overflow detection.
2010-01-14 Richard Guenther <rguenther@suse.de>
2010-01-12 Julian Brown <julian@codesourcery.com>
- * config/arm/neon-schedgen.ml (Utils): Don't try to
+ * config/arm/neon-schedgen.ml (Utils): Don't try to
open missing module.
- (find_with_result): New.
+ (find_with_result): New.
2010-01-12 Jakub Jelinek <jakub@redhat.com>
2010-01-11 Andy Hutchinson <hutchinsonandy@gcc.gnu.org>
- * config/avr/avr.h (LINKER_NAME): Remove.
+ * config/avr/avr.h (LINKER_NAME): Remove.
2010-01-11 Janis Johnson <janis187@us.ibm.com>
2010-01-11 Joseph Myers <joseph@codesourcery.com>
Shujing Zhao <pearly.zhao@oracle.com>
-
+
PR translation/42469
* common.opt (Wframe-larger-than=, fcompare-debug=, fdbg-cnt=,
fira-verbose=, flto-compression-level=, fplugin-arg-): Use tab
(*rotw<mode>3): New.
(*rotb<mode>3): New.
* config/avr/avr.c (avr_rotate_bytes): New function.
- * config/avr/avr-proto.h (avr_rotate_bytes): New function.
+ * config/avr/avr-proto.h (avr_rotate_bytes): New function.
2010-01-08 Steve Ellcey <sje@cup.hp.com>
(concat_note_lists): ... here, and ...
(unlink_other_notes, rm_other_notes): Merge into...
(remove_notes): ... here. Create REG_SAVE_NOTEs for
- NOTE_INSN_EPILOGUE_BEG.
+ NOTE_INSN_EPILOGUE_BEG.
2010-01-06 Richard Guenther <rguenther@suse.de>
};
static void
-detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2)
+detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
+ struct cache_desc *level3)
{
struct cache_desc *cache;
case 2:
cache = level2;
break;
+ case 3:
+ cache = level3;
+ break;
default:
cache = NULL;
}
cache->sizekb = (cache->assoc * part
* cache->line * sets) / 1024;
- }
+ }
}
default:
break;
/* Returns the description of caches for an Intel processor. */
static const char *
-detect_caches_intel (bool xeon_mp, unsigned max_level, unsigned max_ext_level)
+detect_caches_intel (bool xeon_mp, unsigned max_level,
+ unsigned max_ext_level, unsigned *l2sizekb)
{
- struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0};
+ struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
if (max_level >= 4)
- detect_caches_cpuid4 (&level1, &level2);
+ detect_caches_cpuid4 (&level1, &level2, &level3);
else if (max_level >= 2)
detect_caches_cpuid2 (xeon_mp, &level1, &level2);
else
if (level1.sizekb == 0)
return "";
+ /* Let the L3 replace the L2. This assumes inclusive caches
+ and single threaded program for now. */
+ if (level3.sizekb)
+ level2 = level3;
+
/* Intel CPUs are equipped with AMD style L2 cache info. Try this
method if other methods fail to provide L2 cache parameters. */
if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
detect_l2_cache (&level2);
+ *l2sizekb = level2.sizekb;
+
return describe_cache (level1, level2);
}
bool arch;
+ unsigned int l2sizekb = 0;
+
if (argc < 1)
return NULL;
else if (vendor == SIG_INTEL)
{
bool xeon_mp = (family == 15 && model == 6);
- cache = detect_caches_intel (xeon_mp, max_level, ext_level);
+ cache = detect_caches_intel (xeon_mp, max_level,
+ ext_level, &l2sizekb);
}
}
cpu = "pentium";
break;
case PROCESSOR_PENTIUMPRO:
- if (has_longmode)
- /* It is Core 2 or Atom. */
- cpu = (model == 28) ? "atom" : "core2";
+ if (model == 28)
+ cpu = "atom";
+ else if (model >= 28 && l2sizekb < 2048)
+ /* Assume it's a small core if there's less than 2MB cache */
+ cpu = "atom";
+ else if (has_longmode)
+ cpu = "core2";
else if (arch)
{
if (has_sse3)
/* It is Core Duo. */
- cpu = "prescott";
+ cpu = "pentium-m";
else if (has_sse2)
/* It is Pentium M. */
cpu = "pentium-m";
2010-01-14 Alexander Monakov <amonakov@ispras.ru>
- PR rtl-optimization/42249
- * gcc.dg/pr42249.c: New.
+ PR rtl-optimization/42249
+ * gcc.dg/pr42249.c: New.
2010-01-14 Jakub Jelinek <jakub@redhat.com>
2010-01-14 Paul Thomas <pault@gcc.gnu.org>
- PR fortran/41478
- * gfortran.dg/alloc_comp_scalar_1.f90: New test.
- * gfortran.dg/alloc_comp_transformational_1.f90: New test.
+ PR fortran/41478
+ * gfortran.dg/alloc_comp_scalar_1.f90: New test.
+ * gfortran.dg/alloc_comp_transformational_1.f90: New test.
2010-01-14 Paul Thomas <pault@gcc.gnu.org>
projects / gcc.git / commitdiff