vexriscv: Fix some floating signals

Signed-off-by: David Shah <dave@ds0.me>

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index e40a2d38e8aa8e4b851d3880c2bb807e7d566092..de30de8d5423c414740c86e5ac31727bfe9448e8 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -126,6 +126,9 @@ class VexRiscv(Module, AutoCSR):
                 i_dBusWishbone_ERR=dbus.err)
 
         if "linux" in variant:
+            # Tie zero to prevent 1'bx here
+            self.cpu_params["i_softwareInterrupt"] = 0
+            self.cpu_params["i_externalInterruptS"] = 0
             self.add_timer()
 
         if "debug" in variant: