+++ /dev/null
-bram_init_1_2_4.vh
-bram_init_9_18_36.vh
-brams_init.mk
-bram_conn_1.vh
-bram_conn_2.vh
-bram_conn_4.vh
-bram_conn_9.vh
-bram_conn_18.vh
-bram_conn_36.vh
-brams_connect.mk
OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o
-GENFILES += techlibs/ecp5/bram_init_1_2_4.vh
-GENFILES += techlibs/ecp5/bram_init_9_18_36.vh
-GENFILES += techlibs/ecp5/bram_conn_1.vh
-GENFILES += techlibs/ecp5/bram_conn_2.vh
-GENFILES += techlibs/ecp5/bram_conn_4.vh
-GENFILES += techlibs/ecp5/bram_conn_9.vh
-GENFILES += techlibs/ecp5/bram_conn_18.vh
-GENFILES += techlibs/ecp5/bram_conn_36.vh
-
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
-
-EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
-.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
-
-techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py
- $(Q) mkdir -p techlibs/ecp5
- $(P) $(PYTHON_EXECUTABLE) $<
- $(Q) touch $@
-
-techlibs/ecp5/brams_connect.mk: techlibs/ecp5/brams_connect.py
- $(Q) mkdir -p techlibs/ecp5
- $(P) $(PYTHON_EXECUTABLE) $<
- $(Q) touch $@
-
-
-techlibs/ecp5/bram_init_1_2_4.vh: techlibs/ecp5/brams_init.mk
-techlibs/ecp5/bram_init_9_18_36.vh: techlibs/ecp5/brams_init.mk
-
-techlibs/ecp5/bram_conn_1.vh: techlibs/ecp5/brams_connect.mk
-techlibs/ecp5/bram_conn_2.vh: techlibs/ecp5/brams_connect.mk
-techlibs/ecp5/bram_conn_4.vh: techlibs/ecp5/brams_connect.mk
-techlibs/ecp5/bram_conn_9.vh: techlibs/ecp5/brams_connect.mk
-techlibs/ecp5/bram_conn_18.vh: techlibs/ecp5/brams_connect.mk
-techlibs/ecp5/bram_conn_36.vh: techlibs/ecp5/brams_connect.mk
-
-$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
-$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
-
-$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_1.vh))
-$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh))
-$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh))
-$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh))
-$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh))
-$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_36.vh))
-bram $__ECP5_PDPW16KD
- init 1
-
- abits 9
- dbits 36
-
- groups 2
- ports 1 1
- wrmode 1 0
- enable 4 1
- transp 0 0
- clocks 2 3
- clkpol 2 3
-endbram
-
-bram $__ECP5_DP16KD
- init 1
-
- abits 10 @a10d18
- dbits 18 @a10d18
- abits 11 @a11d9
- dbits 9 @a11d9
- abits 12 @a12d4
- dbits 4 @a12d4
- abits 13 @a13d2
- dbits 2 @a13d2
- abits 14 @a14d1
- dbits 1 @a14d1
-
- groups 2
- ports 1 1
- wrmode 1 0
- enable 2 1 @a10d18
- enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
- transp 0 2
- clocks 2 3
- clkpol 2 3
-endbram
-
-# The syn_* attributes are described in:
-# https://www.latticesemi.com/view_document?document_id=51556
-attr_icase 1
-
-match $__ECP5_PDPW16KD
- # implicitly requested RAM or ROM
- attribute !syn_ramstyle syn_ramstyle=auto
- attribute !syn_romstyle syn_romstyle=auto
- attribute !ram_block
- attribute !rom_block
- attribute !logic_block
- min bits 2048
- min efficiency 5
- shuffle_enable A
- make_transp
- or_next_if_better
-endmatch
-
-match $__ECP5_PDPW16KD
- # explicitly requested RAM
- attribute syn_ramstyle=block_ram ram_block
- attribute !syn_romstyle
- attribute !rom_block
- attribute !logic_block
- min wports 1
- shuffle_enable A
- make_transp
- or_next_if_better
-endmatch
-
-match $__ECP5_PDPW16KD
- # explicitly requested ROM
- attribute syn_romstyle=ebr rom_block
- attribute !syn_ramstyle
- attribute !ram_block
- attribute !logic_block
- max wports 0
- shuffle_enable A
- make_transp
- or_next_if_better
-endmatch
-
-match $__ECP5_DP16KD
- # implicitly requested RAM or ROM
- attribute !syn_ramstyle syn_ramstyle=auto
- attribute !syn_romstyle syn_romstyle=auto
- attribute !ram_block
- attribute !rom_block
- attribute !logic_block
- min bits 2048
- min efficiency 5
- shuffle_enable A
- or_next_if_better
-endmatch
-
-match $__ECP5_DP16KD
- # explicitly requested RAM
- attribute syn_ramstyle=block_ram ram_block
- attribute !syn_romstyle
- attribute !rom_block
- attribute !logic_block
- min wports 1
- shuffle_enable A
- or_next_if_better
-endmatch
-
-match $__ECP5_DP16KD
- # explicitly requested ROM
- attribute syn_romstyle=ebr rom_block
- attribute !syn_ramstyle
- attribute !ram_block
- attribute !logic_block
- max wports 0
- shuffle_enable A
-endmatch
+ram block $__ECP5_DP16KD_ {
+ abits 14;
+ widths 1 2 4 9 18 per_port;
+ byte 9;
+ cost 128;
+ init no_undef;
+ port srsw "A" "B" {
+ clock anyedge;
+ clken;
+ wrbe_separate;
+ portoption "WRITEMODE" "NORMAL" {
+ rdwr no_change;
+ }
+ portoption "WRITEMODE" "WRITETHROUGH" {
+ rdwr new;
+ }
+ portoption "WRITEMODE" "READBEFOREWRITE" {
+ rdwr old;
+ }
+ option "RESETMODE" "SYNC" {
+ rdsrst zero ungated block_wr;
+ }
+ option "RESETMODE" "ASYNC" {
+ rdarst zero;
+ }
+ rdinit zero;
+ }
+}
+
+ram block $__ECP5_PDPW16KD_ {
+ abits 14;
+ widths 1 2 4 9 18 36 per_port;
+ byte 9;
+ cost 128;
+ init no_undef;
+ port sr "R" {
+ clock anyedge;
+ clken;
+ option "RESETMODE" "SYNC" {
+ rdsrst zero ungated;
+ }
+ option "RESETMODE" "ASYNC" {
+ rdarst zero;
+ }
+ rdinit zero;
+ }
+ port sw "W" {
+ width 36;
+ clock anyedge;
+ clken;
+ }
+}
+++ /dev/null
-#!/usr/bin/env python3
-
-def write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits):
- ada_conn = [".ADA%d(%s)" % (i, ada_bits[i]) for i in range(len(ada_bits))]
- adb_conn = [".ADB%d(%s)" % (i, adb_bits[i]) for i in range(len(adb_bits))]
- dia_conn = [".DIA%d(%s)" % (i, dia_bits[i]) for i in range(len(dia_bits))]
- dob_conn = [".DOB%d(%s)" % (i, dob_bits[i]) for i in range(len(dob_bits))]
- print(" %s," % ", ".join(ada_conn), file=f)
- print(" %s," % ", ".join(adb_conn), file=f)
- print(" %s," % ", ".join(dia_conn), file=f)
- print(" %s," % ", ".join(dob_conn), file=f)
-
-def write_bus_ports_pdp(f, adw_bits, adr_bits, di_bits, do_bits, be_bits):
- adw_conn = [".ADW%d(%s)" % (i, adw_bits[i]) for i in range(len(adw_bits))]
- adr_conn = [".ADR%d(%s)" % (i, adr_bits[i]) for i in range(len(adr_bits))]
- di_conn = [".DI%d(%s)" % (i, di_bits[i]) for i in range(len(di_bits))]
- do_conn = [".DO%d(%s)" % (i, do_bits[i]) for i in range(len(do_bits))]
- be_conn = [".BE%d(%s)" % (i, be_bits[i]) for i in range(len(be_bits))]
- print(" %s," % ", ".join(adw_conn), file=f)
- print(" %s," % ", ".join(adr_conn), file=f)
- print(" %s," % ", ".join(di_conn), file=f)
- print(" %s," % ", ".join(do_conn), file=f)
- print(" %s," % ", ".join(be_conn), file=f)
-
-with open("techlibs/ecp5/bram_conn_1.vh", "w") as f:
- ada_bits = ["A1ADDR[%d]" % i for i in range(14)]
- adb_bits = ["B1ADDR[%d]" % i for i in range(14)]
- dia_bits = ["A1DATA[0]"] + ["1'b0" for i in range(17)]
- dob_bits = ["B1DATA[0]"]
- write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
-
-with open("techlibs/ecp5/bram_conn_2.vh", "w") as f:
- ada_bits = ["1'b0"] + ["A1ADDR[%d]" % i for i in range(13)]
- adb_bits = ["1'b0"] + ["B1ADDR[%d]" % i for i in range(13)]
- dia_bits = ["A1DATA[%d]" % i for i in range(2)] + ["1'b0" for i in range(16)]
- dob_bits = ["B1DATA[%d]" % i for i in range(2)]
- write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
-
-with open("techlibs/ecp5/bram_conn_4.vh", "w") as f:
- ada_bits = ["1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(12)]
- adb_bits = ["1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(12)]
- dia_bits = ["A1DATA[%d]" % i for i in range(4)] + ["1'b0" for i in range(14)]
- dob_bits = ["B1DATA[%d]" % i for i in range(4)]
- write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
-
-with open("techlibs/ecp5/bram_conn_9.vh", "w") as f:
- ada_bits = ["1'b0", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(11)]
- adb_bits = ["1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(11)]
- dia_bits = ["A1DATA[%d]" % i for i in range(9)] + ["1'b0" for i in range(9)]
- dob_bits = ["B1DATA[%d]" % i for i in range(9)]
- write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
-
-with open("techlibs/ecp5/bram_conn_18.vh", "w") as f:
- ada_bits = ["A1EN[0]", "A1EN[1]", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(10)]
- adb_bits = ["1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(10)]
- dia_bits = ["A1DATA[%d]" % i for i in range(18)]
- dob_bits = ["B1DATA[%d]" % i for i in range(18)]
- write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
-
-with open("techlibs/ecp5/bram_conn_36.vh", "w") as f:
- adw_bits = ["A1ADDR[%d]" % i for i in range(9)]
- adr_bits = ["1'b0", "1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(9)]
- di_bits = ["A1DATA[%d]" % i for i in range(36)]
- do_bits = ["B1DATA[%d]" % (i + 18) for i in range(18)] + ["B1DATA[%d]" % i for i in range(18)]
- be_bits = ["A1EN[%d]" % i for i in range(4)]
- write_bus_ports_pdp(f, adw_bits, adr_bits, di_bits, do_bits, be_bits)
+++ /dev/null
-#!/usr/bin/env python3
-with open("techlibs/ecp5/bram_init_1_2_4.vh", "w") as f:
- for i in range(0, 0x40):
- init_snippets = []
- for j in range(32):
- init_snippets.append("INIT[%4d*8 +: 8]" % (32 * i + j))
- init_snippets.append("3'b000" if (j % 2 == 1) else "1'b0")
- init_snippets = list(reversed(init_snippets))
- for k in range(8, 64, 8):
- init_snippets[k] = "\n " + init_snippets[k]
- print(".INITVAL_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
-
-with open("techlibs/ecp5/bram_init_9_18_36.vh", "w") as f:
- for i in range(0, 0x40):
- init_snippets = []
- for j in range(16):
- init_snippets.append("INIT[%3d*18 +: 18]" % (16 * i + j))
- init_snippets.append("2'b00")
- init_snippets = list(reversed(init_snippets))
- for k in range(8, 32, 8):
- init_snippets[k] = "\n " + init_snippets[k]
- print(".INITVAL_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
-module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
- parameter CFG_ABITS = 10;
- parameter CFG_DBITS = 18;
- parameter CFG_ENABLE_A = 2;
-
- parameter CLKPOL2 = 1;
- parameter CLKPOL3 = 1;
- parameter [18431:0] INIT = 18432'bx;
- parameter TRANSP2 = 0;
-
- input CLK2;
- input CLK3;
-
- input [CFG_ABITS-1:0] A1ADDR;
- input [CFG_DBITS-1:0] A1DATA;
- input [CFG_ENABLE_A-1:0] A1EN;
-
- input [CFG_ABITS-1:0] B1ADDR;
- output [CFG_DBITS-1:0] B1DATA;
- input B1EN;
-
- localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV";
- localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV";
-
- localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
-
- generate if (CFG_DBITS == 1) begin
- DP16KD #(
- `include "bram_init_1_2_4.vh"
- .DATA_WIDTH_A(1),
- .DATA_WIDTH_B(1),
- .CLKAMUX(CLKAMUX),
- .CLKBMUX(CLKBMUX),
- .WRITEMODE_A(WRITEMODE_A),
- .WRITEMODE_B("READBEFOREWRITE"),
- .GSR("AUTO")
- ) _TECHMAP_REPLACE_ (
- `include "bram_conn_1.vh"
- .CLKA(CLK2), .CLKB(CLK3),
- .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
- .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
- .RSTA(1'b0), .RSTB(1'b0)
- );
- end else if (CFG_DBITS == 2) begin
- DP16KD #(
- `include "bram_init_1_2_4.vh"
- .DATA_WIDTH_A(2),
- .DATA_WIDTH_B(2),
- .CLKAMUX(CLKAMUX),
- .CLKBMUX(CLKBMUX),
- .WRITEMODE_A(WRITEMODE_A),
- .WRITEMODE_B("READBEFOREWRITE"),
- .GSR("AUTO")
- ) _TECHMAP_REPLACE_ (
- `include "bram_conn_2.vh"
- .CLKA(CLK2), .CLKB(CLK3),
- .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
- .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
- .RSTA(1'b0), .RSTB(1'b0)
- );
- end else if (CFG_DBITS <= 4) begin
- DP16KD #(
- `include "bram_init_1_2_4.vh"
- .DATA_WIDTH_A(4),
- .DATA_WIDTH_B(4),
- .CLKAMUX(CLKAMUX),
- .CLKBMUX(CLKBMUX),
- .WRITEMODE_A(WRITEMODE_A),
- .WRITEMODE_B("READBEFOREWRITE"),
- .GSR("AUTO")
- ) _TECHMAP_REPLACE_ (
- `include "bram_conn_4.vh"
- .CLKA(CLK2), .CLKB(CLK3),
- .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
- .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
- .RSTA(1'b0), .RSTB(1'b0)
- );
- end else if (CFG_DBITS <= 9) begin
- DP16KD #(
- `include "bram_init_9_18_36.vh"
- .DATA_WIDTH_A(9),
- .DATA_WIDTH_B(9),
- .CLKAMUX(CLKAMUX),
- .CLKBMUX(CLKBMUX),
- .WRITEMODE_A(WRITEMODE_A),
- .WRITEMODE_B("READBEFOREWRITE"),
- .GSR("AUTO")
- ) _TECHMAP_REPLACE_ (
- `include "bram_conn_9.vh"
- .CLKA(CLK2), .CLKB(CLK3),
- .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
- .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
- .RSTA(1'b0), .RSTB(1'b0)
- );
- end else if (CFG_DBITS <= 18) begin
- DP16KD #(
- `include "bram_init_9_18_36.vh"
- .DATA_WIDTH_A(18),
- .DATA_WIDTH_B(18),
- .CLKAMUX(CLKAMUX),
- .CLKBMUX(CLKBMUX),
- .WRITEMODE_A(WRITEMODE_A),
- .WRITEMODE_B("READBEFOREWRITE"),
- .GSR("AUTO")
- ) _TECHMAP_REPLACE_ (
- `include "bram_conn_18.vh"
- .CLKA(CLK2), .CLKB(CLK3),
- .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
- .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
- .RSTA(1'b0), .RSTB(1'b0)
- );
- end else begin
- wire TECHMAP_FAIL = 1'b1;
- end endgenerate
+module $__ECP5_DP16KD_ (...);
+
+parameter INIT = 0;
+parameter OPTION_RESETMODE = "SYNC";
+
+parameter PORT_A_WIDTH = 18;
+parameter PORT_A_WR_BE_WIDTH = 2;
+parameter PORT_A_CLK_POL = 1;
+parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
+
+input PORT_A_CLK;
+input PORT_A_CLK_EN;
+input PORT_A_WR_EN;
+input PORT_A_RD_SRST;
+input PORT_A_RD_ARST;
+input [13:0] PORT_A_ADDR;
+input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
+input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
+output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
+
+parameter PORT_B_WIDTH = 18;
+parameter PORT_B_WR_BE_WIDTH = 2;
+parameter PORT_B_CLK_POL = 1;
+parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
+
+input PORT_B_CLK;
+input PORT_B_CLK_EN;
+input PORT_B_WR_EN;
+input PORT_B_RD_SRST;
+input PORT_B_RD_ARST;
+input [13:0] PORT_B_ADDR;
+input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
+input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
+output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
+
+function [319:0] init_slice;
+ input integer idx;
+ integer i, j;
+ init_slice = 0;
+ for (i = 0; i < 16; i = i + 1) begin
+ init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
+ end
+endfunction
+
+wire [17:0] DOA;
+wire [17:0] DOB;
+wire [17:0] DIA = PORT_A_WR_DATA;
+wire [17:0] DIB = PORT_B_WR_DATA;
+
+assign PORT_A_RD_DATA = DOA;
+assign PORT_B_RD_DATA = DOB;
+
+DP16KD #(
+ .INITVAL_00(init_slice('h00)),
+ .INITVAL_01(init_slice('h01)),
+ .INITVAL_02(init_slice('h02)),
+ .INITVAL_03(init_slice('h03)),
+ .INITVAL_04(init_slice('h04)),
+ .INITVAL_05(init_slice('h05)),
+ .INITVAL_06(init_slice('h06)),
+ .INITVAL_07(init_slice('h07)),
+ .INITVAL_08(init_slice('h08)),
+ .INITVAL_09(init_slice('h09)),
+ .INITVAL_0A(init_slice('h0a)),
+ .INITVAL_0B(init_slice('h0b)),
+ .INITVAL_0C(init_slice('h0c)),
+ .INITVAL_0D(init_slice('h0d)),
+ .INITVAL_0E(init_slice('h0e)),
+ .INITVAL_0F(init_slice('h0f)),
+ .INITVAL_10(init_slice('h10)),
+ .INITVAL_11(init_slice('h11)),
+ .INITVAL_12(init_slice('h12)),
+ .INITVAL_13(init_slice('h13)),
+ .INITVAL_14(init_slice('h14)),
+ .INITVAL_15(init_slice('h15)),
+ .INITVAL_16(init_slice('h16)),
+ .INITVAL_17(init_slice('h17)),
+ .INITVAL_18(init_slice('h18)),
+ .INITVAL_19(init_slice('h19)),
+ .INITVAL_1A(init_slice('h1a)),
+ .INITVAL_1B(init_slice('h1b)),
+ .INITVAL_1C(init_slice('h1c)),
+ .INITVAL_1D(init_slice('h1d)),
+ .INITVAL_1E(init_slice('h1e)),
+ .INITVAL_1F(init_slice('h1f)),
+ .INITVAL_20(init_slice('h20)),
+ .INITVAL_21(init_slice('h21)),
+ .INITVAL_22(init_slice('h22)),
+ .INITVAL_23(init_slice('h23)),
+ .INITVAL_24(init_slice('h24)),
+ .INITVAL_25(init_slice('h25)),
+ .INITVAL_26(init_slice('h26)),
+ .INITVAL_27(init_slice('h27)),
+ .INITVAL_28(init_slice('h28)),
+ .INITVAL_29(init_slice('h29)),
+ .INITVAL_2A(init_slice('h2a)),
+ .INITVAL_2B(init_slice('h2b)),
+ .INITVAL_2C(init_slice('h2c)),
+ .INITVAL_2D(init_slice('h2d)),
+ .INITVAL_2E(init_slice('h2e)),
+ .INITVAL_2F(init_slice('h2f)),
+ .INITVAL_30(init_slice('h30)),
+ .INITVAL_31(init_slice('h31)),
+ .INITVAL_32(init_slice('h32)),
+ .INITVAL_33(init_slice('h33)),
+ .INITVAL_34(init_slice('h34)),
+ .INITVAL_35(init_slice('h35)),
+ .INITVAL_36(init_slice('h36)),
+ .INITVAL_37(init_slice('h37)),
+ .INITVAL_38(init_slice('h38)),
+ .INITVAL_39(init_slice('h39)),
+ .INITVAL_3A(init_slice('h3a)),
+ .INITVAL_3B(init_slice('h3b)),
+ .INITVAL_3C(init_slice('h3c)),
+ .INITVAL_3D(init_slice('h3d)),
+ .INITVAL_3E(init_slice('h3e)),
+ .INITVAL_3F(init_slice('h3f)),
+ .DATA_WIDTH_A(PORT_A_WIDTH),
+ .DATA_WIDTH_B(PORT_B_WIDTH),
+ .REGMODE_A("NOREG"),
+ .REGMODE_B("NOREG"),
+ .RESETMODE(OPTION_RESETMODE),
+ .ASYNC_RESET_RELEASE(OPTION_RESETMODE),
+ .CSDECODE_A("0b000"),
+ .CSDECODE_B("0b000"),
+ .CLKAMUX(PORT_A_CLK_POL ? "CLKA" : "INV"),
+ .CLKBMUX(PORT_B_CLK_POL ? "CLKB" : "INV"),
+ .WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
+ .WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
+ .GSR("AUTO")
+) _TECHMAP_REPLACE_ (
+ .CLKA(PORT_A_CLK),
+ .WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])),
+ .CEA(PORT_A_CLK_EN),
+ .OCEA(1'b1),
+ .RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
+ .CSA0(1'b0),
+ .CSA1(1'b0),
+ .CSA2(1'b0),
+ .ADA0(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[0] : PORT_A_ADDR[0]),
+ .ADA1(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[1] : PORT_A_ADDR[1]),
+ .ADA2(PORT_A_ADDR[2]),
+ .ADA3(PORT_A_ADDR[3]),
+ .ADA4(PORT_A_ADDR[4]),
+ .ADA5(PORT_A_ADDR[5]),
+ .ADA6(PORT_A_ADDR[6]),
+ .ADA7(PORT_A_ADDR[7]),
+ .ADA8(PORT_A_ADDR[8]),
+ .ADA9(PORT_A_ADDR[9]),
+ .ADA10(PORT_A_ADDR[10]),
+ .ADA11(PORT_A_ADDR[11]),
+ .ADA12(PORT_A_ADDR[12]),
+ .ADA13(PORT_A_ADDR[13]),
+ .DIA0(DIA[0]),
+ .DIA1(DIA[1]),
+ .DIA2(DIA[2]),
+ .DIA3(DIA[3]),
+ .DIA4(DIA[4]),
+ .DIA5(DIA[5]),
+ .DIA6(DIA[6]),
+ .DIA7(DIA[7]),
+ .DIA8(DIA[8]),
+ .DIA9(DIA[9]),
+ .DIA10(DIA[10]),
+ .DIA11(DIA[11]),
+ .DIA12(DIA[12]),
+ .DIA13(DIA[13]),
+ .DIA14(DIA[14]),
+ .DIA15(DIA[15]),
+ .DIA16(DIA[16]),
+ .DIA17(DIA[17]),
+ .DOA0(DOA[0]),
+ .DOA1(DOA[1]),
+ .DOA2(DOA[2]),
+ .DOA3(DOA[3]),
+ .DOA4(DOA[4]),
+ .DOA5(DOA[5]),
+ .DOA6(DOA[6]),
+ .DOA7(DOA[7]),
+ .DOA8(DOA[8]),
+ .DOA9(DOA[9]),
+ .DOA10(DOA[10]),
+ .DOA11(DOA[11]),
+ .DOA12(DOA[12]),
+ .DOA13(DOA[13]),
+ .DOA14(DOA[14]),
+ .DOA15(DOA[15]),
+ .DOA16(DOA[16]),
+ .DOA17(DOA[17]),
+
+ .CLKB(PORT_B_CLK),
+ .WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])),
+ .CEB(PORT_B_CLK_EN),
+ .OCEB(1'b1),
+ .RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
+ .CSB0(1'b0),
+ .CSB1(1'b0),
+ .CSB2(1'b0),
+ .ADB0(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[0] : PORT_B_ADDR[0]),
+ .ADB1(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[1] : PORT_B_ADDR[1]),
+ .ADB2(PORT_B_ADDR[2]),
+ .ADB3(PORT_B_ADDR[3]),
+ .ADB4(PORT_B_ADDR[4]),
+ .ADB5(PORT_B_ADDR[5]),
+ .ADB6(PORT_B_ADDR[6]),
+ .ADB7(PORT_B_ADDR[7]),
+ .ADB8(PORT_B_ADDR[8]),
+ .ADB9(PORT_B_ADDR[9]),
+ .ADB10(PORT_B_ADDR[10]),
+ .ADB11(PORT_B_ADDR[11]),
+ .ADB12(PORT_B_ADDR[12]),
+ .ADB13(PORT_B_ADDR[13]),
+ .DIB0(DIB[0]),
+ .DIB1(DIB[1]),
+ .DIB2(DIB[2]),
+ .DIB3(DIB[3]),
+ .DIB4(DIB[4]),
+ .DIB5(DIB[5]),
+ .DIB6(DIB[6]),
+ .DIB7(DIB[7]),
+ .DIB8(DIB[8]),
+ .DIB9(DIB[9]),
+ .DIB10(DIB[10]),
+ .DIB11(DIB[11]),
+ .DIB12(DIB[12]),
+ .DIB13(DIB[13]),
+ .DIB14(DIB[14]),
+ .DIB15(DIB[15]),
+ .DIB16(DIB[16]),
+ .DIB17(DIB[17]),
+ .DOB0(DOB[0]),
+ .DOB1(DOB[1]),
+ .DOB2(DOB[2]),
+ .DOB3(DOB[3]),
+ .DOB4(DOB[4]),
+ .DOB5(DOB[5]),
+ .DOB6(DOB[6]),
+ .DOB7(DOB[7]),
+ .DOB8(DOB[8]),
+ .DOB9(DOB[9]),
+ .DOB10(DOB[10]),
+ .DOB11(DOB[11]),
+ .DOB12(DOB[12]),
+ .DOB13(DOB[13]),
+ .DOB14(DOB[14]),
+ .DOB15(DOB[15]),
+ .DOB16(DOB[16]),
+ .DOB17(DOB[17]),
+);
+
endmodule
-module \$__ECP5_PDPW16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
- parameter CFG_ABITS = 9;
- parameter CFG_DBITS = 36;
- parameter CFG_ENABLE_A = 4;
-
- parameter CLKPOL2 = 1;
- parameter CLKPOL3 = 1;
- parameter [18431:0] INIT = 18432'bx;
-
- input CLK2;
- input CLK3;
-
- input [CFG_ABITS-1:0] A1ADDR;
- input [CFG_DBITS-1:0] A1DATA;
- input [CFG_ENABLE_A-1:0] A1EN;
-
- input [CFG_ABITS-1:0] B1ADDR;
- output [CFG_DBITS-1:0] B1DATA;
- input B1EN;
-
- localparam CLKWMUX = CLKPOL2 ? "CLKA" : "INV";
- localparam CLKRMUX = CLKPOL3 ? "CLKB" : "INV";
-
- PDPW16KD #(
- `include "bram_init_9_18_36.vh"
- .DATA_WIDTH_W(36),
- .DATA_WIDTH_R(36),
- .CLKWMUX(CLKWMUX),
- .CLKRMUX(CLKRMUX),
- .GSR("AUTO")
- ) _TECHMAP_REPLACE_ (
- `include "bram_conn_36.vh"
- .CLKW(CLK2), .CLKR(CLK3),
- .CEW(1'b1),
- .CER(B1EN), .OCER(1'b1),
- .RST(1'b0)
- );
+
+module $__ECP5_PDPW16KD_ (...);
+
+parameter INIT = 0;
+parameter OPTION_RESETMODE = "SYNC";
+
+parameter PORT_R_WIDTH = 36;
+parameter PORT_R_CLK_POL = 1;
+
+input PORT_R_CLK;
+input PORT_R_CLK_EN;
+input PORT_R_RD_SRST;
+input PORT_R_RD_ARST;
+input [13:0] PORT_R_ADDR;
+output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
+
+parameter PORT_W_WIDTH = 36;
+parameter PORT_W_WR_EN_WIDTH = 4;
+parameter PORT_W_CLK_POL = 1;
+
+input PORT_W_CLK;
+input PORT_W_CLK_EN;
+input [13:0] PORT_W_ADDR;
+input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
+input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
+
+function [319:0] init_slice;
+ input integer idx;
+ integer i, j;
+ init_slice = 0;
+ for (i = 0; i < 16; i = i + 1) begin
+ init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
+ end
+endfunction
+
+wire [35:0] DI = PORT_W_WR_DATA;
+wire [35:0] DO;
+
+assign PORT_R_RD_DATA = PORT_R_WIDTH == 36 ? DO : DO[35:18];
+
+DP16KD #(
+ .INITVAL_00(init_slice('h00)),
+ .INITVAL_01(init_slice('h01)),
+ .INITVAL_02(init_slice('h02)),
+ .INITVAL_03(init_slice('h03)),
+ .INITVAL_04(init_slice('h04)),
+ .INITVAL_05(init_slice('h05)),
+ .INITVAL_06(init_slice('h06)),
+ .INITVAL_07(init_slice('h07)),
+ .INITVAL_08(init_slice('h08)),
+ .INITVAL_09(init_slice('h09)),
+ .INITVAL_0A(init_slice('h0a)),
+ .INITVAL_0B(init_slice('h0b)),
+ .INITVAL_0C(init_slice('h0c)),
+ .INITVAL_0D(init_slice('h0d)),
+ .INITVAL_0E(init_slice('h0e)),
+ .INITVAL_0F(init_slice('h0f)),
+ .INITVAL_10(init_slice('h10)),
+ .INITVAL_11(init_slice('h11)),
+ .INITVAL_12(init_slice('h12)),
+ .INITVAL_13(init_slice('h13)),
+ .INITVAL_14(init_slice('h14)),
+ .INITVAL_15(init_slice('h15)),
+ .INITVAL_16(init_slice('h16)),
+ .INITVAL_17(init_slice('h17)),
+ .INITVAL_18(init_slice('h18)),
+ .INITVAL_19(init_slice('h19)),
+ .INITVAL_1A(init_slice('h1a)),
+ .INITVAL_1B(init_slice('h1b)),
+ .INITVAL_1C(init_slice('h1c)),
+ .INITVAL_1D(init_slice('h1d)),
+ .INITVAL_1E(init_slice('h1e)),
+ .INITVAL_1F(init_slice('h1f)),
+ .INITVAL_20(init_slice('h20)),
+ .INITVAL_21(init_slice('h21)),
+ .INITVAL_22(init_slice('h22)),
+ .INITVAL_23(init_slice('h23)),
+ .INITVAL_24(init_slice('h24)),
+ .INITVAL_25(init_slice('h25)),
+ .INITVAL_26(init_slice('h26)),
+ .INITVAL_27(init_slice('h27)),
+ .INITVAL_28(init_slice('h28)),
+ .INITVAL_29(init_slice('h29)),
+ .INITVAL_2A(init_slice('h2a)),
+ .INITVAL_2B(init_slice('h2b)),
+ .INITVAL_2C(init_slice('h2c)),
+ .INITVAL_2D(init_slice('h2d)),
+ .INITVAL_2E(init_slice('h2e)),
+ .INITVAL_2F(init_slice('h2f)),
+ .INITVAL_30(init_slice('h30)),
+ .INITVAL_31(init_slice('h31)),
+ .INITVAL_32(init_slice('h32)),
+ .INITVAL_33(init_slice('h33)),
+ .INITVAL_34(init_slice('h34)),
+ .INITVAL_35(init_slice('h35)),
+ .INITVAL_36(init_slice('h36)),
+ .INITVAL_37(init_slice('h37)),
+ .INITVAL_38(init_slice('h38)),
+ .INITVAL_39(init_slice('h39)),
+ .INITVAL_3A(init_slice('h3a)),
+ .INITVAL_3B(init_slice('h3b)),
+ .INITVAL_3C(init_slice('h3c)),
+ .INITVAL_3D(init_slice('h3d)),
+ .INITVAL_3E(init_slice('h3e)),
+ .INITVAL_3F(init_slice('h3f)),
+ .DATA_WIDTH_A(PORT_W_WIDTH),
+ .DATA_WIDTH_B(PORT_R_WIDTH),
+ .REGMODE_A("NOREG"),
+ .REGMODE_B("NOREG"),
+ .RESETMODE(OPTION_RESETMODE),
+ .ASYNC_RESET_RELEASE(OPTION_RESETMODE),
+ .CSDECODE_A("0b000"),
+ .CSDECODE_B("0b000"),
+ .CLKAMUX(PORT_W_CLK_POL ? "CLKA" : "INV"),
+ .CLKBMUX(PORT_R_CLK_POL ? "CLKB" : "INV"),
+ .GSR("AUTO")
+) _TECHMAP_REPLACE_ (
+ .CLKA(PORT_W_CLK),
+ .WEA(PORT_W_WIDTH >= 18 ? 1'b1 : PORT_W_WR_EN[0]),
+ .CEA(PORT_W_CLK_EN),
+ .OCEA(1'b0),
+ .RSTA(1'b0),
+ .CSA0(1'b0),
+ .CSA1(1'b0),
+ .CSA2(1'b0),
+ .ADA0(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]),
+ .ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]),
+ .ADA2(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[2] : PORT_W_ADDR[2]),
+ .ADA3(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[3] : PORT_W_ADDR[3]),
+ .ADA4(PORT_W_ADDR[4]),
+ .ADA5(PORT_W_ADDR[5]),
+ .ADA6(PORT_W_ADDR[6]),
+ .ADA7(PORT_W_ADDR[7]),
+ .ADA8(PORT_W_ADDR[8]),
+ .ADA9(PORT_W_ADDR[9]),
+ .ADA10(PORT_W_ADDR[10]),
+ .ADA11(PORT_W_ADDR[11]),
+ .ADA12(PORT_W_ADDR[12]),
+ .ADA13(PORT_W_ADDR[13]),
+ .DIA0(DI[0]),
+ .DIA1(DI[1]),
+ .DIA2(DI[2]),
+ .DIA3(DI[3]),
+ .DIA4(DI[4]),
+ .DIA5(DI[5]),
+ .DIA6(DI[6]),
+ .DIA7(DI[7]),
+ .DIA8(DI[8]),
+ .DIA9(DI[9]),
+ .DIA10(DI[10]),
+ .DIA11(DI[11]),
+ .DIA12(DI[12]),
+ .DIA13(DI[13]),
+ .DIA14(DI[14]),
+ .DIA15(DI[15]),
+ .DIA16(DI[16]),
+ .DIA17(DI[17]),
+ .DIB0(DI[18]),
+ .DIB1(DI[19]),
+ .DIB2(DI[20]),
+ .DIB3(DI[21]),
+ .DIB4(DI[22]),
+ .DIB5(DI[23]),
+ .DIB6(DI[24]),
+ .DIB7(DI[25]),
+ .DIB8(DI[26]),
+ .DIB9(DI[27]),
+ .DIB10(DI[28]),
+ .DIB11(DI[29]),
+ .DIB12(DI[30]),
+ .DIB13(DI[31]),
+ .DIB14(DI[32]),
+ .DIB15(DI[33]),
+ .DIB16(DI[34]),
+ .DIB17(DI[35]),
+
+ .CLKB(PORT_R_CLK),
+ .WEB(1'b0),
+ .CEB(PORT_R_CLK_EN),
+ .OCEB(1'b1),
+ .RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST),
+ .CSB0(1'b0),
+ .CSB1(1'b0),
+ .CSB2(1'b0),
+ .ADB0(PORT_R_ADDR[0]),
+ .ADB1(PORT_R_ADDR[1]),
+ .ADB2(PORT_R_ADDR[2]),
+ .ADB3(PORT_R_ADDR[3]),
+ .ADB4(PORT_R_ADDR[4]),
+ .ADB5(PORT_R_ADDR[5]),
+ .ADB6(PORT_R_ADDR[6]),
+ .ADB7(PORT_R_ADDR[7]),
+ .ADB8(PORT_R_ADDR[8]),
+ .ADB9(PORT_R_ADDR[9]),
+ .ADB10(PORT_R_ADDR[10]),
+ .ADB11(PORT_R_ADDR[11]),
+ .ADB12(PORT_R_ADDR[12]),
+ .ADB13(PORT_R_ADDR[13]),
+ .DOA0(DO[0]),
+ .DOA1(DO[1]),
+ .DOA2(DO[2]),
+ .DOA3(DO[3]),
+ .DOA4(DO[4]),
+ .DOA5(DO[5]),
+ .DOA6(DO[6]),
+ .DOA7(DO[7]),
+ .DOA8(DO[8]),
+ .DOA9(DO[9]),
+ .DOA10(DO[10]),
+ .DOA11(DO[11]),
+ .DOA12(DO[12]),
+ .DOA13(DO[13]),
+ .DOA14(DO[14]),
+ .DOA15(DO[15]),
+ .DOA16(DO[16]),
+ .DOA17(DO[17]),
+ .DOB0(DO[18]),
+ .DOB1(DO[19]),
+ .DOB2(DO[20]),
+ .DOB3(DO[21]),
+ .DOB4(DO[22]),
+ .DOB5(DO[23]),
+ .DOB6(DO[24]),
+ .DOB7(DO[25]),
+ .DOB8(DO[26]),
+ .DOB9(DO[27]),
+ .DOB10(DO[28]),
+ .DOB11(DO[29]),
+ .DOB12(DO[30]),
+ .DOB13(DO[31]),
+ .DOB14(DO[32]),
+ .DOB15(DO[33]),
+ .DOB16(DO[34]),
+ .DOB17(DO[35]),
+);
endmodule
-bram $__TRELLIS_DPR16X4
- init 1
- abits 4
- dbits 4
- groups 2
- ports 1 1
- wrmode 0 1
- enable 0 1
- transp 0 0
- clocks 0 1
- clkpol 0 2
-endbram
-
-# The syn_* attributes are described in:
-# https://www.latticesemi.com/view_document?document_id=51556
-attr_icase 1
-
-match $__TRELLIS_DPR16X4
- attribute !syn_ramstyle syn_ramstyle=auto syn_ramstyle=distributed
- attribute !syn_romstyle syn_romstyle=auto
- attribute !ram_block
- attribute !rom_block
- attribute !logic_block
- make_outreg
- min wports 1
-endmatch
+ram distributed $__TRELLIS_DPR16X4_ {
+ abits 4;
+ width 4;
+ cost 4;
+ init any;
+ prune_rom;
+ port sw "W" {
+ clock anyedge;
+ }
+ port ar "R" {
+ }
+}
-module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
- parameter [63:0] INIT = 64'bx;
- parameter CLKPOL2 = 1;
- input CLK1;
+module $__TRELLIS_DPR16X4_(...);
- input [3:0] A1ADDR;
- output [3:0] A1DATA;
+parameter INIT = 64'bx;
+parameter PORT_W_CLK_POL = 1;
- input [3:0] B1ADDR;
- input [3:0] B1DATA;
- input B1EN;
+input PORT_W_CLK;
+input [3:0] PORT_W_ADDR;
+input [3:0] PORT_W_WR_DATA;
+input PORT_W_WR_EN;
- localparam WCKMUX = CLKPOL2 ? "WCK" : "INV";
+input [3:0] PORT_R_ADDR;
+output [3:0] PORT_R_RD_DATA;
- TRELLIS_DPR16X4 #(
- .INITVAL(INIT),
- .WCKMUX(WCKMUX),
- .WREMUX("WRE")
- ) _TECHMAP_REPLACE_ (
- .RAD(A1ADDR),
- .DO(A1DATA),
+localparam WCKMUX = PORT_W_CLK_POL ? "WCK" : "INV";
+
+TRELLIS_DPR16X4 #(
+ .INITVAL(INIT),
+ .WCKMUX(WCKMUX),
+ .WREMUX("WRE")
+) _TECHMAP_REPLACE_ (
+ .RAD(PORT_R_ADDR),
+ .DO(PORT_R_RD_DATA),
+
+ .WAD(PORT_W_ADDR),
+ .DI(PORT_W_WR_DATA),
+ .WCK(PORT_W_CLK),
+ .WRE(PORT_W_WR_EN)
+);
- .WAD(B1ADDR),
- .DI(B1DATA),
- .WCK(CLK1),
- .WRE(B1EN)
- );
endmodule
run("opt_clean");
}
- if (!nobram && check_label("map_bram", "(skip if -nobram)"))
+ if (check_label("map_ram"))
{
- run("memory_bram -rules +/ecp5/brams.txt");
- run("techmap -map +/ecp5/brams_map.v");
- }
-
- if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
- {
- run("memory_bram -rules +/ecp5/lutrams.txt");
- run("techmap -map +/ecp5/lutrams_map.v");
+ std::string args = "";
+ if (nobram)
+ args += " -no-auto-block";
+ if (nolutram)
+ args += " -no-auto-distributed";
+ if (help_mode)
+ args += " [-no-auto-block] [-no-auto-distributed]";
+ run("memory_libmap -lib +/ecp5/lutrams.txt -lib +/ecp5/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
+ run("techmap -map +/ecp5/lutrams_map.v -map +/ecp5/brams_map.v");
}
if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
- run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block "
- "-attr syn_ramstyle=auto -attr syn_ramstyle=registers "
- "-attr syn_romstyle=auto -attr syn_romstyle=logic");
+ run("memory_map");
run("opt -undriven -fine");
}
# ================================ RAM ================================
-# RAM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
+# RAM bits <= 18K; Data width <= 36; Address width <= 9: -> DP16KD
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:PDPW16KD
+select -assert-count 1 t:DP16KD
## With parameters
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:PDPW16KD # too inefficient
+select -assert-count 0 t:DP16KD # too inefficient
select -assert-count 9 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "block_ram" m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:PDPW16KD
+select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "Block_RAM" m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:PDPW16KD # any case works
+select -assert-count 1 t:DP16KD # any case works
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set ram_block 1 m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:PDPW16KD
+select -assert-count 0 t:DP16KD
+select -assert-count 9 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "registers" m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
+select -assert-count 0 t:DP16KD # requested FFRAM explicitly
select -assert-count 180 t:TRELLIS_FF
design -reset; read_verilog -defer ../common/blockram.v
hierarchy -top sync_ram_sdp
setattr -set logic_block 1 m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
+select -assert-count 0 t:DP16KD # requested FFRAM explicitly
select -assert-count 180 t:TRELLIS_FF
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_romstyle "ebr" m:memory
-synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set rom_block 1 m:memory
-synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "block_ram" m:memory
-synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set ram_block 1 m:memory
-synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
-
# RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
design -reset; read_verilog -defer ../common/blockram.v
hierarchy -top sync_ram_sdp
setattr -set ram_block 1 m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:DP16KD
+select -assert-count 0 t:DP16KD # too inefficient
+select -assert-count 5 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
select -assert-count 0 t:DP16KD # requested FFRAM explicitly
select -assert-count 90 t:TRELLIS_FF
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_romstyle "ebr" m:memory
-synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set rom_block 1 m:memory
-synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "block_ram" m:memory
-synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
-
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set ram_block 1 m:memory
-synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
-
# RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
select -assert-count 68 t:TRELLIS_FF
-design -reset; read_verilog -defer ../common/blockram.v
-chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
-hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "distributed" m:memory
-synth_ecp5 -top sync_ram_sdp -nolutram; cd sync_ram_sdp
-select -assert-count 1 t:$mem_v2 # requested LUTRAM but LUTRAM is disabled
-
# ================================ ROM ================================
-# ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
+# ROM bits <= 18K; Data width <= 36; Address width <= 9: -> DP16KD
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_rom
hierarchy -top sync_rom
synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:PDPW16KD
+select -assert-count 1 t:DP16KD
## With parameters
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
hierarchy -top sync_rom
synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 0 t:PDPW16KD # too inefficient
+select -assert-count 0 t:DP16KD # too inefficient
select -assert-min 18 t:LUT4
design -reset; read_verilog -defer ../common/blockrom.v
hierarchy -top sync_rom
setattr -set syn_romstyle "ebr" m:memory
synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:PDPW16KD
+select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
hierarchy -top sync_rom
setattr -set rom_block 1 m:memory
synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:PDPW16KD
+select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "logic" m:memory
synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
+select -assert-count 0 t:DP16KD # requested LUTROM explicitly
select -assert-min 18 t:LUT4
design -reset; read_verilog -defer ../common/blockrom.v
hierarchy -top sync_rom
setattr -set logic_block 1 m:memory
synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
+select -assert-count 0 t:DP16KD # requested LUTROM explicitly
select -assert-min 18 t:LUT4
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
-hierarchy -top sync_rom
-setattr -set syn_ramstyle "block_ram" m:memory
-synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
-hierarchy -top sync_rom
-setattr -set ram_block 1 m:memory
-synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
-hierarchy -top sync_rom
-setattr -set syn_ramstyle "block_rom" m:memory
-synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
-hierarchy -top sync_rom
-setattr -set rom_block 1 m:memory
-synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
-
# ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
design -reset; read_verilog -defer ../common/blockrom.v
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:DP16KD # requested LUTROM explicitly
select -assert-min 9 t:LUT4
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
-hierarchy -top sync_rom
-setattr -set syn_ramstyle "block_ram" m:memory
-synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
-hierarchy -top sync_rom
-setattr -set ram_block 1 m:memory
-synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
-hierarchy -top sync_rom
-setattr -set syn_ramstyle "block_rom" m:memory
-synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
-
-design -reset; read_verilog -defer ../common/blockrom.v
-chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
-hierarchy -top sync_rom
-setattr -set rom_block 1 m:memory
-synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
projects / yosys.git / commitdiff