Result CegisCoreConnective::checkSat(Node n, std::vector<Node>& mvs) const
{
Trace("sygus-ccore-debug") << "...check-sat " << n << "..." << std::endl;
+ n = rewrite(n);
Result r = checkWithSubsolver(n, d_vars, mvs, options(), logicInfo());
Trace("sygus-ccore-debug") << "...got " << r << std::endl;
return r;
}
Trace("sygus-engine") << "Check side condition..." << std::endl;
Trace("cegqi-debug") << "Check side condition : " << sc << std::endl;
+ sc = rewrite(sc);
Result r = checkWithSubsolver(sc, options(), logicInfo());
Trace("cegqi-debug") << "...got side condition : " << r << std::endl;
if (r == Result::UNSAT)
}
}
Trace("sygus-engine") << " *** Verify with subcall..." << std::endl;
+ query = rewrite(query);
Result r = checkWithSubsolver(query, vars, mvs, d_subOptions, d_subLogicInfo);
Trace("sygus-engine") << " ...got " << r << std::endl;
if (r.asSatisfiabilityResult().isSat() == Result::SAT)
#include "smt/env.h"
#include "smt/solver_engine.h"
#include "smt/solver_engine_scope.h"
-#include "theory/rewriter.h"
namespace cvc5 {
namespace theory {
// optimization: try to rewrite to constant
Result quickCheck(Node& query)
{
- query = theory::Rewriter::rewrite(query);
if (query.isConst())
{
if (!query.getConst<bool>())
// been introduced
if (d_isHigherOrder)
{
- Node arg = Rewriter::rewrite(node[1]);
+ Node arg = node[1];
Node var = node[0][0][0];
new_body = expr::substituteCaptureAvoiding(new_body, var, arg);
}
else
{
- TNode arg = Rewriter::rewrite(node[1]);
+ TNode arg = node[1];
TNode var = node[0][0][0];
new_body = new_body.substitute(var, arg);
}