Add Wishbone read/write helpers

diff --git a/gram/test/utils.py b/gram/test/utils.py
index 38b8010dbaf5fbba3b273df18ef7d092d6ea818e..45b1c30ff2402b13ede167488942e604b7dca293 100644 (file)
--- a/gram/test/utils.py
+++ b/gram/test/utils.py
@@ -15,7 +15,7 @@ from nmigen.back import rtlil
 from nmigen._toolchain import require_tool
 
 
-__all__ = ["FHDLTestCase", "runSimulation"]
+__all__ = ["FHDLTestCase", "runSimulation", "wb_read", "wb_write"]
 
 def runSimulation(module, process, vcd_filename="anonymous.vcd", clock=1e-6):
     sim = Simulator(module)
@@ -103,3 +103,38 @@ class FHDLTestCase(unittest.TestCase):
             stdout, stderr = proc.communicate(config)
             if proc.returncode != 0:
                 self.fail("Formal verification failed:\n" + stdout)
+
+def wb_read(bus, addr, sel, timeout=32):
+    yield bus.cyc.eq(1)
+    yield bus.stb.eq(1)
+    yield bus.adr.eq(addr)
+    yield bus.sel.eq(sel)
+    yield
+    cycles = 0
+    while not (yield bus.ack):
+        yield
+        if cycles >= timeout:
+            raise RuntimeError("Wishbone transaction timed out")
+        cycles += 1
+    data = (yield bus.dat_r)
+    yield bus.cyc.eq(0)
+    yield bus.stb.eq(0)
+    return data
+
+def wb_write(bus, addr, data, sel, timeout=32):
+    yield bus.cyc.eq(1)
+    yield bus.stb.eq(1)
+    yield bus.adr.eq(addr)
+    yield bus.we.eq(1)
+    yield bus.sel.eq(sel)
+    yield bus.dat_w.eq(data)
+    yield
+    cycles = 0
+    while not (yield bus.ack):
+        yield
+        if cycles >= timeout:
+            raise RuntimeError("Wishbone transaction timed out")
+        cycles += 1
+    yield bus.cyc.eq(0)
+    yield bus.stb.eq(0)
+    yield bus.we.eq(0)