+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64 files.
+ * Makefile.in: Regenerate.
+ * archures.c (bfd_aarch64_arch): New declaration.
+ (bfd_archures_list): Use bfd_archures_list.
+ * bfd-in.h (bfd_elf64_aarch64_init_maps): New declaration.
+ (bfd_aarch64_process_before_allocation): New declaration.
+ (bfd_elf64_aarch64_process_before_allocation): New declaration.
+ (bfd_elf64_aarch64_set_options): New declaration.
+ (bfd_elf64_aarch64_add_glue_sections_to_bfd): New declaration.
+ (BFD_AARCH64_SPECIAL_SYM_TYPE_MAP): New definition.
+ (BFD_AARCH64_SPECIAL_SYM_TYPE_TAG): New definition.
+ (BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER): New definition.
+ (BFD_AARCH64_SPECIAL_SYM_TYPE_ANY): New definition.
+ (bfd_is_aarch64_special_symbol_name): New declaration.
+ (bfd_aarch64_merge_machines): New declaration.
+ (bfd_aarch64_update_notes): New declaration.
+ (int bfd_aarch64_get_mach_from_notes): New declaration.
+ (elf64_aarch64_setup_section_lists): New declaration.
+ (elf64_aarch64_next_input_section): New declaration.
+ (elf64_aarch64_size_stubs): New declaration.
+ (elf64_aarch64_build_stubs): New declaration.
+ * config.bfd: Add AArch64.
+ * configure.in: Add AArch64.
+ * configure: Regenerate.
+ * cpu-aarch64.c: New file.
+ * elf-bfd.h: Add AArch64.
+ * bfd-in2.h: Regenerate.
+ * libbfd.h: Regenerate.
+ * elf64-aarch64.c: New file.
+ * reloc.c: Add AArch64 relocations.
+ * targets.c: Add AArch64.
+ * po/SRC-POTFILES.in: Regenerate.
+
2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
* elfxx-mips.c (mips_elf_calculate_relocation): Fix the handling
# This list is alphabetized to make it easier to keep in sync
# with the decls and initializer in archures.c.
ALL_MACHINES = \
+ cpu-aarch64.lo \
cpu-alpha.lo \
cpu-arc.lo \
cpu-arm.lo \
cpu-z8k.lo
ALL_MACHINES_CFILES = \
+ cpu-aarch64.c \
cpu-alpha.c \
cpu-arc.c \
cpu-arm.c \
# elf32-ia64.c requires a 64-bit bfd_vma, and hence can not be put in
# BFD32_BACKENDS.
BFD64_BACKENDS = \
+ elf64-aarch64.lo \
aix5ppc-core.lo \
aout64.lo \
coff-alpha.lo \
vms-alpha.lo
BFD64_BACKENDS_CFILES = \
+ elf64-aarch64.c \
aix5ppc-core.c \
aout64.c \
coff-alpha.c \
# This list is alphabetized to make it easier to keep in sync
# with the decls and initializer in archures.c.
ALL_MACHINES = \
+ cpu-aarch64.lo \
cpu-alpha.lo \
cpu-arc.lo \
cpu-arm.lo \
cpu-z8k.lo
ALL_MACHINES_CFILES = \
+ cpu-aarch64.c \
cpu-alpha.c \
cpu-arc.c \
cpu-arm.c \
# elf32-ia64.c requires a 64-bit bfd_vma, and hence can not be put in
# BFD32_BACKENDS.
BFD64_BACKENDS = \
+ elf64-aarch64.lo \
aix5ppc-core.lo \
aout64.lo \
coff-alpha.lo \
vms-alpha.lo
BFD64_BACKENDS_CFILES = \
+ elf64-aarch64.c \
aix5ppc-core.c \
aout64.c \
coff-alpha.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cofflink.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/compress.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/corefile.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-alpha.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xstormy16.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xtensa.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-alpha.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-gen.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@
.#define bfd_mach_tilepro 1
.#define bfd_mach_tilegx 1
.#define bfd_mach_tilegx32 2
+. bfd_arch_aarch64, {* AArch64 *}
+.#define bfd_mach_aarch64 0
. bfd_arch_last
. };
*/
.
*/
+extern const bfd_arch_info_type bfd_aarch64_arch;
extern const bfd_arch_info_type bfd_alpha_arch;
extern const bfd_arch_info_type bfd_arc_arch;
extern const bfd_arch_info_type bfd_arm_arch;
#ifdef SELECT_ARCHITECTURES
SELECT_ARCHITECTURES,
#else
+ &bfd_aarch64_arch,
&bfd_alpha_arch,
&bfd_arc_arch,
&bfd_arm_arch,
extern unsigned int _bfd_elf_ppc_at_tprel_transform
(unsigned int, unsigned int);
+extern void bfd_elf64_aarch64_init_maps
+ (bfd *);
+
+void bfd_elf64_aarch64_set_options
+ (bfd *, struct bfd_link_info *, int, int, int);
+
+/* ELF AArch64 mapping symbol support. */
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_MAP (1 << 0)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_TAG (1 << 1)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER (1 << 2)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_ANY (~0)
+extern bfd_boolean bfd_is_aarch64_special_symbol_name
+ (const char * name, int type);
+
+/* AArch64 stub generation support. Called from the linker. */
+extern int elf64_aarch64_setup_section_lists
+ (bfd *, struct bfd_link_info *);
+extern void elf64_aarch64_next_input_section
+ (struct bfd_link_info *, struct bfd_section *);
+extern bfd_boolean elf64_aarch64_size_stubs
+ (bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma,
+ struct bfd_section * (*) (const char *, struct bfd_section *),
+ void (*) (void));
+extern bfd_boolean elf64_aarch64_build_stubs
+ (struct bfd_link_info *);
+
/* TI COFF load page support. */
extern void bfd_ticoff_set_section_load_page
(struct bfd_section *, int);
extern unsigned int _bfd_elf_ppc_at_tprel_transform
(unsigned int, unsigned int);
+extern void bfd_elf64_aarch64_init_maps
+ (bfd *);
+
+void bfd_elf64_aarch64_set_options
+ (bfd *, struct bfd_link_info *, int, int, int);
+
+/* ELF AArch64 mapping symbol support. */
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_MAP (1 << 0)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_TAG (1 << 1)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER (1 << 2)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_ANY (~0)
+extern bfd_boolean bfd_is_aarch64_special_symbol_name
+ (const char * name, int type);
+
+/* AArch64 stub generation support. Called from the linker. */
+extern int elf64_aarch64_setup_section_lists
+ (bfd *, struct bfd_link_info *);
+extern void elf64_aarch64_next_input_section
+ (struct bfd_link_info *, struct bfd_section *);
+extern bfd_boolean elf64_aarch64_size_stubs
+ (bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma,
+ struct bfd_section * (*) (const char *, struct bfd_section *),
+ void (*) (void));
+extern bfd_boolean elf64_aarch64_build_stubs
+ (struct bfd_link_info *);
+
/* TI COFF load page support. */
extern void bfd_ticoff_set_section_load_page
(struct bfd_section *, int);
#define bfd_mach_tilepro 1
#define bfd_mach_tilegx 1
#define bfd_mach_tilegx32 2
+ bfd_arch_aarch64, /* AArch64 */
+#define bfd_mach_aarch64 0
bfd_arch_last
};
the dynamic object into the runtime process image. */
BFD_RELOC_MICROBLAZE_COPY,
+/* AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
+Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_ADD_LO12,
+
+/* Get to the page base of the global offset table entry for a symbol as
+part of an ADRP instruction using a 21 bit PC relative value.Used in
+conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. */
+ BFD_RELOC_AARCH64_ADR_GOT_PAGE,
+
+/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+offset, giving a 4KB aligned page base address. */
+ BFD_RELOC_AARCH64_ADR_HI21_PCREL,
+
+/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+offset, giving a 4KB aligned page base address, but with no overflow
+checking. */
+ BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
+
+/* AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. */
+ BFD_RELOC_AARCH64_ADR_LO21_PCREL,
+
+/* AArch64 19 bit pc-relative conditional branch and compare & branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 21 bit signed byte offset. */
+ BFD_RELOC_AARCH64_BRANCH19,
+
+/* AArch64 26 bit pc-relative unconditional branch and link.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 28 bit signed byte offset. */
+ BFD_RELOC_AARCH64_CALL26,
+
+/* AArch64 pseudo relocation code to be used internally by the AArch64
+assembler and not (currently) written to any object files. */
+ BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP,
+
+/* AArch64 26 bit pc-relative unconditional branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 28 bit signed byte offset. */
+ BFD_RELOC_AARCH64_JUMP26,
+
+/* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
+offset. The lowest two bits must be zero and are not stored in the
+instruction, giving a 21 bit signed byte offset. */
+ BFD_RELOC_AARCH64_LD_LO19_PCREL,
+
+/* Unsigned 12 bit byte offset for 64 bit load/store from the page of
+the GOT entry for this symbol. Used in conjunction with
+BFD_RELOC_AARCH64_ADR_GOTPAGE. */
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC,
+
+/* AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST_LO12,
+
+/* AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST8_LO12,
+
+/* AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST16_LO12,
+
+/* AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST32_LO12,
+
+/* AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST64_LO12,
+
+/* AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST128_LO12,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 0 to 15
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G0,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G0_S,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
+an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G0_NC,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 16 to 31
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G1,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 16 to 31
+of an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G1_NC,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 16 to 31
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G1_S,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 32 to 47
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G2,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 32 to 47
+of an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G2_NC,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 32 to 47
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G2_S,
+
+/* AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
+of a signed or unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G3,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLSDESC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADD,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_CALL,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LDR,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
+
+/* Unsigned 12 bit byte offset to global offset table entry for a symbols
+tls_index structure. Used in conjunction with
+BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. */
+ BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
+
+/* Get to the page base of the global offset table entry for a symbols
+tls_index structure as part of an adrp instruction using a 21 bit PC
+relative value. Used in conjunction with
+BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. */
+ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_DTPMOD64,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_DTPREL64,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_TPREL64,
+
+/* AArch64 14 bit pc-relative test bit and branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 16 bit signed byte offset. */
+ BFD_RELOC_AARCH64_TSTBR14,
+
/* Tilera TILEPro Relocations. */
BFD_RELOC_TILEPRO_COPY,
BFD_RELOC_TILEPRO_GLOB_DAT,
targ_cpu=`echo $targ | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
case "${targ_cpu}" in
+aarch64*) targ_archs="bfd_aarch64_arch bfd_arm_arch";;
alpha*) targ_archs=bfd_alpha_arch ;;
am34*|am33_2.0*) targ_archs=bfd_mn10300_arch ;;
arm*) targ_archs=bfd_arm_arch ;;
# START OF targmatch.h
#ifdef BFD64
+ aarch64-*-elf)
+ targ_defvec=bfd_elf64_littleaarch64_vec
+ targ_selvecs="bfd_elf64_bigaarch64_vec bfd_elf32_littlearm_vec bfd_elf32_bigarm_vec"
+ want64=true
+ ;;
+ aarch64_be-*-elf)
+ targ_defvec=bfd_elf64_bigaarch64_vec
+ targ_selvecs="bfd_elf64_littleaarch64_vec bfd_elf32_bigarm_vec bfd_elf32_littlearm_vec"
+ want64=true
+ ;;
+ aarch64-*-linux*)
+ targ_defvec=bfd_elf64_littleaarch64_vec
+ targ_selvecs="bfd_elf64_bigaarch64_vec bfd_elf32_littlearm_vec bfd_elf32_bigarm_vec"
+ want64=true
+ ;;
+ aarch64_be-*-linux*)
+ targ_defvec=bfd_elf64_bigaarch64_vec
+ targ_selvecs="bfd_elf64_littleaarch64_vec bfd_elf32_bigarm_vec bfd_elf32_littlearm_vec"
+ want64=true
+ ;;
alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu)
targ_defvec=bfd_elf64_alpha_freebsd_vec
targ_selvecs="bfd_elf64_alpha_vec ecoffalpha_little_vec"
bfd_elf32_xtensa_be_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
bfd_elf64_alpha_freebsd_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_alpha_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
+ bfd_elf64_bigaarch64_vec) tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_big_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_bigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_hppa_linux_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_hpux_big_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_little_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_vms_vec) tb="$tb elf64-ia64-vms.lo elf64-ia64.lo elfxx-ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=64 ;;
+ bfd_elf64_littleaarch64_vec)tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;;
bfd_elf32_xtensa_be_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
bfd_elf64_alpha_freebsd_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_alpha_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
+ bfd_elf64_bigaarch64_vec) tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_big_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_bigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_hppa_linux_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_hpux_big_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_little_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_vms_vec) tb="$tb elf64-ia64-vms.lo elf64-ia64.lo elfxx-ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=64 ;;
+ bfd_elf64_littleaarch64_vec)tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;;
--- /dev/null
+/* BFD support for AArch64.
+ Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "libiberty.h"
+
+/* This routine is provided two arch_infos and works out which Aarch64
+ machine which would be compatible with both and returns a pointer
+ to its info structure. */
+
+static const bfd_arch_info_type *
+compatible (const bfd_arch_info_type * a, const bfd_arch_info_type * b)
+{
+ /* If a & b are for different architecture we can do nothing. */
+ if (a->arch != b->arch)
+ return NULL;
+
+ /* If a & b are for the same machine then all is well. */
+ if (a->mach == b->mach)
+ return a;
+
+ /* Otherwise if either a or b is the 'default' machine
+ then it can be polymorphed into the other. */
+ if (a->the_default)
+ return b;
+
+ if (b->the_default)
+ return a;
+
+ /* So far all newer cores are
+ supersets of previous cores. */
+ if (a->mach < b->mach)
+ return b;
+ else if (a->mach > b->mach)
+ return a;
+
+ /* Never reached! */
+ return NULL;
+}
+
+static struct
+{
+ unsigned int mach;
+ char *name;
+}
+processors[] =
+{
+ /* These two are example CPUs supported in GCC, once we have real
+ CPUs they will be removed. */
+ { bfd_mach_aarch64, "example-1" },
+ { bfd_mach_aarch64, "example-2" }
+};
+
+static bfd_boolean
+scan (const struct bfd_arch_info *info, const char *string)
+{
+ int i;
+
+ /* First test for an exact match. */
+ if (strcasecmp (string, info->printable_name) == 0)
+ return TRUE;
+
+ /* Next check for a processor name instead of an Architecture name. */
+ for (i = sizeof (processors) / sizeof (processors[0]); i--;)
+ {
+ if (strcasecmp (string, processors[i].name) == 0)
+ break;
+ }
+
+ if (i != -1 && info->mach == processors[i].mach)
+ return TRUE;
+
+ /* Finally check for the default architecture. */
+ if (strcasecmp (string, "aarch64") == 0)
+ return info->the_default;
+
+ return FALSE;
+}
+
+#define N(NUMBER, PRINT, DEFAULT, NEXT) \
+ { 64, 64, 8, bfd_arch_aarch64, NUMBER, \
+ "aarch64", PRINT, 4, DEFAULT, compatible, scan, \
+ bfd_arch_default_fill, NEXT }
+
+const bfd_arch_info_type bfd_aarch64_arch =
+ N (0, "aarch64", TRUE, NULL);
+
+
+bfd_boolean
+bfd_is_aarch64_special_symbol_name (const char *name, int type)
+{
+ if (!name || name[0] != '$')
+ return FALSE;
+ if (name[1] == 'x' || name[1] == 'd')
+ type &= BFD_AARCH64_SPECIAL_SYM_TYPE_MAP;
+ else if (name[1] == 'm' || name[1] == 'f' || name[1] == 'p')
+ type &= BFD_AARCH64_SPECIAL_SYM_TYPE_TAG;
+ else
+ return FALSE;
+
+ return (type != 0 && (name[2] == 0 || name[2] == '.'));
+}
DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \
$(bfd_TEXINFOS)
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
+am__aclocal_m4_deps = $(top_srcdir)/../bfd/bfd.m4 \
+ $(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/gettext-sister.m4 \
$(top_srcdir)/../config/largefile.m4 \
$(top_srcdir)/../config/stdint.m4 $(top_srcdir)/../libtool.m4 \
$(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \
$(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \
- $(top_srcdir)/bfd.m4 $(top_srcdir)/warning.m4 \
$(top_srcdir)/acinclude.m4 $(top_srcdir)/../config/zlib.m4 \
$(top_srcdir)/configure.in
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
one line. */
enum elf_target_id
{
- ALPHA_ELF_DATA = 1,
+ AARCH64_ELF_DATA = 1,
+ ALPHA_ELF_DATA,
ARM_ELF_DATA,
AVR_ELF_DATA,
BFIN_ELF_DATA,
--- /dev/null
+/* ELF support for AArch64.
+ Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+/* Notes on implementation:
+
+ Thread Local Store (TLS)
+
+ Overview:
+
+ The implementation currently supports both traditional TLS and TLS
+ descriptors, but only general dynamic (GD).
+
+ For traditional TLS the assembler will present us with code
+ fragments of the form:
+
+ adrp x0, :tlsgd:foo
+ R_AARCH64_TLSGD_ADR_PAGE21(foo)
+ add x0, :tlsgd_lo12:foo
+ R_AARCH64_TLSGD_ADD_LO12_NC(foo)
+ bl __tls_get_addr
+ nop
+
+ For TLS descriptors the assembler will present us with code
+ fragments of the form:
+
+ adrp x0, :tlsdesc:foo R_AARCH64_TLSDESC_ADR_PAGE(foo)
+ ldr x1, [x0, #:tlsdesc_lo12:foo] R_AARCH64_TLSDESC_LD64_LO12(foo)
+ add x0, x0, #:tlsdesc_lo12:foo R_AARCH64_TLSDESC_ADD_LO12(foo)
+ .tlsdesccall foo
+ blr x1 R_AARCH64_TLSDESC_CALL(foo)
+
+ The relocations R_AARCH64_TLSGD_{ADR_PREL21,ADD_LO12_NC} against foo
+ indicate that foo is thread local and should be accessed via the
+ traditional TLS mechanims.
+
+ The relocations R_AARCH64_TLSDESC_{ADR_PAGE,LD64_LO12_NC,ADD_LO12_NC}
+ against foo indicate that 'foo' is thread local and should be accessed
+ via a TLS descriptor mechanism.
+
+ The precise instruction sequence is only relevant from the
+ perspective of linker relaxation which is currently not implemented.
+
+ The static linker must detect that 'foo' is a TLS object and
+ allocate a double GOT entry. The GOT entry must be created for both
+ global and local TLS symbols. Note that this is different to none
+ TLS local objects which do not need a GOT entry.
+
+ In the traditional TLS mechanism, the double GOT entry is used to
+ provide the tls_index structure, containing module and offset
+ entries. The static linker places the relocation R_AARCH64_TLS_DTPMOD64
+ on the module entry. The loader will subsequently fixup this
+ relocation with the module identity.
+
+ For global traditional TLS symbols the static linker places an
+ R_AARCH64_TLS_DTPREL64 relocation on the offset entry. The loader
+ will subsequently fixup the offset. For local TLS symbols the static
+ linker fixes up offset.
+
+ In the TLS descriptor mechanism the double GOT entry is used to
+ provide the descriptor. The static linker places the relocation
+ R_AARCH64_TLSDESC on the first GOT slot. The loader will
+ subsequently fix this up.
+
+ Implementation:
+
+ The handling of TLS symbols is implemented across a number of
+ different backend functions. The following is a top level view of
+ what processing is performed where.
+
+ The TLS implementation maintains state information for each TLS
+ symbol. The state information for local and global symbols is kept
+ in different places. Global symbols use generic BFD structures while
+ local symbols use backend specific structures that are allocated and
+ maintained entirely by the backend.
+
+ The flow:
+
+ aarch64_check_relocs()
+
+ This function is invoked for each relocation.
+
+ The TLS relocations R_AARCH64_TLSGD_{ADR_PREL21,ADD_LO12_NC} and
+ R_AARCH64_TLSDESC_{ADR_PAGE,LD64_LO12_NC,ADD_LO12_NC} are
+ spotted. One time creation of local symbol data structures are
+ created when the first local symbol is seen.
+
+ The reference count for a symbol is incremented. The GOT type for
+ each symbol is marked as general dynamic.
+
+ elf64_aarch64_allocate_dynrelocs ()
+
+ For each global with positive reference count we allocate a double
+ GOT slot. For a traditional TLS symbol we allocate space for two
+ relocation entries on the GOT, for a TLS descriptor symbol we
+ allocate space for one relocation on the slot. Record the GOT offset
+ for this symbol.
+
+ elf64_aarch64_size_dynamic_sections ()
+
+ Iterate all input BFDS, look for in the local symbol data structure
+ constructed earlier for local TLS symbols and allocate them double
+ GOT slots along with space for a single GOT relocation. Update the
+ local symbol structure to record the GOT offset allocated.
+
+ elf64_aarch64_relocate_section ()
+
+ Calls elf64_aarch64_final_link_relocate ()
+
+ Emit the relevant TLS relocations against the GOT for each TLS
+ symbol. For local TLS symbols emit the GOT offset directly. The GOT
+ relocations are emitted once the first time a TLS symbol is
+ encountered. The implementation uses the LSB of the GOT offset to
+ flag that the relevant GOT relocations for a symbol have been
+ emitted. All of the TLS code that uses the GOT offset needs to take
+ care to mask out this flag bit before using the offset.
+
+ elf64_aarch64_final_link_relocate ()
+
+ Fixup the R_AARCH64_TLSGD_{ADR_PREL21, ADD_LO12_NC} relocations. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libiberty.h"
+#include "libbfd.h"
+#include "bfd_stdint.h"
+#include "elf-bfd.h"
+#include "bfdlink.h"
+#include "elf/aarch64.h"
+
+static bfd_reloc_status_type
+bfd_elf_aarch64_put_addend (bfd *abfd,
+ bfd_byte *address,
+ reloc_howto_type *howto, bfd_signed_vma addend);
+
+#define IS_AARCH64_TLS_RELOC(R_TYPE) \
+ ((R_TYPE) == R_AARCH64_TLSGD_ADR_PAGE21 \
+ || (R_TYPE) == R_AARCH64_TLSGD_ADD_LO12_NC \
+ || (R_TYPE) == R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 \
+ || (R_TYPE) == R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC \
+ || (R_TYPE) == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 \
+ || (R_TYPE) == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC \
+ || (R_TYPE) == R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 \
+ || (R_TYPE) == R_AARCH64_TLSLE_ADD_TPREL_LO12 \
+ || (R_TYPE) == R_AARCH64_TLSLE_ADD_TPREL_HI12 \
+ || (R_TYPE) == R_AARCH64_TLSLE_ADD_TPREL_LO12_NC \
+ || (R_TYPE) == R_AARCH64_TLSLE_MOVW_TPREL_G2 \
+ || (R_TYPE) == R_AARCH64_TLSLE_MOVW_TPREL_G1 \
+ || (R_TYPE) == R_AARCH64_TLSLE_MOVW_TPREL_G1_NC \
+ || (R_TYPE) == R_AARCH64_TLSLE_MOVW_TPREL_G0 \
+ || (R_TYPE) == R_AARCH64_TLSLE_MOVW_TPREL_G0_NC \
+ || (R_TYPE) == R_AARCH64_TLS_DTPMOD64 \
+ || (R_TYPE) == R_AARCH64_TLS_DTPREL64 \
+ || (R_TYPE) == R_AARCH64_TLS_TPREL64 \
+ || IS_AARCH64_TLSDESC_RELOC ((R_TYPE)))
+
+#define IS_AARCH64_TLSDESC_RELOC(R_TYPE) \
+ ((R_TYPE) == R_AARCH64_TLSDESC_LD64_PREL19 \
+ || (R_TYPE) == R_AARCH64_TLSDESC_ADR_PREL21 \
+ || (R_TYPE) == R_AARCH64_TLSDESC_ADR_PAGE \
+ || (R_TYPE) == R_AARCH64_TLSDESC_ADD_LO12_NC \
+ || (R_TYPE) == R_AARCH64_TLSDESC_LD64_LO12_NC \
+ || (R_TYPE) == R_AARCH64_TLSDESC_OFF_G1 \
+ || (R_TYPE) == R_AARCH64_TLSDESC_OFF_G0_NC \
+ || (R_TYPE) == R_AARCH64_TLSDESC_LDR \
+ || (R_TYPE) == R_AARCH64_TLSDESC_ADD \
+ || (R_TYPE) == R_AARCH64_TLSDESC_CALL \
+ || (R_TYPE) == R_AARCH64_TLSDESC)
+
+#define ELIMINATE_COPY_RELOCS 0
+
+/* Return the relocation section associated with NAME. HTAB is the
+ bfd's elf64_aarch64_link_hash_entry. */
+#define RELOC_SECTION(HTAB, NAME) \
+ ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
+
+/* Return size of a relocation entry. HTAB is the bfd's
+ elf64_aarch64_link_hash_entry. */
+#define RELOC_SIZE(HTAB) (sizeof (Elf64_External_Rela))
+
+/* Return function to swap relocations in. HTAB is the bfd's
+ elf64_aarch64_link_hash_entry. */
+#define SWAP_RELOC_IN(HTAB) (bfd_elf64_swap_reloca_in)
+
+/* Return function to swap relocations out. HTAB is the bfd's
+ elf64_aarch64_link_hash_entry. */
+#define SWAP_RELOC_OUT(HTAB) (bfd_elf64_swap_reloca_out)
+
+/* GOT Entry size - 8 bytes. */
+#define GOT_ENTRY_SIZE (8)
+#define PLT_ENTRY_SIZE (32)
+#define PLT_SMALL_ENTRY_SIZE (16)
+#define PLT_TLSDESC_ENTRY_SIZE (32)
+
+/* Take the PAGE component of an address or offset. */
+#define PG(x) ((x) & ~ 0xfff)
+#define PG_OFFSET(x) ((x) & 0xfff)
+
+/* Encoding of the nop instruction */
+#define INSN_NOP 0xd503201f
+
+#define aarch64_compute_jump_table_size(htab) \
+ (((htab)->root.srelplt == NULL) ? 0 \
+ : (htab)->root.srelplt->reloc_count * GOT_ENTRY_SIZE)
+
+/* The first entry in a procedure linkage table looks like this
+ if the distance between the PLTGOT and the PLT is < 4GB use
+ these PLT entries. Note that the dynamic linker gets &PLTGOT[2]
+ in x16 and needs to work out PLTGOT[1] by using an address of
+ [x16,#-8]. */
+static const bfd_byte elf64_aarch64_small_plt0_entry[PLT_ENTRY_SIZE] =
+{
+ 0xf0, 0x7b, 0xbf, 0xa9, /* stp x16, x30, [sp, #-16]! */
+ 0x10, 0x00, 0x00, 0x90, /* adrp x16, (GOT+16) */
+ 0x11, 0x0A, 0x40, 0xf9, /* ldr x17, [x16, #PLT_GOT+0x10] */
+ 0x10, 0x42, 0x00, 0x91, /* add x16, x16,#PLT_GOT+0x10 */
+ 0x20, 0x02, 0x1f, 0xd6, /* br x17 */
+ 0x1f, 0x20, 0x03, 0xd5, /* nop */
+ 0x1f, 0x20, 0x03, 0xd5, /* nop */
+ 0x1f, 0x20, 0x03, 0xd5, /* nop */
+};
+
+/* Per function entry in a procedure linkage table looks like this
+ if the distance between the PLTGOT and the PLT is < 4GB use
+ these PLT entries. */
+static const bfd_byte elf64_aarch64_small_plt_entry[PLT_SMALL_ENTRY_SIZE] =
+{
+ 0x10, 0x00, 0x00, 0x90, /* adrp x16, PLTGOT + n * 8 */
+ 0x11, 0x02, 0x40, 0xf9, /* ldr x17, [x16, PLTGOT + n * 8] */
+ 0x10, 0x02, 0x00, 0x91, /* add x16, x16, :lo12:PLTGOT + n * 8 */
+ 0x20, 0x02, 0x1f, 0xd6, /* br x17. */
+};
+
+static const bfd_byte
+elf64_aarch64_tlsdesc_small_plt_entry[PLT_TLSDESC_ENTRY_SIZE] =
+{
+ 0xe2, 0x0f, 0xbf, 0xa9, /* stp x2, x3, [sp, #-16]! */
+ 0x02, 0x00, 0x00, 0x90, /* adrp x2, 0 */
+ 0x03, 0x00, 0x00, 0x90, /* adrp x3, 0 */
+ 0x42, 0x08, 0x40, 0xF9, /* ldr x2, [x2, #0] */
+ 0x63, 0x00, 0x00, 0x91, /* add x3, x3, 0 */
+ 0x40, 0x00, 0x1F, 0xD6, /* br x2 */
+ 0x1f, 0x20, 0x03, 0xd5, /* nop */
+ 0x1f, 0x20, 0x03, 0xd5, /* nop */
+};
+
+#define elf_info_to_howto elf64_aarch64_info_to_howto
+#define elf_info_to_howto_rel elf64_aarch64_info_to_howto
+
+#define AARCH64_ELF_ABI_VERSION 0
+#define AARCH64_ELF_OS_ABI_VERSION 0
+
+/* In case we're on a 32-bit machine, construct a 64-bit "-1" value. */
+#define ALL_ONES (~ (bfd_vma) 0)
+
+static reloc_howto_type elf64_aarch64_howto_none =
+ HOWTO (R_AARCH64_NONE, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_NONE", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE); /* pcrel_offset */
+
+static reloc_howto_type elf64_aarch64_howto_dynrelocs[] =
+{
+ HOWTO (R_AARCH64_COPY, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_COPY", /* name */
+ TRUE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_GLOB_DAT, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_GLOB_DAT", /* name */
+ TRUE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_JUMP_SLOT, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_JUMP_SLOT", /* name */
+ TRUE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_RELATIVE, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_RELATIVE", /* name */
+ TRUE, /* partial_inplace */
+ ALL_ONES, /* src_mask */
+ ALL_ONES, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLS_DTPMOD64, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLS_DTPMOD64", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ALL_ONES, /* dst_mask */
+ FALSE), /* pc_reloffset */
+
+ HOWTO (R_AARCH64_TLS_DTPREL64, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLS_DTPREL64", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ALL_ONES, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLS_TPREL64, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLS_TPREL64", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ALL_ONES, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSDESC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ALL_ONES, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+};
+
+/* Note: code such as elf64_aarch64_reloc_type_lookup expect to use e.g.
+ R_AARCH64_PREL64 as an index into this, and find the R_AARCH64_PREL64 HOWTO
+ in that slot. */
+
+static reloc_howto_type elf64_aarch64_howto_table[] =
+{
+ /* Basic data relocations. */
+
+ HOWTO (R_AARCH64_NULL, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_NULL", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* .xword: (S+A) */
+ HOWTO (R_AARCH64_ABS64, /* type */
+ 0, /* rightshift */
+ 4, /* size (4 = long long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_ABS64", /* name */
+ FALSE, /* partial_inplace */
+ ALL_ONES, /* src_mask */
+ ALL_ONES, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* .word: (S+A) */
+ HOWTO (R_AARCH64_ABS32, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_ABS32", /* name */
+ FALSE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* .half: (S+A) */
+ HOWTO (R_AARCH64_ABS16, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_ABS16", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* .xword: (S+A-P) */
+ HOWTO (R_AARCH64_PREL64, /* type */
+ 0, /* rightshift */
+ 4, /* size (4 = long long) */
+ 64, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_PREL64", /* name */
+ FALSE, /* partial_inplace */
+ ALL_ONES, /* src_mask */
+ ALL_ONES, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* .word: (S+A-P) */
+ HOWTO (R_AARCH64_PREL32, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_PREL32", /* name */
+ FALSE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* .half: (S+A-P) */
+ HOWTO (R_AARCH64_PREL16, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_PREL16", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* Group relocations to create a 16, 32, 48 or 64 bit
+ unsigned data or abs address inline. */
+
+ /* MOVZ: ((S+A) >> 0) & 0xffff */
+ HOWTO (R_AARCH64_MOVW_UABS_G0, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_MOVW_UABS_G0", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MOVK: ((S+A) >> 0) & 0xffff [no overflow check] */
+ HOWTO (R_AARCH64_MOVW_UABS_G0_NC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_MOVW_UABS_G0_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MOVZ: ((S+A) >> 16) & 0xffff */
+ HOWTO (R_AARCH64_MOVW_UABS_G1, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_MOVW_UABS_G1", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MOVK: ((S+A) >> 16) & 0xffff [no overflow check] */
+ HOWTO (R_AARCH64_MOVW_UABS_G1_NC, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_MOVW_UABS_G1_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MOVZ: ((S+A) >> 32) & 0xffff */
+ HOWTO (R_AARCH64_MOVW_UABS_G2, /* type */
+ 32, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_MOVW_UABS_G2", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MOVK: ((S+A) >> 32) & 0xffff [no overflow check] */
+ HOWTO (R_AARCH64_MOVW_UABS_G2_NC, /* type */
+ 32, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_MOVW_UABS_G2_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MOVZ: ((S+A) >> 48) & 0xffff */
+ HOWTO (R_AARCH64_MOVW_UABS_G3, /* type */
+ 48, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_MOVW_UABS_G3", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Group relocations to create high part of a 16, 32, 48 or 64 bit
+ signed data or abs address inline. Will change instruction
+ to MOVN or MOVZ depending on sign of calculated value. */
+
+ /* MOV[ZN]: ((S+A) >> 0) & 0xffff */
+ HOWTO (R_AARCH64_MOVW_SABS_G0, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_MOVW_SABS_G0", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MOV[ZN]: ((S+A) >> 16) & 0xffff */
+ HOWTO (R_AARCH64_MOVW_SABS_G1, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_MOVW_SABS_G1", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MOV[ZN]: ((S+A) >> 32) & 0xffff */
+ HOWTO (R_AARCH64_MOVW_SABS_G2, /* type */
+ 32, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_MOVW_SABS_G2", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+/* Relocations to generate 19, 21 and 33 bit PC-relative load/store
+ addresses: PG(x) is (x & ~0xfff). */
+
+ /* LD-lit: ((S+A-P) >> 2) & 0x7ffff */
+ HOWTO (R_AARCH64_LD_PREL_LO19, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 19, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_LD_PREL_LO19", /* name */
+ FALSE, /* partial_inplace */
+ 0x7ffff, /* src_mask */
+ 0x7ffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* ADR: (S+A-P) & 0x1fffff */
+ HOWTO (R_AARCH64_ADR_PREL_LO21, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_ADR_PREL_LO21", /* name */
+ FALSE, /* partial_inplace */
+ 0x1fffff, /* src_mask */
+ 0x1fffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* ADRP: ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */
+ HOWTO (R_AARCH64_ADR_PREL_PG_HI21, /* type */
+ 12, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_ADR_PREL_PG_HI21", /* name */
+ FALSE, /* partial_inplace */
+ 0x1fffff, /* src_mask */
+ 0x1fffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* ADRP: ((PG(S+A)-PG(P)) >> 12) & 0x1fffff [no overflow check] */
+ HOWTO (R_AARCH64_ADR_PREL_PG_HI21_NC, /* type */
+ 12, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_ADR_PREL_PG_HI21_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0x1fffff, /* src_mask */
+ 0x1fffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* ADD: (S+A) & 0xfff [no overflow check] */
+ HOWTO (R_AARCH64_ADD_ABS_LO12_NC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 10, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_ADD_ABS_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffc00, /* src_mask */
+ 0x3ffc00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* LD/ST8: (S+A) & 0xfff */
+ HOWTO (R_AARCH64_LDST8_ABS_LO12_NC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_LDST8_ABS_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xfff, /* src_mask */
+ 0xfff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Relocations for control-flow instructions. */
+
+ /* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff */
+ HOWTO (R_AARCH64_TSTBR14, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 14, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TSTBR14", /* name */
+ FALSE, /* partial_inplace */
+ 0x3fff, /* src_mask */
+ 0x3fff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* B.cond: ((S+A-P) >> 2) & 0x7ffff */
+ HOWTO (R_AARCH64_CONDBR19, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 19, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_CONDBR19", /* name */
+ FALSE, /* partial_inplace */
+ 0x7ffff, /* src_mask */
+ 0x7ffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ EMPTY_HOWTO (281),
+
+ /* B: ((S+A-P) >> 2) & 0x3ffffff */
+ HOWTO (R_AARCH64_JUMP26, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 26, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_JUMP26", /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffffff, /* src_mask */
+ 0x3ffffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* BL: ((S+A-P) >> 2) & 0x3ffffff */
+ HOWTO (R_AARCH64_CALL26, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 26, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_CALL26", /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffffff, /* src_mask */
+ 0x3ffffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* LD/ST16: (S+A) & 0xffe */
+ HOWTO (R_AARCH64_LDST16_ABS_LO12_NC, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_LDST16_ABS_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xffe, /* src_mask */
+ 0xffe, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* LD/ST32: (S+A) & 0xffc */
+ HOWTO (R_AARCH64_LDST32_ABS_LO12_NC, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_LDST32_ABS_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xffc, /* src_mask */
+ 0xffc, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* LD/ST64: (S+A) & 0xff8 */
+ HOWTO (R_AARCH64_LDST64_ABS_LO12_NC, /* type */
+ 3, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_LDST64_ABS_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xff8, /* src_mask */
+ 0xff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (287),
+ EMPTY_HOWTO (288),
+ EMPTY_HOWTO (289),
+ EMPTY_HOWTO (290),
+ EMPTY_HOWTO (291),
+ EMPTY_HOWTO (292),
+ EMPTY_HOWTO (293),
+ EMPTY_HOWTO (294),
+ EMPTY_HOWTO (295),
+ EMPTY_HOWTO (296),
+ EMPTY_HOWTO (297),
+ EMPTY_HOWTO (298),
+
+ /* LD/ST128: (S+A) & 0xff0 */
+ HOWTO (R_AARCH64_LDST128_ABS_LO12_NC, /* type */
+ 4, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_LDST128_ABS_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xff0, /* src_mask */
+ 0xff0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (300),
+ EMPTY_HOWTO (301),
+ EMPTY_HOWTO (302),
+ EMPTY_HOWTO (303),
+ EMPTY_HOWTO (304),
+ EMPTY_HOWTO (305),
+ EMPTY_HOWTO (306),
+ EMPTY_HOWTO (307),
+ EMPTY_HOWTO (308),
+ EMPTY_HOWTO (309),
+ EMPTY_HOWTO (310),
+
+ /* Get to the page for the GOT entry for the symbol
+ (G(S) - P) using an ADRP instruction. */
+ HOWTO (R_AARCH64_ADR_GOT_PAGE, /* type */
+ 12, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_ADR_GOT_PAGE", /* name */
+ FALSE, /* partial_inplace */
+ 0x1fffff, /* src_mask */
+ 0x1fffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* LD64: GOT offset G(S) & 0xff8 */
+ HOWTO (R_AARCH64_LD64_GOT_LO12_NC, /* type */
+ 3, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_LD64_GOT_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xff8, /* src_mask */
+ 0xff8, /* dst_mask */
+ FALSE) /* pcrel_offset */
+};
+
+static reloc_howto_type elf64_aarch64_tls_howto_table[] =
+{
+ EMPTY_HOWTO (512),
+
+ /* Get to the page for the GOT entry for the symbol
+ (G(S) - P) using an ADRP instruction. */
+ HOWTO (R_AARCH64_TLSGD_ADR_PAGE21, /* type */
+ 12, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSGD_ADR_PAGE21", /* name */
+ FALSE, /* partial_inplace */
+ 0x1fffff, /* src_mask */
+ 0x1fffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* ADD: GOT offset G(S) & 0xff8 [no overflow check] */
+ HOWTO (R_AARCH64_TLSGD_ADD_LO12_NC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSGD_ADD_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xfff, /* src_mask */
+ 0xfff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (515),
+ EMPTY_HOWTO (516),
+ EMPTY_HOWTO (517),
+ EMPTY_HOWTO (518),
+ EMPTY_HOWTO (519),
+ EMPTY_HOWTO (520),
+ EMPTY_HOWTO (521),
+ EMPTY_HOWTO (522),
+ EMPTY_HOWTO (523),
+ EMPTY_HOWTO (524),
+ EMPTY_HOWTO (525),
+ EMPTY_HOWTO (526),
+ EMPTY_HOWTO (527),
+ EMPTY_HOWTO (528),
+ EMPTY_HOWTO (529),
+ EMPTY_HOWTO (530),
+ EMPTY_HOWTO (531),
+ EMPTY_HOWTO (532),
+ EMPTY_HOWTO (533),
+ EMPTY_HOWTO (534),
+ EMPTY_HOWTO (535),
+ EMPTY_HOWTO (536),
+ EMPTY_HOWTO (537),
+ EMPTY_HOWTO (538),
+
+ HOWTO (R_AARCH64_TLSIE_MOVW_GOTTPREL_G1, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSIE_MOVW_GOTTPREL_G1", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, /* type */
+ 12, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21", /* name */
+ FALSE, /* partial_inplace */
+ 0x1fffff, /* src_mask */
+ 0x1fffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, /* type */
+ 3, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xff8, /* src_mask */
+ 0xff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSIE_LD_GOTTPREL_PREL19, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSIE_LD_GOTTPREL_PREL19", /* name */
+ FALSE, /* partial_inplace */
+ 0x1ffffc, /* src_mask */
+ 0x1ffffc, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSLE_MOVW_TPREL_G2, /* type */
+ 8, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSLE_MOVW_TPREL_G2", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSLE_MOVW_TPREL_G1, /* type */
+ 4, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSLE_MOVW_TPREL_G1", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSLE_MOVW_TPREL_G1_NC, /* type */
+ 4, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSLE_MOVW_TPREL_G1_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSLE_MOVW_TPREL_G0, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSLE_MOVW_TPREL_G0", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSLE_MOVW_TPREL_G0_NC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSLE_MOVW_TPREL_G0_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSLE_ADD_TPREL_HI12, /* type */
+ 3, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSLE_ADD_TPREL_HI12", /* name */
+ FALSE, /* partial_inplace */
+ 0xfff, /* src_mask */
+ 0xfff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSLE_ADD_TPREL_LO12, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSLE_ADD_TPREL_LO12", /* name */
+ FALSE, /* partial_inplace */
+ 0xfff, /* src_mask */
+ 0xfff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSLE_ADD_TPREL_LO12_NC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSLE_ADD_TPREL_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xfff, /* src_mask */
+ 0xfff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
+
+static reloc_howto_type elf64_aarch64_tlsdesc_howto_table[] =
+{
+ HOWTO (R_AARCH64_TLSDESC_LD64_PREL19, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC_LD64_PREL19", /* name */
+ FALSE, /* partial_inplace */
+ 0x1ffffc, /* src_mask */
+ 0x1ffffc, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSDESC_ADR_PREL21, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC_ADR_PREL21", /* name */
+ FALSE, /* partial_inplace */
+ 0x1fffff, /* src_mask */
+ 0x1fffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* Get to the page for the GOT entry for the symbol
+ (G(S) - P) using an ADRP instruction. */
+ HOWTO (R_AARCH64_TLSDESC_ADR_PAGE, /* type */
+ 12, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC_ADR_PAGE", /* name */
+ FALSE, /* partial_inplace */
+ 0x1fffff, /* src_mask */
+ 0x1fffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* LD64: GOT offset G(S) & 0xfff. */
+ HOWTO (R_AARCH64_TLSDESC_LD64_LO12_NC, /* type */
+ 3, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC_LD64_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xfff, /* src_mask */
+ 0xfff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* ADD: GOT offset G(S) & 0xfff. */
+ HOWTO (R_AARCH64_TLSDESC_ADD_LO12_NC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC_ADD_LO12_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xfff, /* src_mask */
+ 0xfff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSDESC_OFF_G1, /* type */
+ 4, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC_OFF_G1", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSDESC_OFF_G0_NC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC_OFF_G0_NC", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSDESC_LDR, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC_LDR", /* name */
+ FALSE, /* partial_inplace */
+ 0x0, /* src_mask */
+ 0x0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSDESC_ADD, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC_ADD", /* name */
+ FALSE, /* partial_inplace */
+ 0x0, /* src_mask */
+ 0x0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_AARCH64_TLSDESC_CALL, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AARCH64_TLSDESC_CALL", /* name */
+ FALSE, /* partial_inplace */
+ 0x0, /* src_mask */
+ 0x0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
+
+static reloc_howto_type *
+elf64_aarch64_howto_from_type (unsigned int r_type)
+{
+ if (r_type >= R_AARCH64_static_min && r_type < R_AARCH64_static_max)
+ return &elf64_aarch64_howto_table[r_type - R_AARCH64_static_min];
+
+ if (r_type >= R_AARCH64_tls_min && r_type < R_AARCH64_tls_max)
+ return &elf64_aarch64_tls_howto_table[r_type - R_AARCH64_tls_min];
+
+ if (r_type >= R_AARCH64_tlsdesc_min && r_type < R_AARCH64_tlsdesc_max)
+ return &elf64_aarch64_tlsdesc_howto_table[r_type - R_AARCH64_tlsdesc_min];
+
+ if (r_type >= R_AARCH64_dyn_min && r_type < R_AARCH64_dyn_max)
+ return &elf64_aarch64_howto_dynrelocs[r_type - R_AARCH64_dyn_min];
+
+ switch (r_type)
+ {
+ case R_AARCH64_NONE:
+ return &elf64_aarch64_howto_none;
+
+ }
+ bfd_set_error (bfd_error_bad_value);
+ return NULL;
+}
+
+static void
+elf64_aarch64_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, arelent *bfd_reloc,
+ Elf_Internal_Rela *elf_reloc)
+{
+ unsigned int r_type;
+
+ r_type = ELF64_R_TYPE (elf_reloc->r_info);
+ bfd_reloc->howto = elf64_aarch64_howto_from_type (r_type);
+}
+
+struct elf64_aarch64_reloc_map
+{
+ bfd_reloc_code_real_type bfd_reloc_val;
+ unsigned int elf_reloc_val;
+};
+
+/* All entries in this list must also be present in
+ elf64_aarch64_howto_table. */
+static const struct elf64_aarch64_reloc_map elf64_aarch64_reloc_map[] =
+{
+ {BFD_RELOC_NONE, R_AARCH64_NONE},
+
+ /* Basic data relocations. */
+ {BFD_RELOC_CTOR, R_AARCH64_ABS64},
+ {BFD_RELOC_64, R_AARCH64_ABS64},
+ {BFD_RELOC_32, R_AARCH64_ABS32},
+ {BFD_RELOC_16, R_AARCH64_ABS16},
+ {BFD_RELOC_64_PCREL, R_AARCH64_PREL64},
+ {BFD_RELOC_32_PCREL, R_AARCH64_PREL32},
+ {BFD_RELOC_16_PCREL, R_AARCH64_PREL16},
+
+ /* Group relocations to low order bits of a 16, 32, 48 or 64 bit
+ value inline. */
+ {BFD_RELOC_AARCH64_MOVW_G0_NC, R_AARCH64_MOVW_UABS_G0_NC},
+ {BFD_RELOC_AARCH64_MOVW_G1_NC, R_AARCH64_MOVW_UABS_G1_NC},
+ {BFD_RELOC_AARCH64_MOVW_G2_NC, R_AARCH64_MOVW_UABS_G2_NC},
+
+ /* Group relocations to create high bits of a 16, 32, 48 or 64 bit
+ signed value inline. */
+ {BFD_RELOC_AARCH64_MOVW_G0_S, R_AARCH64_MOVW_SABS_G0},
+ {BFD_RELOC_AARCH64_MOVW_G1_S, R_AARCH64_MOVW_SABS_G1},
+ {BFD_RELOC_AARCH64_MOVW_G2_S, R_AARCH64_MOVW_SABS_G2},
+
+ /* Group relocations to create high bits of a 16, 32, 48 or 64 bit
+ unsigned value inline. */
+ {BFD_RELOC_AARCH64_MOVW_G0, R_AARCH64_MOVW_UABS_G0},
+ {BFD_RELOC_AARCH64_MOVW_G1, R_AARCH64_MOVW_UABS_G1},
+ {BFD_RELOC_AARCH64_MOVW_G2, R_AARCH64_MOVW_UABS_G2},
+ {BFD_RELOC_AARCH64_MOVW_G3, R_AARCH64_MOVW_UABS_G3},
+
+ /* Relocations to generate 19, 21 and 33 bit PC-relative load/store. */
+ {BFD_RELOC_AARCH64_LD_LO19_PCREL, R_AARCH64_LD_PREL_LO19},
+ {BFD_RELOC_AARCH64_ADR_LO21_PCREL, R_AARCH64_ADR_PREL_LO21},
+ {BFD_RELOC_AARCH64_ADR_HI21_PCREL, R_AARCH64_ADR_PREL_PG_HI21},
+ {BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL, R_AARCH64_ADR_PREL_PG_HI21_NC},
+ {BFD_RELOC_AARCH64_ADD_LO12, R_AARCH64_ADD_ABS_LO12_NC},
+ {BFD_RELOC_AARCH64_LDST8_LO12, R_AARCH64_LDST8_ABS_LO12_NC},
+ {BFD_RELOC_AARCH64_LDST16_LO12, R_AARCH64_LDST16_ABS_LO12_NC},
+ {BFD_RELOC_AARCH64_LDST32_LO12, R_AARCH64_LDST32_ABS_LO12_NC},
+ {BFD_RELOC_AARCH64_LDST64_LO12, R_AARCH64_LDST64_ABS_LO12_NC},
+ {BFD_RELOC_AARCH64_LDST128_LO12, R_AARCH64_LDST128_ABS_LO12_NC},
+
+ /* Relocations for control-flow instructions. */
+ {BFD_RELOC_AARCH64_TSTBR14, R_AARCH64_TSTBR14},
+ {BFD_RELOC_AARCH64_BRANCH19, R_AARCH64_CONDBR19},
+ {BFD_RELOC_AARCH64_JUMP26, R_AARCH64_JUMP26},
+ {BFD_RELOC_AARCH64_CALL26, R_AARCH64_CALL26},
+
+ /* Relocations for PIC. */
+ {BFD_RELOC_AARCH64_ADR_GOT_PAGE, R_AARCH64_ADR_GOT_PAGE},
+ {BFD_RELOC_AARCH64_LD64_GOT_LO12_NC, R_AARCH64_LD64_GOT_LO12_NC},
+
+ /* Relocations for TLS. */
+ {BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21, R_AARCH64_TLSGD_ADR_PAGE21},
+ {BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC, R_AARCH64_TLSGD_ADD_LO12_NC},
+ {BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
+ R_AARCH64_TLSIE_MOVW_GOTTPREL_G1},
+ {BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
+ R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC},
+ {BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
+ R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21},
+ {BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC,
+ R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC},
+ {BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19,
+ R_AARCH64_TLSIE_LD_GOTTPREL_PREL19},
+ {BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2, R_AARCH64_TLSLE_MOVW_TPREL_G2},
+ {BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1, R_AARCH64_TLSLE_MOVW_TPREL_G1},
+ {BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
+ R_AARCH64_TLSLE_MOVW_TPREL_G1_NC},
+ {BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0, R_AARCH64_TLSLE_MOVW_TPREL_G0},
+ {BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
+ R_AARCH64_TLSLE_MOVW_TPREL_G0_NC},
+ {BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12, R_AARCH64_TLSLE_ADD_TPREL_LO12},
+ {BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12, R_AARCH64_TLSLE_ADD_TPREL_HI12},
+ {BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
+ R_AARCH64_TLSLE_ADD_TPREL_LO12_NC},
+ {BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19, R_AARCH64_TLSDESC_LD64_PREL19},
+ {BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21, R_AARCH64_TLSDESC_ADR_PREL21},
+ {BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE, R_AARCH64_TLSDESC_ADR_PAGE},
+ {BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC, R_AARCH64_TLSDESC_ADD_LO12_NC},
+ {BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC, R_AARCH64_TLSDESC_LD64_LO12_NC},
+ {BFD_RELOC_AARCH64_TLSDESC_OFF_G1, R_AARCH64_TLSDESC_OFF_G1},
+ {BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC, R_AARCH64_TLSDESC_OFF_G0_NC},
+ {BFD_RELOC_AARCH64_TLSDESC_LDR, R_AARCH64_TLSDESC_LDR},
+ {BFD_RELOC_AARCH64_TLSDESC_ADD, R_AARCH64_TLSDESC_ADD},
+ {BFD_RELOC_AARCH64_TLSDESC_CALL, R_AARCH64_TLSDESC_CALL},
+ {BFD_RELOC_AARCH64_TLS_DTPMOD64, R_AARCH64_TLS_DTPMOD64},
+ {BFD_RELOC_AARCH64_TLS_DTPREL64, R_AARCH64_TLS_DTPREL64},
+ {BFD_RELOC_AARCH64_TLS_TPREL64, R_AARCH64_TLS_TPREL64},
+ {BFD_RELOC_AARCH64_TLSDESC, R_AARCH64_TLSDESC},
+};
+
+static reloc_howto_type *
+elf64_aarch64_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ bfd_reloc_code_real_type code)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (elf64_aarch64_reloc_map); i++)
+ if (elf64_aarch64_reloc_map[i].bfd_reloc_val == code)
+ return elf64_aarch64_howto_from_type
+ (elf64_aarch64_reloc_map[i].elf_reloc_val);
+
+ bfd_set_error (bfd_error_bad_value);
+ return NULL;
+}
+
+static reloc_howto_type *
+elf64_aarch64_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ const char *r_name)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (elf64_aarch64_howto_table); i++)
+ if (elf64_aarch64_howto_table[i].name != NULL
+ && strcasecmp (elf64_aarch64_howto_table[i].name, r_name) == 0)
+ return &elf64_aarch64_howto_table[i];
+
+ return NULL;
+}
+
+#define TARGET_LITTLE_SYM bfd_elf64_littleaarch64_vec
+#define TARGET_LITTLE_NAME "elf64-littleaarch64"
+#define TARGET_BIG_SYM bfd_elf64_bigaarch64_vec
+#define TARGET_BIG_NAME "elf64-bigaarch64"
+
+typedef unsigned long int insn32;
+
+/* The linker script knows the section names for placement.
+ The entry_names are used to do simple name mangling on the stubs.
+ Given a function name, and its type, the stub can be found. The
+ name can be changed. The only requirement is the %s be present. */
+#define STUB_ENTRY_NAME "__%s_veneer"
+
+/* The name of the dynamic interpreter. This is put in the .interp
+ section. */
+#define ELF_DYNAMIC_INTERPRETER "/lib/ld.so.1"
+
+#define AARCH64_MAX_FWD_BRANCH_OFFSET \
+ (((1 << 25) - 1) << 2)
+#define AARCH64_MAX_BWD_BRANCH_OFFSET \
+ (-((1 << 25) << 2))
+
+#define AARCH64_MAX_ADRP_IMM ((1 << 20) - 1)
+#define AARCH64_MIN_ADRP_IMM (-(1 << 20))
+
+static int
+aarch64_valid_for_adrp_p (bfd_vma value, bfd_vma place)
+{
+ bfd_signed_vma offset = (bfd_signed_vma) (PG (value) - PG (place)) >> 12;
+ return offset <= AARCH64_MAX_ADRP_IMM && offset >= AARCH64_MIN_ADRP_IMM;
+}
+
+static int
+aarch64_valid_branch_p (bfd_vma value, bfd_vma place)
+{
+ bfd_signed_vma offset = (bfd_signed_vma) (value - place);
+ return (offset <= AARCH64_MAX_FWD_BRANCH_OFFSET
+ && offset >= AARCH64_MAX_BWD_BRANCH_OFFSET);
+}
+
+static const uint32_t aarch64_adrp_branch_stub [] =
+{
+ 0x90000010, /* adrp ip0, X */
+ /* R_AARCH64_ADR_HI21_PCREL(X) */
+ 0x91000210, /* add ip0, ip0, :lo12:X */
+ /* R_AARCH64_ADD_ABS_LO12_NC(X) */
+ 0xd61f0200, /* br ip0 */
+};
+
+static const uint32_t aarch64_long_branch_stub[] =
+{
+ 0x58000090, /* ldr ip0, 1f */
+ 0x10000011, /* adr ip1, #0 */
+ 0x8b110210, /* add ip0, ip0, ip1 */
+ 0xd61f0200, /* br ip0 */
+ 0x00000000, /* 1: .xword
+ R_AARCH64_PREL64(X) + 12
+ */
+ 0x00000000,
+};
+
+/* Section name for stubs is the associated section name plus this
+ string. */
+#define STUB_SUFFIX ".stub"
+
+enum elf64_aarch64_stub_type
+{
+ aarch64_stub_none,
+ aarch64_stub_adrp_branch,
+ aarch64_stub_long_branch,
+};
+
+struct elf64_aarch64_stub_hash_entry
+{
+ /* Base hash table entry structure. */
+ struct bfd_hash_entry root;
+
+ /* The stub section. */
+ asection *stub_sec;
+
+ /* Offset within stub_sec of the beginning of this stub. */
+ bfd_vma stub_offset;
+
+ /* Given the symbol's value and its section we can determine its final
+ value when building the stubs (so the stub knows where to jump). */
+ bfd_vma target_value;
+ asection *target_section;
+
+ enum elf64_aarch64_stub_type stub_type;
+
+ /* The symbol table entry, if any, that this was derived from. */
+ struct elf64_aarch64_link_hash_entry *h;
+
+ /* Destination symbol type */
+ unsigned char st_type;
+
+ /* Where this stub is being called from, or, in the case of combined
+ stub sections, the first input section in the group. */
+ asection *id_sec;
+
+ /* The name for the local symbol at the start of this stub. The
+ stub name in the hash table has to be unique; this does not, so
+ it can be friendlier. */
+ char *output_name;
+};
+
+/* Used to build a map of a section. This is required for mixed-endian
+ code/data. */
+
+typedef struct elf64_elf_section_map
+{
+ bfd_vma vma;
+ char type;
+}
+elf64_aarch64_section_map;
+
+
+typedef struct _aarch64_elf_section_data
+{
+ struct bfd_elf_section_data elf;
+ unsigned int mapcount;
+ unsigned int mapsize;
+ elf64_aarch64_section_map *map;
+}
+_aarch64_elf_section_data;
+
+#define elf64_aarch64_section_data(sec) \
+ ((_aarch64_elf_section_data *) elf_section_data (sec))
+
+/* The size of the thread control block. */
+#define TCB_SIZE 16
+
+struct elf_aarch64_local_symbol
+{
+ unsigned int got_type;
+ bfd_signed_vma got_refcount;
+ bfd_vma got_offset;
+
+ /* Offset of the GOTPLT entry reserved for the TLS descriptor. The
+ offset is from the end of the jump table and reserved entries
+ within the PLTGOT.
+
+ The magic value (bfd_vma) -1 indicates that an offset has not be
+ allocated. */
+ bfd_vma tlsdesc_got_jump_table_offset;
+};
+
+struct elf_aarch64_obj_tdata
+{
+ struct elf_obj_tdata root;
+
+ /* local symbol descriptors */
+ struct elf_aarch64_local_symbol *locals;
+
+ /* Zero to warn when linking objects with incompatible enum sizes. */
+ int no_enum_size_warning;
+
+ /* Zero to warn when linking objects with incompatible wchar_t sizes. */
+ int no_wchar_size_warning;
+};
+
+#define elf_aarch64_tdata(bfd) \
+ ((struct elf_aarch64_obj_tdata *) (bfd)->tdata.any)
+
+#define elf64_aarch64_locals(bfd) (elf_aarch64_tdata (bfd)->locals)
+
+#define is_aarch64_elf(bfd) \
+ (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
+ && elf_tdata (bfd) != NULL \
+ && elf_object_id (bfd) == AARCH64_ELF_DATA)
+
+static bfd_boolean
+elf64_aarch64_mkobject (bfd *abfd)
+{
+ return bfd_elf_allocate_object (abfd, sizeof (struct elf_aarch64_obj_tdata),
+ AARCH64_ELF_DATA);
+}
+
+/* The AArch64 linker needs to keep track of the number of relocs that it
+ decides to copy in check_relocs for each symbol. This is so that
+ it can discard PC relative relocs if it doesn't need them when
+ linking with -Bsymbolic. We store the information in a field
+ extending the regular ELF linker hash table. */
+
+/* This structure keeps track of the number of relocs we have copied
+ for a given symbol. */
+struct elf64_aarch64_relocs_copied
+{
+ /* Next section. */
+ struct elf64_aarch64_relocs_copied *next;
+ /* A section in dynobj. */
+ asection *section;
+ /* Number of relocs copied in this section. */
+ bfd_size_type count;
+ /* Number of PC-relative relocs copied in this section. */
+ bfd_size_type pc_count;
+};
+
+#define elf64_aarch64_hash_entry(ent) \
+ ((struct elf64_aarch64_link_hash_entry *)(ent))
+
+#define GOT_UNKNOWN 0
+#define GOT_NORMAL 1
+#define GOT_TLS_GD 2
+#define GOT_TLS_IE 4
+#define GOT_TLSDESC_GD 8
+
+#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLSDESC_GD))
+
+/* AArch64 ELF linker hash entry. */
+struct elf64_aarch64_link_hash_entry
+{
+ struct elf_link_hash_entry root;
+
+ /* Track dynamic relocs copied for this symbol. */
+ struct elf_dyn_relocs *dyn_relocs;
+
+ /* Number of PC relative relocs copied for this symbol. */
+ struct elf64_aarch64_relocs_copied *relocs_copied;
+
+ /* Since PLT entries have variable size, we need to record the
+ index into .got.plt instead of recomputing it from the PLT
+ offset. */
+ bfd_signed_vma plt_got_offset;
+
+ /* Bit mask representing the type of GOT entry(s) if any required by
+ this symbol. */
+ unsigned int got_type;
+
+ /* A pointer to the most recently used stub hash entry against this
+ symbol. */
+ struct elf64_aarch64_stub_hash_entry *stub_cache;
+
+ /* Offset of the GOTPLT entry reserved for the TLS descriptor. The offset
+ is from the end of the jump table and reserved entries within the PLTGOT.
+
+ The magic value (bfd_vma) -1 indicates that an offset has not
+ be allocated. */
+ bfd_vma tlsdesc_got_jump_table_offset;
+};
+
+static unsigned int
+elf64_aarch64_symbol_got_type (struct elf_link_hash_entry *h,
+ bfd *abfd,
+ unsigned long r_symndx)
+{
+ if (h)
+ return elf64_aarch64_hash_entry (h)->got_type;
+
+ if (! elf64_aarch64_locals (abfd))
+ return GOT_UNKNOWN;
+
+ return elf64_aarch64_locals (abfd)[r_symndx].got_type;
+}
+
+/* Traverse an AArch64 ELF linker hash table. */
+#define elf64_aarch64_link_hash_traverse(table, func, info) \
+ (elf_link_hash_traverse \
+ (&(table)->root, \
+ (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
+ (info)))
+
+/* Get the AArch64 elf linker hash table from a link_info structure. */
+#define elf64_aarch64_hash_table(info) \
+ ((struct elf64_aarch64_link_hash_table *) ((info)->hash))
+
+#define aarch64_stub_hash_lookup(table, string, create, copy) \
+ ((struct elf64_aarch64_stub_hash_entry *) \
+ bfd_hash_lookup ((table), (string), (create), (copy)))
+
+/* AArch64 ELF linker hash table. */
+struct elf64_aarch64_link_hash_table
+{
+ /* The main hash table. */
+ struct elf_link_hash_table root;
+
+ /* Nonzero to force PIC branch veneers. */
+ int pic_veneer;
+
+ /* The number of bytes in the initial entry in the PLT. */
+ bfd_size_type plt_header_size;
+
+ /* The number of bytes in the subsequent PLT etries. */
+ bfd_size_type plt_entry_size;
+
+ /* Short-cuts to get to dynamic linker sections. */
+ asection *sdynbss;
+ asection *srelbss;
+
+ /* Small local sym cache. */
+ struct sym_cache sym_cache;
+
+ /* For convenience in allocate_dynrelocs. */
+ bfd *obfd;
+
+ /* The amount of space used by the reserved portion of the sgotplt
+ section, plus whatever space is used by the jump slots. */
+ bfd_vma sgotplt_jump_table_size;
+
+ /* The stub hash table. */
+ struct bfd_hash_table stub_hash_table;
+
+ /* Linker stub bfd. */
+ bfd *stub_bfd;
+
+ /* Linker call-backs. */
+ asection *(*add_stub_section) (const char *, asection *);
+ void (*layout_sections_again) (void);
+
+ /* Array to keep track of which stub sections have been created, and
+ information on stub grouping. */
+ struct map_stub
+ {
+ /* This is the section to which stubs in the group will be
+ attached. */
+ asection *link_sec;
+ /* The stub section. */
+ asection *stub_sec;
+ } *stub_group;
+
+ /* Assorted information used by elf64_aarch64_size_stubs. */
+ unsigned int bfd_count;
+ int top_index;
+ asection **input_list;
+
+ /* The offset into splt of the PLT entry for the TLS descriptor
+ resolver. Special values are 0, if not necessary (or not found
+ to be necessary yet), and -1 if needed but not determined
+ yet. */
+ bfd_vma tlsdesc_plt;
+
+ /* The GOT offset for the lazy trampoline. Communicated to the
+ loader via DT_TLSDESC_GOT. The magic value (bfd_vma) -1
+ indicates an offset is not allocated. */
+ bfd_vma dt_tlsdesc_got;
+};
+
+
+/* Return non-zero if the indicated VALUE has overflowed the maximum
+ range expressible by a unsigned number with the indicated number of
+ BITS. */
+
+static bfd_reloc_status_type
+aarch64_unsigned_overflow (bfd_vma value, unsigned int bits)
+{
+ bfd_vma lim;
+ if (bits >= sizeof (bfd_vma) * 8)
+ return bfd_reloc_ok;
+ lim = (bfd_vma) 1 << bits;
+ if (value >= lim)
+ return bfd_reloc_overflow;
+ return bfd_reloc_ok;
+}
+
+
+/* Return non-zero if the indicated VALUE has overflowed the maximum
+ range expressible by an signed number with the indicated number of
+ BITS. */
+
+static bfd_reloc_status_type
+aarch64_signed_overflow (bfd_vma value, unsigned int bits)
+{
+ bfd_signed_vma svalue = (bfd_signed_vma) value;
+ bfd_signed_vma lim;
+
+ if (bits >= sizeof (bfd_vma) * 8)
+ return bfd_reloc_ok;
+ lim = (bfd_signed_vma) 1 << (bits - 1);
+ if (svalue < -lim || svalue >= lim)
+ return bfd_reloc_overflow;
+ return bfd_reloc_ok;
+}
+
+/* Create an entry in an AArch64 ELF linker hash table. */
+
+static struct bfd_hash_entry *
+elf64_aarch64_link_hash_newfunc (struct bfd_hash_entry *entry,
+ struct bfd_hash_table *table,
+ const char *string)
+{
+ struct elf64_aarch64_link_hash_entry *ret =
+ (struct elf64_aarch64_link_hash_entry *) entry;
+
+ /* Allocate the structure if it has not already been allocated by a
+ subclass. */
+ if (ret == NULL)
+ ret = bfd_hash_allocate (table,
+ sizeof (struct elf64_aarch64_link_hash_entry));
+ if (ret == NULL)
+ return (struct bfd_hash_entry *) ret;
+
+ /* Call the allocation method of the superclass. */
+ ret = ((struct elf64_aarch64_link_hash_entry *)
+ _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
+ table, string));
+ if (ret != NULL)
+ {
+ ret->dyn_relocs = NULL;
+ ret->relocs_copied = NULL;
+ ret->got_type = GOT_UNKNOWN;
+ ret->plt_got_offset = (bfd_vma) - 1;
+ ret->stub_cache = NULL;
+ ret->tlsdesc_got_jump_table_offset = (bfd_vma) - 1;
+ }
+
+ return (struct bfd_hash_entry *) ret;
+}
+
+/* Initialize an entry in the stub hash table. */
+
+static struct bfd_hash_entry *
+stub_hash_newfunc (struct bfd_hash_entry *entry,
+ struct bfd_hash_table *table, const char *string)
+{
+ /* Allocate the structure if it has not already been allocated by a
+ subclass. */
+ if (entry == NULL)
+ {
+ entry = bfd_hash_allocate (table,
+ sizeof (struct
+ elf64_aarch64_stub_hash_entry));
+ if (entry == NULL)
+ return entry;
+ }
+
+ /* Call the allocation method of the superclass. */
+ entry = bfd_hash_newfunc (entry, table, string);
+ if (entry != NULL)
+ {
+ struct elf64_aarch64_stub_hash_entry *eh;
+
+ /* Initialize the local fields. */
+ eh = (struct elf64_aarch64_stub_hash_entry *) entry;
+ eh->stub_sec = NULL;
+ eh->stub_offset = 0;
+ eh->target_value = 0;
+ eh->target_section = NULL;
+ eh->stub_type = aarch64_stub_none;
+ eh->h = NULL;
+ eh->id_sec = NULL;
+ }
+
+ return entry;
+}
+
+
+/* Copy the extra info we tack onto an elf_link_hash_entry. */
+
+static void
+elf64_aarch64_copy_indirect_symbol (struct bfd_link_info *info,
+ struct elf_link_hash_entry *dir,
+ struct elf_link_hash_entry *ind)
+{
+ struct elf64_aarch64_link_hash_entry *edir, *eind;
+
+ edir = (struct elf64_aarch64_link_hash_entry *) dir;
+ eind = (struct elf64_aarch64_link_hash_entry *) ind;
+
+ if (eind->dyn_relocs != NULL)
+ {
+ if (edir->dyn_relocs != NULL)
+ {
+ struct elf_dyn_relocs **pp;
+ struct elf_dyn_relocs *p;
+
+ /* Add reloc counts against the indirect sym to the direct sym
+ list. Merge any entries against the same section. */
+ for (pp = &eind->dyn_relocs; (p = *pp) != NULL;)
+ {
+ struct elf_dyn_relocs *q;
+
+ for (q = edir->dyn_relocs; q != NULL; q = q->next)
+ if (q->sec == p->sec)
+ {
+ q->pc_count += p->pc_count;
+ q->count += p->count;
+ *pp = p->next;
+ break;
+ }
+ if (q == NULL)
+ pp = &p->next;
+ }
+ *pp = edir->dyn_relocs;
+ }
+
+ edir->dyn_relocs = eind->dyn_relocs;
+ eind->dyn_relocs = NULL;
+ }
+
+ if (eind->relocs_copied != NULL)
+ {
+ if (edir->relocs_copied != NULL)
+ {
+ struct elf64_aarch64_relocs_copied **pp;
+ struct elf64_aarch64_relocs_copied *p;
+
+ /* Add reloc counts against the indirect sym to the direct sym
+ list. Merge any entries against the same section. */
+ for (pp = &eind->relocs_copied; (p = *pp) != NULL;)
+ {
+ struct elf64_aarch64_relocs_copied *q;
+
+ for (q = edir->relocs_copied; q != NULL; q = q->next)
+ if (q->section == p->section)
+ {
+ q->pc_count += p->pc_count;
+ q->count += p->count;
+ *pp = p->next;
+ break;
+ }
+ if (q == NULL)
+ pp = &p->next;
+ }
+ *pp = edir->relocs_copied;
+ }
+
+ edir->relocs_copied = eind->relocs_copied;
+ eind->relocs_copied = NULL;
+ }
+
+ if (ind->root.type == bfd_link_hash_indirect)
+ {
+ /* Copy over PLT info. */
+ if (dir->got.refcount <= 0)
+ {
+ edir->got_type = eind->got_type;
+ eind->got_type = GOT_UNKNOWN;
+ }
+ }
+
+ _bfd_elf_link_hash_copy_indirect (info, dir, ind);
+}
+
+/* Create an AArch64 elf linker hash table. */
+
+static struct bfd_link_hash_table *
+elf64_aarch64_link_hash_table_create (bfd *abfd)
+{
+ struct elf64_aarch64_link_hash_table *ret;
+ bfd_size_type amt = sizeof (struct elf64_aarch64_link_hash_table);
+
+ ret = bfd_malloc (amt);
+ if (ret == NULL)
+ return NULL;
+
+ if (!_bfd_elf_link_hash_table_init
+ (&ret->root, abfd, elf64_aarch64_link_hash_newfunc,
+ sizeof (struct elf64_aarch64_link_hash_entry), AARCH64_ELF_DATA))
+ {
+ free (ret);
+ return NULL;
+ }
+
+ ret->sdynbss = NULL;
+ ret->srelbss = NULL;
+
+ ret->plt_header_size = PLT_ENTRY_SIZE;
+ ret->plt_entry_size = PLT_SMALL_ENTRY_SIZE;
+
+ ret->sym_cache.abfd = NULL;
+ ret->obfd = abfd;
+
+ ret->stub_bfd = NULL;
+ ret->add_stub_section = NULL;
+ ret->layout_sections_again = NULL;
+ ret->stub_group = NULL;
+ ret->bfd_count = 0;
+ ret->top_index = 0;
+ ret->input_list = NULL;
+ ret->tlsdesc_plt = 0;
+ ret->dt_tlsdesc_got = (bfd_vma) - 1;
+
+ if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
+ sizeof (struct elf64_aarch64_stub_hash_entry)))
+ {
+ free (ret);
+ return NULL;
+ }
+
+ return &ret->root.root;
+}
+
+/* Free the derived linker hash table. */
+
+static void
+elf64_aarch64_hash_table_free (struct bfd_link_hash_table *hash)
+{
+ struct elf64_aarch64_link_hash_table *ret
+ = (struct elf64_aarch64_link_hash_table *) hash;
+
+ bfd_hash_table_free (&ret->stub_hash_table);
+ _bfd_generic_link_hash_table_free (hash);
+}
+
+static bfd_vma
+aarch64_resolve_relocation (unsigned int r_type, bfd_vma place, bfd_vma value,
+ bfd_vma addend, bfd_boolean weak_undef_p)
+{
+ switch (r_type)
+ {
+ case R_AARCH64_TLSDESC_CALL:
+ case R_AARCH64_NONE:
+ case R_AARCH64_NULL:
+ break;
+
+ case R_AARCH64_ADR_PREL_LO21:
+ case R_AARCH64_CONDBR19:
+ case R_AARCH64_LD_PREL_LO19:
+ case R_AARCH64_PREL16:
+ case R_AARCH64_PREL32:
+ case R_AARCH64_PREL64:
+ case R_AARCH64_TSTBR14:
+ if (weak_undef_p)
+ value = place;
+ value = value + addend - place;
+ break;
+
+ case R_AARCH64_CALL26:
+ case R_AARCH64_JUMP26:
+ value = value + addend - place;
+ break;
+
+ case R_AARCH64_ABS16:
+ case R_AARCH64_ABS32:
+ case R_AARCH64_MOVW_SABS_G0:
+ case R_AARCH64_MOVW_SABS_G1:
+ case R_AARCH64_MOVW_SABS_G2:
+ case R_AARCH64_MOVW_UABS_G0:
+ case R_AARCH64_MOVW_UABS_G0_NC:
+ case R_AARCH64_MOVW_UABS_G1:
+ case R_AARCH64_MOVW_UABS_G1_NC:
+ case R_AARCH64_MOVW_UABS_G2:
+ case R_AARCH64_MOVW_UABS_G2_NC:
+ case R_AARCH64_MOVW_UABS_G3:
+ value = value + addend;
+ break;
+
+ case R_AARCH64_ADR_PREL_PG_HI21:
+ case R_AARCH64_ADR_PREL_PG_HI21_NC:
+ if (weak_undef_p)
+ value = PG (place);
+ value = PG (value + addend) - PG (place);
+ break;
+
+ case R_AARCH64_ADR_GOT_PAGE:
+ case R_AARCH64_TLSDESC_ADR_PAGE:
+ case R_AARCH64_TLSGD_ADR_PAGE21:
+ case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ value = PG (value + addend) - PG (place);
+ break;
+
+ case R_AARCH64_ADD_ABS_LO12_NC:
+ case R_AARCH64_LD64_GOT_LO12_NC:
+ case R_AARCH64_LDST8_ABS_LO12_NC:
+ case R_AARCH64_LDST16_ABS_LO12_NC:
+ case R_AARCH64_LDST32_ABS_LO12_NC:
+ case R_AARCH64_LDST64_ABS_LO12_NC:
+ case R_AARCH64_LDST128_ABS_LO12_NC:
+ case R_AARCH64_TLSDESC_ADD_LO12_NC:
+ case R_AARCH64_TLSDESC_ADD:
+ case R_AARCH64_TLSDESC_LD64_LO12_NC:
+ case R_AARCH64_TLSDESC_LDR:
+ case R_AARCH64_TLSGD_ADD_LO12_NC:
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+ value = PG_OFFSET (value + addend);
+ break;
+
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+ value = (value + addend) & (bfd_vma) 0xffff0000;
+ break;
+ case R_AARCH64_TLSLE_ADD_TPREL_HI12:
+ value = (value + addend) & (bfd_vma) 0xfff000;
+ break;
+
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+ value = (value + addend) & (bfd_vma) 0xffff;
+ break;
+
+ case R_AARCH64_TLSLE_MOVW_TPREL_G2:
+ value = (value + addend) & ~(bfd_vma) 0xffffffff;
+ value -= place & ~(bfd_vma) 0xffffffff;
+ break;
+ }
+ return value;
+}
+
+static bfd_boolean
+aarch64_relocate (unsigned int r_type, bfd *input_bfd, asection *input_section,
+ bfd_vma offset, bfd_vma value)
+{
+ reloc_howto_type *howto;
+ bfd_vma place;
+
+ howto = elf64_aarch64_howto_from_type (r_type);
+ place = (input_section->output_section->vma + input_section->output_offset
+ + offset);
+ value = aarch64_resolve_relocation (r_type, place, value, 0, FALSE);
+ return bfd_elf_aarch64_put_addend (input_bfd,
+ input_section->contents + offset,
+ howto, value);
+}
+
+static enum elf64_aarch64_stub_type
+aarch64_select_branch_stub (bfd_vma value, bfd_vma place)
+{
+ if (aarch64_valid_for_adrp_p (value, place))
+ return aarch64_stub_adrp_branch;
+ return aarch64_stub_long_branch;
+}
+
+/* Determine the type of stub needed, if any, for a call. */
+
+static enum elf64_aarch64_stub_type
+aarch64_type_of_stub (struct bfd_link_info *info,
+ asection *input_sec,
+ const Elf_Internal_Rela *rel,
+ unsigned char st_type,
+ struct elf64_aarch64_link_hash_entry *hash,
+ bfd_vma destination)
+{
+ bfd_vma location;
+ bfd_signed_vma branch_offset;
+ unsigned int r_type;
+ struct elf64_aarch64_link_hash_table *globals;
+ enum elf64_aarch64_stub_type stub_type = aarch64_stub_none;
+ bfd_boolean via_plt_p;
+
+ if (st_type != STT_FUNC)
+ return stub_type;
+
+ globals = elf64_aarch64_hash_table (info);
+ via_plt_p = (globals->root.splt != NULL && hash != NULL
+ && hash->root.plt.offset != (bfd_vma) - 1);
+
+ if (via_plt_p)
+ return stub_type;
+
+ /* Determine where the call point is. */
+ location = (input_sec->output_offset
+ + input_sec->output_section->vma + rel->r_offset);
+
+ branch_offset = (bfd_signed_vma) (destination - location);
+
+ r_type = ELF64_R_TYPE (rel->r_info);
+
+ /* We don't want to redirect any old unconditional jump in this way,
+ only one which is being used for a sibcall, where it is
+ acceptable for the IP0 and IP1 registers to be clobbered. */
+ if ((r_type == R_AARCH64_CALL26 || r_type == R_AARCH64_JUMP26)
+ && (branch_offset > AARCH64_MAX_FWD_BRANCH_OFFSET
+ || branch_offset < AARCH64_MAX_BWD_BRANCH_OFFSET))
+ {
+ stub_type = aarch64_stub_long_branch;
+ }
+
+ return stub_type;
+}
+
+/* Build a name for an entry in the stub hash table. */
+
+static char *
+elf64_aarch64_stub_name (const asection *input_section,
+ const asection *sym_sec,
+ const struct elf64_aarch64_link_hash_entry *hash,
+ const Elf_Internal_Rela *rel)
+{
+ char *stub_name;
+ bfd_size_type len;
+
+ if (hash)
+ {
+ len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 16 + 1;
+ stub_name = bfd_malloc (len);
+ if (stub_name != NULL)
+ snprintf (stub_name, len, "%08x_%s+%" BFD_VMA_FMT "x",
+ (unsigned int) input_section->id,
+ hash->root.root.root.string,
+ rel->r_addend);
+ }
+ else
+ {
+ len = 8 + 1 + 8 + 1 + 8 + 1 + 16 + 1;
+ stub_name = bfd_malloc (len);
+ if (stub_name != NULL)
+ snprintf (stub_name, len, "%08x_%x:%x+%" BFD_VMA_FMT "x",
+ (unsigned int) input_section->id,
+ (unsigned int) sym_sec->id,
+ (unsigned int) ELF64_R_SYM (rel->r_info),
+ rel->r_addend);
+ }
+
+ return stub_name;
+}
+
+/* Look up an entry in the stub hash. Stub entries are cached because
+ creating the stub name takes a bit of time. */
+
+static struct elf64_aarch64_stub_hash_entry *
+elf64_aarch64_get_stub_entry (const asection *input_section,
+ const asection *sym_sec,
+ struct elf_link_hash_entry *hash,
+ const Elf_Internal_Rela *rel,
+ struct elf64_aarch64_link_hash_table *htab)
+{
+ struct elf64_aarch64_stub_hash_entry *stub_entry;
+ struct elf64_aarch64_link_hash_entry *h =
+ (struct elf64_aarch64_link_hash_entry *) hash;
+ const asection *id_sec;
+
+ if ((input_section->flags & SEC_CODE) == 0)
+ return NULL;
+
+ /* If this input section is part of a group of sections sharing one
+ stub section, then use the id of the first section in the group.
+ Stub names need to include a section id, as there may well be
+ more than one stub used to reach say, printf, and we need to
+ distinguish between them. */
+ id_sec = htab->stub_group[input_section->id].link_sec;
+
+ if (h != NULL && h->stub_cache != NULL
+ && h->stub_cache->h == h && h->stub_cache->id_sec == id_sec)
+ {
+ stub_entry = h->stub_cache;
+ }
+ else
+ {
+ char *stub_name;
+
+ stub_name = elf64_aarch64_stub_name (id_sec, sym_sec, h, rel);
+ if (stub_name == NULL)
+ return NULL;
+
+ stub_entry = aarch64_stub_hash_lookup (&htab->stub_hash_table,
+ stub_name, FALSE, FALSE);
+ if (h != NULL)
+ h->stub_cache = stub_entry;
+
+ free (stub_name);
+ }
+
+ return stub_entry;
+}
+
+/* Add a new stub entry to the stub hash. Not all fields of the new
+ stub entry are initialised. */
+
+static struct elf64_aarch64_stub_hash_entry *
+elf64_aarch64_add_stub (const char *stub_name,
+ asection *section,
+ struct elf64_aarch64_link_hash_table *htab)
+{
+ asection *link_sec;
+ asection *stub_sec;
+ struct elf64_aarch64_stub_hash_entry *stub_entry;
+
+ link_sec = htab->stub_group[section->id].link_sec;
+ stub_sec = htab->stub_group[section->id].stub_sec;
+ if (stub_sec == NULL)
+ {
+ stub_sec = htab->stub_group[link_sec->id].stub_sec;
+ if (stub_sec == NULL)
+ {
+ size_t namelen;
+ bfd_size_type len;
+ char *s_name;
+
+ namelen = strlen (link_sec->name);
+ len = namelen + sizeof (STUB_SUFFIX);
+ s_name = bfd_alloc (htab->stub_bfd, len);
+ if (s_name == NULL)
+ return NULL;
+
+ memcpy (s_name, link_sec->name, namelen);
+ memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
+ stub_sec = (*htab->add_stub_section) (s_name, link_sec);
+ if (stub_sec == NULL)
+ return NULL;
+ htab->stub_group[link_sec->id].stub_sec = stub_sec;
+ }
+ htab->stub_group[section->id].stub_sec = stub_sec;
+ }
+
+ /* Enter this entry into the linker stub hash table. */
+ stub_entry = aarch64_stub_hash_lookup (&htab->stub_hash_table, stub_name,
+ TRUE, FALSE);
+ if (stub_entry == NULL)
+ {
+ (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
+ section->owner, stub_name);
+ return NULL;
+ }
+
+ stub_entry->stub_sec = stub_sec;
+ stub_entry->stub_offset = 0;
+ stub_entry->id_sec = link_sec;
+
+ return stub_entry;
+}
+
+static bfd_boolean
+aarch64_build_one_stub (struct bfd_hash_entry *gen_entry,
+ void *in_arg ATTRIBUTE_UNUSED)
+{
+ struct elf64_aarch64_stub_hash_entry *stub_entry;
+ asection *stub_sec;
+ bfd *stub_bfd;
+ bfd_byte *loc;
+ bfd_vma sym_value;
+ unsigned int template_size;
+ const uint32_t *template;
+ unsigned int i;
+
+ /* Massage our args to the form they really have. */
+ stub_entry = (struct elf64_aarch64_stub_hash_entry *) gen_entry;
+
+ stub_sec = stub_entry->stub_sec;
+
+ /* Make a note of the offset within the stubs for this entry. */
+ stub_entry->stub_offset = stub_sec->size;
+ loc = stub_sec->contents + stub_entry->stub_offset;
+
+ stub_bfd = stub_sec->owner;
+
+ /* This is the address of the stub destination. */
+ sym_value = (stub_entry->target_value
+ + stub_entry->target_section->output_offset
+ + stub_entry->target_section->output_section->vma);
+
+ if (stub_entry->stub_type == aarch64_stub_long_branch)
+ {
+ bfd_vma place = (stub_entry->stub_offset + stub_sec->output_section->vma
+ + stub_sec->output_offset);
+
+ /* See if we can relax the stub. */
+ if (aarch64_valid_for_adrp_p (sym_value, place))
+ stub_entry->stub_type = aarch64_select_branch_stub (sym_value, place);
+ }
+
+ switch (stub_entry->stub_type)
+ {
+ case aarch64_stub_adrp_branch:
+ template = aarch64_adrp_branch_stub;
+ template_size = sizeof (aarch64_adrp_branch_stub);
+ break;
+ case aarch64_stub_long_branch:
+ template = aarch64_long_branch_stub;
+ template_size = sizeof (aarch64_long_branch_stub);
+ break;
+ default:
+ BFD_FAIL ();
+ return FALSE;
+ }
+
+ for (i = 0; i < (template_size / sizeof template[0]); i++)
+ {
+ bfd_putl32 (template[i], loc);
+ loc += 4;
+ }
+
+ template_size = (template_size + 7) & ~7;
+ stub_sec->size += template_size;
+
+ switch (stub_entry->stub_type)
+ {
+ case aarch64_stub_adrp_branch:
+ if (aarch64_relocate (R_AARCH64_ADR_PREL_PG_HI21, stub_bfd, stub_sec,
+ stub_entry->stub_offset, sym_value))
+ /* The stub would not have been relaxed if the offset was out
+ of range. */
+ BFD_FAIL ();
+
+ _bfd_final_link_relocate
+ (elf64_aarch64_howto_from_type (R_AARCH64_ADD_ABS_LO12_NC),
+ stub_bfd,
+ stub_sec,
+ stub_sec->contents,
+ stub_entry->stub_offset + 4,
+ sym_value,
+ 0);
+ break;
+
+ case aarch64_stub_long_branch:
+ /* We want the value relative to the address 12 bytes back from the
+ value itself. */
+ _bfd_final_link_relocate (elf64_aarch64_howto_from_type
+ (R_AARCH64_PREL64), stub_bfd, stub_sec,
+ stub_sec->contents,
+ stub_entry->stub_offset + 16,
+ sym_value + 12, 0);
+ break;
+ default:
+ break;
+ }
+
+ return TRUE;
+}
+
+/* As above, but don't actually build the stub. Just bump offset so
+ we know stub section sizes. */
+
+static bfd_boolean
+aarch64_size_one_stub (struct bfd_hash_entry *gen_entry,
+ void *in_arg ATTRIBUTE_UNUSED)
+{
+ struct elf64_aarch64_stub_hash_entry *stub_entry;
+ int size;
+
+ /* Massage our args to the form they really have. */
+ stub_entry = (struct elf64_aarch64_stub_hash_entry *) gen_entry;
+
+ switch (stub_entry->stub_type)
+ {
+ case aarch64_stub_adrp_branch:
+ size = sizeof (aarch64_adrp_branch_stub);
+ break;
+ case aarch64_stub_long_branch:
+ size = sizeof (aarch64_long_branch_stub);
+ break;
+ default:
+ BFD_FAIL ();
+ return FALSE;
+ break;
+ }
+
+ size = (size + 7) & ~7;
+ stub_entry->stub_sec->size += size;
+ return TRUE;
+}
+
+/* External entry points for sizing and building linker stubs. */
+
+/* Set up various things so that we can make a list of input sections
+ for each output section included in the link. Returns -1 on error,
+ 0 when no stubs will be needed, and 1 on success. */
+
+int
+elf64_aarch64_setup_section_lists (bfd *output_bfd,
+ struct bfd_link_info *info)
+{
+ bfd *input_bfd;
+ unsigned int bfd_count;
+ int top_id, top_index;
+ asection *section;
+ asection **input_list, **list;
+ bfd_size_type amt;
+ struct elf64_aarch64_link_hash_table *htab =
+ elf64_aarch64_hash_table (info);
+
+ if (!is_elf_hash_table (htab))
+ return 0;
+
+ /* Count the number of input BFDs and find the top input section id. */
+ for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
+ input_bfd != NULL; input_bfd = input_bfd->link_next)
+ {
+ bfd_count += 1;
+ for (section = input_bfd->sections;
+ section != NULL; section = section->next)
+ {
+ if (top_id < section->id)
+ top_id = section->id;
+ }
+ }
+ htab->bfd_count = bfd_count;
+
+ amt = sizeof (struct map_stub) * (top_id + 1);
+ htab->stub_group = bfd_zmalloc (amt);
+ if (htab->stub_group == NULL)
+ return -1;
+
+ /* We can't use output_bfd->section_count here to find the top output
+ section index as some sections may have been removed, and
+ _bfd_strip_section_from_output doesn't renumber the indices. */
+ for (section = output_bfd->sections, top_index = 0;
+ section != NULL; section = section->next)
+ {
+ if (top_index < section->index)
+ top_index = section->index;
+ }
+
+ htab->top_index = top_index;
+ amt = sizeof (asection *) * (top_index + 1);
+ input_list = bfd_malloc (amt);
+ htab->input_list = input_list;
+ if (input_list == NULL)
+ return -1;
+
+ /* For sections we aren't interested in, mark their entries with a
+ value we can check later. */
+ list = input_list + top_index;
+ do
+ *list = bfd_abs_section_ptr;
+ while (list-- != input_list);
+
+ for (section = output_bfd->sections;
+ section != NULL; section = section->next)
+ {
+ if ((section->flags & SEC_CODE) != 0)
+ input_list[section->index] = NULL;
+ }
+
+ return 1;
+}
+
+/* Used by elf64_aarch64_next_input_section and group_sections. */
+#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
+
+/* The linker repeatedly calls this function for each input section,
+ in the order that input sections are linked into output sections.
+ Build lists of input sections to determine groupings between which
+ we may insert linker stubs. */
+
+void
+elf64_aarch64_next_input_section (struct bfd_link_info *info, asection *isec)
+{
+ struct elf64_aarch64_link_hash_table *htab =
+ elf64_aarch64_hash_table (info);
+
+ if (isec->output_section->index <= htab->top_index)
+ {
+ asection **list = htab->input_list + isec->output_section->index;
+
+ if (*list != bfd_abs_section_ptr)
+ {
+ /* Steal the link_sec pointer for our list. */
+ /* This happens to make the list in reverse order,
+ which is what we want. */
+ PREV_SEC (isec) = *list;
+ *list = isec;
+ }
+ }
+}
+
+/* See whether we can group stub sections together. Grouping stub
+ sections may result in fewer stubs. More importantly, we need to
+ put all .init* and .fini* stubs at the beginning of the .init or
+ .fini output sections respectively, because glibc splits the
+ _init and _fini functions into multiple parts. Putting a stub in
+ the middle of a function is not a good idea. */
+
+static void
+group_sections (struct elf64_aarch64_link_hash_table *htab,
+ bfd_size_type stub_group_size,
+ bfd_boolean stubs_always_before_branch)
+{
+ asection **list = htab->input_list + htab->top_index;
+
+ do
+ {
+ asection *tail = *list;
+
+ if (tail == bfd_abs_section_ptr)
+ continue;
+
+ while (tail != NULL)
+ {
+ asection *curr;
+ asection *prev;
+ bfd_size_type total;
+
+ curr = tail;
+ total = tail->size;
+ while ((prev = PREV_SEC (curr)) != NULL
+ && ((total += curr->output_offset - prev->output_offset)
+ < stub_group_size))
+ curr = prev;
+
+ /* OK, the size from the start of CURR to the end is less
+ than stub_group_size and thus can be handled by one stub
+ section. (Or the tail section is itself larger than
+ stub_group_size, in which case we may be toast.)
+ We should really be keeping track of the total size of
+ stubs added here, as stubs contribute to the final output
+ section size. */
+ do
+ {
+ prev = PREV_SEC (tail);
+ /* Set up this stub group. */
+ htab->stub_group[tail->id].link_sec = curr;
+ }
+ while (tail != curr && (tail = prev) != NULL);
+
+ /* But wait, there's more! Input sections up to stub_group_size
+ bytes before the stub section can be handled by it too. */
+ if (!stubs_always_before_branch)
+ {
+ total = 0;
+ while (prev != NULL
+ && ((total += tail->output_offset - prev->output_offset)
+ < stub_group_size))
+ {
+ tail = prev;
+ prev = PREV_SEC (tail);
+ htab->stub_group[tail->id].link_sec = curr;
+ }
+ }
+ tail = prev;
+ }
+ }
+ while (list-- != htab->input_list);
+
+ free (htab->input_list);
+}
+
+#undef PREV_SEC
+
+/* Determine and set the size of the stub section for a final link.
+
+ The basic idea here is to examine all the relocations looking for
+ PC-relative calls to a target that is unreachable with a "bl"
+ instruction. */
+
+bfd_boolean
+elf64_aarch64_size_stubs (bfd *output_bfd,
+ bfd *stub_bfd,
+ struct bfd_link_info *info,
+ bfd_signed_vma group_size,
+ asection * (*add_stub_section) (const char *,
+ asection *),
+ void (*layout_sections_again) (void))
+{
+ bfd_size_type stub_group_size;
+ bfd_boolean stubs_always_before_branch;
+ bfd_boolean stub_changed = 0;
+ struct elf64_aarch64_link_hash_table *htab = elf64_aarch64_hash_table (info);
+
+ /* Propagate mach to stub bfd, because it may not have been
+ finalized when we created stub_bfd. */
+ bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
+ bfd_get_mach (output_bfd));
+
+ /* Stash our params away. */
+ htab->stub_bfd = stub_bfd;
+ htab->add_stub_section = add_stub_section;
+ htab->layout_sections_again = layout_sections_again;
+ stubs_always_before_branch = group_size < 0;
+ if (group_size < 0)
+ stub_group_size = -group_size;
+ else
+ stub_group_size = group_size;
+
+ if (stub_group_size == 1)
+ {
+ /* Default values. */
+ /* Aarch64 branch range is +-128MB. The value used is 1MB less. */
+ stub_group_size = 127 * 1024 * 1024;
+ }
+
+ group_sections (htab, stub_group_size, stubs_always_before_branch);
+
+ while (1)
+ {
+ bfd *input_bfd;
+ unsigned int bfd_indx;
+ asection *stub_sec;
+
+ for (input_bfd = info->input_bfds, bfd_indx = 0;
+ input_bfd != NULL; input_bfd = input_bfd->link_next, bfd_indx++)
+ {
+ Elf_Internal_Shdr *symtab_hdr;
+ asection *section;
+ Elf_Internal_Sym *local_syms = NULL;
+
+ /* We'll need the symbol table in a second. */
+ symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
+ if (symtab_hdr->sh_info == 0)
+ continue;
+
+ /* Walk over each section attached to the input bfd. */
+ for (section = input_bfd->sections;
+ section != NULL; section = section->next)
+ {
+ Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
+
+ /* If there aren't any relocs, then there's nothing more
+ to do. */
+ if ((section->flags & SEC_RELOC) == 0
+ || section->reloc_count == 0
+ || (section->flags & SEC_CODE) == 0)
+ continue;
+
+ /* If this section is a link-once section that will be
+ discarded, then don't create any stubs. */
+ if (section->output_section == NULL
+ || section->output_section->owner != output_bfd)
+ continue;
+
+ /* Get the relocs. */
+ internal_relocs
+ = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
+ NULL, info->keep_memory);
+ if (internal_relocs == NULL)
+ goto error_ret_free_local;
+
+ /* Now examine each relocation. */
+ irela = internal_relocs;
+ irelaend = irela + section->reloc_count;
+ for (; irela < irelaend; irela++)
+ {
+ unsigned int r_type, r_indx;
+ enum elf64_aarch64_stub_type stub_type;
+ struct elf64_aarch64_stub_hash_entry *stub_entry;
+ asection *sym_sec;
+ bfd_vma sym_value;
+ bfd_vma destination;
+ struct elf64_aarch64_link_hash_entry *hash;
+ const char *sym_name;
+ char *stub_name;
+ const asection *id_sec;
+ unsigned char st_type;
+ bfd_size_type len;
+
+ r_type = ELF64_R_TYPE (irela->r_info);
+ r_indx = ELF64_R_SYM (irela->r_info);
+
+ if (r_type >= (unsigned int) R_AARCH64_end)
+ {
+ bfd_set_error (bfd_error_bad_value);
+ error_ret_free_internal:
+ if (elf_section_data (section)->relocs == NULL)
+ free (internal_relocs);
+ goto error_ret_free_local;
+ }
+
+ /* Only look for stubs on unconditional branch and
+ branch and link instructions. */
+ if (r_type != (unsigned int) R_AARCH64_CALL26
+ && r_type != (unsigned int) R_AARCH64_JUMP26)
+ continue;
+
+ /* Now determine the call target, its name, value,
+ section. */
+ sym_sec = NULL;
+ sym_value = 0;
+ destination = 0;
+ hash = NULL;
+ sym_name = NULL;
+ if (r_indx < symtab_hdr->sh_info)
+ {
+ /* It's a local symbol. */
+ Elf_Internal_Sym *sym;
+ Elf_Internal_Shdr *hdr;
+
+ if (local_syms == NULL)
+ {
+ local_syms
+ = (Elf_Internal_Sym *) symtab_hdr->contents;
+ if (local_syms == NULL)
+ local_syms
+ = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
+ symtab_hdr->sh_info, 0,
+ NULL, NULL, NULL);
+ if (local_syms == NULL)
+ goto error_ret_free_internal;
+ }
+
+ sym = local_syms + r_indx;
+ hdr = elf_elfsections (input_bfd)[sym->st_shndx];
+ sym_sec = hdr->bfd_section;
+ if (!sym_sec)
+ /* This is an undefined symbol. It can never
+ be resolved. */
+ continue;
+
+ if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
+ sym_value = sym->st_value;
+ destination = (sym_value + irela->r_addend
+ + sym_sec->output_offset
+ + sym_sec->output_section->vma);
+ st_type = ELF_ST_TYPE (sym->st_info);
+ sym_name
+ = bfd_elf_string_from_elf_section (input_bfd,
+ symtab_hdr->sh_link,
+ sym->st_name);
+ }
+ else
+ {
+ int e_indx;
+
+ e_indx = r_indx - symtab_hdr->sh_info;
+ hash = ((struct elf64_aarch64_link_hash_entry *)
+ elf_sym_hashes (input_bfd)[e_indx]);
+
+ while (hash->root.root.type == bfd_link_hash_indirect
+ || hash->root.root.type == bfd_link_hash_warning)
+ hash = ((struct elf64_aarch64_link_hash_entry *)
+ hash->root.root.u.i.link);
+
+ if (hash->root.root.type == bfd_link_hash_defined
+ || hash->root.root.type == bfd_link_hash_defweak)
+ {
+ struct elf64_aarch64_link_hash_table *globals =
+ elf64_aarch64_hash_table (info);
+ sym_sec = hash->root.root.u.def.section;
+ sym_value = hash->root.root.u.def.value;
+ /* For a destination in a shared library,
+ use the PLT stub as target address to
+ decide whether a branch stub is
+ needed. */
+ if (globals->root.splt != NULL && hash != NULL
+ && hash->root.plt.offset != (bfd_vma) - 1)
+ {
+ sym_sec = globals->root.splt;
+ sym_value = hash->root.plt.offset;
+ if (sym_sec->output_section != NULL)
+ destination = (sym_value
+ + sym_sec->output_offset
+ +
+ sym_sec->output_section->vma);
+ }
+ else if (sym_sec->output_section != NULL)
+ destination = (sym_value + irela->r_addend
+ + sym_sec->output_offset
+ + sym_sec->output_section->vma);
+ }
+ else if (hash->root.root.type == bfd_link_hash_undefined
+ || (hash->root.root.type
+ == bfd_link_hash_undefweak))
+ {
+ /* For a shared library, use the PLT stub as
+ target address to decide whether a long
+ branch stub is needed.
+ For absolute code, they cannot be handled. */
+ struct elf64_aarch64_link_hash_table *globals =
+ elf64_aarch64_hash_table (info);
+
+ if (globals->root.splt != NULL && hash != NULL
+ && hash->root.plt.offset != (bfd_vma) - 1)
+ {
+ sym_sec = globals->root.splt;
+ sym_value = hash->root.plt.offset;
+ if (sym_sec->output_section != NULL)
+ destination = (sym_value
+ + sym_sec->output_offset
+ +
+ sym_sec->output_section->vma);
+ }
+ else
+ continue;
+ }
+ else
+ {
+ bfd_set_error (bfd_error_bad_value);
+ goto error_ret_free_internal;
+ }
+ st_type = ELF_ST_TYPE (hash->root.type);
+ sym_name = hash->root.root.root.string;
+ }
+
+ /* Determine what (if any) linker stub is needed. */
+ stub_type = aarch64_type_of_stub
+ (info, section, irela, st_type, hash, destination);
+ if (stub_type == aarch64_stub_none)
+ continue;
+
+ /* Support for grouping stub sections. */
+ id_sec = htab->stub_group[section->id].link_sec;
+
+ /* Get the name of this stub. */
+ stub_name = elf64_aarch64_stub_name (id_sec, sym_sec, hash,
+ irela);
+ if (!stub_name)
+ goto error_ret_free_internal;
+
+ stub_entry =
+ aarch64_stub_hash_lookup (&htab->stub_hash_table,
+ stub_name, FALSE, FALSE);
+ if (stub_entry != NULL)
+ {
+ /* The proper stub has already been created. */
+ free (stub_name);
+ continue;
+ }
+
+ stub_entry = elf64_aarch64_add_stub (stub_name, section,
+ htab);
+ if (stub_entry == NULL)
+ {
+ free (stub_name);
+ goto error_ret_free_internal;
+ }
+
+ stub_entry->target_value = sym_value;
+ stub_entry->target_section = sym_sec;
+ stub_entry->stub_type = stub_type;
+ stub_entry->h = hash;
+ stub_entry->st_type = st_type;
+
+ if (sym_name == NULL)
+ sym_name = "unnamed";
+ len = sizeof (STUB_ENTRY_NAME) + strlen (sym_name);
+ stub_entry->output_name = bfd_alloc (htab->stub_bfd, len);
+ if (stub_entry->output_name == NULL)
+ {
+ free (stub_name);
+ goto error_ret_free_internal;
+ }
+
+ snprintf (stub_entry->output_name, len, STUB_ENTRY_NAME,
+ sym_name);
+
+ stub_changed = TRUE;
+ }
+
+ /* We're done with the internal relocs, free them. */
+ if (elf_section_data (section)->relocs == NULL)
+ free (internal_relocs);
+ }
+ }
+
+ if (!stub_changed)
+ break;
+
+ /* OK, we've added some stubs. Find out the new size of the
+ stub sections. */
+ for (stub_sec = htab->stub_bfd->sections;
+ stub_sec != NULL; stub_sec = stub_sec->next)
+ stub_sec->size = 0;
+
+ bfd_hash_traverse (&htab->stub_hash_table, aarch64_size_one_stub, htab);
+
+ /* Ask the linker to do its stuff. */
+ (*htab->layout_sections_again) ();
+ stub_changed = FALSE;
+ }
+
+ return TRUE;
+
+error_ret_free_local:
+ return FALSE;
+}
+
+/* Build all the stubs associated with the current output file. The
+ stubs are kept in a hash table attached to the main linker hash
+ table. We also set up the .plt entries for statically linked PIC
+ functions here. This function is called via aarch64_elf_finish in the
+ linker. */
+
+bfd_boolean
+elf64_aarch64_build_stubs (struct bfd_link_info *info)
+{
+ asection *stub_sec;
+ struct bfd_hash_table *table;
+ struct elf64_aarch64_link_hash_table *htab;
+
+ htab = elf64_aarch64_hash_table (info);
+
+ for (stub_sec = htab->stub_bfd->sections;
+ stub_sec != NULL; stub_sec = stub_sec->next)
+ {
+ bfd_size_type size;
+
+ /* Ignore non-stub sections. */
+ if (!strstr (stub_sec->name, STUB_SUFFIX))
+ continue;
+
+ /* Allocate memory to hold the linker stubs. */
+ size = stub_sec->size;
+ stub_sec->contents = bfd_zalloc (htab->stub_bfd, size);
+ if (stub_sec->contents == NULL && size != 0)
+ return FALSE;
+ stub_sec->size = 0;
+ }
+
+ /* Build the stubs as directed by the stub hash table. */
+ table = &htab->stub_hash_table;
+ bfd_hash_traverse (table, aarch64_build_one_stub, info);
+
+ return TRUE;
+}
+
+
+/* Add an entry to the code/data map for section SEC. */
+
+static void
+elf64_aarch64_section_map_add (asection *sec, char type, bfd_vma vma)
+{
+ struct _aarch64_elf_section_data *sec_data =
+ elf64_aarch64_section_data (sec);
+ unsigned int newidx;
+
+ if (sec_data->map == NULL)
+ {
+ sec_data->map = bfd_malloc (sizeof (elf64_aarch64_section_map));
+ sec_data->mapcount = 0;
+ sec_data->mapsize = 1;
+ }
+
+ newidx = sec_data->mapcount++;
+
+ if (sec_data->mapcount > sec_data->mapsize)
+ {
+ sec_data->mapsize *= 2;
+ sec_data->map = bfd_realloc_or_free
+ (sec_data->map, sec_data->mapsize * sizeof (elf64_aarch64_section_map));
+ }
+
+ if (sec_data->map)
+ {
+ sec_data->map[newidx].vma = vma;
+ sec_data->map[newidx].type = type;
+ }
+}
+
+
+/* Initialise maps of insn/data for input BFDs. */
+void
+bfd_elf64_aarch64_init_maps (bfd *abfd)
+{
+ Elf_Internal_Sym *isymbuf;
+ Elf_Internal_Shdr *hdr;
+ unsigned int i, localsyms;
+
+ /* Make sure that we are dealing with an AArch64 elf binary. */
+ if (!is_aarch64_elf (abfd))
+ return;
+
+ if ((abfd->flags & DYNAMIC) != 0)
+ return;
+
+ hdr = &elf_symtab_hdr (abfd);
+ localsyms = hdr->sh_info;
+
+ /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
+ should contain the number of local symbols, which should come before any
+ global symbols. Mapping symbols are always local. */
+ isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL, NULL);
+
+ /* No internal symbols read? Skip this BFD. */
+ if (isymbuf == NULL)
+ return;
+
+ for (i = 0; i < localsyms; i++)
+ {
+ Elf_Internal_Sym *isym = &isymbuf[i];
+ asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
+ const char *name;
+
+ if (sec != NULL && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
+ {
+ name = bfd_elf_string_from_elf_section (abfd,
+ hdr->sh_link,
+ isym->st_name);
+
+ if (bfd_is_aarch64_special_symbol_name
+ (name, BFD_AARCH64_SPECIAL_SYM_TYPE_MAP))
+ elf64_aarch64_section_map_add (sec, name[1], isym->st_value);
+ }
+ }
+}
+
+/* Set option values needed during linking. */
+void
+bfd_elf64_aarch64_set_options (struct bfd *output_bfd,
+ struct bfd_link_info *link_info,
+ int no_enum_warn,
+ int no_wchar_warn, int pic_veneer)
+{
+ struct elf64_aarch64_link_hash_table *globals;
+
+ globals = elf64_aarch64_hash_table (link_info);
+ globals->pic_veneer = pic_veneer;
+
+ BFD_ASSERT (is_aarch64_elf (output_bfd));
+ elf_aarch64_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
+ elf_aarch64_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
+}
+
+#define MASK(n) ((1u << (n)) - 1)
+
+/* Decode the 26-bit offset of unconditional branch. */
+static inline uint32_t
+decode_branch_ofs_26 (uint32_t insn)
+{
+ return insn & MASK (26);
+}
+
+/* Decode the 19-bit offset of conditional branch and compare & branch. */
+static inline uint32_t
+decode_cond_branch_ofs_19 (uint32_t insn)
+{
+ return (insn >> 5) & MASK (19);
+}
+
+/* Decode the 19-bit offset of load literal. */
+static inline uint32_t
+decode_ld_lit_ofs_19 (uint32_t insn)
+{
+ return (insn >> 5) & MASK (19);
+}
+
+/* Decode the 14-bit offset of test & branch. */
+static inline uint32_t
+decode_tst_branch_ofs_14 (uint32_t insn)
+{
+ return (insn >> 5) & MASK (14);
+}
+
+/* Decode the 16-bit imm of move wide. */
+static inline uint32_t
+decode_movw_imm (uint32_t insn)
+{
+ return (insn >> 5) & MASK (16);
+}
+
+/* Decode the 21-bit imm of adr. */
+static inline uint32_t
+decode_adr_imm (uint32_t insn)
+{
+ return ((insn >> 29) & MASK (2)) | ((insn >> 3) & (MASK (19) << 2));
+}
+
+/* Decode the 12-bit imm of add immediate. */
+static inline uint32_t
+decode_add_imm (uint32_t insn)
+{
+ return (insn >> 10) & MASK (12);
+}
+
+
+/* Encode the 26-bit offset of unconditional branch. */
+static inline uint32_t
+reencode_branch_ofs_26 (uint32_t insn, uint32_t ofs)
+{
+ return (insn & ~MASK (26)) | (ofs & MASK (26));
+}
+
+/* Encode the 19-bit offset of conditional branch and compare & branch. */
+static inline uint32_t
+reencode_cond_branch_ofs_19 (uint32_t insn, uint32_t ofs)
+{
+ return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5);
+}
+
+/* Decode the 19-bit offset of load literal. */
+static inline uint32_t
+reencode_ld_lit_ofs_19 (uint32_t insn, uint32_t ofs)
+{
+ return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5);
+}
+
+/* Encode the 14-bit offset of test & branch. */
+static inline uint32_t
+reencode_tst_branch_ofs_14 (uint32_t insn, uint32_t ofs)
+{
+ return (insn & ~(MASK (14) << 5)) | ((ofs & MASK (14)) << 5);
+}
+
+/* Reencode the imm field of move wide. */
+static inline uint32_t
+reencode_movw_imm (uint32_t insn, uint32_t imm)
+{
+ return (insn & ~(MASK (16) << 5)) | ((imm & MASK (16)) << 5);
+}
+
+/* Reencode the imm field of adr. */
+static inline uint32_t
+reencode_adr_imm (uint32_t insn, uint32_t imm)
+{
+ return (insn & ~((MASK (2) << 29) | (MASK (19) << 5)))
+ | ((imm & MASK (2)) << 29) | ((imm & (MASK (19) << 2)) << 3);
+}
+
+/* Reencode the imm field of ld/st pos immediate. */
+static inline uint32_t
+reencode_ldst_pos_imm (uint32_t insn, uint32_t imm)
+{
+ return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10);
+}
+
+/* Reencode the imm field of add immediate. */
+static inline uint32_t
+reencode_add_imm (uint32_t insn, uint32_t imm)
+{
+ return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10);
+}
+
+/* Reencode mov[zn] to movz. */
+static inline uint32_t
+reencode_movzn_to_movz (uint32_t opcode)
+{
+ return opcode | (1 << 30);
+}
+
+/* Reencode mov[zn] to movn. */
+static inline uint32_t
+reencode_movzn_to_movn (uint32_t opcode)
+{
+ return opcode & ~(1 << 30);
+}
+
+/* Insert the addend/value into the instruction or data object being
+ relocated. */
+static bfd_reloc_status_type
+bfd_elf_aarch64_put_addend (bfd *abfd,
+ bfd_byte *address,
+ reloc_howto_type *howto, bfd_signed_vma addend)
+{
+ bfd_reloc_status_type status = bfd_reloc_ok;
+ bfd_signed_vma old_addend = addend;
+ bfd_vma contents;
+ int size;
+
+ size = bfd_get_reloc_size (howto);
+ switch (size)
+ {
+ case 2:
+ contents = bfd_get_16 (abfd, address);
+ break;
+ case 4:
+ if (howto->src_mask != 0xffffffff)
+ /* Must be 32-bit instruction, always little-endian. */
+ contents = bfd_getl32 (address);
+ else
+ /* Must be 32-bit data (endianness dependent). */
+ contents = bfd_get_32 (abfd, address);
+ break;
+ case 8:
+ contents = bfd_get_64 (abfd, address);
+ break;
+ default:
+ abort ();
+ }
+
+ switch (howto->complain_on_overflow)
+ {
+ case complain_overflow_dont:
+ break;
+ case complain_overflow_signed:
+ status = aarch64_signed_overflow (addend,
+ howto->bitsize + howto->rightshift);
+ break;
+ case complain_overflow_unsigned:
+ status = aarch64_unsigned_overflow (addend,
+ howto->bitsize + howto->rightshift);
+ break;
+ case complain_overflow_bitfield:
+ default:
+ abort ();
+ }
+
+ addend >>= howto->rightshift;
+
+ switch (howto->type)
+ {
+ case R_AARCH64_JUMP26:
+ case R_AARCH64_CALL26:
+ contents = reencode_branch_ofs_26 (contents, addend);
+ break;
+
+ case R_AARCH64_CONDBR19:
+ contents = reencode_cond_branch_ofs_19 (contents, addend);
+ break;
+
+ case R_AARCH64_TSTBR14:
+ contents = reencode_tst_branch_ofs_14 (contents, addend);
+ break;
+
+ case R_AARCH64_LD_PREL_LO19:
+ if (old_addend & ((1 << howto->rightshift) - 1))
+ return bfd_reloc_overflow;
+ contents = reencode_ld_lit_ofs_19 (contents, addend);
+ break;
+
+ case R_AARCH64_TLSDESC_CALL:
+ break;
+
+ case R_AARCH64_TLSGD_ADR_PAGE21:
+ case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ case R_AARCH64_TLSDESC_ADR_PAGE:
+ case R_AARCH64_ADR_GOT_PAGE:
+ case R_AARCH64_ADR_PREL_LO21:
+ case R_AARCH64_ADR_PREL_PG_HI21:
+ case R_AARCH64_ADR_PREL_PG_HI21_NC:
+ contents = reencode_adr_imm (contents, addend);
+ break;
+
+ case R_AARCH64_TLSGD_ADD_LO12_NC:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12:
+ case R_AARCH64_TLSLE_ADD_TPREL_HI12:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+ case R_AARCH64_TLSDESC_ADD_LO12_NC:
+ case R_AARCH64_ADD_ABS_LO12_NC:
+ /* Corresponds to: add rd, rn, #uimm12 to provide the low order
+ 12 bits of the page offset following
+ R_AARCH64_ADR_PREL_PG_HI21 which computes the
+ (pc-relative) page base. */
+ contents = reencode_add_imm (contents, addend);
+ break;
+
+ case R_AARCH64_LDST8_ABS_LO12_NC:
+ case R_AARCH64_LDST16_ABS_LO12_NC:
+ case R_AARCH64_LDST32_ABS_LO12_NC:
+ case R_AARCH64_LDST64_ABS_LO12_NC:
+ case R_AARCH64_LDST128_ABS_LO12_NC:
+ case R_AARCH64_TLSDESC_LD64_LO12_NC:
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ case R_AARCH64_LD64_GOT_LO12_NC:
+ if (old_addend & ((1 << howto->rightshift) - 1))
+ return bfd_reloc_overflow;
+ /* Used for ldr*|str* rt, [rn, #uimm12] to provide the low order
+ 12 bits of the page offset following R_AARCH64_ADR_PREL_PG_HI21
+ which computes the (pc-relative) page base. */
+ contents = reencode_ldst_pos_imm (contents, addend);
+ break;
+
+ /* Group relocations to create high bits of a 16, 32, 48 or 64
+ bit signed data or abs address inline. Will change
+ instruction to MOVN or MOVZ depending on sign of calculated
+ value. */
+
+ case R_AARCH64_TLSLE_MOVW_TPREL_G2:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+ case R_AARCH64_MOVW_SABS_G0:
+ case R_AARCH64_MOVW_SABS_G1:
+ case R_AARCH64_MOVW_SABS_G2:
+ /* NOTE: We can only come here with movz or movn. */
+ if (addend < 0)
+ {
+ /* Force use of MOVN. */
+ addend = ~addend;
+ contents = reencode_movzn_to_movn (contents);
+ }
+ else
+ {
+ /* Force use of MOVZ. */
+ contents = reencode_movzn_to_movz (contents);
+ }
+ /* fall through */
+
+ /* Group relocations to create a 16, 32, 48 or 64 bit unsigned
+ data or abs address inline. */
+
+ case R_AARCH64_MOVW_UABS_G0:
+ case R_AARCH64_MOVW_UABS_G0_NC:
+ case R_AARCH64_MOVW_UABS_G1:
+ case R_AARCH64_MOVW_UABS_G1_NC:
+ case R_AARCH64_MOVW_UABS_G2:
+ case R_AARCH64_MOVW_UABS_G2_NC:
+ case R_AARCH64_MOVW_UABS_G3:
+ contents = reencode_movw_imm (contents, addend);
+ break;
+
+ default:
+ /* Repack simple data */
+ if (howto->dst_mask & (howto->dst_mask + 1))
+ return bfd_reloc_notsupported;
+
+ contents = ((contents & ~howto->dst_mask) | (addend & howto->dst_mask));
+ break;
+ }
+
+ switch (size)
+ {
+ case 2:
+ bfd_put_16 (abfd, contents, address);
+ break;
+ case 4:
+ if (howto->dst_mask != 0xffffffff)
+ /* must be 32-bit instruction, always little-endian */
+ bfd_putl32 (contents, address);
+ else
+ /* must be 32-bit data (endianness dependent) */
+ bfd_put_32 (abfd, contents, address);
+ break;
+ case 8:
+ bfd_put_64 (abfd, contents, address);
+ break;
+ default:
+ abort ();
+ }
+
+ return status;
+}
+
+static bfd_vma
+aarch64_calculate_got_entry_vma (struct elf_link_hash_entry *h,
+ struct elf64_aarch64_link_hash_table
+ *globals, struct bfd_link_info *info,
+ bfd_vma value, bfd *output_bfd,
+ bfd_boolean *unresolved_reloc_p)
+{
+ bfd_vma off = (bfd_vma) - 1;
+ asection *basegot = globals->root.sgot;
+ bfd_boolean dyn = globals->root.dynamic_sections_created;
+
+ if (h != NULL)
+ {
+ off = h->got.offset;
+ BFD_ASSERT (off != (bfd_vma) - 1);
+ if (!WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h)
+ || (info->shared
+ && SYMBOL_REFERENCES_LOCAL (info, h))
+ || (ELF_ST_VISIBILITY (h->other)
+ && h->root.type == bfd_link_hash_undefweak))
+ {
+ /* This is actually a static link, or it is a -Bsymbolic link
+ and the symbol is defined locally. We must initialize this
+ entry in the global offset table. Since the offset must
+ always be a multiple of 8, we use the least significant bit
+ to record whether we have initialized it already.
+ When doing a dynamic link, we create a .rel(a).got relocation
+ entry to initialize the value. This is done in the
+ finish_dynamic_symbol routine. */
+ if ((off & 1) != 0)
+ off &= ~1;
+ else
+ {
+ bfd_put_64 (output_bfd, value, basegot->contents + off);
+ h->got.offset |= 1;
+ }
+ }
+ else
+ *unresolved_reloc_p = FALSE;
+
+ off = off + basegot->output_section->vma + basegot->output_offset;
+ }
+
+ return off;
+}
+
+/* Change R_TYPE to a more efficient access model where possible,
+ return the new reloc type. */
+
+static unsigned int
+aarch64_tls_transition_without_check (unsigned int r_type,
+ struct elf_link_hash_entry *h)
+{
+ bfd_boolean is_local = h == NULL;
+ switch (r_type)
+ {
+ case R_AARCH64_TLSGD_ADR_PAGE21:
+ case R_AARCH64_TLSDESC_ADR_PAGE:
+ return is_local
+ ? R_AARCH64_TLSLE_MOVW_TPREL_G1 : R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21;
+
+ case R_AARCH64_TLSGD_ADD_LO12_NC:
+ case R_AARCH64_TLSDESC_LD64_LO12_NC:
+ return is_local
+ ? R_AARCH64_TLSLE_MOVW_TPREL_G0_NC
+ : R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
+
+ case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ return is_local ? R_AARCH64_TLSLE_MOVW_TPREL_G1 : r_type;
+
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ return is_local ? R_AARCH64_TLSLE_MOVW_TPREL_G0_NC : r_type;
+
+ case R_AARCH64_TLSDESC_ADD_LO12_NC:
+ case R_AARCH64_TLSDESC_CALL:
+ /* Instructions with these relocations will become NOPs. */
+ return R_AARCH64_NONE;
+ }
+
+ return r_type;
+}
+
+static unsigned int
+aarch64_reloc_got_type (unsigned int r_type)
+{
+ switch (r_type)
+ {
+ case R_AARCH64_LD64_GOT_LO12_NC:
+ case R_AARCH64_ADR_GOT_PAGE:
+ return GOT_NORMAL;
+
+ case R_AARCH64_TLSGD_ADR_PAGE21:
+ case R_AARCH64_TLSGD_ADD_LO12_NC:
+ return GOT_TLS_GD;
+
+ case R_AARCH64_TLSDESC_ADD_LO12_NC:
+ case R_AARCH64_TLSDESC_ADR_PAGE:
+ case R_AARCH64_TLSDESC_CALL:
+ case R_AARCH64_TLSDESC_LD64_LO12_NC:
+ return GOT_TLSDESC_GD;
+
+ case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ return GOT_TLS_IE;
+
+ case R_AARCH64_TLSLE_ADD_TPREL_HI12:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G2:
+ return GOT_UNKNOWN;
+ }
+ return GOT_UNKNOWN;
+}
+
+static bfd_boolean
+aarch64_can_relax_tls (bfd *input_bfd,
+ struct bfd_link_info *info,
+ unsigned int r_type,
+ struct elf_link_hash_entry *h,
+ unsigned long r_symndx)
+{
+ unsigned int symbol_got_type;
+ unsigned int reloc_got_type;
+
+ if (! IS_AARCH64_TLS_RELOC (r_type))
+ return FALSE;
+
+ symbol_got_type = elf64_aarch64_symbol_got_type (h, input_bfd, r_symndx);
+ reloc_got_type = aarch64_reloc_got_type (r_type);
+
+ if (symbol_got_type == GOT_TLS_IE && GOT_TLS_GD_ANY_P (reloc_got_type))
+ return TRUE;
+
+ if (info->shared)
+ return FALSE;
+
+ if (h && h->root.type == bfd_link_hash_undefweak)
+ return FALSE;
+
+ return TRUE;
+}
+
+static unsigned int
+aarch64_tls_transition (bfd *input_bfd,
+ struct bfd_link_info *info,
+ unsigned int r_type,
+ struct elf_link_hash_entry *h,
+ unsigned long r_symndx)
+{
+ if (! aarch64_can_relax_tls (input_bfd, info, r_type, h, r_symndx))
+ return r_type;
+
+ return aarch64_tls_transition_without_check (r_type, h);
+}
+
+/* Return the base VMA address which should be subtracted from real addresses
+ when resolving R_AARCH64_TLS_DTPREL64 relocation. */
+
+static bfd_vma
+dtpoff_base (struct bfd_link_info *info)
+{
+ /* If tls_sec is NULL, we should have signalled an error already. */
+ BFD_ASSERT (elf_hash_table (info)->tls_sec != NULL);
+ return elf_hash_table (info)->tls_sec->vma;
+}
+
+
+/* Return the base VMA address which should be subtracted from real addresses
+ when resolving R_AARCH64_TLS_GOTTPREL64 relocations. */
+
+static bfd_vma
+tpoff_base (struct bfd_link_info *info)
+{
+ struct elf_link_hash_table *htab = elf_hash_table (info);
+
+ /* If tls_sec is NULL, we should have signalled an error already. */
+ if (htab->tls_sec == NULL)
+ return 0;
+
+ bfd_vma base = align_power ((bfd_vma) TCB_SIZE,
+ htab->tls_sec->alignment_power);
+ return htab->tls_sec->vma - base;
+}
+
+static bfd_vma *
+symbol_got_offset_ref (bfd *input_bfd, struct elf_link_hash_entry *h,
+ unsigned long r_symndx)
+{
+ /* Calculate the address of the GOT entry for symbol
+ referred to in h. */
+ if (h != NULL)
+ return &h->got.offset;
+ else
+ {
+ /* local symbol */
+ struct elf_aarch64_local_symbol *l;
+
+ l = elf64_aarch64_locals (input_bfd);
+ return &l[r_symndx].got_offset;
+ }
+}
+
+static void
+symbol_got_offset_mark (bfd *input_bfd, struct elf_link_hash_entry *h,
+ unsigned long r_symndx)
+{
+ bfd_vma *p;
+ p = symbol_got_offset_ref (input_bfd, h, r_symndx);
+ *p |= 1;
+}
+
+static int
+symbol_got_offset_mark_p (bfd *input_bfd, struct elf_link_hash_entry *h,
+ unsigned long r_symndx)
+{
+ bfd_vma value;
+ value = * symbol_got_offset_ref (input_bfd, h, r_symndx);
+ return value & 1;
+}
+
+static bfd_vma
+symbol_got_offset (bfd *input_bfd, struct elf_link_hash_entry *h,
+ unsigned long r_symndx)
+{
+ bfd_vma value;
+ value = * symbol_got_offset_ref (input_bfd, h, r_symndx);
+ value &= ~1;
+ return value;
+}
+
+static bfd_vma *
+symbol_tlsdesc_got_offset_ref (bfd *input_bfd, struct elf_link_hash_entry *h,
+ unsigned long r_symndx)
+{
+ /* Calculate the address of the GOT entry for symbol
+ referred to in h. */
+ if (h != NULL)
+ {
+ struct elf64_aarch64_link_hash_entry *eh;
+ eh = (struct elf64_aarch64_link_hash_entry *) h;
+ return &eh->tlsdesc_got_jump_table_offset;
+ }
+ else
+ {
+ /* local symbol */
+ struct elf_aarch64_local_symbol *l;
+
+ l = elf64_aarch64_locals (input_bfd);
+ return &l[r_symndx].tlsdesc_got_jump_table_offset;
+ }
+}
+
+static void
+symbol_tlsdesc_got_offset_mark (bfd *input_bfd, struct elf_link_hash_entry *h,
+ unsigned long r_symndx)
+{
+ bfd_vma *p;
+ p = symbol_tlsdesc_got_offset_ref (input_bfd, h, r_symndx);
+ *p |= 1;
+}
+
+static int
+symbol_tlsdesc_got_offset_mark_p (bfd *input_bfd,
+ struct elf_link_hash_entry *h,
+ unsigned long r_symndx)
+{
+ bfd_vma value;
+ value = * symbol_tlsdesc_got_offset_ref (input_bfd, h, r_symndx);
+ return value & 1;
+}
+
+static bfd_vma
+symbol_tlsdesc_got_offset (bfd *input_bfd, struct elf_link_hash_entry *h,
+ unsigned long r_symndx)
+{
+ bfd_vma value;
+ value = * symbol_tlsdesc_got_offset_ref (input_bfd, h, r_symndx);
+ value &= ~1;
+ return value;
+}
+
+/* Perform a relocation as part of a final link. */
+static bfd_reloc_status_type
+elf64_aarch64_final_link_relocate (reloc_howto_type *howto,
+ bfd *input_bfd,
+ bfd *output_bfd,
+ asection *input_section,
+ bfd_byte *contents,
+ Elf_Internal_Rela *rel,
+ bfd_vma value,
+ struct bfd_link_info *info,
+ asection *sym_sec,
+ struct elf_link_hash_entry *h,
+ bfd_boolean *unresolved_reloc_p,
+ bfd_boolean save_addend,
+ bfd_vma *saved_addend)
+{
+ unsigned int r_type = howto->type;
+ unsigned long r_symndx;
+ bfd_byte *hit_data = contents + rel->r_offset;
+ bfd_vma place;
+ bfd_signed_vma signed_addend;
+ struct elf64_aarch64_link_hash_table *globals;
+ bfd_boolean weak_undef_p;
+
+ globals = elf64_aarch64_hash_table (info);
+
+ BFD_ASSERT (is_aarch64_elf (input_bfd));
+
+ r_symndx = ELF64_R_SYM (rel->r_info);
+
+ /* It is possible to have linker relaxations on some TLS access
+ models. Update our information here. */
+ r_type = aarch64_tls_transition (input_bfd, info, r_type, h, r_symndx);
+
+ if (r_type != howto->type)
+ howto = elf64_aarch64_howto_from_type (r_type);
+
+ place = input_section->output_section->vma
+ + input_section->output_offset + rel->r_offset;
+
+ /* Get addend, accumulating the addend for consecutive relocs
+ which refer to the same offset. */
+ signed_addend = saved_addend ? *saved_addend : 0;
+ signed_addend += rel->r_addend;
+
+ weak_undef_p = (h ? h->root.type == bfd_link_hash_undefweak
+ : bfd_is_und_section (sym_sec));
+ switch (r_type)
+ {
+ case R_AARCH64_NONE:
+ case R_AARCH64_NULL:
+ case R_AARCH64_TLSDESC_CALL:
+ *unresolved_reloc_p = FALSE;
+ return bfd_reloc_ok;
+
+ case R_AARCH64_ABS64:
+
+ /* When generating a shared object or relocatable executable, these
+ relocations are copied into the output file to be resolved at
+ run time. */
+ if (((info->shared == TRUE) || globals->root.is_relocatable_executable)
+ && (input_section->flags & SEC_ALLOC)
+ && (h == NULL
+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
+ || h->root.type != bfd_link_hash_undefweak))
+ {
+ Elf_Internal_Rela outrel;
+ bfd_byte *loc;
+ bfd_boolean skip, relocate;
+ asection *sreloc;
+
+ *unresolved_reloc_p = FALSE;
+
+ sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd,
+ input_section, 1);
+ if (sreloc == NULL)
+ return bfd_reloc_notsupported;
+
+ skip = FALSE;
+ relocate = FALSE;
+
+ outrel.r_addend = signed_addend;
+ outrel.r_offset =
+ _bfd_elf_section_offset (output_bfd, info, input_section,
+ rel->r_offset);
+ if (outrel.r_offset == (bfd_vma) - 1)
+ skip = TRUE;
+ else if (outrel.r_offset == (bfd_vma) - 2)
+ {
+ skip = TRUE;
+ relocate = TRUE;
+ }
+
+ outrel.r_offset += (input_section->output_section->vma
+ + input_section->output_offset);
+
+ if (skip)
+ memset (&outrel, 0, sizeof outrel);
+ else if (h != NULL
+ && h->dynindx != -1
+ && (!info->shared || !info->symbolic || !h->def_regular))
+ outrel.r_info = ELF64_R_INFO (h->dynindx, r_type);
+ else
+ {
+ int symbol;
+
+ /* On SVR4-ish systems, the dynamic loader cannot
+ relocate the text and data segments independently,
+ so the symbol does not matter. */
+ symbol = 0;
+ outrel.r_info = ELF64_R_INFO (symbol, R_AARCH64_RELATIVE);
+ outrel.r_addend += value;
+ }
+
+ loc = sreloc->contents + sreloc->reloc_count++ * RELOC_SIZE (htab);
+ bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+
+ if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
+ {
+ /* Sanity to check that we have previously allocated
+ sufficient space in the relocation section for the
+ number of relocations we actually want to emit. */
+ abort ();
+ }
+
+ /* If this reloc is against an external symbol, we do not want to
+ fiddle with the addend. Otherwise, we need to include the symbol
+ value so that it becomes an addend for the dynamic reloc. */
+ if (!relocate)
+ return bfd_reloc_ok;
+
+ return _bfd_final_link_relocate (howto, input_bfd, input_section,
+ contents, rel->r_offset, value,
+ signed_addend);
+ }
+ else
+ value += signed_addend;
+ break;
+
+ case R_AARCH64_JUMP26:
+ case R_AARCH64_CALL26:
+ {
+ asection *splt = globals->root.splt;
+ bfd_boolean via_plt_p =
+ splt != NULL && h != NULL && h->plt.offset != (bfd_vma) - 1;
+
+ /* A call to an undefined weak symbol is converted to a jump to
+ the next instruction unless a PLT entry will be created.
+ The jump to the next instruction is optimized as a NOP.
+ Do the same for local undefined symbols. */
+ if (weak_undef_p && ! via_plt_p)
+ {
+ bfd_putl32 (INSN_NOP, hit_data);
+ return bfd_reloc_ok;
+ }
+
+ /* If the call goes through a PLT entry, make sure to
+ check distance to the right destination address. */
+ if (via_plt_p)
+ {
+ value = (splt->output_section->vma
+ + splt->output_offset + h->plt.offset);
+ *unresolved_reloc_p = FALSE;
+ }
+
+ /* If the target symbol is global and marked as a function the
+ relocation applies a function call or a tail call. In this
+ situation we can veneer out of range branches. The veneers
+ use IP0 and IP1 hence cannot be used arbitrary out of range
+ branches that occur within the body of a function. */
+ if (h && h->type == STT_FUNC)
+ {
+ /* Check if a stub has to be inserted because the destination
+ is too far away. */
+ if (! aarch64_valid_branch_p (value, place))
+ {
+ /* The target is out of reach, so redirect the branch to
+ the local stub for this function. */
+ struct elf64_aarch64_stub_hash_entry *stub_entry;
+ stub_entry = elf64_aarch64_get_stub_entry (input_section,
+ sym_sec, h,
+ rel, globals);
+ if (stub_entry != NULL)
+ value = (stub_entry->stub_offset
+ + stub_entry->stub_sec->output_offset
+ + stub_entry->stub_sec->output_section->vma);
+ }
+ }
+ }
+ value = aarch64_resolve_relocation (r_type, place, value,
+ signed_addend, weak_undef_p);
+ break;
+
+ case R_AARCH64_ABS16:
+ case R_AARCH64_ABS32:
+ case R_AARCH64_ADD_ABS_LO12_NC:
+ case R_AARCH64_ADR_PREL_LO21:
+ case R_AARCH64_ADR_PREL_PG_HI21:
+ case R_AARCH64_ADR_PREL_PG_HI21_NC:
+ case R_AARCH64_CONDBR19:
+ case R_AARCH64_LD_PREL_LO19:
+ case R_AARCH64_LDST8_ABS_LO12_NC:
+ case R_AARCH64_LDST16_ABS_LO12_NC:
+ case R_AARCH64_LDST32_ABS_LO12_NC:
+ case R_AARCH64_LDST64_ABS_LO12_NC:
+ case R_AARCH64_LDST128_ABS_LO12_NC:
+ case R_AARCH64_MOVW_SABS_G0:
+ case R_AARCH64_MOVW_SABS_G1:
+ case R_AARCH64_MOVW_SABS_G2:
+ case R_AARCH64_MOVW_UABS_G0:
+ case R_AARCH64_MOVW_UABS_G0_NC:
+ case R_AARCH64_MOVW_UABS_G1:
+ case R_AARCH64_MOVW_UABS_G1_NC:
+ case R_AARCH64_MOVW_UABS_G2:
+ case R_AARCH64_MOVW_UABS_G2_NC:
+ case R_AARCH64_MOVW_UABS_G3:
+ case R_AARCH64_PREL16:
+ case R_AARCH64_PREL32:
+ case R_AARCH64_PREL64:
+ case R_AARCH64_TSTBR14:
+ value = aarch64_resolve_relocation (r_type, place, value,
+ signed_addend, weak_undef_p);
+ break;
+
+ case R_AARCH64_LD64_GOT_LO12_NC:
+ case R_AARCH64_ADR_GOT_PAGE:
+ if (globals->root.sgot == NULL)
+ BFD_ASSERT (h != NULL);
+
+ if (h != NULL)
+ {
+ value = aarch64_calculate_got_entry_vma (h, globals, info, value,
+ output_bfd,
+ unresolved_reloc_p);
+ value = aarch64_resolve_relocation (r_type, place, value,
+ 0, weak_undef_p);
+ }
+ break;
+
+ case R_AARCH64_TLSGD_ADR_PAGE21:
+ case R_AARCH64_TLSGD_ADD_LO12_NC:
+ case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ if (globals->root.sgot == NULL)
+ return bfd_reloc_notsupported;
+
+ value = (symbol_got_offset (input_bfd, h, r_symndx)
+ + globals->root.sgot->output_section->vma
+ + globals->root.sgot->output_section->output_offset);
+
+ value = aarch64_resolve_relocation (r_type, place, value,
+ 0, weak_undef_p);
+ *unresolved_reloc_p = FALSE;
+ break;
+
+ case R_AARCH64_TLSLE_ADD_TPREL_HI12:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G2:
+ value = aarch64_resolve_relocation (r_type, place, value,
+ - tpoff_base (info), weak_undef_p);
+ *unresolved_reloc_p = FALSE;
+ break;
+
+ case R_AARCH64_TLSDESC_ADR_PAGE:
+ case R_AARCH64_TLSDESC_LD64_LO12_NC:
+ case R_AARCH64_TLSDESC_ADD_LO12_NC:
+ case R_AARCH64_TLSDESC_ADD:
+ case R_AARCH64_TLSDESC_LDR:
+ if (globals->root.sgot == NULL)
+ return bfd_reloc_notsupported;
+
+ value = (symbol_tlsdesc_got_offset (input_bfd, h, r_symndx)
+ + globals->root.sgotplt->output_section->vma
+ + globals->root.sgotplt->output_section->output_offset
+ + globals->sgotplt_jump_table_size);
+
+ value = aarch64_resolve_relocation (r_type, place, value,
+ 0, weak_undef_p);
+ *unresolved_reloc_p = FALSE;
+ break;
+
+ default:
+ return bfd_reloc_notsupported;
+ }
+
+ if (saved_addend)
+ *saved_addend = value;
+
+ /* Only apply the final relocation in a sequence. */
+ if (save_addend)
+ return bfd_reloc_continue;
+
+ return bfd_elf_aarch64_put_addend (input_bfd, hit_data, howto, value);
+}
+
+/* Handle TLS relaxations. Relaxing is possible for symbols that use
+ R_AARCH64_TLSDESC_ADR_{PAGE, LD64_LO12_NC, ADD_LO12_NC} during a static
+ link.
+
+ Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
+ is to then call final_link_relocate. Return other values in the
+ case of error. */
+
+static bfd_reloc_status_type
+elf64_aarch64_tls_relax (struct elf64_aarch64_link_hash_table *globals,
+ bfd *input_bfd, bfd_byte *contents,
+ Elf_Internal_Rela *rel, struct elf_link_hash_entry *h)
+{
+ bfd_boolean is_local = h == NULL;
+ unsigned int r_type = ELF64_R_TYPE (rel->r_info);
+ unsigned long insn;
+
+ BFD_ASSERT (globals && input_bfd && contents && rel);
+
+ switch (r_type)
+ {
+ case R_AARCH64_TLSGD_ADR_PAGE21:
+ case R_AARCH64_TLSDESC_ADR_PAGE:
+ if (is_local)
+ {
+ /* GD->LE relaxation:
+ adrp x0, :tlsgd:var => movz x0, :tprel_g1:var
+ or
+ adrp x0, :tlsdesc:var => movz x0, :tprel_g1:var
+ */
+ bfd_putl32 (0xd2a00000, contents + rel->r_offset);
+ return bfd_reloc_continue;
+ }
+ else
+ {
+ /* GD->IE relaxation:
+ adrp x0, :tlsgd:var => adrp x0, :gottprel:var
+ or
+ adrp x0, :tlsdesc:var => adrp x0, :gottprel:var
+ */
+ insn = bfd_getl32 (contents + rel->r_offset);
+ return bfd_reloc_continue;
+ }
+
+ case R_AARCH64_TLSDESC_LD64_LO12_NC:
+ if (is_local)
+ {
+ /* GD->LE relaxation:
+ ldr xd, [x0, #:tlsdesc_lo12:var] => movk x0, :tprel_g0_nc:var
+ */
+ bfd_putl32 (0xf2800000, contents + rel->r_offset);
+ return bfd_reloc_continue;
+ }
+ else
+ {
+ /* GD->IE relaxation:
+ ldr xd, [x0, #:tlsdesc_lo12:var] => ldr x0, [x0, #:gottprel_lo12:var]
+ */
+ insn = bfd_getl32 (contents + rel->r_offset);
+ insn &= 0xfffffff0;
+ bfd_putl32 (insn, contents + rel->r_offset);
+ return bfd_reloc_continue;
+ }
+
+ case R_AARCH64_TLSGD_ADD_LO12_NC:
+ if (is_local)
+ {
+ /* GD->LE relaxation
+ add x0, #:tlsgd_lo12:var => movk x0, :tprel_g0_nc:var
+ bl __tls_get_addr => mrs x1, tpidr_el0
+ nop => add x0, x1, x0
+ */
+
+ /* First kill the tls_get_addr reloc on the bl instruction. */
+ BFD_ASSERT (rel->r_offset + 4 == rel[1].r_offset);
+ rel[1].r_info = ELF64_R_INFO (STN_UNDEF, R_AARCH64_NONE);
+
+ bfd_putl32 (0xf2800000, contents + rel->r_offset);
+ bfd_putl32 (0xd53bd041, contents + rel->r_offset + 4);
+ bfd_putl32 (0x8b000020, contents + rel->r_offset + 8);
+ return bfd_reloc_continue;
+ }
+ else
+ {
+ /* GD->IE relaxation
+ ADD x0, #:tlsgd_lo12:var => ldr x0, [x0, #:gottprel_lo12:var]
+ BL __tls_get_addr => mrs x1, tpidr_el0
+ R_AARCH64_CALL26
+ NOP => add x0, x1, x0
+ */
+
+ BFD_ASSERT (ELF64_R_TYPE (rel[1].r_info) == R_AARCH64_CALL26);
+
+ /* Remove the relocation on the BL instruction. */
+ rel[1].r_info = ELF64_R_INFO (STN_UNDEF, R_AARCH64_NONE);
+
+ bfd_putl32 (0xf9400000, contents + rel->r_offset);
+
+ /* We choose to fixup the BL and NOP instructions using the
+ offset from the second relocation to allow flexibility in
+ scheduling instructions between the ADD and BL. */
+ bfd_putl32 (0xd53bd041, contents + rel[1].r_offset);
+ bfd_putl32 (0x8b000020, contents + rel[1].r_offset + 4);
+ return bfd_reloc_continue;
+ }
+
+ case R_AARCH64_TLSDESC_ADD_LO12_NC:
+ case R_AARCH64_TLSDESC_CALL:
+ /* GD->IE/LE relaxation:
+ add x0, x0, #:tlsdesc_lo12:var => nop
+ blr xd => nop
+ */
+ bfd_putl32 (INSN_NOP, contents + rel->r_offset);
+ return bfd_reloc_ok;
+
+ case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ /* IE->LE relaxation:
+ adrp xd, :gottprel:var => movz xd, :tprel_g1:var
+ */
+ if (is_local)
+ {
+ insn = bfd_getl32 (contents + rel->r_offset);
+ bfd_putl32 (0xd2a00000 | (insn & 0x1f), contents + rel->r_offset);
+ }
+ return bfd_reloc_continue;
+
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ /* IE->LE relaxation:
+ ldr xd, [xm, #:gottprel_lo12:var] => movk xd, :tprel_g0_nc:var
+ */
+ if (is_local)
+ {
+ insn = bfd_getl32 (contents + rel->r_offset);
+ bfd_putl32 (0xf2800000 | (insn & 0x1f), contents + rel->r_offset);
+ }
+ return bfd_reloc_continue;
+
+ default:
+ return bfd_reloc_continue;
+ }
+
+ return bfd_reloc_ok;
+}
+
+/* Relocate an AArch64 ELF section. */
+
+static bfd_boolean
+elf64_aarch64_relocate_section (bfd *output_bfd,
+ struct bfd_link_info *info,
+ bfd *input_bfd,
+ asection *input_section,
+ bfd_byte *contents,
+ Elf_Internal_Rela *relocs,
+ Elf_Internal_Sym *local_syms,
+ asection **local_sections)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **sym_hashes;
+ Elf_Internal_Rela *rel;
+ Elf_Internal_Rela *relend;
+ const char *name;
+ struct elf64_aarch64_link_hash_table *globals;
+ bfd_boolean save_addend = FALSE;
+ bfd_vma addend = 0;
+
+ globals = elf64_aarch64_hash_table (info);
+
+ symtab_hdr = &elf_symtab_hdr (input_bfd);
+ sym_hashes = elf_sym_hashes (input_bfd);
+
+ rel = relocs;
+ relend = relocs + input_section->reloc_count;
+ for (; rel < relend; rel++)
+ {
+ unsigned int r_type;
+ unsigned int relaxed_r_type;
+ reloc_howto_type *howto;
+ unsigned long r_symndx;
+ Elf_Internal_Sym *sym;
+ asection *sec;
+ struct elf_link_hash_entry *h;
+ bfd_vma relocation;
+ bfd_reloc_status_type r;
+ arelent bfd_reloc;
+ char sym_type;
+ bfd_boolean unresolved_reloc = FALSE;
+ char *error_message = NULL;
+
+ r_symndx = ELF64_R_SYM (rel->r_info);
+ r_type = ELF64_R_TYPE (rel->r_info);
+
+ bfd_reloc.howto = elf64_aarch64_howto_from_type (r_type);
+ howto = bfd_reloc.howto;
+
+ h = NULL;
+ sym = NULL;
+ sec = NULL;
+
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ sym_type = ELF64_ST_TYPE (sym->st_info);
+ sec = local_sections[r_symndx];
+
+ /* An object file might have a reference to a local
+ undefined symbol. This is a daft object file, but we
+ should at least do something about it. */
+ if (r_type != R_AARCH64_NONE && r_type != R_AARCH64_NULL
+ && bfd_is_und_section (sec)
+ && ELF_ST_BIND (sym->st_info) != STB_WEAK)
+ {
+ if (!info->callbacks->undefined_symbol
+ (info, bfd_elf_string_from_elf_section
+ (input_bfd, symtab_hdr->sh_link, sym->st_name),
+ input_bfd, input_section, rel->r_offset, TRUE))
+ return FALSE;
+ }
+
+ if (r_type >= R_AARCH64_dyn_max)
+ {
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+
+ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+ }
+ else
+ {
+ bfd_boolean warned;
+
+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+ r_symndx, symtab_hdr, sym_hashes,
+ h, sec, relocation,
+ unresolved_reloc, warned);
+
+ sym_type = h->type;
+ }
+
+ if (sec != NULL && discarded_section (sec))
+ RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
+ rel, 1, relend, howto, 0, contents);
+
+ if (info->relocatable)
+ {
+ /* This is a relocatable link. We don't have to change
+ anything, unless the reloc is against a section symbol,
+ in which case we have to adjust according to where the
+ section symbol winds up in the output section. */
+ if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+ rel->r_addend += sec->output_offset;
+ continue;
+ }
+
+ if (h != NULL)
+ name = h->root.root.string;
+ else
+ {
+ name = (bfd_elf_string_from_elf_section
+ (input_bfd, symtab_hdr->sh_link, sym->st_name));
+ if (name == NULL || *name == '\0')
+ name = bfd_section_name (input_bfd, sec);
+ }
+
+ if (r_symndx != 0
+ && r_type != R_AARCH64_NONE
+ && r_type != R_AARCH64_NULL
+ && (h == NULL
+ || h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak)
+ && IS_AARCH64_TLS_RELOC (r_type) != (sym_type == STT_TLS))
+ {
+ (*_bfd_error_handler)
+ ((sym_type == STT_TLS
+ ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
+ : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
+ input_bfd,
+ input_section, (long) rel->r_offset, howto->name, name);
+ }
+
+
+ /* We relax only if we can see that there can be a valid transition
+ from a reloc type to another.
+ We call elf64_aarch64_final_link_relocate unless we're completely
+ done, i.e., the relaxation produced the final output we want. */
+
+ relaxed_r_type = aarch64_tls_transition (input_bfd, info, r_type,
+ h, r_symndx);
+ if (relaxed_r_type != r_type)
+ {
+ r_type = relaxed_r_type;
+ howto = elf64_aarch64_howto_from_type (r_type);
+
+ r = elf64_aarch64_tls_relax (globals, input_bfd, contents, rel, h);
+ unresolved_reloc = 0;
+ }
+ else
+ r = bfd_reloc_continue;
+
+ /* There may be multiple consecutive relocations for the
+ same offset. In that case we are supposed to treat the
+ output of each relocation as the addend for the next. */
+ if (rel + 1 < relend
+ && rel->r_offset == rel[1].r_offset
+ && ELF64_R_TYPE (rel[1].r_info) != R_AARCH64_NONE
+ && ELF64_R_TYPE (rel[1].r_info) != R_AARCH64_NULL)
+ save_addend = TRUE;
+ else
+ save_addend = FALSE;
+
+ if (r == bfd_reloc_continue)
+ r = elf64_aarch64_final_link_relocate (howto, input_bfd, output_bfd,
+ input_section, contents, rel,
+ relocation, info, sec,
+ h, &unresolved_reloc,
+ save_addend, &addend);
+
+ switch (r_type)
+ {
+ case R_AARCH64_TLSGD_ADR_PAGE21:
+ case R_AARCH64_TLSGD_ADD_LO12_NC:
+ if (! symbol_got_offset_mark_p (input_bfd, h, r_symndx))
+ {
+ bfd_boolean need_relocs = FALSE;
+ bfd_byte *loc;
+ int indx;
+ bfd_vma off;
+
+ off = symbol_got_offset (input_bfd, h, r_symndx);
+ indx = h && h->dynindx != -1 ? h->dynindx : 0;
+
+ need_relocs =
+ (info->shared || indx != 0) &&
+ (h == NULL
+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
+ || h->root.type != bfd_link_hash_undefweak);
+
+ BFD_ASSERT (globals->root.srelgot != NULL);
+
+ if (need_relocs)
+ {
+ Elf_Internal_Rela rela;
+ rela.r_info = ELF64_R_INFO (indx, R_AARCH64_TLS_DTPMOD64);
+ rela.r_addend = 0;
+ rela.r_offset = globals->root.sgot->output_section->vma +
+ globals->root.sgot->output_offset + off;
+
+
+ loc = globals->root.srelgot->contents;
+ loc += globals->root.srelgot->reloc_count++
+ * RELOC_SIZE (htab);
+ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+
+ if (indx == 0)
+ {
+ bfd_put_64 (output_bfd,
+ relocation - dtpoff_base (info),
+ globals->root.sgot->contents + off
+ + GOT_ENTRY_SIZE);
+ }
+ else
+ {
+ /* This TLS symbol is global. We emit a
+ relocation to fixup the tls offset at load
+ time. */
+ rela.r_info =
+ ELF64_R_INFO (indx, R_AARCH64_TLS_DTPREL64);
+ rela.r_addend = 0;
+ rela.r_offset =
+ (globals->root.sgot->output_section->vma
+ + globals->root.sgot->output_offset + off
+ + GOT_ENTRY_SIZE);
+
+ loc = globals->root.srelgot->contents;
+ loc += globals->root.srelgot->reloc_count++
+ * RELOC_SIZE (globals);
+ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+ bfd_put_64 (output_bfd, (bfd_vma) 0,
+ globals->root.sgot->contents + off
+ + GOT_ENTRY_SIZE);
+ }
+ }
+ else
+ {
+ bfd_put_64 (output_bfd, (bfd_vma) 1,
+ globals->root.sgot->contents + off);
+ bfd_put_64 (output_bfd,
+ relocation - dtpoff_base (info),
+ globals->root.sgot->contents + off
+ + GOT_ENTRY_SIZE);
+ }
+
+ symbol_got_offset_mark (input_bfd, h, r_symndx);
+ }
+ break;
+
+ case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ if (! symbol_got_offset_mark_p (input_bfd, h, r_symndx))
+ {
+ bfd_boolean need_relocs = FALSE;
+ bfd_byte *loc;
+ int indx;
+ bfd_vma off;
+
+ off = symbol_got_offset (input_bfd, h, r_symndx);
+
+ indx = h && h->dynindx != -1 ? h->dynindx : 0;
+
+ need_relocs =
+ (info->shared || indx != 0) &&
+ (h == NULL
+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
+ || h->root.type != bfd_link_hash_undefweak);
+
+ BFD_ASSERT (globals->root.srelgot != NULL);
+
+ if (need_relocs)
+ {
+ Elf_Internal_Rela rela;
+
+ if (indx == 0)
+ rela.r_addend = relocation - dtpoff_base (info);
+ else
+ rela.r_addend = 0;
+
+ rela.r_info = ELF64_R_INFO (indx, R_AARCH64_TLS_TPREL64);
+ rela.r_offset = globals->root.sgot->output_section->vma +
+ globals->root.sgot->output_offset + off;
+
+ loc = globals->root.srelgot->contents;
+ loc += globals->root.srelgot->reloc_count++
+ * RELOC_SIZE (htab);
+
+ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+
+ bfd_put_64 (output_bfd, rela.r_addend,
+ globals->root.sgot->contents + off);
+ }
+ else
+ bfd_put_64 (output_bfd, relocation - tpoff_base (info),
+ globals->root.sgot->contents + off);
+
+ symbol_got_offset_mark (input_bfd, h, r_symndx);
+ }
+ break;
+
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12:
+ case R_AARCH64_TLSLE_ADD_TPREL_HI12:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G2:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+ break;
+
+ case R_AARCH64_TLSDESC_ADR_PAGE:
+ case R_AARCH64_TLSDESC_LD64_LO12_NC:
+ case R_AARCH64_TLSDESC_ADD_LO12_NC:
+ if (! symbol_tlsdesc_got_offset_mark_p (input_bfd, h, r_symndx))
+ {
+ bfd_boolean need_relocs = FALSE;
+ int indx = h && h->dynindx != -1 ? h->dynindx : 0;
+ bfd_vma off = symbol_tlsdesc_got_offset (input_bfd, h, r_symndx);
+
+ need_relocs = (h == NULL
+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
+ || h->root.type != bfd_link_hash_undefweak);
+
+ BFD_ASSERT (globals->root.srelgot != NULL);
+ BFD_ASSERT (globals->root.sgot != NULL);
+
+ if (need_relocs)
+ {
+ bfd_byte *loc;
+ Elf_Internal_Rela rela;
+ rela.r_info = ELF64_R_INFO (indx, R_AARCH64_TLSDESC);
+ rela.r_addend = 0;
+ rela.r_offset = (globals->root.sgotplt->output_section->vma
+ + globals->root.sgotplt->output_offset
+ + off + globals->sgotplt_jump_table_size);
+
+ if (indx == 0)
+ rela.r_addend = relocation - dtpoff_base (info);
+
+ /* Allocate the next available slot in the PLT reloc
+ section to hold our R_AARCH64_TLSDESC, the next
+ available slot is determined from reloc_count,
+ which we step. But note, reloc_count was
+ artifically moved down while allocating slots for
+ real PLT relocs such that all of the PLT relocs
+ will fit above the initial reloc_count and the
+ extra stuff will fit below. */
+ loc = globals->root.srelplt->contents;
+ loc += globals->root.srelplt->reloc_count++
+ * RELOC_SIZE (globals);
+
+ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+
+ bfd_put_64 (output_bfd, (bfd_vma) 0,
+ globals->root.sgotplt->contents + off +
+ globals->sgotplt_jump_table_size);
+ bfd_put_64 (output_bfd, (bfd_vma) 0,
+ globals->root.sgotplt->contents + off +
+ globals->sgotplt_jump_table_size +
+ GOT_ENTRY_SIZE);
+ }
+
+ symbol_tlsdesc_got_offset_mark (input_bfd, h, r_symndx);
+ }
+ break;
+ }
+
+ if (!save_addend)
+ addend = 0;
+
+
+ /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
+ because such sections are not SEC_ALLOC and thus ld.so will
+ not process them. */
+ if (unresolved_reloc
+ && !((input_section->flags & SEC_DEBUGGING) != 0
+ && h->def_dynamic)
+ && _bfd_elf_section_offset (output_bfd, info, input_section,
+ +rel->r_offset) != (bfd_vma) - 1)
+ {
+ (*_bfd_error_handler)
+ (_
+ ("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
+ input_bfd, input_section, (long) rel->r_offset, howto->name,
+ h->root.root.string);
+ return FALSE;
+ }
+
+ if (r != bfd_reloc_ok && r != bfd_reloc_continue)
+ {
+ switch (r)
+ {
+ case bfd_reloc_overflow:
+ /* If the overflowing reloc was to an undefined symbol,
+ we have already printed one error message and there
+ is no point complaining again. */
+ if ((!h ||
+ h->root.type != bfd_link_hash_undefined)
+ && (!((*info->callbacks->reloc_overflow)
+ (info, (h ? &h->root : NULL), name, howto->name,
+ (bfd_vma) 0, input_bfd, input_section,
+ rel->r_offset))))
+ return FALSE;
+ break;
+
+ case bfd_reloc_undefined:
+ if (!((*info->callbacks->undefined_symbol)
+ (info, name, input_bfd, input_section,
+ rel->r_offset, TRUE)))
+ return FALSE;
+ break;
+
+ case bfd_reloc_outofrange:
+ error_message = _("out of range");
+ goto common_error;
+
+ case bfd_reloc_notsupported:
+ error_message = _("unsupported relocation");
+ goto common_error;
+
+ case bfd_reloc_dangerous:
+ /* error_message should already be set. */
+ goto common_error;
+
+ default:
+ error_message = _("unknown error");
+ /* Fall through. */
+
+ common_error:
+ BFD_ASSERT (error_message != NULL);
+ if (!((*info->callbacks->reloc_dangerous)
+ (info, error_message, input_bfd, input_section,
+ rel->r_offset)))
+ return FALSE;
+ break;
+ }
+ }
+ }
+
+ return TRUE;
+}
+
+/* Set the right machine number. */
+
+static bfd_boolean
+elf64_aarch64_object_p (bfd *abfd)
+{
+ bfd_default_set_arch_mach (abfd, bfd_arch_aarch64, bfd_mach_aarch64);
+ return TRUE;
+}
+
+/* Function to keep AArch64 specific flags in the ELF header. */
+
+static bfd_boolean
+elf64_aarch64_set_private_flags (bfd *abfd, flagword flags)
+{
+ if (elf_flags_init (abfd) && elf_elfheader (abfd)->e_flags != flags)
+ {
+ }
+ else
+ {
+ elf_elfheader (abfd)->e_flags = flags;
+ elf_flags_init (abfd) = TRUE;
+ }
+
+ return TRUE;
+}
+
+/* Copy backend specific data from one object module to another. */
+
+static bfd_boolean
+elf64_aarch64_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
+{
+ flagword in_flags;
+
+ if (!is_aarch64_elf (ibfd) || !is_aarch64_elf (obfd))
+ return TRUE;
+
+ in_flags = elf_elfheader (ibfd)->e_flags;
+
+ elf_elfheader (obfd)->e_flags = in_flags;
+ elf_flags_init (obfd) = TRUE;
+
+ /* Also copy the EI_OSABI field. */
+ elf_elfheader (obfd)->e_ident[EI_OSABI] =
+ elf_elfheader (ibfd)->e_ident[EI_OSABI];
+
+ /* Copy object attributes. */
+ _bfd_elf_copy_obj_attributes (ibfd, obfd);
+
+ return TRUE;
+}
+
+/* Merge backend specific data from an object file to the output
+ object file when linking. */
+
+static bfd_boolean
+elf64_aarch64_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
+{
+ flagword out_flags;
+ flagword in_flags;
+ bfd_boolean flags_compatible = TRUE;
+ asection *sec;
+
+ /* Check if we have the same endianess. */
+ if (!_bfd_generic_verify_endian_match (ibfd, obfd))
+ return FALSE;
+
+ if (!is_aarch64_elf (ibfd) || !is_aarch64_elf (obfd))
+ return TRUE;
+
+ /* The input BFD must have had its flags initialised. */
+ /* The following seems bogus to me -- The flags are initialized in
+ the assembler but I don't think an elf_flags_init field is
+ written into the object. */
+ /* BFD_ASSERT (elf_flags_init (ibfd)); */
+
+ in_flags = elf_elfheader (ibfd)->e_flags;
+ out_flags = elf_elfheader (obfd)->e_flags;
+
+ if (!elf_flags_init (obfd))
+ {
+ /* If the input is the default architecture and had the default
+ flags then do not bother setting the flags for the output
+ architecture, instead allow future merges to do this. If no
+ future merges ever set these flags then they will retain their
+ uninitialised values, which surprise surprise, correspond
+ to the default values. */
+ if (bfd_get_arch_info (ibfd)->the_default
+ && elf_elfheader (ibfd)->e_flags == 0)
+ return TRUE;
+
+ elf_flags_init (obfd) = TRUE;
+ elf_elfheader (obfd)->e_flags = in_flags;
+
+ if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
+ && bfd_get_arch_info (obfd)->the_default)
+ return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd),
+ bfd_get_mach (ibfd));
+
+ return TRUE;
+ }
+
+ /* Identical flags must be compatible. */
+ if (in_flags == out_flags)
+ return TRUE;
+
+ /* Check to see if the input BFD actually contains any sections. If
+ not, its flags may not have been initialised either, but it
+ cannot actually cause any incompatiblity. Do not short-circuit
+ dynamic objects; their section list may be emptied by
+ elf_link_add_object_symbols.
+
+ Also check to see if there are no code sections in the input.
+ In this case there is no need to check for code specific flags.
+ XXX - do we need to worry about floating-point format compatability
+ in data sections ? */
+ if (!(ibfd->flags & DYNAMIC))
+ {
+ bfd_boolean null_input_bfd = TRUE;
+ bfd_boolean only_data_sections = TRUE;
+
+ for (sec = ibfd->sections; sec != NULL; sec = sec->next)
+ {
+ if ((bfd_get_section_flags (ibfd, sec)
+ & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
+ == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
+ only_data_sections = FALSE;
+
+ null_input_bfd = FALSE;
+ break;
+ }
+
+ if (null_input_bfd || only_data_sections)
+ return TRUE;
+ }
+
+ return flags_compatible;
+}
+
+/* Display the flags field. */
+
+static bfd_boolean
+elf64_aarch64_print_private_bfd_data (bfd *abfd, void *ptr)
+{
+ FILE *file = (FILE *) ptr;
+ unsigned long flags;
+
+ BFD_ASSERT (abfd != NULL && ptr != NULL);
+
+ /* Print normal ELF private data. */
+ _bfd_elf_print_private_bfd_data (abfd, ptr);
+
+ flags = elf_elfheader (abfd)->e_flags;
+ /* Ignore init flag - it may not be set, despite the flags field
+ containing valid data. */
+
+ /* xgettext:c-format */
+ fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
+
+ if (flags)
+ fprintf (file, _("<Unrecognised flag bits set>"));
+
+ fputc ('\n', file);
+
+ return TRUE;
+}
+
+/* Update the got entry reference counts for the section being removed. */
+
+static bfd_boolean
+elf64_aarch64_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED,
+ struct bfd_link_info *info ATTRIBUTE_UNUSED,
+ asection *sec ATTRIBUTE_UNUSED,
+ const Elf_Internal_Rela *
+ relocs ATTRIBUTE_UNUSED)
+{
+ return TRUE;
+}
+
+/* Adjust a symbol defined by a dynamic object and referenced by a
+ regular object. The current definition is in some section of the
+ dynamic object, but we're not including those sections. We have to
+ change the definition to something the rest of the link can
+ understand. */
+
+static bfd_boolean
+elf64_aarch64_adjust_dynamic_symbol (struct bfd_link_info *info,
+ struct elf_link_hash_entry *h)
+{
+ struct elf64_aarch64_link_hash_table *htab;
+ asection *s;
+
+ /* If this is a function, put it in the procedure linkage table. We
+ will fill in the contents of the procedure linkage table later,
+ when we know the address of the .got section. */
+ if (h->type == STT_FUNC || h->needs_plt)
+ {
+ if (h->plt.refcount <= 0
+ || SYMBOL_CALLS_LOCAL (info, h)
+ || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
+ && h->root.type == bfd_link_hash_undefweak))
+ {
+ /* This case can occur if we saw a CALL26 reloc in
+ an input file, but the symbol wasn't referred to
+ by a dynamic object or all references were
+ garbage collected. In which case we can end up
+ resolving. */
+ h->plt.offset = (bfd_vma) - 1;
+ h->needs_plt = 0;
+ }
+
+ return TRUE;
+ }
+ else
+ /* It's possible that we incorrectly decided a .plt reloc was
+ needed for an R_X86_64_PC32 reloc to a non-function sym in
+ check_relocs. We can't decide accurately between function and
+ non-function syms in check-relocs; Objects loaded later in
+ the link may change h->type. So fix it now. */
+ h->plt.offset = (bfd_vma) - 1;
+
+
+ /* If this is a weak symbol, and there is a real definition, the
+ processor independent code will have arranged for us to see the
+ real definition first, and we can just use the same value. */
+ if (h->u.weakdef != NULL)
+ {
+ BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
+ || h->u.weakdef->root.type == bfd_link_hash_defweak);
+ h->root.u.def.section = h->u.weakdef->root.u.def.section;
+ h->root.u.def.value = h->u.weakdef->root.u.def.value;
+ if (ELIMINATE_COPY_RELOCS || info->nocopyreloc)
+ h->non_got_ref = h->u.weakdef->non_got_ref;
+ return TRUE;
+ }
+
+ /* If we are creating a shared library, we must presume that the
+ only references to the symbol are via the global offset table.
+ For such cases we need not do anything here; the relocations will
+ be handled correctly by relocate_section. */
+ if (info->shared)
+ return TRUE;
+
+ /* If there are no references to this symbol that do not use the
+ GOT, we don't need to generate a copy reloc. */
+ if (!h->non_got_ref)
+ return TRUE;
+
+ /* If -z nocopyreloc was given, we won't generate them either. */
+ if (info->nocopyreloc)
+ {
+ h->non_got_ref = 0;
+ return TRUE;
+ }
+
+ /* We must allocate the symbol in our .dynbss section, which will
+ become part of the .bss section of the executable. There will be
+ an entry for this symbol in the .dynsym section. The dynamic
+ object will contain position independent code, so all references
+ from the dynamic object to this symbol will go through the global
+ offset table. The dynamic linker will use the .dynsym entry to
+ determine the address it must put in the global offset table, so
+ both the dynamic object and the regular object will refer to the
+ same memory location for the variable. */
+
+ htab = elf64_aarch64_hash_table (info);
+
+ /* We must generate a R_AARCH64_COPY reloc to tell the dynamic linker
+ to copy the initial value out of the dynamic object and into the
+ runtime process image. */
+ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0 && h->size != 0)
+ {
+ htab->srelbss->size += RELOC_SIZE (htab);
+ h->needs_copy = 1;
+ }
+
+ s = htab->sdynbss;
+
+ return _bfd_elf_adjust_dynamic_copy (h, s);
+
+}
+
+static bfd_boolean
+elf64_aarch64_allocate_local_symbols (bfd *abfd, unsigned number)
+{
+ struct elf_aarch64_local_symbol *locals;
+ locals = elf64_aarch64_locals (abfd);
+ if (locals == NULL)
+ {
+ locals = (struct elf_aarch64_local_symbol *)
+ bfd_zalloc (abfd, number * sizeof (struct elf_aarch64_local_symbol));
+ if (locals == NULL)
+ return FALSE;
+ elf64_aarch64_locals (abfd) = locals;
+ }
+ return TRUE;
+}
+
+/* Look through the relocs for a section during the first phase. */
+
+static bfd_boolean
+elf64_aarch64_check_relocs (bfd *abfd, struct bfd_link_info *info,
+ asection *sec, const Elf_Internal_Rela *relocs)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **sym_hashes;
+ const Elf_Internal_Rela *rel;
+ const Elf_Internal_Rela *rel_end;
+ asection *sreloc;
+
+ struct elf64_aarch64_link_hash_table *htab;
+
+ unsigned long nsyms;
+
+ if (info->relocatable)
+ return TRUE;
+
+ BFD_ASSERT (is_aarch64_elf (abfd));
+
+ htab = elf64_aarch64_hash_table (info);
+ sreloc = NULL;
+
+ symtab_hdr = &elf_symtab_hdr (abfd);
+ sym_hashes = elf_sym_hashes (abfd);
+ nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
+
+ rel_end = relocs + sec->reloc_count;
+ for (rel = relocs; rel < rel_end; rel++)
+ {
+ struct elf_link_hash_entry *h;
+ unsigned long r_symndx;
+ unsigned int r_type;
+
+ r_symndx = ELF64_R_SYM (rel->r_info);
+ r_type = ELF64_R_TYPE (rel->r_info);
+
+ if (r_symndx >= NUM_SHDR_ENTRIES (symtab_hdr))
+ {
+ (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
+ r_symndx);
+ return FALSE;
+ }
+
+ if (r_symndx >= nsyms
+ /* PR 9934: It is possible to have relocations that do not
+ refer to symbols, thus it is also possible to have an
+ object file containing relocations but no symbol table. */
+ && (r_symndx > 0 || nsyms > 0))
+ {
+ (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
+ r_symndx);
+ return FALSE;
+ }
+
+ if (nsyms == 0 || r_symndx < symtab_hdr->sh_info)
+ h = NULL;
+ else
+ {
+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+ }
+
+ /* Could be done earlier, if h were already available. */
+ r_type = aarch64_tls_transition (abfd, info, r_type, h, r_symndx);
+
+ switch (r_type)
+ {
+ case R_AARCH64_ABS64:
+
+ /* We don't need to handle relocs into sections not going into
+ the "real" output. */
+ if ((sec->flags & SEC_ALLOC) == 0)
+ break;
+
+ if (h != NULL)
+ {
+ if (!info->shared)
+ h->non_got_ref = 1;
+
+ h->plt.refcount += 1;
+ h->pointer_equality_needed = 1;
+ }
+
+ /* No need to do anything if we're not creating a shared
+ object. */
+ if (! info->shared)
+ break;
+
+ {
+ struct elf_dyn_relocs *p;
+ struct elf_dyn_relocs **head;
+
+ /* We must copy these reloc types into the output file.
+ Create a reloc section in dynobj and make room for
+ this reloc. */
+ if (sreloc == NULL)
+ {
+ if (htab->root.dynobj == NULL)
+ htab->root.dynobj = abfd;
+
+ sreloc = _bfd_elf_make_dynamic_reloc_section
+ (sec, htab->root.dynobj, 3, abfd, /*rela? */ TRUE);
+
+ if (sreloc == NULL)
+ return FALSE;
+ }
+
+ /* If this is a global symbol, we count the number of
+ relocations we need for this symbol. */
+ if (h != NULL)
+ {
+ struct elf64_aarch64_link_hash_entry *eh;
+ eh = (struct elf64_aarch64_link_hash_entry *) h;
+ head = &eh->dyn_relocs;
+ }
+ else
+ {
+ /* Track dynamic relocs needed for local syms too.
+ We really need local syms available to do this
+ easily. Oh well. */
+
+ asection *s;
+ void **vpp;
+ Elf_Internal_Sym *isym;
+
+ isym = bfd_sym_from_r_symndx (&htab->sym_cache,
+ abfd, r_symndx);
+ if (isym == NULL)
+ return FALSE;
+
+ s = bfd_section_from_elf_index (abfd, isym->st_shndx);
+ if (s == NULL)
+ s = sec;
+
+ /* Beware of type punned pointers vs strict aliasing
+ rules. */
+ vpp = &(elf_section_data (s)->local_dynrel);
+ head = (struct elf_dyn_relocs **) vpp;
+ }
+
+ p = *head;
+ if (p == NULL || p->sec != sec)
+ {
+ bfd_size_type amt = sizeof *p;
+ p = ((struct elf_dyn_relocs *)
+ bfd_zalloc (htab->root.dynobj, amt));
+ if (p == NULL)
+ return FALSE;
+ p->next = *head;
+ *head = p;
+ p->sec = sec;
+ }
+
+ p->count += 1;
+
+ }
+ break;
+
+ /* RR: We probably want to keep a consistency check that
+ there are no dangling GOT_PAGE relocs. */
+ case R_AARCH64_LD64_GOT_LO12_NC:
+ case R_AARCH64_ADR_GOT_PAGE:
+ case R_AARCH64_TLSGD_ADR_PAGE21:
+ case R_AARCH64_TLSGD_ADD_LO12_NC:
+ case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12:
+ case R_AARCH64_TLSLE_ADD_TPREL_HI12:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G2:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0:
+ case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+ case R_AARCH64_TLSDESC_ADR_PAGE:
+ case R_AARCH64_TLSDESC_ADD_LO12_NC:
+ case R_AARCH64_TLSDESC_LD64_LO12_NC:
+ {
+ unsigned got_type;
+ unsigned old_got_type;
+
+ got_type = aarch64_reloc_got_type (r_type);
+
+ if (h)
+ {
+ h->got.refcount += 1;
+ old_got_type = elf64_aarch64_hash_entry (h)->got_type;
+ }
+ else
+ {
+ struct elf_aarch64_local_symbol *locals;
+
+ if (!elf64_aarch64_allocate_local_symbols
+ (abfd, symtab_hdr->sh_info))
+ return FALSE;
+
+ locals = elf64_aarch64_locals (abfd);
+ BFD_ASSERT (r_symndx < symtab_hdr->sh_info);
+ locals[r_symndx].got_refcount += 1;
+ old_got_type = locals[r_symndx].got_type;
+ }
+
+ /* If a variable is accessed with both general dynamic TLS
+ methods, two slots may be created. */
+ if (GOT_TLS_GD_ANY_P (old_got_type) && GOT_TLS_GD_ANY_P (got_type))
+ got_type |= old_got_type;
+
+ /* We will already have issued an error message if there
+ is a TLS/non-TLS mismatch, based on the symbol type.
+ So just combine any TLS types needed. */
+ if (old_got_type != GOT_UNKNOWN && old_got_type != GOT_NORMAL
+ && got_type != GOT_NORMAL)
+ got_type |= old_got_type;
+
+ /* If the symbol is accessed by both IE and GD methods, we
+ are able to relax. Turn off the GD flag, without
+ messing up with any other kind of TLS types that may be
+ involved. */
+ if ((got_type & GOT_TLS_IE) && GOT_TLS_GD_ANY_P (got_type))
+ got_type &= ~ (GOT_TLSDESC_GD | GOT_TLS_GD);
+
+ if (old_got_type != got_type)
+ {
+ if (h != NULL)
+ elf64_aarch64_hash_entry (h)->got_type = got_type;
+ else
+ {
+ struct elf_aarch64_local_symbol *locals;
+ locals = elf64_aarch64_locals (abfd);
+ BFD_ASSERT (r_symndx < symtab_hdr->sh_info);
+ locals[r_symndx].got_type = got_type;
+ }
+ }
+
+ if (htab->root.sgot == NULL)
+ {
+ if (htab->root.dynobj == NULL)
+ htab->root.dynobj = abfd;
+ if (!_bfd_elf_create_got_section (htab->root.dynobj, info))
+ return FALSE;
+ }
+ break;
+ }
+
+ case R_AARCH64_ADR_PREL_PG_HI21_NC:
+ case R_AARCH64_ADR_PREL_PG_HI21:
+ if (h != NULL && info->executable)
+ {
+ /* If this reloc is in a read-only section, we might
+ need a copy reloc. We can't check reliably at this
+ stage whether the section is read-only, as input
+ sections have not yet been mapped to output sections.
+ Tentatively set the flag for now, and correct in
+ adjust_dynamic_symbol. */
+ h->non_got_ref = 1;
+ h->plt.refcount += 1;
+ h->pointer_equality_needed = 1;
+ }
+ /* FIXME:: RR need to handle these in shared libraries
+ and essentially bomb out as these being non-PIC
+ relocations in shared libraries. */
+ break;
+
+ case R_AARCH64_CALL26:
+ case R_AARCH64_JUMP26:
+ /* If this is a local symbol then we resolve it
+ directly without creating a PLT entry. */
+ if (h == NULL)
+ continue;
+
+ h->needs_plt = 1;
+ h->plt.refcount += 1;
+ break;
+ }
+ }
+ return TRUE;
+}
+
+/* Treat mapping symbols as special target symbols. */
+
+static bfd_boolean
+elf64_aarch64_is_target_special_symbol (bfd *abfd ATTRIBUTE_UNUSED,
+ asymbol *sym)
+{
+ return bfd_is_aarch64_special_symbol_name (sym->name,
+ BFD_AARCH64_SPECIAL_SYM_TYPE_ANY);
+}
+
+/* This is a copy of elf_find_function () from elf.c except that
+ AArch64 mapping symbols are ignored when looking for function names. */
+
+static bfd_boolean
+aarch64_elf_find_function (bfd *abfd ATTRIBUTE_UNUSED,
+ asection *section,
+ asymbol **symbols,
+ bfd_vma offset,
+ const char **filename_ptr,
+ const char **functionname_ptr)
+{
+ const char *filename = NULL;
+ asymbol *func = NULL;
+ bfd_vma low_func = 0;
+ asymbol **p;
+
+ for (p = symbols; *p != NULL; p++)
+ {
+ elf_symbol_type *q;
+
+ q = (elf_symbol_type *) * p;
+
+ switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
+ {
+ default:
+ break;
+ case STT_FILE:
+ filename = bfd_asymbol_name (&q->symbol);
+ break;
+ case STT_FUNC:
+ case STT_NOTYPE:
+ /* Skip mapping symbols. */
+ if ((q->symbol.flags & BSF_LOCAL)
+ && (bfd_is_aarch64_special_symbol_name
+ (q->symbol.name, BFD_AARCH64_SPECIAL_SYM_TYPE_ANY)))
+ continue;
+ /* Fall through. */
+ if (bfd_get_section (&q->symbol) == section
+ && q->symbol.value >= low_func && q->symbol.value <= offset)
+ {
+ func = (asymbol *) q;
+ low_func = q->symbol.value;
+ }
+ break;
+ }
+ }
+
+ if (func == NULL)
+ return FALSE;
+
+ if (filename_ptr)
+ *filename_ptr = filename;
+ if (functionname_ptr)
+ *functionname_ptr = bfd_asymbol_name (func);
+
+ return TRUE;
+}
+
+
+/* Find the nearest line to a particular section and offset, for error
+ reporting. This code is a duplicate of the code in elf.c, except
+ that it uses aarch64_elf_find_function. */
+
+static bfd_boolean
+elf64_aarch64_find_nearest_line (bfd *abfd,
+ asection *section,
+ asymbol **symbols,
+ bfd_vma offset,
+ const char **filename_ptr,
+ const char **functionname_ptr,
+ unsigned int *line_ptr)
+{
+ bfd_boolean found = FALSE;
+
+ /* We skip _bfd_dwarf1_find_nearest_line since no known AArch64
+ toolchain uses it. */
+
+ if (_bfd_dwarf2_find_nearest_line (abfd, dwarf_debug_sections,
+ section, symbols, offset,
+ filename_ptr, functionname_ptr,
+ line_ptr, NULL, 0,
+ &elf_tdata (abfd)->dwarf2_find_line_info))
+ {
+ if (!*functionname_ptr)
+ aarch64_elf_find_function (abfd, section, symbols, offset,
+ *filename_ptr ? NULL : filename_ptr,
+ functionname_ptr);
+
+ return TRUE;
+ }
+
+ if (!_bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
+ &found, filename_ptr,
+ functionname_ptr, line_ptr,
+ &elf_tdata (abfd)->line_info))
+ return FALSE;
+
+ if (found && (*functionname_ptr || *line_ptr))
+ return TRUE;
+
+ if (symbols == NULL)
+ return FALSE;
+
+ if (!aarch64_elf_find_function (abfd, section, symbols, offset,
+ filename_ptr, functionname_ptr))
+ return FALSE;
+
+ *line_ptr = 0;
+ return TRUE;
+}
+
+static bfd_boolean
+elf64_aarch64_find_inliner_info (bfd *abfd,
+ const char **filename_ptr,
+ const char **functionname_ptr,
+ unsigned int *line_ptr)
+{
+ bfd_boolean found;
+ found = _bfd_dwarf2_find_inliner_info
+ (abfd, filename_ptr,
+ functionname_ptr, line_ptr, &elf_tdata (abfd)->dwarf2_find_line_info);
+ return found;
+}
+
+
+static void
+elf64_aarch64_post_process_headers (bfd *abfd,
+ struct bfd_link_info *link_info
+ ATTRIBUTE_UNUSED)
+{
+ Elf_Internal_Ehdr *i_ehdrp; /* ELF file header, internal form. */
+
+ i_ehdrp = elf_elfheader (abfd);
+ i_ehdrp->e_ident[EI_OSABI] = 0;
+ i_ehdrp->e_ident[EI_ABIVERSION] = AARCH64_ELF_ABI_VERSION;
+}
+
+static enum elf_reloc_type_class
+elf64_aarch64_reloc_type_class (const Elf_Internal_Rela *rela)
+{
+ switch ((int) ELF64_R_TYPE (rela->r_info))
+ {
+ case R_AARCH64_RELATIVE:
+ return reloc_class_relative;
+ case R_AARCH64_JUMP_SLOT:
+ return reloc_class_plt;
+ case R_AARCH64_COPY:
+ return reloc_class_copy;
+ default:
+ return reloc_class_normal;
+ }
+}
+
+/* Set the right machine number for an AArch64 ELF file. */
+
+static bfd_boolean
+elf64_aarch64_section_flags (flagword *flags, const Elf_Internal_Shdr *hdr)
+{
+ if (hdr->sh_type == SHT_NOTE)
+ *flags |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_SAME_CONTENTS;
+
+ return TRUE;
+}
+
+/* Handle an AArch64 specific section when reading an object file. This is
+ called when bfd_section_from_shdr finds a section with an unknown
+ type. */
+
+static bfd_boolean
+elf64_aarch64_section_from_shdr (bfd *abfd,
+ Elf_Internal_Shdr *hdr,
+ const char *name, int shindex)
+{
+ /* There ought to be a place to keep ELF backend specific flags, but
+ at the moment there isn't one. We just keep track of the
+ sections by their name, instead. Fortunately, the ABI gives
+ names for all the AArch64 specific sections, so we will probably get
+ away with this. */
+ switch (hdr->sh_type)
+ {
+ case SHT_AARCH64_ATTRIBUTES:
+ break;
+
+ default:
+ return FALSE;
+ }
+
+ if (!_bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
+ return FALSE;
+
+ return TRUE;
+}
+
+/* A structure used to record a list of sections, independently
+ of the next and prev fields in the asection structure. */
+typedef struct section_list
+{
+ asection *sec;
+ struct section_list *next;
+ struct section_list *prev;
+}
+section_list;
+
+/* Unfortunately we need to keep a list of sections for which
+ an _aarch64_elf_section_data structure has been allocated. This
+ is because it is possible for functions like elf64_aarch64_write_section
+ to be called on a section which has had an elf_data_structure
+ allocated for it (and so the used_by_bfd field is valid) but
+ for which the AArch64 extended version of this structure - the
+ _aarch64_elf_section_data structure - has not been allocated. */
+static section_list *sections_with_aarch64_elf_section_data = NULL;
+
+static void
+record_section_with_aarch64_elf_section_data (asection *sec)
+{
+ struct section_list *entry;
+
+ entry = bfd_malloc (sizeof (*entry));
+ if (entry == NULL)
+ return;
+ entry->sec = sec;
+ entry->next = sections_with_aarch64_elf_section_data;
+ entry->prev = NULL;
+ if (entry->next != NULL)
+ entry->next->prev = entry;
+ sections_with_aarch64_elf_section_data = entry;
+}
+
+static struct section_list *
+find_aarch64_elf_section_entry (asection *sec)
+{
+ struct section_list *entry;
+ static struct section_list *last_entry = NULL;
+
+ /* This is a short cut for the typical case where the sections are added
+ to the sections_with_aarch64_elf_section_data list in forward order and
+ then looked up here in backwards order. This makes a real difference
+ to the ld-srec/sec64k.exp linker test. */
+ entry = sections_with_aarch64_elf_section_data;
+ if (last_entry != NULL)
+ {
+ if (last_entry->sec == sec)
+ entry = last_entry;
+ else if (last_entry->next != NULL && last_entry->next->sec == sec)
+ entry = last_entry->next;
+ }
+
+ for (; entry; entry = entry->next)
+ if (entry->sec == sec)
+ break;
+
+ if (entry)
+ /* Record the entry prior to this one - it is the entry we are
+ most likely to want to locate next time. Also this way if we
+ have been called from
+ unrecord_section_with_aarch64_elf_section_data () we will not
+ be caching a pointer that is about to be freed. */
+ last_entry = entry->prev;
+
+ return entry;
+}
+
+static void
+unrecord_section_with_aarch64_elf_section_data (asection *sec)
+{
+ struct section_list *entry;
+
+ entry = find_aarch64_elf_section_entry (sec);
+
+ if (entry)
+ {
+ if (entry->prev != NULL)
+ entry->prev->next = entry->next;
+ if (entry->next != NULL)
+ entry->next->prev = entry->prev;
+ if (entry == sections_with_aarch64_elf_section_data)
+ sections_with_aarch64_elf_section_data = entry->next;
+ free (entry);
+ }
+}
+
+
+typedef struct
+{
+ void *finfo;
+ struct bfd_link_info *info;
+ asection *sec;
+ int sec_shndx;
+ int (*func) (void *, const char *, Elf_Internal_Sym *,
+ asection *, struct elf_link_hash_entry *);
+} output_arch_syminfo;
+
+enum map_symbol_type
+{
+ AARCH64_MAP_INSN,
+ AARCH64_MAP_DATA
+};
+
+
+/* Output a single mapping symbol. */
+
+static bfd_boolean
+elf64_aarch64_output_map_sym (output_arch_syminfo *osi,
+ enum map_symbol_type type, bfd_vma offset)
+{
+ static const char *names[2] = { "$x", "$d" };
+ Elf_Internal_Sym sym;
+
+ sym.st_value = (osi->sec->output_section->vma
+ + osi->sec->output_offset + offset);
+ sym.st_size = 0;
+ sym.st_other = 0;
+ sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
+ sym.st_shndx = osi->sec_shndx;
+ return osi->func (osi->finfo, names[type], &sym, osi->sec, NULL) == 1;
+}
+
+
+
+/* Output mapping symbols for PLT entries associated with H. */
+
+static bfd_boolean
+elf64_aarch64_output_plt_map (struct elf_link_hash_entry *h, void *inf)
+{
+ output_arch_syminfo *osi = (output_arch_syminfo *) inf;
+ bfd_vma addr;
+
+ if (h->root.type == bfd_link_hash_indirect)
+ return TRUE;
+
+ if (h->root.type == bfd_link_hash_warning)
+ /* When warning symbols are created, they **replace** the "real"
+ entry in the hash table, thus we never get to see the real
+ symbol in a hash traversal. So look at it now. */
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ if (h->plt.offset == (bfd_vma) - 1)
+ return TRUE;
+
+ addr = h->plt.offset;
+ if (addr == 32)
+ {
+ if (!elf64_aarch64_output_map_sym (osi, AARCH64_MAP_INSN, addr))
+ return FALSE;
+ }
+ return TRUE;
+}
+
+
+/* Output a single local symbol for a generated stub. */
+
+static bfd_boolean
+elf64_aarch64_output_stub_sym (output_arch_syminfo *osi, const char *name,
+ bfd_vma offset, bfd_vma size)
+{
+ Elf_Internal_Sym sym;
+
+ sym.st_value = (osi->sec->output_section->vma
+ + osi->sec->output_offset + offset);
+ sym.st_size = size;
+ sym.st_other = 0;
+ sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
+ sym.st_shndx = osi->sec_shndx;
+ return osi->func (osi->finfo, name, &sym, osi->sec, NULL) == 1;
+}
+
+static bfd_boolean
+aarch64_map_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
+{
+ struct elf64_aarch64_stub_hash_entry *stub_entry;
+ asection *stub_sec;
+ bfd_vma addr;
+ char *stub_name;
+ output_arch_syminfo *osi;
+
+ /* Massage our args to the form they really have. */
+ stub_entry = (struct elf64_aarch64_stub_hash_entry *) gen_entry;
+ osi = (output_arch_syminfo *) in_arg;
+
+ stub_sec = stub_entry->stub_sec;
+
+ /* Ensure this stub is attached to the current section being
+ processed. */
+ if (stub_sec != osi->sec)
+ return TRUE;
+
+ addr = (bfd_vma) stub_entry->stub_offset;
+
+ stub_name = stub_entry->output_name;
+
+ switch (stub_entry->stub_type)
+ {
+ case aarch64_stub_adrp_branch:
+ if (!elf64_aarch64_output_stub_sym (osi, stub_name, addr,
+ sizeof (aarch64_adrp_branch_stub)))
+ return FALSE;
+ if (!elf64_aarch64_output_map_sym (osi, AARCH64_MAP_INSN, addr))
+ return FALSE;
+ break;
+ case aarch64_stub_long_branch:
+ if (!elf64_aarch64_output_stub_sym
+ (osi, stub_name, addr, sizeof (aarch64_long_branch_stub)))
+ return FALSE;
+ if (!elf64_aarch64_output_map_sym (osi, AARCH64_MAP_INSN, addr))
+ return FALSE;
+ if (!elf64_aarch64_output_map_sym (osi, AARCH64_MAP_DATA, addr + 16))
+ return FALSE;
+ break;
+ default:
+ BFD_FAIL ();
+ }
+
+ return TRUE;
+}
+
+/* Output mapping symbols for linker generated sections. */
+
+static bfd_boolean
+elf64_aarch64_output_arch_local_syms (bfd *output_bfd,
+ struct bfd_link_info *info,
+ void *finfo,
+ int (*func) (void *, const char *,
+ Elf_Internal_Sym *,
+ asection *,
+ struct elf_link_hash_entry
+ *))
+{
+ output_arch_syminfo osi;
+ struct elf64_aarch64_link_hash_table *htab;
+
+ htab = elf64_aarch64_hash_table (info);
+
+ osi.finfo = finfo;
+ osi.info = info;
+ osi.func = func;
+
+ /* Long calls stubs. */
+ if (htab->stub_bfd && htab->stub_bfd->sections)
+ {
+ asection *stub_sec;
+
+ for (stub_sec = htab->stub_bfd->sections;
+ stub_sec != NULL; stub_sec = stub_sec->next)
+ {
+ /* Ignore non-stub sections. */
+ if (!strstr (stub_sec->name, STUB_SUFFIX))
+ continue;
+
+ osi.sec = stub_sec;
+
+ osi.sec_shndx = _bfd_elf_section_from_bfd_section
+ (output_bfd, osi.sec->output_section);
+
+ bfd_hash_traverse (&htab->stub_hash_table, aarch64_map_one_stub,
+ &osi);
+ }
+ }
+
+ /* Finally, output mapping symbols for the PLT. */
+ if (!htab->root.splt || htab->root.splt->size == 0)
+ return TRUE;
+
+ /* For now live without mapping symbols for the plt. */
+ osi.sec_shndx = _bfd_elf_section_from_bfd_section
+ (output_bfd, htab->root.splt->output_section);
+ osi.sec = htab->root.splt;
+
+ elf_link_hash_traverse (&htab->root, elf64_aarch64_output_plt_map,
+ (void *) &osi);
+
+ return TRUE;
+
+}
+
+/* Allocate target specific section data. */
+
+static bfd_boolean
+elf64_aarch64_new_section_hook (bfd *abfd, asection *sec)
+{
+ if (!sec->used_by_bfd)
+ {
+ _aarch64_elf_section_data *sdata;
+ bfd_size_type amt = sizeof (*sdata);
+
+ sdata = bfd_zalloc (abfd, amt);
+ if (sdata == NULL)
+ return FALSE;
+ sec->used_by_bfd = sdata;
+ }
+
+ record_section_with_aarch64_elf_section_data (sec);
+
+ return _bfd_elf_new_section_hook (abfd, sec);
+}
+
+
+static void
+unrecord_section_via_map_over_sections (bfd *abfd ATTRIBUTE_UNUSED,
+ asection *sec,
+ void *ignore ATTRIBUTE_UNUSED)
+{
+ unrecord_section_with_aarch64_elf_section_data (sec);
+}
+
+static bfd_boolean
+elf64_aarch64_close_and_cleanup (bfd *abfd)
+{
+ if (abfd->sections)
+ bfd_map_over_sections (abfd,
+ unrecord_section_via_map_over_sections, NULL);
+
+ return _bfd_elf_close_and_cleanup (abfd);
+}
+
+static bfd_boolean
+elf64_aarch64_bfd_free_cached_info (bfd *abfd)
+{
+ if (abfd->sections)
+ bfd_map_over_sections (abfd,
+ unrecord_section_via_map_over_sections, NULL);
+
+ return _bfd_free_cached_info (abfd);
+}
+
+static bfd_boolean
+elf64_aarch64_is_function_type (unsigned int type)
+{
+ return type == STT_FUNC;
+}
+
+/* Create dynamic sections. This is different from the ARM backend in that
+ the got, plt, gotplt and their relocation sections are all created in the
+ standard part of the bfd elf backend. */
+
+static bfd_boolean
+elf64_aarch64_create_dynamic_sections (bfd *dynobj,
+ struct bfd_link_info *info)
+{
+ struct elf64_aarch64_link_hash_table *htab;
+ struct elf_link_hash_entry *h;
+
+ if (!_bfd_elf_create_dynamic_sections (dynobj, info))
+ return FALSE;
+
+ htab = elf64_aarch64_hash_table (info);
+ htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
+ if (!info->shared)
+ htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss");
+
+ if (!htab->sdynbss || (!info->shared && !htab->srelbss))
+ abort ();
+
+ /* Define the symbol _GLOBAL_OFFSET_TABLE_ at the start of the
+ dynobj's .got section. We don't do this in the linker script
+ because we don't want to define the symbol if we are not creating
+ a global offset table. */
+ h = _bfd_elf_define_linkage_sym (dynobj, info,
+ htab->root.sgot, "_GLOBAL_OFFSET_TABLE_");
+ elf_hash_table (info)->hgot = h;
+ if (h == NULL)
+ return FALSE;
+
+ return TRUE;
+}
+
+
+/* Allocate space in .plt, .got and associated reloc sections for
+ dynamic relocs. */
+
+static bfd_boolean
+elf64_aarch64_allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf)
+{
+ struct bfd_link_info *info;
+ struct elf64_aarch64_link_hash_table *htab;
+ struct elf64_aarch64_link_hash_entry *eh;
+ struct elf_dyn_relocs *p;
+
+ /* An example of a bfd_link_hash_indirect symbol is versioned
+ symbol. For example: __gxx_personality_v0(bfd_link_hash_indirect)
+ -> __gxx_personality_v0(bfd_link_hash_defined)
+
+ There is no need to process bfd_link_hash_indirect symbols here
+ because we will also be presented with the concrete instance of
+ the symbol and elf64_aarch64_copy_indirect_symbol () will have been
+ called to copy all relevant data from the generic to the concrete
+ symbol instance.
+ */
+ if (h->root.type == bfd_link_hash_indirect)
+ return TRUE;
+
+ if (h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ info = (struct bfd_link_info *) inf;
+ htab = elf64_aarch64_hash_table (info);
+
+ if (htab->root.dynamic_sections_created && h->plt.refcount > 0)
+ {
+ /* Make sure this symbol is output as a dynamic symbol.
+ Undefined weak syms won't yet be marked as dynamic. */
+ if (h->dynindx == -1 && !h->forced_local)
+ {
+ if (!bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+ }
+
+ if (info->shared || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
+ {
+ asection *s = htab->root.splt;
+
+ /* If this is the first .plt entry, make room for the special
+ first entry. */
+ if (s->size == 0)
+ s->size += htab->plt_header_size;
+
+ h->plt.offset = s->size;
+
+ /* If this symbol is not defined in a regular file, and we are
+ not generating a shared library, then set the symbol to this
+ location in the .plt. This is required to make function
+ pointers compare as equal between the normal executable and
+ the shared library. */
+ if (!info->shared && !h->def_regular)
+ {
+ h->root.u.def.section = s;
+ h->root.u.def.value = h->plt.offset;
+ }
+
+ /* Make room for this entry. For now we only create the
+ small model PLT entries. We later need to find a way
+ of relaxing into these from the large model PLT entries. */
+ s->size += PLT_SMALL_ENTRY_SIZE;
+
+ /* We also need to make an entry in the .got.plt section, which
+ will be placed in the .got section by the linker script. */
+ htab->root.sgotplt->size += GOT_ENTRY_SIZE;
+
+ /* We also need to make an entry in the .rela.plt section. */
+ htab->root.srelplt->size += RELOC_SIZE (htab);
+
+ /* We need to ensure that all GOT entries that serve the PLT
+ are consecutive with the special GOT slots [0] [1] and
+ [2]. Any addtional relocations, such as
+ R_AARCH64_TLSDESC, must be placed after the PLT related
+ entries. We abuse the reloc_count such that during
+ sizing we adjust reloc_count to indicate the number of
+ PLT related reserved entries. In subsequent phases when
+ filling in the contents of the reloc entries, PLT related
+ entries are placed by computing their PLT index (0
+ .. reloc_count). While other none PLT relocs are placed
+ at the slot indicated by reloc_count and reloc_count is
+ updated. */
+
+ htab->root.srelplt->reloc_count++;
+ }
+ else
+ {
+ h->plt.offset = (bfd_vma) - 1;
+ h->needs_plt = 0;
+ }
+ }
+ else
+ {
+ h->plt.offset = (bfd_vma) - 1;
+ h->needs_plt = 0;
+ }
+
+ eh = (struct elf64_aarch64_link_hash_entry *) h;
+ eh->tlsdesc_got_jump_table_offset = (bfd_vma) - 1;
+
+ if (h->got.refcount > 0)
+ {
+ bfd_boolean dyn;
+ unsigned got_type = elf64_aarch64_hash_entry (h)->got_type;
+
+ h->got.offset = (bfd_vma) - 1;
+
+ dyn = htab->root.dynamic_sections_created;
+
+ /* Make sure this symbol is output as a dynamic symbol.
+ Undefined weak syms won't yet be marked as dynamic. */
+ if (dyn && h->dynindx == -1 && !h->forced_local)
+ {
+ if (!bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+ }
+
+ if (got_type == GOT_UNKNOWN)
+ {
+ }
+ else if (got_type == GOT_NORMAL)
+ {
+ h->got.offset = htab->root.sgot->size;
+ htab->root.sgot->size += GOT_ENTRY_SIZE;
+ if ((ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
+ || h->root.type != bfd_link_hash_undefweak)
+ && (info->shared
+ || WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, 0, h)))
+ {
+ htab->root.srelgot->size += RELOC_SIZE (htab);
+ }
+ }
+ else
+ {
+ int indx;
+ if (got_type & GOT_TLSDESC_GD)
+ {
+ eh->tlsdesc_got_jump_table_offset =
+ (htab->root.sgotplt->size
+ - aarch64_compute_jump_table_size (htab));
+ htab->root.sgotplt->size += GOT_ENTRY_SIZE * 2;
+ h->got.offset = (bfd_vma) - 2;
+ }
+
+ if (got_type & GOT_TLS_GD)
+ {
+ h->got.offset = htab->root.sgot->size;
+ htab->root.sgot->size += GOT_ENTRY_SIZE * 2;
+ }
+
+ if (got_type & GOT_TLS_IE)
+ {
+ h->got.offset = htab->root.sgot->size;
+ htab->root.sgot->size += GOT_ENTRY_SIZE;
+ }
+
+ indx = h && h->dynindx != -1 ? h->dynindx : 0;
+ if ((ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
+ || h->root.type != bfd_link_hash_undefweak)
+ && (info->shared
+ || indx != 0
+ || WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, 0, h)))
+ {
+ if (got_type & GOT_TLSDESC_GD)
+ {
+ htab->root.srelplt->size += RELOC_SIZE (htab);
+ /* Note reloc_count not incremented here! We have
+ already adjusted reloc_count for this relocation
+ type. */
+
+ /* TLSDESC PLT is now needed, but not yet determined. */
+ htab->tlsdesc_plt = (bfd_vma) - 1;
+ }
+
+ if (got_type & GOT_TLS_GD)
+ htab->root.srelgot->size += RELOC_SIZE (htab) * 2;
+
+ if (got_type & GOT_TLS_IE)
+ htab->root.srelgot->size += RELOC_SIZE (htab);
+ }
+ }
+ }
+ else
+ {
+ h->got.offset = (bfd_vma) - 1;
+ }
+
+ if (eh->dyn_relocs == NULL)
+ return TRUE;
+
+ /* In the shared -Bsymbolic case, discard space allocated for
+ dynamic pc-relative relocs against symbols which turn out to be
+ defined in regular objects. For the normal shared case, discard
+ space for pc-relative relocs that have become local due to symbol
+ visibility changes. */
+
+ if (info->shared)
+ {
+ /* Relocs that use pc_count are those that appear on a call
+ insn, or certain REL relocs that can generated via assembly.
+ We want calls to protected symbols to resolve directly to the
+ function rather than going via the plt. If people want
+ function pointer comparisons to work as expected then they
+ should avoid writing weird assembly. */
+ if (SYMBOL_CALLS_LOCAL (info, h))
+ {
+ struct elf_dyn_relocs **pp;
+
+ for (pp = &eh->dyn_relocs; (p = *pp) != NULL;)
+ {
+ p->count -= p->pc_count;
+ p->pc_count = 0;
+ if (p->count == 0)
+ *pp = p->next;
+ else
+ pp = &p->next;
+ }
+ }
+
+ /* Also discard relocs on undefined weak syms with non-default
+ visibility. */
+ if (eh->dyn_relocs != NULL && h->root.type == bfd_link_hash_undefweak)
+ {
+ if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
+ eh->dyn_relocs = NULL;
+
+ /* Make sure undefined weak symbols are output as a dynamic
+ symbol in PIEs. */
+ else if (h->dynindx == -1
+ && !h->forced_local
+ && !bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+ }
+
+ }
+ else if (ELIMINATE_COPY_RELOCS)
+ {
+ /* For the non-shared case, discard space for relocs against
+ symbols which turn out to need copy relocs or are not
+ dynamic. */
+
+ if (!h->non_got_ref
+ && ((h->def_dynamic
+ && !h->def_regular)
+ || (htab->root.dynamic_sections_created
+ && (h->root.type == bfd_link_hash_undefweak
+ || h->root.type == bfd_link_hash_undefined))))
+ {
+ /* Make sure this symbol is output as a dynamic symbol.
+ Undefined weak syms won't yet be marked as dynamic. */
+ if (h->dynindx == -1
+ && !h->forced_local
+ && !bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+
+ /* If that succeeded, we know we'll be keeping all the
+ relocs. */
+ if (h->dynindx != -1)
+ goto keep;
+ }
+
+ eh->dyn_relocs = NULL;
+
+ keep:;
+ }
+
+ /* Finally, allocate space. */
+ for (p = eh->dyn_relocs; p != NULL; p = p->next)
+ {
+ asection *sreloc;
+
+ sreloc = elf_section_data (p->sec)->sreloc;
+
+ BFD_ASSERT (sreloc != NULL);
+
+ sreloc->size += p->count * RELOC_SIZE (htab);
+ }
+
+ return TRUE;
+}
+
+
+
+
+/* This is the most important function of all . Innocuosly named
+ though ! */
+static bfd_boolean
+elf64_aarch64_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ struct bfd_link_info *info)
+{
+ struct elf64_aarch64_link_hash_table *htab;
+ bfd *dynobj;
+ asection *s;
+ bfd_boolean relocs;
+ bfd *ibfd;
+
+ htab = elf64_aarch64_hash_table ((info));
+ dynobj = htab->root.dynobj;
+
+ BFD_ASSERT (dynobj != NULL);
+
+ if (htab->root.dynamic_sections_created)
+ {
+ if (info->executable)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+ abort ();
+ s->size = sizeof ELF_DYNAMIC_INTERPRETER;
+ s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
+ }
+ }
+
+ /* Set up .got offsets for local syms, and space for local dynamic
+ relocs. */
+ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next)
+ {
+ struct elf_aarch64_local_symbol *locals = NULL;
+ Elf_Internal_Shdr *symtab_hdr;
+ asection *srel;
+ unsigned int i;
+
+ if (!is_aarch64_elf (ibfd))
+ continue;
+
+ for (s = ibfd->sections; s != NULL; s = s->next)
+ {
+ struct elf_dyn_relocs *p;
+
+ for (p = (struct elf_dyn_relocs *)
+ (elf_section_data (s)->local_dynrel); p != NULL; p = p->next)
+ {
+ if (!bfd_is_abs_section (p->sec)
+ && bfd_is_abs_section (p->sec->output_section))
+ {
+ /* Input section has been discarded, either because
+ it is a copy of a linkonce section or due to
+ linker script /DISCARD/, so we'll be discarding
+ the relocs too. */
+ }
+ else if (p->count != 0)
+ {
+ srel = elf_section_data (p->sec)->sreloc;
+ srel->size += p->count * RELOC_SIZE (htab);
+ if ((p->sec->output_section->flags & SEC_READONLY) != 0)
+ info->flags |= DF_TEXTREL;
+ }
+ }
+ }
+
+ locals = elf64_aarch64_locals (ibfd);
+ if (!locals)
+ continue;
+
+ symtab_hdr = &elf_symtab_hdr (ibfd);
+ srel = htab->root.srelgot;
+ for (i = 0; i < symtab_hdr->sh_info; i++)
+ {
+ locals[i].got_offset = (bfd_vma) - 1;
+ locals[i].tlsdesc_got_jump_table_offset = (bfd_vma) - 1;
+ if (locals[i].got_refcount > 0)
+ {
+ unsigned got_type = locals[i].got_type;
+ if (got_type & GOT_TLSDESC_GD)
+ {
+ locals[i].tlsdesc_got_jump_table_offset =
+ (htab->root.sgotplt->size
+ - aarch64_compute_jump_table_size (htab));
+ htab->root.sgotplt->size += GOT_ENTRY_SIZE * 2;
+ locals[i].got_offset = (bfd_vma) - 2;
+ }
+
+ if (got_type & GOT_TLS_GD)
+ {
+ locals[i].got_offset = htab->root.sgot->size;
+ htab->root.sgot->size += GOT_ENTRY_SIZE * 2;
+ }
+
+ if (got_type & GOT_TLS_IE)
+ {
+ locals[i].got_offset = htab->root.sgot->size;
+ htab->root.sgot->size += GOT_ENTRY_SIZE;
+ }
+
+ if (got_type == GOT_UNKNOWN)
+ {
+ }
+
+ if (got_type == GOT_NORMAL)
+ {
+ }
+
+ if (info->shared)
+ {
+ if (got_type & GOT_TLSDESC_GD)
+ {
+ htab->root.srelplt->size += RELOC_SIZE (htab);
+ /* Note RELOC_COUNT not incremented here! */
+ htab->tlsdesc_plt = (bfd_vma) - 1;
+ }
+
+ if (got_type & GOT_TLS_GD)
+ htab->root.srelgot->size += RELOC_SIZE (htab) * 2;
+
+ if (got_type & GOT_TLS_IE)
+ htab->root.srelgot->size += RELOC_SIZE (htab);
+ }
+ }
+ else
+ {
+ locals[i].got_refcount = (bfd_vma) - 1;
+ }
+ }
+ }
+
+
+ /* Allocate global sym .plt and .got entries, and space for global
+ sym dynamic relocs. */
+ elf_link_hash_traverse (&htab->root, elf64_aarch64_allocate_dynrelocs,
+ info);
+
+
+ /* For every jump slot reserved in the sgotplt, reloc_count is
+ incremented. However, when we reserve space for TLS descriptors,
+ it's not incremented, so in order to compute the space reserved
+ for them, it suffices to multiply the reloc count by the jump
+ slot size. */
+
+ if (htab->root.srelplt)
+ htab->sgotplt_jump_table_size = aarch64_compute_jump_table_size (htab);
+
+ if (htab->tlsdesc_plt)
+ {
+ if (htab->root.splt->size == 0)
+ htab->root.splt->size += PLT_ENTRY_SIZE;
+
+ htab->tlsdesc_plt = htab->root.splt->size;
+ htab->root.splt->size += PLT_TLSDESC_ENTRY_SIZE;
+
+ /* If we're not using lazy TLS relocations, don't generate the
+ GOT entry required. */
+ if (!(info->flags & DF_BIND_NOW))
+ {
+ htab->dt_tlsdesc_got = htab->root.sgot->size;
+ htab->root.sgot->size += GOT_ENTRY_SIZE;
+ }
+ }
+
+ /* We now have determined the sizes of the various dynamic sections.
+ Allocate memory for them. */
+ relocs = FALSE;
+ for (s = dynobj->sections; s != NULL; s = s->next)
+ {
+ if ((s->flags & SEC_LINKER_CREATED) == 0)
+ continue;
+
+ if (s == htab->root.splt
+ || s == htab->root.sgot
+ || s == htab->root.sgotplt
+ || s == htab->root.iplt
+ || s == htab->root.igotplt || s == htab->sdynbss)
+ {
+ /* Strip this section if we don't need it; see the
+ comment below. */
+ }
+ else if (CONST_STRNEQ (bfd_get_section_name (dynobj, s), ".rela"))
+ {
+ if (s->size != 0 && s != htab->root.srelplt)
+ relocs = TRUE;
+
+ /* We use the reloc_count field as a counter if we need
+ to copy relocs into the output file. */
+ if (s != htab->root.srelplt)
+ s->reloc_count = 0;
+ }
+ else
+ {
+ /* It's not one of our sections, so don't allocate space. */
+ continue;
+ }
+
+ if (s->size == 0)
+ {
+ /* If we don't need this section, strip it from the
+ output file. This is mostly to handle .rela.bss and
+ .rela.plt. We must create both sections in
+ create_dynamic_sections, because they must be created
+ before the linker maps input sections to output
+ sections. The linker does that before
+ adjust_dynamic_symbol is called, and it is that
+ function which decides whether anything needs to go
+ into these sections. */
+
+ s->flags |= SEC_EXCLUDE;
+ continue;
+ }
+
+ if ((s->flags & SEC_HAS_CONTENTS) == 0)
+ continue;
+
+ /* Allocate memory for the section contents. We use bfd_zalloc
+ here in case unused entries are not reclaimed before the
+ section's contents are written out. This should not happen,
+ but this way if it does, we get a R_AARCH64_NONE reloc instead
+ of garbage. */
+ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size);
+ if (s->contents == NULL)
+ return FALSE;
+ }
+
+ if (htab->root.dynamic_sections_created)
+ {
+ /* Add some entries to the .dynamic section. We fill in the
+ values later, in elf64_aarch64_finish_dynamic_sections, but we
+ must add the entries now so that we get the correct size for
+ the .dynamic section. The DT_DEBUG entry is filled in by the
+ dynamic linker and used by the debugger. */
+#define add_dynamic_entry(TAG, VAL) \
+ _bfd_elf_add_dynamic_entry (info, TAG, VAL)
+
+ if (info->executable)
+ {
+ if (!add_dynamic_entry (DT_DEBUG, 0))
+ return FALSE;
+ }
+
+ if (htab->root.splt->size != 0)
+ {
+ if (!add_dynamic_entry (DT_PLTGOT, 0)
+ || !add_dynamic_entry (DT_PLTRELSZ, 0)
+ || !add_dynamic_entry (DT_PLTREL, DT_RELA)
+ || !add_dynamic_entry (DT_JMPREL, 0))
+ return FALSE;
+
+ if (htab->tlsdesc_plt
+ && (!add_dynamic_entry (DT_TLSDESC_PLT, 0)
+ || !add_dynamic_entry (DT_TLSDESC_GOT, 0)))
+ return FALSE;
+ }
+
+ if (relocs)
+ {
+ if (!add_dynamic_entry (DT_RELA, 0)
+ || !add_dynamic_entry (DT_RELASZ, 0)
+ || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
+ return FALSE;
+
+ /* If any dynamic relocs apply to a read-only section,
+ then we need a DT_TEXTREL entry. */
+ if ((info->flags & DF_TEXTREL) != 0)
+ {
+ if (!add_dynamic_entry (DT_TEXTREL, 0))
+ return FALSE;
+ }
+ }
+ }
+#undef add_dynamic_entry
+
+ return TRUE;
+
+
+}
+
+static inline void
+elf64_aarch64_update_plt_entry (bfd *output_bfd,
+ unsigned int r_type,
+ bfd_byte *plt_entry, bfd_vma value)
+{
+ reloc_howto_type *howto;
+ howto = elf64_aarch64_howto_from_type (r_type);
+ bfd_elf_aarch64_put_addend (output_bfd, plt_entry, howto, value);
+}
+
+static void
+elf64_aarch64_create_small_pltn_entry (struct elf_link_hash_entry *h,
+ struct elf64_aarch64_link_hash_table
+ *htab, bfd *output_bfd)
+{
+ bfd_byte *plt_entry;
+ bfd_vma plt_index;
+ bfd_vma got_offset;
+ bfd_vma gotplt_entry_address;
+ bfd_vma plt_entry_address;
+ Elf_Internal_Rela rela;
+ bfd_byte *loc;
+
+ plt_index = (h->plt.offset - htab->plt_header_size) / htab->plt_entry_size;
+
+ /* Offset in the GOT is PLT index plus got GOT headers(3)
+ times 8. */
+ got_offset = (plt_index + 3) * GOT_ENTRY_SIZE;
+ plt_entry = htab->root.splt->contents + h->plt.offset;
+ plt_entry_address = htab->root.splt->output_section->vma
+ + htab->root.splt->output_section->output_offset + h->plt.offset;
+ gotplt_entry_address = htab->root.sgotplt->output_section->vma +
+ htab->root.sgotplt->output_offset + got_offset;
+
+ /* Copy in the boiler-plate for the PLTn entry. */
+ memcpy (plt_entry, elf64_aarch64_small_plt_entry, PLT_SMALL_ENTRY_SIZE);
+
+ /* Fill in the top 21 bits for this: ADRP x16, PLT_GOT + n * 8.
+ ADRP: ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */
+ elf64_aarch64_update_plt_entry (output_bfd, R_AARCH64_ADR_PREL_PG_HI21,
+ plt_entry,
+ PG (gotplt_entry_address) -
+ PG (plt_entry_address));
+
+ /* Fill in the lo12 bits for the load from the pltgot. */
+ elf64_aarch64_update_plt_entry (output_bfd, R_AARCH64_LDST64_ABS_LO12_NC,
+ plt_entry + 4,
+ PG_OFFSET (gotplt_entry_address));
+
+ /* Fill in the the lo12 bits for the add from the pltgot entry. */
+ elf64_aarch64_update_plt_entry (output_bfd, R_AARCH64_ADD_ABS_LO12_NC,
+ plt_entry + 8,
+ PG_OFFSET (gotplt_entry_address));
+
+ /* All the GOTPLT Entries are essentially initialized to PLT0. */
+ bfd_put_64 (output_bfd,
+ (htab->root.splt->output_section->vma
+ + htab->root.splt->output_offset),
+ htab->root.sgotplt->contents + got_offset);
+
+ /* Fill in the entry in the .rela.plt section. */
+ rela.r_offset = gotplt_entry_address;
+ rela.r_info = ELF64_R_INFO (h->dynindx, R_AARCH64_JUMP_SLOT);
+ rela.r_addend = 0;
+
+ /* Compute the relocation entry to used based on PLT index and do
+ not adjust reloc_count. The reloc_count has already been adjusted
+ to account for this entry. */
+ loc = htab->root.srelplt->contents + plt_index * RELOC_SIZE (htab);
+ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+}
+
+/* Size sections even though they're not dynamic. We use it to setup
+ _TLS_MODULE_BASE_, if needed. */
+
+static bfd_boolean
+elf64_aarch64_always_size_sections (bfd *output_bfd,
+ struct bfd_link_info *info)
+{
+ asection *tls_sec;
+
+ if (info->relocatable)
+ return TRUE;
+
+ tls_sec = elf_hash_table (info)->tls_sec;
+
+ if (tls_sec)
+ {
+ struct elf_link_hash_entry *tlsbase;
+
+ tlsbase = elf_link_hash_lookup (elf_hash_table (info),
+ "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
+
+ if (tlsbase)
+ {
+ struct bfd_link_hash_entry *h = NULL;
+ const struct elf_backend_data *bed =
+ get_elf_backend_data (output_bfd);
+
+ if (!(_bfd_generic_link_add_one_symbol
+ (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
+ tls_sec, 0, NULL, FALSE, bed->collect, &h)))
+ return FALSE;
+
+ tlsbase->type = STT_TLS;
+ tlsbase = (struct elf_link_hash_entry *) h;
+ tlsbase->def_regular = 1;
+ tlsbase->other = STV_HIDDEN;
+ (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
+ }
+ }
+
+ return TRUE;
+}
+
+/* Finish up dynamic symbol handling. We set the contents of various
+ dynamic sections here. */
+static bfd_boolean
+elf64_aarch64_finish_dynamic_symbol (bfd *output_bfd,
+ struct bfd_link_info *info,
+ struct elf_link_hash_entry *h,
+ Elf_Internal_Sym *sym)
+{
+ struct elf64_aarch64_link_hash_table *htab;
+ htab = elf64_aarch64_hash_table (info);
+
+ if (h->plt.offset != (bfd_vma) - 1)
+ {
+ /* This symbol has an entry in the procedure linkage table. Set
+ it up. */
+
+ if (h->dynindx == -1
+ || htab->root.splt == NULL
+ || htab->root.sgotplt == NULL || htab->root.srelplt == NULL)
+ abort ();
+
+ elf64_aarch64_create_small_pltn_entry (h, htab, output_bfd);
+ if (!h->def_regular)
+ {
+ /* Mark the symbol as undefined, rather than as defined in
+ the .plt section. Leave the value alone. This is a clue
+ for the dynamic linker, to make function pointer
+ comparisons work between an application and shared
+ library. */
+ sym->st_shndx = SHN_UNDEF;
+ }
+ }
+
+ if (h->got.offset != (bfd_vma) - 1
+ && elf64_aarch64_hash_entry (h)->got_type == GOT_NORMAL)
+ {
+ Elf_Internal_Rela rela;
+ bfd_byte *loc;
+
+ /* This symbol has an entry in the global offset table. Set it
+ up. */
+ if (htab->root.sgot == NULL || htab->root.srelgot == NULL)
+ abort ();
+
+ rela.r_offset = (htab->root.sgot->output_section->vma
+ + htab->root.sgot->output_offset
+ + (h->got.offset & ~(bfd_vma) 1));
+
+ if (info->shared && SYMBOL_REFERENCES_LOCAL (info, h))
+ {
+ if (!h->def_regular)
+ return FALSE;
+
+ BFD_ASSERT ((h->got.offset & 1) != 0);
+ rela.r_info = ELF64_R_INFO (0, R_AARCH64_RELATIVE);
+ rela.r_addend = (h->root.u.def.value
+ + h->root.u.def.section->output_section->vma
+ + h->root.u.def.section->output_offset);
+ }
+ else
+ {
+ BFD_ASSERT ((h->got.offset & 1) == 0);
+ bfd_put_64 (output_bfd, (bfd_vma) 0,
+ htab->root.sgot->contents + h->got.offset);
+ rela.r_info = ELF64_R_INFO (h->dynindx, R_AARCH64_GLOB_DAT);
+ rela.r_addend = 0;
+ }
+
+ loc = htab->root.srelgot->contents;
+ loc += htab->root.srelgot->reloc_count++ * RELOC_SIZE (htab);
+ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+ }
+
+ if (h->needs_copy)
+ {
+ Elf_Internal_Rela rela;
+ bfd_byte *loc;
+
+ /* This symbol needs a copy reloc. Set it up. */
+
+ if (h->dynindx == -1
+ || (h->root.type != bfd_link_hash_defined
+ && h->root.type != bfd_link_hash_defweak)
+ || htab->srelbss == NULL)
+ abort ();
+
+ rela.r_offset = (h->root.u.def.value
+ + h->root.u.def.section->output_section->vma
+ + h->root.u.def.section->output_offset);
+ rela.r_info = ELF64_R_INFO (h->dynindx, R_AARCH64_COPY);
+ rela.r_addend = 0;
+ loc = htab->srelbss->contents;
+ loc += htab->srelbss->reloc_count++ * RELOC_SIZE (htab);
+ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+ }
+
+ /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. SYM may
+ be NULL for local symbols. */
+ if (sym != NULL
+ && (strcmp (h->root.root.string, "_DYNAMIC") == 0
+ || h == elf_hash_table (info)->hgot))
+ sym->st_shndx = SHN_ABS;
+
+ return TRUE;
+}
+
+static void
+elf64_aarch64_init_small_plt0_entry (bfd *output_bfd ATTRIBUTE_UNUSED,
+ struct elf64_aarch64_link_hash_table
+ *htab)
+{
+ /* Fill in PLT0. Fixme:RR Note this doesn't distinguish between
+ small and large plts and at the minute just generates
+ the small PLT. */
+
+ /* PLT0 of the small PLT looks like this -
+ stp x16, x30, [sp, #-16]! // Save the reloc and lr on stack.
+ adrp x16, PLT_GOT + 16 // Get the page base of the GOTPLT
+ ldr x17, [x16, #:lo12:PLT_GOT+16] // Load the address of the
+ // symbol resolver
+ add x16, x16, #:lo12:PLT_GOT+16 // Load the lo12 bits of the
+ // GOTPLT entry for this.
+ br x17
+ */
+ bfd_vma plt_got_base;
+ bfd_vma plt_base;
+
+
+ memcpy (htab->root.splt->contents, elf64_aarch64_small_plt0_entry,
+ PLT_ENTRY_SIZE);
+ elf_section_data (htab->root.splt->output_section)->this_hdr.sh_entsize =
+ PLT_ENTRY_SIZE;
+
+ plt_got_base = (htab->root.sgotplt->output_section->vma
+ + htab->root.sgotplt->output_offset);
+
+ plt_base = htab->root.splt->output_section->vma +
+ htab->root.splt->output_section->output_offset;
+
+ /* Fill in the top 21 bits for this: ADRP x16, PLT_GOT + n * 8.
+ ADRP: ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */
+ elf64_aarch64_update_plt_entry (output_bfd, R_AARCH64_ADR_PREL_PG_HI21,
+ htab->root.splt->contents + 4,
+ PG (plt_got_base + 16) - PG (plt_base + 4));
+
+ elf64_aarch64_update_plt_entry (output_bfd, R_AARCH64_LDST64_ABS_LO12_NC,
+ htab->root.splt->contents + 8,
+ PG_OFFSET (plt_got_base + 16));
+
+ elf64_aarch64_update_plt_entry (output_bfd, R_AARCH64_ADD_ABS_LO12_NC,
+ htab->root.splt->contents + 12,
+ PG_OFFSET (plt_got_base + 16));
+}
+
+static bfd_boolean
+elf64_aarch64_finish_dynamic_sections (bfd *output_bfd,
+ struct bfd_link_info *info)
+{
+ struct elf64_aarch64_link_hash_table *htab;
+ bfd *dynobj;
+ asection *sdyn;
+
+ htab = elf64_aarch64_hash_table (info);
+ dynobj = htab->root.dynobj;
+ sdyn = bfd_get_linker_section (dynobj, ".dynamic");
+
+ if (htab->root.dynamic_sections_created)
+ {
+ Elf64_External_Dyn *dyncon, *dynconend;
+
+ if (sdyn == NULL || htab->root.sgot == NULL)
+ abort ();
+
+ dyncon = (Elf64_External_Dyn *) sdyn->contents;
+ dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size);
+ for (; dyncon < dynconend; dyncon++)
+ {
+ Elf_Internal_Dyn dyn;
+ asection *s;
+
+ bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn);
+
+ switch (dyn.d_tag)
+ {
+ default:
+ continue;
+
+ case DT_PLTGOT:
+ s = htab->root.sgotplt;
+ dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
+ break;
+
+ case DT_JMPREL:
+ dyn.d_un.d_ptr = htab->root.srelplt->output_section->vma;
+ break;
+
+ case DT_PLTRELSZ:
+ s = htab->root.srelplt->output_section;
+ dyn.d_un.d_val = s->size;
+ break;
+
+ case DT_RELASZ:
+ /* The procedure linkage table relocs (DT_JMPREL) should
+ not be included in the overall relocs (DT_RELA).
+ Therefore, we override the DT_RELASZ entry here to
+ make it not include the JMPREL relocs. Since the
+ linker script arranges for .rela.plt to follow all
+ other relocation sections, we don't have to worry
+ about changing the DT_RELA entry. */
+ if (htab->root.srelplt != NULL)
+ {
+ s = htab->root.srelplt->output_section;
+ dyn.d_un.d_val -= s->size;
+ }
+ break;
+
+ case DT_TLSDESC_PLT:
+ s = htab->root.splt;
+ dyn.d_un.d_ptr = s->output_section->vma + s->output_offset
+ + htab->tlsdesc_plt;
+ break;
+
+ case DT_TLSDESC_GOT:
+ s = htab->root.sgot;
+ dyn.d_un.d_ptr = s->output_section->vma + s->output_offset
+ + htab->dt_tlsdesc_got;
+ break;
+ }
+
+ bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
+ }
+
+ }
+
+ /* Fill in the special first entry in the procedure linkage table. */
+ if (htab->root.splt && htab->root.splt->size > 0)
+ {
+ elf64_aarch64_init_small_plt0_entry (output_bfd, htab);
+
+ elf_section_data (htab->root.splt->output_section)->
+ this_hdr.sh_entsize = htab->plt_entry_size;
+
+
+ if (htab->tlsdesc_plt)
+ {
+ bfd_put_64 (output_bfd, (bfd_vma) 0,
+ htab->root.sgot->contents + htab->dt_tlsdesc_got);
+
+ memcpy (htab->root.splt->contents + htab->tlsdesc_plt,
+ elf64_aarch64_tlsdesc_small_plt_entry,
+ sizeof (elf64_aarch64_tlsdesc_small_plt_entry));
+
+ {
+ bfd_vma adrp1_addr =
+ htab->root.splt->output_section->vma
+ + htab->root.splt->output_offset + htab->tlsdesc_plt + 4;
+
+ bfd_vma adrp2_addr =
+ htab->root.splt->output_section->vma
+ + htab->root.splt->output_offset + htab->tlsdesc_plt + 8;
+
+ bfd_vma got_addr =
+ htab->root.sgot->output_section->vma
+ + htab->root.sgot->output_offset;
+
+ bfd_vma pltgot_addr =
+ htab->root.sgotplt->output_section->vma
+ + htab->root.sgotplt->output_offset;
+
+ bfd_vma dt_tlsdesc_got = got_addr + htab->dt_tlsdesc_got;
+ bfd_vma opcode;
+
+ /* adrp x2, DT_TLSDESC_GOT */
+ opcode = bfd_get_32 (output_bfd,
+ htab->root.splt->contents
+ + htab->tlsdesc_plt + 4);
+ opcode = reencode_adr_imm
+ (opcode, (PG (dt_tlsdesc_got) - PG (adrp1_addr)) >> 12);
+ bfd_put_32 (output_bfd, opcode,
+ htab->root.splt->contents + htab->tlsdesc_plt + 4);
+
+ /* adrp x3, 0 */
+ opcode = bfd_get_32 (output_bfd,
+ htab->root.splt->contents
+ + htab->tlsdesc_plt + 8);
+ opcode = reencode_adr_imm
+ (opcode, (PG (pltgot_addr) - PG (adrp2_addr)) >> 12);
+ bfd_put_32 (output_bfd, opcode,
+ htab->root.splt->contents + htab->tlsdesc_plt + 8);
+
+ /* ldr x2, [x2, #0] */
+ opcode = bfd_get_32 (output_bfd,
+ htab->root.splt->contents
+ + htab->tlsdesc_plt + 12);
+ opcode = reencode_ldst_pos_imm (opcode,
+ PG_OFFSET (dt_tlsdesc_got) >> 3);
+ bfd_put_32 (output_bfd, opcode,
+ htab->root.splt->contents + htab->tlsdesc_plt + 12);
+
+ /* add x3, x3, 0 */
+ opcode = bfd_get_32 (output_bfd,
+ htab->root.splt->contents
+ + htab->tlsdesc_plt + 16);
+ opcode = reencode_add_imm (opcode, PG_OFFSET (pltgot_addr));
+ bfd_put_32 (output_bfd, opcode,
+ htab->root.splt->contents + htab->tlsdesc_plt + 16);
+ }
+ }
+ }
+
+ if (htab->root.sgotplt)
+ {
+ if (bfd_is_abs_section (htab->root.sgotplt->output_section))
+ {
+ (*_bfd_error_handler)
+ (_("discarded output section: `%A'"), htab->root.sgotplt);
+ return FALSE;
+ }
+
+ /* Fill in the first three entries in the global offset table. */
+ if (htab->root.sgotplt->size > 0)
+ {
+ /* Set the first entry in the global offset table to the address of
+ the dynamic section. */
+ if (sdyn == NULL)
+ bfd_put_64 (output_bfd, (bfd_vma) 0,
+ htab->root.sgotplt->contents);
+ else
+ bfd_put_64 (output_bfd,
+ sdyn->output_section->vma + sdyn->output_offset,
+ htab->root.sgotplt->contents);
+ /* Write GOT[1] and GOT[2], needed for the dynamic linker. */
+ bfd_put_64 (output_bfd,
+ (bfd_vma) 0,
+ htab->root.sgotplt->contents + GOT_ENTRY_SIZE);
+ bfd_put_64 (output_bfd,
+ (bfd_vma) 0,
+ htab->root.sgotplt->contents + GOT_ENTRY_SIZE * 2);
+ }
+
+ elf_section_data (htab->root.sgotplt->output_section)->
+ this_hdr.sh_entsize = GOT_ENTRY_SIZE;
+ }
+
+ if (htab->root.sgot && htab->root.sgot->size > 0)
+ elf_section_data (htab->root.sgot->output_section)->this_hdr.sh_entsize
+ = GOT_ENTRY_SIZE;
+
+ return TRUE;
+}
+
+/* Return address for Ith PLT stub in section PLT, for relocation REL
+ or (bfd_vma) -1 if it should not be included. */
+
+static bfd_vma
+elf64_aarch64_plt_sym_val (bfd_vma i, const asection *plt,
+ const arelent *rel ATTRIBUTE_UNUSED)
+{
+ return plt->vma + PLT_ENTRY_SIZE + i * PLT_SMALL_ENTRY_SIZE;
+}
+
+
+/* We use this so we can override certain functions
+ (though currently we don't). */
+
+const struct elf_size_info elf64_aarch64_size_info =
+{
+ sizeof (Elf64_External_Ehdr),
+ sizeof (Elf64_External_Phdr),
+ sizeof (Elf64_External_Shdr),
+ sizeof (Elf64_External_Rel),
+ sizeof (Elf64_External_Rela),
+ sizeof (Elf64_External_Sym),
+ sizeof (Elf64_External_Dyn),
+ sizeof (Elf_External_Note),
+ 4, /* Hash table entry size. */
+ 1, /* Internal relocs per external relocs. */
+ 64, /* Arch size. */
+ 3, /* Log_file_align. */
+ ELFCLASS64, EV_CURRENT,
+ bfd_elf64_write_out_phdrs,
+ bfd_elf64_write_shdrs_and_ehdr,
+ bfd_elf64_checksum_contents,
+ bfd_elf64_write_relocs,
+ bfd_elf64_swap_symbol_in,
+ bfd_elf64_swap_symbol_out,
+ bfd_elf64_slurp_reloc_table,
+ bfd_elf64_slurp_symbol_table,
+ bfd_elf64_swap_dyn_in,
+ bfd_elf64_swap_dyn_out,
+ bfd_elf64_swap_reloc_in,
+ bfd_elf64_swap_reloc_out,
+ bfd_elf64_swap_reloca_in,
+ bfd_elf64_swap_reloca_out
+};
+
+#define ELF_ARCH bfd_arch_aarch64
+#define ELF_MACHINE_CODE EM_AARCH64
+#define ELF_MAXPAGESIZE 0x10000
+#define ELF_MINPAGESIZE 0x1000
+#define ELF_COMMONPAGESIZE 0x1000
+
+#define bfd_elf64_close_and_cleanup \
+ elf64_aarch64_close_and_cleanup
+
+#define bfd_elf64_bfd_copy_private_bfd_data \
+ elf64_aarch64_copy_private_bfd_data
+
+#define bfd_elf64_bfd_free_cached_info \
+ elf64_aarch64_bfd_free_cached_info
+
+#define bfd_elf64_bfd_is_target_special_symbol \
+ elf64_aarch64_is_target_special_symbol
+
+#define bfd_elf64_bfd_link_hash_table_create \
+ elf64_aarch64_link_hash_table_create
+
+#define bfd_elf64_bfd_link_hash_table_free \
+ elf64_aarch64_hash_table_free
+
+#define bfd_elf64_bfd_merge_private_bfd_data \
+ elf64_aarch64_merge_private_bfd_data
+
+#define bfd_elf64_bfd_print_private_bfd_data \
+ elf64_aarch64_print_private_bfd_data
+
+#define bfd_elf64_bfd_reloc_type_lookup \
+ elf64_aarch64_reloc_type_lookup
+
+#define bfd_elf64_bfd_reloc_name_lookup \
+ elf64_aarch64_reloc_name_lookup
+
+#define bfd_elf64_bfd_set_private_flags \
+ elf64_aarch64_set_private_flags
+
+#define bfd_elf64_find_inliner_info \
+ elf64_aarch64_find_inliner_info
+
+#define bfd_elf64_find_nearest_line \
+ elf64_aarch64_find_nearest_line
+
+#define bfd_elf64_mkobject \
+ elf64_aarch64_mkobject
+
+#define bfd_elf64_new_section_hook \
+ elf64_aarch64_new_section_hook
+
+#define elf_backend_adjust_dynamic_symbol \
+ elf64_aarch64_adjust_dynamic_symbol
+
+#define elf_backend_always_size_sections \
+ elf64_aarch64_always_size_sections
+
+#define elf_backend_check_relocs \
+ elf64_aarch64_check_relocs
+
+#define elf_backend_copy_indirect_symbol \
+ elf64_aarch64_copy_indirect_symbol
+
+/* Create .dynbss, and .rela.bss sections in DYNOBJ, and set up shortcuts
+ to them in our hash. */
+#define elf_backend_create_dynamic_sections \
+ elf64_aarch64_create_dynamic_sections
+
+#define elf_backend_init_index_section \
+ _bfd_elf_init_2_index_sections
+
+#define elf_backend_is_function_type \
+ elf64_aarch64_is_function_type
+
+#define elf_backend_finish_dynamic_sections \
+ elf64_aarch64_finish_dynamic_sections
+
+#define elf_backend_finish_dynamic_symbol \
+ elf64_aarch64_finish_dynamic_symbol
+
+#define elf_backend_gc_sweep_hook \
+ elf64_aarch64_gc_sweep_hook
+
+#define elf_backend_object_p \
+ elf64_aarch64_object_p
+
+#define elf_backend_output_arch_local_syms \
+ elf64_aarch64_output_arch_local_syms
+
+#define elf_backend_plt_sym_val \
+ elf64_aarch64_plt_sym_val
+
+#define elf_backend_post_process_headers \
+ elf64_aarch64_post_process_headers
+
+#define elf_backend_relocate_section \
+ elf64_aarch64_relocate_section
+
+#define elf_backend_reloc_type_class \
+ elf64_aarch64_reloc_type_class
+
+#define elf_backend_section_flags \
+ elf64_aarch64_section_flags
+
+#define elf_backend_section_from_shdr \
+ elf64_aarch64_section_from_shdr
+
+#define elf_backend_size_dynamic_sections \
+ elf64_aarch64_size_dynamic_sections
+
+#define elf_backend_size_info \
+ elf64_aarch64_size_info
+
+#define elf_backend_can_refcount 1
+#define elf_backend_can_gc_sections 0
+#define elf_backend_plt_readonly 1
+#define elf_backend_want_got_plt 1
+#define elf_backend_want_plt_sym 0
+#define elf_backend_may_use_rel_p 0
+#define elf_backend_may_use_rela_p 1
+#define elf_backend_default_use_rela_p 1
+#define elf_backend_got_header_size (GOT_ENTRY_SIZE * 3)
+
+#undef elf_backend_obj_attrs_section
+#define elf_backend_obj_attrs_section ".ARM.attributes"
+
+#include "elf64-target.h"
"BFD_RELOC_MICROBLAZE_64_GOTOFF",
"BFD_RELOC_MICROBLAZE_32_GOTOFF",
"BFD_RELOC_MICROBLAZE_COPY",
+ "BFD_RELOC_AARCH64_ADD_LO12",
+ "BFD_RELOC_AARCH64_ADR_GOT_PAGE",
+ "BFD_RELOC_AARCH64_ADR_HI21_PCREL",
+ "BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL",
+ "BFD_RELOC_AARCH64_ADR_LO21_PCREL",
+ "BFD_RELOC_AARCH64_BRANCH19",
+ "BFD_RELOC_AARCH64_CALL26",
+ "BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP",
+ "BFD_RELOC_AARCH64_JUMP26",
+ "BFD_RELOC_AARCH64_LD_LO19_PCREL",
+ "BFD_RELOC_AARCH64_LD64_GOT_LO12_NC",
+ "BFD_RELOC_AARCH64_LDST_LO12",
+ "BFD_RELOC_AARCH64_LDST8_LO12",
+ "BFD_RELOC_AARCH64_LDST16_LO12",
+ "BFD_RELOC_AARCH64_LDST32_LO12",
+ "BFD_RELOC_AARCH64_LDST64_LO12",
+ "BFD_RELOC_AARCH64_LDST128_LO12",
+ "BFD_RELOC_AARCH64_MOVW_G0",
+ "BFD_RELOC_AARCH64_MOVW_G0_S",
+ "BFD_RELOC_AARCH64_MOVW_G0_NC",
+ "BFD_RELOC_AARCH64_MOVW_G1",
+ "BFD_RELOC_AARCH64_MOVW_G1_NC",
+ "BFD_RELOC_AARCH64_MOVW_G1_S",
+ "BFD_RELOC_AARCH64_MOVW_G2",
+ "BFD_RELOC_AARCH64_MOVW_G2_NC",
+ "BFD_RELOC_AARCH64_MOVW_G2_S",
+ "BFD_RELOC_AARCH64_MOVW_G3",
+ "BFD_RELOC_AARCH64_TLSDESC",
+ "BFD_RELOC_AARCH64_TLSDESC_ADD",
+ "BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE",
+ "BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21",
+ "BFD_RELOC_AARCH64_TLSDESC_CALL",
+ "BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19",
+ "BFD_RELOC_AARCH64_TLSDESC_LDR",
+ "BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC",
+ "BFD_RELOC_AARCH64_TLSDESC_OFF_G1",
+ "BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21",
+ "BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21",
+ "BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19",
+ "BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC",
+ "BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1",
+ "BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12",
+ "BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12",
+ "BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0",
+ "BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC",
+ "BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1",
+ "BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC",
+ "BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2",
+ "BFD_RELOC_AARCH64_TLS_DTPMOD64",
+ "BFD_RELOC_AARCH64_TLS_DTPREL64",
+ "BFD_RELOC_AARCH64_TLS_TPREL64",
+ "BFD_RELOC_AARCH64_TSTBR14",
"BFD_RELOC_TILEPRO_COPY",
"BFD_RELOC_TILEPRO_GLOB_DAT",
"BFD_RELOC_TILEPRO_JMP_SLOT",
This is used to tell the dynamic linker to copy the value out of
the dynamic object into the runtime process image.
+ENUM
+ BFD_RELOC_AARCH64_ADD_LO12
+ENUMDOC
+ AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
+ Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_ADR_GOT_PAGE
+ENUMDOC
+ Get to the page base of the global offset table entry for a symbol as
+ part of an ADRP instruction using a 21 bit PC relative value.Used in
+ conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
+ENUM
+ BFD_RELOC_AARCH64_ADR_HI21_PCREL
+ENUMDOC
+ AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+ offset, giving a 4KB aligned page base address.
+ENUM
+ BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
+ENUMDOC
+ AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+ offset, giving a 4KB aligned page base address, but with no overflow
+ checking.
+ENUM
+ BFD_RELOC_AARCH64_ADR_LO21_PCREL
+ENUMDOC
+ AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
+ENUM
+ BFD_RELOC_AARCH64_BRANCH19
+ENUMDOC
+ AArch64 19 bit pc-relative conditional branch and compare & branch.
+ The lowest two bits must be zero and are not stored in the instruction,
+ giving a 21 bit signed byte offset.
+ENUM
+ BFD_RELOC_AARCH64_CALL26
+ENUMDOC
+ AArch64 26 bit pc-relative unconditional branch and link.
+ The lowest two bits must be zero and are not stored in the instruction,
+ giving a 28 bit signed byte offset.
+ENUM
+ BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
+ENUMDOC
+ AArch64 pseudo relocation code to be used internally by the AArch64
+ assembler and not (currently) written to any object files.
+ENUM
+ BFD_RELOC_AARCH64_JUMP26
+ENUMDOC
+ AArch64 26 bit pc-relative unconditional branch.
+ The lowest two bits must be zero and are not stored in the instruction,
+ giving a 28 bit signed byte offset.
+ENUM
+ BFD_RELOC_AARCH64_LD_LO19_PCREL
+ENUMDOC
+ AArch64 Load Literal instruction, holding a 19 bit pc-relative word
+ offset. The lowest two bits must be zero and are not stored in the
+ instruction, giving a 21 bit signed byte offset.
+ENUM
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
+ENUMDOC
+ Unsigned 12 bit byte offset for 64 bit load/store from the page of
+ the GOT entry for this symbol. Used in conjunction with
+ BFD_RELOC_AARCH64_ADR_GOTPAGE.
+ENUM
+ BFD_RELOC_AARCH64_LDST_LO12
+ENUMDOC
+ AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_LDST8_LO12
+ENUMDOC
+ AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_LDST16_LO12
+ENUMDOC
+ AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_LDST32_LO12
+ENUMDOC
+ AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_LDST64_LO12
+ENUMDOC
+ AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_LDST128_LO12
+ENUMDOC
+ AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
+ address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G0
+ENUMDOC
+ AArch64 MOV[NZK] instruction with most significant bits 0 to 15
+ of an unsigned address/value.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G0_S
+ENUMDOC
+ AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
+ value's sign.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G0_NC
+ENUMDOC
+ AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
+ an address/value. No overflow checking.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G1
+ENUMDOC
+ AArch64 MOV[NZK] instruction with most significant bits 16 to 31
+ of an unsigned address/value.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G1_NC
+ENUMDOC
+ AArch64 MOV[NZK] instruction with less significant bits 16 to 31
+ of an address/value. No overflow checking.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G1_S
+ENUMDOC
+ AArch64 MOV[NZ] instruction with most significant bits 16 to 31
+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
+ value's sign.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G2
+ENUMDOC
+ AArch64 MOV[NZK] instruction with most significant bits 32 to 47
+ of an unsigned address/value.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G2_NC
+ENUMDOC
+ AArch64 MOV[NZK] instruction with less significant bits 32 to 47
+ of an address/value. No overflow checking.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G2_S
+ENUMDOC
+ AArch64 MOV[NZ] instruction with most significant bits 32 to 47
+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
+ value's sign.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_G3
+ENUMDOC
+ AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
+ of a signed or unsigned address/value.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC
+ENUMDOC
+ AArch64 TLS relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_ADD
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_CALL
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_LDR
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G1
+ENUMDOC
+ AArch64 TLS DESC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
+ENUMDOC
+ Unsigned 12 bit byte offset to global offset table entry for a symbols
+ tls_index structure. Used in conjunction with
+ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
+ENUM
+ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
+ENUMDOC
+ Get to the page base of the global offset table entry for a symbols
+ tls_index structure as part of an adrp instruction using a 21 bit PC
+ relative value. Used in conjunction with
+ BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
+ENUM
+ BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
+ENUMDOC
+ AArch64 TLS INITIAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
+ENUMDOC
+ AArch64 TLS INITIAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
+ENUMDOC
+ AArch64 TLS INITIAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
+ENUMDOC
+ AArch64 TLS INITIAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
+ENUMDOC
+ AArch64 TLS INITIAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
+ENUMDOC
+ AArch64 TLS LOCAL EXEC relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLS_DTPMOD64
+ENUMDOC
+ AArch64 TLS relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLS_DTPREL64
+ENUMDOC
+ AArch64 TLS relocation.
+ENUM
+ BFD_RELOC_AARCH64_TLS_TPREL64
+ENUMDOC
+ AArch64 TLS relocation.
+ENUM
+ BFD_RELOC_AARCH64_TSTBR14
+ENUMDOC
+ AArch64 14 bit pc-relative test bit and branch.
+ The lowest two bits must be zero and are not stored in the instruction,
+ giving a 16 bit signed byte offset.
+
ENUM
BFD_RELOC_TILEPRO_COPY
ENUMX
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
ENUMDOC
Tilera TILEPro Relocations.
-
ENUM
BFD_RELOC_TILEGX_HW0
ENUMX
BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
ENUMDOC
Tilera TILE-Gx Relocations.
-
ENUM
BFD_RELOC_EPIPHANY_SIMM8
ENUMDOC
extern const bfd_target bfd_elf64_alpha_vec;
extern const bfd_target bfd_elf64_big_generic_vec;
extern const bfd_target bfd_elf64_bigmips_vec;
+extern const bfd_target bfd_elf64_bigaarch64_vec;
extern const bfd_target bfd_elf64_hppa_linux_vec;
extern const bfd_target bfd_elf64_hppa_vec;
extern const bfd_target bfd_elf64_ia64_big_vec;
extern const bfd_target bfd_elf64_ia64_vms_vec;
extern const bfd_target bfd_elf64_little_generic_vec;
extern const bfd_target bfd_elf64_littlemips_vec;
+extern const bfd_target bfd_elf64_littleaarch64_vec;
extern const bfd_target bfd_elf64_mmix_vec;
extern const bfd_target bfd_elf64_powerpc_vec;
extern const bfd_target bfd_elf64_powerpcle_vec;
&bfd_elf64_alpha_vec,
&bfd_elf64_big_generic_vec,
&bfd_elf64_bigmips_vec,
+ &bfd_elf64_bigaarch64_vec,
&bfd_elf64_hppa_linux_vec,
&bfd_elf64_hppa_vec,
&bfd_elf64_ia64_big_vec,
&bfd_elf64_ia64_vms_vec,
&bfd_elf64_little_generic_vec,
&bfd_elf64_littlemips_vec,
+ &bfd_elf64_littleaarch64_vec,
&bfd_elf64_mmix_vec,
&bfd_elf64_powerpc_vec,
&bfd_elf64_powerpcle_vec,
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * readelf.c (guess_is_rela): Handle EM_AARCH64.
+ (get_machine_name): Likewise.
+ (get_aarch64_segment_type): New function.
+ (get_segment_type): Handle EM_AARCH64 by calling the new function.
+ (get_aarch64_section_type_name): New function.
+ (get_section_type_name): Handle EM_AARCH64 by calling the new function.
+ (is_32bit_abs_reloc): Handle EM_AARCH64.
+ (is_32bit_pcrel_reloc): Likewise.
+ (is_64bit_abs_reloc): Likewise.
+ (is_64bit_pcrel_reloc): Likewise.
+ (is_none_reloc): Likewise.
+
2012-08-09 Nick Clifton <nickc@redhat.com>
* po/vi.po: Updated Vietnamese translation.
responsibility among the other maintainers.
ALPHA Richard Henderson <rth@redhat.com>
+ AARCH64 Richard Earnshaw <rearnsha@arm.com>
ARM Nick Clifton <nickc@redhat.com>
ARM Richard Earnshaw <rearnsha@arm.com>
ARM Paul Brook <paul@codesourcery.com>
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
$(top_srcdir)/../config/zlib.m4 \
- $(top_srcdir)/../bfd/warning.m4 \
+ $(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/gettext-sister.m4 \
$(top_srcdir)/../config/iconv.m4 \
#define RELOC_MACROS_GEN_FUNC
+#include "elf/aarch64.h"
#include "elf/alpha.h"
#include "elf/arc.h"
#include "elf/arm.h"
/* Targets that use RELA relocations. */
case EM_68K:
case EM_860:
+ case EM_AARCH64:
case EM_ADAPTEVA_EPIPHANY:
case EM_ALPHA:
case EM_ALTERA_NIOS2:
rtype = NULL;
break;
+ case EM_AARCH64:
+ rtype = elf_aarch64_reloc_type (type);
+ break;
+
case EM_M32R:
case EM_CYGNUS_M32R:
rtype = elf_m32r_reloc_type (type);
switch (e_machine)
{
case EM_NONE: return _("None");
+ case EM_AARCH64: return "AArch64";
case EM_M32: return "WE32100";
case EM_SPARC: return "Sparc";
case EM_SPU: return "SPU";
}
}
+static const char *
+get_aarch64_segment_type (unsigned long type)
+{
+ switch (type)
+ {
+ case PT_AARCH64_ARCHEXT:
+ return "AARCH64_ARCHEXT";
+ default:
+ break;
+ }
+
+ return NULL;
+}
+
static const char *
get_arm_segment_type (unsigned long type)
{
switch (elf_header.e_machine)
{
+ case EM_AARCH64:
+ result = get_aarch64_segment_type (p_type);
+ break;
case EM_ARM:
result = get_arm_segment_type (p_type);
break;
return NULL;
}
+static const char *
+get_aarch64_section_type_name (unsigned int sh_type)
+{
+ switch (sh_type)
+ {
+ case SHT_AARCH64_ATTRIBUTES:
+ return "AARCH64_ATTRIBUTES";
+ default:
+ break;
+ }
+ return NULL;
+}
+
static const char *
get_arm_section_type_name (unsigned int sh_type)
{
case EM_K1OM:
result = get_x86_64_section_type_name (sh_type);
break;
+ case EM_AARCH64:
+ result = get_aarch64_section_type_name (sh_type);
+ break;
case EM_ARM:
result = get_arm_section_type_name (sh_type);
break;
return reloc_type == 1; /* R_860_32. */
case EM_960:
return reloc_type == 2; /* R_960_32. */
+ case EM_AARCH64:
+ return reloc_type == 258; /* R_AARCH64_ABS32 */
case EM_ALPHA:
return reloc_type == 1; /* R_ALPHA_REFLONG. */
case EM_ARC:
return reloc_type == 2; /* R_386_PC32. */
case EM_68K:
return reloc_type == 4; /* R_68K_PC32. */
+ case EM_AARCH64:
+ return reloc_type == 261; /* R_AARCH64_PREL32 */
case EM_ADAPTEVA_EPIPHANY:
return reloc_type == 6;
case EM_ALPHA:
{
switch (elf_header.e_machine)
{
+ case EM_AARCH64:
+ return reloc_type == 257; /* R_AARCH64_ABS64. */
case EM_ALPHA:
return reloc_type == 2; /* R_ALPHA_REFQUAD. */
case EM_IA_64:
{
switch (elf_header.e_machine)
{
+ case EM_AARCH64:
+ return reloc_type == 260; /* R_AARCH64_PREL64. */
case EM_ALPHA:
return reloc_type == 11; /* R_ALPHA_SREL64. */
case EM_IA_64:
case EM_XC16X:
case EM_C166: /* R_XC16X_NONE. */
return reloc_type == 0;
+ case EM_AARCH64:
+ return reloc_type == 0 || reloc_type == 256;
case EM_XTENSA_OLD:
case EM_XTENSA:
return (reloc_type == 0 /* R_XTENSA_NONE. */
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * objdump.exp: Add AArch64.
+
2012-08-02 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/14420
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
-lappend cpus_expected alpha arc arm cris
+lappend cpus_expected aarch64 alpha arc arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp ns32k pj powerpc pyramid
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64.
+ * Makefile.in: Regenerate.
+ * config/tc-aarch64.c: New file.
+ * config/tc-aarch64.h: New file.
+ * configure.tgt: Add AArch64.
+ * doc/Makefile.am: Add AArch64.
+ * doc/Makefile.in: Regenerate.
+ * doc/all.texi: Add AArch64.
+ * doc/as.texinfo: Add AArch64.
+ * doc/c-aarch64.texi: New file.
+ * po/POTFILES.in: Regenerate.
+ * NEWS: Mention the new support.
+
2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.
# CPU files in config.
TARGET_CPU_CFILES = \
+ config/tc-aarch64.c \
config/tc-alpha.c \
config/tc-arc.c \
config/tc-arm.c \
config/xtensa-relax.c
TARGET_CPU_HFILES = \
+ config/tc-aarch64.h \
config/tc-alpha.h \
config/tc-arc.h \
config/tc-arm.h \
# CPU files in config.
TARGET_CPU_CFILES = \
+ config/tc-aarch64.c \
config/tc-alpha.c \
config/tc-arc.c \
config/tc-arm.c \
config/xtensa-relax.c
TARGET_CPU_HFILES = \
+ config/tc-aarch64.h \
config/tc-alpha.h \
config/tc-arc.h \
config/tc-arm.h \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stabs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/subsegs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/symbols.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-aarch64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-alpha.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arm.Po@am__quote@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(LTCOMPILE) -c -o $@ $<
+tc-aarch64.o: config/tc-aarch64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-aarch64.o -MD -MP -MF $(DEPDIR)/tc-aarch64.Tpo -c -o tc-aarch64.o `test -f 'config/tc-aarch64.c' || echo '$(srcdir)/'`config/tc-aarch64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-aarch64.Tpo $(DEPDIR)/tc-aarch64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-aarch64.c' object='tc-aarch64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-aarch64.o `test -f 'config/tc-aarch64.c' || echo '$(srcdir)/'`config/tc-aarch64.c
+
+tc-aarch64.obj: config/tc-aarch64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-aarch64.obj -MD -MP -MF $(DEPDIR)/tc-aarch64.Tpo -c -o tc-aarch64.obj `if test -f 'config/tc-aarch64.c'; then $(CYGPATH_W) 'config/tc-aarch64.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-aarch64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-aarch64.Tpo $(DEPDIR)/tc-aarch64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-aarch64.c' object='tc-aarch64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-aarch64.obj `if test -f 'config/tc-aarch64.c'; then $(CYGPATH_W) 'config/tc-aarch64.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-aarch64.c'; fi`
+
tc-alpha.o: config/tc-alpha.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-alpha.o -MD -MP -MF $(DEPDIR)/tc-alpha.Tpo -c -o tc-alpha.o `test -f 'config/tc-alpha.c' || echo '$(srcdir)/'`config/tc-alpha.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-alpha.Tpo $(DEPDIR)/tc-alpha.Po
-*- text -*-
+* Add support for the 64-bit ARM architecture: AArch64.
+
Changes in 2.23:
* Add support for S12X processor.
--- /dev/null
+/* tc-aarch64.c -- Assemble for the AArch64 ISA
+
+ Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "as.h"
+#include <limits.h>
+#include <stdarg.h>
+#include "bfd_stdint.h"
+#define NO_RELOC 0
+#include "safe-ctype.h"
+#include "subsegs.h"
+#include "obstack.h"
+
+#ifdef OBJ_ELF
+#include "elf/aarch64.h"
+#include "dw2gencfi.h"
+#endif
+
+#include "dwarf2dbg.h"
+
+/* Types of processor to assemble for. */
+#ifndef CPU_DEFAULT
+#define CPU_DEFAULT AARCH64_ARCH_V8
+#endif
+
+#define streq(a, b) (strcmp (a, b) == 0)
+
+static aarch64_feature_set cpu_variant;
+
+/* Variables that we set while parsing command-line options. Once all
+ options have been read we re-process these values to set the real
+ assembly flags. */
+static const aarch64_feature_set *mcpu_cpu_opt = NULL;
+static const aarch64_feature_set *march_cpu_opt = NULL;
+
+/* Constants for known architecture features. */
+static const aarch64_feature_set cpu_default = CPU_DEFAULT;
+
+static const aarch64_feature_set aarch64_arch_any = AARCH64_ANY;
+static const aarch64_feature_set aarch64_arch_none = AARCH64_ARCH_NONE;
+
+#ifdef OBJ_ELF
+/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
+static symbolS *GOT_symbol;
+#endif
+
+enum neon_el_type
+{
+ NT_invtype = -1,
+ NT_b,
+ NT_h,
+ NT_s,
+ NT_d,
+ NT_q
+};
+
+/* Bits for DEFINED field in neon_type_el. */
+#define NTA_HASTYPE 1
+#define NTA_HASINDEX 2
+
+struct neon_type_el
+{
+ enum neon_el_type type;
+ unsigned char defined;
+ unsigned width;
+ int64_t index;
+};
+
+#define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
+
+struct reloc
+{
+ bfd_reloc_code_real_type type;
+ expressionS exp;
+ int pc_rel;
+ enum aarch64_opnd opnd;
+ uint32_t flags;
+ unsigned need_libopcodes_p : 1;
+};
+
+struct aarch64_instruction
+{
+ /* libopcodes structure for instruction intermediate representation. */
+ aarch64_inst base;
+ /* Record assembly errors found during the parsing. */
+ struct
+ {
+ enum aarch64_operand_error_kind kind;
+ const char *error;
+ } parsing_error;
+ /* The condition that appears in the assembly line. */
+ int cond;
+ /* Relocation information (including the GAS internal fixup). */
+ struct reloc reloc;
+ /* Need to generate an immediate in the literal pool. */
+ unsigned gen_lit_pool : 1;
+};
+
+typedef struct aarch64_instruction aarch64_instruction;
+
+static aarch64_instruction inst;
+
+static bfd_boolean parse_operands (char *, const aarch64_opcode *);
+static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
+
+/* Diagnostics inline function utilites.
+
+ These are lightweight utlities which should only be called by parse_operands
+ and other parsers. GAS processes each assembly line by parsing it against
+ instruction template(s), in the case of multiple templates (for the same
+ mnemonic name), those templates are tried one by one until one succeeds or
+ all fail. An assembly line may fail a few templates before being
+ successfully parsed; an error saved here in most cases is not a user error
+ but an error indicating the current template is not the right template.
+ Therefore it is very important that errors can be saved at a low cost during
+ the parsing; we don't want to slow down the whole parsing by recording
+ non-user errors in detail.
+
+ Remember that the objective is to help GAS pick up the most approapriate
+ error message in the case of multiple templates, e.g. FMOV which has 8
+ templates. */
+
+static inline void
+clear_error (void)
+{
+ inst.parsing_error.kind = AARCH64_OPDE_NIL;
+ inst.parsing_error.error = NULL;
+}
+
+static inline bfd_boolean
+error_p (void)
+{
+ return inst.parsing_error.kind != AARCH64_OPDE_NIL;
+}
+
+static inline const char *
+get_error_message (void)
+{
+ return inst.parsing_error.error;
+}
+
+static inline void
+set_error_message (const char *error)
+{
+ inst.parsing_error.error = error;
+}
+
+static inline enum aarch64_operand_error_kind
+get_error_kind (void)
+{
+ return inst.parsing_error.kind;
+}
+
+static inline void
+set_error_kind (enum aarch64_operand_error_kind kind)
+{
+ inst.parsing_error.kind = kind;
+}
+
+static inline void
+set_error (enum aarch64_operand_error_kind kind, const char *error)
+{
+ inst.parsing_error.kind = kind;
+ inst.parsing_error.error = error;
+}
+
+static inline void
+set_recoverable_error (const char *error)
+{
+ set_error (AARCH64_OPDE_RECOVERABLE, error);
+}
+
+/* Use the DESC field of the corresponding aarch64_operand entry to compose
+ the error message. */
+static inline void
+set_default_error (void)
+{
+ set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
+}
+
+static inline void
+set_syntax_error (const char *error)
+{
+ set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
+}
+
+static inline void
+set_first_syntax_error (const char *error)
+{
+ if (! error_p ())
+ set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
+}
+
+static inline void
+set_fatal_syntax_error (const char *error)
+{
+ set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
+}
+\f
+/* Number of littlenums required to hold an extended precision number. */
+#define MAX_LITTLENUMS 6
+
+/* Return value for certain parsers when the parsing fails; those parsers
+ return the information of the parsed result, e.g. register number, on
+ success. */
+#define PARSE_FAIL -1
+
+/* This is an invalid condition code that means no conditional field is
+ present. */
+#define COND_ALWAYS 0x10
+
+typedef struct
+{
+ const char *template;
+ unsigned long value;
+} asm_barrier_opt;
+
+typedef struct
+{
+ const char *template;
+ uint32_t value;
+} asm_nzcv;
+
+struct reloc_entry
+{
+ char *name;
+ bfd_reloc_code_real_type reloc;
+};
+
+/* Structure for a hash table entry for a register. */
+typedef struct
+{
+ const char *name;
+ unsigned char number;
+ unsigned char type;
+ unsigned char builtin;
+} reg_entry;
+
+/* Macros to define the register types and masks for the purpose
+ of parsing. */
+
+#undef AARCH64_REG_TYPES
+#define AARCH64_REG_TYPES \
+ BASIC_REG_TYPE(R_32) /* w[0-30] */ \
+ BASIC_REG_TYPE(R_64) /* x[0-30] */ \
+ BASIC_REG_TYPE(SP_32) /* wsp */ \
+ BASIC_REG_TYPE(SP_64) /* sp */ \
+ BASIC_REG_TYPE(Z_32) /* wzr */ \
+ BASIC_REG_TYPE(Z_64) /* xzr */ \
+ BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
+ BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
+ BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
+ BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
+ BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
+ BASIC_REG_TYPE(CN) /* c[0-7] */ \
+ BASIC_REG_TYPE(VN) /* v[0-31] */ \
+ /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
+ MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
+ /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
+ MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
+ | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
+ | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
+ /* Typecheck: any [BHSDQ]P FP. */ \
+ MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
+ | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
+ /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
+ MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
+ | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
+ | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
+ | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
+ /* Any integer register; used for error messages only. */ \
+ MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
+ | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
+ | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
+ /* Pseudo type to mark the end of the enumerator sequence. */ \
+ BASIC_REG_TYPE(MAX)
+
+#undef BASIC_REG_TYPE
+#define BASIC_REG_TYPE(T) REG_TYPE_##T,
+#undef MULTI_REG_TYPE
+#define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
+
+/* Register type enumerators. */
+typedef enum
+{
+ /* A list of REG_TYPE_*. */
+ AARCH64_REG_TYPES
+} aarch64_reg_type;
+
+#undef BASIC_REG_TYPE
+#define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
+#undef REG_TYPE
+#define REG_TYPE(T) (1 << REG_TYPE_##T)
+#undef MULTI_REG_TYPE
+#define MULTI_REG_TYPE(T,V) V,
+
+/* Values indexed by aarch64_reg_type to assist the type checking. */
+static const unsigned reg_type_masks[] =
+{
+ AARCH64_REG_TYPES
+};
+
+#undef BASIC_REG_TYPE
+#undef REG_TYPE
+#undef MULTI_REG_TYPE
+#undef AARCH64_REG_TYPES
+
+/* Diagnostics used when we don't get a register of the expected type.
+ Note: this has to synchronized with aarch64_reg_type definitions
+ above. */
+static const char *
+get_reg_expected_msg (aarch64_reg_type reg_type)
+{
+ const char *msg;
+
+ switch (reg_type)
+ {
+ case REG_TYPE_R_32:
+ msg = N_("integer 32-bit register expected");
+ break;
+ case REG_TYPE_R_64:
+ msg = N_("integer 64-bit register expected");
+ break;
+ case REG_TYPE_R_N:
+ msg = N_("integer register expected");
+ break;
+ case REG_TYPE_R_Z_SP:
+ msg = N_("integer, zero or SP register expected");
+ break;
+ case REG_TYPE_FP_B:
+ msg = N_("8-bit SIMD scalar register expected");
+ break;
+ case REG_TYPE_FP_H:
+ msg = N_("16-bit SIMD scalar or floating-point half precision "
+ "register expected");
+ break;
+ case REG_TYPE_FP_S:
+ msg = N_("32-bit SIMD scalar or floating-point single precision "
+ "register expected");
+ break;
+ case REG_TYPE_FP_D:
+ msg = N_("64-bit SIMD scalar or floating-point double precision "
+ "register expected");
+ break;
+ case REG_TYPE_FP_Q:
+ msg = N_("128-bit SIMD scalar or floating-point quad precision "
+ "register expected");
+ break;
+ case REG_TYPE_CN:
+ msg = N_("C0 - C15 expected");
+ break;
+ case REG_TYPE_R_Z_BHSDQ_V:
+ msg = N_("register expected");
+ break;
+ case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
+ msg = N_("SIMD scalar or floating-point register expected");
+ break;
+ case REG_TYPE_VN: /* any V reg */
+ msg = N_("vector register expected");
+ break;
+ default:
+ as_fatal (_("invalid register type %d"), reg_type);
+ }
+ return msg;
+}
+
+/* Some well known registers that we refer to directly elsewhere. */
+#define REG_SP 31
+
+/* Instructions take 4 bytes in the object file. */
+#define INSN_SIZE 4
+
+/* Define some common error messages. */
+#define BAD_SP _("SP not allowed here")
+
+static struct hash_control *aarch64_ops_hsh;
+static struct hash_control *aarch64_cond_hsh;
+static struct hash_control *aarch64_shift_hsh;
+static struct hash_control *aarch64_sys_regs_hsh;
+static struct hash_control *aarch64_pstatefield_hsh;
+static struct hash_control *aarch64_sys_regs_ic_hsh;
+static struct hash_control *aarch64_sys_regs_dc_hsh;
+static struct hash_control *aarch64_sys_regs_at_hsh;
+static struct hash_control *aarch64_sys_regs_tlbi_hsh;
+static struct hash_control *aarch64_reg_hsh;
+static struct hash_control *aarch64_barrier_opt_hsh;
+static struct hash_control *aarch64_nzcv_hsh;
+static struct hash_control *aarch64_pldop_hsh;
+
+/* Stuff needed to resolve the label ambiguity
+ As:
+ ...
+ label: <insn>
+ may differ from:
+ ...
+ label:
+ <insn> */
+
+static symbolS *last_label_seen;
+
+/* Literal pool structure. Held on a per-section
+ and per-sub-section basis. */
+
+#define MAX_LITERAL_POOL_SIZE 1024
+typedef struct literal_pool
+{
+ expressionS literals[MAX_LITERAL_POOL_SIZE];
+ unsigned int next_free_entry;
+ unsigned int id;
+ symbolS *symbol;
+ segT section;
+ subsegT sub_section;
+ int size;
+ struct literal_pool *next;
+} literal_pool;
+
+/* Pointer to a linked list of literal pools. */
+static literal_pool *list_of_pools = NULL;
+\f
+/* Pure syntax. */
+
+/* This array holds the chars that always start a comment. If the
+ pre-processor is disabled, these aren't very useful. */
+const char comment_chars[] = "";
+
+/* This array holds the chars that only start a comment at the beginning of
+ a line. If the line seems to have the form '# 123 filename'
+ .line and .file directives will appear in the pre-processed output. */
+/* Note that input_file.c hand checks for '#' at the beginning of the
+ first line of the input file. This is because the compiler outputs
+ #NO_APP at the beginning of its output. */
+/* Also note that comments like this one will always work. */
+const char line_comment_chars[] = "#";
+
+const char line_separator_chars[] = ";";
+
+/* Chars that can be used to separate mant
+ from exp in floating point numbers. */
+const char EXP_CHARS[] = "eE";
+
+/* Chars that mean this number is a floating point constant. */
+/* As in 0f12.456 */
+/* or 0d1.2345e12 */
+
+const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
+
+/* Prefix character that indicates the start of an immediate value. */
+#define is_immediate_prefix(C) ((C) == '#')
+
+/* Separator character handling. */
+
+#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
+
+static inline bfd_boolean
+skip_past_char (char **str, char c)
+{
+ if (**str == c)
+ {
+ (*str)++;
+ return TRUE;
+ }
+ else
+ return FALSE;
+}
+
+#define skip_past_comma(str) skip_past_char (str, ',')
+
+/* Arithmetic expressions (possibly involving symbols). */
+
+/* Return TRUE if anything in the expression *SP is a bignum. */
+
+static bfd_boolean
+exp_has_bignum_p (symbolS * sp)
+{
+ if (symbol_get_value_expression (sp)->X_op == O_big)
+ return TRUE;
+
+ if (symbol_get_value_expression (sp)->X_add_symbol)
+ {
+ return (exp_has_bignum_p (symbol_get_value_expression (sp)->X_add_symbol)
+ || (symbol_get_value_expression (sp)->X_op_symbol
+ && exp_has_bignum_p (symbol_get_value_expression (sp)->
+ X_op_symbol)));
+ }
+
+ return FALSE;
+}
+
+static bfd_boolean in_my_get_expression_p = FALSE;
+
+/* Third argument to my_get_expression. */
+#define GE_NO_PREFIX 0
+#define GE_OPT_PREFIX 1
+
+/* Return TRUE if the string pointed by *STR is successfully parsed
+ as an valid expression; *EP will be filled with the information of
+ such an expression. Otherwise return FALSE. */
+
+static bfd_boolean
+my_get_expression (expressionS * ep, char **str, int prefix_mode,
+ int reject_absent)
+{
+ char *save_in;
+ segT seg;
+ int prefix_present_p = 0;
+
+ switch (prefix_mode)
+ {
+ case GE_NO_PREFIX:
+ break;
+ case GE_OPT_PREFIX:
+ if (is_immediate_prefix (**str))
+ {
+ (*str)++;
+ prefix_present_p = 1;
+ }
+ break;
+ default:
+ abort ();
+ }
+
+ memset (ep, 0, sizeof (expressionS));
+
+ save_in = input_line_pointer;
+ input_line_pointer = *str;
+ in_my_get_expression_p = TRUE;
+ seg = expression (ep);
+ in_my_get_expression_p = FALSE;
+
+ if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
+ {
+ /* We found a bad expression in md_operand(). */
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ if (prefix_present_p && ! error_p ())
+ set_fatal_syntax_error (_("bad expression"));
+ else
+ set_first_syntax_error (_("bad expression"));
+ return FALSE;
+ }
+
+#ifdef OBJ_AOUT
+ if (seg != absolute_section
+ && seg != text_section
+ && seg != data_section
+ && seg != bss_section && seg != undefined_section)
+ {
+ set_syntax_error (_("bad segment"));
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return FALSE;
+ }
+#else
+ (void) seg;
+#endif
+
+ /* Get rid of any bignums now, so that we don't generate an error for which
+ we can't establish a line number later on. Big numbers are never valid
+ in instructions, which is where this routine is always called. */
+ if (ep->X_op == O_big
+ || (ep->X_add_symbol
+ && (exp_has_bignum_p (ep->X_add_symbol)
+ || (ep->X_op_symbol && exp_has_bignum_p (ep->X_op_symbol)))))
+ {
+ if (prefix_present_p && error_p ())
+ set_fatal_syntax_error (_("invalid constant"));
+ else
+ set_first_syntax_error (_("invalid constant"));
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return FALSE;
+ }
+
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return TRUE;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
+ returned, or NULL on OK. */
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+ return ieee_md_atof (type, litP, sizeP, target_big_endian);
+}
+
+/* We handle all bad expressions here, so that we can report the faulty
+ instruction in the error message. */
+void
+md_operand (expressionS * exp)
+{
+ if (in_my_get_expression_p)
+ exp->X_op = O_illegal;
+}
+
+/* Immediate values. */
+
+/* Errors may be set multiple times during parsing or bit encoding
+ (particularly in the Neon bits), but usually the earliest error which is set
+ will be the most meaningful. Avoid overwriting it with later (cascading)
+ errors by calling this function. */
+
+static void
+first_error (const char *error)
+{
+ if (! error_p ())
+ set_syntax_error (error);
+}
+
+/* Similiar to first_error, but this function accepts formatted error
+ message. */
+static void
+first_error_fmt (const char *format, ...)
+{
+ va_list args;
+ enum
+ { size = 100 };
+ /* N.B. this single buffer will not cause error messages for different
+ instructions to pollute each other; this is because at the end of
+ processing of each assembly line, error message if any will be
+ collected by as_bad. */
+ static char buffer[size];
+
+ if (! error_p ())
+ {
+ int ret;
+ va_start (args, format);
+ ret = vsnprintf (buffer, size, format, args);
+ know (ret <= size - 1 && ret >= 0);
+ va_end (args);
+ set_syntax_error (buffer);
+ }
+}
+
+/* Register parsing. */
+
+/* Generic register parser which is called by other specialized
+ register parsers.
+ CCP points to what should be the beginning of a register name.
+ If it is indeed a valid register name, advance CCP over it and
+ return the reg_entry structure; otherwise return NULL.
+ It does not issue diagnostics. */
+
+static reg_entry *
+parse_reg (char **ccp)
+{
+ char *start = *ccp;
+ char *p;
+ reg_entry *reg;
+
+#ifdef REGISTER_PREFIX
+ if (*start != REGISTER_PREFIX)
+ return NULL;
+ start++;
+#endif
+
+ p = start;
+ if (!ISALPHA (*p) || !is_name_beginner (*p))
+ return NULL;
+
+ do
+ p++;
+ while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
+
+ reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start);
+
+ if (!reg)
+ return NULL;
+
+ *ccp = p;
+ return reg;
+}
+
+/* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
+ return FALSE. */
+static bfd_boolean
+aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
+{
+ if (reg->type == type)
+ return TRUE;
+
+ switch (type)
+ {
+ case REG_TYPE_R64_SP: /* 64-bit integer reg (inc SP exc XZR). */
+ case REG_TYPE_R_Z_SP: /* Integer reg (inc {X}SP inc [WX]ZR). */
+ case REG_TYPE_R_Z_BHSDQ_V: /* Any register apart from Cn. */
+ case REG_TYPE_BHSDQ: /* Any [BHSDQ]P FP or SIMD scalar register. */
+ case REG_TYPE_VN: /* Vector register. */
+ gas_assert (reg->type < REG_TYPE_MAX && type < REG_TYPE_MAX);
+ return ((reg_type_masks[reg->type] & reg_type_masks[type])
+ == reg_type_masks[reg->type]);
+ default:
+ as_fatal ("unhandled type %d", type);
+ abort ();
+ }
+}
+
+/* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
+ Return the register number otherwise. *ISREG32 is set to one if the
+ register is 32-bit wide; *ISREGZERO is set to one if the register is
+ of type Z_32 or Z_64.
+ Note that this function does not issue any diagnostics. */
+
+static int
+aarch64_reg_parse_32_64 (char **ccp, int reject_sp, int reject_rz,
+ int *isreg32, int *isregzero)
+{
+ char *str = *ccp;
+ const reg_entry *reg = parse_reg (&str);
+
+ if (reg == NULL)
+ return PARSE_FAIL;
+
+ if (! aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP))
+ return PARSE_FAIL;
+
+ switch (reg->type)
+ {
+ case REG_TYPE_SP_32:
+ case REG_TYPE_SP_64:
+ if (reject_sp)
+ return PARSE_FAIL;
+ *isreg32 = reg->type == REG_TYPE_SP_32;
+ *isregzero = 0;
+ break;
+ case REG_TYPE_R_32:
+ case REG_TYPE_R_64:
+ *isreg32 = reg->type == REG_TYPE_R_32;
+ *isregzero = 0;
+ break;
+ case REG_TYPE_Z_32:
+ case REG_TYPE_Z_64:
+ if (reject_rz)
+ return PARSE_FAIL;
+ *isreg32 = reg->type == REG_TYPE_Z_32;
+ *isregzero = 1;
+ break;
+ default:
+ return PARSE_FAIL;
+ }
+
+ *ccp = str;
+
+ return reg->number;
+}
+
+/* Parse the qualifier of a SIMD vector register or a SIMD vector element.
+ Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
+ otherwise return FALSE.
+
+ Accept only one occurrence of:
+ 8b 16b 4h 8h 2s 4s 1d 2d
+ b h s d q */
+static bfd_boolean
+parse_neon_type_for_operand (struct neon_type_el *parsed_type, char **str)
+{
+ char *ptr = *str;
+ unsigned width;
+ unsigned element_size;
+ enum neon_el_type type;
+
+ /* skip '.' */
+ ptr++;
+
+ if (!ISDIGIT (*ptr))
+ {
+ width = 0;
+ goto elt_size;
+ }
+ width = strtoul (ptr, &ptr, 10);
+ if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
+ {
+ first_error_fmt (_("bad size %d in vector width specifier"), width);
+ return FALSE;
+ }
+
+elt_size:
+ switch (TOLOWER (*ptr))
+ {
+ case 'b':
+ type = NT_b;
+ element_size = 8;
+ break;
+ case 'h':
+ type = NT_h;
+ element_size = 16;
+ break;
+ case 's':
+ type = NT_s;
+ element_size = 32;
+ break;
+ case 'd':
+ type = NT_d;
+ element_size = 64;
+ break;
+ case 'q':
+ if (width == 1)
+ {
+ type = NT_q;
+ element_size = 128;
+ break;
+ }
+ /* fall through. */
+ default:
+ if (*ptr != '\0')
+ first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
+ else
+ first_error (_("missing element size"));
+ return FALSE;
+ }
+ if (width != 0 && width * element_size != 64 && width * element_size != 128)
+ {
+ first_error_fmt (_
+ ("invalid element size %d and vector size combination %c"),
+ width, *ptr);
+ return FALSE;
+ }
+ ptr++;
+
+ parsed_type->type = type;
+ parsed_type->width = width;
+
+ *str = ptr;
+
+ return TRUE;
+}
+
+/* Parse a single type, e.g. ".8b", leading period included.
+ Only applicable to Vn registers.
+
+ Return TRUE on success; otherwise return FALSE. */
+static bfd_boolean
+parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
+{
+ char *str = *ccp;
+
+ if (*str == '.')
+ {
+ if (! parse_neon_type_for_operand (vectype, &str))
+ {
+ first_error (_("vector type expected"));
+ return FALSE;
+ }
+ }
+ else
+ return FALSE;
+
+ *ccp = str;
+
+ return TRUE;
+}
+
+/* Parse a register of the type TYPE.
+
+ Return PARSE_FAIL if the string pointed by *CCP is not a valid register
+ name or the parsed register is not of TYPE.
+
+ Otherwise return the register number, and optionally fill in the actual
+ type of the register in *RTYPE when multiple alternatives were given, and
+ return the register shape and element index information in *TYPEINFO.
+
+ IN_REG_LIST should be set with TRUE if the caller is parsing a register
+ list. */
+
+static int
+parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
+ struct neon_type_el *typeinfo, bfd_boolean in_reg_list)
+{
+ char *str = *ccp;
+ const reg_entry *reg = parse_reg (&str);
+ struct neon_type_el atype;
+ struct neon_type_el parsetype;
+ bfd_boolean is_typed_vecreg = FALSE;
+
+ atype.defined = 0;
+ atype.type = NT_invtype;
+ atype.width = -1;
+ atype.index = 0;
+
+ if (reg == NULL)
+ {
+ if (typeinfo)
+ *typeinfo = atype;
+ set_default_error ();
+ return PARSE_FAIL;
+ }
+
+ if (! aarch64_check_reg_type (reg, type))
+ {
+ DEBUG_TRACE ("reg type check failed");
+ set_default_error ();
+ return PARSE_FAIL;
+ }
+ type = reg->type;
+
+ if (type == REG_TYPE_VN
+ && parse_neon_operand_type (&parsetype, &str))
+ {
+ /* Register if of the form Vn.[bhsdq]. */
+ is_typed_vecreg = TRUE;
+
+ if (parsetype.width == 0)
+ /* Expect index. In the new scheme we cannot have
+ Vn.[bhsdq] represent a scalar. Therefore any
+ Vn.[bhsdq] should have an index following it.
+ Except in reglists ofcourse. */
+ atype.defined |= NTA_HASINDEX;
+ else
+ atype.defined |= NTA_HASTYPE;
+
+ atype.type = parsetype.type;
+ atype.width = parsetype.width;
+ }
+
+ if (skip_past_char (&str, '['))
+ {
+ expressionS exp;
+
+ /* Reject Sn[index] syntax. */
+ if (!is_typed_vecreg)
+ {
+ first_error (_("this type of register can't be indexed"));
+ return PARSE_FAIL;
+ }
+
+ if (in_reg_list == TRUE)
+ {
+ first_error (_("index not allowed inside register list"));
+ return PARSE_FAIL;
+ }
+
+ atype.defined |= NTA_HASINDEX;
+
+ my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
+
+ if (exp.X_op != O_constant)
+ {
+ first_error (_("constant expression required"));
+ return PARSE_FAIL;
+ }
+
+ if (! skip_past_char (&str, ']'))
+ return PARSE_FAIL;
+
+ atype.index = exp.X_add_number;
+ }
+ else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
+ {
+ /* Indexed vector register expected. */
+ first_error (_("indexed vector register expected"));
+ return PARSE_FAIL;
+ }
+
+ /* A vector reg Vn should be typed or indexed. */
+ if (type == REG_TYPE_VN && atype.defined == 0)
+ {
+ first_error (_("invalid use of vector register"));
+ }
+
+ if (typeinfo)
+ *typeinfo = atype;
+
+ if (rtype)
+ *rtype = type;
+
+ *ccp = str;
+
+ return reg->number;
+}
+
+/* Parse register.
+
+ Return the register number on success; return PARSE_FAIL otherwise.
+
+ If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
+ the register (e.g. NEON double or quad reg when either has been requested).
+
+ If this is a NEON vector register with additional type information, fill
+ in the struct pointed to by VECTYPE (if non-NULL).
+
+ This parser does not handle register list. */
+
+static int
+aarch64_reg_parse (char **ccp, aarch64_reg_type type,
+ aarch64_reg_type *rtype, struct neon_type_el *vectype)
+{
+ struct neon_type_el atype;
+ char *str = *ccp;
+ int reg = parse_typed_reg (&str, type, rtype, &atype,
+ /*in_reg_list= */ FALSE);
+
+ if (reg == PARSE_FAIL)
+ return PARSE_FAIL;
+
+ if (vectype)
+ *vectype = atype;
+
+ *ccp = str;
+
+ return reg;
+}
+
+static inline bfd_boolean
+eq_neon_type_el (struct neon_type_el e1, struct neon_type_el e2)
+{
+ return
+ e1.type == e2.type
+ && e1.defined == e2.defined
+ && e1.width == e2.width && e1.index == e2.index;
+}
+
+/* This function parses the NEON register list. On success, it returns
+ the parsed register list information in the following encoded format:
+
+ bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
+ 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
+
+ The information of the register shape and/or index is returned in
+ *VECTYPE.
+
+ It returns PARSE_FAIL if the register list is invalid.
+
+ The list contains one to four registers.
+ Each register can be one of:
+ <Vt>.<T>[<index>]
+ <Vt>.<T>
+ All <T> should be identical.
+ All <index> should be identical.
+ There are restrictions on <Vt> numbers which are checked later
+ (by reg_list_valid_p). */
+
+static int
+parse_neon_reg_list (char **ccp, struct neon_type_el *vectype)
+{
+ char *str = *ccp;
+ int nb_regs;
+ struct neon_type_el typeinfo, typeinfo_first;
+ int val, val_range;
+ int in_range;
+ int ret_val;
+ int i;
+ bfd_boolean error = FALSE;
+ bfd_boolean expect_index = FALSE;
+
+ if (*str != '{')
+ {
+ set_syntax_error (_("expecting {"));
+ return PARSE_FAIL;
+ }
+ str++;
+
+ nb_regs = 0;
+ typeinfo_first.defined = 0;
+ typeinfo_first.type = NT_invtype;
+ typeinfo_first.width = -1;
+ typeinfo_first.index = 0;
+ ret_val = 0;
+ val = -1;
+ val_range = -1;
+ in_range = 0;
+ do
+ {
+ if (in_range)
+ {
+ str++; /* skip over '-' */
+ val_range = val;
+ }
+ val = parse_typed_reg (&str, REG_TYPE_VN, NULL, &typeinfo,
+ /*in_reg_list= */ TRUE);
+ if (val == PARSE_FAIL)
+ {
+ set_first_syntax_error (_("invalid vector register in list"));
+ error = TRUE;
+ continue;
+ }
+ /* reject [bhsd]n */
+ if (typeinfo.defined == 0)
+ {
+ set_first_syntax_error (_("invalid scalar register in list"));
+ error = TRUE;
+ continue;
+ }
+
+ if (typeinfo.defined & NTA_HASINDEX)
+ expect_index = TRUE;
+
+ if (in_range)
+ {
+ if (val < val_range)
+ {
+ set_first_syntax_error
+ (_("invalid range in vector register list"));
+ error = TRUE;
+ }
+ val_range++;
+ }
+ else
+ {
+ val_range = val;
+ if (nb_regs == 0)
+ typeinfo_first = typeinfo;
+ else if (! eq_neon_type_el (typeinfo_first, typeinfo))
+ {
+ set_first_syntax_error
+ (_("type mismatch in vector register list"));
+ error = TRUE;
+ }
+ }
+ if (! error)
+ for (i = val_range; i <= val; i++)
+ {
+ ret_val |= i << (5 * nb_regs);
+ nb_regs++;
+ }
+ in_range = 0;
+ }
+ while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
+
+ skip_whitespace (str);
+ if (*str != '}')
+ {
+ set_first_syntax_error (_("end of vector register list not found"));
+ error = TRUE;
+ }
+ str++;
+
+ skip_whitespace (str);
+
+ if (expect_index)
+ {
+ if (skip_past_char (&str, '['))
+ {
+ expressionS exp;
+
+ my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
+ if (exp.X_op != O_constant)
+ {
+ set_first_syntax_error (_("constant expression required."));
+ error = TRUE;
+ }
+ if (! skip_past_char (&str, ']'))
+ error = TRUE;
+ else
+ typeinfo_first.index = exp.X_add_number;
+ }
+ else
+ {
+ set_first_syntax_error (_("expected index"));
+ error = TRUE;
+ }
+ }
+
+ if (nb_regs > 4)
+ {
+ set_first_syntax_error (_("too many registers in vector register list"));
+ error = TRUE;
+ }
+ else if (nb_regs == 0)
+ {
+ set_first_syntax_error (_("empty vector register list"));
+ error = TRUE;
+ }
+
+ *ccp = str;
+ if (! error)
+ *vectype = typeinfo_first;
+
+ return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1);
+}
+
+/* Directives: register aliases. */
+
+static reg_entry *
+insert_reg_alias (char *str, int number, aarch64_reg_type type)
+{
+ reg_entry *new;
+ const char *name;
+
+ if ((new = hash_find (aarch64_reg_hsh, str)) != 0)
+ {
+ if (new->builtin)
+ as_warn (_("ignoring attempt to redefine built-in register '%s'"),
+ str);
+
+ /* Only warn about a redefinition if it's not defined as the
+ same register. */
+ else if (new->number != number || new->type != type)
+ as_warn (_("ignoring redefinition of register alias '%s'"), str);
+
+ return NULL;
+ }
+
+ name = xstrdup (str);
+ new = xmalloc (sizeof (reg_entry));
+
+ new->name = name;
+ new->number = number;
+ new->type = type;
+ new->builtin = FALSE;
+
+ if (hash_insert (aarch64_reg_hsh, name, (void *) new))
+ abort ();
+
+ return new;
+}
+
+/* Look for the .req directive. This is of the form:
+
+ new_register_name .req existing_register_name
+
+ If we find one, or if it looks sufficiently like one that we want to
+ handle any error here, return TRUE. Otherwise return FALSE. */
+
+static bfd_boolean
+create_register_alias (char *newname, char *p)
+{
+ const reg_entry *old;
+ char *oldname, *nbuf;
+ size_t nlen;
+
+ /* The input scrubber ensures that whitespace after the mnemonic is
+ collapsed to single spaces. */
+ oldname = p;
+ if (strncmp (oldname, " .req ", 6) != 0)
+ return FALSE;
+
+ oldname += 6;
+ if (*oldname == '\0')
+ return FALSE;
+
+ old = hash_find (aarch64_reg_hsh, oldname);
+ if (!old)
+ {
+ as_warn (_("unknown register '%s' -- .req ignored"), oldname);
+ return TRUE;
+ }
+
+ /* If TC_CASE_SENSITIVE is defined, then newname already points to
+ the desired alias name, and p points to its end. If not, then
+ the desired alias name is in the global original_case_string. */
+#ifdef TC_CASE_SENSITIVE
+ nlen = p - newname;
+#else
+ newname = original_case_string;
+ nlen = strlen (newname);
+#endif
+
+ nbuf = alloca (nlen + 1);
+ memcpy (nbuf, newname, nlen);
+ nbuf[nlen] = '\0';
+
+ /* Create aliases under the new name as stated; an all-lowercase
+ version of the new name; and an all-uppercase version of the new
+ name. */
+ if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
+ {
+ for (p = nbuf; *p; p++)
+ *p = TOUPPER (*p);
+
+ if (strncmp (nbuf, newname, nlen))
+ {
+ /* If this attempt to create an additional alias fails, do not bother
+ trying to create the all-lower case alias. We will fail and issue
+ a second, duplicate error message. This situation arises when the
+ programmer does something like:
+ foo .req r0
+ Foo .req r1
+ The second .req creates the "Foo" alias but then fails to create
+ the artificial FOO alias because it has already been created by the
+ first .req. */
+ if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
+ return TRUE;
+ }
+
+ for (p = nbuf; *p; p++)
+ *p = TOLOWER (*p);
+
+ if (strncmp (nbuf, newname, nlen))
+ insert_reg_alias (nbuf, old->number, old->type);
+ }
+
+ return TRUE;
+}
+
+/* Should never be called, as .req goes between the alias and the
+ register name, not at the beginning of the line. */
+static void
+s_req (int a ATTRIBUTE_UNUSED)
+{
+ as_bad (_("invalid syntax for .req directive"));
+}
+
+/* The .unreq directive deletes an alias which was previously defined
+ by .req. For example:
+
+ my_alias .req r11
+ .unreq my_alias */
+
+static void
+s_unreq (int a ATTRIBUTE_UNUSED)
+{
+ char *name;
+ char saved_char;
+
+ name = input_line_pointer;
+
+ while (*input_line_pointer != 0
+ && *input_line_pointer != ' ' && *input_line_pointer != '\n')
+ ++input_line_pointer;
+
+ saved_char = *input_line_pointer;
+ *input_line_pointer = 0;
+
+ if (!*name)
+ as_bad (_("invalid syntax for .unreq directive"));
+ else
+ {
+ reg_entry *reg = hash_find (aarch64_reg_hsh, name);
+
+ if (!reg)
+ as_bad (_("unknown register alias '%s'"), name);
+ else if (reg->builtin)
+ as_warn (_("ignoring attempt to undefine built-in register '%s'"),
+ name);
+ else
+ {
+ char *p;
+ char *nbuf;
+
+ hash_delete (aarch64_reg_hsh, name, FALSE);
+ free ((char *) reg->name);
+ free (reg);
+
+ /* Also locate the all upper case and all lower case versions.
+ Do not complain if we cannot find one or the other as it
+ was probably deleted above. */
+
+ nbuf = strdup (name);
+ for (p = nbuf; *p; p++)
+ *p = TOUPPER (*p);
+ reg = hash_find (aarch64_reg_hsh, nbuf);
+ if (reg)
+ {
+ hash_delete (aarch64_reg_hsh, nbuf, FALSE);
+ free ((char *) reg->name);
+ free (reg);
+ }
+
+ for (p = nbuf; *p; p++)
+ *p = TOLOWER (*p);
+ reg = hash_find (aarch64_reg_hsh, nbuf);
+ if (reg)
+ {
+ hash_delete (aarch64_reg_hsh, nbuf, FALSE);
+ free ((char *) reg->name);
+ free (reg);
+ }
+
+ free (nbuf);
+ }
+ }
+
+ *input_line_pointer = saved_char;
+ demand_empty_rest_of_line ();
+}
+
+/* Directives: Instruction set selection. */
+
+#ifdef OBJ_ELF
+/* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
+ spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
+ Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
+ and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
+
+/* Create a new mapping symbol for the transition to STATE. */
+
+static void
+make_mapping_symbol (enum mstate state, valueT value, fragS * frag)
+{
+ symbolS *symbolP;
+ const char *symname;
+ int type;
+
+ switch (state)
+ {
+ case MAP_DATA:
+ symname = "$d";
+ type = BSF_NO_FLAGS;
+ break;
+ case MAP_INSN:
+ symname = "$x";
+ type = BSF_NO_FLAGS;
+ break;
+ default:
+ abort ();
+ }
+
+ symbolP = symbol_new (symname, now_seg, value, frag);
+ symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
+
+ /* Save the mapping symbols for future reference. Also check that
+ we do not place two mapping symbols at the same offset within a
+ frag. We'll handle overlap between frags in
+ check_mapping_symbols.
+
+ If .fill or other data filling directive generates zero sized data,
+ the mapping symbol for the following code will have the same value
+ as the one generated for the data filling directive. In this case,
+ we replace the old symbol with the new one at the same address. */
+ if (value == 0)
+ {
+ if (frag->tc_frag_data.first_map != NULL)
+ {
+ know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
+ symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP,
+ &symbol_lastP);
+ }
+ frag->tc_frag_data.first_map = symbolP;
+ }
+ if (frag->tc_frag_data.last_map != NULL)
+ {
+ know (S_GET_VALUE (frag->tc_frag_data.last_map) <=
+ S_GET_VALUE (symbolP));
+ if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
+ symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP,
+ &symbol_lastP);
+ }
+ frag->tc_frag_data.last_map = symbolP;
+}
+
+/* We must sometimes convert a region marked as code to data during
+ code alignment, if an odd number of bytes have to be padded. The
+ code mapping symbol is pushed to an aligned address. */
+
+static void
+insert_data_mapping_symbol (enum mstate state,
+ valueT value, fragS * frag, offsetT bytes)
+{
+ /* If there was already a mapping symbol, remove it. */
+ if (frag->tc_frag_data.last_map != NULL
+ && S_GET_VALUE (frag->tc_frag_data.last_map) ==
+ frag->fr_address + value)
+ {
+ symbolS *symp = frag->tc_frag_data.last_map;
+
+ if (value == 0)
+ {
+ know (frag->tc_frag_data.first_map == symp);
+ frag->tc_frag_data.first_map = NULL;
+ }
+ frag->tc_frag_data.last_map = NULL;
+ symbol_remove (symp, &symbol_rootP, &symbol_lastP);
+ }
+
+ make_mapping_symbol (MAP_DATA, value, frag);
+ make_mapping_symbol (state, value + bytes, frag);
+}
+
+static void mapping_state_2 (enum mstate state, int max_chars);
+
+/* Set the mapping state to STATE. Only call this when about to
+ emit some STATE bytes to the file. */
+
+void
+mapping_state (enum mstate state)
+{
+ enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
+
+#define TRANSITION(from, to) (mapstate == (from) && state == (to))
+
+ if (mapstate == state)
+ /* The mapping symbol has already been emitted.
+ There is nothing else to do. */
+ return;
+ else if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
+ /* This case will be evaluated later in the next else. */
+ return;
+ else if (TRANSITION (MAP_UNDEFINED, MAP_INSN))
+ {
+ /* Only add the symbol if the offset is > 0:
+ if we're at the first frag, check it's size > 0;
+ if we're not at the first frag, then for sure
+ the offset is > 0. */
+ struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root;
+ const int add_symbol = (frag_now != frag_first)
+ || (frag_now_fix () > 0);
+
+ if (add_symbol)
+ make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
+ }
+
+ mapping_state_2 (state, 0);
+#undef TRANSITION
+}
+
+/* Same as mapping_state, but MAX_CHARS bytes have already been
+ allocated. Put the mapping symbol that far back. */
+
+static void
+mapping_state_2 (enum mstate state, int max_chars)
+{
+ enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
+
+ if (!SEG_NORMAL (now_seg))
+ return;
+
+ if (mapstate == state)
+ /* The mapping symbol has already been emitted.
+ There is nothing else to do. */
+ return;
+
+ seg_info (now_seg)->tc_segment_info_data.mapstate = state;
+ make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
+}
+#else
+#define mapping_state(x) /* nothing */
+#define mapping_state_2(x, y) /* nothing */
+#endif
+
+/* Directives: sectioning and alignment. */
+
+static void
+s_bss (int ignore ATTRIBUTE_UNUSED)
+{
+ /* We don't support putting frags in the BSS segment, we fake it by
+ marking in_bss, then looking at s_skip for clues. */
+ subseg_set (bss_section, 0);
+ demand_empty_rest_of_line ();
+ mapping_state (MAP_DATA);
+}
+
+static void
+s_even (int ignore ATTRIBUTE_UNUSED)
+{
+ /* Never make frag if expect extra pass. */
+ if (!need_pass_2)
+ frag_align (1, 0, 0);
+
+ record_alignment (now_seg, 1);
+
+ demand_empty_rest_of_line ();
+}
+
+/* Directives: Literal pools. */
+
+static literal_pool *
+find_literal_pool (int size)
+{
+ literal_pool *pool;
+
+ for (pool = list_of_pools; pool != NULL; pool = pool->next)
+ {
+ if (pool->section == now_seg
+ && pool->sub_section == now_subseg && pool->size == size)
+ break;
+ }
+
+ return pool;
+}
+
+static literal_pool *
+find_or_make_literal_pool (int size)
+{
+ /* Next literal pool ID number. */
+ static unsigned int latest_pool_num = 1;
+ literal_pool *pool;
+
+ pool = find_literal_pool (size);
+
+ if (pool == NULL)
+ {
+ /* Create a new pool. */
+ pool = xmalloc (sizeof (*pool));
+ if (!pool)
+ return NULL;
+
+ /* Currently we always put the literal pool in the current text
+ section. If we were generating "small" model code where we
+ knew that all code and initialised data was within 1MB then
+ we could output literals to mergeable, read-only data
+ sections. */
+
+ pool->next_free_entry = 0;
+ pool->section = now_seg;
+ pool->sub_section = now_subseg;
+ pool->size = size;
+ pool->next = list_of_pools;
+ pool->symbol = NULL;
+
+ /* Add it to the list. */
+ list_of_pools = pool;
+ }
+
+ /* New pools, and emptied pools, will have a NULL symbol. */
+ if (pool->symbol == NULL)
+ {
+ pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
+ (valueT) 0, &zero_address_frag);
+ pool->id = latest_pool_num++;
+ }
+
+ /* Done. */
+ return pool;
+}
+
+/* Add the literal of size SIZE in *EXP to the relevant literal pool.
+ Return TRUE on success, otherwise return FALSE. */
+static bfd_boolean
+add_to_lit_pool (expressionS *exp, int size)
+{
+ literal_pool *pool;
+ unsigned int entry;
+
+ pool = find_or_make_literal_pool (size);
+
+ /* Check if this literal value is already in the pool. */
+ for (entry = 0; entry < pool->next_free_entry; entry++)
+ {
+ if ((pool->literals[entry].X_op == exp->X_op)
+ && (exp->X_op == O_constant)
+ && (pool->literals[entry].X_add_number == exp->X_add_number)
+ && (pool->literals[entry].X_unsigned == exp->X_unsigned))
+ break;
+
+ if ((pool->literals[entry].X_op == exp->X_op)
+ && (exp->X_op == O_symbol)
+ && (pool->literals[entry].X_add_number == exp->X_add_number)
+ && (pool->literals[entry].X_add_symbol == exp->X_add_symbol)
+ && (pool->literals[entry].X_op_symbol == exp->X_op_symbol))
+ break;
+ }
+
+ /* Do we need to create a new entry? */
+ if (entry == pool->next_free_entry)
+ {
+ if (entry >= MAX_LITERAL_POOL_SIZE)
+ {
+ set_syntax_error (_("literal pool overflow"));
+ return FALSE;
+ }
+
+ pool->literals[entry] = *exp;
+ pool->next_free_entry += 1;
+ }
+
+ exp->X_op = O_symbol;
+ exp->X_add_number = ((int) entry) * size;
+ exp->X_add_symbol = pool->symbol;
+
+ return TRUE;
+}
+
+/* Can't use symbol_new here, so have to create a symbol and then at
+ a later date assign it a value. Thats what these functions do. */
+
+static void
+symbol_locate (symbolS * symbolP,
+ const char *name,/* It is copied, the caller can modify. */
+ segT segment, /* Segment identifier (SEG_<something>). */
+ valueT valu, /* Symbol value. */
+ fragS * frag) /* Associated fragment. */
+{
+ unsigned int name_length;
+ char *preserved_copy_of_name;
+
+ name_length = strlen (name) + 1; /* +1 for \0. */
+ obstack_grow (¬es, name, name_length);
+ preserved_copy_of_name = obstack_finish (¬es);
+
+#ifdef tc_canonicalize_symbol_name
+ preserved_copy_of_name =
+ tc_canonicalize_symbol_name (preserved_copy_of_name);
+#endif
+
+ S_SET_NAME (symbolP, preserved_copy_of_name);
+
+ S_SET_SEGMENT (symbolP, segment);
+ S_SET_VALUE (symbolP, valu);
+ symbol_clear_list_pointers (symbolP);
+
+ symbol_set_frag (symbolP, frag);
+
+ /* Link to end of symbol chain. */
+ {
+ extern int symbol_table_frozen;
+
+ if (symbol_table_frozen)
+ abort ();
+ }
+
+ symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
+
+ obj_symbol_new_hook (symbolP);
+
+#ifdef tc_symbol_new_hook
+ tc_symbol_new_hook (symbolP);
+#endif
+
+#ifdef DEBUG_SYMS
+ verify_symbol_chain (symbol_rootP, symbol_lastP);
+#endif /* DEBUG_SYMS */
+}
+
+
+static void
+s_ltorg (int ignored ATTRIBUTE_UNUSED)
+{
+ unsigned int entry;
+ literal_pool *pool;
+ char sym_name[20];
+ int align;
+
+ for (align = 2; align < 4; align++)
+ {
+ int size = 1 << align;
+
+ pool = find_literal_pool (size);
+ if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
+ continue;
+
+ mapping_state (MAP_DATA);
+
+ /* Align pool as you have word accesses.
+ Only make a frag if we have to. */
+ if (!need_pass_2)
+ frag_align (align, 0, 0);
+
+ record_alignment (now_seg, align);
+
+ sprintf (sym_name, "$$lit_\002%x", pool->id);
+
+ symbol_locate (pool->symbol, sym_name, now_seg,
+ (valueT) frag_now_fix (), frag_now);
+ symbol_table_insert (pool->symbol);
+
+ for (entry = 0; entry < pool->next_free_entry; entry++)
+ /* First output the expression in the instruction to the pool. */
+ emit_expr (&(pool->literals[entry]), size); /* .word|.xword */
+
+ /* Mark the pool as empty. */
+ pool->next_free_entry = 0;
+ pool->symbol = NULL;
+ }
+}
+
+#ifdef OBJ_ELF
+/* Forward declarations for functions below, in the MD interface
+ section. */
+static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int);
+static struct reloc_table_entry * find_reloc_table_entry (char **);
+
+/* Directives: Data. */
+/* N.B. the support for relocation suffix in this directive needs to be
+ implemented properly. */
+
+static void
+s_aarch64_elf_cons (int nbytes)
+{
+ expressionS exp;
+
+#ifdef md_flush_pending_output
+ md_flush_pending_output ();
+#endif
+
+ if (is_it_end_of_statement ())
+ {
+ demand_empty_rest_of_line ();
+ return;
+ }
+
+#ifdef md_cons_align
+ md_cons_align (nbytes);
+#endif
+
+ mapping_state (MAP_DATA);
+ do
+ {
+ struct reloc_table_entry *reloc;
+
+ expression (&exp);
+
+ if (exp.X_op != O_symbol)
+ emit_expr (&exp, (unsigned int) nbytes);
+ else
+ {
+ skip_past_char (&input_line_pointer, '#');
+ if (skip_past_char (&input_line_pointer, ':'))
+ {
+ reloc = find_reloc_table_entry (&input_line_pointer);
+ if (reloc == NULL)
+ as_bad (_("unrecognized relocation suffix"));
+ else
+ as_bad (_("unimplemented relocation suffix"));
+ ignore_rest_of_line ();
+ return;
+ }
+ else
+ emit_expr (&exp, (unsigned int) nbytes);
+ }
+ }
+ while (*input_line_pointer++ == ',');
+
+ /* Put terminator back into stream. */
+ input_line_pointer--;
+ demand_empty_rest_of_line ();
+}
+
+#endif /* OBJ_ELF */
+
+/* Output a 32-bit word, but mark as an instruction. */
+
+static void
+s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
+{
+ expressionS exp;
+
+#ifdef md_flush_pending_output
+ md_flush_pending_output ();
+#endif
+
+ if (is_it_end_of_statement ())
+ {
+ demand_empty_rest_of_line ();
+ return;
+ }
+
+ if (!need_pass_2)
+ frag_align_code (2, 0);
+#ifdef OBJ_ELF
+ mapping_state (MAP_INSN);
+#endif
+
+ do
+ {
+ expression (&exp);
+ if (exp.X_op != O_constant)
+ {
+ as_bad (_("constant expression required"));
+ ignore_rest_of_line ();
+ return;
+ }
+
+ if (target_big_endian)
+ {
+ unsigned int val = exp.X_add_number;
+ exp.X_add_number = SWAP_32 (val);
+ }
+ emit_expr (&exp, 4);
+ }
+ while (*input_line_pointer++ == ',');
+
+ /* Put terminator back into stream. */
+ input_line_pointer--;
+ demand_empty_rest_of_line ();
+}
+
+#ifdef OBJ_ELF
+/* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
+
+static void
+s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
+{
+ expressionS exp;
+
+ /* Since we're just labelling the code, there's no need to define a
+ mapping symbol. */
+ expression (&exp);
+ /* Make sure there is enough room in this frag for the following
+ blr. This trick only works if the blr follows immediately after
+ the .tlsdesc directive. */
+ frag_grow (4);
+ fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
+ BFD_RELOC_AARCH64_TLSDESC_CALL);
+
+ demand_empty_rest_of_line ();
+}
+#endif /* OBJ_ELF */
+
+static void s_aarch64_arch (int);
+static void s_aarch64_cpu (int);
+
+/* This table describes all the machine specific pseudo-ops the assembler
+ has to support. The fields are:
+ pseudo-op name without dot
+ function to call to execute this pseudo-op
+ Integer arg to pass to the function. */
+
+const pseudo_typeS md_pseudo_table[] = {
+ /* Never called because '.req' does not start a line. */
+ {"req", s_req, 0},
+ {"unreq", s_unreq, 0},
+ {"bss", s_bss, 0},
+ {"even", s_even, 0},
+ {"ltorg", s_ltorg, 0},
+ {"pool", s_ltorg, 0},
+ {"cpu", s_aarch64_cpu, 0},
+ {"arch", s_aarch64_arch, 0},
+ {"inst", s_aarch64_inst, 0},
+#ifdef OBJ_ELF
+ {"tlsdesccall", s_tlsdesccall, 0},
+ {"word", s_aarch64_elf_cons, 4},
+ {"long", s_aarch64_elf_cons, 4},
+ {"xword", s_aarch64_elf_cons, 8},
+ {"dword", s_aarch64_elf_cons, 8},
+#endif
+ {0, 0, 0}
+};
+\f
+
+/* Check whether STR points to a register name followed by a comma or the
+ end of line; REG_TYPE indicates which register types are checked
+ against. Return TRUE if STR is such a register name; otherwise return
+ FALSE. The function does not intend to produce any diagnostics, but since
+ the register parser aarch64_reg_parse, which is called by this function,
+ does produce diagnostics, we call clear_error to clear any diagnostics
+ that may be generated by aarch64_reg_parse.
+ Also, the function returns FALSE directly if there is any user error
+ present at the function entry. This prevents the existing diagnostics
+ state from being spoiled.
+ The function currently serves parse_constant_immediate and
+ parse_big_immediate only. */
+static bfd_boolean
+reg_name_p (char *str, aarch64_reg_type reg_type)
+{
+ int reg;
+
+ /* Prevent the diagnostics state from being spoiled. */
+ if (error_p ())
+ return FALSE;
+
+ reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
+
+ /* Clear the parsing error that may be set by the reg parser. */
+ clear_error ();
+
+ if (reg == PARSE_FAIL)
+ return FALSE;
+
+ skip_whitespace (str);
+ if (*str == ',' || is_end_of_line[(unsigned int) *str])
+ return TRUE;
+
+ return FALSE;
+}
+
+/* Parser functions used exclusively in instruction operands. */
+
+/* Parse an immediate expression which may not be constant.
+
+ To prevent the expression parser from pushing a register name
+ into the symbol table as an undefined symbol, firstly a check is
+ done to find out whether STR is a valid register name followed
+ by a comma or the end of line. Return FALSE if STR is such a
+ string. */
+
+static bfd_boolean
+parse_immediate_expression (char **str, expressionS *exp)
+{
+ if (reg_name_p (*str, REG_TYPE_R_Z_BHSDQ_V))
+ {
+ set_recoverable_error (_("immediate operand required"));
+ return FALSE;
+ }
+
+ my_get_expression (exp, str, GE_OPT_PREFIX, 1);
+
+ if (exp->X_op == O_absent)
+ {
+ set_fatal_syntax_error (_("missing immediate expression"));
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+/* Constant immediate-value read function for use in insn parsing.
+ STR points to the beginning of the immediate (with the optional
+ leading #); *VAL receives the value.
+
+ Return TRUE on success; otherwise return FALSE. */
+
+static bfd_boolean
+parse_constant_immediate (char **str, int64_t * val)
+{
+ expressionS exp;
+
+ if (! parse_immediate_expression (str, &exp))
+ return FALSE;
+
+ if (exp.X_op != O_constant)
+ {
+ set_syntax_error (_("constant expression required"));
+ return FALSE;
+ }
+
+ *val = exp.X_add_number;
+ return TRUE;
+}
+
+static uint32_t
+encode_imm_float_bits (uint32_t imm)
+{
+ return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */
+ | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
+}
+
+/* Return TRUE if IMM is a valid floating-point immediate; return FALSE
+ otherwise. */
+static bfd_boolean
+aarch64_imm_float_p (uint32_t imm)
+{
+ /* 3 32222222 2221111111111
+ 1 09876543 21098765432109876543210
+ n Eeeeeexx xxxx0000000000000000000 */
+ uint32_t e;
+
+ e = (imm >> 30) & 0x1;
+ if (e == 0)
+ e = 0x3e000000;
+ else
+ e = 0x40000000;
+ return (imm & 0x7ffff) == 0 /* lower 19 bits are 0 */
+ && ((imm & 0x7e000000) == e); /* bits 25-29 = ~ bit 30 */
+}
+
+/* Note: this accepts the floating-point 0 constant. */
+static bfd_boolean
+parse_aarch64_imm_float (char **ccp, int *immed)
+{
+ char *str = *ccp;
+ char *fpnum;
+ LITTLENUM_TYPE words[MAX_LITTLENUMS];
+ int found_fpchar = 0;
+
+ skip_past_char (&str, '#');
+
+ /* We must not accidentally parse an integer as a floating-point number. Make
+ sure that the value we parse is not an integer by checking for special
+ characters '.' or 'e'.
+ FIXME: This is a hack that is not very efficient, but doing better is
+ tricky because type information isn't in a very usable state at parse
+ time. */
+ fpnum = str;
+ skip_whitespace (fpnum);
+
+ if (strncmp (fpnum, "0x", 2) == 0)
+ return FALSE;
+ else
+ {
+ for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
+ if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
+ {
+ found_fpchar = 1;
+ break;
+ }
+
+ if (!found_fpchar)
+ return FALSE;
+ }
+
+ if ((str = atof_ieee (str, 's', words)) != NULL)
+ {
+ unsigned fpword = 0;
+ int i;
+
+ /* Our FP word must be 32 bits (single-precision FP). */
+ for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
+ {
+ fpword <<= LITTLENUM_NUMBER_OF_BITS;
+ fpword |= words[i];
+ }
+
+ if (aarch64_imm_float_p (fpword) || (fpword & 0x7fffffff) == 0)
+ *immed = fpword;
+ else
+ goto invalid_fp;
+
+ *ccp = str;
+
+ return TRUE;
+ }
+
+invalid_fp:
+ set_fatal_syntax_error (_("invalid floating-point constant"));
+ return FALSE;
+}
+
+/* Less-generic immediate-value read function with the possibility of loading
+ a big (64-bit) immediate, as required by AdvSIMD Modified immediate
+ instructions.
+
+ To prevent the expression parser from pushing a register name into the
+ symbol table as an undefined symbol, a check is firstly done to find
+ out whether STR is a valid register name followed by a comma or the end
+ of line. Return FALSE if STR is such a register. */
+
+static bfd_boolean
+parse_big_immediate (char **str, int64_t *imm)
+{
+ char *ptr = *str;
+
+ if (reg_name_p (ptr, REG_TYPE_R_Z_BHSDQ_V))
+ {
+ set_syntax_error (_("immediate operand required"));
+ return FALSE;
+ }
+
+ my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
+
+ if (inst.reloc.exp.X_op == O_constant)
+ *imm = inst.reloc.exp.X_add_number;
+
+ *str = ptr;
+
+ return TRUE;
+}
+
+/* Set operand IDX of the *INSTR that needs a GAS internal fixup.
+ if NEED_LIBOPCODES is non-zero, the fixup will need
+ assistance from the libopcodes. */
+
+static inline void
+aarch64_set_gas_internal_fixup (struct reloc *reloc,
+ const aarch64_opnd_info *operand,
+ int need_libopcodes_p)
+{
+ reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
+ reloc->opnd = operand->type;
+ if (need_libopcodes_p)
+ reloc->need_libopcodes_p = 1;
+};
+
+/* Return TRUE if the instruction needs to be fixed up later internally by
+ the GAS; otherwise return FALSE. */
+
+static inline bfd_boolean
+aarch64_gas_internal_fixup_p (void)
+{
+ return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
+}
+
+/* Assign the immediate value to the relavant field in *OPERAND if
+ RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
+ needs an internal fixup in a later stage.
+ ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
+ IMM.VALUE that may get assigned with the constant. */
+static inline void
+assign_imm_if_const_or_fixup_later (struct reloc *reloc,
+ aarch64_opnd_info *operand,
+ int addr_off_p,
+ int need_libopcodes_p,
+ int skip_p)
+{
+ if (reloc->exp.X_op == O_constant)
+ {
+ if (addr_off_p)
+ operand->addr.offset.imm = reloc->exp.X_add_number;
+ else
+ operand->imm.value = reloc->exp.X_add_number;
+ reloc->type = BFD_RELOC_UNUSED;
+ }
+ else
+ {
+ aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p);
+ /* Tell libopcodes to ignore this operand or not. This is helpful
+ when one of the operands needs to be fixed up later but we need
+ libopcodes to check the other operands. */
+ operand->skip = skip_p;
+ }
+}
+
+/* Relocation modifiers. Each entry in the table contains the textual
+ name for the relocation which may be placed before a symbol used as
+ a load/store offset, or add immediate. It must be surrounded by a
+ leading and trailing colon, for example:
+
+ ldr x0, [x1, #:rello:varsym]
+ add x0, x1, #:rello:varsym */
+
+struct reloc_table_entry
+{
+ const char *name;
+ int pc_rel;
+ bfd_reloc_code_real_type adrp_type;
+ bfd_reloc_code_real_type movw_type;
+ bfd_reloc_code_real_type add_type;
+ bfd_reloc_code_real_type ldst_type;
+};
+
+static struct reloc_table_entry reloc_table[] = {
+ /* Low 12 bits of absolute address: ADD/i and LDR/STR */
+ {"lo12", 0,
+ 0,
+ 0,
+ BFD_RELOC_AARCH64_ADD_LO12,
+ BFD_RELOC_AARCH64_LDST_LO12},
+
+ /* Higher 21 bits of pc-relative page offset: ADRP */
+ {"pg_hi21", 1,
+ BFD_RELOC_AARCH64_ADR_HI21_PCREL,
+ 0,
+ 0,
+ 0},
+
+ /* Higher 21 bits of pc-relative page offset: ADRP, no check */
+ {"pg_hi21_nc", 1,
+ BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
+ 0,
+ 0,
+ 0},
+
+ /* Most significant bits 0-15 of unsigned address/value: MOVZ */
+ {"abs_g0", 0,
+ 0,
+ BFD_RELOC_AARCH64_MOVW_G0,
+ 0,
+ 0},
+
+ /* Most significant bits 0-15 of signed address/value: MOVN/Z */
+ {"abs_g0_s", 0,
+ 0,
+ BFD_RELOC_AARCH64_MOVW_G0_S,
+ 0,
+ 0},
+
+ /* Less significant bits 0-15 of address/value: MOVK, no check */
+ {"abs_g0_nc", 0,
+ 0,
+ BFD_RELOC_AARCH64_MOVW_G0_NC,
+ 0,
+ 0},
+
+ /* Most significant bits 16-31 of unsigned address/value: MOVZ */
+ {"abs_g1", 0,
+ 0,
+ BFD_RELOC_AARCH64_MOVW_G1,
+ 0,
+ 0},
+
+ /* Most significant bits 16-31 of signed address/value: MOVN/Z */
+ {"abs_g1_s", 0,
+ 0,
+ BFD_RELOC_AARCH64_MOVW_G1_S,
+ 0,
+ 0},
+
+ /* Less significant bits 16-31 of address/value: MOVK, no check */
+ {"abs_g1_nc", 0,
+ 0,
+ BFD_RELOC_AARCH64_MOVW_G1_NC,
+ 0,
+ 0},
+
+ /* Most significant bits 32-47 of unsigned address/value: MOVZ */
+ {"abs_g2", 0,
+ 0,
+ BFD_RELOC_AARCH64_MOVW_G2,
+ 0,
+ 0},
+
+ /* Most significant bits 32-47 of signed address/value: MOVN/Z */
+ {"abs_g2_s", 0,
+ 0,
+ BFD_RELOC_AARCH64_MOVW_G2_S,
+ 0,
+ 0},
+
+ /* Less significant bits 32-47 of address/value: MOVK, no check */
+ {"abs_g2_nc", 0,
+ 0,
+ BFD_RELOC_AARCH64_MOVW_G2_NC,
+ 0,
+ 0},
+
+ /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
+ {"abs_g3", 0,
+ 0,
+ BFD_RELOC_AARCH64_MOVW_G3,
+ 0,
+ 0},
+ /* Get to the page containing GOT entry for a symbol. */
+ {"got", 1,
+ BFD_RELOC_AARCH64_ADR_GOT_PAGE,
+ 0,
+ 0,
+ 0},
+ /* 12 bit offset into the page containing GOT entry for that symbol. */
+ {"got_lo12", 0,
+ 0,
+ 0,
+ 0,
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC},
+
+ /* Get to the page containing GOT TLS entry for a symbol */
+ {"tlsgd", 0,
+ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
+ 0,
+ 0,
+ 0},
+
+ /* 12 bit offset into the page containing GOT TLS entry for a symbol */
+ {"tlsgd_lo12", 0,
+ 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
+ 0},
+
+ /* Get to the page containing GOT TLS entry for a symbol */
+ {"tlsdesc", 0,
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE,
+ 0,
+ 0,
+ 0},
+
+ /* 12 bit offset into the page containing GOT TLS entry for a symbol */
+ {"tlsdesc_lo12", 0,
+ 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC},
+
+ /* Get to the page containing GOT TLS entry for a symbol */
+ {"gottprel", 0,
+ BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
+ 0,
+ 0,
+ 0},
+
+ /* 12 bit offset into the page containing GOT TLS entry for a symbol */
+ {"gottprel_lo12", 0,
+ 0,
+ 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC},
+
+ /* Get tp offset for a symbol. */
+ {"tprel", 0,
+ 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
+ 0},
+
+ /* Get tp offset for a symbol. */
+ {"tprel_lo12", 0,
+ 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
+ 0},
+
+ /* Get tp offset for a symbol. */
+ {"tprel_hi12", 0,
+ 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
+ 0},
+
+ /* Get tp offset for a symbol. */
+ {"tprel_lo12_nc", 0,
+ 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
+ 0},
+
+ /* Most significant bits 32-47 of address/value: MOVZ. */
+ {"tprel_g2", 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
+ 0,
+ 0},
+
+ /* Most significant bits 16-31 of address/value: MOVZ. */
+ {"tprel_g1", 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
+ 0,
+ 0},
+
+ /* Most significant bits 16-31 of address/value: MOVZ, no check. */
+ {"tprel_g1_nc", 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
+ 0,
+ 0},
+
+ /* Most significant bits 0-15 of address/value: MOVZ. */
+ {"tprel_g0", 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
+ 0,
+ 0},
+
+ /* Most significant bits 0-15 of address/value: MOVZ, no check. */
+ {"tprel_g0_nc", 0,
+ 0,
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
+ 0,
+ 0},
+};
+
+/* Given the address of a pointer pointing to the textual name of a
+ relocation as may appear in assembler source, attempt to find its
+ details in reloc_table. The pointer will be updated to the character
+ after the trailing colon. On failure, NULL will be returned;
+ otherwise return the reloc_table_entry. */
+
+static struct reloc_table_entry *
+find_reloc_table_entry (char **str)
+{
+ unsigned int i;
+ for (i = 0; i < ARRAY_SIZE (reloc_table); i++)
+ {
+ int length = strlen (reloc_table[i].name);
+
+ if (strncasecmp (reloc_table[i].name, *str, length) == 0
+ && (*str)[length] == ':')
+ {
+ *str += (length + 1);
+ return &reloc_table[i];
+ }
+ }
+
+ return NULL;
+}
+
+/* Mode argument to parse_shift and parser_shifter_operand. */
+enum parse_shift_mode
+{
+ SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
+ "#imm{,lsl #n}" */
+ SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
+ "#imm" */
+ SHIFTED_LSL, /* bare "lsl #n" */
+ SHIFTED_LSL_MSL, /* "lsl|msl #n" */
+ SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */
+};
+
+/* Parse a <shift> operator on an AArch64 data processing instruction.
+ Return TRUE on success; otherwise return FALSE. */
+static bfd_boolean
+parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
+{
+ const struct aarch64_name_value_pair *shift_op;
+ enum aarch64_modifier_kind kind;
+ expressionS exp;
+ int exp_has_prefix;
+ char *s = *str;
+ char *p = s;
+
+ for (p = *str; ISALPHA (*p); p++)
+ ;
+
+ if (p == *str)
+ {
+ set_syntax_error (_("shift expression expected"));
+ return FALSE;
+ }
+
+ shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str);
+
+ if (shift_op == NULL)
+ {
+ set_syntax_error (_("shift operator expected"));
+ return FALSE;
+ }
+
+ kind = aarch64_get_operand_modifier (shift_op);
+
+ if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
+ {
+ set_syntax_error (_("invalid use of 'MSL'"));
+ return FALSE;
+ }
+
+ switch (mode)
+ {
+ case SHIFTED_LOGIC_IMM:
+ if (aarch64_extend_operator_p (kind) == TRUE)
+ {
+ set_syntax_error (_("extending shift is not permitted"));
+ return FALSE;
+ }
+ break;
+
+ case SHIFTED_ARITH_IMM:
+ if (kind == AARCH64_MOD_ROR)
+ {
+ set_syntax_error (_("'ROR' shift is not permitted"));
+ return FALSE;
+ }
+ break;
+
+ case SHIFTED_LSL:
+ if (kind != AARCH64_MOD_LSL)
+ {
+ set_syntax_error (_("only 'LSL' shift is permitted"));
+ return FALSE;
+ }
+ break;
+
+ case SHIFTED_REG_OFFSET:
+ if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
+ && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX)
+ {
+ set_fatal_syntax_error
+ (_("invalid shift for the register offset addressing mode"));
+ return FALSE;
+ }
+ break;
+
+ case SHIFTED_LSL_MSL:
+ if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
+ {
+ set_syntax_error (_("invalid shift operator"));
+ return FALSE;
+ }
+ break;
+
+ default:
+ abort ();
+ }
+
+ /* Whitespace can appear here if the next thing is a bare digit. */
+ skip_whitespace (p);
+
+ /* Parse shift amount. */
+ exp_has_prefix = 0;
+ if (mode == SHIFTED_REG_OFFSET && *p == ']')
+ exp.X_op = O_absent;
+ else
+ {
+ if (is_immediate_prefix (*p))
+ {
+ p++;
+ exp_has_prefix = 1;
+ }
+ my_get_expression (&exp, &p, GE_NO_PREFIX, 0);
+ }
+ if (exp.X_op == O_absent)
+ {
+ if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
+ {
+ set_syntax_error (_("missing shift amount"));
+ return FALSE;
+ }
+ operand->shifter.amount = 0;
+ }
+ else if (exp.X_op != O_constant)
+ {
+ set_syntax_error (_("constant shift amount required"));
+ return FALSE;
+ }
+ else if (exp.X_add_number < 0 || exp.X_add_number > 63)
+ {
+ set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
+ return FALSE;
+ }
+ else
+ {
+ operand->shifter.amount = exp.X_add_number;
+ operand->shifter.amount_present = 1;
+ }
+
+ operand->shifter.operator_present = 1;
+ operand->shifter.kind = kind;
+
+ *str = p;
+ return TRUE;
+}
+
+/* Parse a <shifter_operand> for a data processing instruction:
+
+ #<immediate>
+ #<immediate>, LSL #imm
+
+ Validation of immediate operands is deferred to md_apply_fix.
+
+ Return TRUE on success; otherwise return FALSE. */
+
+static bfd_boolean
+parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
+ enum parse_shift_mode mode)
+{
+ char *p;
+
+ if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
+ return FALSE;
+
+ p = *str;
+
+ /* Accept an immediate expression. */
+ if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
+ return FALSE;
+
+ /* Accept optional LSL for arithmetic immediate values. */
+ if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
+ if (! parse_shift (&p, operand, SHIFTED_LSL))
+ return FALSE;
+
+ /* Not accept any shifter for logical immediate values. */
+ if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
+ && parse_shift (&p, operand, mode))
+ {
+ set_syntax_error (_("unexpected shift operator"));
+ return FALSE;
+ }
+
+ *str = p;
+ return TRUE;
+}
+
+/* Parse a <shifter_operand> for a data processing instruction:
+
+ <Rm>
+ <Rm>, <shift>
+ #<immediate>
+ #<immediate>, LSL #imm
+
+ where <shift> is handled by parse_shift above, and the last two
+ cases are handled by the function above.
+
+ Validation of immediate operands is deferred to md_apply_fix.
+
+ Return TRUE on success; otherwise return FALSE. */
+
+static bfd_boolean
+parse_shifter_operand (char **str, aarch64_opnd_info *operand,
+ enum parse_shift_mode mode)
+{
+ int reg;
+ int isreg32, isregzero;
+ enum aarch64_operand_class opd_class
+ = aarch64_get_operand_class (operand->type);
+
+ if ((reg =
+ aarch64_reg_parse_32_64 (str, 0, 0, &isreg32, &isregzero)) != PARSE_FAIL)
+ {
+ if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
+ {
+ set_syntax_error (_("unexpected register in the immediate operand"));
+ return FALSE;
+ }
+
+ if (!isregzero && reg == REG_SP)
+ {
+ set_syntax_error (BAD_SP);
+ return FALSE;
+ }
+
+ operand->reg.regno = reg;
+ operand->qualifier = isreg32 ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
+
+ /* Accept optional shift operation on register. */
+ if (! skip_past_comma (str))
+ return TRUE;
+
+ if (! parse_shift (str, operand, mode))
+ return FALSE;
+
+ return TRUE;
+ }
+ else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
+ {
+ set_syntax_error
+ (_("integer register expected in the extended/shifted operand "
+ "register"));
+ return FALSE;
+ }
+
+ /* We have a shifted immediate variable. */
+ return parse_shifter_operand_imm (str, operand, mode);
+}
+
+/* Return TRUE on success; return FALSE otherwise. */
+
+static bfd_boolean
+parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
+ enum parse_shift_mode mode)
+{
+ char *p = *str;
+
+ /* Determine if we have the sequence of characters #: or just :
+ coming next. If we do, then we check for a :rello: relocation
+ modifier. If we don't, punt the whole lot to
+ parse_shifter_operand. */
+
+ if ((p[0] == '#' && p[1] == ':') || p[0] == ':')
+ {
+ struct reloc_table_entry *entry;
+
+ if (p[0] == '#')
+ p += 2;
+ else
+ p++;
+ *str = p;
+
+ /* Try to parse a relocation. Anything else is an error. */
+ if (!(entry = find_reloc_table_entry (str)))
+ {
+ set_syntax_error (_("unknown relocation modifier"));
+ return FALSE;
+ }
+
+ if (entry->add_type == 0)
+ {
+ set_syntax_error
+ (_("this relocation modifier is not allowed on this instruction"));
+ return FALSE;
+ }
+
+ /* Save str before we decompose it. */
+ p = *str;
+
+ /* Next, we parse the expression. */
+ if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
+ return FALSE;
+
+ /* Record the relocation type (use the ADD variant here). */
+ inst.reloc.type = entry->add_type;
+ inst.reloc.pc_rel = entry->pc_rel;
+
+ /* If str is empty, we've reached the end, stop here. */
+ if (**str == '\0')
+ return TRUE;
+
+ /* Otherwise, we have a shifted reloc modifier, so rewind to
+ recover the variable name and continue parsing for the shifter. */
+ *str = p;
+ return parse_shifter_operand_imm (str, operand, mode);
+ }
+
+ return parse_shifter_operand (str, operand, mode);
+}
+
+/* Parse all forms of an address expression. Information is written
+ to *OPERAND and/or inst.reloc.
+
+ The A64 instruction set has the following addressing modes:
+
+ Offset
+ [base] // in SIMD ld/st structure
+ [base{,#0}] // in ld/st exclusive
+ [base{,#imm}]
+ [base,Xm{,LSL #imm}]
+ [base,Xm,SXTX {#imm}]
+ [base,Wm,(S|U)XTW {#imm}]
+ Pre-indexed
+ [base,#imm]!
+ Post-indexed
+ [base],#imm
+ [base],Xm // in SIMD ld/st structure
+ PC-relative (literal)
+ label
+ =immediate
+
+ (As a convenience, the notation "=immediate" is permitted in conjunction
+ with the pc-relative literal load instructions to automatically place an
+ immediate value or symbolic address in a nearby literal pool and generate
+ a hidden label which references it.)
+
+ Upon a successful parsing, the address structure in *OPERAND will be
+ filled in the following way:
+
+ .base_regno = <base>
+ .offset.is_reg // 1 if the offset is a register
+ .offset.imm = <imm>
+ .offset.regno = <Rm>
+
+ For different addressing modes defined in the A64 ISA:
+
+ Offset
+ .pcrel=0; .preind=1; .postind=0; .writeback=0
+ Pre-indexed
+ .pcrel=0; .preind=1; .postind=0; .writeback=1
+ Post-indexed
+ .pcrel=0; .preind=0; .postind=1; .writeback=1
+ PC-relative (literal)
+ .pcrel=1; .preind=1; .postind=0; .writeback=0
+
+ The shift/extension information, if any, will be stored in .shifter.
+
+ It is the caller's responsibility to check for addressing modes not
+ supported by the instruction, and to set inst.reloc.type. */
+
+static bfd_boolean
+parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
+ int accept_reg_post_index)
+{
+ char *p = *str;
+ int reg;
+ int isreg32, isregzero;
+ expressionS *exp = &inst.reloc.exp;
+
+ if (! skip_past_char (&p, '['))
+ {
+ /* =immediate or label. */
+ operand->addr.pcrel = 1;
+ operand->addr.preind = 1;
+
+ if (skip_past_char (&p, '='))
+ /* =immediate; need to generate the literal in the liternal pool. */
+ inst.gen_lit_pool = 1;
+
+ if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
+ {
+ set_syntax_error (_("invalid address"));
+ return FALSE;
+ }
+
+ *str = p;
+ return TRUE;
+ }
+
+ /* [ */
+
+ /* Accept SP and reject ZR */
+ reg = aarch64_reg_parse_32_64 (&p, 0, 1, &isreg32, &isregzero);
+ if (reg == PARSE_FAIL || isreg32)
+ {
+ set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
+ return FALSE;
+ }
+ operand->addr.base_regno = reg;
+
+ /* [Xn */
+ if (skip_past_comma (&p))
+ {
+ /* [Xn, */
+ operand->addr.preind = 1;
+
+ /* Reject SP and accept ZR */
+ reg = aarch64_reg_parse_32_64 (&p, 1, 0, &isreg32, &isregzero);
+ if (reg != PARSE_FAIL)
+ {
+ /* [Xn,Rm */
+ operand->addr.offset.regno = reg;
+ operand->addr.offset.is_reg = 1;
+ /* Shifted index. */
+ if (skip_past_comma (&p))
+ {
+ /* [Xn,Rm, */
+ if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
+ /* Use the diagnostics set in parse_shift, so not set new
+ error message here. */
+ return FALSE;
+ }
+ /* We only accept:
+ [base,Xm{,LSL #imm}]
+ [base,Xm,SXTX {#imm}]
+ [base,Wm,(S|U)XTW {#imm}] */
+ if (operand->shifter.kind == AARCH64_MOD_NONE
+ || operand->shifter.kind == AARCH64_MOD_LSL
+ || operand->shifter.kind == AARCH64_MOD_SXTX)
+ {
+ if (isreg32)
+ {
+ set_syntax_error (_("invalid use of 32-bit register offset"));
+ return FALSE;
+ }
+ }
+ else if (!isreg32)
+ {
+ set_syntax_error (_("invalid use of 64-bit register offset"));
+ return FALSE;
+ }
+ }
+ else
+ {
+ /* [Xn,#:<reloc_op>:<symbol> */
+ skip_past_char (&p, '#');
+ if (reloc && skip_past_char (&p, ':'))
+ {
+ struct reloc_table_entry *entry;
+
+ /* Try to parse a relocation modifier. Anything else is
+ an error. */
+ if (!(entry = find_reloc_table_entry (&p)))
+ {
+ set_syntax_error (_("unknown relocation modifier"));
+ return FALSE;
+ }
+
+ if (entry->ldst_type == 0)
+ {
+ set_syntax_error
+ (_("this relocation modifier is not allowed on this "
+ "instruction"));
+ return FALSE;
+ }
+
+ /* [Xn,#:<reloc_op>: */
+ /* We now have the group relocation table entry corresponding to
+ the name in the assembler source. Next, we parse the
+ expression. */
+ if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
+ {
+ set_syntax_error (_("invalid relocation expression"));
+ return FALSE;
+ }
+
+ /* [Xn,#:<reloc_op>:<expr> */
+ /* Record the load/store relocation type. */
+ inst.reloc.type = entry->ldst_type;
+ inst.reloc.pc_rel = entry->pc_rel;
+ }
+ else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
+ {
+ set_syntax_error (_("invalid expression in the address"));
+ return FALSE;
+ }
+ /* [Xn,<expr> */
+ }
+ }
+
+ if (! skip_past_char (&p, ']'))
+ {
+ set_syntax_error (_("']' expected"));
+ return FALSE;
+ }
+
+ if (skip_past_char (&p, '!'))
+ {
+ if (operand->addr.preind && operand->addr.offset.is_reg)
+ {
+ set_syntax_error (_("register offset not allowed in pre-indexed "
+ "addressing mode"));
+ return FALSE;
+ }
+ /* [Xn]! */
+ operand->addr.writeback = 1;
+ }
+ else if (skip_past_comma (&p))
+ {
+ /* [Xn], */
+ operand->addr.postind = 1;
+ operand->addr.writeback = 1;
+
+ if (operand->addr.preind)
+ {
+ set_syntax_error (_("cannot combine pre- and post-indexing"));
+ return FALSE;
+ }
+
+ if (accept_reg_post_index
+ && (reg = aarch64_reg_parse_32_64 (&p, 1, 1, &isreg32,
+ &isregzero)) != PARSE_FAIL)
+ {
+ /* [Xn],Xm */
+ if (isreg32)
+ {
+ set_syntax_error (_("invalid 32-bit register offset"));
+ return FALSE;
+ }
+ operand->addr.offset.regno = reg;
+ operand->addr.offset.is_reg = 1;
+ }
+ else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
+ {
+ /* [Xn],#expr */
+ set_syntax_error (_("invalid expression in the address"));
+ return FALSE;
+ }
+ }
+
+ /* If at this point neither .preind nor .postind is set, we have a
+ bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
+ if (operand->addr.preind == 0 && operand->addr.postind == 0)
+ {
+ if (operand->addr.writeback)
+ {
+ /* Reject [Rn]! */
+ set_syntax_error (_("missing offset in the pre-indexed address"));
+ return FALSE;
+ }
+ operand->addr.preind = 1;
+ inst.reloc.exp.X_op = O_constant;
+ inst.reloc.exp.X_add_number = 0;
+ }
+
+ *str = p;
+ return TRUE;
+}
+
+/* Return TRUE on success; otherwise return FALSE. */
+static bfd_boolean
+parse_address (char **str, aarch64_opnd_info *operand,
+ int accept_reg_post_index)
+{
+ return parse_address_main (str, operand, 0, accept_reg_post_index);
+}
+
+/* Return TRUE on success; otherwise return FALSE. */
+static bfd_boolean
+parse_address_reloc (char **str, aarch64_opnd_info *operand)
+{
+ return parse_address_main (str, operand, 1, 0);
+}
+
+/* Parse an operand for a MOVZ, MOVN or MOVK instruction.
+ Return TRUE on success; otherwise return FALSE. */
+static bfd_boolean
+parse_half (char **str, int *internal_fixup_p)
+{
+ char *p, *saved;
+ int dummy;
+
+ p = *str;
+ skip_past_char (&p, '#');
+
+ gas_assert (internal_fixup_p);
+ *internal_fixup_p = 0;
+
+ if (*p == ':')
+ {
+ struct reloc_table_entry *entry;
+
+ /* Try to parse a relocation. Anything else is an error. */
+ ++p;
+ if (!(entry = find_reloc_table_entry (&p)))
+ {
+ set_syntax_error (_("unknown relocation modifier"));
+ return FALSE;
+ }
+
+ if (entry->movw_type == 0)
+ {
+ set_syntax_error
+ (_("this relocation modifier is not allowed on this instruction"));
+ return FALSE;
+ }
+
+ inst.reloc.type = entry->movw_type;
+ }
+ else
+ *internal_fixup_p = 1;
+
+ /* Avoid parsing a register as a general symbol. */
+ saved = p;
+ if (aarch64_reg_parse_32_64 (&p, 0, 0, &dummy, &dummy) != PARSE_FAIL)
+ return FALSE;
+ p = saved;
+
+ if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
+ return FALSE;
+
+ *str = p;
+ return TRUE;
+}
+
+/* Parse an operand for an ADRP instruction:
+ ADRP <Xd>, <label>
+ Return TRUE on success; otherwise return FALSE. */
+
+static bfd_boolean
+parse_adrp (char **str)
+{
+ char *p;
+
+ p = *str;
+ if (*p == ':')
+ {
+ struct reloc_table_entry *entry;
+
+ /* Try to parse a relocation. Anything else is an error. */
+ ++p;
+ if (!(entry = find_reloc_table_entry (&p)))
+ {
+ set_syntax_error (_("unknown relocation modifier"));
+ return FALSE;
+ }
+
+ if (entry->adrp_type == 0)
+ {
+ set_syntax_error
+ (_("this relocation modifier is not allowed on this instruction"));
+ return FALSE;
+ }
+
+ inst.reloc.type = entry->adrp_type;
+ }
+ else
+ inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
+
+ inst.reloc.pc_rel = 1;
+
+ if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
+ return FALSE;
+
+ *str = p;
+ return TRUE;
+}
+
+/* Miscellaneous. */
+
+/* Parse an option for a preload instruction. Returns the encoding for the
+ option, or PARSE_FAIL. */
+
+static int
+parse_pldop (char **str)
+{
+ char *p, *q;
+ const struct aarch64_name_value_pair *o;
+
+ p = q = *str;
+ while (ISALNUM (*q))
+ q++;
+
+ o = hash_find_n (aarch64_pldop_hsh, p, q - p);
+ if (!o)
+ return PARSE_FAIL;
+
+ *str = q;
+ return o->value;
+}
+
+/* Parse an option for a barrier instruction. Returns the encoding for the
+ option, or PARSE_FAIL. */
+
+static int
+parse_barrier (char **str)
+{
+ char *p, *q;
+ const asm_barrier_opt *o;
+
+ p = q = *str;
+ while (ISALPHA (*q))
+ q++;
+
+ o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p);
+ if (!o)
+ return PARSE_FAIL;
+
+ *str = q;
+ return o->value;
+}
+
+/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
+ Returns the encoding for the option, or PARSE_FAIL.
+
+ If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
+ implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
+
+static int
+parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
+{
+ char *p, *q;
+ char buf[32];
+ const struct aarch64_name_value_pair *o;
+ int value;
+
+ p = buf;
+ for (q = *str; ISALNUM (*q) || *q == '_'; q++)
+ if (p < buf + 31)
+ *p++ = TOLOWER (*q);
+ *p = '\0';
+ /* Assert that BUF be large enough. */
+ gas_assert (p - buf == q - *str);
+
+ o = hash_find (sys_regs, buf);
+ if (!o)
+ {
+ if (!imple_defined_p)
+ return PARSE_FAIL;
+ else
+ {
+ /* Parse S3_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
+ registers. */
+ unsigned int op0, op1, cn, cm, op2;
+ if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
+ return PARSE_FAIL;
+ /* Register access is encoded as follows:
+ op0 op1 CRn CRm op2
+ 11 xxx 1x11 xxxx xxx. */
+ if (op0 != 3 || op1 > 7 || (cn | 0x4) != 0xf || cm > 15 || op2 > 7)
+ return PARSE_FAIL;
+ value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
+ }
+ }
+ else
+ value = o->value;
+
+ *str = q;
+ return value;
+}
+
+/* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
+ for the option, or NULL. */
+
+static const aarch64_sys_ins_reg *
+parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
+{
+ char *p, *q;
+ char buf[32];
+ const aarch64_sys_ins_reg *o;
+
+ p = buf;
+ for (q = *str; ISALNUM (*q) || *q == '_'; q++)
+ if (p < buf + 31)
+ *p++ = TOLOWER (*q);
+ *p = '\0';
+
+ o = hash_find (sys_ins_regs, buf);
+ if (!o)
+ return NULL;
+
+ *str = q;
+ return o;
+}
+\f
+#define po_char_or_fail(chr) do { \
+ if (! skip_past_char (&str, chr)) \
+ goto failure; \
+} while (0)
+
+#define po_reg_or_fail(regtype) do { \
+ val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
+ if (val == PARSE_FAIL) \
+ { \
+ set_default_error (); \
+ goto failure; \
+ } \
+ } while (0)
+
+#define po_int_reg_or_fail(reject_sp, reject_rz) do { \
+ val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
+ &isreg32, &isregzero); \
+ if (val == PARSE_FAIL) \
+ { \
+ set_default_error (); \
+ goto failure; \
+ } \
+ info->reg.regno = val; \
+ if (isreg32) \
+ info->qualifier = AARCH64_OPND_QLF_W; \
+ else \
+ info->qualifier = AARCH64_OPND_QLF_X; \
+ } while (0)
+
+#define po_imm_nc_or_fail() do { \
+ if (! parse_constant_immediate (&str, &val)) \
+ goto failure; \
+ } while (0)
+
+#define po_imm_or_fail(min, max) do { \
+ if (! parse_constant_immediate (&str, &val)) \
+ goto failure; \
+ if (val < min || val > max) \
+ { \
+ set_fatal_syntax_error (_("immediate value out of range "\
+#min " to "#max)); \
+ goto failure; \
+ } \
+ } while (0)
+
+#define po_misc_or_fail(expr) do { \
+ if (!expr) \
+ goto failure; \
+ } while (0)
+\f
+/* encode the 12-bit imm field of Add/sub immediate */
+static inline uint32_t
+encode_addsub_imm (uint32_t imm)
+{
+ return imm << 10;
+}
+
+/* encode the shift amount field of Add/sub immediate */
+static inline uint32_t
+encode_addsub_imm_shift_amount (uint32_t cnt)
+{
+ return cnt << 22;
+}
+
+
+/* encode the imm field of Adr instruction */
+static inline uint32_t
+encode_adr_imm (uint32_t imm)
+{
+ return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */
+ | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
+}
+
+/* encode the immediate field of Move wide immediate */
+static inline uint32_t
+encode_movw_imm (uint32_t imm)
+{
+ return imm << 5;
+}
+
+/* encode the 26-bit offset of unconditional branch */
+static inline uint32_t
+encode_branch_ofs_26 (uint32_t ofs)
+{
+ return ofs & ((1 << 26) - 1);
+}
+
+/* encode the 19-bit offset of conditional branch and compare & branch */
+static inline uint32_t
+encode_cond_branch_ofs_19 (uint32_t ofs)
+{
+ return (ofs & ((1 << 19) - 1)) << 5;
+}
+
+/* encode the 19-bit offset of ld literal */
+static inline uint32_t
+encode_ld_lit_ofs_19 (uint32_t ofs)
+{
+ return (ofs & ((1 << 19) - 1)) << 5;
+}
+
+/* Encode the 14-bit offset of test & branch. */
+static inline uint32_t
+encode_tst_branch_ofs_14 (uint32_t ofs)
+{
+ return (ofs & ((1 << 14) - 1)) << 5;
+}
+
+/* Encode the 16-bit imm field of svc/hvc/smc. */
+static inline uint32_t
+encode_svc_imm (uint32_t imm)
+{
+ return imm << 5;
+}
+
+/* Reencode add(s) to sub(s), or sub(s) to add(s). */
+static inline uint32_t
+reencode_addsub_switch_add_sub (uint32_t opcode)
+{
+ return opcode ^ (1 << 30);
+}
+
+static inline uint32_t
+reencode_movzn_to_movz (uint32_t opcode)
+{
+ return opcode | (1 << 30);
+}
+
+static inline uint32_t
+reencode_movzn_to_movn (uint32_t opcode)
+{
+ return opcode & ~(1 << 30);
+}
+
+/* Overall per-instruction processing. */
+
+/* We need to be able to fix up arbitrary expressions in some statements.
+ This is so that we can handle symbols that are an arbitrary distance from
+ the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
+ which returns part of an address in a form which will be valid for
+ a data instruction. We do this by pushing the expression into a symbol
+ in the expr_section, and creating a fix for that. */
+
+static fixS *
+fix_new_aarch64 (fragS * frag,
+ int where,
+ short int size, expressionS * exp, int pc_rel, int reloc)
+{
+ fixS *new_fix;
+
+ switch (exp->X_op)
+ {
+ case O_constant:
+ case O_symbol:
+ case O_add:
+ case O_subtract:
+ new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
+ break;
+
+ default:
+ new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
+ pc_rel, reloc);
+ break;
+ }
+ return new_fix;
+}
+\f
+/* Diagnostics on operands errors. */
+
+/* By default, output one-line error message only.
+ Enable the verbose error message by -merror-verbose. */
+static int verbose_error_p = 0;
+
+#ifdef DEBUG_AARCH64
+/* N.B. this is only for the purpose of debugging. */
+const char* operand_mismatch_kind_names[] =
+{
+ "AARCH64_OPDE_NIL",
+ "AARCH64_OPDE_RECOVERABLE",
+ "AARCH64_OPDE_SYNTAX_ERROR",
+ "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
+ "AARCH64_OPDE_INVALID_VARIANT",
+ "AARCH64_OPDE_OUT_OF_RANGE",
+ "AARCH64_OPDE_UNALIGNED",
+ "AARCH64_OPDE_REG_LIST",
+ "AARCH64_OPDE_OTHER_ERROR",
+};
+#endif /* DEBUG_AARCH64 */
+
+/* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
+
+ When multiple errors of different kinds are found in the same assembly
+ line, only the error of the highest severity will be picked up for
+ issuing the diagnostics. */
+
+static inline bfd_boolean
+operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
+ enum aarch64_operand_error_kind rhs)
+{
+ gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL);
+ gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE);
+ gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
+ gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
+ gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
+ gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
+ gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
+ gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
+ return lhs > rhs;
+}
+
+/* Helper routine to get the mnemonic name from the assembly instruction
+ line; should only be called for the diagnosis purpose, as there is
+ string copy operation involved, which may affect the runtime
+ performance if used in elsewhere. */
+
+static const char*
+get_mnemonic_name (const char *str)
+{
+ static char mnemonic[32];
+ char *ptr;
+
+ /* Get the first 15 bytes and assume that the full name is included. */
+ strncpy (mnemonic, str, 31);
+ mnemonic[31] = '\0';
+
+ /* Scan up to the end of the mnemonic, which must end in white space,
+ '.', or end of string. */
+ for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr)
+ ;
+
+ *ptr = '\0';
+
+ /* Append '...' to the truncated long name. */
+ if (ptr - mnemonic == 31)
+ mnemonic[28] = mnemonic[29] = mnemonic[30] = '.';
+
+ return mnemonic;
+}
+
+static void
+reset_aarch64_instruction (aarch64_instruction *instruction)
+{
+ memset (instruction, '\0', sizeof (aarch64_instruction));
+ instruction->reloc.type = BFD_RELOC_UNUSED;
+}
+
+/* Data strutures storing one user error in the assembly code related to
+ operands. */
+
+struct operand_error_record
+{
+ const aarch64_opcode *opcode;
+ aarch64_operand_error detail;
+ struct operand_error_record *next;
+};
+
+typedef struct operand_error_record operand_error_record;
+
+struct operand_errors
+{
+ operand_error_record *head;
+ operand_error_record *tail;
+};
+
+typedef struct operand_errors operand_errors;
+
+/* Top-level data structure reporting user errors for the current line of
+ the assembly code.
+ The way md_assemble works is that all opcodes sharing the same mnemonic
+ name are iterated to find a match to the assembly line. In this data
+ structure, each of the such opcodes will have one operand_error_record
+ allocated and inserted. In other words, excessive errors related with
+ a single opcode are disregarded. */
+operand_errors operand_error_report;
+
+/* Free record nodes. */
+static operand_error_record *free_opnd_error_record_nodes = NULL;
+
+/* Initialize the data structure that stores the operand mismatch
+ information on assembling one line of the assembly code. */
+static void
+init_operand_error_report (void)
+{
+ if (operand_error_report.head != NULL)
+ {
+ gas_assert (operand_error_report.tail != NULL);
+ operand_error_report.tail->next = free_opnd_error_record_nodes;
+ free_opnd_error_record_nodes = operand_error_report.head;
+ operand_error_report.head = NULL;
+ operand_error_report.tail = NULL;
+ return;
+ }
+ gas_assert (operand_error_report.tail == NULL);
+}
+
+/* Return TRUE if some operand error has been recorded during the
+ parsing of the current assembly line using the opcode *OPCODE;
+ otherwise return FALSE. */
+static inline bfd_boolean
+opcode_has_operand_error_p (const aarch64_opcode *opcode)
+{
+ operand_error_record *record = operand_error_report.head;
+ return record && record->opcode == opcode;
+}
+
+/* Add the error record *NEW_RECORD to operand_error_report. The record's
+ OPCODE field is initialized with OPCODE.
+ N.B. only one record for each opcode, i.e. the maximum of one error is
+ recorded for each instruction template. */
+
+static void
+add_operand_error_record (const operand_error_record* new_record)
+{
+ const aarch64_opcode *opcode = new_record->opcode;
+ operand_error_record* record = operand_error_report.head;
+
+ /* The record may have been created for this opcode. If not, we need
+ to prepare one. */
+ if (! opcode_has_operand_error_p (opcode))
+ {
+ /* Get one empty record. */
+ if (free_opnd_error_record_nodes == NULL)
+ {
+ record = xmalloc (sizeof (operand_error_record));
+ if (record == NULL)
+ abort ();
+ }
+ else
+ {
+ record = free_opnd_error_record_nodes;
+ free_opnd_error_record_nodes = record->next;
+ }
+ record->opcode = opcode;
+ /* Insert at the head. */
+ record->next = operand_error_report.head;
+ operand_error_report.head = record;
+ if (operand_error_report.tail == NULL)
+ operand_error_report.tail = record;
+ }
+ else if (record->detail.kind != AARCH64_OPDE_NIL
+ && record->detail.index <= new_record->detail.index
+ && operand_error_higher_severity_p (record->detail.kind,
+ new_record->detail.kind))
+ {
+ /* In the case of multiple errors found on operands related with a
+ single opcode, only record the error of the leftmost operand and
+ only if the error is of higher severity. */
+ DEBUG_TRACE ("error %s on operand %d not added to the report due to"
+ " the existing error %s on operand %d",
+ operand_mismatch_kind_names[new_record->detail.kind],
+ new_record->detail.index,
+ operand_mismatch_kind_names[record->detail.kind],
+ record->detail.index);
+ return;
+ }
+
+ record->detail = new_record->detail;
+}
+
+static inline void
+record_operand_error_info (const aarch64_opcode *opcode,
+ aarch64_operand_error *error_info)
+{
+ operand_error_record record;
+ record.opcode = opcode;
+ record.detail = *error_info;
+ add_operand_error_record (&record);
+}
+
+/* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
+ error message *ERROR, for operand IDX (count from 0). */
+
+static void
+record_operand_error (const aarch64_opcode *opcode, int idx,
+ enum aarch64_operand_error_kind kind,
+ const char* error)
+{
+ aarch64_operand_error info;
+ memset(&info, 0, sizeof (info));
+ info.index = idx;
+ info.kind = kind;
+ info.error = error;
+ record_operand_error_info (opcode, &info);
+}
+
+static void
+record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
+ enum aarch64_operand_error_kind kind,
+ const char* error, const int *extra_data)
+{
+ aarch64_operand_error info;
+ info.index = idx;
+ info.kind = kind;
+ info.error = error;
+ info.data[0] = extra_data[0];
+ info.data[1] = extra_data[1];
+ info.data[2] = extra_data[2];
+ record_operand_error_info (opcode, &info);
+}
+
+static void
+record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx,
+ const char* error, int lower_bound,
+ int upper_bound)
+{
+ int data[3] = {lower_bound, upper_bound, 0};
+ record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE,
+ error, data);
+}
+
+/* Remove the operand error record for *OPCODE. */
+static void ATTRIBUTE_UNUSED
+remove_operand_error_record (const aarch64_opcode *opcode)
+{
+ if (opcode_has_operand_error_p (opcode))
+ {
+ operand_error_record* record = operand_error_report.head;
+ gas_assert (record != NULL && operand_error_report.tail != NULL);
+ operand_error_report.head = record->next;
+ record->next = free_opnd_error_record_nodes;
+ free_opnd_error_record_nodes = record;
+ if (operand_error_report.head == NULL)
+ {
+ gas_assert (operand_error_report.tail == record);
+ operand_error_report.tail = NULL;
+ }
+ }
+}
+
+/* Given the instruction in *INSTR, return the index of the best matched
+ qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
+
+ Return -1 if there is no qualifier sequence; return the first match
+ if there is multiple matches found. */
+
+static int
+find_best_match (const aarch64_inst *instr,
+ const aarch64_opnd_qualifier_seq_t *qualifiers_list)
+{
+ int i, num_opnds, max_num_matched, idx;
+
+ num_opnds = aarch64_num_of_operands (instr->opcode);
+ if (num_opnds == 0)
+ {
+ DEBUG_TRACE ("no operand");
+ return -1;
+ }
+
+ max_num_matched = 0;
+ idx = -1;
+
+ /* For each pattern. */
+ for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
+ {
+ int j, num_matched;
+ const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
+
+ /* Most opcodes has much fewer patterns in the list. */
+ if (empty_qualifier_sequence_p (qualifiers) == TRUE)
+ {
+ DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
+ if (i != 0 && idx == -1)
+ /* If nothing has been matched, return the 1st sequence. */
+ idx = 0;
+ break;
+ }
+
+ for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers)
+ if (*qualifiers == instr->operands[j].qualifier)
+ ++num_matched;
+
+ if (num_matched > max_num_matched)
+ {
+ max_num_matched = num_matched;
+ idx = i;
+ }
+ }
+
+ DEBUG_TRACE ("return with %d", idx);
+ return idx;
+}
+
+/* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
+ corresponding operands in *INSTR. */
+
+static inline void
+assign_qualifier_sequence (aarch64_inst *instr,
+ const aarch64_opnd_qualifier_t *qualifiers)
+{
+ int i = 0;
+ int num_opnds = aarch64_num_of_operands (instr->opcode);
+ gas_assert (num_opnds);
+ for (i = 0; i < num_opnds; ++i, ++qualifiers)
+ instr->operands[i].qualifier = *qualifiers;
+}
+
+/* Print operands for the diagnosis purpose. */
+
+static void
+print_operands (char *buf, const aarch64_opcode *opcode,
+ const aarch64_opnd_info *opnds)
+{
+ int i;
+
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ {
+ const size_t size = 128;
+ char str[size];
+
+ /* We regard the opcode operand info more, however we also look into
+ the inst->operands to support the disassembling of the optional
+ operand.
+ The two operand code should be the same in all cases, apart from
+ when the operand can be optional. */
+ if (opcode->operands[i] == AARCH64_OPND_NIL
+ || opnds[i].type == AARCH64_OPND_NIL)
+ break;
+
+ /* Generate the operand string in STR. */
+ aarch64_print_operand (str, size, 0, opcode, opnds, i, NULL, NULL);
+
+ /* Delimiter. */
+ if (str[0] != '\0')
+ strcat (buf, i == 0 ? " " : ",");
+
+ /* Append the operand string. */
+ strcat (buf, str);
+ }
+}
+
+/* Send to stderr a string as information. */
+
+static void
+output_info (const char *format, ...)
+{
+ char *file;
+ unsigned int line;
+ va_list args;
+
+ as_where (&file, &line);
+ if (file)
+ {
+ if (line != 0)
+ fprintf (stderr, "%s:%u: ", file, line);
+ else
+ fprintf (stderr, "%s: ", file);
+ }
+ fprintf (stderr, _("Info: "));
+ va_start (args, format);
+ vfprintf (stderr, format, args);
+ va_end (args);
+ (void) putc ('\n', stderr);
+}
+
+/* Output one operand error record. */
+
+static void
+output_operand_error_record (const operand_error_record *record, char *str)
+{
+ int idx = record->detail.index;
+ const aarch64_opcode *opcode = record->opcode;
+ enum aarch64_opnd opd_code = (idx != -1 ? opcode->operands[idx]
+ : AARCH64_OPND_NIL);
+ const aarch64_operand_error *detail = &record->detail;
+
+ switch (detail->kind)
+ {
+ case AARCH64_OPDE_NIL:
+ gas_assert (0);
+ break;
+
+ case AARCH64_OPDE_SYNTAX_ERROR:
+ case AARCH64_OPDE_RECOVERABLE:
+ case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
+ case AARCH64_OPDE_OTHER_ERROR:
+ gas_assert (idx >= 0);
+ /* Use the prepared error message if there is, otherwise use the
+ operand description string to describe the error. */
+ if (detail->error != NULL)
+ {
+ if (detail->index == -1)
+ as_bad (_("%s -- `%s'"), detail->error, str);
+ else
+ as_bad (_("%s at operand %d -- `%s'"),
+ detail->error, detail->index + 1, str);
+ }
+ else
+ as_bad (_("operand %d should be %s -- `%s'"), idx + 1,
+ aarch64_get_operand_desc (opd_code), str);
+ break;
+
+ case AARCH64_OPDE_INVALID_VARIANT:
+ as_bad (_("operand mismatch -- `%s'"), str);
+ if (verbose_error_p)
+ {
+ /* We will try to correct the erroneous instruction and also provide
+ more information e.g. all other valid variants.
+
+ The string representation of the corrected instruction and other
+ valid variants are generated by
+
+ 1) obtaining the intermediate representation of the erroneous
+ instruction;
+ 2) manipulating the IR, e.g. replacing the operand qualifier;
+ 3) printing out the instruction by calling the printer functions
+ shared with the disassembler.
+
+ The limitation of this method is that the exact input assembly
+ line cannot be accurately reproduced in some cases, for example an
+ optional operand present in the actual assembly line will be
+ omitted in the output; likewise for the optional syntax rules,
+ e.g. the # before the immediate. Another limitation is that the
+ assembly symbols and relocation operations in the assembly line
+ currently cannot be printed out in the error report. Last but not
+ least, when there is other error(s) co-exist with this error, the
+ 'corrected' instruction may be still incorrect, e.g. given
+ 'ldnp h0,h1,[x0,#6]!'
+ this diagnosis will provide the version:
+ 'ldnp s0,s1,[x0,#6]!'
+ which is still not right. */
+ size_t len = strlen (get_mnemonic_name (str));
+ int i, qlf_idx;
+ bfd_boolean result;
+ const size_t size = 2048;
+ char buf[size];
+ aarch64_inst *inst_base = &inst.base;
+ const aarch64_opnd_qualifier_seq_t *qualifiers_list;
+
+ /* Init inst. */
+ reset_aarch64_instruction (&inst);
+ inst_base->opcode = opcode;
+
+ /* Reset the error report so that there is no side effect on the
+ following operand parsing. */
+ init_operand_error_report ();
+
+ /* Fill inst. */
+ result = parse_operands (str + len, opcode)
+ && programmer_friendly_fixup (&inst);
+ gas_assert (result);
+ result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
+ NULL, NULL);
+ gas_assert (!result);
+
+ /* Find the most matched qualifier sequence. */
+ qlf_idx = find_best_match (inst_base, opcode->qualifiers_list);
+ gas_assert (qlf_idx > -1);
+
+ /* Assign the qualifiers. */
+ assign_qualifier_sequence (inst_base,
+ opcode->qualifiers_list[qlf_idx]);
+
+ /* Print the hint. */
+ output_info (_(" did you mean this?"));
+ snprintf (buf, size, "\t%s", get_mnemonic_name (str));
+ print_operands (buf, opcode, inst_base->operands);
+ output_info (_(" %s"), buf);
+
+ /* Print out other variant(s) if there is any. */
+ if (qlf_idx != 0 ||
+ !empty_qualifier_sequence_p (opcode->qualifiers_list[1]))
+ output_info (_(" other valid variant(s):"));
+
+ /* For each pattern. */
+ qualifiers_list = opcode->qualifiers_list;
+ for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
+ {
+ /* Most opcodes has much fewer patterns in the list.
+ First NIL qualifier indicates the end in the list. */
+ if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
+ break;
+
+ if (i != qlf_idx)
+ {
+ /* Mnemonics name. */
+ snprintf (buf, size, "\t%s", get_mnemonic_name (str));
+
+ /* Assign the qualifiers. */
+ assign_qualifier_sequence (inst_base, *qualifiers_list);
+
+ /* Print instruction. */
+ print_operands (buf, opcode, inst_base->operands);
+
+ output_info (_(" %s"), buf);
+ }
+ }
+ }
+ break;
+
+ case AARCH64_OPDE_OUT_OF_RANGE:
+ as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
+ detail->error ? detail->error : _("immediate value"),
+ detail->data[0], detail->data[1], detail->index + 1, str);
+ break;
+
+ case AARCH64_OPDE_REG_LIST:
+ if (detail->data[0] == 1)
+ as_bad (_("invalid number of registers in the list; "
+ "only 1 register is expected at operand %d -- `%s'"),
+ detail->index + 1, str);
+ else
+ as_bad (_("invalid number of registers in the list; "
+ "%d registers are expected at operand %d -- `%s'"),
+ detail->data[0], detail->index + 1, str);
+ break;
+
+ case AARCH64_OPDE_UNALIGNED:
+ as_bad (_("immediate value should be a multiple of "
+ "%d at operand %d -- `%s'"),
+ detail->data[0], detail->index + 1, str);
+ break;
+
+ default:
+ gas_assert (0);
+ break;
+ }
+}
+
+/* Process and output the error message about the operand mismatching.
+
+ When this function is called, the operand error information had
+ been collected for an assembly line and there will be multiple
+ errors in the case of mulitple instruction templates; output the
+ error message that most closely describes the problem. */
+
+static void
+output_operand_error_report (char *str)
+{
+ int largest_error_pos;
+ const char *msg = NULL;
+ enum aarch64_operand_error_kind kind;
+ operand_error_record *curr;
+ operand_error_record *head = operand_error_report.head;
+ operand_error_record *record = NULL;
+
+ /* No error to report. */
+ if (head == NULL)
+ return;
+
+ gas_assert (head != NULL && operand_error_report.tail != NULL);
+
+ /* Only one error. */
+ if (head == operand_error_report.tail)
+ {
+ DEBUG_TRACE ("single opcode entry with error kind: %s",
+ operand_mismatch_kind_names[head->detail.kind]);
+ output_operand_error_record (head, str);
+ return;
+ }
+
+ /* Find the error kind of the highest severity. */
+ DEBUG_TRACE ("multiple opcode entres with error kind");
+ kind = AARCH64_OPDE_NIL;
+ for (curr = head; curr != NULL; curr = curr->next)
+ {
+ gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
+ DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
+ if (operand_error_higher_severity_p (curr->detail.kind, kind))
+ kind = curr->detail.kind;
+ }
+ gas_assert (kind != AARCH64_OPDE_NIL);
+
+ /* Pick up one of errors of KIND to report. */
+ largest_error_pos = -2; /* Index can be -1 which means unknown index. */
+ for (curr = head; curr != NULL; curr = curr->next)
+ {
+ if (curr->detail.kind != kind)
+ continue;
+ /* If there are multiple errors, pick up the one with the highest
+ mismatching operand index. In the case of multiple errors with
+ the equally highest operand index, pick up the first one or the
+ first one with non-NULL error message. */
+ if (curr->detail.index > largest_error_pos
+ || (curr->detail.index == largest_error_pos && msg == NULL
+ && curr->detail.error != NULL))
+ {
+ largest_error_pos = curr->detail.index;
+ record = curr;
+ msg = record->detail.error;
+ }
+ }
+
+ gas_assert (largest_error_pos != -2 && record != NULL);
+ DEBUG_TRACE ("Pick up error kind %s to report",
+ operand_mismatch_kind_names[record->detail.kind]);
+
+ /* Output. */
+ output_operand_error_record (record, str);
+}
+\f
+/* Write an AARCH64 instruction to buf - always little-endian. */
+static void
+put_aarch64_insn (char *buf, uint32_t insn)
+{
+ unsigned char *where = (unsigned char *) buf;
+ where[0] = insn;
+ where[1] = insn >> 8;
+ where[2] = insn >> 16;
+ where[3] = insn >> 24;
+}
+
+static uint32_t
+get_aarch64_insn (char *buf)
+{
+ unsigned char *where = (unsigned char *) buf;
+ uint32_t result;
+ result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
+ return result;
+}
+
+static void
+output_inst (struct aarch64_inst *new_inst)
+{
+ char *to = NULL;
+
+ to = frag_more (INSN_SIZE);
+
+ frag_now->tc_frag_data.recorded = 1;
+
+ put_aarch64_insn (to, inst.base.value);
+
+ if (inst.reloc.type != BFD_RELOC_UNUSED)
+ {
+ fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal,
+ INSN_SIZE, &inst.reloc.exp,
+ inst.reloc.pc_rel,
+ inst.reloc.type);
+ DEBUG_TRACE ("Prepared relocation fix up");
+ /* Don't check the addend value against the instruction size,
+ that's the job of our code in md_apply_fix(). */
+ fixp->fx_no_overflow = 1;
+ if (new_inst != NULL)
+ fixp->tc_fix_data.inst = new_inst;
+ if (aarch64_gas_internal_fixup_p ())
+ {
+ gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL);
+ fixp->tc_fix_data.opnd = inst.reloc.opnd;
+ fixp->fx_addnumber = inst.reloc.flags;
+ }
+ }
+
+ dwarf2_emit_insn (INSN_SIZE);
+}
+
+/* Link together opcodes of the same name. */
+
+struct templates
+{
+ aarch64_opcode *opcode;
+ struct templates *next;
+};
+
+typedef struct templates templates;
+
+static templates *
+lookup_mnemonic (const char *start, int len)
+{
+ templates *templ = NULL;
+
+ templ = hash_find_n (aarch64_ops_hsh, start, len);
+ return templ;
+}
+
+/* Subroutine of md_assemble, responsible for looking up the primary
+ opcode from the mnemonic the user wrote. STR points to the
+ beginning of the mnemonic. */
+
+static templates *
+opcode_lookup (char **str)
+{
+ char *end, *base;
+ const aarch64_cond *cond;
+ char condname[16];
+ int len;
+
+ /* Scan up to the end of the mnemonic, which must end in white space,
+ '.', or end of string. */
+ for (base = end = *str; is_part_of_name(*end); end++)
+ if (*end == '.')
+ break;
+
+ if (end == base)
+ return 0;
+
+ inst.cond = COND_ALWAYS;
+
+ /* Handle a possible condition. */
+ if (end[0] == '.')
+ {
+ cond = hash_find_n (aarch64_cond_hsh, end + 1, 2);
+ if (cond)
+ {
+ inst.cond = cond->value;
+ *str = end + 3;
+ }
+ else
+ {
+ *str = end;
+ return 0;
+ }
+ }
+ else
+ *str = end;
+
+ len = end - base;
+
+ if (inst.cond == COND_ALWAYS)
+ {
+ /* Look for unaffixed mnemonic. */
+ return lookup_mnemonic (base, len);
+ }
+ else if (len <= 13)
+ {
+ /* append ".c" to mnemonic if conditional */
+ memcpy (condname, base, len);
+ memcpy (condname + len, ".c", 2);
+ base = condname;
+ len += 2;
+ return lookup_mnemonic (base, len);
+ }
+
+ return NULL;
+}
+
+/* Internal helper routine converting a vector neon_type_el structure
+ *VECTYPE to a corresponding operand qualifier. */
+
+static inline aarch64_opnd_qualifier_t
+vectype_to_qualifier (const struct neon_type_el *vectype)
+{
+ /* Element size in bytes indexed by neon_el_type. */
+ const unsigned char ele_size[5]
+ = {1, 2, 4, 8, 16};
+
+ if (!vectype->defined || vectype->type == NT_invtype)
+ goto vectype_conversion_fail;
+
+ gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
+
+ if (vectype->defined & NTA_HASINDEX)
+ /* Vector element register. */
+ return AARCH64_OPND_QLF_S_B + vectype->type;
+ else
+ {
+ /* Vector register. */
+ int reg_size = ele_size[vectype->type] * vectype->width;
+ unsigned offset;
+ if (reg_size != 16 && reg_size != 8)
+ goto vectype_conversion_fail;
+ /* The conversion is calculated based on the relation of the order of
+ qualifiers to the vector element size and vector register size. */
+ offset = (vectype->type == NT_q)
+ ? 8 : (vectype->type << 1) + (reg_size >> 4);
+ gas_assert (offset <= 8);
+ return AARCH64_OPND_QLF_V_8B + offset;
+ }
+
+vectype_conversion_fail:
+ first_error (_("bad vector arrangement type"));
+ return AARCH64_OPND_QLF_NIL;
+}
+
+/* Process an optional operand that is found omitted from the assembly line.
+ Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
+ instruction's opcode entry while IDX is the index of this omitted operand.
+ */
+
+static void
+process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
+ int idx, aarch64_opnd_info *operand)
+{
+ aarch64_insn default_value = get_optional_operand_default_value (opcode);
+ gas_assert (optional_operand_p (opcode, idx));
+ gas_assert (!operand->present);
+
+ switch (type)
+ {
+ case AARCH64_OPND_Rd:
+ case AARCH64_OPND_Rn:
+ case AARCH64_OPND_Rm:
+ case AARCH64_OPND_Rt:
+ case AARCH64_OPND_Rt2:
+ case AARCH64_OPND_Rs:
+ case AARCH64_OPND_Ra:
+ case AARCH64_OPND_Rt_SYS:
+ case AARCH64_OPND_Rd_SP:
+ case AARCH64_OPND_Rn_SP:
+ case AARCH64_OPND_Fd:
+ case AARCH64_OPND_Fn:
+ case AARCH64_OPND_Fm:
+ case AARCH64_OPND_Fa:
+ case AARCH64_OPND_Ft:
+ case AARCH64_OPND_Ft2:
+ case AARCH64_OPND_Sd:
+ case AARCH64_OPND_Sn:
+ case AARCH64_OPND_Sm:
+ case AARCH64_OPND_Vd:
+ case AARCH64_OPND_Vn:
+ case AARCH64_OPND_Vm:
+ case AARCH64_OPND_VdD1:
+ case AARCH64_OPND_VnD1:
+ operand->reg.regno = default_value;
+ break;
+
+ case AARCH64_OPND_Ed:
+ case AARCH64_OPND_En:
+ case AARCH64_OPND_Em:
+ operand->reglane.regno = default_value;
+ break;
+
+ case AARCH64_OPND_IDX:
+ case AARCH64_OPND_BIT_NUM:
+ case AARCH64_OPND_IMMR:
+ case AARCH64_OPND_IMMS:
+ case AARCH64_OPND_SHLL_IMM:
+ case AARCH64_OPND_IMM_VLSL:
+ case AARCH64_OPND_IMM_VLSR:
+ case AARCH64_OPND_CCMP_IMM:
+ case AARCH64_OPND_FBITS:
+ case AARCH64_OPND_UIMM4:
+ case AARCH64_OPND_UIMM3_OP1:
+ case AARCH64_OPND_UIMM3_OP2:
+ case AARCH64_OPND_IMM:
+ case AARCH64_OPND_WIDTH:
+ case AARCH64_OPND_UIMM7:
+ case AARCH64_OPND_NZCV:
+ operand->imm.value = default_value;
+ break;
+
+ case AARCH64_OPND_EXCEPTION:
+ inst.reloc.type = BFD_RELOC_UNUSED;
+ break;
+
+ case AARCH64_OPND_BARRIER_ISB:
+ operand->barrier = aarch64_barrier_options + default_value;
+
+ default:
+ break;
+ }
+}
+
+/* Process the relocation type for move wide instructions.
+ Return TRUE on success; otherwise return FALSE. */
+
+static bfd_boolean
+process_movw_reloc_info (void)
+{
+ int is32;
+ unsigned shift;
+
+ is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
+
+ if (inst.base.opcode->op == OP_MOVK)
+ switch (inst.reloc.type)
+ {
+ case BFD_RELOC_AARCH64_MOVW_G0_S:
+ case BFD_RELOC_AARCH64_MOVW_G1_S:
+ case BFD_RELOC_AARCH64_MOVW_G2_S:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
+ set_syntax_error
+ (_("the specified relocation type is not allowed for MOVK"));
+ return FALSE;
+ default:
+ break;
+ }
+
+ switch (inst.reloc.type)
+ {
+ case BFD_RELOC_AARCH64_MOVW_G0:
+ case BFD_RELOC_AARCH64_MOVW_G0_S:
+ case BFD_RELOC_AARCH64_MOVW_G0_NC:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+ shift = 0;
+ break;
+ case BFD_RELOC_AARCH64_MOVW_G1:
+ case BFD_RELOC_AARCH64_MOVW_G1_S:
+ case BFD_RELOC_AARCH64_MOVW_G1_NC:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+ shift = 16;
+ break;
+ case BFD_RELOC_AARCH64_MOVW_G2:
+ case BFD_RELOC_AARCH64_MOVW_G2_S:
+ case BFD_RELOC_AARCH64_MOVW_G2_NC:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
+ if (is32)
+ {
+ set_fatal_syntax_error
+ (_("the specified relocation type is not allowed for 32-bit "
+ "register"));
+ return FALSE;
+ }
+ shift = 32;
+ break;
+ case BFD_RELOC_AARCH64_MOVW_G3:
+ if (is32)
+ {
+ set_fatal_syntax_error
+ (_("the specified relocation type is not allowed for 32-bit "
+ "register"));
+ return FALSE;
+ }
+ shift = 48;
+ break;
+ default:
+ /* More cases should be added when more MOVW-related relocation types
+ are supported in GAS. */
+ gas_assert (aarch64_gas_internal_fixup_p ());
+ /* The shift amount should have already been set by the parser. */
+ return TRUE;
+ }
+ inst.base.operands[1].shifter.amount = shift;
+ return TRUE;
+}
+
+/* A primitive log caculator. */
+
+static inline unsigned int
+get_logsz (unsigned int size)
+{
+ const unsigned char ls[16] =
+ {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
+ if (size > 16)
+ {
+ gas_assert (0);
+ return -1;
+ }
+ gas_assert (ls[size - 1] != (unsigned char)-1);
+ return ls[size - 1];
+}
+
+/* Determine and return the real reloc type code for an instruction
+ with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
+
+static inline bfd_reloc_code_real_type
+ldst_lo12_determine_real_reloc_type (void)
+{
+ int logsz;
+ enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
+ enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
+
+ const bfd_reloc_code_real_type reloc_ldst_lo12[5] = {
+ BFD_RELOC_AARCH64_LDST8_LO12, BFD_RELOC_AARCH64_LDST16_LO12,
+ BFD_RELOC_AARCH64_LDST32_LO12, BFD_RELOC_AARCH64_LDST64_LO12,
+ BFD_RELOC_AARCH64_LDST128_LO12
+ };
+
+ gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12);
+ gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
+
+ if (opd1_qlf == AARCH64_OPND_QLF_NIL)
+ opd1_qlf =
+ aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list,
+ 1, opd0_qlf, 0);
+ gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
+
+ logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
+ gas_assert (logsz >= 0 && logsz <= 4);
+
+ return reloc_ldst_lo12[logsz];
+}
+
+/* Check whether a register list REGINFO is valid. The registers must be
+ numbered in increasing order (modulo 32), in increments of one or two.
+
+ If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
+ increments of two.
+
+ Return FALSE if such a register list is invalid, otherwise return TRUE. */
+
+static bfd_boolean
+reg_list_valid_p (uint32_t reginfo, int accept_alternate)
+{
+ uint32_t i, nb_regs, prev_regno, incr;
+
+ nb_regs = 1 + (reginfo & 0x3);
+ reginfo >>= 2;
+ prev_regno = reginfo & 0x1f;
+ incr = accept_alternate ? 2 : 1;
+
+ for (i = 1; i < nb_regs; ++i)
+ {
+ uint32_t curr_regno;
+ reginfo >>= 5;
+ curr_regno = reginfo & 0x1f;
+ if (curr_regno != ((prev_regno + incr) & 0x1f))
+ return FALSE;
+ prev_regno = curr_regno;
+ }
+
+ return TRUE;
+}
+
+/* Generic instruction operand parser. This does no encoding and no
+ semantic validation; it merely squirrels values away in the inst
+ structure. Returns TRUE or FALSE depending on whether the
+ specified grammar matched. */
+
+static bfd_boolean
+parse_operands (char *str, const aarch64_opcode *opcode)
+{
+ int i;
+ char *backtrack_pos = 0;
+ const enum aarch64_opnd *operands = opcode->operands;
+
+ clear_error ();
+ skip_whitespace (str);
+
+ for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
+ {
+ int64_t val;
+ int isreg32, isregzero;
+ int comma_skipped_p = 0;
+ aarch64_reg_type rtype;
+ struct neon_type_el vectype;
+ aarch64_opnd_info *info = &inst.base.operands[i];
+
+ DEBUG_TRACE ("parse operand %d", i);
+
+ /* Assign the operand code. */
+ info->type = operands[i];
+
+ if (optional_operand_p (opcode, i))
+ {
+ /* Remember where we are in case we need to backtrack. */
+ gas_assert (!backtrack_pos);
+ backtrack_pos = str;
+ }
+
+ /* Expect comma between operands; the backtrack mechanizm will take
+ care of cases of omitted optional operand. */
+ if (i > 0 && ! skip_past_char (&str, ','))
+ {
+ set_syntax_error (_("comma expected between operands"));
+ goto failure;
+ }
+ else
+ comma_skipped_p = 1;
+
+ switch (operands[i])
+ {
+ case AARCH64_OPND_Rd:
+ case AARCH64_OPND_Rn:
+ case AARCH64_OPND_Rm:
+ case AARCH64_OPND_Rt:
+ case AARCH64_OPND_Rt2:
+ case AARCH64_OPND_Rs:
+ case AARCH64_OPND_Ra:
+ case AARCH64_OPND_Rt_SYS:
+ po_int_reg_or_fail (1, 0);
+ break;
+
+ case AARCH64_OPND_Rd_SP:
+ case AARCH64_OPND_Rn_SP:
+ po_int_reg_or_fail (0, 1);
+ break;
+
+ case AARCH64_OPND_Rm_EXT:
+ case AARCH64_OPND_Rm_SFT:
+ po_misc_or_fail (parse_shifter_operand
+ (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT
+ ? SHIFTED_ARITH_IMM
+ : SHIFTED_LOGIC_IMM)));
+ if (!info->shifter.operator_present)
+ {
+ /* Default to LSL if not present. Libopcodes prefers shifter
+ kind to be explicit. */
+ gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
+ info->shifter.kind = AARCH64_MOD_LSL;
+ /* For Rm_EXT, libopcodes will carry out further check on whether
+ or not stack pointer is used in the instruction (Recall that
+ "the extend operator is not optional unless at least one of
+ "Rd" or "Rn" is '11111' (i.e. WSP)"). */
+ }
+ break;
+
+ case AARCH64_OPND_Fd:
+ case AARCH64_OPND_Fn:
+ case AARCH64_OPND_Fm:
+ case AARCH64_OPND_Fa:
+ case AARCH64_OPND_Ft:
+ case AARCH64_OPND_Ft2:
+ case AARCH64_OPND_Sd:
+ case AARCH64_OPND_Sn:
+ case AARCH64_OPND_Sm:
+ val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
+ if (val == PARSE_FAIL)
+ {
+ first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
+ goto failure;
+ }
+ gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
+
+ info->reg.regno = val;
+ info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
+ break;
+
+ case AARCH64_OPND_Vd:
+ case AARCH64_OPND_Vn:
+ case AARCH64_OPND_Vm:
+ val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
+ if (val == PARSE_FAIL)
+ {
+ first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
+ goto failure;
+ }
+ if (vectype.defined & NTA_HASINDEX)
+ goto failure;
+
+ info->reg.regno = val;
+ info->qualifier = vectype_to_qualifier (&vectype);
+ if (info->qualifier == AARCH64_OPND_QLF_NIL)
+ goto failure;
+ break;
+
+ case AARCH64_OPND_VdD1:
+ case AARCH64_OPND_VnD1:
+ val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
+ if (val == PARSE_FAIL)
+ {
+ set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
+ goto failure;
+ }
+ if (vectype.type != NT_d || vectype.index != 1)
+ {
+ set_fatal_syntax_error
+ (_("the top half of a 128-bit FP/SIMD register is expected"));
+ goto failure;
+ }
+ info->reg.regno = val;
+ /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
+ here; it is correct for the purpose of encoding/decoding since
+ only the register number is explicitly encoded in the related
+ instructions, although this appears a bit hacky. */
+ info->qualifier = AARCH64_OPND_QLF_S_D;
+ break;
+
+ case AARCH64_OPND_Ed:
+ case AARCH64_OPND_En:
+ case AARCH64_OPND_Em:
+ val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
+ if (val == PARSE_FAIL)
+ {
+ first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
+ goto failure;
+ }
+ if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
+ goto failure;
+
+ info->reglane.regno = val;
+ info->reglane.index = vectype.index;
+ info->qualifier = vectype_to_qualifier (&vectype);
+ if (info->qualifier == AARCH64_OPND_QLF_NIL)
+ goto failure;
+ break;
+
+ case AARCH64_OPND_LVn:
+ case AARCH64_OPND_LVt:
+ case AARCH64_OPND_LVt_AL:
+ case AARCH64_OPND_LEt:
+ if ((val = parse_neon_reg_list (&str, &vectype)) == PARSE_FAIL)
+ goto failure;
+ if (! reg_list_valid_p (val, /* accept_alternate */ 0))
+ {
+ set_fatal_syntax_error (_("invalid register list"));
+ goto failure;
+ }
+ info->reglist.first_regno = (val >> 2) & 0x1f;
+ info->reglist.num_regs = (val & 0x3) + 1;
+ if (operands[i] == AARCH64_OPND_LEt)
+ {
+ if (!(vectype.defined & NTA_HASINDEX))
+ goto failure;
+ info->reglist.has_index = 1;
+ info->reglist.index = vectype.index;
+ }
+ else if (!(vectype.defined & NTA_HASTYPE))
+ goto failure;
+ info->qualifier = vectype_to_qualifier (&vectype);
+ if (info->qualifier == AARCH64_OPND_QLF_NIL)
+ goto failure;
+ break;
+
+ case AARCH64_OPND_Cn:
+ case AARCH64_OPND_Cm:
+ po_reg_or_fail (REG_TYPE_CN);
+ if (val > 15)
+ {
+ set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN)));
+ goto failure;
+ }
+ inst.base.operands[i].reg.regno = val;
+ break;
+
+ case AARCH64_OPND_SHLL_IMM:
+ case AARCH64_OPND_IMM_VLSR:
+ po_imm_or_fail (1, 64);
+ info->imm.value = val;
+ break;
+
+ case AARCH64_OPND_CCMP_IMM:
+ case AARCH64_OPND_FBITS:
+ case AARCH64_OPND_UIMM4:
+ case AARCH64_OPND_UIMM3_OP1:
+ case AARCH64_OPND_UIMM3_OP2:
+ case AARCH64_OPND_IMM_VLSL:
+ case AARCH64_OPND_IMM:
+ case AARCH64_OPND_WIDTH:
+ po_imm_nc_or_fail ();
+ info->imm.value = val;
+ break;
+
+ case AARCH64_OPND_UIMM7:
+ po_imm_or_fail (0, 127);
+ info->imm.value = val;
+ break;
+
+ case AARCH64_OPND_IDX:
+ case AARCH64_OPND_BIT_NUM:
+ case AARCH64_OPND_IMMR:
+ case AARCH64_OPND_IMMS:
+ po_imm_or_fail (0, 63);
+ info->imm.value = val;
+ break;
+
+ case AARCH64_OPND_IMM0:
+ po_imm_nc_or_fail ();
+ if (val != 0)
+ {
+ set_fatal_syntax_error (_("immediate zero expected"));
+ goto failure;
+ }
+ info->imm.value = 0;
+ break;
+
+ case AARCH64_OPND_FPIMM0:
+ {
+ int qfloat;
+ bfd_boolean res1 = FALSE, res2 = FALSE;
+ /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
+ it is probably not worth the effort to support it. */
+ if (!(res1 = parse_aarch64_imm_float (&str, &qfloat))
+ && !(res2 = parse_constant_immediate (&str, &val)))
+ goto failure;
+ if ((res1 && qfloat == 0) || (res2 && val == 0))
+ {
+ info->imm.value = 0;
+ info->imm.is_fp = 1;
+ break;
+ }
+ set_fatal_syntax_error (_("immediate zero expected"));
+ goto failure;
+ }
+
+ case AARCH64_OPND_IMM_MOV:
+ {
+ char *saved = str;
+ if (reg_name_p (str, REG_TYPE_R_Z_SP))
+ goto failure;
+ str = saved;
+ po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
+ GE_OPT_PREFIX, 1));
+ /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
+ later. fix_mov_imm_insn will try to determine a machine
+ instruction (MOVZ, MOVN or ORR) for it and will issue an error
+ message if the immediate cannot be moved by a single
+ instruction. */
+ aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
+ inst.base.operands[i].skip = 1;
+ }
+ break;
+
+ case AARCH64_OPND_SIMD_IMM:
+ case AARCH64_OPND_SIMD_IMM_SFT:
+ if (! parse_big_immediate (&str, &val))
+ goto failure;
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 0,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 1);
+ /* Parse shift.
+ N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
+ shift, we don't check it here; we leave the checking to
+ the libopcodes (operand_general_constraint_met_p). By
+ doing this, we achieve better diagnostics. */
+ if (skip_past_comma (&str)
+ && ! parse_shift (&str, info, SHIFTED_LSL_MSL))
+ goto failure;
+ if (!info->shifter.operator_present
+ && info->type == AARCH64_OPND_SIMD_IMM_SFT)
+ {
+ /* Default to LSL if not present. Libopcodes prefers shifter
+ kind to be explicit. */
+ gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
+ info->shifter.kind = AARCH64_MOD_LSL;
+ }
+ break;
+
+ case AARCH64_OPND_FPIMM:
+ case AARCH64_OPND_SIMD_FPIMM:
+ {
+ int qfloat;
+ if (! parse_aarch64_imm_float (&str, &qfloat))
+ goto failure;
+ if (qfloat == 0)
+ {
+ set_fatal_syntax_error (_("invalid floating-point constant"));
+ goto failure;
+ }
+ inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat);
+ inst.base.operands[i].imm.is_fp = 1;
+ }
+ break;
+
+ case AARCH64_OPND_LIMM:
+ po_misc_or_fail (parse_shifter_operand (&str, info,
+ SHIFTED_LOGIC_IMM));
+ if (info->shifter.operator_present)
+ {
+ set_fatal_syntax_error
+ (_("shift not allowed for bitmask immediate"));
+ goto failure;
+ }
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 0,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 1);
+ break;
+
+ case AARCH64_OPND_AIMM:
+ if (opcode->op == OP_ADD)
+ /* ADD may have relocation types. */
+ po_misc_or_fail (parse_shifter_operand_reloc (&str, info,
+ SHIFTED_ARITH_IMM));
+ else
+ po_misc_or_fail (parse_shifter_operand (&str, info,
+ SHIFTED_ARITH_IMM));
+ switch (inst.reloc.type)
+ {
+ case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
+ info->shifter.amount = 12;
+ break;
+ case BFD_RELOC_UNUSED:
+ aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
+ if (info->shifter.kind != AARCH64_MOD_NONE)
+ inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT;
+ inst.reloc.pc_rel = 0;
+ break;
+ default:
+ break;
+ }
+ info->imm.value = 0;
+ if (!info->shifter.operator_present)
+ {
+ /* Default to LSL if not present. Libopcodes prefers shifter
+ kind to be explicit. */
+ gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
+ info->shifter.kind = AARCH64_MOD_LSL;
+ }
+ break;
+
+ case AARCH64_OPND_HALF:
+ {
+ /* #<imm16> or relocation. */
+ int internal_fixup_p;
+ po_misc_or_fail (parse_half (&str, &internal_fixup_p));
+ if (internal_fixup_p)
+ aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
+ skip_whitespace (str);
+ if (skip_past_comma (&str))
+ {
+ /* {, LSL #<shift>} */
+ if (! aarch64_gas_internal_fixup_p ())
+ {
+ set_fatal_syntax_error (_("can't mix relocation modifier "
+ "with explicit shift"));
+ goto failure;
+ }
+ po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
+ }
+ else
+ inst.base.operands[i].shifter.amount = 0;
+ inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
+ inst.base.operands[i].imm.value = 0;
+ if (! process_movw_reloc_info ())
+ goto failure;
+ }
+ break;
+
+ case AARCH64_OPND_EXCEPTION:
+ po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp));
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 0,
+ /* need_libopcodes_p */ 0,
+ /* skip_p */ 1);
+ break;
+
+ case AARCH64_OPND_NZCV:
+ {
+ const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4);
+ if (nzcv != NULL)
+ {
+ str += 4;
+ info->imm.value = nzcv->value;
+ break;
+ }
+ po_imm_or_fail (0, 15);
+ info->imm.value = val;
+ }
+ break;
+
+ case AARCH64_OPND_COND:
+ info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
+ str += 2;
+ if (info->cond == NULL)
+ {
+ set_syntax_error (_("invalid condition"));
+ goto failure;
+ }
+ break;
+
+ case AARCH64_OPND_ADDR_ADRP:
+ po_misc_or_fail (parse_adrp (&str));
+ /* Clear the value as operand needs to be relocated. */
+ info->imm.value = 0;
+ break;
+
+ case AARCH64_OPND_ADDR_PCREL14:
+ case AARCH64_OPND_ADDR_PCREL19:
+ case AARCH64_OPND_ADDR_PCREL21:
+ case AARCH64_OPND_ADDR_PCREL26:
+ po_misc_or_fail (parse_address_reloc (&str, info));
+ if (!info->addr.pcrel)
+ {
+ set_syntax_error (_("invalid pc-relative address"));
+ goto failure;
+ }
+ if (inst.gen_lit_pool
+ && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT))
+ {
+ /* Only permit "=value" in the literal load instructions.
+ The literal will be generated by programmer_friendly_fixup. */
+ set_syntax_error (_("invalid use of \"=immediate\""));
+ goto failure;
+ }
+ if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str))
+ {
+ set_syntax_error (_("unrecognized relocation suffix"));
+ goto failure;
+ }
+ if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
+ {
+ info->imm.value = inst.reloc.exp.X_add_number;
+ inst.reloc.type = BFD_RELOC_UNUSED;
+ }
+ else
+ {
+ info->imm.value = 0;
+ switch (opcode->iclass)
+ {
+ case compbranch:
+ case condbranch:
+ /* e.g. CBZ or B.COND */
+ gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
+ inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
+ break;
+ case testbranch:
+ /* e.g. TBZ */
+ gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
+ inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
+ break;
+ case branch_imm:
+ /* e.g. B or BL */
+ gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
+ inst.reloc.type = (opcode->op == OP_BL)
+ ? BFD_RELOC_AARCH64_CALL26 : BFD_RELOC_AARCH64_JUMP26;
+ break;
+ case loadlit:
+ gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
+ inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
+ break;
+ case pcreladdr:
+ gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
+ inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
+ break;
+ default:
+ gas_assert (0);
+ abort ();
+ }
+ inst.reloc.pc_rel = 1;
+ }
+ break;
+
+ case AARCH64_OPND_ADDR_SIMPLE:
+ case AARCH64_OPND_SIMD_ADDR_SIMPLE:
+ /* [<Xn|SP>{, #<simm>}] */
+ po_char_or_fail ('[');
+ po_reg_or_fail (REG_TYPE_R64_SP);
+ /* Accept optional ", #0". */
+ if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
+ && skip_past_char (&str, ','))
+ {
+ skip_past_char (&str, '#');
+ if (! skip_past_char (&str, '0'))
+ {
+ set_fatal_syntax_error
+ (_("the optional immediate offset can only be 0"));
+ goto failure;
+ }
+ }
+ po_char_or_fail (']');
+ info->addr.base_regno = val;
+ break;
+
+ case AARCH64_OPND_ADDR_REGOFF:
+ /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
+ po_misc_or_fail (parse_address (&str, info, 0));
+ if (info->addr.pcrel || !info->addr.offset.is_reg
+ || !info->addr.preind || info->addr.postind
+ || info->addr.writeback)
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ if (!info->shifter.operator_present)
+ {
+ /* Default to LSL if not present. Libopcodes prefers shifter
+ kind to be explicit. */
+ gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
+ info->shifter.kind = AARCH64_MOD_LSL;
+ }
+ /* Qualifier to be deduced by libopcodes. */
+ break;
+
+ case AARCH64_OPND_ADDR_SIMM7:
+ po_misc_or_fail (parse_address (&str, info, 0));
+ if (info->addr.pcrel || info->addr.offset.is_reg
+ || (!info->addr.preind && !info->addr.postind))
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+
+ case AARCH64_OPND_ADDR_SIMM9:
+ case AARCH64_OPND_ADDR_SIMM9_2:
+ po_misc_or_fail (parse_address_reloc (&str, info));
+ if (info->addr.pcrel || info->addr.offset.is_reg
+ || (!info->addr.preind && !info->addr.postind)
+ || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
+ && info->addr.writeback))
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ if (inst.reloc.type != BFD_RELOC_UNUSED)
+ {
+ set_syntax_error (_("relocation not allowed"));
+ goto failure;
+ }
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+
+ case AARCH64_OPND_ADDR_UIMM12:
+ po_misc_or_fail (parse_address_reloc (&str, info));
+ if (info->addr.pcrel || info->addr.offset.is_reg
+ || !info->addr.preind || info->addr.writeback)
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ if (inst.reloc.type == BFD_RELOC_UNUSED)
+ aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
+ else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12)
+ inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
+ /* Leave qualifier to be determined by libopcodes. */
+ break;
+
+ case AARCH64_OPND_SIMD_ADDR_POST:
+ /* [<Xn|SP>], <Xm|#<amount>> */
+ po_misc_or_fail (parse_address (&str, info, 1));
+ if (!info->addr.postind || !info->addr.writeback)
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ if (!info->addr.offset.is_reg)
+ {
+ if (inst.reloc.exp.X_op == O_constant)
+ info->addr.offset.imm = inst.reloc.exp.X_add_number;
+ else
+ {
+ set_fatal_syntax_error
+ (_("writeback value should be an immediate constant"));
+ goto failure;
+ }
+ }
+ /* No qualifier. */
+ break;
+
+ case AARCH64_OPND_SYSREG:
+ if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1)) == FALSE)
+ {
+ set_syntax_error (_("unknown or missing system register name"));
+ goto failure;
+ }
+ inst.base.operands[i].sysreg = val;
+ break;
+
+ case AARCH64_OPND_PSTATEFIELD:
+ if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0)) == FALSE)
+ {
+ set_syntax_error (_("unknown or missing PSTATE field name"));
+ goto failure;
+ }
+ inst.base.operands[i].pstatefield = val;
+ break;
+
+ case AARCH64_OPND_SYSREG_IC:
+ inst.base.operands[i].sysins_op =
+ parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
+ goto sys_reg_ins;
+ case AARCH64_OPND_SYSREG_DC:
+ inst.base.operands[i].sysins_op =
+ parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
+ goto sys_reg_ins;
+ case AARCH64_OPND_SYSREG_AT:
+ inst.base.operands[i].sysins_op =
+ parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
+ goto sys_reg_ins;
+ case AARCH64_OPND_SYSREG_TLBI:
+ inst.base.operands[i].sysins_op =
+ parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
+sys_reg_ins:
+ if (inst.base.operands[i].sysins_op == NULL)
+ {
+ set_fatal_syntax_error ( _("unknown or missing operation name"));
+ goto failure;
+ }
+ break;
+
+ case AARCH64_OPND_BARRIER:
+ case AARCH64_OPND_BARRIER_ISB:
+ val = parse_barrier (&str);
+ if (val != PARSE_FAIL
+ && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf)
+ {
+ /* ISB only accepts options name 'sy'. */
+ set_syntax_error
+ (_("the specified option is not accepted in ISB"));
+ /* Turn off backtrack as this optional operand is present. */
+ backtrack_pos = 0;
+ goto failure;
+ }
+ /* This is an extension to accept a 0..15 immediate. */
+ if (val == PARSE_FAIL)
+ po_imm_or_fail (0, 15);
+ info->barrier = aarch64_barrier_options + val;
+ break;
+
+ case AARCH64_OPND_PRFOP:
+ val = parse_pldop (&str);
+ /* This is an extension to accept a 0..31 immediate. */
+ if (val == PARSE_FAIL)
+ po_imm_or_fail (0, 31);
+ inst.base.operands[i].prfop = aarch64_prfops + val;
+ break;
+
+ default:
+ as_fatal (_("unhandled operand code %d"), operands[i]);
+ }
+
+ /* If we get here, this operand was successfully parsed. */
+ inst.base.operands[i].present = 1;
+ continue;
+
+failure:
+ /* The parse routine should already have set the error, but in case
+ not, set a default one here. */
+ if (! error_p ())
+ set_default_error ();
+
+ if (! backtrack_pos)
+ goto parse_operands_return;
+
+ /* Reaching here means we are dealing with an optional operand that is
+ omitted from the assembly line. */
+ gas_assert (optional_operand_p (opcode, i));
+ info->present = 0;
+ process_omitted_operand (operands[i], opcode, i, info);
+
+ /* Try again, skipping the optional operand at backtrack_pos. */
+ str = backtrack_pos;
+ backtrack_pos = 0;
+
+ /* If this is the last operand that is optional and omitted, but without
+ the presence of a comma. */
+ if (i && comma_skipped_p && i == aarch64_num_of_operands (opcode) - 1)
+ {
+ set_fatal_syntax_error
+ (_("unexpected comma before the omitted optional operand"));
+ goto parse_operands_return;
+ }
+
+ /* Clear any error record after the omitted optional operand has been
+ successfully handled. */
+ clear_error ();
+ }
+
+ /* Check if we have parsed all the operands. */
+ if (*str != '\0' && ! error_p ())
+ {
+ /* Set I to the index of the last present operand; this is
+ for the purpose of diagnostics. */
+ for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i)
+ ;
+ set_fatal_syntax_error
+ (_("unexpected characters following instruction"));
+ }
+
+parse_operands_return:
+
+ if (error_p ())
+ {
+ DEBUG_TRACE ("parsing FAIL: %s - %s",
+ operand_mismatch_kind_names[get_error_kind ()],
+ get_error_message ());
+ /* Record the operand error properly; this is useful when there
+ are multiple instruction templates for a mnemonic name, so that
+ later on, we can select the error that most closely describes
+ the problem. */
+ record_operand_error (opcode, i, get_error_kind (),
+ get_error_message ());
+ return FALSE;
+ }
+ else
+ {
+ DEBUG_TRACE ("parsing SUCCESS");
+ return TRUE;
+ }
+}
+
+/* It does some fix-up to provide some programmer friendly feature while
+ keeping the libopcodes happy, i.e. libopcodes only accepts
+ the preferred architectural syntax.
+ Return FALSE if there is any failure; otherwise return TRUE. */
+
+static bfd_boolean
+programmer_friendly_fixup (aarch64_instruction *instr)
+{
+ aarch64_inst *base = &instr->base;
+ const aarch64_opcode *opcode = base->opcode;
+ enum aarch64_op op = opcode->op;
+ aarch64_opnd_info *operands = base->operands;
+
+ DEBUG_TRACE ("enter");
+
+ switch (opcode->iclass)
+ {
+ case testbranch:
+ /* TBNZ Xn|Wn, #uimm6, label
+ Test and Branch Not Zero: conditionally jumps to label if bit number
+ uimm6 in register Xn is not zero. The bit number implies the width of
+ the register, which may be written and should be disassembled as Wn if
+ uimm is less than 32. */
+ if (operands[0].qualifier == AARCH64_OPND_QLF_W)
+ {
+ if (operands[1].imm.value >= 32)
+ {
+ record_operand_out_of_range_error (opcode, 1, _("immediate value"),
+ 0, 31);
+ return FALSE;
+ }
+ operands[0].qualifier = AARCH64_OPND_QLF_X;
+ }
+ break;
+ case loadlit:
+ /* LDR Wt, label | =value
+ As a convenience assemblers will typically permit the notation
+ "=value" in conjunction with the pc-relative literal load instructions
+ to automatically place an immediate value or symbolic address in a
+ nearby literal pool and generate a hidden label which references it.
+ ISREG has been set to 0 in the case of =value. */
+ if (instr->gen_lit_pool
+ && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT))
+ {
+ int size = aarch64_get_qualifier_esize (operands[0].qualifier);
+ if (op == OP_LDRSW_LIT)
+ size = 4;
+ if (instr->reloc.exp.X_op != O_constant
+ && instr->reloc.exp.X_op != O_symbol)
+ {
+ record_operand_error (opcode, 1,
+ AARCH64_OPDE_FATAL_SYNTAX_ERROR,
+ _("constant expression expected"));
+ return FALSE;
+ }
+ if (! add_to_lit_pool (&instr->reloc.exp, size))
+ {
+ record_operand_error (opcode, 1,
+ AARCH64_OPDE_OTHER_ERROR,
+ _("literal pool insertion failed"));
+ return FALSE;
+ }
+ }
+ break;
+ case asimdimm:
+ /* Allow MOVI V0.16B, 97, LSL 0, although the preferred architectural
+ syntax requires that the LSL shifter can only be used when the
+ destination register has the shape of 4H, 8H, 2S or 4S. */
+ if (op == OP_V_MOVI_B && operands[1].shifter.kind == AARCH64_MOD_LSL
+ && (operands[0].qualifier == AARCH64_OPND_QLF_V_8B
+ || operands[0].qualifier == AARCH64_OPND_QLF_V_16B))
+ {
+ if (operands[1].shifter.amount != 0)
+ {
+ record_operand_error (opcode, 1,
+ AARCH64_OPDE_OTHER_ERROR,
+ _("shift amount non-zero"));
+ return FALSE;
+ }
+ operands[1].shifter.kind = AARCH64_MOD_NONE;
+ operands[1].qualifier = AARCH64_OPND_QLF_NIL;
+ }
+ break;
+ case log_shift:
+ case bitfield:
+ /* UXT[BHW] Wd, Wn
+ Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
+ for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
+ encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
+ A programmer-friendly assembler should accept a destination Xd in
+ place of Wd, however that is not the preferred form for disassembly.
+ */
+ if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW)
+ && operands[1].qualifier == AARCH64_OPND_QLF_W
+ && operands[0].qualifier == AARCH64_OPND_QLF_X)
+ operands[0].qualifier = AARCH64_OPND_QLF_W;
+ break;
+
+ case addsub_ext:
+ {
+ /* In the 64-bit form, the final register operand is written as Wm
+ for all but the (possibly omitted) UXTX/LSL and SXTX
+ operators.
+ As a programmer-friendly assembler, we accept e.g.
+ ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
+ ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
+ int idx = aarch64_operand_index (opcode->operands,
+ AARCH64_OPND_Rm_EXT);
+ gas_assert (idx == 1 || idx == 2);
+ if (operands[0].qualifier == AARCH64_OPND_QLF_X
+ && operands[idx].qualifier == AARCH64_OPND_QLF_X
+ && operands[idx].shifter.kind != AARCH64_MOD_LSL
+ && operands[idx].shifter.kind != AARCH64_MOD_UXTX
+ && operands[idx].shifter.kind != AARCH64_MOD_SXTX)
+ operands[idx].qualifier = AARCH64_OPND_QLF_W;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ DEBUG_TRACE ("exit with SUCCESS");
+ return TRUE;
+}
+
+/* A wrapper function to interface with libopcodes on encoding and
+ record the error message if there is any.
+
+ Return TRUE on success; otherwise return FALSE. */
+
+static bfd_boolean
+do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
+ aarch64_insn *code)
+{
+ aarch64_operand_error error_info;
+ error_info.kind = AARCH64_OPDE_NIL;
+ if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
+ return TRUE;
+ else
+ {
+ gas_assert (error_info.kind != AARCH64_OPDE_NIL);
+ record_operand_error_info (opcode, &error_info);
+ return FALSE;
+ }
+}
+
+#ifdef DEBUG_AARCH64
+static inline void
+dump_opcode_operands (const aarch64_opcode *opcode)
+{
+ int i = 0;
+ while (opcode->operands[i] != AARCH64_OPND_NIL)
+ {
+ aarch64_verbose ("\t\t opnd%d: %s", i,
+ aarch64_get_operand_name (opcode->operands[i])[0] != '\0'
+ ? aarch64_get_operand_name (opcode->operands[i])
+ : aarch64_get_operand_desc (opcode->operands[i]));
+ ++i;
+ }
+}
+#endif /* DEBUG_AARCH64 */
+
+/* This is the guts of the machine-dependent assembler. STR points to a
+ machine dependent instruction. This function is supposed to emit
+ the frags/bytes it assembles to. */
+
+void
+md_assemble (char *str)
+{
+ char *p = str;
+ templates *template;
+ aarch64_opcode *opcode;
+ aarch64_inst *inst_base;
+ unsigned saved_cond;
+
+ /* Align the previous label if needed. */
+ if (last_label_seen != NULL)
+ {
+ symbol_set_frag (last_label_seen, frag_now);
+ S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
+ S_SET_SEGMENT (last_label_seen, now_seg);
+ }
+
+ inst.reloc.type = BFD_RELOC_UNUSED;
+
+ DEBUG_TRACE ("\n\n");
+ DEBUG_TRACE ("==============================");
+ DEBUG_TRACE ("Enter md_assemble with %s", str);
+
+ template = opcode_lookup (&p);
+ if (!template)
+ {
+ /* It wasn't an instruction, but it might be a register alias of
+ the form alias .req reg directive. */
+ if (!create_register_alias (str, p))
+ as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
+ str);
+ return;
+ }
+
+ skip_whitespace (p);
+ if (*p == ',')
+ {
+ as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
+ get_mnemonic_name (str), str);
+ return;
+ }
+
+ init_operand_error_report ();
+
+ saved_cond = inst.cond;
+ reset_aarch64_instruction (&inst);
+ inst.cond = saved_cond;
+
+ /* Iterate through all opcode entries with the same mnemonic name. */
+ do
+ {
+ opcode = template->opcode;
+
+ DEBUG_TRACE ("opcode %s found", opcode->name);
+#ifdef DEBUG_AARCH64
+ if (debug_dump)
+ dump_opcode_operands (opcode);
+#endif /* DEBUG_AARCH64 */
+
+ /* Check that this instruction is supported for this CPU. */
+ if (!opcode->avariant
+ || !AARCH64_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
+ {
+ as_bad (_("selected processor does not support `%s'"), str);
+ return;
+ }
+
+ mapping_state (MAP_INSN);
+
+ inst_base = &inst.base;
+ inst_base->opcode = opcode;
+
+ /* Truly conditionally executed instructions, e.g. b.cond. */
+ if (opcode->flags & F_COND)
+ {
+ gas_assert (inst.cond != COND_ALWAYS);
+ inst_base->cond = get_cond_from_value (inst.cond);
+ DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]);
+ }
+ else if (inst.cond != COND_ALWAYS)
+ {
+ /* It shouldn't arrive here, where the assembly looks like a
+ conditional instruction but the found opcode is unconditional. */
+ gas_assert (0);
+ continue;
+ }
+
+ if (parse_operands (p, opcode)
+ && programmer_friendly_fixup (&inst)
+ && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
+ {
+ if (inst.reloc.type == BFD_RELOC_UNUSED
+ || !inst.reloc.need_libopcodes_p)
+ output_inst (NULL);
+ else
+ {
+ /* If there is relocation generated for the instruction,
+ store the instruction information for the future fix-up. */
+ struct aarch64_inst *copy;
+ gas_assert (inst.reloc.type != BFD_RELOC_UNUSED);
+ if ((copy = xmalloc (sizeof (struct aarch64_inst))) == NULL)
+ abort ();
+ memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
+ output_inst (copy);
+ }
+ return;
+ }
+
+ template = template->next;
+ if (template != NULL)
+ {
+ reset_aarch64_instruction (&inst);
+ inst.cond = saved_cond;
+ }
+ }
+ while (template != NULL);
+
+ /* Issue the error messages if any. */
+ output_operand_error_report (str);
+}
+
+/* Various frobbings of labels and their addresses. */
+
+void
+aarch64_start_line_hook (void)
+{
+ last_label_seen = NULL;
+}
+
+void
+aarch64_frob_label (symbolS * sym)
+{
+ last_label_seen = sym;
+
+ dwarf2_emit_label (sym);
+}
+
+int
+aarch64_data_in_code (void)
+{
+ if (!strncmp (input_line_pointer + 1, "data:", 5))
+ {
+ *input_line_pointer = '/';
+ input_line_pointer += 5;
+ *input_line_pointer = 0;
+ return 1;
+ }
+
+ return 0;
+}
+
+char *
+aarch64_canonicalize_symbol_name (char *name)
+{
+ int len;
+
+ if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data"))
+ *(name + len - 5) = 0;
+
+ return name;
+}
+\f
+/* Table of all register names defined by default. The user can
+ define additional names with .req. Note that all register names
+ should appear in both upper and lowercase variants. Some registers
+ also have mixed-case names. */
+
+#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
+#define REGNUM(p,n,t) REGDEF(p##n, n, t)
+#define REGSET31(p,t) \
+ REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
+ REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
+ REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
+ REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
+ REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
+ REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
+ REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
+ REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
+#define REGSET(p,t) \
+ REGSET31(p,t), REGNUM(p,31,t)
+
+/* These go into aarch64_reg_hsh hash-table. */
+static const reg_entry reg_names[] = {
+ /* Integer registers. */
+ REGSET31 (x, R_64), REGSET31 (X, R_64),
+ REGSET31 (w, R_32), REGSET31 (W, R_32),
+
+ REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
+ REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
+
+ REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
+ REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
+
+ /* Coprocessor register numbers. */
+ REGSET (c, CN), REGSET (C, CN),
+
+ /* Floating-point single precision registers. */
+ REGSET (s, FP_S), REGSET (S, FP_S),
+
+ /* Floating-point double precision registers. */
+ REGSET (d, FP_D), REGSET (D, FP_D),
+
+ /* Floating-point half precision registers. */
+ REGSET (h, FP_H), REGSET (H, FP_H),
+
+ /* Floating-point byte precision registers. */
+ REGSET (b, FP_B), REGSET (B, FP_B),
+
+ /* Floating-point quad precision registers. */
+ REGSET (q, FP_Q), REGSET (Q, FP_Q),
+
+ /* FP/SIMD registers. */
+ REGSET (v, VN), REGSET (V, VN),
+};
+
+#undef REGDEF
+#undef REGNUM
+#undef REGSET
+
+#define N 1
+#define n 0
+#define Z 1
+#define z 0
+#define C 1
+#define c 0
+#define V 1
+#define v 0
+#define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
+static const asm_nzcv nzcv_names[] = {
+ {"nzcv", B (n, z, c, v)},
+ {"nzcV", B (n, z, c, V)},
+ {"nzCv", B (n, z, C, v)},
+ {"nzCV", B (n, z, C, V)},
+ {"nZcv", B (n, Z, c, v)},
+ {"nZcV", B (n, Z, c, V)},
+ {"nZCv", B (n, Z, C, v)},
+ {"nZCV", B (n, Z, C, V)},
+ {"Nzcv", B (N, z, c, v)},
+ {"NzcV", B (N, z, c, V)},
+ {"NzCv", B (N, z, C, v)},
+ {"NzCV", B (N, z, C, V)},
+ {"NZcv", B (N, Z, c, v)},
+ {"NZcV", B (N, Z, c, V)},
+ {"NZCv", B (N, Z, C, v)},
+ {"NZCV", B (N, Z, C, V)}
+};
+
+#undef N
+#undef n
+#undef Z
+#undef z
+#undef C
+#undef c
+#undef V
+#undef v
+#undef B
+\f
+/* MD interface: bits in the object file. */
+
+/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
+ for use in the a.out file, and stores them in the array pointed to by buf.
+ This knows about the endian-ness of the target machine and does
+ THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
+ 2 (short) and 4 (long) Floating numbers are put out as a series of
+ LITTLENUMS (shorts, here at least). */
+
+void
+md_number_to_chars (char *buf, valueT val, int n)
+{
+ if (target_big_endian)
+ number_to_chars_bigendian (buf, val, n);
+ else
+ number_to_chars_littleendian (buf, val, n);
+}
+
+/* MD interface: Sections. */
+
+/* Estimate the size of a frag before relaxing. Assume everything fits in
+ 4 bytes. */
+
+int
+md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED)
+{
+ fragp->fr_var = 4;
+ return 4;
+}
+
+/* Round up a section size to the appropriate boundary. */
+
+valueT
+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
+{
+ return size;
+}
+
+/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
+ of an rs_align_code fragment. */
+
+void
+aarch64_handle_align (fragS * fragP)
+{
+ /* NOP = d503201f */
+ /* AArch64 instructions are always little-endian. */
+ static char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
+
+ int bytes, fix, noop_size;
+ char *p;
+ const char *noop;
+
+ if (fragP->fr_type != rs_align_code)
+ return;
+
+ bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
+ p = fragP->fr_literal + fragP->fr_fix;
+ fix = 0;
+
+ if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
+ bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
+
+#ifdef OBJ_ELF
+ gas_assert (fragP->tc_frag_data.recorded);
+#endif
+
+ noop = aarch64_noop;
+ noop_size = sizeof (aarch64_noop);
+ fragP->fr_var = noop_size;
+
+ if (bytes & (noop_size - 1))
+ {
+ fix = bytes & (noop_size - 1);
+#ifdef OBJ_ELF
+ insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
+#endif
+ memset (p, 0, fix);
+ p += fix;
+ bytes -= fix;
+ }
+
+ while (bytes >= noop_size)
+ {
+ memcpy (p, noop, noop_size);
+ p += noop_size;
+ bytes -= noop_size;
+ fix += noop_size;
+ }
+
+ fragP->fr_fix += fix;
+}
+
+/* Called from md_do_align. Used to create an alignment
+ frag in a code section. */
+
+void
+aarch64_frag_align_code (int n, int max)
+{
+ char *p;
+
+ /* We assume that there will never be a requirement
+ to support alignments greater than x bytes. */
+ if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
+ as_fatal (_
+ ("alignments greater than %d bytes not supported in .text sections"),
+ MAX_MEM_FOR_RS_ALIGN_CODE + 1);
+
+ p = frag_var (rs_align_code,
+ MAX_MEM_FOR_RS_ALIGN_CODE,
+ 1,
+ (relax_substateT) max,
+ (symbolS *) NULL, (offsetT) n, (char *) NULL);
+ *p = 0;
+}
+
+/* Perform target specific initialisation of a frag.
+ Note - despite the name this initialisation is not done when the frag
+ is created, but only when its type is assigned. A frag can be created
+ and used a long time before its type is set, so beware of assuming that
+ this initialisationis performed first. */
+
+#ifndef OBJ_ELF
+void
+aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED,
+ int max_chars ATTRIBUTE_UNUSED)
+{
+}
+
+#else /* OBJ_ELF is defined. */
+void
+aarch64_init_frag (fragS * fragP, int max_chars)
+{
+ /* Record a mapping symbol for alignment frags. We will delete this
+ later if the alignment ends up empty. */
+ if (!fragP->tc_frag_data.recorded)
+ {
+ fragP->tc_frag_data.recorded = 1;
+ switch (fragP->fr_type)
+ {
+ case rs_align:
+ case rs_align_test:
+ case rs_fill:
+ mapping_state_2 (MAP_DATA, max_chars);
+ break;
+ case rs_align_code:
+ mapping_state_2 (MAP_INSN, max_chars);
+ break;
+ default:
+ break;
+ }
+ }
+}
+\f
+/* Initialize the DWARF-2 unwind information for this procedure. */
+
+void
+tc_aarch64_frame_initial_instructions (void)
+{
+ cfi_add_CFA_def_cfa (REG_SP, 0);
+}
+#endif /* OBJ_ELF */
+
+/* Convert REGNAME to a DWARF-2 register number. */
+
+int
+tc_aarch64_regname_to_dw2regnum (char *regname)
+{
+ const reg_entry *reg = parse_reg (®name);
+ if (reg == NULL)
+ return -1;
+
+ switch (reg->type)
+ {
+ case REG_TYPE_SP_32:
+ case REG_TYPE_SP_64:
+ case REG_TYPE_R_32:
+ case REG_TYPE_R_64:
+ case REG_TYPE_FP_B:
+ case REG_TYPE_FP_H:
+ case REG_TYPE_FP_S:
+ case REG_TYPE_FP_D:
+ case REG_TYPE_FP_Q:
+ return reg->number;
+ default:
+ break;
+ }
+ return -1;
+}
+
+/* MD interface: Symbol and relocation handling. */
+
+/* Return the address within the segment that a PC-relative fixup is
+ relative to. For AArch64 PC-relative fixups applied to instructions
+ are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
+
+long
+md_pcrel_from_section (fixS * fixP, segT seg)
+{
+ offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
+
+ /* If this is pc-relative and we are going to emit a relocation
+ then we just want to put out any pipeline compensation that the linker
+ will need. Otherwise we want to use the calculated base. */
+ if (fixP->fx_pcrel
+ && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
+ || aarch64_force_relocation (fixP)))
+ base = 0;
+
+ /* AArch64 should be consistent for all pc-relative relocations. */
+ return base + AARCH64_PCREL_OFFSET;
+}
+
+/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
+ Otherwise we have no need to default values of symbols. */
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+#ifdef OBJ_ELF
+ if (name[0] == '_' && name[1] == 'G'
+ && streq (name, GLOBAL_OFFSET_TABLE_NAME))
+ {
+ if (!GOT_symbol)
+ {
+ if (symbol_find (name))
+ as_bad (_("GOT already in the symbol table"));
+
+ GOT_symbol = symbol_new (name, undefined_section,
+ (valueT) 0, &zero_address_frag);
+ }
+
+ return GOT_symbol;
+ }
+#endif
+
+ return 0;
+}
+
+/* Return non-zero if the indicated VALUE has overflowed the maximum
+ range expressible by a unsigned number with the indicated number of
+ BITS. */
+
+static bfd_boolean
+unsigned_overflow (valueT value, unsigned bits)
+{
+ valueT lim;
+ if (bits >= sizeof (valueT) * 8)
+ return FALSE;
+ lim = (valueT) 1 << bits;
+ return (value >= lim);
+}
+
+
+/* Return non-zero if the indicated VALUE has overflowed the maximum
+ range expressible by an signed number with the indicated number of
+ BITS. */
+
+static bfd_boolean
+signed_overflow (offsetT value, unsigned bits)
+{
+ offsetT lim;
+ if (bits >= sizeof (offsetT) * 8)
+ return FALSE;
+ lim = (offsetT) 1 << (bits - 1);
+ return (value < -lim || value >= lim);
+}
+
+/* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
+ unsigned immediate offset load/store instruction, try to encode it as
+ an unscaled, 9-bit, signed immediate offset load/store instruction.
+ Return TRUE if it is successful; otherwise return FALSE.
+
+ As a programmer-friendly assembler, LDUR/STUR instructions can be generated
+ in response to the standard LDR/STR mnemonics when the immediate offset is
+ unambiguous, i.e. when it is negative or unaligned. */
+
+static bfd_boolean
+try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
+{
+ int idx;
+ enum aarch64_op new_op;
+ const aarch64_opcode *new_opcode;
+
+ gas_assert (instr->opcode->iclass == ldst_pos);
+
+ switch (instr->opcode->op)
+ {
+ case OP_LDRB_POS:new_op = OP_LDURB; break;
+ case OP_STRB_POS: new_op = OP_STURB; break;
+ case OP_LDRSB_POS: new_op = OP_LDURSB; break;
+ case OP_LDRH_POS: new_op = OP_LDURH; break;
+ case OP_STRH_POS: new_op = OP_STURH; break;
+ case OP_LDRSH_POS: new_op = OP_LDURSH; break;
+ case OP_LDR_POS: new_op = OP_LDUR; break;
+ case OP_STR_POS: new_op = OP_STUR; break;
+ case OP_LDRF_POS: new_op = OP_LDURV; break;
+ case OP_STRF_POS: new_op = OP_STURV; break;
+ case OP_LDRSW_POS: new_op = OP_LDURSW; break;
+ case OP_PRFM_POS: new_op = OP_PRFUM; break;
+ default: new_op = OP_NIL; break;
+ }
+
+ if (new_op == OP_NIL)
+ return FALSE;
+
+ new_opcode = aarch64_get_opcode (new_op);
+ gas_assert (new_opcode != NULL);
+
+ DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
+ instr->opcode->op, new_opcode->op);
+
+ aarch64_replace_opcode (instr, new_opcode);
+
+ /* Clear up the ADDR_SIMM9's qualifier; otherwise the
+ qualifier matching may fail because the out-of-date qualifier will
+ prevent the operand being updated with a new and correct qualifier. */
+ idx = aarch64_operand_index (instr->opcode->operands,
+ AARCH64_OPND_ADDR_SIMM9);
+ gas_assert (idx == 1);
+ instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
+
+ DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
+
+ if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
+ return FALSE;
+
+ return TRUE;
+}
+
+/* Called by fix_insn to fix a MOV immediate alias instruction.
+
+ Operand for a generic move immediate instruction, which is an alias
+ instruction that generates a single MOVZ, MOVN or ORR instruction to loads
+ a 32-bit/64-bit immediate value into general register. An assembler error
+ shall result if the immediate cannot be created by a single one of these
+ instructions. If there is a choice, then to ensure reversability an
+ assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
+
+static void
+fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
+{
+ const aarch64_opcode *opcode;
+
+ /* Need to check if the destination is SP/ZR. The check has to be done
+ before any aarch64_replace_opcode. */
+ int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]);
+ int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]);
+
+ instr->operands[1].imm.value = value;
+ instr->operands[1].skip = 0;
+
+ if (try_mov_wide_p)
+ {
+ /* Try the MOVZ alias. */
+ opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
+ aarch64_replace_opcode (instr, opcode);
+ if (aarch64_opcode_encode (instr->opcode, instr,
+ &instr->value, NULL, NULL))
+ {
+ put_aarch64_insn (buf, instr->value);
+ return;
+ }
+ /* Try the MOVK alias. */
+ opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
+ aarch64_replace_opcode (instr, opcode);
+ if (aarch64_opcode_encode (instr->opcode, instr,
+ &instr->value, NULL, NULL))
+ {
+ put_aarch64_insn (buf, instr->value);
+ return;
+ }
+ }
+
+ if (try_mov_bitmask_p)
+ {
+ /* Try the ORR alias. */
+ opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
+ aarch64_replace_opcode (instr, opcode);
+ if (aarch64_opcode_encode (instr->opcode, instr,
+ &instr->value, NULL, NULL))
+ {
+ put_aarch64_insn (buf, instr->value);
+ return;
+ }
+ }
+
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate cannot be moved by a single instruction"));
+}
+
+/* An instruction operand which is immediate related may have symbol used
+ in the assembly, e.g.
+
+ mov w0, u32
+ .set u32, 0x00ffff00
+
+ At the time when the assembly instruction is parsed, a referenced symbol,
+ like 'u32' in the above example may not have been seen; a fixS is created
+ in such a case and is handled here after symbols have been resolved.
+ Instruction is fixed up with VALUE using the information in *FIXP plus
+ extra information in FLAGS.
+
+ This function is called by md_apply_fix to fix up instructions that need
+ a fix-up described above but does not involve any linker-time relocation. */
+
+static void
+fix_insn (fixS *fixP, uint32_t flags, offsetT value)
+{
+ int idx;
+ uint32_t insn;
+ char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
+ enum aarch64_opnd opnd = fixP->tc_fix_data.opnd;
+ aarch64_inst *new_inst = fixP->tc_fix_data.inst;
+
+ if (new_inst)
+ {
+ /* Now the instruction is about to be fixed-up, so the operand that
+ was previously marked as 'ignored' needs to be unmarked in order
+ to get the encoding done properly. */
+ idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
+ new_inst->operands[idx].skip = 0;
+ }
+
+ gas_assert (opnd != AARCH64_OPND_NIL);
+
+ switch (opnd)
+ {
+ case AARCH64_OPND_EXCEPTION:
+ if (unsigned_overflow (value, 16))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate out of range"));
+ insn = get_aarch64_insn (buf);
+ insn |= encode_svc_imm (value);
+ put_aarch64_insn (buf, insn);
+ break;
+
+ case AARCH64_OPND_AIMM:
+ /* ADD or SUB with immediate.
+ NOTE this assumes we come here with a add/sub shifted reg encoding
+ 3 322|2222|2 2 2 21111 111111
+ 1 098|7654|3 2 1 09876 543210 98765 43210
+ 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
+ 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
+ 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
+ 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
+ ->
+ 3 322|2222|2 2 221111111111
+ 1 098|7654|3 2 109876543210 98765 43210
+ 11000000 sf 001|0001|shift imm12 Rn Rd ADD
+ 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
+ 51000000 sf 101|0001|shift imm12 Rn Rd SUB
+ 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
+ Fields sf Rn Rd are already set. */
+ insn = get_aarch64_insn (buf);
+ if (value < 0)
+ {
+ /* Add <-> sub. */
+ insn = reencode_addsub_switch_add_sub (insn);
+ value = -value;
+ }
+
+ if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0
+ && unsigned_overflow (value, 12))
+ {
+ /* Try to shift the value by 12 to make it fit. */
+ if (((value >> 12) << 12) == value
+ && ! unsigned_overflow (value, 12 + 12))
+ {
+ value >>= 12;
+ insn |= encode_addsub_imm_shift_amount (1);
+ }
+ }
+
+ if (unsigned_overflow (value, 12))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate out of range"));
+
+ insn |= encode_addsub_imm (value);
+
+ put_aarch64_insn (buf, insn);
+ break;
+
+ case AARCH64_OPND_SIMD_IMM:
+ case AARCH64_OPND_SIMD_IMM_SFT:
+ case AARCH64_OPND_LIMM:
+ /* Bit mask immediate. */
+ gas_assert (new_inst != NULL);
+ idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
+ new_inst->operands[idx].imm.value = value;
+ if (aarch64_opcode_encode (new_inst->opcode, new_inst,
+ &new_inst->value, NULL, NULL))
+ put_aarch64_insn (buf, new_inst->value);
+ else
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("invalid immediate"));
+ break;
+
+ case AARCH64_OPND_HALF:
+ /* 16-bit unsigned immediate. */
+ if (unsigned_overflow (value, 16))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate out of range"));
+ insn = get_aarch64_insn (buf);
+ insn |= encode_movw_imm (value & 0xffff);
+ put_aarch64_insn (buf, insn);
+ break;
+
+ case AARCH64_OPND_IMM_MOV:
+ /* Operand for a generic move immediate instruction, which is
+ an alias instruction that generates a single MOVZ, MOVN or ORR
+ instruction to loads a 32-bit/64-bit immediate value into general
+ register. An assembler error shall result if the immediate cannot be
+ created by a single one of these instructions. If there is a choice,
+ then to ensure reversability an assembler must prefer a MOVZ to MOVN,
+ and MOVZ or MOVN to ORR. */
+ gas_assert (new_inst != NULL);
+ fix_mov_imm_insn (fixP, buf, new_inst, value);
+ break;
+
+ case AARCH64_OPND_ADDR_SIMM7:
+ case AARCH64_OPND_ADDR_SIMM9:
+ case AARCH64_OPND_ADDR_SIMM9_2:
+ case AARCH64_OPND_ADDR_UIMM12:
+ /* Immediate offset in an address. */
+ insn = get_aarch64_insn (buf);
+
+ gas_assert (new_inst != NULL && new_inst->value == insn);
+ gas_assert (new_inst->opcode->operands[1] == opnd
+ || new_inst->opcode->operands[2] == opnd);
+
+ /* Get the index of the address operand. */
+ if (new_inst->opcode->operands[1] == opnd)
+ /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+ idx = 1;
+ else
+ /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
+ idx = 2;
+
+ /* Update the resolved offset value. */
+ new_inst->operands[idx].addr.offset.imm = value;
+
+ /* Encode/fix-up. */
+ if (aarch64_opcode_encode (new_inst->opcode, new_inst,
+ &new_inst->value, NULL, NULL))
+ {
+ put_aarch64_insn (buf, new_inst->value);
+ break;
+ }
+ else if (new_inst->opcode->iclass == ldst_pos
+ && try_to_encode_as_unscaled_ldst (new_inst))
+ {
+ put_aarch64_insn (buf, new_inst->value);
+ break;
+ }
+
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate offset out of range"));
+ break;
+
+ default:
+ gas_assert (0);
+ as_fatal (_("unhandled operand code %d"), opnd);
+ }
+}
+
+/* Apply a fixup (fixP) to segment data, once it has been determined
+ by our caller that we have all the info we need to fix it up.
+
+ Parameter valP is the pointer to the value of the bits. */
+
+void
+md_apply_fix (fixS * fixP, valueT * valP, segT seg)
+{
+ offsetT value = *valP;
+ uint32_t insn;
+ char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
+ int scale;
+ unsigned flags = fixP->fx_addnumber;
+
+ DEBUG_TRACE ("\n\n");
+ DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
+ DEBUG_TRACE ("Enter md_apply_fix");
+
+ gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
+
+ /* Note whether this will delete the relocation. */
+
+ if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
+ fixP->fx_done = 1;
+
+ /* Process the relocations. */
+ switch (fixP->fx_r_type)
+ {
+ case BFD_RELOC_NONE:
+ /* This will need to go in the object file. */
+ fixP->fx_done = 0;
+ break;
+
+ case BFD_RELOC_8:
+ case BFD_RELOC_8_PCREL:
+ if (fixP->fx_done || !seg->use_rela_p)
+ md_number_to_chars (buf, value, 1);
+ break;
+
+ case BFD_RELOC_16:
+ case BFD_RELOC_16_PCREL:
+ if (fixP->fx_done || !seg->use_rela_p)
+ md_number_to_chars (buf, value, 2);
+ break;
+
+ case BFD_RELOC_32:
+ case BFD_RELOC_32_PCREL:
+ if (fixP->fx_done || !seg->use_rela_p)
+ md_number_to_chars (buf, value, 4);
+ break;
+
+ case BFD_RELOC_64:
+ case BFD_RELOC_64_PCREL:
+ if (fixP->fx_done || !seg->use_rela_p)
+ md_number_to_chars (buf, value, 8);
+ break;
+
+ case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
+ /* We claim that these fixups have been processed here, even if
+ in fact we generate an error because we do not have a reloc
+ for them, so tc_gen_reloc() will reject them. */
+ fixP->fx_done = 1;
+ if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy))
+ {
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("undefined symbol %s used as an immediate value"),
+ S_GET_NAME (fixP->fx_addsy));
+ goto apply_fix_return;
+ }
+ fix_insn (fixP, flags, value);
+ break;
+
+ case BFD_RELOC_AARCH64_LD_LO19_PCREL:
+ if (value & 3)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("pc-relative load offset not word aligned"));
+ if (signed_overflow (value, 21))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("pc-relative load offset out of range"));
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ insn = get_aarch64_insn (buf);
+ insn |= encode_ld_lit_ofs_19 (value >> 2);
+ put_aarch64_insn (buf, insn);
+ }
+ break;
+
+ case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
+ if (signed_overflow (value, 21))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("pc-relative address offset out of range"));
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ insn = get_aarch64_insn (buf);
+ insn |= encode_adr_imm (value);
+ put_aarch64_insn (buf, insn);
+ }
+ break;
+
+ case BFD_RELOC_AARCH64_BRANCH19:
+ if (value & 3)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("conditional branch target not word aligned"));
+ if (signed_overflow (value, 21))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("conditional branch out of range"));
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ insn = get_aarch64_insn (buf);
+ insn |= encode_cond_branch_ofs_19 (value >> 2);
+ put_aarch64_insn (buf, insn);
+ }
+ break;
+
+ case BFD_RELOC_AARCH64_TSTBR14:
+ if (value & 3)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("conditional branch target not word aligned"));
+ if (signed_overflow (value, 16))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("conditional branch out of range"));
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ insn = get_aarch64_insn (buf);
+ insn |= encode_tst_branch_ofs_14 (value >> 2);
+ put_aarch64_insn (buf, insn);
+ }
+ break;
+
+ case BFD_RELOC_AARCH64_JUMP26:
+ case BFD_RELOC_AARCH64_CALL26:
+ if (value & 3)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("branch target not word aligned"));
+ if (signed_overflow (value, 28))
+ as_bad_where (fixP->fx_file, fixP->fx_line, _("branch out of range"));
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ insn = get_aarch64_insn (buf);
+ insn |= encode_branch_ofs_26 (value >> 2);
+ put_aarch64_insn (buf, insn);
+ }
+ break;
+
+ case BFD_RELOC_AARCH64_MOVW_G0:
+ case BFD_RELOC_AARCH64_MOVW_G0_S:
+ case BFD_RELOC_AARCH64_MOVW_G0_NC:
+ scale = 0;
+ goto movw_common;
+ case BFD_RELOC_AARCH64_MOVW_G1:
+ case BFD_RELOC_AARCH64_MOVW_G1_S:
+ case BFD_RELOC_AARCH64_MOVW_G1_NC:
+ scale = 16;
+ goto movw_common;
+ case BFD_RELOC_AARCH64_MOVW_G2:
+ case BFD_RELOC_AARCH64_MOVW_G2_S:
+ case BFD_RELOC_AARCH64_MOVW_G2_NC:
+ scale = 32;
+ goto movw_common;
+ case BFD_RELOC_AARCH64_MOVW_G3:
+ scale = 48;
+ movw_common:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ insn = get_aarch64_insn (buf);
+
+ if (!fixP->fx_done)
+ {
+ /* REL signed addend must fit in 16 bits */
+ if (signed_overflow (value, 16))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("offset out of range"));
+ }
+ else
+ {
+ /* Check for overflow and scale. */
+ switch (fixP->fx_r_type)
+ {
+ case BFD_RELOC_AARCH64_MOVW_G0:
+ case BFD_RELOC_AARCH64_MOVW_G1:
+ case BFD_RELOC_AARCH64_MOVW_G2:
+ case BFD_RELOC_AARCH64_MOVW_G3:
+ if (unsigned_overflow (value, scale + 16))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("unsigned value out of range"));
+ break;
+ case BFD_RELOC_AARCH64_MOVW_G0_S:
+ case BFD_RELOC_AARCH64_MOVW_G1_S:
+ case BFD_RELOC_AARCH64_MOVW_G2_S:
+ /* NOTE: We can only come here with movz or movn. */
+ if (signed_overflow (value, scale + 16))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("signed value out of range"));
+ if (value < 0)
+ {
+ /* Force use of MOVN. */
+ value = ~value;
+ insn = reencode_movzn_to_movn (insn);
+ }
+ else
+ {
+ /* Force use of MOVZ. */
+ insn = reencode_movzn_to_movz (insn);
+ }
+ break;
+ default:
+ /* Unchecked relocations. */
+ break;
+ }
+ value >>= scale;
+ }
+
+ /* Insert value into MOVN/MOVZ/MOVK instruction. */
+ insn |= encode_movw_imm (value & 0xffff);
+
+ put_aarch64_insn (buf, insn);
+ }
+ break;
+
+ case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
+ case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
+ case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
+ case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+ case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE:
+ case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
+ S_SET_THREAD_LOCAL (fixP->fx_addsy);
+ /* Should always be exported to object file, see
+ aarch64_force_relocation(). */
+ gas_assert (!fixP->fx_done);
+ gas_assert (seg->use_rela_p);
+ break;
+
+ case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
+ case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
+ case BFD_RELOC_AARCH64_ADD_LO12:
+ case BFD_RELOC_AARCH64_LDST8_LO12:
+ case BFD_RELOC_AARCH64_LDST16_LO12:
+ case BFD_RELOC_AARCH64_LDST32_LO12:
+ case BFD_RELOC_AARCH64_LDST64_LO12:
+ case BFD_RELOC_AARCH64_LDST128_LO12:
+ case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
+ case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
+ /* Should always be exported to object file, see
+ aarch64_force_relocation(). */
+ gas_assert (!fixP->fx_done);
+ gas_assert (seg->use_rela_p);
+ break;
+
+ case BFD_RELOC_AARCH64_TLSDESC_ADD:
+ case BFD_RELOC_AARCH64_TLSDESC_LDR:
+ case BFD_RELOC_AARCH64_TLSDESC_CALL:
+ break;
+
+ default:
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("unexpected %s fixup"),
+ bfd_get_reloc_code_name (fixP->fx_r_type));
+ break;
+ }
+
+apply_fix_return:
+ /* Free the allocated the struct aarch64_inst.
+ N.B. currently there are very limited number of fix-up types actually use
+ this field, so the impact on the performance should be minimal . */
+ if (fixP->tc_fix_data.inst != NULL)
+ free (fixP->tc_fix_data.inst);
+
+ return;
+}
+
+/* Translate internal representation of relocation info to BFD target
+ format. */
+
+arelent *
+tc_gen_reloc (asection * section, fixS * fixp)
+{
+ arelent *reloc;
+ bfd_reloc_code_real_type code;
+
+ reloc = xmalloc (sizeof (arelent));
+
+ reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+ reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+
+ if (fixp->fx_pcrel)
+ {
+ if (section->use_rela_p)
+ fixp->fx_offset -= md_pcrel_from_section (fixp, section);
+ else
+ fixp->fx_offset = reloc->address;
+ }
+ reloc->addend = fixp->fx_offset;
+
+ code = fixp->fx_r_type;
+ switch (code)
+ {
+ case BFD_RELOC_16:
+ if (fixp->fx_pcrel)
+ code = BFD_RELOC_16_PCREL;
+ break;
+
+ case BFD_RELOC_32:
+ if (fixp->fx_pcrel)
+ code = BFD_RELOC_32_PCREL;
+ break;
+
+ case BFD_RELOC_64:
+ if (fixp->fx_pcrel)
+ code = BFD_RELOC_64_PCREL;
+ break;
+
+ default:
+ break;
+ }
+
+ reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
+ if (reloc->howto == NULL)
+ {
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ _
+ ("cannot represent %s relocation in this object file format"),
+ bfd_get_reloc_code_name (code));
+ return NULL;
+ }
+
+ return reloc;
+}
+
+/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
+
+void
+cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp)
+{
+ bfd_reloc_code_real_type type;
+ int pcrel = 0;
+
+ /* Pick a reloc.
+ FIXME: @@ Should look at CPU word size. */
+ switch (size)
+ {
+ case 1:
+ type = BFD_RELOC_8;
+ break;
+ case 2:
+ type = BFD_RELOC_16;
+ break;
+ case 4:
+ type = BFD_RELOC_32;
+ break;
+ case 8:
+ type = BFD_RELOC_64;
+ break;
+ default:
+ as_bad (_("cannot do %u-byte relocation"), size);
+ type = BFD_RELOC_UNUSED;
+ break;
+ }
+
+ fix_new_exp (frag, where, (int) size, exp, pcrel, type);
+}
+
+int
+aarch64_force_relocation (struct fix *fixp)
+{
+ switch (fixp->fx_r_type)
+ {
+ case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
+ /* Perform these "immediate" internal relocations
+ even if the symbol is extern or weak. */
+ return 0;
+
+ case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
+ case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
+ case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
+ case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
+ case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+ case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE:
+ case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
+ case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
+ case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
+ case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
+ case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
+ case BFD_RELOC_AARCH64_ADD_LO12:
+ case BFD_RELOC_AARCH64_LDST8_LO12:
+ case BFD_RELOC_AARCH64_LDST16_LO12:
+ case BFD_RELOC_AARCH64_LDST32_LO12:
+ case BFD_RELOC_AARCH64_LDST64_LO12:
+ case BFD_RELOC_AARCH64_LDST128_LO12:
+ /* Always leave these relocations for the linker. */
+ return 1;
+
+ default:
+ break;
+ }
+
+ return generic_force_reloc (fixp);
+}
+
+#ifdef OBJ_ELF
+
+const char *
+elf64_aarch64_target_format (void)
+{
+ if (target_big_endian)
+ return "elf64-bigaarch64";
+ else
+ return "elf64-littleaarch64";
+}
+
+void
+aarch64elf_frob_symbol (symbolS * symp, int *puntp)
+{
+ elf_frob_symbol (symp, puntp);
+}
+#endif
+
+/* MD interface: Finalization. */
+
+/* A good place to do this, although this was probably not intended
+ for this kind of use. We need to dump the literal pool before
+ references are made to a null symbol pointer. */
+
+void
+aarch64_cleanup (void)
+{
+ literal_pool *pool;
+
+ for (pool = list_of_pools; pool; pool = pool->next)
+ {
+ /* Put it at the end of the relevant section. */
+ subseg_set (pool->section, pool->sub_section);
+ s_ltorg (0);
+ }
+}
+
+#ifdef OBJ_ELF
+/* Remove any excess mapping symbols generated for alignment frags in
+ SEC. We may have created a mapping symbol before a zero byte
+ alignment; remove it if there's a mapping symbol after the
+ alignment. */
+static void
+check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec,
+ void *dummy ATTRIBUTE_UNUSED)
+{
+ segment_info_type *seginfo = seg_info (sec);
+ fragS *fragp;
+
+ if (seginfo == NULL || seginfo->frchainP == NULL)
+ return;
+
+ for (fragp = seginfo->frchainP->frch_root;
+ fragp != NULL; fragp = fragp->fr_next)
+ {
+ symbolS *sym = fragp->tc_frag_data.last_map;
+ fragS *next = fragp->fr_next;
+
+ /* Variable-sized frags have been converted to fixed size by
+ this point. But if this was variable-sized to start with,
+ there will be a fixed-size frag after it. So don't handle
+ next == NULL. */
+ if (sym == NULL || next == NULL)
+ continue;
+
+ if (S_GET_VALUE (sym) < next->fr_address)
+ /* Not at the end of this frag. */
+ continue;
+ know (S_GET_VALUE (sym) == next->fr_address);
+
+ do
+ {
+ if (next->tc_frag_data.first_map != NULL)
+ {
+ /* Next frag starts with a mapping symbol. Discard this
+ one. */
+ symbol_remove (sym, &symbol_rootP, &symbol_lastP);
+ break;
+ }
+
+ if (next->fr_next == NULL)
+ {
+ /* This mapping symbol is at the end of the section. Discard
+ it. */
+ know (next->fr_fix == 0 && next->fr_var == 0);
+ symbol_remove (sym, &symbol_rootP, &symbol_lastP);
+ break;
+ }
+
+ /* As long as we have empty frags without any mapping symbols,
+ keep looking. */
+ /* If the next frag is non-empty and does not start with a
+ mapping symbol, then this mapping symbol is required. */
+ if (next->fr_address != next->fr_next->fr_address)
+ break;
+
+ next = next->fr_next;
+ }
+ while (next != NULL);
+ }
+}
+#endif
+
+/* Adjust the symbol table. */
+
+void
+aarch64_adjust_symtab (void)
+{
+#ifdef OBJ_ELF
+ /* Remove any overlapping mapping symbols generated by alignment frags. */
+ bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
+ /* Now do generic ELF adjustments. */
+ elf_adjust_symtab ();
+#endif
+}
+
+static void
+checked_hash_insert (struct hash_control *table, const char *key, void *value)
+{
+ const char *hash_err;
+
+ hash_err = hash_insert (table, key, value);
+ if (hash_err)
+ printf ("Internal Error: Can't hash %s\n", key);
+}
+
+static void
+fill_instruction_hash_table (void)
+{
+ aarch64_opcode *opcode = aarch64_opcode_table;
+
+ while (opcode->name != NULL)
+ {
+ templates *templ, *new_templ;
+ templ = hash_find (aarch64_ops_hsh, opcode->name);
+
+ new_templ = (templates *) xmalloc (sizeof (templates));
+ new_templ->opcode = opcode;
+ new_templ->next = NULL;
+
+ if (!templ)
+ checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ);
+ else
+ {
+ new_templ->next = templ->next;
+ templ->next = new_templ;
+ }
+ ++opcode;
+ }
+}
+
+static inline void
+convert_to_upper (char *dst, const char *src, size_t num)
+{
+ unsigned int i;
+ for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src)
+ *dst = TOUPPER (*src);
+ *dst = '\0';
+}
+
+/* Assume STR point to a lower-case string, allocate, convert and return
+ the corresponding upper-case string. */
+static inline const char*
+get_upper_str (const char *str)
+{
+ char *ret;
+ size_t len = strlen (str);
+ if ((ret = xmalloc (len + 1)) == NULL)
+ abort ();
+ convert_to_upper (ret, str, len);
+ return ret;
+}
+
+/* MD interface: Initialization. */
+
+void
+md_begin (void)
+{
+ unsigned mach;
+ unsigned int i;
+
+ if ((aarch64_ops_hsh = hash_new ()) == NULL
+ || (aarch64_cond_hsh = hash_new ()) == NULL
+ || (aarch64_shift_hsh = hash_new ()) == NULL
+ || (aarch64_sys_regs_hsh = hash_new ()) == NULL
+ || (aarch64_pstatefield_hsh = hash_new ()) == NULL
+ || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
+ || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
+ || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
+ || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
+ || (aarch64_reg_hsh = hash_new ()) == NULL
+ || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
+ || (aarch64_nzcv_hsh = hash_new ()) == NULL
+ || (aarch64_pldop_hsh = hash_new ()) == NULL)
+ as_fatal (_("virtual memory exhausted"));
+
+ fill_instruction_hash_table ();
+
+ for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
+ checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
+ (void *) (aarch64_sys_regs + i));
+
+ for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
+ checked_hash_insert (aarch64_pstatefield_hsh,
+ aarch64_pstatefields[i].name,
+ (void *) (aarch64_pstatefields + i));
+
+ for (i = 0; aarch64_sys_regs_ic[i].template != NULL; i++)
+ checked_hash_insert (aarch64_sys_regs_ic_hsh,
+ aarch64_sys_regs_ic[i].template,
+ (void *) (aarch64_sys_regs_ic + i));
+
+ for (i = 0; aarch64_sys_regs_dc[i].template != NULL; i++)
+ checked_hash_insert (aarch64_sys_regs_dc_hsh,
+ aarch64_sys_regs_dc[i].template,
+ (void *) (aarch64_sys_regs_dc + i));
+
+ for (i = 0; aarch64_sys_regs_at[i].template != NULL; i++)
+ checked_hash_insert (aarch64_sys_regs_at_hsh,
+ aarch64_sys_regs_at[i].template,
+ (void *) (aarch64_sys_regs_at + i));
+
+ for (i = 0; aarch64_sys_regs_tlbi[i].template != NULL; i++)
+ checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
+ aarch64_sys_regs_tlbi[i].template,
+ (void *) (aarch64_sys_regs_tlbi + i));
+
+ for (i = 0; i < ARRAY_SIZE (reg_names); i++)
+ checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
+ (void *) (reg_names + i));
+
+ for (i = 0; i < ARRAY_SIZE (nzcv_names); i++)
+ checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template,
+ (void *) (nzcv_names + i));
+
+ for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++)
+ {
+ const char *name = aarch64_operand_modifiers[i].name;
+ checked_hash_insert (aarch64_shift_hsh, name,
+ (void *) (aarch64_operand_modifiers + i));
+ /* Also hash the name in the upper case. */
+ checked_hash_insert (aarch64_shift_hsh, get_upper_str (name),
+ (void *) (aarch64_operand_modifiers + i));
+ }
+
+ for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++)
+ {
+ unsigned int j;
+ /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
+ the same condition code. */
+ for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j)
+ {
+ const char *name = aarch64_conds[i].names[j];
+ if (name == NULL)
+ break;
+ checked_hash_insert (aarch64_cond_hsh, name,
+ (void *) (aarch64_conds + i));
+ /* Also hash the name in the upper case. */
+ checked_hash_insert (aarch64_cond_hsh, get_upper_str (name),
+ (void *) (aarch64_conds + i));
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++)
+ {
+ const char *name = aarch64_barrier_options[i].name;
+ /* Skip xx00 - the unallocated values of option. */
+ if ((i & 0x3) == 0)
+ continue;
+ checked_hash_insert (aarch64_barrier_opt_hsh, name,
+ (void *) (aarch64_barrier_options + i));
+ /* Also hash the name in the upper case. */
+ checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
+ (void *) (aarch64_barrier_options + i));
+ }
+
+ for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
+ {
+ const char* name = aarch64_prfops[i].name;
+ /* Skip 0011x, 01xxx, 1011x and 11xxx - the unallocated hint encodings
+ as a 5-bit immediate #uimm5. */
+ if ((i & 0xf) >= 6)
+ continue;
+ checked_hash_insert (aarch64_pldop_hsh, name,
+ (void *) (aarch64_prfops + i));
+ /* Also hash the name in the upper case. */
+ checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
+ (void *) (aarch64_prfops + i));
+ }
+
+ /* Set the cpu variant based on the command-line options. */
+ if (!mcpu_cpu_opt)
+ mcpu_cpu_opt = march_cpu_opt;
+
+ if (!mcpu_cpu_opt)
+ mcpu_cpu_opt = &cpu_default;
+
+ cpu_variant = *mcpu_cpu_opt;
+
+ /* Record the CPU type. */
+ mach = bfd_mach_aarch64;
+
+ bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
+}
+
+/* Command line processing. */
+
+const char *md_shortopts = "m:";
+
+#ifdef AARCH64_BI_ENDIAN
+#define OPTION_EB (OPTION_MD_BASE + 0)
+#define OPTION_EL (OPTION_MD_BASE + 1)
+#else
+#if TARGET_BYTES_BIG_ENDIAN
+#define OPTION_EB (OPTION_MD_BASE + 0)
+#else
+#define OPTION_EL (OPTION_MD_BASE + 1)
+#endif
+#endif
+
+struct option md_longopts[] = {
+#ifdef OPTION_EB
+ {"EB", no_argument, NULL, OPTION_EB},
+#endif
+#ifdef OPTION_EL
+ {"EL", no_argument, NULL, OPTION_EL},
+#endif
+ {NULL, no_argument, NULL, 0}
+};
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+struct aarch64_option_table
+{
+ char *option; /* Option name to match. */
+ char *help; /* Help information. */
+ int *var; /* Variable to change. */
+ int value; /* What to change it to. */
+ char *deprecated; /* If non-null, print this message. */
+};
+
+static struct aarch64_option_table aarch64_opts[] = {
+ {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
+ {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
+ NULL},
+#ifdef DEBUG_AARCH64
+ {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL},
+#endif /* DEBUG_AARCH64 */
+ {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1,
+ NULL},
+ {NULL, NULL, NULL, 0, NULL}
+};
+
+struct aarch64_cpu_option_table
+{
+ char *name;
+ const aarch64_feature_set value;
+ /* The canonical name of the CPU, or NULL to use NAME converted to upper
+ case. */
+ const char *canonical_name;
+};
+
+/* This list should, at a minimum, contain all the cpu names
+ recognized by GCC. */
+static const struct aarch64_cpu_option_table aarch64_cpus[] = {
+ {"all", AARCH64_ANY, NULL},
+ {"generic", AARCH64_ARCH_V8, NULL},
+
+ /* These two are example CPUs supported in GCC, once we have real
+ CPUs they will be removed. */
+ {"example-1", AARCH64_ARCH_V8, NULL},
+ {"example-2", AARCH64_ARCH_V8, NULL},
+
+ {NULL, AARCH64_ARCH_NONE, NULL}
+};
+
+struct aarch64_arch_option_table
+{
+ char *name;
+ const aarch64_feature_set value;
+};
+
+/* This list should, at a minimum, contain all the architecture names
+ recognized by GCC. */
+static const struct aarch64_arch_option_table aarch64_archs[] = {
+ {"all", AARCH64_ANY},
+ {"armv8", AARCH64_ARCH_V8},
+ {NULL, AARCH64_ARCH_NONE}
+};
+
+/* ISA extensions. */
+struct aarch64_option_cpu_value_table
+{
+ char *name;
+ const aarch64_feature_set value;
+};
+
+static const struct aarch64_option_cpu_value_table aarch64_features[] = {
+ {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0)},
+ {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
+ {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
+ {NULL, AARCH64_ARCH_NONE}
+};
+
+struct aarch64_long_option_table
+{
+ char *option; /* Substring to match. */
+ char *help; /* Help information. */
+ int (*func) (char *subopt); /* Function to decode sub-option. */
+ char *deprecated; /* If non-null, print this message. */
+};
+
+static int
+aarch64_parse_features (char *str, const aarch64_feature_set **opt_p)
+{
+ /* We insist on extensions being added before being removed. We achieve
+ this by using the ADDING_VALUE variable to indicate whether we are
+ adding an extension (1) or removing it (0) and only allowing it to
+ change in the order -1 -> 1 -> 0. */
+ int adding_value = -1;
+ aarch64_feature_set *ext_set = xmalloc (sizeof (aarch64_feature_set));
+
+ /* Copy the feature set, so that we can modify it. */
+ *ext_set = **opt_p;
+ *opt_p = ext_set;
+
+ while (str != NULL && *str != 0)
+ {
+ const struct aarch64_option_cpu_value_table *opt;
+ char *ext;
+ int optlen;
+
+ if (*str != '+')
+ {
+ as_bad (_("invalid architectural extension"));
+ return 0;
+ }
+
+ str++;
+ ext = strchr (str, '+');
+
+ if (ext != NULL)
+ optlen = ext - str;
+ else
+ optlen = strlen (str);
+
+ if (optlen >= 2 && strncmp (str, "no", 2) == 0)
+ {
+ if (adding_value != 0)
+ adding_value = 0;
+ optlen -= 2;
+ str += 2;
+ }
+ else if (optlen > 0)
+ {
+ if (adding_value == -1)
+ adding_value = 1;
+ else if (adding_value != 1)
+ {
+ as_bad (_("must specify extensions to add before specifying "
+ "those to remove"));
+ return FALSE;
+ }
+ }
+
+ if (optlen == 0)
+ {
+ as_bad (_("missing architectural extension"));
+ return 0;
+ }
+
+ gas_assert (adding_value != -1);
+
+ for (opt = aarch64_features; opt->name != NULL; opt++)
+ if (strncmp (opt->name, str, optlen) == 0)
+ {
+ /* Add or remove the extension. */
+ if (adding_value)
+ AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
+ else
+ AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
+ break;
+ }
+
+ if (opt->name == NULL)
+ {
+ as_bad (_("unknown architectural extension `%s'"), str);
+ return 0;
+ }
+
+ str = ext;
+ };
+
+ return 1;
+}
+
+static int
+aarch64_parse_cpu (char *str)
+{
+ const struct aarch64_cpu_option_table *opt;
+ char *ext = strchr (str, '+');
+ size_t optlen;
+
+ if (ext != NULL)
+ optlen = ext - str;
+ else
+ optlen = strlen (str);
+
+ if (optlen == 0)
+ {
+ as_bad (_("missing cpu name `%s'"), str);
+ return 0;
+ }
+
+ for (opt = aarch64_cpus; opt->name != NULL; opt++)
+ if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
+ {
+ mcpu_cpu_opt = &opt->value;
+ if (ext != NULL)
+ return aarch64_parse_features (ext, &mcpu_cpu_opt);
+
+ return 1;
+ }
+
+ as_bad (_("unknown cpu `%s'"), str);
+ return 0;
+}
+
+static int
+aarch64_parse_arch (char *str)
+{
+ const struct aarch64_arch_option_table *opt;
+ char *ext = strchr (str, '+');
+ size_t optlen;
+
+ if (ext != NULL)
+ optlen = ext - str;
+ else
+ optlen = strlen (str);
+
+ if (optlen == 0)
+ {
+ as_bad (_("missing architecture name `%s'"), str);
+ return 0;
+ }
+
+ for (opt = aarch64_archs; opt->name != NULL; opt++)
+ if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
+ {
+ march_cpu_opt = &opt->value;
+ if (ext != NULL)
+ return aarch64_parse_features (ext, &march_cpu_opt);
+
+ return 1;
+ }
+
+ as_bad (_("unknown architecture `%s'\n"), str);
+ return 0;
+}
+
+static struct aarch64_long_option_table aarch64_long_opts[] = {
+ {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
+ aarch64_parse_cpu, NULL},
+ {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
+ aarch64_parse_arch, NULL},
+ {NULL, NULL, 0, NULL}
+};
+
+int
+md_parse_option (int c, char *arg)
+{
+ struct aarch64_option_table *opt;
+ struct aarch64_long_option_table *lopt;
+
+ switch (c)
+ {
+#ifdef OPTION_EB
+ case OPTION_EB:
+ target_big_endian = 1;
+ break;
+#endif
+
+#ifdef OPTION_EL
+ case OPTION_EL:
+ target_big_endian = 0;
+ break;
+#endif
+
+ case 'a':
+ /* Listing option. Just ignore these, we don't support additional
+ ones. */
+ return 0;
+
+ default:
+ for (opt = aarch64_opts; opt->option != NULL; opt++)
+ {
+ if (c == opt->option[0]
+ && ((arg == NULL && opt->option[1] == 0)
+ || streq (arg, opt->option + 1)))
+ {
+ /* If the option is deprecated, tell the user. */
+ if (opt->deprecated != NULL)
+ as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
+ arg ? arg : "", _(opt->deprecated));
+
+ if (opt->var != NULL)
+ *opt->var = opt->value;
+
+ return 1;
+ }
+ }
+
+ for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
+ {
+ /* These options are expected to have an argument. */
+ if (c == lopt->option[0]
+ && arg != NULL
+ && strncmp (arg, lopt->option + 1,
+ strlen (lopt->option + 1)) == 0)
+ {
+ /* If the option is deprecated, tell the user. */
+ if (lopt->deprecated != NULL)
+ as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
+ _(lopt->deprecated));
+
+ /* Call the sup-option parser. */
+ return lopt->func (arg + strlen (lopt->option) - 1);
+ }
+ }
+
+ return 0;
+ }
+
+ return 1;
+}
+
+void
+md_show_usage (FILE * fp)
+{
+ struct aarch64_option_table *opt;
+ struct aarch64_long_option_table *lopt;
+
+ fprintf (fp, _(" AArch64-specific assembler options:\n"));
+
+ for (opt = aarch64_opts; opt->option != NULL; opt++)
+ if (opt->help != NULL)
+ fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
+
+ for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
+ if (lopt->help != NULL)
+ fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
+
+#ifdef OPTION_EB
+ fprintf (fp, _("\
+ -EB assemble code for a big-endian cpu\n"));
+#endif
+
+#ifdef OPTION_EL
+ fprintf (fp, _("\
+ -EL assemble code for a little-endian cpu\n"));
+#endif
+}
+
+/* Parse a .cpu directive. */
+
+static void
+s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
+{
+ const struct aarch64_cpu_option_table *opt;
+ char saved_char;
+ char *name;
+ char *ext;
+ size_t optlen;
+
+ name = input_line_pointer;
+ while (*input_line_pointer && !ISSPACE (*input_line_pointer))
+ input_line_pointer++;
+ saved_char = *input_line_pointer;
+ *input_line_pointer = 0;
+
+ ext = strchr (name, '+');
+
+ if (ext != NULL)
+ optlen = ext - name;
+ else
+ optlen = strlen (name);
+
+ /* Skip the first "all" entry. */
+ for (opt = aarch64_cpus + 1; opt->name != NULL; opt++)
+ if (strlen (opt->name) == optlen
+ && strncmp (name, opt->name, optlen) == 0)
+ {
+ mcpu_cpu_opt = &opt->value;
+ if (ext != NULL)
+ if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
+ return;
+
+ cpu_variant = *mcpu_cpu_opt;
+
+ *input_line_pointer = saved_char;
+ demand_empty_rest_of_line ();
+ return;
+ }
+ as_bad (_("unknown cpu `%s'"), name);
+ *input_line_pointer = saved_char;
+ ignore_rest_of_line ();
+}
+
+
+/* Parse a .arch directive. */
+
+static void
+s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
+{
+ const struct aarch64_arch_option_table *opt;
+ char saved_char;
+ char *name;
+ char *ext;
+ size_t optlen;
+
+ name = input_line_pointer;
+ while (*input_line_pointer && !ISSPACE (*input_line_pointer))
+ input_line_pointer++;
+ saved_char = *input_line_pointer;
+ *input_line_pointer = 0;
+
+ ext = strchr (name, '+');
+
+ if (ext != NULL)
+ optlen = ext - name;
+ else
+ optlen = strlen (name);
+
+ /* Skip the first "all" entry. */
+ for (opt = aarch64_archs + 1; opt->name != NULL; opt++)
+ if (strlen (opt->name) == optlen
+ && strncmp (name, opt->name, optlen) == 0)
+ {
+ mcpu_cpu_opt = &opt->value;
+ if (ext != NULL)
+ if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
+ return;
+
+ cpu_variant = *mcpu_cpu_opt;
+
+ *input_line_pointer = saved_char;
+ demand_empty_rest_of_line ();
+ return;
+ }
+
+ as_bad (_("unknown architecture `%s'\n"), name);
+ *input_line_pointer = saved_char;
+ ignore_rest_of_line ();
+}
+
+/* Copy symbol information. */
+
+void
+aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
+{
+ AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);
+}
--- /dev/null
+/* tc-aarch64.h -- Header file for tc-aarch64.c.
+ Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#ifndef TC_AARCH64
+#define TC_AARCH64 1
+
+#include "opcode/aarch64.h"
+
+#ifndef TARGET_BYTES_BIG_ENDIAN
+#define TARGET_BYTES_BIG_ENDIAN 0
+#endif
+
+#define WORKING_DOT_WORD
+
+#define TARGET_ARCH bfd_arch_aarch64
+
+#define DIFF_EXPR_OK
+
+/* Permit // comments. */
+#define DOUBLESLASH_LINE_COMMENTS
+
+#ifdef LITTLE_ENDIAN
+#undef LITTLE_ENDIAN
+#endif
+
+#ifdef BIG_ENDIAN
+#undef BIG_ENDIAN
+#endif
+
+#define LITTLE_ENDIAN 1234
+#define BIG_ENDIAN 4321
+
+#define SWAP_32(n) \
+ ((((n) & 0xff) << 24) | (((n) & 0xff00) << 8) | (((n) >> 8) & 0xff00) \
+ | (((n) >> 24) & 0xff))
+
+struct fix;
+
+struct aarch64_fix
+{
+ struct aarch64_inst *inst;
+ enum aarch64_opnd opnd;
+};
+
+#if defined OBJ_ELF
+# define AARCH64_BI_ENDIAN
+# define TARGET_FORMAT elf64_aarch64_target_format ()
+#endif
+
+#define TC_FORCE_RELOCATION(FIX) aarch64_force_relocation (FIX)
+
+/* Currently there is no machine specific frags generated. */
+#define md_convert_frag(b,s,f) as_fatal ("aarch64 convert_frag called\n")
+
+#define md_cleanup() aarch64_cleanup ()
+
+#define md_start_line_hook() aarch64_start_line_hook ()
+
+#define tc_frob_label(S) aarch64_frob_label (S)
+
+/* We also need to mark assembler created symbols: */
+#define tc_frob_fake_label(S) aarch64_frob_label (S)
+
+#define TC_FIX_TYPE struct aarch64_fix
+#define TC_INIT_FIX_DATA(FIX) { (FIX)->tc_fix_data.inst = NULL; \
+ (FIX)->tc_fix_data.opnd = AARCH64_OPND_NIL; }
+
+#define TC_SYMFIELD_TYPE unsigned int
+#define AARCH64_GET_FLAG(s) (*symbol_get_tc (s))
+
+void aarch64_copy_symbol_attributes (symbolS *, symbolS *);
+#ifndef TC_COPY_SYMBOL_ATTRIBUTES
+#define TC_COPY_SYMBOL_ATTRIBUTES(DEST, SRC) \
+ (aarch64_copy_symbol_attributes (DEST, SRC))
+#endif
+
+#define TC_START_LABEL(C,S,STR) ((C) == ':' \
+ || ((C) == '/' && aarch64_data_in_code ()))
+#define tc_canonicalize_symbol_name(str) aarch64_canonicalize_symbol_name (str);
+#define obj_adjust_symtab() aarch64_adjust_symtab ()
+
+#define LISTING_HEADER "AARCH64 GAS "
+
+#define LOCAL_LABEL(name) (name[0] == '.' && name[1] == 'L')
+#define LOCAL_LABELS_FB 1
+
+/* This expression evaluates to true if the relocation is for a local
+ object for which we still want to do the relocation at runtime.
+ False if we are willing to perform this relocation while building
+ the .o file. GOTOFF does not need to be checked here because it is
+ not pcrel. I am not sure if some of the others are ever used with
+ pcrel, but it is easier to be safe than sorry. */
+
+#define TC_FORCE_RELOCATION_LOCAL(FIX) \
+ (!(FIX)->fx_pcrel \
+ || (FIX)->fx_r_type == BFD_RELOC_64 \
+ || (FIX)->fx_r_type == BFD_RELOC_32 \
+ || TC_FORCE_RELOCATION (FIX))
+
+#define TC_CONS_FIX_NEW cons_fix_new_aarch64
+
+/* Max code alignment is 32 bytes */
+#define MAX_MEM_FOR_RS_ALIGN_CODE 31
+
+/* For frags in code sections we need to record whether they contain
+ code or data. */
+struct aarch64_frag_type
+{
+ int recorded;
+#ifdef OBJ_ELF
+ /* If there is a mapping symbol at offset 0 in this frag,
+ it will be saved in FIRST_MAP. If there are any mapping
+ symbols in this frag, the last one will be saved in
+ LAST_MAP. */
+ symbolS *first_map, *last_map;
+#endif
+};
+
+#define TC_FRAG_TYPE struct aarch64_frag_type
+/* NOTE: max_chars is a local variable from frag_var / frag_variant. */
+#define TC_FRAG_INIT(fragp) aarch64_init_frag (fragp, max_chars)
+#define HANDLE_ALIGN(fragp) aarch64_handle_align (fragp)
+
+#define md_do_align(N, FILL, LEN, MAX, LABEL) \
+ if (FILL == NULL && (N) != 0 && ! need_pass_2 && subseg_text_p (now_seg)) \
+ { \
+ aarch64_frag_align_code (N, MAX); \
+ goto LABEL; \
+ }
+
+#define DWARF2_LINE_MIN_INSN_LENGTH 2
+
+/* The lr register is r30. */
+#define DWARF2_DEFAULT_RETURN_COLUMN 30
+
+/* Registers are generally saved at negative offsets to the CFA. */
+#define DWARF2_CIE_DATA_ALIGNMENT (-4)
+
+#ifdef OBJ_ELF
+# define obj_frob_symbol(sym, punt) aarch64elf_frob_symbol ((sym), & (punt))
+
+# define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
+# define TC_SEGMENT_INFO_TYPE struct aarch64_segment_info_type
+
+/* This is not really an alignment operation, but it's something we
+ need to do at the same time: whenever we are figuring out the
+ alignment for data, we should check whether a $d symbol is
+ necessary. */
+# define md_cons_align(nbytes) mapping_state (MAP_DATA)
+
+enum mstate
+{
+ MAP_UNDEFINED = 0, /* Must be zero, for seginfo in new sections. */
+ MAP_DATA,
+ MAP_INSN,
+};
+
+void mapping_state (enum mstate);
+
+struct aarch64_segment_info_type
+{
+ enum mstate mapstate;
+ unsigned int marked_pr_dependency;
+};
+
+/* We want .cfi_* pseudo-ops for generating unwind info. */
+#define TARGET_USE_CFIPOP 1
+
+/* CFI hooks. */
+#define tc_regname_to_dw2regnum tc_aarch64_regname_to_dw2regnum
+#define tc_cfi_frame_initial_instructions tc_aarch64_frame_initial_instructions
+
+#else /* Not OBJ_ELF. */
+#define GLOBAL_OFFSET_TABLE_NAME "__GLOBAL_OFFSET_TABLE_"
+#endif
+
+#if defined OBJ_ELF || defined OBJ_COFF
+
+# define EXTERN_FORCE_RELOC 1
+# define tc_fix_adjustable(FIX) 1
+/* Values passed to md_apply_fix don't include the symbol value. */
+# define MD_APPLY_SYM_VALUE(FIX) 0
+
+#endif
+
+#define MD_PCREL_FROM_SECTION(F,S) md_pcrel_from_section(F,S)
+
+extern long md_pcrel_from_section (struct fix *, segT);
+extern void aarch64_frag_align_code (int, int);
+extern const char * elf64_aarch64_target_format (void);
+extern int aarch64_force_relocation (struct fix *);
+extern void aarch64_cleanup (void);
+extern void aarch64_start_line_hook (void);
+extern void aarch64_frob_label (symbolS *);
+extern int aarch64_data_in_code (void);
+extern char * aarch64_canonicalize_symbol_name (char *);
+extern void aarch64_adjust_symtab (void);
+extern void aarch64elf_frob_symbol (symbolS *, int *);
+extern void cons_fix_new_aarch64 (fragS *, int, int, expressionS *);
+extern void aarch64_init_frag (struct frag *, int);
+extern void aarch64_handle_align (struct frag *);
+extern int tc_aarch64_regname_to_dw2regnum (char *regname);
+extern void tc_aarch64_frame_initial_instructions (void);
+
+#ifdef TE_PE
+
+#define O_secrel O_md1
+
+#define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset
+void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
+
+#endif /* TE_PE */
+
+#endif /* TC_AARCH64 */
# endian and arch.
# Note: This table is alpha-sorted, please try to keep it that way.
case ${cpu} in
+ aarch64) cpu_type=aarch64 endian=little ;;
+ aarch64_be) cpu_type=aarch64 endian=big ;;
alpha*) cpu_type=alpha ;;
am33_2.0) cpu_type=mn10300 endian=little ;;
arm*be|arm*b) cpu_type=arm endian=big ;;
generic_target=${cpu_type}-$vendor-$os
# Note: This table is alpha-sorted, please try to keep it that way.
case ${generic_target} in
+ aarch64*-*-elf) fmt=elf;;
+ aarch64*-*-linux*) fmt=elf em=linux ;;
+
alpha-*-*vms*) fmt=evax ;;
alpha-*-osf*) fmt=ecoff ;;
alpha-*-linuxecoff*) fmt=ecoff ;;
esac
case ${cpu_type} in
- alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k)
+ aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k)
bfd_gas=yes
;;
esac
chmod u+w ./asconfig.texi
CPU_DOCS = \
+ c-aarch64.texi \
c-alpha.texi \
c-arc.texi \
c-arm.texi \
DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \
$(as_TEXINFOS)
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
+am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
+ $(top_srcdir)/../config/zlib.m4 \
+ $(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/gettext-sister.m4 \
$(top_srcdir)/../config/largefile.m4 \
$(top_srcdir)/../config/plugins.m4 \
$(top_srcdir)/../config/po.m4 \
$(top_srcdir)/../config/progtest.m4 \
- $(top_srcdir)/../bfd/acinclude.m4 \
- $(top_srcdir)/../config/zlib.m4 \
- $(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/acinclude.m4 \
+ $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
+ $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
+ $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/acinclude.m4 \
$(top_srcdir)/configure.in
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
$(ACLOCAL_M4)
DATADIRNAME = @DATADIRNAME@
DEFS = @DEFS@
DEPDIR = @DEPDIR@
-DLLTOOL = @DLLTOOL@
DSYMUTIL = @DSYMUTIL@
DUMPBIN = @DUMPBIN@
ECHO_C = @ECHO_C@
LTLIBOBJS = @LTLIBOBJS@
MAINT = @MAINT@
MAKEINFO = @MAKEINFO@
-MANIFEST_TOOL = @MANIFEST_TOOL@
MKDIR_P = @MKDIR_P@
MKINSTALLDIRS = @MKINSTALLDIRS@
MSGFMT = @MSGFMT@
abs_srcdir = @abs_srcdir@
abs_top_builddir = @abs_top_builddir@
abs_top_srcdir = @abs_top_srcdir@
-ac_ct_AR = @ac_ct_AR@
ac_ct_CC = @ac_ct_CC@
ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
am__include = @am__include@
-I "$(top_srcdir)/../bfd/doc" -I ../../bfd/doc
CPU_DOCS = \
+ c-aarch64.texi \
c-alpha.texi \
c-arc.texi \
c-arm.texi \
@c CPUs of interest
@c ================
+@set AARCH64
@set ALPHA
@set ARC
@set ARM
@c
@c Target dependent options are listed below. Keep the list sorted.
@c Add an empty line for separation.
+@ifset AARCH64
+
+@emph{Target AArch64 options:}
+ [@b{-EB}|@b{-EL}]
+@end ifset
@ifset ALPHA
@emph{Target Alpha options:}
@end table
@c man end
+@ifset AARCH64
+
+@ifclear man
+@xref{AArch64 Options}, for the options available when @value{AS} is configured
+for the 64-bit mode of the ARM Architecture (AArch64).
+@end ifclear
+
+@ifset man
+@c man begin OPTIONS
+The following options are available when @value{AS} is configured for the
+64-bit mode of the ARM Architecture (AArch64).
+@c man end
+@c man begin INCLUDE
+@include c-aarch64.texi
+@c ended inside the included file
+@end ifset
+
+@end ifset
+
@ifset ALPHA
@ifclear man
subject, see the hardware manufacturer's manual.
@menu
+@ifset AARCH64
+* AArch64-Dependent:: AArch64 Dependent Features
+@end ifset
@ifset ALPHA
* Alpha-Dependent:: Alpha Dependent Features
@end ifset
@c node and sectioning commands; hence the repetition of @chapter BLAH
@c in both conditional blocks.
+@ifset AARCH64
+@include c-aarch64.texi
+@end ifset
+
@ifset ALPHA
@include c-alpha.texi
@end ifset
--- /dev/null
+@c Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+@c Contributed by ARM Ltd.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@c man end
+
+@ifset GENERIC
+@page
+@node AArch64-Dependent
+@chapter AArch64 Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter AArch64 Dependent Features
+@end ifclear
+
+@cindex AArch64 support
+@cindex Thumb support
+@menu
+* AArch64 Options:: Options
+* AArch64 Syntax:: Syntax
+* AArch64 Floating Point:: Floating Point
+* AArch64 Directives:: AArch64 Machine Directives
+* AArch64 Opcodes:: Opcodes
+* AArch64 Mapping Symbols:: Mapping Symbols
+@end menu
+
+@node AArch64 Options
+@section Options
+@cindex AArch64 options (none)
+@cindex options for AArch64 (none)
+
+@c man begin OPTIONS
+@table @gcctabopt
+
+@cindex @code{-EB} command line option, AArch64
+@item -EB
+This option specifies that the output generated by the assembler should
+be marked as being encoded for a big-endian processor.
+
+@cindex @code{-EL} command line option, AArch64
+@item -EL
+This option specifies that the output generated by the assembler should
+be marked as being encoded for a little-endian processor.
+
+@end table
+@c man end
+
+@node AArch64 Syntax
+@section Syntax
+@menu
+* AArch64-Chars:: Special Characters
+* AArch64-Regs:: Register Names
+* AArch64-Relocations:: Relocations
+@end menu
+
+@node AArch64-Chars
+@subsection Special Characters
+
+@cindex line comment character, AArch64
+@cindex AArch64 line comment character
+The presence of a @samp{//} on a line indicates the start of a comment
+that extends to the end of the current line. If a @samp{#} appears as
+the first character of a line, the whole line is treated as a comment.
+
+@cindex line separator, AArch64
+@cindex statement separator, AArch64
+@cindex AArch64 line separator
+The @samp{;} character can be used instead of a newline to separate
+statements.
+
+@cindex immediate character, AArch64
+@cindex AArch64 immediate character
+The @samp{#} can be optionally used to indicate immediate operands.
+
+@node AArch64-Regs
+@subsection Register Names
+
+@cindex AArch64 register names
+@cindex register names, AArch64
+Please refer to the section @samp{4.4 Register Names} of
+@samp{ARMv8 Instruction Set Overview}, which is available at
+@uref{http://infocenter.arm.com}.
+
+@node AArch64-Relocations
+@subsection Relocations
+
+@cindex relocations, AArch64
+@cindex AArch64 relocations
+@cindex MOVN, MOVZ and MOVK group relocations, AArch64
+Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
+by prefixing the label with @samp{#:abs_g2:} etc.
+For example to load the 48-bit absolute address of @var{foo} into x0:
+
+@smallexample
+ movz x0, #:abs_g2:foo // bits 32-47, overflow check
+ movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
+ movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
+@end smallexample
+
+@cindex ADRP, ADD, LDR/STR group relocations, AArch64
+Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
+instructions can be generated by prefixing the label with
+@samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
+
+For example to use 33-bit (+/-4GB) pc-relative addressing to
+load the address of @var{foo} into x0:
+
+@smallexample
+ adrp x0, #:pg_hi21:foo
+ add x0, x0, #:lo12:foo
+@end smallexample
+
+Or to load the value of @var{foo} into x0:
+
+@smallexample
+ adrp x0, #:pg_hi21:foo
+ ldr x0, [x0, #:lo12:foo]
+@end smallexample
+
+Note that @samp{#:pg_hi21:} is optional.
+
+@smallexample
+ adrp x0, foo
+@end smallexample
+
+is equivalent to
+
+@smallexample
+ adrp x0, #:pg_hi21:foo
+@end smallexample
+
+@node AArch64 Floating Point
+@section Floating Point
+
+@cindex floating point, AArch64 (@sc{ieee})
+@cindex AArch64 floating point (@sc{ieee})
+The AArch64 architecture uses @sc{ieee} floating-point numbers.
+
+@node AArch64 Directives
+@section AArch64 Machine Directives
+
+@cindex machine directives, AArch64
+@cindex AArch64 machine directives
+@table @code
+
+@c AAAAAAAAAAAAAAAAAAAAAAAAA
+@c BBBBBBBBBBBBBBBBBBBBBBBBBB
+
+@cindex @code{.bss} directive, AArch64
+@item .bss
+This directive switches to the @code{.bss} section.
+
+@c CCCCCCCCCCCCCCCCCCCCCCCCCC
+@c DDDDDDDDDDDDDDDDDDDDDDDDDD
+@c EEEEEEEEEEEEEEEEEEEEEEEEEE
+@c FFFFFFFFFFFFFFFFFFFFFFFFFF
+@c GGGGGGGGGGGGGGGGGGGGGGGGGG
+@c HHHHHHHHHHHHHHHHHHHHHHHHHH
+@c IIIIIIIIIIIIIIIIIIIIIIIIII
+@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
+@c KKKKKKKKKKKKKKKKKKKKKKKKKK
+@c LLLLLLLLLLLLLLLLLLLLLLLLLL
+
+@cindex @code{.ltorg} directive, AArch64
+@item .ltorg
+This directive causes the current contents of the literal pool to be
+dumped into the current section (which is assumed to be the .text
+section) at the current location (aligned to a word boundary).
+@code{GAS} maintains a separate literal pool for each section and each
+sub-section. The @code{.ltorg} directive will only affect the literal
+pool of the current section and sub-section. At the end of assembly
+all remaining, un-empty literal pools will automatically be dumped.
+
+Note - older versions of @code{GAS} would dump the current literal
+pool any time a section change occurred. This is no longer done, since
+it prevents accurate control of the placement of literal pools.
+
+@c MMMMMMMMMMMMMMMMMMMMMMMMMM
+
+@c NNNNNNNNNNNNNNNNNNNNNNNNNN
+@c OOOOOOOOOOOOOOOOOOOOOOOOOO
+
+@c PPPPPPPPPPPPPPPPPPPPPPPPPP
+
+@cindex @code{.pool} directive, AArch64
+@item .pool
+This is a synonym for .ltorg.
+
+@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
+@c RRRRRRRRRRRRRRRRRRRRRRRRRR
+
+@cindex @code{.req} directive, AArch64
+@item @var{name} .req @var{register name}
+This creates an alias for @var{register name} called @var{name}. For
+example:
+
+@smallexample
+ foo .req w0
+@end smallexample
+
+@c SSSSSSSSSSSSSSSSSSSSSSSSSS
+
+@c TTTTTTTTTTTTTTTTTTTTTTTTTT
+
+@c UUUUUUUUUUUUUUUUUUUUUUUUUU
+
+@cindex @code{.unreq} directive, AArch64
+@item .unreq @var{alias-name}
+This undefines a register alias which was previously defined using the
+@code{req} directive. For example:
+
+@smallexample
+ foo .req w0
+ .unreq foo
+@end smallexample
+
+An error occurs if the name is undefined. Note - this pseudo op can
+be used to delete builtin in register name aliases (eg 'w0'). This
+should only be done if it is really necessary.
+
+@c VVVVVVVVVVVVVVVVVVVVVVVVVV
+
+@c WWWWWWWWWWWWWWWWWWWWWWWWWW
+@c XXXXXXXXXXXXXXXXXXXXXXXXXX
+@c YYYYYYYYYYYYYYYYYYYYYYYYYY
+@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
+
+@end table
+
+@node AArch64 Opcodes
+@section Opcodes
+
+@cindex AArch64 opcodes
+@cindex opcodes for AArch64
+@code{@value{AS}} implements all the standard AArch64 opcodes. It also
+implements several pseudo opcodes, including several synthetic load
+instructions.
+
+@table @code
+
+@cindex @code{LDR reg,=<expr>} pseudo op, AArch64
+@item LDR =
+@smallexample
+ ldr <register> , =<expression>
+@end smallexample
+
+The constant expression will be placed into the nearest literal pool (if it not
+already there) and a PC-relative LDR instruction will be generated.
+
+@end table
+
+For more information on the AArch64 instruction set and assembly language
+notation, see @samp{ARMv8 Instruction Set Overview} available at
+@uref{http://infocenter.arm.com}.
+
+
+@node AArch64 Mapping Symbols
+@section Mapping Symbols
+
+The AArch64 ELF specification requires that special symbols be inserted
+into object files to mark certain features:
+
+@table @code
+
+@cindex @code{$x}
+@item $x
+At the start of a region of code containing AArch64 instructions.
+
+@cindex @code{$d}
+@item $d
+At the start of a region of data.
+
+@end table
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * gas/aarch64: New directory.
+ * gas/aarch64/aarch64.exp: New file.
+ * gas/aarch64/addsub.d: New file.
+ * gas/aarch64/addsub.s: New file.
+ * gas/aarch64/advsimd-across.d: New file.
+ * gas/aarch64/advsimd-across.s: New file.
+ * gas/aarch64/advsimd-misc.d: New file.
+ * gas/aarch64/advsimd-misc.s: New file.
+ * gas/aarch64/advsisd-copy.d: New file.
+ * gas/aarch64/advsisd-copy.s: New file.
+ * gas/aarch64/advsisd-misc.d: New file.
+ * gas/aarch64/advsisd-misc.s: New file.
+ * gas/aarch64/alias.d: New file.
+ * gas/aarch64/alias.s: New file.
+ * gas/aarch64/bitfield-alias.d: New file.
+ * gas/aarch64/bitfield-alias.s: New file.
+ * gas/aarch64/bitfield-bfm.d: New file.
+ * gas/aarch64/bitfield-bfm.s: New file.
+ * gas/aarch64/bitfield-dump: New file.
+ * gas/aarch64/bitfield-no-aliases.d: New file.
+ * gas/aarch64/crypto.d: New file.
+ * gas/aarch64/crypto.s: New file.
+ * gas/aarch64/diagnostic.d: New file.
+ * gas/aarch64/diagnostic.l: New file.
+ * gas/aarch64/diagnostic.s: New file.
+ * gas/aarch64/floatdp2.d: New file.
+ * gas/aarch64/floatdp2.s: New file.
+ * gas/aarch64/fp_cvt_int.d: New file.
+ * gas/aarch64/fp_cvt_int.s: New file.
+ * gas/aarch64/illegal-2.d: New file.
+ * gas/aarch64/illegal-2.l: New file.
+ * gas/aarch64/illegal-2.s: New file.
+ * gas/aarch64/illegal.d: New file.
+ * gas/aarch64/illegal.l: New file.
+ * gas/aarch64/illegal.s: New file.
+ * gas/aarch64/inst-directive.d: New file.
+ * gas/aarch64/inst-directive.s: New file.
+ * gas/aarch64/int-insns.d: New file.
+ * gas/aarch64/int-insns.s: New file.
+ * gas/aarch64/ldst-exclusive.d: New file.
+ * gas/aarch64/ldst-exclusive.s: New file.
+ * gas/aarch64/ldst-reg-imm-post-ind.d: New file.
+ * gas/aarch64/ldst-reg-imm-post-ind.s: New file.
+ * gas/aarch64/ldst-reg-imm-pre-ind.d: New file.
+ * gas/aarch64/ldst-reg-imm-pre-ind.s: New file.
+ * gas/aarch64/ldst-reg-pair.d: New file.
+ * gas/aarch64/ldst-reg-pair.s: New file.
+ * gas/aarch64/ldst-reg-reg-offset.d: New file.
+ * gas/aarch64/ldst-reg-reg-offset.s: New file.
+ * gas/aarch64/ldst-reg-uns-imm.d: New file.
+ * gas/aarch64/ldst-reg-uns-imm.s: New file.
+ * gas/aarch64/ldst-reg-unscaled-imm.d: New file.
+ * gas/aarch64/ldst-reg-unscaled-imm.s: New file.
+ * gas/aarch64/legacy_reg_names.d: New file.
+ * gas/aarch64/legacy_reg_names.l: New file.
+ * gas/aarch64/legacy_reg_names.s: New file.
+ * gas/aarch64/mapmisc.d: New file.
+ * gas/aarch64/mapmisc.dat: New file.
+ * gas/aarch64/mapmisc.s: New file.
+ * gas/aarch64/mapping.d: New file.
+ * gas/aarch64/mapping.s: New file.
+ * gas/aarch64/mapping2.d: New file.
+ * gas/aarch64/mapping2.s: New file.
+ * gas/aarch64/mapping3.d: New file.
+ * gas/aarch64/mapping3.s: New file.
+ * gas/aarch64/mapping4.d: New file.
+ * gas/aarch64/mapping4.s: New file.
+ * gas/aarch64/mov-no-aliases.d: New file.
+ * gas/aarch64/mov.d: New file.
+ * gas/aarch64/mov.s: New file.
+ * gas/aarch64/movi.d: New file.
+ * gas/aarch64/movi.s: New file.
+ * gas/aarch64/msr.d: New file.
+ * gas/aarch64/msr.s: New file.
+ * gas/aarch64/neon-fp-cvt-int.d: New file.
+ * gas/aarch64/neon-fp-cvt-int.s: New file.
+ * gas/aarch64/neon-frint.d: New file.
+ * gas/aarch64/neon-frint.s: New file.
+ * gas/aarch64/neon-ins.d: New file.
+ * gas/aarch64/neon-ins.s: New file.
+ * gas/aarch64/neon-not.d: New file.
+ * gas/aarch64/neon-not.s: New file.
+ * gas/aarch64/neon-vfp-reglist-post.d: New file.
+ * gas/aarch64/neon-vfp-reglist-post.s: New file.
+ * gas/aarch64/neon-vfp-reglist.d: New file.
+ * gas/aarch64/neon-vfp-reglist.s: New file.
+ * gas/aarch64/no-aliases.d: New file.
+ * gas/aarch64/optional.d: New file.
+ * gas/aarch64/optional.s: New file.
+ * gas/aarch64/programmer-friendly.d: New file.
+ * gas/aarch64/programmer-friendly.s: New file.
+ * gas/aarch64/reloc-data.d: New file.
+ * gas/aarch64/reloc-data.s: New file.
+ * gas/aarch64/reloc-insn.d: New file.
+ * gas/aarch64/reloc-insn.s: New file.
+ * gas/aarch64/shifted.d: New file.
+ * gas/aarch64/shifted.s: New file.
+ * gas/aarch64/symbol.d: New file.
+ * gas/aarch64/symbol.s: New file.
+ * gas/aarch64/sysreg-1.d: New file.
+ * gas/aarch64/sysreg-1.s: New file.
+ * gas/aarch64/sysreg.d: New file.
+ * gas/aarch64/sysreg.s: New file.
+ * gas/aarch64/system.d: New file.
+ * gas/aarch64/system.s: New file.
+ * gas/aarch64/tlbi_op.d: New file.
+ * gas/aarch64/tlbi_op.s: New file.
+ * gas/aarch64/tls.d: New file.
+ * gas/aarch64/tls.s: New file.
+ * gas/aarch64/verbose-error.d: New file.
+ * gas/aarch64/verbose-error.l: New file.
+ * gas/aarch64/verbose-error.s: New file.
+
2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
PR gas/14423
--- /dev/null
+#
+# Some AArch64 tests
+#
+
+if {[istarget aarch64*-*-*]} {
+ run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+}
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 0b0100f0 add w16, w7, w1
+ 4: 0b2100f0 add w16, w7, w1, uxtb
+ 8: 0b2100f0 add w16, w7, w1, uxtb
+ c: 0b2104f0 add w16, w7, w1, uxtb #1
+ 10: 0b2108f0 add w16, w7, w1, uxtb #2
+ 14: 0b210cf0 add w16, w7, w1, uxtb #3
+ 18: 0b2110f0 add w16, w7, w1, uxtb #4
+ 1c: 0b2120f0 add w16, w7, w1, uxth
+ 20: 0b2120f0 add w16, w7, w1, uxth
+ 24: 0b2124f0 add w16, w7, w1, uxth #1
+ 28: 0b2128f0 add w16, w7, w1, uxth #2
+ 2c: 0b212cf0 add w16, w7, w1, uxth #3
+ 30: 0b2130f0 add w16, w7, w1, uxth #4
+ 34: 0b2140f0 add w16, w7, w1, uxtw
+ 38: 0b2140f0 add w16, w7, w1, uxtw
+ 3c: 0b2144f0 add w16, w7, w1, uxtw #1
+ 40: 0b2148f0 add w16, w7, w1, uxtw #2
+ 44: 0b214cf0 add w16, w7, w1, uxtw #3
+ 48: 0b2150f0 add w16, w7, w1, uxtw #4
+ 4c: 0b2160f0 add w16, w7, w1, uxtx
+ 50: 0b2160f0 add w16, w7, w1, uxtx
+ 54: 0b2164f0 add w16, w7, w1, uxtx #1
+ 58: 0b2168f0 add w16, w7, w1, uxtx #2
+ 5c: 0b216cf0 add w16, w7, w1, uxtx #3
+ 60: 0b2170f0 add w16, w7, w1, uxtx #4
+ 64: 0b2180f0 add w16, w7, w1, sxtb
+ 68: 0b2180f0 add w16, w7, w1, sxtb
+ 6c: 0b2184f0 add w16, w7, w1, sxtb #1
+ 70: 0b2188f0 add w16, w7, w1, sxtb #2
+ 74: 0b218cf0 add w16, w7, w1, sxtb #3
+ 78: 0b2190f0 add w16, w7, w1, sxtb #4
+ 7c: 0b21a0f0 add w16, w7, w1, sxth
+ 80: 0b21a0f0 add w16, w7, w1, sxth
+ 84: 0b21a4f0 add w16, w7, w1, sxth #1
+ 88: 0b21a8f0 add w16, w7, w1, sxth #2
+ 8c: 0b21acf0 add w16, w7, w1, sxth #3
+ 90: 0b21b0f0 add w16, w7, w1, sxth #4
+ 94: 0b21c0f0 add w16, w7, w1, sxtw
+ 98: 0b21c0f0 add w16, w7, w1, sxtw
+ 9c: 0b21c4f0 add w16, w7, w1, sxtw #1
+ a0: 0b21c8f0 add w16, w7, w1, sxtw #2
+ a4: 0b21ccf0 add w16, w7, w1, sxtw #3
+ a8: 0b21d0f0 add w16, w7, w1, sxtw #4
+ ac: 0b21e0f0 add w16, w7, w1, sxtx
+ b0: 0b21e0f0 add w16, w7, w1, sxtx
+ b4: 0b21e4f0 add w16, w7, w1, sxtx #1
+ b8: 0b21e8f0 add w16, w7, w1, sxtx #2
+ bc: 0b21ecf0 add w16, w7, w1, sxtx #3
+ c0: 0b21f0f0 add w16, w7, w1, sxtx #4
+ c4: 0b0100f0 add w16, w7, w1
+ c8: 0b0104f0 add w16, w7, w1, lsl #1
+ cc: 0b0108f0 add w16, w7, w1, lsl #2
+ d0: 0b010cf0 add w16, w7, w1, lsl #3
+ d4: 0b0110f0 add w16, w7, w1, lsl #4
+ d8: 0b2143f0 add w16, wsp, w1
+ dc: 0b2103f0 add w16, wsp, w1, uxtb
+ e0: 0b2103f0 add w16, wsp, w1, uxtb
+ e4: 0b2107f0 add w16, wsp, w1, uxtb #1
+ e8: 0b210bf0 add w16, wsp, w1, uxtb #2
+ ec: 0b210ff0 add w16, wsp, w1, uxtb #3
+ f0: 0b2113f0 add w16, wsp, w1, uxtb #4
+ f4: 0b2123f0 add w16, wsp, w1, uxth
+ f8: 0b2123f0 add w16, wsp, w1, uxth
+ fc: 0b2127f0 add w16, wsp, w1, uxth #1
+ 100: 0b212bf0 add w16, wsp, w1, uxth #2
+ 104: 0b212ff0 add w16, wsp, w1, uxth #3
+ 108: 0b2133f0 add w16, wsp, w1, uxth #4
+ 10c: 0b2143f0 add w16, wsp, w1
+ 110: 0b2143f0 add w16, wsp, w1
+ 114: 0b2147f0 add w16, wsp, w1, lsl #1
+ 118: 0b214bf0 add w16, wsp, w1, lsl #2
+ 11c: 0b214ff0 add w16, wsp, w1, lsl #3
+ 120: 0b2153f0 add w16, wsp, w1, lsl #4
+ 124: 0b2163f0 add w16, wsp, w1, uxtx
+ 128: 0b2163f0 add w16, wsp, w1, uxtx
+ 12c: 0b2167f0 add w16, wsp, w1, uxtx #1
+ 130: 0b216bf0 add w16, wsp, w1, uxtx #2
+ 134: 0b216ff0 add w16, wsp, w1, uxtx #3
+ 138: 0b2173f0 add w16, wsp, w1, uxtx #4
+ 13c: 0b2183f0 add w16, wsp, w1, sxtb
+ 140: 0b2183f0 add w16, wsp, w1, sxtb
+ 144: 0b2187f0 add w16, wsp, w1, sxtb #1
+ 148: 0b218bf0 add w16, wsp, w1, sxtb #2
+ 14c: 0b218ff0 add w16, wsp, w1, sxtb #3
+ 150: 0b2193f0 add w16, wsp, w1, sxtb #4
+ 154: 0b21a3f0 add w16, wsp, w1, sxth
+ 158: 0b21a3f0 add w16, wsp, w1, sxth
+ 15c: 0b21a7f0 add w16, wsp, w1, sxth #1
+ 160: 0b21abf0 add w16, wsp, w1, sxth #2
+ 164: 0b21aff0 add w16, wsp, w1, sxth #3
+ 168: 0b21b3f0 add w16, wsp, w1, sxth #4
+ 16c: 0b21c3f0 add w16, wsp, w1, sxtw
+ 170: 0b21c3f0 add w16, wsp, w1, sxtw
+ 174: 0b21c7f0 add w16, wsp, w1, sxtw #1
+ 178: 0b21cbf0 add w16, wsp, w1, sxtw #2
+ 17c: 0b21cff0 add w16, wsp, w1, sxtw #3
+ 180: 0b21d3f0 add w16, wsp, w1, sxtw #4
+ 184: 0b21e3f0 add w16, wsp, w1, sxtx
+ 188: 0b21e3f0 add w16, wsp, w1, sxtx
+ 18c: 0b21e7f0 add w16, wsp, w1, sxtx #1
+ 190: 0b21ebf0 add w16, wsp, w1, sxtx #2
+ 194: 0b21eff0 add w16, wsp, w1, sxtx #3
+ 198: 0b21f3f0 add w16, wsp, w1, sxtx #4
+ 19c: 0b2143f0 add w16, wsp, w1
+ 1a0: 0b2147f0 add w16, wsp, w1, lsl #1
+ 1a4: 0b214bf0 add w16, wsp, w1, lsl #2
+ 1a8: 0b214ff0 add w16, wsp, w1, lsl #3
+ 1ac: 0b2153f0 add w16, wsp, w1, lsl #4
+ 1b0: 8b0100f0 add x16, x7, x1
+ 1b4: 8b2100f0 add x16, x7, w1, uxtb
+ 1b8: 8b2100f0 add x16, x7, w1, uxtb
+ 1bc: 8b2104f0 add x16, x7, w1, uxtb #1
+ 1c0: 8b2108f0 add x16, x7, w1, uxtb #2
+ 1c4: 8b210cf0 add x16, x7, w1, uxtb #3
+ 1c8: 8b2110f0 add x16, x7, w1, uxtb #4
+ 1cc: 8b2120f0 add x16, x7, w1, uxth
+ 1d0: 8b2120f0 add x16, x7, w1, uxth
+ 1d4: 8b2124f0 add x16, x7, w1, uxth #1
+ 1d8: 8b2128f0 add x16, x7, w1, uxth #2
+ 1dc: 8b212cf0 add x16, x7, w1, uxth #3
+ 1e0: 8b2130f0 add x16, x7, w1, uxth #4
+ 1e4: 8b2140f0 add x16, x7, w1, uxtw
+ 1e8: 8b2140f0 add x16, x7, w1, uxtw
+ 1ec: 8b2144f0 add x16, x7, w1, uxtw #1
+ 1f0: 8b2148f0 add x16, x7, w1, uxtw #2
+ 1f4: 8b214cf0 add x16, x7, w1, uxtw #3
+ 1f8: 8b2150f0 add x16, x7, w1, uxtw #4
+ 1fc: 8b2160f0 add x16, x7, x1, uxtx
+ 200: 8b2160f0 add x16, x7, x1, uxtx
+ 204: 8b2164f0 add x16, x7, x1, uxtx #1
+ 208: 8b2168f0 add x16, x7, x1, uxtx #2
+ 20c: 8b216cf0 add x16, x7, x1, uxtx #3
+ 210: 8b2170f0 add x16, x7, x1, uxtx #4
+ 214: 8b2180f0 add x16, x7, w1, sxtb
+ 218: 8b2180f0 add x16, x7, w1, sxtb
+ 21c: 8b2184f0 add x16, x7, w1, sxtb #1
+ 220: 8b2188f0 add x16, x7, w1, sxtb #2
+ 224: 8b218cf0 add x16, x7, w1, sxtb #3
+ 228: 8b2190f0 add x16, x7, w1, sxtb #4
+ 22c: 8b21a0f0 add x16, x7, w1, sxth
+ 230: 8b21a0f0 add x16, x7, w1, sxth
+ 234: 8b21a4f0 add x16, x7, w1, sxth #1
+ 238: 8b21a8f0 add x16, x7, w1, sxth #2
+ 23c: 8b21acf0 add x16, x7, w1, sxth #3
+ 240: 8b21b0f0 add x16, x7, w1, sxth #4
+ 244: 8b21c0f0 add x16, x7, w1, sxtw
+ 248: 8b21c0f0 add x16, x7, w1, sxtw
+ 24c: 8b21c4f0 add x16, x7, w1, sxtw #1
+ 250: 8b21c8f0 add x16, x7, w1, sxtw #2
+ 254: 8b21ccf0 add x16, x7, w1, sxtw #3
+ 258: 8b21d0f0 add x16, x7, w1, sxtw #4
+ 25c: 8b21e0f0 add x16, x7, x1, sxtx
+ 260: 8b21e0f0 add x16, x7, x1, sxtx
+ 264: 8b21e4f0 add x16, x7, x1, sxtx #1
+ 268: 8b21e8f0 add x16, x7, x1, sxtx #2
+ 26c: 8b21ecf0 add x16, x7, x1, sxtx #3
+ 270: 8b21f0f0 add x16, x7, x1, sxtx #4
+ 274: 8b0100f0 add x16, x7, x1
+ 278: 8b0104f0 add x16, x7, x1, lsl #1
+ 27c: 8b0108f0 add x16, x7, x1, lsl #2
+ 280: 8b010cf0 add x16, x7, x1, lsl #3
+ 284: 8b0110f0 add x16, x7, x1, lsl #4
+ 288: 8b2163f0 add x16, sp, x1
+ 28c: 8b2103f0 add x16, sp, w1, uxtb
+ 290: 8b2103f0 add x16, sp, w1, uxtb
+ 294: 8b2107f0 add x16, sp, w1, uxtb #1
+ 298: 8b210bf0 add x16, sp, w1, uxtb #2
+ 29c: 8b210ff0 add x16, sp, w1, uxtb #3
+ 2a0: 8b2113f0 add x16, sp, w1, uxtb #4
+ 2a4: 8b2123f0 add x16, sp, w1, uxth
+ 2a8: 8b2123f0 add x16, sp, w1, uxth
+ 2ac: 8b2127f0 add x16, sp, w1, uxth #1
+ 2b0: 8b212bf0 add x16, sp, w1, uxth #2
+ 2b4: 8b212ff0 add x16, sp, w1, uxth #3
+ 2b8: 8b2133f0 add x16, sp, w1, uxth #4
+ 2bc: 8b2143f0 add x16, sp, w1, uxtw
+ 2c0: 8b2143f0 add x16, sp, w1, uxtw
+ 2c4: 8b2147f0 add x16, sp, w1, uxtw #1
+ 2c8: 8b214bf0 add x16, sp, w1, uxtw #2
+ 2cc: 8b214ff0 add x16, sp, w1, uxtw #3
+ 2d0: 8b2153f0 add x16, sp, w1, uxtw #4
+ 2d4: 8b2163f0 add x16, sp, x1
+ 2d8: 8b2163f0 add x16, sp, x1
+ 2dc: 8b2167f0 add x16, sp, x1, lsl #1
+ 2e0: 8b216bf0 add x16, sp, x1, lsl #2
+ 2e4: 8b216ff0 add x16, sp, x1, lsl #3
+ 2e8: 8b2173f0 add x16, sp, x1, lsl #4
+ 2ec: 8b2183f0 add x16, sp, w1, sxtb
+ 2f0: 8b2183f0 add x16, sp, w1, sxtb
+ 2f4: 8b2187f0 add x16, sp, w1, sxtb #1
+ 2f8: 8b218bf0 add x16, sp, w1, sxtb #2
+ 2fc: 8b218ff0 add x16, sp, w1, sxtb #3
+ 300: 8b2193f0 add x16, sp, w1, sxtb #4
+ 304: 8b21a3f0 add x16, sp, w1, sxth
+ 308: 8b21a3f0 add x16, sp, w1, sxth
+ 30c: 8b21a7f0 add x16, sp, w1, sxth #1
+ 310: 8b21abf0 add x16, sp, w1, sxth #2
+ 314: 8b21aff0 add x16, sp, w1, sxth #3
+ 318: 8b21b3f0 add x16, sp, w1, sxth #4
+ 31c: 8b21c3f0 add x16, sp, w1, sxtw
+ 320: 8b21c3f0 add x16, sp, w1, sxtw
+ 324: 8b21c7f0 add x16, sp, w1, sxtw #1
+ 328: 8b21cbf0 add x16, sp, w1, sxtw #2
+ 32c: 8b21cff0 add x16, sp, w1, sxtw #3
+ 330: 8b21d3f0 add x16, sp, w1, sxtw #4
+ 334: 8b21e3f0 add x16, sp, x1, sxtx
+ 338: 8b21e3f0 add x16, sp, x1, sxtx
+ 33c: 8b21e7f0 add x16, sp, x1, sxtx #1
+ 340: 8b21ebf0 add x16, sp, x1, sxtx #2
+ 344: 8b21eff0 add x16, sp, x1, sxtx #3
+ 348: 8b21f3f0 add x16, sp, x1, sxtx #4
+ 34c: 8b2163f0 add x16, sp, x1
+ 350: 8b2167f0 add x16, sp, x1, lsl #1
+ 354: 8b216bf0 add x16, sp, x1, lsl #2
+ 358: 8b216ff0 add x16, sp, x1, lsl #3
+ 35c: 8b2173f0 add x16, sp, x1, lsl #4
+ 360: 2b0100f0 adds w16, w7, w1
+ 364: 2b2100f0 adds w16, w7, w1, uxtb
+ 368: 2b2100f0 adds w16, w7, w1, uxtb
+ 36c: 2b2104f0 adds w16, w7, w1, uxtb #1
+ 370: 2b2108f0 adds w16, w7, w1, uxtb #2
+ 374: 2b210cf0 adds w16, w7, w1, uxtb #3
+ 378: 2b2110f0 adds w16, w7, w1, uxtb #4
+ 37c: 2b2120f0 adds w16, w7, w1, uxth
+ 380: 2b2120f0 adds w16, w7, w1, uxth
+ 384: 2b2124f0 adds w16, w7, w1, uxth #1
+ 388: 2b2128f0 adds w16, w7, w1, uxth #2
+ 38c: 2b212cf0 adds w16, w7, w1, uxth #3
+ 390: 2b2130f0 adds w16, w7, w1, uxth #4
+ 394: 2b2140f0 adds w16, w7, w1, uxtw
+ 398: 2b2140f0 adds w16, w7, w1, uxtw
+ 39c: 2b2144f0 adds w16, w7, w1, uxtw #1
+ 3a0: 2b2148f0 adds w16, w7, w1, uxtw #2
+ 3a4: 2b214cf0 adds w16, w7, w1, uxtw #3
+ 3a8: 2b2150f0 adds w16, w7, w1, uxtw #4
+ 3ac: 2b2160f0 adds w16, w7, w1, uxtx
+ 3b0: 2b2160f0 adds w16, w7, w1, uxtx
+ 3b4: 2b2164f0 adds w16, w7, w1, uxtx #1
+ 3b8: 2b2168f0 adds w16, w7, w1, uxtx #2
+ 3bc: 2b216cf0 adds w16, w7, w1, uxtx #3
+ 3c0: 2b2170f0 adds w16, w7, w1, uxtx #4
+ 3c4: 2b2180f0 adds w16, w7, w1, sxtb
+ 3c8: 2b2180f0 adds w16, w7, w1, sxtb
+ 3cc: 2b2184f0 adds w16, w7, w1, sxtb #1
+ 3d0: 2b2188f0 adds w16, w7, w1, sxtb #2
+ 3d4: 2b218cf0 adds w16, w7, w1, sxtb #3
+ 3d8: 2b2190f0 adds w16, w7, w1, sxtb #4
+ 3dc: 2b21a0f0 adds w16, w7, w1, sxth
+ 3e0: 2b21a0f0 adds w16, w7, w1, sxth
+ 3e4: 2b21a4f0 adds w16, w7, w1, sxth #1
+ 3e8: 2b21a8f0 adds w16, w7, w1, sxth #2
+ 3ec: 2b21acf0 adds w16, w7, w1, sxth #3
+ 3f0: 2b21b0f0 adds w16, w7, w1, sxth #4
+ 3f4: 2b21c0f0 adds w16, w7, w1, sxtw
+ 3f8: 2b21c0f0 adds w16, w7, w1, sxtw
+ 3fc: 2b21c4f0 adds w16, w7, w1, sxtw #1
+ 400: 2b21c8f0 adds w16, w7, w1, sxtw #2
+ 404: 2b21ccf0 adds w16, w7, w1, sxtw #3
+ 408: 2b21d0f0 adds w16, w7, w1, sxtw #4
+ 40c: 2b21e0f0 adds w16, w7, w1, sxtx
+ 410: 2b21e0f0 adds w16, w7, w1, sxtx
+ 414: 2b21e4f0 adds w16, w7, w1, sxtx #1
+ 418: 2b21e8f0 adds w16, w7, w1, sxtx #2
+ 41c: 2b21ecf0 adds w16, w7, w1, sxtx #3
+ 420: 2b21f0f0 adds w16, w7, w1, sxtx #4
+ 424: 2b0100f0 adds w16, w7, w1
+ 428: 2b0104f0 adds w16, w7, w1, lsl #1
+ 42c: 2b0108f0 adds w16, w7, w1, lsl #2
+ 430: 2b010cf0 adds w16, w7, w1, lsl #3
+ 434: 2b0110f0 adds w16, w7, w1, lsl #4
+ 438: 2b2143f0 adds w16, wsp, w1
+ 43c: 2b2103f0 adds w16, wsp, w1, uxtb
+ 440: 2b2103f0 adds w16, wsp, w1, uxtb
+ 444: 2b2107f0 adds w16, wsp, w1, uxtb #1
+ 448: 2b210bf0 adds w16, wsp, w1, uxtb #2
+ 44c: 2b210ff0 adds w16, wsp, w1, uxtb #3
+ 450: 2b2113f0 adds w16, wsp, w1, uxtb #4
+ 454: 2b2123f0 adds w16, wsp, w1, uxth
+ 458: 2b2123f0 adds w16, wsp, w1, uxth
+ 45c: 2b2127f0 adds w16, wsp, w1, uxth #1
+ 460: 2b212bf0 adds w16, wsp, w1, uxth #2
+ 464: 2b212ff0 adds w16, wsp, w1, uxth #3
+ 468: 2b2133f0 adds w16, wsp, w1, uxth #4
+ 46c: 2b2143f0 adds w16, wsp, w1
+ 470: 2b2143f0 adds w16, wsp, w1
+ 474: 2b2147f0 adds w16, wsp, w1, lsl #1
+ 478: 2b214bf0 adds w16, wsp, w1, lsl #2
+ 47c: 2b214ff0 adds w16, wsp, w1, lsl #3
+ 480: 2b2153f0 adds w16, wsp, w1, lsl #4
+ 484: 2b2163f0 adds w16, wsp, w1, uxtx
+ 488: 2b2163f0 adds w16, wsp, w1, uxtx
+ 48c: 2b2167f0 adds w16, wsp, w1, uxtx #1
+ 490: 2b216bf0 adds w16, wsp, w1, uxtx #2
+ 494: 2b216ff0 adds w16, wsp, w1, uxtx #3
+ 498: 2b2173f0 adds w16, wsp, w1, uxtx #4
+ 49c: 2b2183f0 adds w16, wsp, w1, sxtb
+ 4a0: 2b2183f0 adds w16, wsp, w1, sxtb
+ 4a4: 2b2187f0 adds w16, wsp, w1, sxtb #1
+ 4a8: 2b218bf0 adds w16, wsp, w1, sxtb #2
+ 4ac: 2b218ff0 adds w16, wsp, w1, sxtb #3
+ 4b0: 2b2193f0 adds w16, wsp, w1, sxtb #4
+ 4b4: 2b21a3f0 adds w16, wsp, w1, sxth
+ 4b8: 2b21a3f0 adds w16, wsp, w1, sxth
+ 4bc: 2b21a7f0 adds w16, wsp, w1, sxth #1
+ 4c0: 2b21abf0 adds w16, wsp, w1, sxth #2
+ 4c4: 2b21aff0 adds w16, wsp, w1, sxth #3
+ 4c8: 2b21b3f0 adds w16, wsp, w1, sxth #4
+ 4cc: 2b21c3f0 adds w16, wsp, w1, sxtw
+ 4d0: 2b21c3f0 adds w16, wsp, w1, sxtw
+ 4d4: 2b21c7f0 adds w16, wsp, w1, sxtw #1
+ 4d8: 2b21cbf0 adds w16, wsp, w1, sxtw #2
+ 4dc: 2b21cff0 adds w16, wsp, w1, sxtw #3
+ 4e0: 2b21d3f0 adds w16, wsp, w1, sxtw #4
+ 4e4: 2b21e3f0 adds w16, wsp, w1, sxtx
+ 4e8: 2b21e3f0 adds w16, wsp, w1, sxtx
+ 4ec: 2b21e7f0 adds w16, wsp, w1, sxtx #1
+ 4f0: 2b21ebf0 adds w16, wsp, w1, sxtx #2
+ 4f4: 2b21eff0 adds w16, wsp, w1, sxtx #3
+ 4f8: 2b21f3f0 adds w16, wsp, w1, sxtx #4
+ 4fc: 2b2143f0 adds w16, wsp, w1
+ 500: 2b2147f0 adds w16, wsp, w1, lsl #1
+ 504: 2b214bf0 adds w16, wsp, w1, lsl #2
+ 508: 2b214ff0 adds w16, wsp, w1, lsl #3
+ 50c: 2b2153f0 adds w16, wsp, w1, lsl #4
+ 510: ab0100f0 adds x16, x7, x1
+ 514: ab2100f0 adds x16, x7, w1, uxtb
+ 518: ab2100f0 adds x16, x7, w1, uxtb
+ 51c: ab2104f0 adds x16, x7, w1, uxtb #1
+ 520: ab2108f0 adds x16, x7, w1, uxtb #2
+ 524: ab210cf0 adds x16, x7, w1, uxtb #3
+ 528: ab2110f0 adds x16, x7, w1, uxtb #4
+ 52c: ab2120f0 adds x16, x7, w1, uxth
+ 530: ab2120f0 adds x16, x7, w1, uxth
+ 534: ab2124f0 adds x16, x7, w1, uxth #1
+ 538: ab2128f0 adds x16, x7, w1, uxth #2
+ 53c: ab212cf0 adds x16, x7, w1, uxth #3
+ 540: ab2130f0 adds x16, x7, w1, uxth #4
+ 544: ab2140f0 adds x16, x7, w1, uxtw
+ 548: ab2140f0 adds x16, x7, w1, uxtw
+ 54c: ab2144f0 adds x16, x7, w1, uxtw #1
+ 550: ab2148f0 adds x16, x7, w1, uxtw #2
+ 554: ab214cf0 adds x16, x7, w1, uxtw #3
+ 558: ab2150f0 adds x16, x7, w1, uxtw #4
+ 55c: ab2160f0 adds x16, x7, x1, uxtx
+ 560: ab2160f0 adds x16, x7, x1, uxtx
+ 564: ab2164f0 adds x16, x7, x1, uxtx #1
+ 568: ab2168f0 adds x16, x7, x1, uxtx #2
+ 56c: ab216cf0 adds x16, x7, x1, uxtx #3
+ 570: ab2170f0 adds x16, x7, x1, uxtx #4
+ 574: ab2180f0 adds x16, x7, w1, sxtb
+ 578: ab2180f0 adds x16, x7, w1, sxtb
+ 57c: ab2184f0 adds x16, x7, w1, sxtb #1
+ 580: ab2188f0 adds x16, x7, w1, sxtb #2
+ 584: ab218cf0 adds x16, x7, w1, sxtb #3
+ 588: ab2190f0 adds x16, x7, w1, sxtb #4
+ 58c: ab21a0f0 adds x16, x7, w1, sxth
+ 590: ab21a0f0 adds x16, x7, w1, sxth
+ 594: ab21a4f0 adds x16, x7, w1, sxth #1
+ 598: ab21a8f0 adds x16, x7, w1, sxth #2
+ 59c: ab21acf0 adds x16, x7, w1, sxth #3
+ 5a0: ab21b0f0 adds x16, x7, w1, sxth #4
+ 5a4: ab21c0f0 adds x16, x7, w1, sxtw
+ 5a8: ab21c0f0 adds x16, x7, w1, sxtw
+ 5ac: ab21c4f0 adds x16, x7, w1, sxtw #1
+ 5b0: ab21c8f0 adds x16, x7, w1, sxtw #2
+ 5b4: ab21ccf0 adds x16, x7, w1, sxtw #3
+ 5b8: ab21d0f0 adds x16, x7, w1, sxtw #4
+ 5bc: ab21e0f0 adds x16, x7, x1, sxtx
+ 5c0: ab21e0f0 adds x16, x7, x1, sxtx
+ 5c4: ab21e4f0 adds x16, x7, x1, sxtx #1
+ 5c8: ab21e8f0 adds x16, x7, x1, sxtx #2
+ 5cc: ab21ecf0 adds x16, x7, x1, sxtx #3
+ 5d0: ab21f0f0 adds x16, x7, x1, sxtx #4
+ 5d4: ab0100f0 adds x16, x7, x1
+ 5d8: ab0104f0 adds x16, x7, x1, lsl #1
+ 5dc: ab0108f0 adds x16, x7, x1, lsl #2
+ 5e0: ab010cf0 adds x16, x7, x1, lsl #3
+ 5e4: ab0110f0 adds x16, x7, x1, lsl #4
+ 5e8: ab2163f0 adds x16, sp, x1
+ 5ec: ab2103f0 adds x16, sp, w1, uxtb
+ 5f0: ab2103f0 adds x16, sp, w1, uxtb
+ 5f4: ab2107f0 adds x16, sp, w1, uxtb #1
+ 5f8: ab210bf0 adds x16, sp, w1, uxtb #2
+ 5fc: ab210ff0 adds x16, sp, w1, uxtb #3
+ 600: ab2113f0 adds x16, sp, w1, uxtb #4
+ 604: ab2123f0 adds x16, sp, w1, uxth
+ 608: ab2123f0 adds x16, sp, w1, uxth
+ 60c: ab2127f0 adds x16, sp, w1, uxth #1
+ 610: ab212bf0 adds x16, sp, w1, uxth #2
+ 614: ab212ff0 adds x16, sp, w1, uxth #3
+ 618: ab2133f0 adds x16, sp, w1, uxth #4
+ 61c: ab2143f0 adds x16, sp, w1, uxtw
+ 620: ab2143f0 adds x16, sp, w1, uxtw
+ 624: ab2147f0 adds x16, sp, w1, uxtw #1
+ 628: ab214bf0 adds x16, sp, w1, uxtw #2
+ 62c: ab214ff0 adds x16, sp, w1, uxtw #3
+ 630: ab2153f0 adds x16, sp, w1, uxtw #4
+ 634: ab2163f0 adds x16, sp, x1
+ 638: ab2163f0 adds x16, sp, x1
+ 63c: ab2167f0 adds x16, sp, x1, lsl #1
+ 640: ab216bf0 adds x16, sp, x1, lsl #2
+ 644: ab216ff0 adds x16, sp, x1, lsl #3
+ 648: ab2173f0 adds x16, sp, x1, lsl #4
+ 64c: ab2183f0 adds x16, sp, w1, sxtb
+ 650: ab2183f0 adds x16, sp, w1, sxtb
+ 654: ab2187f0 adds x16, sp, w1, sxtb #1
+ 658: ab218bf0 adds x16, sp, w1, sxtb #2
+ 65c: ab218ff0 adds x16, sp, w1, sxtb #3
+ 660: ab2193f0 adds x16, sp, w1, sxtb #4
+ 664: ab21a3f0 adds x16, sp, w1, sxth
+ 668: ab21a3f0 adds x16, sp, w1, sxth
+ 66c: ab21a7f0 adds x16, sp, w1, sxth #1
+ 670: ab21abf0 adds x16, sp, w1, sxth #2
+ 674: ab21aff0 adds x16, sp, w1, sxth #3
+ 678: ab21b3f0 adds x16, sp, w1, sxth #4
+ 67c: ab21c3f0 adds x16, sp, w1, sxtw
+ 680: ab21c3f0 adds x16, sp, w1, sxtw
+ 684: ab21c7f0 adds x16, sp, w1, sxtw #1
+ 688: ab21cbf0 adds x16, sp, w1, sxtw #2
+ 68c: ab21cff0 adds x16, sp, w1, sxtw #3
+ 690: ab21d3f0 adds x16, sp, w1, sxtw #4
+ 694: ab21e3f0 adds x16, sp, x1, sxtx
+ 698: ab21e3f0 adds x16, sp, x1, sxtx
+ 69c: ab21e7f0 adds x16, sp, x1, sxtx #1
+ 6a0: ab21ebf0 adds x16, sp, x1, sxtx #2
+ 6a4: ab21eff0 adds x16, sp, x1, sxtx #3
+ 6a8: ab21f3f0 adds x16, sp, x1, sxtx #4
+ 6ac: ab2163f0 adds x16, sp, x1
+ 6b0: ab2167f0 adds x16, sp, x1, lsl #1
+ 6b4: ab216bf0 adds x16, sp, x1, lsl #2
+ 6b8: ab216ff0 adds x16, sp, x1, lsl #3
+ 6bc: ab2173f0 adds x16, sp, x1, lsl #4
+ 6c0: 4b0100f0 sub w16, w7, w1
+ 6c4: 4b2100f0 sub w16, w7, w1, uxtb
+ 6c8: 4b2100f0 sub w16, w7, w1, uxtb
+ 6cc: 4b2104f0 sub w16, w7, w1, uxtb #1
+ 6d0: 4b2108f0 sub w16, w7, w1, uxtb #2
+ 6d4: 4b210cf0 sub w16, w7, w1, uxtb #3
+ 6d8: 4b2110f0 sub w16, w7, w1, uxtb #4
+ 6dc: 4b2120f0 sub w16, w7, w1, uxth
+ 6e0: 4b2120f0 sub w16, w7, w1, uxth
+ 6e4: 4b2124f0 sub w16, w7, w1, uxth #1
+ 6e8: 4b2128f0 sub w16, w7, w1, uxth #2
+ 6ec: 4b212cf0 sub w16, w7, w1, uxth #3
+ 6f0: 4b2130f0 sub w16, w7, w1, uxth #4
+ 6f4: 4b2140f0 sub w16, w7, w1, uxtw
+ 6f8: 4b2140f0 sub w16, w7, w1, uxtw
+ 6fc: 4b2144f0 sub w16, w7, w1, uxtw #1
+ 700: 4b2148f0 sub w16, w7, w1, uxtw #2
+ 704: 4b214cf0 sub w16, w7, w1, uxtw #3
+ 708: 4b2150f0 sub w16, w7, w1, uxtw #4
+ 70c: 4b2160f0 sub w16, w7, w1, uxtx
+ 710: 4b2160f0 sub w16, w7, w1, uxtx
+ 714: 4b2164f0 sub w16, w7, w1, uxtx #1
+ 718: 4b2168f0 sub w16, w7, w1, uxtx #2
+ 71c: 4b216cf0 sub w16, w7, w1, uxtx #3
+ 720: 4b2170f0 sub w16, w7, w1, uxtx #4
+ 724: 4b2180f0 sub w16, w7, w1, sxtb
+ 728: 4b2180f0 sub w16, w7, w1, sxtb
+ 72c: 4b2184f0 sub w16, w7, w1, sxtb #1
+ 730: 4b2188f0 sub w16, w7, w1, sxtb #2
+ 734: 4b218cf0 sub w16, w7, w1, sxtb #3
+ 738: 4b2190f0 sub w16, w7, w1, sxtb #4
+ 73c: 4b21a0f0 sub w16, w7, w1, sxth
+ 740: 4b21a0f0 sub w16, w7, w1, sxth
+ 744: 4b21a4f0 sub w16, w7, w1, sxth #1
+ 748: 4b21a8f0 sub w16, w7, w1, sxth #2
+ 74c: 4b21acf0 sub w16, w7, w1, sxth #3
+ 750: 4b21b0f0 sub w16, w7, w1, sxth #4
+ 754: 4b21c0f0 sub w16, w7, w1, sxtw
+ 758: 4b21c0f0 sub w16, w7, w1, sxtw
+ 75c: 4b21c4f0 sub w16, w7, w1, sxtw #1
+ 760: 4b21c8f0 sub w16, w7, w1, sxtw #2
+ 764: 4b21ccf0 sub w16, w7, w1, sxtw #3
+ 768: 4b21d0f0 sub w16, w7, w1, sxtw #4
+ 76c: 4b21e0f0 sub w16, w7, w1, sxtx
+ 770: 4b21e0f0 sub w16, w7, w1, sxtx
+ 774: 4b21e4f0 sub w16, w7, w1, sxtx #1
+ 778: 4b21e8f0 sub w16, w7, w1, sxtx #2
+ 77c: 4b21ecf0 sub w16, w7, w1, sxtx #3
+ 780: 4b21f0f0 sub w16, w7, w1, sxtx #4
+ 784: 4b0100f0 sub w16, w7, w1
+ 788: 4b0104f0 sub w16, w7, w1, lsl #1
+ 78c: 4b0108f0 sub w16, w7, w1, lsl #2
+ 790: 4b010cf0 sub w16, w7, w1, lsl #3
+ 794: 4b0110f0 sub w16, w7, w1, lsl #4
+ 798: 4b2143f0 sub w16, wsp, w1
+ 79c: 4b2103f0 sub w16, wsp, w1, uxtb
+ 7a0: 4b2103f0 sub w16, wsp, w1, uxtb
+ 7a4: 4b2107f0 sub w16, wsp, w1, uxtb #1
+ 7a8: 4b210bf0 sub w16, wsp, w1, uxtb #2
+ 7ac: 4b210ff0 sub w16, wsp, w1, uxtb #3
+ 7b0: 4b2113f0 sub w16, wsp, w1, uxtb #4
+ 7b4: 4b2123f0 sub w16, wsp, w1, uxth
+ 7b8: 4b2123f0 sub w16, wsp, w1, uxth
+ 7bc: 4b2127f0 sub w16, wsp, w1, uxth #1
+ 7c0: 4b212bf0 sub w16, wsp, w1, uxth #2
+ 7c4: 4b212ff0 sub w16, wsp, w1, uxth #3
+ 7c8: 4b2133f0 sub w16, wsp, w1, uxth #4
+ 7cc: 4b2143f0 sub w16, wsp, w1
+ 7d0: 4b2143f0 sub w16, wsp, w1
+ 7d4: 4b2147f0 sub w16, wsp, w1, lsl #1
+ 7d8: 4b214bf0 sub w16, wsp, w1, lsl #2
+ 7dc: 4b214ff0 sub w16, wsp, w1, lsl #3
+ 7e0: 4b2153f0 sub w16, wsp, w1, lsl #4
+ 7e4: 4b2163f0 sub w16, wsp, w1, uxtx
+ 7e8: 4b2163f0 sub w16, wsp, w1, uxtx
+ 7ec: 4b2167f0 sub w16, wsp, w1, uxtx #1
+ 7f0: 4b216bf0 sub w16, wsp, w1, uxtx #2
+ 7f4: 4b216ff0 sub w16, wsp, w1, uxtx #3
+ 7f8: 4b2173f0 sub w16, wsp, w1, uxtx #4
+ 7fc: 4b2183f0 sub w16, wsp, w1, sxtb
+ 800: 4b2183f0 sub w16, wsp, w1, sxtb
+ 804: 4b2187f0 sub w16, wsp, w1, sxtb #1
+ 808: 4b218bf0 sub w16, wsp, w1, sxtb #2
+ 80c: 4b218ff0 sub w16, wsp, w1, sxtb #3
+ 810: 4b2193f0 sub w16, wsp, w1, sxtb #4
+ 814: 4b21a3f0 sub w16, wsp, w1, sxth
+ 818: 4b21a3f0 sub w16, wsp, w1, sxth
+ 81c: 4b21a7f0 sub w16, wsp, w1, sxth #1
+ 820: 4b21abf0 sub w16, wsp, w1, sxth #2
+ 824: 4b21aff0 sub w16, wsp, w1, sxth #3
+ 828: 4b21b3f0 sub w16, wsp, w1, sxth #4
+ 82c: 4b21c3f0 sub w16, wsp, w1, sxtw
+ 830: 4b21c3f0 sub w16, wsp, w1, sxtw
+ 834: 4b21c7f0 sub w16, wsp, w1, sxtw #1
+ 838: 4b21cbf0 sub w16, wsp, w1, sxtw #2
+ 83c: 4b21cff0 sub w16, wsp, w1, sxtw #3
+ 840: 4b21d3f0 sub w16, wsp, w1, sxtw #4
+ 844: 4b21e3f0 sub w16, wsp, w1, sxtx
+ 848: 4b21e3f0 sub w16, wsp, w1, sxtx
+ 84c: 4b21e7f0 sub w16, wsp, w1, sxtx #1
+ 850: 4b21ebf0 sub w16, wsp, w1, sxtx #2
+ 854: 4b21eff0 sub w16, wsp, w1, sxtx #3
+ 858: 4b21f3f0 sub w16, wsp, w1, sxtx #4
+ 85c: 4b2143f0 sub w16, wsp, w1
+ 860: 4b2147f0 sub w16, wsp, w1, lsl #1
+ 864: 4b214bf0 sub w16, wsp, w1, lsl #2
+ 868: 4b214ff0 sub w16, wsp, w1, lsl #3
+ 86c: 4b2153f0 sub w16, wsp, w1, lsl #4
+ 870: cb0100f0 sub x16, x7, x1
+ 874: cb2100f0 sub x16, x7, w1, uxtb
+ 878: cb2100f0 sub x16, x7, w1, uxtb
+ 87c: cb2104f0 sub x16, x7, w1, uxtb #1
+ 880: cb2108f0 sub x16, x7, w1, uxtb #2
+ 884: cb210cf0 sub x16, x7, w1, uxtb #3
+ 888: cb2110f0 sub x16, x7, w1, uxtb #4
+ 88c: cb2120f0 sub x16, x7, w1, uxth
+ 890: cb2120f0 sub x16, x7, w1, uxth
+ 894: cb2124f0 sub x16, x7, w1, uxth #1
+ 898: cb2128f0 sub x16, x7, w1, uxth #2
+ 89c: cb212cf0 sub x16, x7, w1, uxth #3
+ 8a0: cb2130f0 sub x16, x7, w1, uxth #4
+ 8a4: cb2140f0 sub x16, x7, w1, uxtw
+ 8a8: cb2140f0 sub x16, x7, w1, uxtw
+ 8ac: cb2144f0 sub x16, x7, w1, uxtw #1
+ 8b0: cb2148f0 sub x16, x7, w1, uxtw #2
+ 8b4: cb214cf0 sub x16, x7, w1, uxtw #3
+ 8b8: cb2150f0 sub x16, x7, w1, uxtw #4
+ 8bc: cb2160f0 sub x16, x7, x1, uxtx
+ 8c0: cb2160f0 sub x16, x7, x1, uxtx
+ 8c4: cb2164f0 sub x16, x7, x1, uxtx #1
+ 8c8: cb2168f0 sub x16, x7, x1, uxtx #2
+ 8cc: cb216cf0 sub x16, x7, x1, uxtx #3
+ 8d0: cb2170f0 sub x16, x7, x1, uxtx #4
+ 8d4: cb2180f0 sub x16, x7, w1, sxtb
+ 8d8: cb2180f0 sub x16, x7, w1, sxtb
+ 8dc: cb2184f0 sub x16, x7, w1, sxtb #1
+ 8e0: cb2188f0 sub x16, x7, w1, sxtb #2
+ 8e4: cb218cf0 sub x16, x7, w1, sxtb #3
+ 8e8: cb2190f0 sub x16, x7, w1, sxtb #4
+ 8ec: cb21a0f0 sub x16, x7, w1, sxth
+ 8f0: cb21a0f0 sub x16, x7, w1, sxth
+ 8f4: cb21a4f0 sub x16, x7, w1, sxth #1
+ 8f8: cb21a8f0 sub x16, x7, w1, sxth #2
+ 8fc: cb21acf0 sub x16, x7, w1, sxth #3
+ 900: cb21b0f0 sub x16, x7, w1, sxth #4
+ 904: cb21c0f0 sub x16, x7, w1, sxtw
+ 908: cb21c0f0 sub x16, x7, w1, sxtw
+ 90c: cb21c4f0 sub x16, x7, w1, sxtw #1
+ 910: cb21c8f0 sub x16, x7, w1, sxtw #2
+ 914: cb21ccf0 sub x16, x7, w1, sxtw #3
+ 918: cb21d0f0 sub x16, x7, w1, sxtw #4
+ 91c: cb21e0f0 sub x16, x7, x1, sxtx
+ 920: cb21e0f0 sub x16, x7, x1, sxtx
+ 924: cb21e4f0 sub x16, x7, x1, sxtx #1
+ 928: cb21e8f0 sub x16, x7, x1, sxtx #2
+ 92c: cb21ecf0 sub x16, x7, x1, sxtx #3
+ 930: cb21f0f0 sub x16, x7, x1, sxtx #4
+ 934: cb0100f0 sub x16, x7, x1
+ 938: cb0104f0 sub x16, x7, x1, lsl #1
+ 93c: cb0108f0 sub x16, x7, x1, lsl #2
+ 940: cb010cf0 sub x16, x7, x1, lsl #3
+ 944: cb0110f0 sub x16, x7, x1, lsl #4
+ 948: cb2163f0 sub x16, sp, x1
+ 94c: cb2103f0 sub x16, sp, w1, uxtb
+ 950: cb2103f0 sub x16, sp, w1, uxtb
+ 954: cb2107f0 sub x16, sp, w1, uxtb #1
+ 958: cb210bf0 sub x16, sp, w1, uxtb #2
+ 95c: cb210ff0 sub x16, sp, w1, uxtb #3
+ 960: cb2113f0 sub x16, sp, w1, uxtb #4
+ 964: cb2123f0 sub x16, sp, w1, uxth
+ 968: cb2123f0 sub x16, sp, w1, uxth
+ 96c: cb2127f0 sub x16, sp, w1, uxth #1
+ 970: cb212bf0 sub x16, sp, w1, uxth #2
+ 974: cb212ff0 sub x16, sp, w1, uxth #3
+ 978: cb2133f0 sub x16, sp, w1, uxth #4
+ 97c: cb2143f0 sub x16, sp, w1, uxtw
+ 980: cb2143f0 sub x16, sp, w1, uxtw
+ 984: cb2147f0 sub x16, sp, w1, uxtw #1
+ 988: cb214bf0 sub x16, sp, w1, uxtw #2
+ 98c: cb214ff0 sub x16, sp, w1, uxtw #3
+ 990: cb2153f0 sub x16, sp, w1, uxtw #4
+ 994: cb2163f0 sub x16, sp, x1
+ 998: cb2163f0 sub x16, sp, x1
+ 99c: cb2167f0 sub x16, sp, x1, lsl #1
+ 9a0: cb216bf0 sub x16, sp, x1, lsl #2
+ 9a4: cb216ff0 sub x16, sp, x1, lsl #3
+ 9a8: cb2173f0 sub x16, sp, x1, lsl #4
+ 9ac: cb2183f0 sub x16, sp, w1, sxtb
+ 9b0: cb2183f0 sub x16, sp, w1, sxtb
+ 9b4: cb2187f0 sub x16, sp, w1, sxtb #1
+ 9b8: cb218bf0 sub x16, sp, w1, sxtb #2
+ 9bc: cb218ff0 sub x16, sp, w1, sxtb #3
+ 9c0: cb2193f0 sub x16, sp, w1, sxtb #4
+ 9c4: cb21a3f0 sub x16, sp, w1, sxth
+ 9c8: cb21a3f0 sub x16, sp, w1, sxth
+ 9cc: cb21a7f0 sub x16, sp, w1, sxth #1
+ 9d0: cb21abf0 sub x16, sp, w1, sxth #2
+ 9d4: cb21aff0 sub x16, sp, w1, sxth #3
+ 9d8: cb21b3f0 sub x16, sp, w1, sxth #4
+ 9dc: cb21c3f0 sub x16, sp, w1, sxtw
+ 9e0: cb21c3f0 sub x16, sp, w1, sxtw
+ 9e4: cb21c7f0 sub x16, sp, w1, sxtw #1
+ 9e8: cb21cbf0 sub x16, sp, w1, sxtw #2
+ 9ec: cb21cff0 sub x16, sp, w1, sxtw #3
+ 9f0: cb21d3f0 sub x16, sp, w1, sxtw #4
+ 9f4: cb21e3f0 sub x16, sp, x1, sxtx
+ 9f8: cb21e3f0 sub x16, sp, x1, sxtx
+ 9fc: cb21e7f0 sub x16, sp, x1, sxtx #1
+ a00: cb21ebf0 sub x16, sp, x1, sxtx #2
+ a04: cb21eff0 sub x16, sp, x1, sxtx #3
+ a08: cb21f3f0 sub x16, sp, x1, sxtx #4
+ a0c: cb2163f0 sub x16, sp, x1
+ a10: cb2167f0 sub x16, sp, x1, lsl #1
+ a14: cb216bf0 sub x16, sp, x1, lsl #2
+ a18: cb216ff0 sub x16, sp, x1, lsl #3
+ a1c: cb2173f0 sub x16, sp, x1, lsl #4
+ a20: 6b0100f0 subs w16, w7, w1
+ a24: 6b2100f0 subs w16, w7, w1, uxtb
+ a28: 6b2100f0 subs w16, w7, w1, uxtb
+ a2c: 6b2104f0 subs w16, w7, w1, uxtb #1
+ a30: 6b2108f0 subs w16, w7, w1, uxtb #2
+ a34: 6b210cf0 subs w16, w7, w1, uxtb #3
+ a38: 6b2110f0 subs w16, w7, w1, uxtb #4
+ a3c: 6b2120f0 subs w16, w7, w1, uxth
+ a40: 6b2120f0 subs w16, w7, w1, uxth
+ a44: 6b2124f0 subs w16, w7, w1, uxth #1
+ a48: 6b2128f0 subs w16, w7, w1, uxth #2
+ a4c: 6b212cf0 subs w16, w7, w1, uxth #3
+ a50: 6b2130f0 subs w16, w7, w1, uxth #4
+ a54: 6b2140f0 subs w16, w7, w1, uxtw
+ a58: 6b2140f0 subs w16, w7, w1, uxtw
+ a5c: 6b2144f0 subs w16, w7, w1, uxtw #1
+ a60: 6b2148f0 subs w16, w7, w1, uxtw #2
+ a64: 6b214cf0 subs w16, w7, w1, uxtw #3
+ a68: 6b2150f0 subs w16, w7, w1, uxtw #4
+ a6c: 6b2160f0 subs w16, w7, w1, uxtx
+ a70: 6b2160f0 subs w16, w7, w1, uxtx
+ a74: 6b2164f0 subs w16, w7, w1, uxtx #1
+ a78: 6b2168f0 subs w16, w7, w1, uxtx #2
+ a7c: 6b216cf0 subs w16, w7, w1, uxtx #3
+ a80: 6b2170f0 subs w16, w7, w1, uxtx #4
+ a84: 6b2180f0 subs w16, w7, w1, sxtb
+ a88: 6b2180f0 subs w16, w7, w1, sxtb
+ a8c: 6b2184f0 subs w16, w7, w1, sxtb #1
+ a90: 6b2188f0 subs w16, w7, w1, sxtb #2
+ a94: 6b218cf0 subs w16, w7, w1, sxtb #3
+ a98: 6b2190f0 subs w16, w7, w1, sxtb #4
+ a9c: 6b21a0f0 subs w16, w7, w1, sxth
+ aa0: 6b21a0f0 subs w16, w7, w1, sxth
+ aa4: 6b21a4f0 subs w16, w7, w1, sxth #1
+ aa8: 6b21a8f0 subs w16, w7, w1, sxth #2
+ aac: 6b21acf0 subs w16, w7, w1, sxth #3
+ ab0: 6b21b0f0 subs w16, w7, w1, sxth #4
+ ab4: 6b21c0f0 subs w16, w7, w1, sxtw
+ ab8: 6b21c0f0 subs w16, w7, w1, sxtw
+ abc: 6b21c4f0 subs w16, w7, w1, sxtw #1
+ ac0: 6b21c8f0 subs w16, w7, w1, sxtw #2
+ ac4: 6b21ccf0 subs w16, w7, w1, sxtw #3
+ ac8: 6b21d0f0 subs w16, w7, w1, sxtw #4
+ acc: 6b21e0f0 subs w16, w7, w1, sxtx
+ ad0: 6b21e0f0 subs w16, w7, w1, sxtx
+ ad4: 6b21e4f0 subs w16, w7, w1, sxtx #1
+ ad8: 6b21e8f0 subs w16, w7, w1, sxtx #2
+ adc: 6b21ecf0 subs w16, w7, w1, sxtx #3
+ ae0: 6b21f0f0 subs w16, w7, w1, sxtx #4
+ ae4: 6b0100f0 subs w16, w7, w1
+ ae8: 6b0104f0 subs w16, w7, w1, lsl #1
+ aec: 6b0108f0 subs w16, w7, w1, lsl #2
+ af0: 6b010cf0 subs w16, w7, w1, lsl #3
+ af4: 6b0110f0 subs w16, w7, w1, lsl #4
+ af8: 6b2143f0 subs w16, wsp, w1
+ afc: 6b2103f0 subs w16, wsp, w1, uxtb
+ b00: 6b2103f0 subs w16, wsp, w1, uxtb
+ b04: 6b2107f0 subs w16, wsp, w1, uxtb #1
+ b08: 6b210bf0 subs w16, wsp, w1, uxtb #2
+ b0c: 6b210ff0 subs w16, wsp, w1, uxtb #3
+ b10: 6b2113f0 subs w16, wsp, w1, uxtb #4
+ b14: 6b2123f0 subs w16, wsp, w1, uxth
+ b18: 6b2123f0 subs w16, wsp, w1, uxth
+ b1c: 6b2127f0 subs w16, wsp, w1, uxth #1
+ b20: 6b212bf0 subs w16, wsp, w1, uxth #2
+ b24: 6b212ff0 subs w16, wsp, w1, uxth #3
+ b28: 6b2133f0 subs w16, wsp, w1, uxth #4
+ b2c: 6b2143f0 subs w16, wsp, w1
+ b30: 6b2143f0 subs w16, wsp, w1
+ b34: 6b2147f0 subs w16, wsp, w1, lsl #1
+ b38: 6b214bf0 subs w16, wsp, w1, lsl #2
+ b3c: 6b214ff0 subs w16, wsp, w1, lsl #3
+ b40: 6b2153f0 subs w16, wsp, w1, lsl #4
+ b44: 6b2163f0 subs w16, wsp, w1, uxtx
+ b48: 6b2163f0 subs w16, wsp, w1, uxtx
+ b4c: 6b2167f0 subs w16, wsp, w1, uxtx #1
+ b50: 6b216bf0 subs w16, wsp, w1, uxtx #2
+ b54: 6b216ff0 subs w16, wsp, w1, uxtx #3
+ b58: 6b2173f0 subs w16, wsp, w1, uxtx #4
+ b5c: 6b2183f0 subs w16, wsp, w1, sxtb
+ b60: 6b2183f0 subs w16, wsp, w1, sxtb
+ b64: 6b2187f0 subs w16, wsp, w1, sxtb #1
+ b68: 6b218bf0 subs w16, wsp, w1, sxtb #2
+ b6c: 6b218ff0 subs w16, wsp, w1, sxtb #3
+ b70: 6b2193f0 subs w16, wsp, w1, sxtb #4
+ b74: 6b21a3f0 subs w16, wsp, w1, sxth
+ b78: 6b21a3f0 subs w16, wsp, w1, sxth
+ b7c: 6b21a7f0 subs w16, wsp, w1, sxth #1
+ b80: 6b21abf0 subs w16, wsp, w1, sxth #2
+ b84: 6b21aff0 subs w16, wsp, w1, sxth #3
+ b88: 6b21b3f0 subs w16, wsp, w1, sxth #4
+ b8c: 6b21c3f0 subs w16, wsp, w1, sxtw
+ b90: 6b21c3f0 subs w16, wsp, w1, sxtw
+ b94: 6b21c7f0 subs w16, wsp, w1, sxtw #1
+ b98: 6b21cbf0 subs w16, wsp, w1, sxtw #2
+ b9c: 6b21cff0 subs w16, wsp, w1, sxtw #3
+ ba0: 6b21d3f0 subs w16, wsp, w1, sxtw #4
+ ba4: 6b21e3f0 subs w16, wsp, w1, sxtx
+ ba8: 6b21e3f0 subs w16, wsp, w1, sxtx
+ bac: 6b21e7f0 subs w16, wsp, w1, sxtx #1
+ bb0: 6b21ebf0 subs w16, wsp, w1, sxtx #2
+ bb4: 6b21eff0 subs w16, wsp, w1, sxtx #3
+ bb8: 6b21f3f0 subs w16, wsp, w1, sxtx #4
+ bbc: 6b2143f0 subs w16, wsp, w1
+ bc0: 6b2147f0 subs w16, wsp, w1, lsl #1
+ bc4: 6b214bf0 subs w16, wsp, w1, lsl #2
+ bc8: 6b214ff0 subs w16, wsp, w1, lsl #3
+ bcc: 6b2153f0 subs w16, wsp, w1, lsl #4
+ bd0: eb0100f0 subs x16, x7, x1
+ bd4: eb2100f0 subs x16, x7, w1, uxtb
+ bd8: eb2100f0 subs x16, x7, w1, uxtb
+ bdc: eb2104f0 subs x16, x7, w1, uxtb #1
+ be0: eb2108f0 subs x16, x7, w1, uxtb #2
+ be4: eb210cf0 subs x16, x7, w1, uxtb #3
+ be8: eb2110f0 subs x16, x7, w1, uxtb #4
+ bec: eb2120f0 subs x16, x7, w1, uxth
+ bf0: eb2120f0 subs x16, x7, w1, uxth
+ bf4: eb2124f0 subs x16, x7, w1, uxth #1
+ bf8: eb2128f0 subs x16, x7, w1, uxth #2
+ bfc: eb212cf0 subs x16, x7, w1, uxth #3
+ c00: eb2130f0 subs x16, x7, w1, uxth #4
+ c04: eb2140f0 subs x16, x7, w1, uxtw
+ c08: eb2140f0 subs x16, x7, w1, uxtw
+ c0c: eb2144f0 subs x16, x7, w1, uxtw #1
+ c10: eb2148f0 subs x16, x7, w1, uxtw #2
+ c14: eb214cf0 subs x16, x7, w1, uxtw #3
+ c18: eb2150f0 subs x16, x7, w1, uxtw #4
+ c1c: eb2160f0 subs x16, x7, x1, uxtx
+ c20: eb2160f0 subs x16, x7, x1, uxtx
+ c24: eb2164f0 subs x16, x7, x1, uxtx #1
+ c28: eb2168f0 subs x16, x7, x1, uxtx #2
+ c2c: eb216cf0 subs x16, x7, x1, uxtx #3
+ c30: eb2170f0 subs x16, x7, x1, uxtx #4
+ c34: eb2180f0 subs x16, x7, w1, sxtb
+ c38: eb2180f0 subs x16, x7, w1, sxtb
+ c3c: eb2184f0 subs x16, x7, w1, sxtb #1
+ c40: eb2188f0 subs x16, x7, w1, sxtb #2
+ c44: eb218cf0 subs x16, x7, w1, sxtb #3
+ c48: eb2190f0 subs x16, x7, w1, sxtb #4
+ c4c: eb21a0f0 subs x16, x7, w1, sxth
+ c50: eb21a0f0 subs x16, x7, w1, sxth
+ c54: eb21a4f0 subs x16, x7, w1, sxth #1
+ c58: eb21a8f0 subs x16, x7, w1, sxth #2
+ c5c: eb21acf0 subs x16, x7, w1, sxth #3
+ c60: eb21b0f0 subs x16, x7, w1, sxth #4
+ c64: eb21c0f0 subs x16, x7, w1, sxtw
+ c68: eb21c0f0 subs x16, x7, w1, sxtw
+ c6c: eb21c4f0 subs x16, x7, w1, sxtw #1
+ c70: eb21c8f0 subs x16, x7, w1, sxtw #2
+ c74: eb21ccf0 subs x16, x7, w1, sxtw #3
+ c78: eb21d0f0 subs x16, x7, w1, sxtw #4
+ c7c: eb21e0f0 subs x16, x7, x1, sxtx
+ c80: eb21e0f0 subs x16, x7, x1, sxtx
+ c84: eb21e4f0 subs x16, x7, x1, sxtx #1
+ c88: eb21e8f0 subs x16, x7, x1, sxtx #2
+ c8c: eb21ecf0 subs x16, x7, x1, sxtx #3
+ c90: eb21f0f0 subs x16, x7, x1, sxtx #4
+ c94: eb0100f0 subs x16, x7, x1
+ c98: eb0104f0 subs x16, x7, x1, lsl #1
+ c9c: eb0108f0 subs x16, x7, x1, lsl #2
+ ca0: eb010cf0 subs x16, x7, x1, lsl #3
+ ca4: eb0110f0 subs x16, x7, x1, lsl #4
+ ca8: eb2163f0 subs x16, sp, x1
+ cac: eb2103f0 subs x16, sp, w1, uxtb
+ cb0: eb2103f0 subs x16, sp, w1, uxtb
+ cb4: eb2107f0 subs x16, sp, w1, uxtb #1
+ cb8: eb210bf0 subs x16, sp, w1, uxtb #2
+ cbc: eb210ff0 subs x16, sp, w1, uxtb #3
+ cc0: eb2113f0 subs x16, sp, w1, uxtb #4
+ cc4: eb2123f0 subs x16, sp, w1, uxth
+ cc8: eb2123f0 subs x16, sp, w1, uxth
+ ccc: eb2127f0 subs x16, sp, w1, uxth #1
+ cd0: eb212bf0 subs x16, sp, w1, uxth #2
+ cd4: eb212ff0 subs x16, sp, w1, uxth #3
+ cd8: eb2133f0 subs x16, sp, w1, uxth #4
+ cdc: eb2143f0 subs x16, sp, w1, uxtw
+ ce0: eb2143f0 subs x16, sp, w1, uxtw
+ ce4: eb2147f0 subs x16, sp, w1, uxtw #1
+ ce8: eb214bf0 subs x16, sp, w1, uxtw #2
+ cec: eb214ff0 subs x16, sp, w1, uxtw #3
+ cf0: eb2153f0 subs x16, sp, w1, uxtw #4
+ cf4: eb2163f0 subs x16, sp, x1
+ cf8: eb2163f0 subs x16, sp, x1
+ cfc: eb2167f0 subs x16, sp, x1, lsl #1
+ d00: eb216bf0 subs x16, sp, x1, lsl #2
+ d04: eb216ff0 subs x16, sp, x1, lsl #3
+ d08: eb2173f0 subs x16, sp, x1, lsl #4
+ d0c: eb2183f0 subs x16, sp, w1, sxtb
+ d10: eb2183f0 subs x16, sp, w1, sxtb
+ d14: eb2187f0 subs x16, sp, w1, sxtb #1
+ d18: eb218bf0 subs x16, sp, w1, sxtb #2
+ d1c: eb218ff0 subs x16, sp, w1, sxtb #3
+ d20: eb2193f0 subs x16, sp, w1, sxtb #4
+ d24: eb21a3f0 subs x16, sp, w1, sxth
+ d28: eb21a3f0 subs x16, sp, w1, sxth
+ d2c: eb21a7f0 subs x16, sp, w1, sxth #1
+ d30: eb21abf0 subs x16, sp, w1, sxth #2
+ d34: eb21aff0 subs x16, sp, w1, sxth #3
+ d38: eb21b3f0 subs x16, sp, w1, sxth #4
+ d3c: eb21c3f0 subs x16, sp, w1, sxtw
+ d40: eb21c3f0 subs x16, sp, w1, sxtw
+ d44: eb21c7f0 subs x16, sp, w1, sxtw #1
+ d48: eb21cbf0 subs x16, sp, w1, sxtw #2
+ d4c: eb21cff0 subs x16, sp, w1, sxtw #3
+ d50: eb21d3f0 subs x16, sp, w1, sxtw #4
+ d54: eb21e3f0 subs x16, sp, x1, sxtx
+ d58: eb21e3f0 subs x16, sp, x1, sxtx
+ d5c: eb21e7f0 subs x16, sp, x1, sxtx #1
+ d60: eb21ebf0 subs x16, sp, x1, sxtx #2
+ d64: eb21eff0 subs x16, sp, x1, sxtx #3
+ d68: eb21f3f0 subs x16, sp, x1, sxtx #4
+ d6c: eb2163f0 subs x16, sp, x1
+ d70: eb2167f0 subs x16, sp, x1, lsl #1
+ d74: eb216bf0 subs x16, sp, x1, lsl #2
+ d78: eb216ff0 subs x16, sp, x1, lsl #3
+ d7c: eb2173f0 subs x16, sp, x1, lsl #4
+ d80: 2b0100ff cmn w7, w1
+ d84: 2b2100ff cmn w7, w1, uxtb
+ d88: 2b2100ff cmn w7, w1, uxtb
+ d8c: 2b2104ff cmn w7, w1, uxtb #1
+ d90: 2b2108ff cmn w7, w1, uxtb #2
+ d94: 2b210cff cmn w7, w1, uxtb #3
+ d98: 2b2110ff cmn w7, w1, uxtb #4
+ d9c: 2b2120ff cmn w7, w1, uxth
+ da0: 2b2120ff cmn w7, w1, uxth
+ da4: 2b2124ff cmn w7, w1, uxth #1
+ da8: 2b2128ff cmn w7, w1, uxth #2
+ dac: 2b212cff cmn w7, w1, uxth #3
+ db0: 2b2130ff cmn w7, w1, uxth #4
+ db4: 2b2140ff cmn w7, w1, uxtw
+ db8: 2b2140ff cmn w7, w1, uxtw
+ dbc: 2b2144ff cmn w7, w1, uxtw #1
+ dc0: 2b2148ff cmn w7, w1, uxtw #2
+ dc4: 2b214cff cmn w7, w1, uxtw #3
+ dc8: 2b2150ff cmn w7, w1, uxtw #4
+ dcc: 2b2160ff cmn w7, w1, uxtx
+ dd0: 2b2160ff cmn w7, w1, uxtx
+ dd4: 2b2164ff cmn w7, w1, uxtx #1
+ dd8: 2b2168ff cmn w7, w1, uxtx #2
+ ddc: 2b216cff cmn w7, w1, uxtx #3
+ de0: 2b2170ff cmn w7, w1, uxtx #4
+ de4: 2b2180ff cmn w7, w1, sxtb
+ de8: 2b2180ff cmn w7, w1, sxtb
+ dec: 2b2184ff cmn w7, w1, sxtb #1
+ df0: 2b2188ff cmn w7, w1, sxtb #2
+ df4: 2b218cff cmn w7, w1, sxtb #3
+ df8: 2b2190ff cmn w7, w1, sxtb #4
+ dfc: 2b21a0ff cmn w7, w1, sxth
+ e00: 2b21a0ff cmn w7, w1, sxth
+ e04: 2b21a4ff cmn w7, w1, sxth #1
+ e08: 2b21a8ff cmn w7, w1, sxth #2
+ e0c: 2b21acff cmn w7, w1, sxth #3
+ e10: 2b21b0ff cmn w7, w1, sxth #4
+ e14: 2b21c0ff cmn w7, w1, sxtw
+ e18: 2b21c0ff cmn w7, w1, sxtw
+ e1c: 2b21c4ff cmn w7, w1, sxtw #1
+ e20: 2b21c8ff cmn w7, w1, sxtw #2
+ e24: 2b21ccff cmn w7, w1, sxtw #3
+ e28: 2b21d0ff cmn w7, w1, sxtw #4
+ e2c: 2b21e0ff cmn w7, w1, sxtx
+ e30: 2b21e0ff cmn w7, w1, sxtx
+ e34: 2b21e4ff cmn w7, w1, sxtx #1
+ e38: 2b21e8ff cmn w7, w1, sxtx #2
+ e3c: 2b21ecff cmn w7, w1, sxtx #3
+ e40: 2b21f0ff cmn w7, w1, sxtx #4
+ e44: 2b0100ff cmn w7, w1
+ e48: 2b0104ff cmn w7, w1, lsl #1
+ e4c: 2b0108ff cmn w7, w1, lsl #2
+ e50: 2b010cff cmn w7, w1, lsl #3
+ e54: 2b0110ff cmn w7, w1, lsl #4
+ e58: 2b2143ff cmn wsp, w1
+ e5c: 2b2103ff cmn wsp, w1, uxtb
+ e60: 2b2103ff cmn wsp, w1, uxtb
+ e64: 2b2107ff cmn wsp, w1, uxtb #1
+ e68: 2b210bff cmn wsp, w1, uxtb #2
+ e6c: 2b210fff cmn wsp, w1, uxtb #3
+ e70: 2b2113ff cmn wsp, w1, uxtb #4
+ e74: 2b2123ff cmn wsp, w1, uxth
+ e78: 2b2123ff cmn wsp, w1, uxth
+ e7c: 2b2127ff cmn wsp, w1, uxth #1
+ e80: 2b212bff cmn wsp, w1, uxth #2
+ e84: 2b212fff cmn wsp, w1, uxth #3
+ e88: 2b2133ff cmn wsp, w1, uxth #4
+ e8c: 2b2143ff cmn wsp, w1
+ e90: 2b2143ff cmn wsp, w1
+ e94: 2b2147ff cmn wsp, w1, lsl #1
+ e98: 2b214bff cmn wsp, w1, lsl #2
+ e9c: 2b214fff cmn wsp, w1, lsl #3
+ ea0: 2b2153ff cmn wsp, w1, lsl #4
+ ea4: 2b2163ff cmn wsp, w1, uxtx
+ ea8: 2b2163ff cmn wsp, w1, uxtx
+ eac: 2b2167ff cmn wsp, w1, uxtx #1
+ eb0: 2b216bff cmn wsp, w1, uxtx #2
+ eb4: 2b216fff cmn wsp, w1, uxtx #3
+ eb8: 2b2173ff cmn wsp, w1, uxtx #4
+ ebc: 2b2183ff cmn wsp, w1, sxtb
+ ec0: 2b2183ff cmn wsp, w1, sxtb
+ ec4: 2b2187ff cmn wsp, w1, sxtb #1
+ ec8: 2b218bff cmn wsp, w1, sxtb #2
+ ecc: 2b218fff cmn wsp, w1, sxtb #3
+ ed0: 2b2193ff cmn wsp, w1, sxtb #4
+ ed4: 2b21a3ff cmn wsp, w1, sxth
+ ed8: 2b21a3ff cmn wsp, w1, sxth
+ edc: 2b21a7ff cmn wsp, w1, sxth #1
+ ee0: 2b21abff cmn wsp, w1, sxth #2
+ ee4: 2b21afff cmn wsp, w1, sxth #3
+ ee8: 2b21b3ff cmn wsp, w1, sxth #4
+ eec: 2b21c3ff cmn wsp, w1, sxtw
+ ef0: 2b21c3ff cmn wsp, w1, sxtw
+ ef4: 2b21c7ff cmn wsp, w1, sxtw #1
+ ef8: 2b21cbff cmn wsp, w1, sxtw #2
+ efc: 2b21cfff cmn wsp, w1, sxtw #3
+ f00: 2b21d3ff cmn wsp, w1, sxtw #4
+ f04: 2b21e3ff cmn wsp, w1, sxtx
+ f08: 2b21e3ff cmn wsp, w1, sxtx
+ f0c: 2b21e7ff cmn wsp, w1, sxtx #1
+ f10: 2b21ebff cmn wsp, w1, sxtx #2
+ f14: 2b21efff cmn wsp, w1, sxtx #3
+ f18: 2b21f3ff cmn wsp, w1, sxtx #4
+ f1c: 2b2143ff cmn wsp, w1
+ f20: 2b2147ff cmn wsp, w1, lsl #1
+ f24: 2b214bff cmn wsp, w1, lsl #2
+ f28: 2b214fff cmn wsp, w1, lsl #3
+ f2c: 2b2153ff cmn wsp, w1, lsl #4
+ f30: ab0100ff cmn x7, x1
+ f34: ab2100ff cmn x7, w1, uxtb
+ f38: ab2100ff cmn x7, w1, uxtb
+ f3c: ab2104ff cmn x7, w1, uxtb #1
+ f40: ab2108ff cmn x7, w1, uxtb #2
+ f44: ab210cff cmn x7, w1, uxtb #3
+ f48: ab2110ff cmn x7, w1, uxtb #4
+ f4c: ab2120ff cmn x7, w1, uxth
+ f50: ab2120ff cmn x7, w1, uxth
+ f54: ab2124ff cmn x7, w1, uxth #1
+ f58: ab2128ff cmn x7, w1, uxth #2
+ f5c: ab212cff cmn x7, w1, uxth #3
+ f60: ab2130ff cmn x7, w1, uxth #4
+ f64: ab2140ff cmn x7, w1, uxtw
+ f68: ab2140ff cmn x7, w1, uxtw
+ f6c: ab2144ff cmn x7, w1, uxtw #1
+ f70: ab2148ff cmn x7, w1, uxtw #2
+ f74: ab214cff cmn x7, w1, uxtw #3
+ f78: ab2150ff cmn x7, w1, uxtw #4
+ f7c: ab2160ff cmn x7, x1, uxtx
+ f80: ab2160ff cmn x7, x1, uxtx
+ f84: ab2164ff cmn x7, x1, uxtx #1
+ f88: ab2168ff cmn x7, x1, uxtx #2
+ f8c: ab216cff cmn x7, x1, uxtx #3
+ f90: ab2170ff cmn x7, x1, uxtx #4
+ f94: ab2180ff cmn x7, w1, sxtb
+ f98: ab2180ff cmn x7, w1, sxtb
+ f9c: ab2184ff cmn x7, w1, sxtb #1
+ fa0: ab2188ff cmn x7, w1, sxtb #2
+ fa4: ab218cff cmn x7, w1, sxtb #3
+ fa8: ab2190ff cmn x7, w1, sxtb #4
+ fac: ab21a0ff cmn x7, w1, sxth
+ fb0: ab21a0ff cmn x7, w1, sxth
+ fb4: ab21a4ff cmn x7, w1, sxth #1
+ fb8: ab21a8ff cmn x7, w1, sxth #2
+ fbc: ab21acff cmn x7, w1, sxth #3
+ fc0: ab21b0ff cmn x7, w1, sxth #4
+ fc4: ab21c0ff cmn x7, w1, sxtw
+ fc8: ab21c0ff cmn x7, w1, sxtw
+ fcc: ab21c4ff cmn x7, w1, sxtw #1
+ fd0: ab21c8ff cmn x7, w1, sxtw #2
+ fd4: ab21ccff cmn x7, w1, sxtw #3
+ fd8: ab21d0ff cmn x7, w1, sxtw #4
+ fdc: ab21e0ff cmn x7, x1, sxtx
+ fe0: ab21e0ff cmn x7, x1, sxtx
+ fe4: ab21e4ff cmn x7, x1, sxtx #1
+ fe8: ab21e8ff cmn x7, x1, sxtx #2
+ fec: ab21ecff cmn x7, x1, sxtx #3
+ ff0: ab21f0ff cmn x7, x1, sxtx #4
+ ff4: ab0100ff cmn x7, x1
+ ff8: ab0104ff cmn x7, x1, lsl #1
+ ffc: ab0108ff cmn x7, x1, lsl #2
+ 1000: ab010cff cmn x7, x1, lsl #3
+ 1004: ab0110ff cmn x7, x1, lsl #4
+ 1008: ab2163ff cmn sp, x1
+ 100c: ab2103ff cmn sp, w1, uxtb
+ 1010: ab2103ff cmn sp, w1, uxtb
+ 1014: ab2107ff cmn sp, w1, uxtb #1
+ 1018: ab210bff cmn sp, w1, uxtb #2
+ 101c: ab210fff cmn sp, w1, uxtb #3
+ 1020: ab2113ff cmn sp, w1, uxtb #4
+ 1024: ab2123ff cmn sp, w1, uxth
+ 1028: ab2123ff cmn sp, w1, uxth
+ 102c: ab2127ff cmn sp, w1, uxth #1
+ 1030: ab212bff cmn sp, w1, uxth #2
+ 1034: ab212fff cmn sp, w1, uxth #3
+ 1038: ab2133ff cmn sp, w1, uxth #4
+ 103c: ab2143ff cmn sp, w1, uxtw
+ 1040: ab2143ff cmn sp, w1, uxtw
+ 1044: ab2147ff cmn sp, w1, uxtw #1
+ 1048: ab214bff cmn sp, w1, uxtw #2
+ 104c: ab214fff cmn sp, w1, uxtw #3
+ 1050: ab2153ff cmn sp, w1, uxtw #4
+ 1054: ab2163ff cmn sp, x1
+ 1058: ab2163ff cmn sp, x1
+ 105c: ab2167ff cmn sp, x1, lsl #1
+ 1060: ab216bff cmn sp, x1, lsl #2
+ 1064: ab216fff cmn sp, x1, lsl #3
+ 1068: ab2173ff cmn sp, x1, lsl #4
+ 106c: ab2183ff cmn sp, w1, sxtb
+ 1070: ab2183ff cmn sp, w1, sxtb
+ 1074: ab2187ff cmn sp, w1, sxtb #1
+ 1078: ab218bff cmn sp, w1, sxtb #2
+ 107c: ab218fff cmn sp, w1, sxtb #3
+ 1080: ab2193ff cmn sp, w1, sxtb #4
+ 1084: ab21a3ff cmn sp, w1, sxth
+ 1088: ab21a3ff cmn sp, w1, sxth
+ 108c: ab21a7ff cmn sp, w1, sxth #1
+ 1090: ab21abff cmn sp, w1, sxth #2
+ 1094: ab21afff cmn sp, w1, sxth #3
+ 1098: ab21b3ff cmn sp, w1, sxth #4
+ 109c: ab21c3ff cmn sp, w1, sxtw
+ 10a0: ab21c3ff cmn sp, w1, sxtw
+ 10a4: ab21c7ff cmn sp, w1, sxtw #1
+ 10a8: ab21cbff cmn sp, w1, sxtw #2
+ 10ac: ab21cfff cmn sp, w1, sxtw #3
+ 10b0: ab21d3ff cmn sp, w1, sxtw #4
+ 10b4: ab21e3ff cmn sp, x1, sxtx
+ 10b8: ab21e3ff cmn sp, x1, sxtx
+ 10bc: ab21e7ff cmn sp, x1, sxtx #1
+ 10c0: ab21ebff cmn sp, x1, sxtx #2
+ 10c4: ab21efff cmn sp, x1, sxtx #3
+ 10c8: ab21f3ff cmn sp, x1, sxtx #4
+ 10cc: ab2163ff cmn sp, x1
+ 10d0: ab2167ff cmn sp, x1, lsl #1
+ 10d4: ab216bff cmn sp, x1, lsl #2
+ 10d8: ab216fff cmn sp, x1, lsl #3
+ 10dc: ab2173ff cmn sp, x1, lsl #4
+ 10e0: 6b0100ff cmp w7, w1
+ 10e4: 6b2100ff cmp w7, w1, uxtb
+ 10e8: 6b2100ff cmp w7, w1, uxtb
+ 10ec: 6b2104ff cmp w7, w1, uxtb #1
+ 10f0: 6b2108ff cmp w7, w1, uxtb #2
+ 10f4: 6b210cff cmp w7, w1, uxtb #3
+ 10f8: 6b2110ff cmp w7, w1, uxtb #4
+ 10fc: 6b2120ff cmp w7, w1, uxth
+ 1100: 6b2120ff cmp w7, w1, uxth
+ 1104: 6b2124ff cmp w7, w1, uxth #1
+ 1108: 6b2128ff cmp w7, w1, uxth #2
+ 110c: 6b212cff cmp w7, w1, uxth #3
+ 1110: 6b2130ff cmp w7, w1, uxth #4
+ 1114: 6b2140ff cmp w7, w1, uxtw
+ 1118: 6b2140ff cmp w7, w1, uxtw
+ 111c: 6b2144ff cmp w7, w1, uxtw #1
+ 1120: 6b2148ff cmp w7, w1, uxtw #2
+ 1124: 6b214cff cmp w7, w1, uxtw #3
+ 1128: 6b2150ff cmp w7, w1, uxtw #4
+ 112c: 6b2160ff cmp w7, w1, uxtx
+ 1130: 6b2160ff cmp w7, w1, uxtx
+ 1134: 6b2164ff cmp w7, w1, uxtx #1
+ 1138: 6b2168ff cmp w7, w1, uxtx #2
+ 113c: 6b216cff cmp w7, w1, uxtx #3
+ 1140: 6b2170ff cmp w7, w1, uxtx #4
+ 1144: 6b2180ff cmp w7, w1, sxtb
+ 1148: 6b2180ff cmp w7, w1, sxtb
+ 114c: 6b2184ff cmp w7, w1, sxtb #1
+ 1150: 6b2188ff cmp w7, w1, sxtb #2
+ 1154: 6b218cff cmp w7, w1, sxtb #3
+ 1158: 6b2190ff cmp w7, w1, sxtb #4
+ 115c: 6b21a0ff cmp w7, w1, sxth
+ 1160: 6b21a0ff cmp w7, w1, sxth
+ 1164: 6b21a4ff cmp w7, w1, sxth #1
+ 1168: 6b21a8ff cmp w7, w1, sxth #2
+ 116c: 6b21acff cmp w7, w1, sxth #3
+ 1170: 6b21b0ff cmp w7, w1, sxth #4
+ 1174: 6b21c0ff cmp w7, w1, sxtw
+ 1178: 6b21c0ff cmp w7, w1, sxtw
+ 117c: 6b21c4ff cmp w7, w1, sxtw #1
+ 1180: 6b21c8ff cmp w7, w1, sxtw #2
+ 1184: 6b21ccff cmp w7, w1, sxtw #3
+ 1188: 6b21d0ff cmp w7, w1, sxtw #4
+ 118c: 6b21e0ff cmp w7, w1, sxtx
+ 1190: 6b21e0ff cmp w7, w1, sxtx
+ 1194: 6b21e4ff cmp w7, w1, sxtx #1
+ 1198: 6b21e8ff cmp w7, w1, sxtx #2
+ 119c: 6b21ecff cmp w7, w1, sxtx #3
+ 11a0: 6b21f0ff cmp w7, w1, sxtx #4
+ 11a4: 6b0100ff cmp w7, w1
+ 11a8: 6b0104ff cmp w7, w1, lsl #1
+ 11ac: 6b0108ff cmp w7, w1, lsl #2
+ 11b0: 6b010cff cmp w7, w1, lsl #3
+ 11b4: 6b0110ff cmp w7, w1, lsl #4
+ 11b8: 6b2143ff cmp wsp, w1
+ 11bc: 6b2103ff cmp wsp, w1, uxtb
+ 11c0: 6b2103ff cmp wsp, w1, uxtb
+ 11c4: 6b2107ff cmp wsp, w1, uxtb #1
+ 11c8: 6b210bff cmp wsp, w1, uxtb #2
+ 11cc: 6b210fff cmp wsp, w1, uxtb #3
+ 11d0: 6b2113ff cmp wsp, w1, uxtb #4
+ 11d4: 6b2123ff cmp wsp, w1, uxth
+ 11d8: 6b2123ff cmp wsp, w1, uxth
+ 11dc: 6b2127ff cmp wsp, w1, uxth #1
+ 11e0: 6b212bff cmp wsp, w1, uxth #2
+ 11e4: 6b212fff cmp wsp, w1, uxth #3
+ 11e8: 6b2133ff cmp wsp, w1, uxth #4
+ 11ec: 6b2143ff cmp wsp, w1
+ 11f0: 6b2143ff cmp wsp, w1
+ 11f4: 6b2147ff cmp wsp, w1, lsl #1
+ 11f8: 6b214bff cmp wsp, w1, lsl #2
+ 11fc: 6b214fff cmp wsp, w1, lsl #3
+ 1200: 6b2153ff cmp wsp, w1, lsl #4
+ 1204: 6b2163ff cmp wsp, w1, uxtx
+ 1208: 6b2163ff cmp wsp, w1, uxtx
+ 120c: 6b2167ff cmp wsp, w1, uxtx #1
+ 1210: 6b216bff cmp wsp, w1, uxtx #2
+ 1214: 6b216fff cmp wsp, w1, uxtx #3
+ 1218: 6b2173ff cmp wsp, w1, uxtx #4
+ 121c: 6b2183ff cmp wsp, w1, sxtb
+ 1220: 6b2183ff cmp wsp, w1, sxtb
+ 1224: 6b2187ff cmp wsp, w1, sxtb #1
+ 1228: 6b218bff cmp wsp, w1, sxtb #2
+ 122c: 6b218fff cmp wsp, w1, sxtb #3
+ 1230: 6b2193ff cmp wsp, w1, sxtb #4
+ 1234: 6b21a3ff cmp wsp, w1, sxth
+ 1238: 6b21a3ff cmp wsp, w1, sxth
+ 123c: 6b21a7ff cmp wsp, w1, sxth #1
+ 1240: 6b21abff cmp wsp, w1, sxth #2
+ 1244: 6b21afff cmp wsp, w1, sxth #3
+ 1248: 6b21b3ff cmp wsp, w1, sxth #4
+ 124c: 6b21c3ff cmp wsp, w1, sxtw
+ 1250: 6b21c3ff cmp wsp, w1, sxtw
+ 1254: 6b21c7ff cmp wsp, w1, sxtw #1
+ 1258: 6b21cbff cmp wsp, w1, sxtw #2
+ 125c: 6b21cfff cmp wsp, w1, sxtw #3
+ 1260: 6b21d3ff cmp wsp, w1, sxtw #4
+ 1264: 6b21e3ff cmp wsp, w1, sxtx
+ 1268: 6b21e3ff cmp wsp, w1, sxtx
+ 126c: 6b21e7ff cmp wsp, w1, sxtx #1
+ 1270: 6b21ebff cmp wsp, w1, sxtx #2
+ 1274: 6b21efff cmp wsp, w1, sxtx #3
+ 1278: 6b21f3ff cmp wsp, w1, sxtx #4
+ 127c: 6b2143ff cmp wsp, w1
+ 1280: 6b2147ff cmp wsp, w1, lsl #1
+ 1284: 6b214bff cmp wsp, w1, lsl #2
+ 1288: 6b214fff cmp wsp, w1, lsl #3
+ 128c: 6b2153ff cmp wsp, w1, lsl #4
+ 1290: eb0100ff cmp x7, x1
+ 1294: eb2100ff cmp x7, w1, uxtb
+ 1298: eb2100ff cmp x7, w1, uxtb
+ 129c: eb2104ff cmp x7, w1, uxtb #1
+ 12a0: eb2108ff cmp x7, w1, uxtb #2
+ 12a4: eb210cff cmp x7, w1, uxtb #3
+ 12a8: eb2110ff cmp x7, w1, uxtb #4
+ 12ac: eb2120ff cmp x7, w1, uxth
+ 12b0: eb2120ff cmp x7, w1, uxth
+ 12b4: eb2124ff cmp x7, w1, uxth #1
+ 12b8: eb2128ff cmp x7, w1, uxth #2
+ 12bc: eb212cff cmp x7, w1, uxth #3
+ 12c0: eb2130ff cmp x7, w1, uxth #4
+ 12c4: eb2140ff cmp x7, w1, uxtw
+ 12c8: eb2140ff cmp x7, w1, uxtw
+ 12cc: eb2144ff cmp x7, w1, uxtw #1
+ 12d0: eb2148ff cmp x7, w1, uxtw #2
+ 12d4: eb214cff cmp x7, w1, uxtw #3
+ 12d8: eb2150ff cmp x7, w1, uxtw #4
+ 12dc: eb2160ff cmp x7, x1, uxtx
+ 12e0: eb2160ff cmp x7, x1, uxtx
+ 12e4: eb2164ff cmp x7, x1, uxtx #1
+ 12e8: eb2168ff cmp x7, x1, uxtx #2
+ 12ec: eb216cff cmp x7, x1, uxtx #3
+ 12f0: eb2170ff cmp x7, x1, uxtx #4
+ 12f4: eb2180ff cmp x7, w1, sxtb
+ 12f8: eb2180ff cmp x7, w1, sxtb
+ 12fc: eb2184ff cmp x7, w1, sxtb #1
+ 1300: eb2188ff cmp x7, w1, sxtb #2
+ 1304: eb218cff cmp x7, w1, sxtb #3
+ 1308: eb2190ff cmp x7, w1, sxtb #4
+ 130c: eb21a0ff cmp x7, w1, sxth
+ 1310: eb21a0ff cmp x7, w1, sxth
+ 1314: eb21a4ff cmp x7, w1, sxth #1
+ 1318: eb21a8ff cmp x7, w1, sxth #2
+ 131c: eb21acff cmp x7, w1, sxth #3
+ 1320: eb21b0ff cmp x7, w1, sxth #4
+ 1324: eb21c0ff cmp x7, w1, sxtw
+ 1328: eb21c0ff cmp x7, w1, sxtw
+ 132c: eb21c4ff cmp x7, w1, sxtw #1
+ 1330: eb21c8ff cmp x7, w1, sxtw #2
+ 1334: eb21ccff cmp x7, w1, sxtw #3
+ 1338: eb21d0ff cmp x7, w1, sxtw #4
+ 133c: eb21e0ff cmp x7, x1, sxtx
+ 1340: eb21e0ff cmp x7, x1, sxtx
+ 1344: eb21e4ff cmp x7, x1, sxtx #1
+ 1348: eb21e8ff cmp x7, x1, sxtx #2
+ 134c: eb21ecff cmp x7, x1, sxtx #3
+ 1350: eb21f0ff cmp x7, x1, sxtx #4
+ 1354: eb0100ff cmp x7, x1
+ 1358: eb0104ff cmp x7, x1, lsl #1
+ 135c: eb0108ff cmp x7, x1, lsl #2
+ 1360: eb010cff cmp x7, x1, lsl #3
+ 1364: eb0110ff cmp x7, x1, lsl #4
+ 1368: eb2163ff cmp sp, x1
+ 136c: eb2103ff cmp sp, w1, uxtb
+ 1370: eb2103ff cmp sp, w1, uxtb
+ 1374: eb2107ff cmp sp, w1, uxtb #1
+ 1378: eb210bff cmp sp, w1, uxtb #2
+ 137c: eb210fff cmp sp, w1, uxtb #3
+ 1380: eb2113ff cmp sp, w1, uxtb #4
+ 1384: eb2123ff cmp sp, w1, uxth
+ 1388: eb2123ff cmp sp, w1, uxth
+ 138c: eb2127ff cmp sp, w1, uxth #1
+ 1390: eb212bff cmp sp, w1, uxth #2
+ 1394: eb212fff cmp sp, w1, uxth #3
+ 1398: eb2133ff cmp sp, w1, uxth #4
+ 139c: eb2143ff cmp sp, w1, uxtw
+ 13a0: eb2143ff cmp sp, w1, uxtw
+ 13a4: eb2147ff cmp sp, w1, uxtw #1
+ 13a8: eb214bff cmp sp, w1, uxtw #2
+ 13ac: eb214fff cmp sp, w1, uxtw #3
+ 13b0: eb2153ff cmp sp, w1, uxtw #4
+ 13b4: eb2163ff cmp sp, x1
+ 13b8: eb2163ff cmp sp, x1
+ 13bc: eb2167ff cmp sp, x1, lsl #1
+ 13c0: eb216bff cmp sp, x1, lsl #2
+ 13c4: eb216fff cmp sp, x1, lsl #3
+ 13c8: eb2173ff cmp sp, x1, lsl #4
+ 13cc: eb2183ff cmp sp, w1, sxtb
+ 13d0: eb2183ff cmp sp, w1, sxtb
+ 13d4: eb2187ff cmp sp, w1, sxtb #1
+ 13d8: eb218bff cmp sp, w1, sxtb #2
+ 13dc: eb218fff cmp sp, w1, sxtb #3
+ 13e0: eb2193ff cmp sp, w1, sxtb #4
+ 13e4: eb21a3ff cmp sp, w1, sxth
+ 13e8: eb21a3ff cmp sp, w1, sxth
+ 13ec: eb21a7ff cmp sp, w1, sxth #1
+ 13f0: eb21abff cmp sp, w1, sxth #2
+ 13f4: eb21afff cmp sp, w1, sxth #3
+ 13f8: eb21b3ff cmp sp, w1, sxth #4
+ 13fc: eb21c3ff cmp sp, w1, sxtw
+ 1400: eb21c3ff cmp sp, w1, sxtw
+ 1404: eb21c7ff cmp sp, w1, sxtw #1
+ 1408: eb21cbff cmp sp, w1, sxtw #2
+ 140c: eb21cfff cmp sp, w1, sxtw #3
+ 1410: eb21d3ff cmp sp, w1, sxtw #4
+ 1414: eb21e3ff cmp sp, x1, sxtx
+ 1418: eb21e3ff cmp sp, x1, sxtx
+ 141c: eb21e7ff cmp sp, x1, sxtx #1
+ 1420: eb21ebff cmp sp, x1, sxtx #2
+ 1424: eb21efff cmp sp, x1, sxtx #3
+ 1428: eb21f3ff cmp sp, x1, sxtx #4
+ 142c: eb2163ff cmp sp, x1
+ 1430: eb2167ff cmp sp, x1, lsl #1
+ 1434: eb216bff cmp sp, x1, lsl #2
+ 1438: eb216fff cmp sp, x1, lsl #3
+ 143c: eb2173ff cmp sp, x1, lsl #4
+ 1440: 2b0100ff cmn w7, w1
+ 1444: 2b2100ff cmn w7, w1, uxtb
+ 1448: 2b2100ff cmn w7, w1, uxtb
+ 144c: 2b2104ff cmn w7, w1, uxtb #1
+ 1450: 2b2108ff cmn w7, w1, uxtb #2
+ 1454: 2b210cff cmn w7, w1, uxtb #3
+ 1458: 2b2110ff cmn w7, w1, uxtb #4
+ 145c: 2b2120ff cmn w7, w1, uxth
+ 1460: 2b2120ff cmn w7, w1, uxth
+ 1464: 2b2124ff cmn w7, w1, uxth #1
+ 1468: 2b2128ff cmn w7, w1, uxth #2
+ 146c: 2b212cff cmn w7, w1, uxth #3
+ 1470: 2b2130ff cmn w7, w1, uxth #4
+ 1474: 2b2140ff cmn w7, w1, uxtw
+ 1478: 2b2140ff cmn w7, w1, uxtw
+ 147c: 2b2144ff cmn w7, w1, uxtw #1
+ 1480: 2b2148ff cmn w7, w1, uxtw #2
+ 1484: 2b214cff cmn w7, w1, uxtw #3
+ 1488: 2b2150ff cmn w7, w1, uxtw #4
+ 148c: 2b2160ff cmn w7, w1, uxtx
+ 1490: 2b2160ff cmn w7, w1, uxtx
+ 1494: 2b2164ff cmn w7, w1, uxtx #1
+ 1498: 2b2168ff cmn w7, w1, uxtx #2
+ 149c: 2b216cff cmn w7, w1, uxtx #3
+ 14a0: 2b2170ff cmn w7, w1, uxtx #4
+ 14a4: 2b2180ff cmn w7, w1, sxtb
+ 14a8: 2b2180ff cmn w7, w1, sxtb
+ 14ac: 2b2184ff cmn w7, w1, sxtb #1
+ 14b0: 2b2188ff cmn w7, w1, sxtb #2
+ 14b4: 2b218cff cmn w7, w1, sxtb #3
+ 14b8: 2b2190ff cmn w7, w1, sxtb #4
+ 14bc: 2b21a0ff cmn w7, w1, sxth
+ 14c0: 2b21a0ff cmn w7, w1, sxth
+ 14c4: 2b21a4ff cmn w7, w1, sxth #1
+ 14c8: 2b21a8ff cmn w7, w1, sxth #2
+ 14cc: 2b21acff cmn w7, w1, sxth #3
+ 14d0: 2b21b0ff cmn w7, w1, sxth #4
+ 14d4: 2b21c0ff cmn w7, w1, sxtw
+ 14d8: 2b21c0ff cmn w7, w1, sxtw
+ 14dc: 2b21c4ff cmn w7, w1, sxtw #1
+ 14e0: 2b21c8ff cmn w7, w1, sxtw #2
+ 14e4: 2b21ccff cmn w7, w1, sxtw #3
+ 14e8: 2b21d0ff cmn w7, w1, sxtw #4
+ 14ec: 2b21e0ff cmn w7, w1, sxtx
+ 14f0: 2b21e0ff cmn w7, w1, sxtx
+ 14f4: 2b21e4ff cmn w7, w1, sxtx #1
+ 14f8: 2b21e8ff cmn w7, w1, sxtx #2
+ 14fc: 2b21ecff cmn w7, w1, sxtx #3
+ 1500: 2b21f0ff cmn w7, w1, sxtx #4
+ 1504: 2b0100ff cmn w7, w1
+ 1508: 2b0104ff cmn w7, w1, lsl #1
+ 150c: 2b0108ff cmn w7, w1, lsl #2
+ 1510: 2b010cff cmn w7, w1, lsl #3
+ 1514: 2b0110ff cmn w7, w1, lsl #4
+ 1518: 2b2143ff cmn wsp, w1
+ 151c: 2b2103ff cmn wsp, w1, uxtb
+ 1520: 2b2103ff cmn wsp, w1, uxtb
+ 1524: 2b2107ff cmn wsp, w1, uxtb #1
+ 1528: 2b210bff cmn wsp, w1, uxtb #2
+ 152c: 2b210fff cmn wsp, w1, uxtb #3
+ 1530: 2b2113ff cmn wsp, w1, uxtb #4
+ 1534: 2b2123ff cmn wsp, w1, uxth
+ 1538: 2b2123ff cmn wsp, w1, uxth
+ 153c: 2b2127ff cmn wsp, w1, uxth #1
+ 1540: 2b212bff cmn wsp, w1, uxth #2
+ 1544: 2b212fff cmn wsp, w1, uxth #3
+ 1548: 2b2133ff cmn wsp, w1, uxth #4
+ 154c: 2b2143ff cmn wsp, w1
+ 1550: 2b2143ff cmn wsp, w1
+ 1554: 2b2147ff cmn wsp, w1, lsl #1
+ 1558: 2b214bff cmn wsp, w1, lsl #2
+ 155c: 2b214fff cmn wsp, w1, lsl #3
+ 1560: 2b2153ff cmn wsp, w1, lsl #4
+ 1564: 2b2163ff cmn wsp, w1, uxtx
+ 1568: 2b2163ff cmn wsp, w1, uxtx
+ 156c: 2b2167ff cmn wsp, w1, uxtx #1
+ 1570: 2b216bff cmn wsp, w1, uxtx #2
+ 1574: 2b216fff cmn wsp, w1, uxtx #3
+ 1578: 2b2173ff cmn wsp, w1, uxtx #4
+ 157c: 2b2183ff cmn wsp, w1, sxtb
+ 1580: 2b2183ff cmn wsp, w1, sxtb
+ 1584: 2b2187ff cmn wsp, w1, sxtb #1
+ 1588: 2b218bff cmn wsp, w1, sxtb #2
+ 158c: 2b218fff cmn wsp, w1, sxtb #3
+ 1590: 2b2193ff cmn wsp, w1, sxtb #4
+ 1594: 2b21a3ff cmn wsp, w1, sxth
+ 1598: 2b21a3ff cmn wsp, w1, sxth
+ 159c: 2b21a7ff cmn wsp, w1, sxth #1
+ 15a0: 2b21abff cmn wsp, w1, sxth #2
+ 15a4: 2b21afff cmn wsp, w1, sxth #3
+ 15a8: 2b21b3ff cmn wsp, w1, sxth #4
+ 15ac: 2b21c3ff cmn wsp, w1, sxtw
+ 15b0: 2b21c3ff cmn wsp, w1, sxtw
+ 15b4: 2b21c7ff cmn wsp, w1, sxtw #1
+ 15b8: 2b21cbff cmn wsp, w1, sxtw #2
+ 15bc: 2b21cfff cmn wsp, w1, sxtw #3
+ 15c0: 2b21d3ff cmn wsp, w1, sxtw #4
+ 15c4: 2b21e3ff cmn wsp, w1, sxtx
+ 15c8: 2b21e3ff cmn wsp, w1, sxtx
+ 15cc: 2b21e7ff cmn wsp, w1, sxtx #1
+ 15d0: 2b21ebff cmn wsp, w1, sxtx #2
+ 15d4: 2b21efff cmn wsp, w1, sxtx #3
+ 15d8: 2b21f3ff cmn wsp, w1, sxtx #4
+ 15dc: 2b2143ff cmn wsp, w1
+ 15e0: 2b2147ff cmn wsp, w1, lsl #1
+ 15e4: 2b214bff cmn wsp, w1, lsl #2
+ 15e8: 2b214fff cmn wsp, w1, lsl #3
+ 15ec: 2b2153ff cmn wsp, w1, lsl #4
+ 15f0: ab0100ff cmn x7, x1
+ 15f4: ab2100ff cmn x7, w1, uxtb
+ 15f8: ab2100ff cmn x7, w1, uxtb
+ 15fc: ab2104ff cmn x7, w1, uxtb #1
+ 1600: ab2108ff cmn x7, w1, uxtb #2
+ 1604: ab210cff cmn x7, w1, uxtb #3
+ 1608: ab2110ff cmn x7, w1, uxtb #4
+ 160c: ab2120ff cmn x7, w1, uxth
+ 1610: ab2120ff cmn x7, w1, uxth
+ 1614: ab2124ff cmn x7, w1, uxth #1
+ 1618: ab2128ff cmn x7, w1, uxth #2
+ 161c: ab212cff cmn x7, w1, uxth #3
+ 1620: ab2130ff cmn x7, w1, uxth #4
+ 1624: ab2140ff cmn x7, w1, uxtw
+ 1628: ab2140ff cmn x7, w1, uxtw
+ 162c: ab2144ff cmn x7, w1, uxtw #1
+ 1630: ab2148ff cmn x7, w1, uxtw #2
+ 1634: ab214cff cmn x7, w1, uxtw #3
+ 1638: ab2150ff cmn x7, w1, uxtw #4
+ 163c: ab2160ff cmn x7, x1, uxtx
+ 1640: ab2160ff cmn x7, x1, uxtx
+ 1644: ab2164ff cmn x7, x1, uxtx #1
+ 1648: ab2168ff cmn x7, x1, uxtx #2
+ 164c: ab216cff cmn x7, x1, uxtx #3
+ 1650: ab2170ff cmn x7, x1, uxtx #4
+ 1654: ab2180ff cmn x7, w1, sxtb
+ 1658: ab2180ff cmn x7, w1, sxtb
+ 165c: ab2184ff cmn x7, w1, sxtb #1
+ 1660: ab2188ff cmn x7, w1, sxtb #2
+ 1664: ab218cff cmn x7, w1, sxtb #3
+ 1668: ab2190ff cmn x7, w1, sxtb #4
+ 166c: ab21a0ff cmn x7, w1, sxth
+ 1670: ab21a0ff cmn x7, w1, sxth
+ 1674: ab21a4ff cmn x7, w1, sxth #1
+ 1678: ab21a8ff cmn x7, w1, sxth #2
+ 167c: ab21acff cmn x7, w1, sxth #3
+ 1680: ab21b0ff cmn x7, w1, sxth #4
+ 1684: ab21c0ff cmn x7, w1, sxtw
+ 1688: ab21c0ff cmn x7, w1, sxtw
+ 168c: ab21c4ff cmn x7, w1, sxtw #1
+ 1690: ab21c8ff cmn x7, w1, sxtw #2
+ 1694: ab21ccff cmn x7, w1, sxtw #3
+ 1698: ab21d0ff cmn x7, w1, sxtw #4
+ 169c: ab21e0ff cmn x7, x1, sxtx
+ 16a0: ab21e0ff cmn x7, x1, sxtx
+ 16a4: ab21e4ff cmn x7, x1, sxtx #1
+ 16a8: ab21e8ff cmn x7, x1, sxtx #2
+ 16ac: ab21ecff cmn x7, x1, sxtx #3
+ 16b0: ab21f0ff cmn x7, x1, sxtx #4
+ 16b4: ab0100ff cmn x7, x1
+ 16b8: ab0104ff cmn x7, x1, lsl #1
+ 16bc: ab0108ff cmn x7, x1, lsl #2
+ 16c0: ab010cff cmn x7, x1, lsl #3
+ 16c4: ab0110ff cmn x7, x1, lsl #4
+ 16c8: ab2163ff cmn sp, x1
+ 16cc: ab2103ff cmn sp, w1, uxtb
+ 16d0: ab2103ff cmn sp, w1, uxtb
+ 16d4: ab2107ff cmn sp, w1, uxtb #1
+ 16d8: ab210bff cmn sp, w1, uxtb #2
+ 16dc: ab210fff cmn sp, w1, uxtb #3
+ 16e0: ab2113ff cmn sp, w1, uxtb #4
+ 16e4: ab2123ff cmn sp, w1, uxth
+ 16e8: ab2123ff cmn sp, w1, uxth
+ 16ec: ab2127ff cmn sp, w1, uxth #1
+ 16f0: ab212bff cmn sp, w1, uxth #2
+ 16f4: ab212fff cmn sp, w1, uxth #3
+ 16f8: ab2133ff cmn sp, w1, uxth #4
+ 16fc: ab2143ff cmn sp, w1, uxtw
+ 1700: ab2143ff cmn sp, w1, uxtw
+ 1704: ab2147ff cmn sp, w1, uxtw #1
+ 1708: ab214bff cmn sp, w1, uxtw #2
+ 170c: ab214fff cmn sp, w1, uxtw #3
+ 1710: ab2153ff cmn sp, w1, uxtw #4
+ 1714: ab2163ff cmn sp, x1
+ 1718: ab2163ff cmn sp, x1
+ 171c: ab2167ff cmn sp, x1, lsl #1
+ 1720: ab216bff cmn sp, x1, lsl #2
+ 1724: ab216fff cmn sp, x1, lsl #3
+ 1728: ab2173ff cmn sp, x1, lsl #4
+ 172c: ab2183ff cmn sp, w1, sxtb
+ 1730: ab2183ff cmn sp, w1, sxtb
+ 1734: ab2187ff cmn sp, w1, sxtb #1
+ 1738: ab218bff cmn sp, w1, sxtb #2
+ 173c: ab218fff cmn sp, w1, sxtb #3
+ 1740: ab2193ff cmn sp, w1, sxtb #4
+ 1744: ab21a3ff cmn sp, w1, sxth
+ 1748: ab21a3ff cmn sp, w1, sxth
+ 174c: ab21a7ff cmn sp, w1, sxth #1
+ 1750: ab21abff cmn sp, w1, sxth #2
+ 1754: ab21afff cmn sp, w1, sxth #3
+ 1758: ab21b3ff cmn sp, w1, sxth #4
+ 175c: ab21c3ff cmn sp, w1, sxtw
+ 1760: ab21c3ff cmn sp, w1, sxtw
+ 1764: ab21c7ff cmn sp, w1, sxtw #1
+ 1768: ab21cbff cmn sp, w1, sxtw #2
+ 176c: ab21cfff cmn sp, w1, sxtw #3
+ 1770: ab21d3ff cmn sp, w1, sxtw #4
+ 1774: ab21e3ff cmn sp, x1, sxtx
+ 1778: ab21e3ff cmn sp, x1, sxtx
+ 177c: ab21e7ff cmn sp, x1, sxtx #1
+ 1780: ab21ebff cmn sp, x1, sxtx #2
+ 1784: ab21efff cmn sp, x1, sxtx #3
+ 1788: ab21f3ff cmn sp, x1, sxtx #4
+ 178c: ab2163ff cmn sp, x1
+ 1790: ab2167ff cmn sp, x1, lsl #1
+ 1794: ab216bff cmn sp, x1, lsl #2
+ 1798: ab216fff cmn sp, x1, lsl #3
+ 179c: ab2173ff cmn sp, x1, lsl #4
+ 17a0: 6b0100ff cmp w7, w1
+ 17a4: 6b2100ff cmp w7, w1, uxtb
+ 17a8: 6b2100ff cmp w7, w1, uxtb
+ 17ac: 6b2104ff cmp w7, w1, uxtb #1
+ 17b0: 6b2108ff cmp w7, w1, uxtb #2
+ 17b4: 6b210cff cmp w7, w1, uxtb #3
+ 17b8: 6b2110ff cmp w7, w1, uxtb #4
+ 17bc: 6b2120ff cmp w7, w1, uxth
+ 17c0: 6b2120ff cmp w7, w1, uxth
+ 17c4: 6b2124ff cmp w7, w1, uxth #1
+ 17c8: 6b2128ff cmp w7, w1, uxth #2
+ 17cc: 6b212cff cmp w7, w1, uxth #3
+ 17d0: 6b2130ff cmp w7, w1, uxth #4
+ 17d4: 6b2140ff cmp w7, w1, uxtw
+ 17d8: 6b2140ff cmp w7, w1, uxtw
+ 17dc: 6b2144ff cmp w7, w1, uxtw #1
+ 17e0: 6b2148ff cmp w7, w1, uxtw #2
+ 17e4: 6b214cff cmp w7, w1, uxtw #3
+ 17e8: 6b2150ff cmp w7, w1, uxtw #4
+ 17ec: 6b2160ff cmp w7, w1, uxtx
+ 17f0: 6b2160ff cmp w7, w1, uxtx
+ 17f4: 6b2164ff cmp w7, w1, uxtx #1
+ 17f8: 6b2168ff cmp w7, w1, uxtx #2
+ 17fc: 6b216cff cmp w7, w1, uxtx #3
+ 1800: 6b2170ff cmp w7, w1, uxtx #4
+ 1804: 6b2180ff cmp w7, w1, sxtb
+ 1808: 6b2180ff cmp w7, w1, sxtb
+ 180c: 6b2184ff cmp w7, w1, sxtb #1
+ 1810: 6b2188ff cmp w7, w1, sxtb #2
+ 1814: 6b218cff cmp w7, w1, sxtb #3
+ 1818: 6b2190ff cmp w7, w1, sxtb #4
+ 181c: 6b21a0ff cmp w7, w1, sxth
+ 1820: 6b21a0ff cmp w7, w1, sxth
+ 1824: 6b21a4ff cmp w7, w1, sxth #1
+ 1828: 6b21a8ff cmp w7, w1, sxth #2
+ 182c: 6b21acff cmp w7, w1, sxth #3
+ 1830: 6b21b0ff cmp w7, w1, sxth #4
+ 1834: 6b21c0ff cmp w7, w1, sxtw
+ 1838: 6b21c0ff cmp w7, w1, sxtw
+ 183c: 6b21c4ff cmp w7, w1, sxtw #1
+ 1840: 6b21c8ff cmp w7, w1, sxtw #2
+ 1844: 6b21ccff cmp w7, w1, sxtw #3
+ 1848: 6b21d0ff cmp w7, w1, sxtw #4
+ 184c: 6b21e0ff cmp w7, w1, sxtx
+ 1850: 6b21e0ff cmp w7, w1, sxtx
+ 1854: 6b21e4ff cmp w7, w1, sxtx #1
+ 1858: 6b21e8ff cmp w7, w1, sxtx #2
+ 185c: 6b21ecff cmp w7, w1, sxtx #3
+ 1860: 6b21f0ff cmp w7, w1, sxtx #4
+ 1864: 6b0100ff cmp w7, w1
+ 1868: 6b0104ff cmp w7, w1, lsl #1
+ 186c: 6b0108ff cmp w7, w1, lsl #2
+ 1870: 6b010cff cmp w7, w1, lsl #3
+ 1874: 6b0110ff cmp w7, w1, lsl #4
+ 1878: 6b2143ff cmp wsp, w1
+ 187c: 6b2103ff cmp wsp, w1, uxtb
+ 1880: 6b2103ff cmp wsp, w1, uxtb
+ 1884: 6b2107ff cmp wsp, w1, uxtb #1
+ 1888: 6b210bff cmp wsp, w1, uxtb #2
+ 188c: 6b210fff cmp wsp, w1, uxtb #3
+ 1890: 6b2113ff cmp wsp, w1, uxtb #4
+ 1894: 6b2123ff cmp wsp, w1, uxth
+ 1898: 6b2123ff cmp wsp, w1, uxth
+ 189c: 6b2127ff cmp wsp, w1, uxth #1
+ 18a0: 6b212bff cmp wsp, w1, uxth #2
+ 18a4: 6b212fff cmp wsp, w1, uxth #3
+ 18a8: 6b2133ff cmp wsp, w1, uxth #4
+ 18ac: 6b2143ff cmp wsp, w1
+ 18b0: 6b2143ff cmp wsp, w1
+ 18b4: 6b2147ff cmp wsp, w1, lsl #1
+ 18b8: 6b214bff cmp wsp, w1, lsl #2
+ 18bc: 6b214fff cmp wsp, w1, lsl #3
+ 18c0: 6b2153ff cmp wsp, w1, lsl #4
+ 18c4: 6b2163ff cmp wsp, w1, uxtx
+ 18c8: 6b2163ff cmp wsp, w1, uxtx
+ 18cc: 6b2167ff cmp wsp, w1, uxtx #1
+ 18d0: 6b216bff cmp wsp, w1, uxtx #2
+ 18d4: 6b216fff cmp wsp, w1, uxtx #3
+ 18d8: 6b2173ff cmp wsp, w1, uxtx #4
+ 18dc: 6b2183ff cmp wsp, w1, sxtb
+ 18e0: 6b2183ff cmp wsp, w1, sxtb
+ 18e4: 6b2187ff cmp wsp, w1, sxtb #1
+ 18e8: 6b218bff cmp wsp, w1, sxtb #2
+ 18ec: 6b218fff cmp wsp, w1, sxtb #3
+ 18f0: 6b2193ff cmp wsp, w1, sxtb #4
+ 18f4: 6b21a3ff cmp wsp, w1, sxth
+ 18f8: 6b21a3ff cmp wsp, w1, sxth
+ 18fc: 6b21a7ff cmp wsp, w1, sxth #1
+ 1900: 6b21abff cmp wsp, w1, sxth #2
+ 1904: 6b21afff cmp wsp, w1, sxth #3
+ 1908: 6b21b3ff cmp wsp, w1, sxth #4
+ 190c: 6b21c3ff cmp wsp, w1, sxtw
+ 1910: 6b21c3ff cmp wsp, w1, sxtw
+ 1914: 6b21c7ff cmp wsp, w1, sxtw #1
+ 1918: 6b21cbff cmp wsp, w1, sxtw #2
+ 191c: 6b21cfff cmp wsp, w1, sxtw #3
+ 1920: 6b21d3ff cmp wsp, w1, sxtw #4
+ 1924: 6b21e3ff cmp wsp, w1, sxtx
+ 1928: 6b21e3ff cmp wsp, w1, sxtx
+ 192c: 6b21e7ff cmp wsp, w1, sxtx #1
+ 1930: 6b21ebff cmp wsp, w1, sxtx #2
+ 1934: 6b21efff cmp wsp, w1, sxtx #3
+ 1938: 6b21f3ff cmp wsp, w1, sxtx #4
+ 193c: 6b2143ff cmp wsp, w1
+ 1940: 6b2147ff cmp wsp, w1, lsl #1
+ 1944: 6b214bff cmp wsp, w1, lsl #2
+ 1948: 6b214fff cmp wsp, w1, lsl #3
+ 194c: 6b2153ff cmp wsp, w1, lsl #4
+ 1950: eb0100ff cmp x7, x1
+ 1954: eb2100ff cmp x7, w1, uxtb
+ 1958: eb2100ff cmp x7, w1, uxtb
+ 195c: eb2104ff cmp x7, w1, uxtb #1
+ 1960: eb2108ff cmp x7, w1, uxtb #2
+ 1964: eb210cff cmp x7, w1, uxtb #3
+ 1968: eb2110ff cmp x7, w1, uxtb #4
+ 196c: eb2120ff cmp x7, w1, uxth
+ 1970: eb2120ff cmp x7, w1, uxth
+ 1974: eb2124ff cmp x7, w1, uxth #1
+ 1978: eb2128ff cmp x7, w1, uxth #2
+ 197c: eb212cff cmp x7, w1, uxth #3
+ 1980: eb2130ff cmp x7, w1, uxth #4
+ 1984: eb2140ff cmp x7, w1, uxtw
+ 1988: eb2140ff cmp x7, w1, uxtw
+ 198c: eb2144ff cmp x7, w1, uxtw #1
+ 1990: eb2148ff cmp x7, w1, uxtw #2
+ 1994: eb214cff cmp x7, w1, uxtw #3
+ 1998: eb2150ff cmp x7, w1, uxtw #4
+ 199c: eb2160ff cmp x7, x1, uxtx
+ 19a0: eb2160ff cmp x7, x1, uxtx
+ 19a4: eb2164ff cmp x7, x1, uxtx #1
+ 19a8: eb2168ff cmp x7, x1, uxtx #2
+ 19ac: eb216cff cmp x7, x1, uxtx #3
+ 19b0: eb2170ff cmp x7, x1, uxtx #4
+ 19b4: eb2180ff cmp x7, w1, sxtb
+ 19b8: eb2180ff cmp x7, w1, sxtb
+ 19bc: eb2184ff cmp x7, w1, sxtb #1
+ 19c0: eb2188ff cmp x7, w1, sxtb #2
+ 19c4: eb218cff cmp x7, w1, sxtb #3
+ 19c8: eb2190ff cmp x7, w1, sxtb #4
+ 19cc: eb21a0ff cmp x7, w1, sxth
+ 19d0: eb21a0ff cmp x7, w1, sxth
+ 19d4: eb21a4ff cmp x7, w1, sxth #1
+ 19d8: eb21a8ff cmp x7, w1, sxth #2
+ 19dc: eb21acff cmp x7, w1, sxth #3
+ 19e0: eb21b0ff cmp x7, w1, sxth #4
+ 19e4: eb21c0ff cmp x7, w1, sxtw
+ 19e8: eb21c0ff cmp x7, w1, sxtw
+ 19ec: eb21c4ff cmp x7, w1, sxtw #1
+ 19f0: eb21c8ff cmp x7, w1, sxtw #2
+ 19f4: eb21ccff cmp x7, w1, sxtw #3
+ 19f8: eb21d0ff cmp x7, w1, sxtw #4
+ 19fc: eb21e0ff cmp x7, x1, sxtx
+ 1a00: eb21e0ff cmp x7, x1, sxtx
+ 1a04: eb21e4ff cmp x7, x1, sxtx #1
+ 1a08: eb21e8ff cmp x7, x1, sxtx #2
+ 1a0c: eb21ecff cmp x7, x1, sxtx #3
+ 1a10: eb21f0ff cmp x7, x1, sxtx #4
+ 1a14: eb0100ff cmp x7, x1
+ 1a18: eb0104ff cmp x7, x1, lsl #1
+ 1a1c: eb0108ff cmp x7, x1, lsl #2
+ 1a20: eb010cff cmp x7, x1, lsl #3
+ 1a24: eb0110ff cmp x7, x1, lsl #4
+ 1a28: eb2163ff cmp sp, x1
+ 1a2c: eb2103ff cmp sp, w1, uxtb
+ 1a30: eb2103ff cmp sp, w1, uxtb
+ 1a34: eb2107ff cmp sp, w1, uxtb #1
+ 1a38: eb210bff cmp sp, w1, uxtb #2
+ 1a3c: eb210fff cmp sp, w1, uxtb #3
+ 1a40: eb2113ff cmp sp, w1, uxtb #4
+ 1a44: eb2123ff cmp sp, w1, uxth
+ 1a48: eb2123ff cmp sp, w1, uxth
+ 1a4c: eb2127ff cmp sp, w1, uxth #1
+ 1a50: eb212bff cmp sp, w1, uxth #2
+ 1a54: eb212fff cmp sp, w1, uxth #3
+ 1a58: eb2133ff cmp sp, w1, uxth #4
+ 1a5c: eb2143ff cmp sp, w1, uxtw
+ 1a60: eb2143ff cmp sp, w1, uxtw
+ 1a64: eb2147ff cmp sp, w1, uxtw #1
+ 1a68: eb214bff cmp sp, w1, uxtw #2
+ 1a6c: eb214fff cmp sp, w1, uxtw #3
+ 1a70: eb2153ff cmp sp, w1, uxtw #4
+ 1a74: eb2163ff cmp sp, x1
+ 1a78: eb2163ff cmp sp, x1
+ 1a7c: eb2167ff cmp sp, x1, lsl #1
+ 1a80: eb216bff cmp sp, x1, lsl #2
+ 1a84: eb216fff cmp sp, x1, lsl #3
+ 1a88: eb2173ff cmp sp, x1, lsl #4
+ 1a8c: eb2183ff cmp sp, w1, sxtb
+ 1a90: eb2183ff cmp sp, w1, sxtb
+ 1a94: eb2187ff cmp sp, w1, sxtb #1
+ 1a98: eb218bff cmp sp, w1, sxtb #2
+ 1a9c: eb218fff cmp sp, w1, sxtb #3
+ 1aa0: eb2193ff cmp sp, w1, sxtb #4
+ 1aa4: eb21a3ff cmp sp, w1, sxth
+ 1aa8: eb21a3ff cmp sp, w1, sxth
+ 1aac: eb21a7ff cmp sp, w1, sxth #1
+ 1ab0: eb21abff cmp sp, w1, sxth #2
+ 1ab4: eb21afff cmp sp, w1, sxth #3
+ 1ab8: eb21b3ff cmp sp, w1, sxth #4
+ 1abc: eb21c3ff cmp sp, w1, sxtw
+ 1ac0: eb21c3ff cmp sp, w1, sxtw
+ 1ac4: eb21c7ff cmp sp, w1, sxtw #1
+ 1ac8: eb21cbff cmp sp, w1, sxtw #2
+ 1acc: eb21cfff cmp sp, w1, sxtw #3
+ 1ad0: eb21d3ff cmp sp, w1, sxtw #4
+ 1ad4: eb21e3ff cmp sp, x1, sxtx
+ 1ad8: eb21e3ff cmp sp, x1, sxtx
+ 1adc: eb21e7ff cmp sp, x1, sxtx #1
+ 1ae0: eb21ebff cmp sp, x1, sxtx #2
+ 1ae4: eb21efff cmp sp, x1, sxtx #3
+ 1ae8: eb21f3ff cmp sp, x1, sxtx #4
+ 1aec: eb2163ff cmp sp, x1
+ 1af0: eb2167ff cmp sp, x1, lsl #1
+ 1af4: eb216bff cmp sp, x1, lsl #2
+ 1af8: eb216fff cmp sp, x1, lsl #3
+ 1afc: eb2173ff cmp sp, x1, lsl #4
+ 1b00: 0b0100f0 add w16, w7, w1
+ 1b04: 0b0100f0 add w16, w7, w1
+ 1b08: 0b0104f0 add w16, w7, w1, lsl #1
+ 1b0c: 0b0108f0 add w16, w7, w1, lsl #2
+ 1b10: 0b010cf0 add w16, w7, w1, lsl #3
+ 1b14: 0b0110f0 add w16, w7, w1, lsl #4
+ 1b18: 0b0114f0 add w16, w7, w1, lsl #5
+ 1b1c: 0b0140f0 add w16, w7, w1, lsl #16
+ 1b20: 0b017cf0 add w16, w7, w1, lsl #31
+ 1b24: 0b4100f0 add w16, w7, w1, lsr #0
+ 1b28: 0b4104f0 add w16, w7, w1, lsr #1
+ 1b2c: 0b4108f0 add w16, w7, w1, lsr #2
+ 1b30: 0b410cf0 add w16, w7, w1, lsr #3
+ 1b34: 0b4110f0 add w16, w7, w1, lsr #4
+ 1b38: 0b4114f0 add w16, w7, w1, lsr #5
+ 1b3c: 0b4140f0 add w16, w7, w1, lsr #16
+ 1b40: 0b417cf0 add w16, w7, w1, lsr #31
+ 1b44: 0b8100f0 add w16, w7, w1, asr #0
+ 1b48: 0b8104f0 add w16, w7, w1, asr #1
+ 1b4c: 0b8108f0 add w16, w7, w1, asr #2
+ 1b50: 0b810cf0 add w16, w7, w1, asr #3
+ 1b54: 0b8110f0 add w16, w7, w1, asr #4
+ 1b58: 0b8114f0 add w16, w7, w1, asr #5
+ 1b5c: 0b8140f0 add w16, w7, w1, asr #16
+ 1b60: 0b817cf0 add w16, w7, w1, asr #31
+ 1b64: 8b0100f0 add x16, x7, x1
+ 1b68: 8b0100f0 add x16, x7, x1
+ 1b6c: 8b0104f0 add x16, x7, x1, lsl #1
+ 1b70: 8b0108f0 add x16, x7, x1, lsl #2
+ 1b74: 8b010cf0 add x16, x7, x1, lsl #3
+ 1b78: 8b0110f0 add x16, x7, x1, lsl #4
+ 1b7c: 8b0114f0 add x16, x7, x1, lsl #5
+ 1b80: 8b0140f0 add x16, x7, x1, lsl #16
+ 1b84: 8b017cf0 add x16, x7, x1, lsl #31
+ 1b88: 8b01fcf0 add x16, x7, x1, lsl #63
+ 1b8c: 8b4100f0 add x16, x7, x1, lsr #0
+ 1b90: 8b4104f0 add x16, x7, x1, lsr #1
+ 1b94: 8b4108f0 add x16, x7, x1, lsr #2
+ 1b98: 8b410cf0 add x16, x7, x1, lsr #3
+ 1b9c: 8b4110f0 add x16, x7, x1, lsr #4
+ 1ba0: 8b4114f0 add x16, x7, x1, lsr #5
+ 1ba4: 8b4140f0 add x16, x7, x1, lsr #16
+ 1ba8: 8b417cf0 add x16, x7, x1, lsr #31
+ 1bac: 8b41fcf0 add x16, x7, x1, lsr #63
+ 1bb0: 8b8100f0 add x16, x7, x1, asr #0
+ 1bb4: 8b8104f0 add x16, x7, x1, asr #1
+ 1bb8: 8b8108f0 add x16, x7, x1, asr #2
+ 1bbc: 8b810cf0 add x16, x7, x1, asr #3
+ 1bc0: 8b8110f0 add x16, x7, x1, asr #4
+ 1bc4: 8b8114f0 add x16, x7, x1, asr #5
+ 1bc8: 8b8140f0 add x16, x7, x1, asr #16
+ 1bcc: 8b817cf0 add x16, x7, x1, asr #31
+ 1bd0: 8b81fcf0 add x16, x7, x1, asr #63
+ 1bd4: 2b0100f0 adds w16, w7, w1
+ 1bd8: 2b0100f0 adds w16, w7, w1
+ 1bdc: 2b0104f0 adds w16, w7, w1, lsl #1
+ 1be0: 2b0108f0 adds w16, w7, w1, lsl #2
+ 1be4: 2b010cf0 adds w16, w7, w1, lsl #3
+ 1be8: 2b0110f0 adds w16, w7, w1, lsl #4
+ 1bec: 2b0114f0 adds w16, w7, w1, lsl #5
+ 1bf0: 2b0140f0 adds w16, w7, w1, lsl #16
+ 1bf4: 2b017cf0 adds w16, w7, w1, lsl #31
+ 1bf8: 2b4100f0 adds w16, w7, w1, lsr #0
+ 1bfc: 2b4104f0 adds w16, w7, w1, lsr #1
+ 1c00: 2b4108f0 adds w16, w7, w1, lsr #2
+ 1c04: 2b410cf0 adds w16, w7, w1, lsr #3
+ 1c08: 2b4110f0 adds w16, w7, w1, lsr #4
+ 1c0c: 2b4114f0 adds w16, w7, w1, lsr #5
+ 1c10: 2b4140f0 adds w16, w7, w1, lsr #16
+ 1c14: 2b417cf0 adds w16, w7, w1, lsr #31
+ 1c18: 2b8100f0 adds w16, w7, w1, asr #0
+ 1c1c: 2b8104f0 adds w16, w7, w1, asr #1
+ 1c20: 2b8108f0 adds w16, w7, w1, asr #2
+ 1c24: 2b810cf0 adds w16, w7, w1, asr #3
+ 1c28: 2b8110f0 adds w16, w7, w1, asr #4
+ 1c2c: 2b8114f0 adds w16, w7, w1, asr #5
+ 1c30: 2b8140f0 adds w16, w7, w1, asr #16
+ 1c34: 2b817cf0 adds w16, w7, w1, asr #31
+ 1c38: ab0100f0 adds x16, x7, x1
+ 1c3c: ab0100f0 adds x16, x7, x1
+ 1c40: ab0104f0 adds x16, x7, x1, lsl #1
+ 1c44: ab0108f0 adds x16, x7, x1, lsl #2
+ 1c48: ab010cf0 adds x16, x7, x1, lsl #3
+ 1c4c: ab0110f0 adds x16, x7, x1, lsl #4
+ 1c50: ab0114f0 adds x16, x7, x1, lsl #5
+ 1c54: ab0140f0 adds x16, x7, x1, lsl #16
+ 1c58: ab017cf0 adds x16, x7, x1, lsl #31
+ 1c5c: ab01fcf0 adds x16, x7, x1, lsl #63
+ 1c60: ab4100f0 adds x16, x7, x1, lsr #0
+ 1c64: ab4104f0 adds x16, x7, x1, lsr #1
+ 1c68: ab4108f0 adds x16, x7, x1, lsr #2
+ 1c6c: ab410cf0 adds x16, x7, x1, lsr #3
+ 1c70: ab4110f0 adds x16, x7, x1, lsr #4
+ 1c74: ab4114f0 adds x16, x7, x1, lsr #5
+ 1c78: ab4140f0 adds x16, x7, x1, lsr #16
+ 1c7c: ab417cf0 adds x16, x7, x1, lsr #31
+ 1c80: ab41fcf0 adds x16, x7, x1, lsr #63
+ 1c84: ab8100f0 adds x16, x7, x1, asr #0
+ 1c88: ab8104f0 adds x16, x7, x1, asr #1
+ 1c8c: ab8108f0 adds x16, x7, x1, asr #2
+ 1c90: ab810cf0 adds x16, x7, x1, asr #3
+ 1c94: ab8110f0 adds x16, x7, x1, asr #4
+ 1c98: ab8114f0 adds x16, x7, x1, asr #5
+ 1c9c: ab8140f0 adds x16, x7, x1, asr #16
+ 1ca0: ab817cf0 adds x16, x7, x1, asr #31
+ 1ca4: ab81fcf0 adds x16, x7, x1, asr #63
+ 1ca8: 4b0100f0 sub w16, w7, w1
+ 1cac: 4b0100f0 sub w16, w7, w1
+ 1cb0: 4b0104f0 sub w16, w7, w1, lsl #1
+ 1cb4: 4b0108f0 sub w16, w7, w1, lsl #2
+ 1cb8: 4b010cf0 sub w16, w7, w1, lsl #3
+ 1cbc: 4b0110f0 sub w16, w7, w1, lsl #4
+ 1cc0: 4b0114f0 sub w16, w7, w1, lsl #5
+ 1cc4: 4b0140f0 sub w16, w7, w1, lsl #16
+ 1cc8: 4b017cf0 sub w16, w7, w1, lsl #31
+ 1ccc: 4b4100f0 sub w16, w7, w1, lsr #0
+ 1cd0: 4b4104f0 sub w16, w7, w1, lsr #1
+ 1cd4: 4b4108f0 sub w16, w7, w1, lsr #2
+ 1cd8: 4b410cf0 sub w16, w7, w1, lsr #3
+ 1cdc: 4b4110f0 sub w16, w7, w1, lsr #4
+ 1ce0: 4b4114f0 sub w16, w7, w1, lsr #5
+ 1ce4: 4b4140f0 sub w16, w7, w1, lsr #16
+ 1ce8: 4b417cf0 sub w16, w7, w1, lsr #31
+ 1cec: 4b8100f0 sub w16, w7, w1, asr #0
+ 1cf0: 4b8104f0 sub w16, w7, w1, asr #1
+ 1cf4: 4b8108f0 sub w16, w7, w1, asr #2
+ 1cf8: 4b810cf0 sub w16, w7, w1, asr #3
+ 1cfc: 4b8110f0 sub w16, w7, w1, asr #4
+ 1d00: 4b8114f0 sub w16, w7, w1, asr #5
+ 1d04: 4b8140f0 sub w16, w7, w1, asr #16
+ 1d08: 4b817cf0 sub w16, w7, w1, asr #31
+ 1d0c: cb0100f0 sub x16, x7, x1
+ 1d10: cb0100f0 sub x16, x7, x1
+ 1d14: cb0104f0 sub x16, x7, x1, lsl #1
+ 1d18: cb0108f0 sub x16, x7, x1, lsl #2
+ 1d1c: cb010cf0 sub x16, x7, x1, lsl #3
+ 1d20: cb0110f0 sub x16, x7, x1, lsl #4
+ 1d24: cb0114f0 sub x16, x7, x1, lsl #5
+ 1d28: cb0140f0 sub x16, x7, x1, lsl #16
+ 1d2c: cb017cf0 sub x16, x7, x1, lsl #31
+ 1d30: cb01fcf0 sub x16, x7, x1, lsl #63
+ 1d34: cb4100f0 sub x16, x7, x1, lsr #0
+ 1d38: cb4104f0 sub x16, x7, x1, lsr #1
+ 1d3c: cb4108f0 sub x16, x7, x1, lsr #2
+ 1d40: cb410cf0 sub x16, x7, x1, lsr #3
+ 1d44: cb4110f0 sub x16, x7, x1, lsr #4
+ 1d48: cb4114f0 sub x16, x7, x1, lsr #5
+ 1d4c: cb4140f0 sub x16, x7, x1, lsr #16
+ 1d50: cb417cf0 sub x16, x7, x1, lsr #31
+ 1d54: cb41fcf0 sub x16, x7, x1, lsr #63
+ 1d58: cb8100f0 sub x16, x7, x1, asr #0
+ 1d5c: cb8104f0 sub x16, x7, x1, asr #1
+ 1d60: cb8108f0 sub x16, x7, x1, asr #2
+ 1d64: cb810cf0 sub x16, x7, x1, asr #3
+ 1d68: cb8110f0 sub x16, x7, x1, asr #4
+ 1d6c: cb8114f0 sub x16, x7, x1, asr #5
+ 1d70: cb8140f0 sub x16, x7, x1, asr #16
+ 1d74: cb817cf0 sub x16, x7, x1, asr #31
+ 1d78: cb81fcf0 sub x16, x7, x1, asr #63
+ 1d7c: 6b0100f0 subs w16, w7, w1
+ 1d80: 6b0100f0 subs w16, w7, w1
+ 1d84: 6b0104f0 subs w16, w7, w1, lsl #1
+ 1d88: 6b0108f0 subs w16, w7, w1, lsl #2
+ 1d8c: 6b010cf0 subs w16, w7, w1, lsl #3
+ 1d90: 6b0110f0 subs w16, w7, w1, lsl #4
+ 1d94: 6b0114f0 subs w16, w7, w1, lsl #5
+ 1d98: 6b0140f0 subs w16, w7, w1, lsl #16
+ 1d9c: 6b017cf0 subs w16, w7, w1, lsl #31
+ 1da0: 6b4100f0 subs w16, w7, w1, lsr #0
+ 1da4: 6b4104f0 subs w16, w7, w1, lsr #1
+ 1da8: 6b4108f0 subs w16, w7, w1, lsr #2
+ 1dac: 6b410cf0 subs w16, w7, w1, lsr #3
+ 1db0: 6b4110f0 subs w16, w7, w1, lsr #4
+ 1db4: 6b4114f0 subs w16, w7, w1, lsr #5
+ 1db8: 6b4140f0 subs w16, w7, w1, lsr #16
+ 1dbc: 6b417cf0 subs w16, w7, w1, lsr #31
+ 1dc0: 6b8100f0 subs w16, w7, w1, asr #0
+ 1dc4: 6b8104f0 subs w16, w7, w1, asr #1
+ 1dc8: 6b8108f0 subs w16, w7, w1, asr #2
+ 1dcc: 6b810cf0 subs w16, w7, w1, asr #3
+ 1dd0: 6b8110f0 subs w16, w7, w1, asr #4
+ 1dd4: 6b8114f0 subs w16, w7, w1, asr #5
+ 1dd8: 6b8140f0 subs w16, w7, w1, asr #16
+ 1ddc: 6b817cf0 subs w16, w7, w1, asr #31
+ 1de0: eb0100f0 subs x16, x7, x1
+ 1de4: eb0100f0 subs x16, x7, x1
+ 1de8: eb0104f0 subs x16, x7, x1, lsl #1
+ 1dec: eb0108f0 subs x16, x7, x1, lsl #2
+ 1df0: eb010cf0 subs x16, x7, x1, lsl #3
+ 1df4: eb0110f0 subs x16, x7, x1, lsl #4
+ 1df8: eb0114f0 subs x16, x7, x1, lsl #5
+ 1dfc: eb0140f0 subs x16, x7, x1, lsl #16
+ 1e00: eb017cf0 subs x16, x7, x1, lsl #31
+ 1e04: eb01fcf0 subs x16, x7, x1, lsl #63
+ 1e08: eb4100f0 subs x16, x7, x1, lsr #0
+ 1e0c: eb4104f0 subs x16, x7, x1, lsr #1
+ 1e10: eb4108f0 subs x16, x7, x1, lsr #2
+ 1e14: eb410cf0 subs x16, x7, x1, lsr #3
+ 1e18: eb4110f0 subs x16, x7, x1, lsr #4
+ 1e1c: eb4114f0 subs x16, x7, x1, lsr #5
+ 1e20: eb4140f0 subs x16, x7, x1, lsr #16
+ 1e24: eb417cf0 subs x16, x7, x1, lsr #31
+ 1e28: eb41fcf0 subs x16, x7, x1, lsr #63
+ 1e2c: eb8100f0 subs x16, x7, x1, asr #0
+ 1e30: eb8104f0 subs x16, x7, x1, asr #1
+ 1e34: eb8108f0 subs x16, x7, x1, asr #2
+ 1e38: eb810cf0 subs x16, x7, x1, asr #3
+ 1e3c: eb8110f0 subs x16, x7, x1, asr #4
+ 1e40: eb8114f0 subs x16, x7, x1, asr #5
+ 1e44: eb8140f0 subs x16, x7, x1, asr #16
+ 1e48: eb817cf0 subs x16, x7, x1, asr #31
+ 1e4c: eb81fcf0 subs x16, x7, x1, asr #63
+ 1e50: 2b0100ff cmn w7, w1
+ 1e54: 2b0100ff cmn w7, w1
+ 1e58: 2b0104ff cmn w7, w1, lsl #1
+ 1e5c: 2b0108ff cmn w7, w1, lsl #2
+ 1e60: 2b010cff cmn w7, w1, lsl #3
+ 1e64: 2b0110ff cmn w7, w1, lsl #4
+ 1e68: 2b0114ff cmn w7, w1, lsl #5
+ 1e6c: 2b0140ff cmn w7, w1, lsl #16
+ 1e70: 2b017cff cmn w7, w1, lsl #31
+ 1e74: 2b4100ff cmn w7, w1, lsr #0
+ 1e78: 2b4104ff cmn w7, w1, lsr #1
+ 1e7c: 2b4108ff cmn w7, w1, lsr #2
+ 1e80: 2b410cff cmn w7, w1, lsr #3
+ 1e84: 2b4110ff cmn w7, w1, lsr #4
+ 1e88: 2b4114ff cmn w7, w1, lsr #5
+ 1e8c: 2b4140ff cmn w7, w1, lsr #16
+ 1e90: 2b417cff cmn w7, w1, lsr #31
+ 1e94: 2b8100ff cmn w7, w1, asr #0
+ 1e98: 2b8104ff cmn w7, w1, asr #1
+ 1e9c: 2b8108ff cmn w7, w1, asr #2
+ 1ea0: 2b810cff cmn w7, w1, asr #3
+ 1ea4: 2b8110ff cmn w7, w1, asr #4
+ 1ea8: 2b8114ff cmn w7, w1, asr #5
+ 1eac: 2b8140ff cmn w7, w1, asr #16
+ 1eb0: 2b817cff cmn w7, w1, asr #31
+ 1eb4: ab0100ff cmn x7, x1
+ 1eb8: ab0100ff cmn x7, x1
+ 1ebc: ab0104ff cmn x7, x1, lsl #1
+ 1ec0: ab0108ff cmn x7, x1, lsl #2
+ 1ec4: ab010cff cmn x7, x1, lsl #3
+ 1ec8: ab0110ff cmn x7, x1, lsl #4
+ 1ecc: ab0114ff cmn x7, x1, lsl #5
+ 1ed0: ab0140ff cmn x7, x1, lsl #16
+ 1ed4: ab017cff cmn x7, x1, lsl #31
+ 1ed8: ab01fcff cmn x7, x1, lsl #63
+ 1edc: ab4100ff cmn x7, x1, lsr #0
+ 1ee0: ab4104ff cmn x7, x1, lsr #1
+ 1ee4: ab4108ff cmn x7, x1, lsr #2
+ 1ee8: ab410cff cmn x7, x1, lsr #3
+ 1eec: ab4110ff cmn x7, x1, lsr #4
+ 1ef0: ab4114ff cmn x7, x1, lsr #5
+ 1ef4: ab4140ff cmn x7, x1, lsr #16
+ 1ef8: ab417cff cmn x7, x1, lsr #31
+ 1efc: ab41fcff cmn x7, x1, lsr #63
+ 1f00: ab8100ff cmn x7, x1, asr #0
+ 1f04: ab8104ff cmn x7, x1, asr #1
+ 1f08: ab8108ff cmn x7, x1, asr #2
+ 1f0c: ab810cff cmn x7, x1, asr #3
+ 1f10: ab8110ff cmn x7, x1, asr #4
+ 1f14: ab8114ff cmn x7, x1, asr #5
+ 1f18: ab8140ff cmn x7, x1, asr #16
+ 1f1c: ab817cff cmn x7, x1, asr #31
+ 1f20: ab81fcff cmn x7, x1, asr #63
+ 1f24: 6b0100ff cmp w7, w1
+ 1f28: 6b0100ff cmp w7, w1
+ 1f2c: 6b0104ff cmp w7, w1, lsl #1
+ 1f30: 6b0108ff cmp w7, w1, lsl #2
+ 1f34: 6b010cff cmp w7, w1, lsl #3
+ 1f38: 6b0110ff cmp w7, w1, lsl #4
+ 1f3c: 6b0114ff cmp w7, w1, lsl #5
+ 1f40: 6b0140ff cmp w7, w1, lsl #16
+ 1f44: 6b017cff cmp w7, w1, lsl #31
+ 1f48: 6b4100ff cmp w7, w1, lsr #0
+ 1f4c: 6b4104ff cmp w7, w1, lsr #1
+ 1f50: 6b4108ff cmp w7, w1, lsr #2
+ 1f54: 6b410cff cmp w7, w1, lsr #3
+ 1f58: 6b4110ff cmp w7, w1, lsr #4
+ 1f5c: 6b4114ff cmp w7, w1, lsr #5
+ 1f60: 6b4140ff cmp w7, w1, lsr #16
+ 1f64: 6b417cff cmp w7, w1, lsr #31
+ 1f68: 6b8100ff cmp w7, w1, asr #0
+ 1f6c: 6b8104ff cmp w7, w1, asr #1
+ 1f70: 6b8108ff cmp w7, w1, asr #2
+ 1f74: 6b810cff cmp w7, w1, asr #3
+ 1f78: 6b8110ff cmp w7, w1, asr #4
+ 1f7c: 6b8114ff cmp w7, w1, asr #5
+ 1f80: 6b8140ff cmp w7, w1, asr #16
+ 1f84: 6b817cff cmp w7, w1, asr #31
+ 1f88: eb0100ff cmp x7, x1
+ 1f8c: eb0100ff cmp x7, x1
+ 1f90: eb0104ff cmp x7, x1, lsl #1
+ 1f94: eb0108ff cmp x7, x1, lsl #2
+ 1f98: eb010cff cmp x7, x1, lsl #3
+ 1f9c: eb0110ff cmp x7, x1, lsl #4
+ 1fa0: eb0114ff cmp x7, x1, lsl #5
+ 1fa4: eb0140ff cmp x7, x1, lsl #16
+ 1fa8: eb017cff cmp x7, x1, lsl #31
+ 1fac: eb01fcff cmp x7, x1, lsl #63
+ 1fb0: eb4100ff cmp x7, x1, lsr #0
+ 1fb4: eb4104ff cmp x7, x1, lsr #1
+ 1fb8: eb4108ff cmp x7, x1, lsr #2
+ 1fbc: eb410cff cmp x7, x1, lsr #3
+ 1fc0: eb4110ff cmp x7, x1, lsr #4
+ 1fc4: eb4114ff cmp x7, x1, lsr #5
+ 1fc8: eb4140ff cmp x7, x1, lsr #16
+ 1fcc: eb417cff cmp x7, x1, lsr #31
+ 1fd0: eb41fcff cmp x7, x1, lsr #63
+ 1fd4: eb8100ff cmp x7, x1, asr #0
+ 1fd8: eb8104ff cmp x7, x1, asr #1
+ 1fdc: eb8108ff cmp x7, x1, asr #2
+ 1fe0: eb810cff cmp x7, x1, asr #3
+ 1fe4: eb8110ff cmp x7, x1, asr #4
+ 1fe8: eb8114ff cmp x7, x1, asr #5
+ 1fec: eb8140ff cmp x7, x1, asr #16
+ 1ff0: eb817cff cmp x7, x1, asr #31
+ 1ff4: eb81fcff cmp x7, x1, asr #63
+ 1ff8: 2b0100ff cmn w7, w1
+ 1ffc: 2b0100ff cmn w7, w1
+ 2000: 2b0104ff cmn w7, w1, lsl #1
+ 2004: 2b0108ff cmn w7, w1, lsl #2
+ 2008: 2b010cff cmn w7, w1, lsl #3
+ 200c: 2b0110ff cmn w7, w1, lsl #4
+ 2010: 2b0114ff cmn w7, w1, lsl #5
+ 2014: 2b0140ff cmn w7, w1, lsl #16
+ 2018: 2b017cff cmn w7, w1, lsl #31
+ 201c: 2b4100ff cmn w7, w1, lsr #0
+ 2020: 2b4104ff cmn w7, w1, lsr #1
+ 2024: 2b4108ff cmn w7, w1, lsr #2
+ 2028: 2b410cff cmn w7, w1, lsr #3
+ 202c: 2b4110ff cmn w7, w1, lsr #4
+ 2030: 2b4114ff cmn w7, w1, lsr #5
+ 2034: 2b4140ff cmn w7, w1, lsr #16
+ 2038: 2b417cff cmn w7, w1, lsr #31
+ 203c: 2b8100ff cmn w7, w1, asr #0
+ 2040: 2b8104ff cmn w7, w1, asr #1
+ 2044: 2b8108ff cmn w7, w1, asr #2
+ 2048: 2b810cff cmn w7, w1, asr #3
+ 204c: 2b8110ff cmn w7, w1, asr #4
+ 2050: 2b8114ff cmn w7, w1, asr #5
+ 2054: 2b8140ff cmn w7, w1, asr #16
+ 2058: 2b817cff cmn w7, w1, asr #31
+ 205c: ab0100ff cmn x7, x1
+ 2060: ab0100ff cmn x7, x1
+ 2064: ab0104ff cmn x7, x1, lsl #1
+ 2068: ab0108ff cmn x7, x1, lsl #2
+ 206c: ab010cff cmn x7, x1, lsl #3
+ 2070: ab0110ff cmn x7, x1, lsl #4
+ 2074: ab0114ff cmn x7, x1, lsl #5
+ 2078: ab0140ff cmn x7, x1, lsl #16
+ 207c: ab017cff cmn x7, x1, lsl #31
+ 2080: ab01fcff cmn x7, x1, lsl #63
+ 2084: ab4100ff cmn x7, x1, lsr #0
+ 2088: ab4104ff cmn x7, x1, lsr #1
+ 208c: ab4108ff cmn x7, x1, lsr #2
+ 2090: ab410cff cmn x7, x1, lsr #3
+ 2094: ab4110ff cmn x7, x1, lsr #4
+ 2098: ab4114ff cmn x7, x1, lsr #5
+ 209c: ab4140ff cmn x7, x1, lsr #16
+ 20a0: ab417cff cmn x7, x1, lsr #31
+ 20a4: ab41fcff cmn x7, x1, lsr #63
+ 20a8: ab8100ff cmn x7, x1, asr #0
+ 20ac: ab8104ff cmn x7, x1, asr #1
+ 20b0: ab8108ff cmn x7, x1, asr #2
+ 20b4: ab810cff cmn x7, x1, asr #3
+ 20b8: ab8110ff cmn x7, x1, asr #4
+ 20bc: ab8114ff cmn x7, x1, asr #5
+ 20c0: ab8140ff cmn x7, x1, asr #16
+ 20c4: ab817cff cmn x7, x1, asr #31
+ 20c8: ab81fcff cmn x7, x1, asr #63
+ 20cc: 6b0100ff cmp w7, w1
+ 20d0: 6b0100ff cmp w7, w1
+ 20d4: 6b0104ff cmp w7, w1, lsl #1
+ 20d8: 6b0108ff cmp w7, w1, lsl #2
+ 20dc: 6b010cff cmp w7, w1, lsl #3
+ 20e0: 6b0110ff cmp w7, w1, lsl #4
+ 20e4: 6b0114ff cmp w7, w1, lsl #5
+ 20e8: 6b0140ff cmp w7, w1, lsl #16
+ 20ec: 6b017cff cmp w7, w1, lsl #31
+ 20f0: 6b4100ff cmp w7, w1, lsr #0
+ 20f4: 6b4104ff cmp w7, w1, lsr #1
+ 20f8: 6b4108ff cmp w7, w1, lsr #2
+ 20fc: 6b410cff cmp w7, w1, lsr #3
+ 2100: 6b4110ff cmp w7, w1, lsr #4
+ 2104: 6b4114ff cmp w7, w1, lsr #5
+ 2108: 6b4140ff cmp w7, w1, lsr #16
+ 210c: 6b417cff cmp w7, w1, lsr #31
+ 2110: 6b8100ff cmp w7, w1, asr #0
+ 2114: 6b8104ff cmp w7, w1, asr #1
+ 2118: 6b8108ff cmp w7, w1, asr #2
+ 211c: 6b810cff cmp w7, w1, asr #3
+ 2120: 6b8110ff cmp w7, w1, asr #4
+ 2124: 6b8114ff cmp w7, w1, asr #5
+ 2128: 6b8140ff cmp w7, w1, asr #16
+ 212c: 6b817cff cmp w7, w1, asr #31
+ 2130: eb0100ff cmp x7, x1
+ 2134: eb0100ff cmp x7, x1
+ 2138: eb0104ff cmp x7, x1, lsl #1
+ 213c: eb0108ff cmp x7, x1, lsl #2
+ 2140: eb010cff cmp x7, x1, lsl #3
+ 2144: eb0110ff cmp x7, x1, lsl #4
+ 2148: eb0114ff cmp x7, x1, lsl #5
+ 214c: eb0140ff cmp x7, x1, lsl #16
+ 2150: eb017cff cmp x7, x1, lsl #31
+ 2154: eb01fcff cmp x7, x1, lsl #63
+ 2158: eb4100ff cmp x7, x1, lsr #0
+ 215c: eb4104ff cmp x7, x1, lsr #1
+ 2160: eb4108ff cmp x7, x1, lsr #2
+ 2164: eb410cff cmp x7, x1, lsr #3
+ 2168: eb4110ff cmp x7, x1, lsr #4
+ 216c: eb4114ff cmp x7, x1, lsr #5
+ 2170: eb4140ff cmp x7, x1, lsr #16
+ 2174: eb417cff cmp x7, x1, lsr #31
+ 2178: eb41fcff cmp x7, x1, lsr #63
+ 217c: eb8100ff cmp x7, x1, asr #0
+ 2180: eb8104ff cmp x7, x1, asr #1
+ 2184: eb8108ff cmp x7, x1, asr #2
+ 2188: eb810cff cmp x7, x1, asr #3
+ 218c: eb8110ff cmp x7, x1, asr #4
+ 2190: eb8114ff cmp x7, x1, asr #5
+ 2194: eb8140ff cmp x7, x1, asr #16
+ 2198: eb817cff cmp x7, x1, asr #31
+ 219c: eb81fcff cmp x7, x1, asr #63
+ 21a0: 4b0103e7 neg w7, w1
+ 21a4: 4b0103e7 neg w7, w1
+ 21a8: 4b0107e7 neg w7, w1, lsl #1
+ 21ac: 4b010be7 neg w7, w1, lsl #2
+ 21b0: 4b010fe7 neg w7, w1, lsl #3
+ 21b4: 4b0113e7 neg w7, w1, lsl #4
+ 21b8: 4b0117e7 neg w7, w1, lsl #5
+ 21bc: 4b0143e7 neg w7, w1, lsl #16
+ 21c0: 4b017fe7 neg w7, w1, lsl #31
+ 21c4: 4b4103e7 neg w7, w1, lsr #0
+ 21c8: 4b4107e7 neg w7, w1, lsr #1
+ 21cc: 4b410be7 neg w7, w1, lsr #2
+ 21d0: 4b410fe7 neg w7, w1, lsr #3
+ 21d4: 4b4113e7 neg w7, w1, lsr #4
+ 21d8: 4b4117e7 neg w7, w1, lsr #5
+ 21dc: 4b4143e7 neg w7, w1, lsr #16
+ 21e0: 4b417fe7 neg w7, w1, lsr #31
+ 21e4: 4b8103e7 neg w7, w1, asr #0
+ 21e8: 4b8107e7 neg w7, w1, asr #1
+ 21ec: 4b810be7 neg w7, w1, asr #2
+ 21f0: 4b810fe7 neg w7, w1, asr #3
+ 21f4: 4b8113e7 neg w7, w1, asr #4
+ 21f8: 4b8117e7 neg w7, w1, asr #5
+ 21fc: 4b8143e7 neg w7, w1, asr #16
+ 2200: 4b817fe7 neg w7, w1, asr #31
+ 2204: cb0103e7 neg x7, x1
+ 2208: cb0103e7 neg x7, x1
+ 220c: cb0107e7 neg x7, x1, lsl #1
+ 2210: cb010be7 neg x7, x1, lsl #2
+ 2214: cb010fe7 neg x7, x1, lsl #3
+ 2218: cb0113e7 neg x7, x1, lsl #4
+ 221c: cb0117e7 neg x7, x1, lsl #5
+ 2220: cb0143e7 neg x7, x1, lsl #16
+ 2224: cb017fe7 neg x7, x1, lsl #31
+ 2228: cb01ffe7 neg x7, x1, lsl #63
+ 222c: cb4103e7 neg x7, x1, lsr #0
+ 2230: cb4107e7 neg x7, x1, lsr #1
+ 2234: cb410be7 neg x7, x1, lsr #2
+ 2238: cb410fe7 neg x7, x1, lsr #3
+ 223c: cb4113e7 neg x7, x1, lsr #4
+ 2240: cb4117e7 neg x7, x1, lsr #5
+ 2244: cb4143e7 neg x7, x1, lsr #16
+ 2248: cb417fe7 neg x7, x1, lsr #31
+ 224c: cb41ffe7 neg x7, x1, lsr #63
+ 2250: cb8103e7 neg x7, x1, asr #0
+ 2254: cb8107e7 neg x7, x1, asr #1
+ 2258: cb810be7 neg x7, x1, asr #2
+ 225c: cb810fe7 neg x7, x1, asr #3
+ 2260: cb8113e7 neg x7, x1, asr #4
+ 2264: cb8117e7 neg x7, x1, asr #5
+ 2268: cb8143e7 neg x7, x1, asr #16
+ 226c: cb817fe7 neg x7, x1, asr #31
+ 2270: cb81ffe7 neg x7, x1, asr #63
+ 2274: 6b0103e7 negs w7, w1
+ 2278: 6b0103e7 negs w7, w1
+ 227c: 6b0107e7 negs w7, w1, lsl #1
+ 2280: 6b010be7 negs w7, w1, lsl #2
+ 2284: 6b010fe7 negs w7, w1, lsl #3
+ 2288: 6b0113e7 negs w7, w1, lsl #4
+ 228c: 6b0117e7 negs w7, w1, lsl #5
+ 2290: 6b0143e7 negs w7, w1, lsl #16
+ 2294: 6b017fe7 negs w7, w1, lsl #31
+ 2298: 6b4103e7 negs w7, w1, lsr #0
+ 229c: 6b4107e7 negs w7, w1, lsr #1
+ 22a0: 6b410be7 negs w7, w1, lsr #2
+ 22a4: 6b410fe7 negs w7, w1, lsr #3
+ 22a8: 6b4113e7 negs w7, w1, lsr #4
+ 22ac: 6b4117e7 negs w7, w1, lsr #5
+ 22b0: 6b4143e7 negs w7, w1, lsr #16
+ 22b4: 6b417fe7 negs w7, w1, lsr #31
+ 22b8: 6b8103e7 negs w7, w1, asr #0
+ 22bc: 6b8107e7 negs w7, w1, asr #1
+ 22c0: 6b810be7 negs w7, w1, asr #2
+ 22c4: 6b810fe7 negs w7, w1, asr #3
+ 22c8: 6b8113e7 negs w7, w1, asr #4
+ 22cc: 6b8117e7 negs w7, w1, asr #5
+ 22d0: 6b8143e7 negs w7, w1, asr #16
+ 22d4: 6b817fe7 negs w7, w1, asr #31
+ 22d8: eb0103e7 negs x7, x1
+ 22dc: eb0103e7 negs x7, x1
+ 22e0: eb0107e7 negs x7, x1, lsl #1
+ 22e4: eb010be7 negs x7, x1, lsl #2
+ 22e8: eb010fe7 negs x7, x1, lsl #3
+ 22ec: eb0113e7 negs x7, x1, lsl #4
+ 22f0: eb0117e7 negs x7, x1, lsl #5
+ 22f4: eb0143e7 negs x7, x1, lsl #16
+ 22f8: eb017fe7 negs x7, x1, lsl #31
+ 22fc: eb01ffe7 negs x7, x1, lsl #63
+ 2300: eb4103e7 negs x7, x1, lsr #0
+ 2304: eb4107e7 negs x7, x1, lsr #1
+ 2308: eb410be7 negs x7, x1, lsr #2
+ 230c: eb410fe7 negs x7, x1, lsr #3
+ 2310: eb4113e7 negs x7, x1, lsr #4
+ 2314: eb4117e7 negs x7, x1, lsr #5
+ 2318: eb4143e7 negs x7, x1, lsr #16
+ 231c: eb417fe7 negs x7, x1, lsr #31
+ 2320: eb41ffe7 negs x7, x1, lsr #63
+ 2324: eb8103e7 negs x7, x1, asr #0
+ 2328: eb8107e7 negs x7, x1, asr #1
+ 232c: eb810be7 negs x7, x1, asr #2
+ 2330: eb810fe7 negs x7, x1, asr #3
+ 2334: eb8113e7 negs x7, x1, asr #4
+ 2338: eb8117e7 negs x7, x1, asr #5
+ 233c: eb8143e7 negs x7, x1, asr #16
+ 2340: eb817fe7 negs x7, x1, asr #31
+ 2344: eb81ffe7 negs x7, x1, asr #63
+ 2348: 4b0103e7 neg w7, w1
+ 234c: 4b0103e7 neg w7, w1
+ 2350: 4b0107e7 neg w7, w1, lsl #1
+ 2354: 4b010be7 neg w7, w1, lsl #2
+ 2358: 4b010fe7 neg w7, w1, lsl #3
+ 235c: 4b0113e7 neg w7, w1, lsl #4
+ 2360: 4b0117e7 neg w7, w1, lsl #5
+ 2364: 4b0143e7 neg w7, w1, lsl #16
+ 2368: 4b017fe7 neg w7, w1, lsl #31
+ 236c: 4b4103e7 neg w7, w1, lsr #0
+ 2370: 4b4107e7 neg w7, w1, lsr #1
+ 2374: 4b410be7 neg w7, w1, lsr #2
+ 2378: 4b410fe7 neg w7, w1, lsr #3
+ 237c: 4b4113e7 neg w7, w1, lsr #4
+ 2380: 4b4117e7 neg w7, w1, lsr #5
+ 2384: 4b4143e7 neg w7, w1, lsr #16
+ 2388: 4b417fe7 neg w7, w1, lsr #31
+ 238c: 4b8103e7 neg w7, w1, asr #0
+ 2390: 4b8107e7 neg w7, w1, asr #1
+ 2394: 4b810be7 neg w7, w1, asr #2
+ 2398: 4b810fe7 neg w7, w1, asr #3
+ 239c: 4b8113e7 neg w7, w1, asr #4
+ 23a0: 4b8117e7 neg w7, w1, asr #5
+ 23a4: 4b8143e7 neg w7, w1, asr #16
+ 23a8: 4b817fe7 neg w7, w1, asr #31
+ 23ac: cb0103e7 neg x7, x1
+ 23b0: cb0103e7 neg x7, x1
+ 23b4: cb0107e7 neg x7, x1, lsl #1
+ 23b8: cb010be7 neg x7, x1, lsl #2
+ 23bc: cb010fe7 neg x7, x1, lsl #3
+ 23c0: cb0113e7 neg x7, x1, lsl #4
+ 23c4: cb0117e7 neg x7, x1, lsl #5
+ 23c8: cb0143e7 neg x7, x1, lsl #16
+ 23cc: cb017fe7 neg x7, x1, lsl #31
+ 23d0: cb01ffe7 neg x7, x1, lsl #63
+ 23d4: cb4103e7 neg x7, x1, lsr #0
+ 23d8: cb4107e7 neg x7, x1, lsr #1
+ 23dc: cb410be7 neg x7, x1, lsr #2
+ 23e0: cb410fe7 neg x7, x1, lsr #3
+ 23e4: cb4113e7 neg x7, x1, lsr #4
+ 23e8: cb4117e7 neg x7, x1, lsr #5
+ 23ec: cb4143e7 neg x7, x1, lsr #16
+ 23f0: cb417fe7 neg x7, x1, lsr #31
+ 23f4: cb41ffe7 neg x7, x1, lsr #63
+ 23f8: cb8103e7 neg x7, x1, asr #0
+ 23fc: cb8107e7 neg x7, x1, asr #1
+ 2400: cb810be7 neg x7, x1, asr #2
+ 2404: cb810fe7 neg x7, x1, asr #3
+ 2408: cb8113e7 neg x7, x1, asr #4
+ 240c: cb8117e7 neg x7, x1, asr #5
+ 2410: cb8143e7 neg x7, x1, asr #16
+ 2414: cb817fe7 neg x7, x1, asr #31
+ 2418: cb81ffe7 neg x7, x1, asr #63
+ 241c: 6b0103e7 negs w7, w1
+ 2420: 6b0103e7 negs w7, w1
+ 2424: 6b0107e7 negs w7, w1, lsl #1
+ 2428: 6b010be7 negs w7, w1, lsl #2
+ 242c: 6b010fe7 negs w7, w1, lsl #3
+ 2430: 6b0113e7 negs w7, w1, lsl #4
+ 2434: 6b0117e7 negs w7, w1, lsl #5
+ 2438: 6b0143e7 negs w7, w1, lsl #16
+ 243c: 6b017fe7 negs w7, w1, lsl #31
+ 2440: 6b4103e7 negs w7, w1, lsr #0
+ 2444: 6b4107e7 negs w7, w1, lsr #1
+ 2448: 6b410be7 negs w7, w1, lsr #2
+ 244c: 6b410fe7 negs w7, w1, lsr #3
+ 2450: 6b4113e7 negs w7, w1, lsr #4
+ 2454: 6b4117e7 negs w7, w1, lsr #5
+ 2458: 6b4143e7 negs w7, w1, lsr #16
+ 245c: 6b417fe7 negs w7, w1, lsr #31
+ 2460: 6b8103e7 negs w7, w1, asr #0
+ 2464: 6b8107e7 negs w7, w1, asr #1
+ 2468: 6b810be7 negs w7, w1, asr #2
+ 246c: 6b810fe7 negs w7, w1, asr #3
+ 2470: 6b8113e7 negs w7, w1, asr #4
+ 2474: 6b8117e7 negs w7, w1, asr #5
+ 2478: 6b8143e7 negs w7, w1, asr #16
+ 247c: 6b817fe7 negs w7, w1, asr #31
+ 2480: eb0103e7 negs x7, x1
+ 2484: eb0103e7 negs x7, x1
+ 2488: eb0107e7 negs x7, x1, lsl #1
+ 248c: eb010be7 negs x7, x1, lsl #2
+ 2490: eb010fe7 negs x7, x1, lsl #3
+ 2494: eb0113e7 negs x7, x1, lsl #4
+ 2498: eb0117e7 negs x7, x1, lsl #5
+ 249c: eb0143e7 negs x7, x1, lsl #16
+ 24a0: eb017fe7 negs x7, x1, lsl #31
+ 24a4: eb01ffe7 negs x7, x1, lsl #63
+ 24a8: eb4103e7 negs x7, x1, lsr #0
+ 24ac: eb4107e7 negs x7, x1, lsr #1
+ 24b0: eb410be7 negs x7, x1, lsr #2
+ 24b4: eb410fe7 negs x7, x1, lsr #3
+ 24b8: eb4113e7 negs x7, x1, lsr #4
+ 24bc: eb4117e7 negs x7, x1, lsr #5
+ 24c0: eb4143e7 negs x7, x1, lsr #16
+ 24c4: eb417fe7 negs x7, x1, lsr #31
+ 24c8: eb41ffe7 negs x7, x1, lsr #63
+ 24cc: eb8103e7 negs x7, x1, asr #0
+ 24d0: eb8107e7 negs x7, x1, asr #1
+ 24d4: eb810be7 negs x7, x1, asr #2
+ 24d8: eb810fe7 negs x7, x1, asr #3
+ 24dc: eb8113e7 negs x7, x1, asr #4
+ 24e0: eb8117e7 negs x7, x1, asr #5
+ 24e4: eb8143e7 negs x7, x1, asr #16
+ 24e8: eb817fe7 negs x7, x1, asr #31
+ 24ec: eb81ffe7 negs x7, x1, asr #63
--- /dev/null
+/* addsub.s Test file for AArch64 add-subtract instructions.
+
+ Copyright 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+// TODO: also cover the addsub_imm instructions.
+
+ /*
+ * Adjust Rm
+ */
+ .macro adjust_rm op, rd, rn, rm_r, rm_n, extend, amount
+ // for 64-bit instruction, Rm is Xm when <extend> is explicitely
+ // or implicitly UXTX, SXTX or LSL; otherwise it Wm.
+ .ifc \rm_r, X
+ .ifnc \extend, UXTX
+ .ifnc \extend, SXTX
+ .ifnc \extend, LSL
+ .ifb \amount
+ \op \rd, \rn, W\()\rm_n, \extend
+ .else
+ \op \rd, \rn, W\()\rm_n, \extend #\amount
+ .endif
+ .exitm
+ .endif
+ .endif
+ .endif
+ .endif
+
+ .ifb \amount
+ \op \rd, \rn, \rm_r\()\rm_n, \extend
+ .else
+ \op \rd, \rn, \rm_r\()\rm_n, \extend #\amount
+ .endif
+ .endm
+
+ /*
+ * Emitting addsub_ext instruction
+ */
+ .macro do_addsub_ext type, op, Rn, reg, extend, amount
+ .ifc \type, 0
+ // normal add/adds/sub/subs
+ .ifb \extend
+ \op \reg\()16, \Rn, \reg\()1
+ .else
+ .ifb \amount
+ adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend
+ .else
+ adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend, \amount
+ .endif
+ .endif
+ .else
+ .ifc \type, 1
+ // adds/subs with ZR as Rd
+ .ifb \extend
+ \op \reg\()ZR, \Rn, \reg\()1
+ .else
+ .ifb \amount
+ adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend
+ .else
+ adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend, \amount
+ .endif
+ .endif
+ .else
+ // cmn/cmp
+ .ifb \extend
+ \op \Rn, \reg\()1
+ .else
+ .ifb \amount
+ \op \Rn, \reg\()1, \extend
+ .else
+ \op \Rn, \reg\()1, \extend #\amount
+ .endif
+ .endif
+ .endif
+ .endif
+ .endm
+
+ /*
+ * Optional extension and optional shift amount
+ */
+ .macro do_extend type, op, Rn, reg
+ // <extend> absent
+ // note that when SP is not used, the GAS will encode it as addsub_shift
+ do_addsub_ext \type, \op, \Rn, \reg
+ // optional absent <amount>
+ .irp extend, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX
+ .irp amount, , 0, 1, 2, 3, 4
+ do_addsub_ext \type, \op, \Rn, \reg, \extend, \amount
+ .endr
+ .endr
+ // when <extend> is LSL, <amount> cannot be absent
+ // note that when SP is not used, the GAS will encode it as addsub_shift
+ .irp amount, 0, 1, 2, 3, 4
+ do_addsub_ext \type, \op, \Rn, \reg, LSL, \amount
+ .endr
+ .endm
+
+ /*
+ * Leaf macro emitting addsub_shift instruction
+ */
+ .macro do_addsub_shift type, op, R, reg, shift, amount
+ .ifc \type, 0
+ // normal add/adds/sub/subs
+ .ifb \shift
+ \op \reg\()16, \R, \reg\()1
+ .else
+ \op \reg\()16, \R, \reg\()1, \shift #\amount
+ .endif
+ .else
+ .ifc \type, 1
+ // adds/subs with ZR as Rd
+ .ifb \shift
+ \op \reg\()ZR, \R, \reg\()1
+ .else
+ \op \reg\()ZR, \R, \reg\()1, \shift #\amount
+ .endif
+ .else
+ .ifc \type, 2
+ // cmn/cmp/neg/negs
+ .ifb \shift
+ \op \R, \reg\()1
+ .else
+ \op \R, \reg\()1, \shift #\amount
+ .endif
+ .else
+ // sub/subs with ZR as Rn
+ .ifb \shift
+ \op \R, \reg\()ZR, \reg\()1
+ .else
+ \op \R, \reg\()ZR, \reg\()1, \shift #\amount
+ .endif
+ .endif
+ .endif
+ .endif
+ .endm
+
+ /*
+ * Optional shift and optional shift amount
+ */
+ .macro do_shift type, op, R, reg
+ // <shift> absent
+ do_addsub_shift \type, \op, \R, \reg
+ // optional absent <amount>
+ .irp shift, LSL, LSR, ASR
+ .irp amount, 0, 1, 2, 3, 4, 5, 16, 31
+ // amount cannot be absent when shift is present.
+ do_addsub_shift \type, \op, \R, \reg, \shift, \amount
+ .endr
+ .ifc \reg, X
+ do_addsub_shift \type, \op, \R, \reg, \shift, 63
+ .endif
+ .endr
+ .endm
+
+func:
+ /*
+ * Add-subtract (extended register)
+ */
+
+ .irp op, ADD, ADDS, SUB, SUBS
+ do_extend 0, \op, W7, W
+ do_extend 0, \op, WSP, W
+ do_extend 0, \op, X7, X
+ do_extend 0, \op, SP, X
+ .endr
+
+ .irp op, ADDS, SUBS
+ do_extend 1, \op, W7, W
+ do_extend 1, \op, WSP, W
+ do_extend 1, \op, X7, X
+ do_extend 1, \op, SP, X
+ .endr
+
+ .irp op, CMN, CMP
+ do_extend 2, \op, W7, W
+ do_extend 2, \op, WSP, W
+ do_extend 2, \op, X7, X
+ do_extend 2, \op, SP, X
+ .endr
+
+ /*
+ * Add-subtract (shift register)
+ */
+
+ .irp op, ADD, ADDS, SUB, SUBS
+ do_shift 0, \op, W7, W
+ do_shift 0, \op, X7, X
+ .endr
+
+ .irp op, ADDS, SUBS
+ do_shift 1, \op, W7, W
+ do_shift 1, \op, X7, X
+ .endr
+
+ .irp op, CMN, CMP
+ do_shift 2, \op, W7, W
+ do_shift 2, \op, X7, X
+ .endr
+
+ .irp op, SUB, SUBS
+ do_shift 3, \op, W7, W
+ do_shift 3, \op, X7, X
+ .endr
+
+ .irp op, NEG, NEGS
+ do_shift 2, \op, W7, W
+ do_shift 2, \op, X7, X
+ .endr
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 0e303be7 saddlv h7, v31.8b
+ 4: 4e303be7 saddlv h7, v31.16b
+ 8: 0e703be7 saddlv s7, v31.4h
+ c: 4e703be7 saddlv s7, v31.8h
+ 10: 4eb03be7 saddlv d7, v31.4s
+ 14: 2e303be7 uaddlv h7, v31.8b
+ 18: 6e303be7 uaddlv h7, v31.16b
+ 1c: 2e703be7 uaddlv s7, v31.4h
+ 20: 6e703be7 uaddlv s7, v31.8h
+ 24: 6eb03be7 uaddlv d7, v31.4s
+ 28: 0e30abe7 smaxv b7, v31.8b
+ 2c: 4e30abe7 smaxv b7, v31.16b
+ 30: 0e70abe7 smaxv h7, v31.4h
+ 34: 4e70abe7 smaxv h7, v31.8h
+ 38: 4eb0abe7 smaxv s7, v31.4s
+ 3c: 2e30abe7 umaxv b7, v31.8b
+ 40: 6e30abe7 umaxv b7, v31.16b
+ 44: 2e70abe7 umaxv h7, v31.4h
+ 48: 6e70abe7 umaxv h7, v31.8h
+ 4c: 6eb0abe7 umaxv s7, v31.4s
+ 50: 0e31abe7 sminv b7, v31.8b
+ 54: 4e31abe7 sminv b7, v31.16b
+ 58: 0e71abe7 sminv h7, v31.4h
+ 5c: 4e71abe7 sminv h7, v31.8h
+ 60: 4eb1abe7 sminv s7, v31.4s
+ 64: 2e31abe7 uminv b7, v31.8b
+ 68: 6e31abe7 uminv b7, v31.16b
+ 6c: 2e71abe7 uminv h7, v31.4h
+ 70: 6e71abe7 uminv h7, v31.8h
+ 74: 6eb1abe7 uminv s7, v31.4s
+ 78: 0e31bbe7 addv b7, v31.8b
+ 7c: 4e31bbe7 addv b7, v31.16b
+ 80: 0e71bbe7 addv h7, v31.4h
+ 84: 4e71bbe7 addv h7, v31.8h
+ 88: 4eb1bbe7 addv s7, v31.4s
+ 8c: 6e30cbe7 fmaxnmv s7, v31.4s
+ 90: 6eb0cbe7 fminnmv s7, v31.4s
+ 94: 6e30fbe7 fmaxv s7, v31.4s
+ 98: 6eb0fbe7 fminv s7, v31.4s
--- /dev/null
+/* advsimd-across.s Test file for AArch64 Advanced-SIMD across
+ instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro asimdall op, V, T
+ \op \V\()7, v31.\()\T
+ .endm
+
+.text
+ .irp op, saddlv, uaddlv
+ asimdall \op, h, 8b
+ asimdall \op, h, 16b
+ asimdall \op, s, 4h
+ asimdall \op, s, 8h
+ asimdall \op, d, 4s
+ .endr
+
+ .irp op, smaxv, umaxv, sminv, uminv, addv
+ asimdall \op, b, 8b
+ asimdall \op, b, 16b
+ asimdall \op, h, 4h
+ asimdall \op, h, 8h
+ asimdall \op, s, 4s
+ .endr
+
+ .irp op, fmaxnmv, fminnmv, fmaxv, fminv
+ asimdall \op, s, 4s
+ .endr
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 0e20bbe0 abs v0.8b, v31.8b
+ 4: 4e20bbe0 abs v0.16b, v31.16b
+ 8: 0e60bbe0 abs v0.4h, v31.4h
+ c: 4e60bbe0 abs v0.8h, v31.8h
+ 10: 0ea0bbe0 abs v0.2s, v31.2s
+ 14: 4ea0bbe0 abs v0.4s, v31.4s
+ 18: 4ee0bbe0 abs v0.2d, v31.2d
+ 1c: 2e20bbe0 neg v0.8b, v31.8b
+ 20: 6e20bbe0 neg v0.16b, v31.16b
+ 24: 2e60bbe0 neg v0.4h, v31.4h
+ 28: 6e60bbe0 neg v0.8h, v31.8h
+ 2c: 2ea0bbe0 neg v0.2s, v31.2s
+ 30: 6ea0bbe0 neg v0.4s, v31.4s
+ 34: 6ee0bbe0 neg v0.2d, v31.2d
+ 38: 0e207be0 sqabs v0.8b, v31.8b
+ 3c: 4e207be0 sqabs v0.16b, v31.16b
+ 40: 0e607be0 sqabs v0.4h, v31.4h
+ 44: 4e607be0 sqabs v0.8h, v31.8h
+ 48: 0ea07be0 sqabs v0.2s, v31.2s
+ 4c: 4ea07be0 sqabs v0.4s, v31.4s
+ 50: 4ee07be0 sqabs v0.2d, v31.2d
+ 54: 2e207be0 sqneg v0.8b, v31.8b
+ 58: 6e207be0 sqneg v0.16b, v31.16b
+ 5c: 2e607be0 sqneg v0.4h, v31.4h
+ 60: 6e607be0 sqneg v0.8h, v31.8h
+ 64: 2ea07be0 sqneg v0.2s, v31.2s
+ 68: 6ea07be0 sqneg v0.4s, v31.4s
+ 6c: 6ee07be0 sqneg v0.2d, v31.2d
--- /dev/null
+/* advsimd-abs.s Test file for AArch64 Advanced-SIMD Integer absolute
+ instruction.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro asimdabs op, T
+ \op v0.\()\T, v31.\()\T
+ .endm
+
+ .text
+ .irp op, abs, neg, sqabs, sqneg
+ .irp type, 8b, 16b, 4h, 8h, 2s, 4s, 2d
+ asimdabs \op \type
+ .endr
+ .endr
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 5e0104ff mov b31, v7.b\[0\]
+ 4: 5e0304ff mov b31, v7.b\[1\]
+ 8: 5e0504ff mov b31, v7.b\[2\]
+ c: 5e0704ff mov b31, v7.b\[3\]
+ 10: 5e0904ff mov b31, v7.b\[4\]
+ 14: 5e0b04ff mov b31, v7.b\[5\]
+ 18: 5e0d04ff mov b31, v7.b\[6\]
+ 1c: 5e0f04ff mov b31, v7.b\[7\]
+ 20: 5e1104ff mov b31, v7.b\[8\]
+ 24: 5e1304ff mov b31, v7.b\[9\]
+ 28: 5e1504ff mov b31, v7.b\[10\]
+ 2c: 5e1704ff mov b31, v7.b\[11\]
+ 30: 5e1904ff mov b31, v7.b\[12\]
+ 34: 5e1b04ff mov b31, v7.b\[13\]
+ 38: 5e1d04ff mov b31, v7.b\[14\]
+ 3c: 5e1f04ff mov b31, v7.b\[15\]
+ 40: 5e0204ff mov h31, v7.h\[0\]
+ 44: 5e0604ff mov h31, v7.h\[1\]
+ 48: 5e0a04ff mov h31, v7.h\[2\]
+ 4c: 5e0e04ff mov h31, v7.h\[3\]
+ 50: 5e1204ff mov h31, v7.h\[4\]
+ 54: 5e1604ff mov h31, v7.h\[5\]
+ 58: 5e1a04ff mov h31, v7.h\[6\]
+ 5c: 5e1e04ff mov h31, v7.h\[7\]
+ 60: 5e0404ff mov s31, v7.s\[0\]
+ 64: 5e0c04ff mov s31, v7.s\[1\]
+ 68: 5e1404ff mov s31, v7.s\[2\]
+ 6c: 5e1c04ff mov s31, v7.s\[3\]
+ 70: 5e0804ff mov d31, v7.d\[0\]
+ 74: 5e1804ff mov d31, v7.d\[1\]
+ 78: 5e0104ff mov b31, v7.b\[0\]
+ 7c: 5e0304ff mov b31, v7.b\[1\]
+ 80: 5e0504ff mov b31, v7.b\[2\]
+ 84: 5e0704ff mov b31, v7.b\[3\]
+ 88: 5e0904ff mov b31, v7.b\[4\]
+ 8c: 5e0b04ff mov b31, v7.b\[5\]
+ 90: 5e0d04ff mov b31, v7.b\[6\]
+ 94: 5e0f04ff mov b31, v7.b\[7\]
+ 98: 5e1104ff mov b31, v7.b\[8\]
+ 9c: 5e1304ff mov b31, v7.b\[9\]
+ a0: 5e1504ff mov b31, v7.b\[10\]
+ a4: 5e1704ff mov b31, v7.b\[11\]
+ a8: 5e1904ff mov b31, v7.b\[12\]
+ ac: 5e1b04ff mov b31, v7.b\[13\]
+ b0: 5e1d04ff mov b31, v7.b\[14\]
+ b4: 5e1f04ff mov b31, v7.b\[15\]
+ b8: 5e0204ff mov h31, v7.h\[0\]
+ bc: 5e0604ff mov h31, v7.h\[1\]
+ c0: 5e0a04ff mov h31, v7.h\[2\]
+ c4: 5e0e04ff mov h31, v7.h\[3\]
+ c8: 5e1204ff mov h31, v7.h\[4\]
+ cc: 5e1604ff mov h31, v7.h\[5\]
+ d0: 5e1a04ff mov h31, v7.h\[6\]
+ d4: 5e1e04ff mov h31, v7.h\[7\]
+ d8: 5e0404ff mov s31, v7.s\[0\]
+ dc: 5e0c04ff mov s31, v7.s\[1\]
+ e0: 5e1404ff mov s31, v7.s\[2\]
+ e4: 5e1c04ff mov s31, v7.s\[3\]
+ e8: 5e0804ff mov d31, v7.d\[0\]
+ ec: 5e1804ff mov d31, v7.d\[1\]
--- /dev/null
+/* advsisd-copy.s Test file for AArch64 Advanced-SISD copy instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro element2scalar op, type, index
+ \op \type\()31, V7.\type[\index]
+ .endm
+
+ .macro iterate op, type, from, to
+ element2scalar \op, \type, \from
+ .if \to-\from
+ iterate \op, \type, "(\from+1)", \to
+ .endif
+ .endm
+
+.text
+ .irp op, dup, mov
+ iterate \op, b, 0, 15
+ iterate \op, h, 0, 7
+ iterate \op, s, 0, 3
+ iterate \op, d, 0, 1
+ .endr
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 5ee0bbe0 abs d0, d31
+ 4: 7ee0bbe0 neg d0, d31
+ 8: 5e207be0 sqabs b0, b31
+ c: 7e207be0 sqneg b0, b31
+ 10: 5e607be0 sqabs h0, h31
+ 14: 7e607be0 sqneg h0, h31
+ 18: 5ea07be0 sqabs s0, s31
+ 1c: 7ea07be0 sqneg s0, s31
+ 20: 5ee07be0 sqabs d0, d31
+ 24: 7ee07be0 sqneg d0, d31
--- /dev/null
+/* advsimd-abs.s Test file for AArch64 AdvSISD Scalar Misc
+ instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro asisd op T
+ \op \T\()0, \T\()31
+ .endm
+
+ .text
+ .irp op, abs, neg
+ asisd \op d
+ .endr
+
+ .irp type, b, h, s, d
+ .irp op, sqabs, sqneg
+ asisd \op \type
+ .endr
+ .endr
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 13823c20 extr w0, w1, w2, #15
+ 4: 93c23c20 extr x0, x1, x2, #15
+ 8: 13831c60 ror w0, w3, #7
+ c: 93c51ca0 ror x0, x5, #7
+ 10: 138748e6 ror w6, w7, #18
+ 14: 93c7a0e6 ror x6, x7, #40
+ 18: 1b020c20 madd w0, w1, w2, w3
+ 1c: 1b027c20 mul w0, w1, w2
+ 20: 1b027c20 mul w0, w1, w2
+ 24: 9b028c20 msub x0, x1, x2, x3
+ 28: 9b02fc20 mneg x0, x1, x2
+ 2c: 9b02fc20 mneg x0, x1, x2
+ 30: 9b220c20 smaddl x0, w1, w2, x3
+ 34: 9b227c20 smull x0, w1, w2
+ 38: 9b227c20 smull x0, w1, w2
+ 3c: 9b228c20 smsubl x0, w1, w2, x3
+ 40: 9b22fc20 smnegl x0, w1, w2
+ 44: 9b22fc20 smnegl x0, w1, w2
+ 48: 9ba20c20 umaddl x0, w1, w2, x3
+ 4c: 9ba27c20 umull x0, w1, w2
+ 50: 9ba27c20 umull x0, w1, w2
+ 54: 9ba28c20 umsubl x0, w1, w2, x3
+ 58: 9ba2fc20 umnegl x0, w1, w2
+ 5c: 9ba2fc20 umnegl x0, w1, w2
+ 60: 1a9f0420 csinc w0, w1, wzr, eq
+ 64: 1a810420 cinc w0, w1, ne
+ 68: 1a810420 cinc w0, w1, ne
+ 6c: 1a9f37e0 cset w0, cs
+ 70: 1a9f37e0 cset w0, cs
+ 74: da9f2020 csinv x0, x1, xzr, cs
+ 78: da812020 cinv x0, x1, cc
+ 7c: da812020 cinv x0, x1, cc
+ 80: da9f43e0 csetm x0, pl
+ 84: da9f43e0 csetm x0, pl
+ 88: da9eb7e0 csneg x0, xzr, x30, lt
+ 8c: da9eb7c0 cneg x0, x30, ge
+ 90: da9eb7c0 cneg x0, x30, ge
+ 94: ea020020 ands x0, x1, x2
+ 98: ea02003f tst x1, x2
+ 9c: ea02003f tst x1, x2
+ a0: 6ac27c3f tst w1, w2, ror #31
+ a4: 6ac27c3f tst w1, w2, ror #31
+ a8: aa220020 orn x0, x1, x2
+ ac: aa22003f orn xzr, x1, x2
+ b0: aa2203e0 mvn x0, x2
+ b4: aa2203e0 mvn x0, x2
+ b8: 2aa23c3f orn wzr, w1, w2, asr #15
+ bc: 2aa23fe0 mvn w0, w2, asr #15
+ c0: 2aa23fe0 mvn w0, w2, asr #15
+ c4: 0ea11c20 mov v0.8b, v1.8b
+ c8: 0ea21c20 orr v0.8b, v1.8b, v2.8b
+ cc: 0ea11c20 mov v0.8b, v1.8b
+ d0: aa1103e3 mov x3, x17
+ d4: aa110003 orr x3, x0, x17
+ d8: aa1103e3 mov x3, x17
+ dc: 92628421 and x1, x1, #0xffffffffc0000000
+ e0: 927ef800 and x0, x0, #0xfffffffffffffffd
+ e4: 121e7800 and w0, w0, #0xfffffffd
+ e8: 721d1f1f tst w24, #0x7f8
+ ec: 721d1f00 ands w0, w24, #0x7f8
+ f0: 721d1f1f tst w24, #0x7f8
+ f4: 7100807f cmp w3, #0x20
+ f8: 710083e3 subs w3, wsp, #0x20
+ fc: 7100807f cmp w3, #0x20
+ 100: b13ffdff cmn x15, #0xfff
+ 104: f13fffef subs x15, sp, #0xfff
+ 108: b13ffdff cmn x15, #0xfff
--- /dev/null
+/* alias.s Test file for AArch64 instructions aliases or disassembly
+ preference. It is also used to test the -Mno-aliases option in
+ the disassemler.
+
+ Copyright 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+.text
+ extr w0, w1, w2, #15
+ extr x0, x1, x2, #15
+ extr w0, w3, w3, #7
+ extr x0, x5, x5, #7
+ ror w6, w7, #18
+ ror x6, x7, #40
+
+ madd w0, w1, w2, w3
+ madd w0, w1, w2, wzr
+ mul w0, w1, w2
+ msub x0, x1, x2, x3
+ msub x0, x1, x2, xzr
+ mneg x0, x1, x2
+ smaddl x0, w1, w2, x3
+ smaddl x0, w1, w2, xzr
+ smull x0, w1, w2
+ smsubl x0, w1, w2, x3
+ smsubl x0, w1, w2, xzr
+ smnegl x0, w1, w2
+ umaddl x0, w1, w2, x3
+ umaddl x0, w1, w2, xzr
+ umull x0, w1, w2
+ umsubl x0, w1, w2, x3
+ umsubl x0, w1, w2, xzr
+ umnegl x0, w1, w2
+
+ csinc w0, w1, wzr, eq
+ csinc w0, w1, w1, eq
+ cinc w0, w1, ne
+ csinc w0, wzr, wzr, lo
+ cset w0, cs
+ csinv x0, x1, xzr, hs
+ csinv x0, x1, x1, hs
+ cinv x0, x1, cc
+ csinv x0, xzr, xzr, mi
+ csetm x0, pl
+ csneg x0, xzr, x30, lt
+ csneg x0, x30, x30, lt
+ cneg x0, x30, ge
+
+ ands x0, x1, x2
+ ands xzr, x1, x2
+ tst x1, x2
+ ands wzr, w1, w2, ror #31
+ tst w1, w2, ror #31
+
+ orn x0, x1, x2
+ orn xzr, x1, x2
+ orn x0, xzr, x2
+ mvn x0, x2
+ orn wzr, w1, w2, asr #15
+ orn w0, wzr, w2, asr #15
+ mvn w0, w2, asr #15
+
+ mov v0.8b, v1.8b
+ orr v0.8b, v1.8b, v2.8b
+ orr v0.8b, v1.8b, v1.8b
+
+ mov x3, x17
+ orr x3, x0, x17
+ orr x3, xzr, x17
+
+ bic x1, x1, #(1<<30)-1
+ bic x0, x0, #2
+ bic w0, w0, #2
+
+ ands wzr, w24, #0x7f8
+ ands w0, w24, #0x7f8
+ tst w24, #0x7f8
+
+ subs wzr, w3, #0x20
+ subs w3, wsp, #0x20
+ cmp w3, #0x20
+
+ adds xzr, x15, #0xfff
+ subs x15, sp, #0xfff
+ cmn x15, #0xfff
--- /dev/null
+#objdump: -dr
+#dump: bitfield-dump
--- /dev/null
+/* bitfield-alias.s Test file for AArch64 bitfield instructions
+ alias mnemonics.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+/* This file tests the GAS's ability in assembling the alias mnemonics
+ of sbfm, bfm and ubfm. Disassembler should prefer to use alias
+ mnemonics to display {[u|s]}bfm instructions.
+ bitfield-bfm.s and bitfield-alias.s will be assembled into idential
+ binary, which is why the two tests share the same dump match
+ file 'bitfield-dump'.
+ This assembly file is also used for the bitfield-no-aliases test. */
+
+ // <op> <Wd>, <Wn>
+ .macro bf_32r op
+ \op wzr, w7
+ .endm
+
+ // <op> <Xd>, <Wn>
+ .macro bf_64x op
+ \op xzr, w7
+ .endm
+
+ // <op> <Wd>, <Wn>, #<shift>
+ .macro bf_32s op, shift
+ \op wzr, w7, \shift
+ .endm
+
+ // <op> <Xd>, <Xn>, #<shift>
+ .macro bf_64s op, shift
+ \op xzr, x7, \shift
+ .endm
+
+ // <op> <Wd>, <Wn>, #<lsb>, #<width>
+ .macro bf_32 op, lsb, width
+ \op wzr, w7, #\lsb, #\width
+ .endm
+
+ // <op> <Xd>, <Xn>, #<lsb>, #<width>
+ .macro bf_64 op, lsb, width
+ \op xzr, x7, #\lsb, #\width
+ .endm
+
+.text
+ /*
+ * extend
+ */
+
+ bf_32r sxtb
+ bf_64x sxtb
+ bf_32r sxth
+ bf_64x sxth
+ bf_64x sxtw
+
+ bf_32r uxtb
+ bf_64x uxtb
+ bf_32r uxth
+ bf_64x uxth
+ bf_32r uxtw
+ bf_64x uxtw
+
+ /*
+ * shift
+ */
+
+ .irp op, asr, lsr, lsl
+ .irp shift, 0, 16, 31
+ bf_32s \op, \shift
+ .endr
+ .irp shift, 0, 31, 63
+ bf_64s \op, \shift
+ .endr
+ .endr
+
+ /*
+ * Insert & Extract
+ */
+
+ .irp op, sbfiz, sbfx, bfi, bfxil, ubfiz, ubfx
+ bf_32 \op, 0, 1
+ bf_32 \op, 0, 16
+ bf_32 \op, 0, 32
+ bf_32 \op, 16, 1
+ bf_32 \op, 16, 8
+ bf_32 \op, 16, 16
+ bf_32 \op, 31, 1
+
+ bf_64 \op, 0, 1
+ bf_64 \op, 0, 32
+ bf_64 \op, 0, 64
+ bf_64 \op, 32, 1
+ bf_64 \op, 32, 16
+ bf_64 \op, 32, 32
+ bf_64 \op, 63, 1
+ .endr
--- /dev/null
+#objdump: -dr
+#dump: bitfield-dump
--- /dev/null
+/* bitfield-bfm.s Test file for AArch64 bitfield instructions
+ sbfm, bfm and ubfm mnemonics.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+/* This file tests the GAS's ability in assembling sbfm, bfm and ubfm
+ instructions. Disassembler should use alias mnemonics to display
+ {[u|s]}bfm instructions. bitfield-bfm.s and bitfield-alias.s will be
+ assembled into idential binary, which is why the two tests share the
+ same dump match file 'bitfield-dump'. */
+
+ // <op> <Wd>, <Wn>
+ .macro bf_32r op
+ \op wzr, w7
+ .endm
+
+ // <op> <Xd>, <Wn>
+ .macro bf_64x op
+ \op xzr, w7
+ .endm
+
+ // <op> <Wd>, <Wn>, #<shift>
+ .macro bf_32s op, shift
+ \op wzr, w7, \shift
+ .endm
+
+ // <op> <Xd>, <Xn>, #<shift>
+ .macro bf_64s op, shift
+ \op xzr, x7, \shift
+ .endm
+
+
+ .macro op_bfm signed, reg, immr, imms
+ \signed\()bfm \reg\()zr, \reg\()7, #\immr, #\imms // e.g. sbfm xzr, x7, #0, #15
+ .endm
+
+ .macro ext2bfm signed, reg, imms
+ op_bfm signed=\signed, reg=\reg, immr=0, imms=\imms
+ .endm
+
+ // shift right -> bfm
+ .macro sr2bfm signed, reg, shift, imms
+ op_bfm signed=\signed, reg=\reg, immr=\shift, imms=\imms
+ .endm
+
+ // shift left -> bfm
+ .macro sl2bfm signed, reg, shift
+ .ifc \reg, w
+ op_bfm signed=\signed, reg=\reg, immr="((32-\shift)&31)", imms="(31-\shift)"
+ .else
+ op_bfm signed=\signed, reg=\reg, immr="((64-\shift)&63)", imms="(63-\shift)"
+ .endif
+ .endm
+
+ // bitfield insert -> bfm
+ .macro ins2bfm signed, reg, lsb, width
+ .ifc \reg, w
+ op_bfm signed=\signed, reg=\reg, immr="((32-\lsb)&31)", imms="(\width-1)"
+ .else
+ op_bfm signed=\signed, reg=\reg, immr="((64-\lsb)&63)", imms="(\width-1)"
+ .endif
+ .endm
+
+ // bitfield extract -> bfm
+ .macro x2bfm signed, reg, lsb, width
+ op_bfm signed=\signed, reg=\reg, immr=\lsb, imms="(\lsb+\width-1)"
+ .endm
+
+.text
+ /*
+ * aliasing extend
+ */
+
+ ext2bfm s, w, 7 // sxtb wzr, w7
+ ext2bfm s, x, 7 // sxtb xzr, x7
+ ext2bfm s, w, 15 // sxth wzr, w7
+ ext2bfm s, x, 15 // sxth xzr, x7
+ ext2bfm s, x, 31 // sxtw xzr, x7
+
+ ext2bfm u, w, 7 // uxtb wzr, w7
+ ext2bfm u, w, 7 // uxtb xzr, w7
+ ext2bfm u, w, 15 // uxth wzr, w7
+ ext2bfm u, w, 15 // uxth xzr, w7
+ orr wzr, wzr, w7 // uxtw wzr, w7
+ orr wzr, wzr, w7 // uxtw wzr, w7
+
+ /*
+ * aliasing shift
+ */
+
+ .irp shift 0, 16, 31 // asr wzr, w7, #\shift
+ sr2bfm s, w, \shift, 31
+ .endr
+
+ .irp shift 0, 31, 63 // asr xzr, x7, #\shift
+ sr2bfm s, x, \shift, 63
+ .endr
+
+ .irp shift 0, 16, 31 // lsr wzr, w7, #\shift
+ sr2bfm u, w, \shift, 31
+ .endr
+
+ .irp shift 0, 31, 63 // lsr xzr, x7, #\shift
+ sr2bfm u, x, \shift, 63
+ .endr
+
+ .irp shift 0, 16, 31 // lsl wzr, w7, #\shift
+ sl2bfm u, w, \shift
+ .endr
+
+ .irp shift 0, 31, 63 // lsl xzr, x7, #\shift
+ sl2bfm u, x, \shift
+ .endr
+
+ /*
+ * aliasing insert and extract
+ */
+
+ .irp signed, s, , u
+ .irp whichm, ins2bfm, x2bfm
+ \whichm \signed, w, 0, 1
+ \whichm \signed, w, 0, 16
+ \whichm \signed, w, 0, 32
+ \whichm \signed, w, 16, 1
+ \whichm \signed, w, 16, 8
+ \whichm \signed, w, 16, 16
+ \whichm \signed, w, 31, 1
+
+ \whichm \signed, x, 0, 1
+ \whichm \signed, x, 0, 32
+ \whichm \signed, x, 0, 64
+ \whichm \signed, x, 32, 1
+ \whichm \signed, x, 32, 16
+ \whichm \signed, x, 32, 32
+ \whichm \signed, x, 63, 1
+ .endr
+ .endr
--- /dev/null
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 13001cff sxtb wzr, w7
+ 4: 93401cff sxtb xzr, w7
+ 8: 13003cff sxth wzr, w7
+ c: 93403cff sxth xzr, w7
+ 10: 93407cff sxtw xzr, w7
+ 14: 53001cff uxtb wzr, w7
+ 18: 53001cff uxtb wzr, w7
+ 1c: 53003cff uxth wzr, w7
+ 20: 53003cff uxth wzr, w7
+ 24: 2a0703ff mov wzr, w7
+ 28: 2a0703ff mov wzr, w7
+ 2c: 13007cff asr wzr, w7, #0
+ 30: 13107cff asr wzr, w7, #16
+ 34: 131f7cff asr wzr, w7, #31
+ 38: 9340fcff asr xzr, x7, #0
+ 3c: 935ffcff asr xzr, x7, #31
+ 40: 937ffcff asr xzr, x7, #63
+ 44: 53007cff lsr wzr, w7, #0
+ 48: 53107cff lsr wzr, w7, #16
+ 4c: 531f7cff lsr wzr, w7, #31
+ 50: d340fcff lsr xzr, x7, #0
+ 54: d35ffcff lsr xzr, x7, #31
+ 58: d37ffcff lsr xzr, x7, #63
+ 5c: 53007cff lsr wzr, w7, #0
+ 60: 53103cff lsl wzr, w7, #16
+ 64: 530100ff lsl wzr, w7, #31
+ 68: d340fcff lsr xzr, x7, #0
+ 6c: d36180ff lsl xzr, x7, #31
+ 70: d34100ff lsl xzr, x7, #63
+ 74: 130000ff sbfx wzr, w7, #0, #1
+ 78: 13003cff sxth wzr, w7
+ 7c: 13007cff asr wzr, w7, #0
+ 80: 131000ff sbfiz wzr, w7, #16, #1
+ 84: 13101cff sbfiz wzr, w7, #16, #8
+ 88: 13103cff sbfiz wzr, w7, #16, #16
+ 8c: 130100ff sbfiz wzr, w7, #31, #1
+ 90: 934000ff sbfx xzr, x7, #0, #1
+ 94: 93407cff sxtw xzr, w7
+ 98: 9340fcff asr xzr, x7, #0
+ 9c: 936000ff sbfiz xzr, x7, #32, #1
+ a0: 93603cff sbfiz xzr, x7, #32, #16
+ a4: 93607cff sbfiz xzr, x7, #32, #32
+ a8: 934100ff sbfiz xzr, x7, #63, #1
+ ac: 130000ff sbfx wzr, w7, #0, #1
+ b0: 13003cff sxth wzr, w7
+ b4: 13007cff asr wzr, w7, #0
+ b8: 131040ff sbfx wzr, w7, #16, #1
+ bc: 13105cff sbfx wzr, w7, #16, #8
+ c0: 13107cff asr wzr, w7, #16
+ c4: 131f7cff asr wzr, w7, #31
+ c8: 934000ff sbfx xzr, x7, #0, #1
+ cc: 93407cff sxtw xzr, w7
+ d0: 9340fcff asr xzr, x7, #0
+ d4: 936080ff sbfx xzr, x7, #32, #1
+ d8: 9360bcff sbfx xzr, x7, #32, #16
+ dc: 9360fcff asr xzr, x7, #32
+ e0: 937ffcff asr xzr, x7, #63
+ e4: 330000ff bfxil wzr, w7, #0, #1
+ e8: 33003cff bfxil wzr, w7, #0, #16
+ ec: 33007cff bfxil wzr, w7, #0, #32
+ f0: 331000ff bfi wzr, w7, #16, #1
+ f4: 33101cff bfi wzr, w7, #16, #8
+ f8: 33103cff bfi wzr, w7, #16, #16
+ fc: 330100ff bfi wzr, w7, #31, #1
+ 100: b34000ff bfxil xzr, x7, #0, #1
+ 104: b3407cff bfxil xzr, x7, #0, #32
+ 108: b340fcff bfxil xzr, x7, #0, #64
+ 10c: b36000ff bfi xzr, x7, #32, #1
+ 110: b3603cff bfi xzr, x7, #32, #16
+ 114: b3607cff bfi xzr, x7, #32, #32
+ 118: b34100ff bfi xzr, x7, #63, #1
+ 11c: 330000ff bfxil wzr, w7, #0, #1
+ 120: 33003cff bfxil wzr, w7, #0, #16
+ 124: 33007cff bfxil wzr, w7, #0, #32
+ 128: 331040ff bfxil wzr, w7, #16, #1
+ 12c: 33105cff bfxil wzr, w7, #16, #8
+ 130: 33107cff bfxil wzr, w7, #16, #16
+ 134: 331f7cff bfxil wzr, w7, #31, #1
+ 138: b34000ff bfxil xzr, x7, #0, #1
+ 13c: b3407cff bfxil xzr, x7, #0, #32
+ 140: b340fcff bfxil xzr, x7, #0, #64
+ 144: b36080ff bfxil xzr, x7, #32, #1
+ 148: b360bcff bfxil xzr, x7, #32, #16
+ 14c: b360fcff bfxil xzr, x7, #32, #32
+ 150: b37ffcff bfxil xzr, x7, #63, #1
+ 154: 530000ff ubfx wzr, w7, #0, #1
+ 158: 53003cff uxth wzr, w7
+ 15c: 53007cff lsr wzr, w7, #0
+ 160: 531000ff ubfiz wzr, w7, #16, #1
+ 164: 53101cff ubfiz wzr, w7, #16, #8
+ 168: 53103cff lsl wzr, w7, #16
+ 16c: 530100ff lsl wzr, w7, #31
+ 170: d34000ff ubfx xzr, x7, #0, #1
+ 174: d3407cff ubfx xzr, x7, #0, #32
+ 178: d340fcff lsr xzr, x7, #0
+ 17c: d36000ff ubfiz xzr, x7, #32, #1
+ 180: d3603cff ubfiz xzr, x7, #32, #16
+ 184: d3607cff lsl xzr, x7, #32
+ 188: d34100ff lsl xzr, x7, #63
+ 18c: 530000ff ubfx wzr, w7, #0, #1
+ 190: 53003cff uxth wzr, w7
+ 194: 53007cff lsr wzr, w7, #0
+ 198: 531040ff ubfx wzr, w7, #16, #1
+ 19c: 53105cff ubfx wzr, w7, #16, #8
+ 1a0: 53107cff lsr wzr, w7, #16
+ 1a4: 531f7cff lsr wzr, w7, #31
+ 1a8: d34000ff ubfx xzr, x7, #0, #1
+ 1ac: d3407cff ubfx xzr, x7, #0, #32
+ 1b0: d340fcff lsr xzr, x7, #0
+ 1b4: d36080ff ubfx xzr, x7, #32, #1
+ 1b8: d360bcff ubfx xzr, x7, #32, #16
+ 1bc: d360fcff lsr xzr, x7, #32
+ 1c0: d37ffcff lsr xzr, x7, #63
--- /dev/null
+#source: bitfield-alias.s
+#objdump: -dr -Mno-aliases
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 13001cff sbfm wzr, w7, #0, #7
+ 4: 93401cff sbfm xzr, x7, #0, #7
+ 8: 13003cff sbfm wzr, w7, #0, #15
+ c: 93403cff sbfm xzr, x7, #0, #15
+ 10: 93407cff sbfm xzr, x7, #0, #31
+ 14: 53001cff ubfm wzr, w7, #0, #7
+ 18: 53001cff ubfm wzr, w7, #0, #7
+ 1c: 53003cff ubfm wzr, w7, #0, #15
+ 20: 53003cff ubfm wzr, w7, #0, #15
+ 24: 2a0703ff orr wzr, wzr, w7
+ 28: 2a0703ff orr wzr, wzr, w7
+ 2c: 13007cff sbfm wzr, w7, #0, #31
+ 30: 13107cff sbfm wzr, w7, #16, #31
+ 34: 131f7cff sbfm wzr, w7, #31, #31
+ 38: 9340fcff sbfm xzr, x7, #0, #63
+ 3c: 935ffcff sbfm xzr, x7, #31, #63
+ 40: 937ffcff sbfm xzr, x7, #63, #63
+ 44: 53007cff ubfm wzr, w7, #0, #31
+ 48: 53107cff ubfm wzr, w7, #16, #31
+ 4c: 531f7cff ubfm wzr, w7, #31, #31
+ 50: d340fcff ubfm xzr, x7, #0, #63
+ 54: d35ffcff ubfm xzr, x7, #31, #63
+ 58: d37ffcff ubfm xzr, x7, #63, #63
+ 5c: 53007cff ubfm wzr, w7, #0, #31
+ 60: 53103cff ubfm wzr, w7, #16, #15
+ 64: 530100ff ubfm wzr, w7, #1, #0
+ 68: d340fcff ubfm xzr, x7, #0, #63
+ 6c: d36180ff ubfm xzr, x7, #33, #32
+ 70: d34100ff ubfm xzr, x7, #1, #0
+ 74: 130000ff sbfm wzr, w7, #0, #0
+ 78: 13003cff sbfm wzr, w7, #0, #15
+ 7c: 13007cff sbfm wzr, w7, #0, #31
+ 80: 131000ff sbfm wzr, w7, #16, #0
+ 84: 13101cff sbfm wzr, w7, #16, #7
+ 88: 13103cff sbfm wzr, w7, #16, #15
+ 8c: 130100ff sbfm wzr, w7, #1, #0
+ 90: 934000ff sbfm xzr, x7, #0, #0
+ 94: 93407cff sbfm xzr, x7, #0, #31
+ 98: 9340fcff sbfm xzr, x7, #0, #63
+ 9c: 936000ff sbfm xzr, x7, #32, #0
+ a0: 93603cff sbfm xzr, x7, #32, #15
+ a4: 93607cff sbfm xzr, x7, #32, #31
+ a8: 934100ff sbfm xzr, x7, #1, #0
+ ac: 130000ff sbfm wzr, w7, #0, #0
+ b0: 13003cff sbfm wzr, w7, #0, #15
+ b4: 13007cff sbfm wzr, w7, #0, #31
+ b8: 131040ff sbfm wzr, w7, #16, #16
+ bc: 13105cff sbfm wzr, w7, #16, #23
+ c0: 13107cff sbfm wzr, w7, #16, #31
+ c4: 131f7cff sbfm wzr, w7, #31, #31
+ c8: 934000ff sbfm xzr, x7, #0, #0
+ cc: 93407cff sbfm xzr, x7, #0, #31
+ d0: 9340fcff sbfm xzr, x7, #0, #63
+ d4: 936080ff sbfm xzr, x7, #32, #32
+ d8: 9360bcff sbfm xzr, x7, #32, #47
+ dc: 9360fcff sbfm xzr, x7, #32, #63
+ e0: 937ffcff sbfm xzr, x7, #63, #63
+ e4: 330000ff bfm wzr, w7, #0, #0
+ e8: 33003cff bfm wzr, w7, #0, #15
+ ec: 33007cff bfm wzr, w7, #0, #31
+ f0: 331000ff bfm wzr, w7, #16, #0
+ f4: 33101cff bfm wzr, w7, #16, #7
+ f8: 33103cff bfm wzr, w7, #16, #15
+ fc: 330100ff bfm wzr, w7, #1, #0
+ 100: b34000ff bfm xzr, x7, #0, #0
+ 104: b3407cff bfm xzr, x7, #0, #31
+ 108: b340fcff bfm xzr, x7, #0, #63
+ 10c: b36000ff bfm xzr, x7, #32, #0
+ 110: b3603cff bfm xzr, x7, #32, #15
+ 114: b3607cff bfm xzr, x7, #32, #31
+ 118: b34100ff bfm xzr, x7, #1, #0
+ 11c: 330000ff bfm wzr, w7, #0, #0
+ 120: 33003cff bfm wzr, w7, #0, #15
+ 124: 33007cff bfm wzr, w7, #0, #31
+ 128: 331040ff bfm wzr, w7, #16, #16
+ 12c: 33105cff bfm wzr, w7, #16, #23
+ 130: 33107cff bfm wzr, w7, #16, #31
+ 134: 331f7cff bfm wzr, w7, #31, #31
+ 138: b34000ff bfm xzr, x7, #0, #0
+ 13c: b3407cff bfm xzr, x7, #0, #31
+ 140: b340fcff bfm xzr, x7, #0, #63
+ 144: b36080ff bfm xzr, x7, #32, #32
+ 148: b360bcff bfm xzr, x7, #32, #47
+ 14c: b360fcff bfm xzr, x7, #32, #63
+ 150: b37ffcff bfm xzr, x7, #63, #63
+ 154: 530000ff ubfm wzr, w7, #0, #0
+ 158: 53003cff ubfm wzr, w7, #0, #15
+ 15c: 53007cff ubfm wzr, w7, #0, #31
+ 160: 531000ff ubfm wzr, w7, #16, #0
+ 164: 53101cff ubfm wzr, w7, #16, #7
+ 168: 53103cff ubfm wzr, w7, #16, #15
+ 16c: 530100ff ubfm wzr, w7, #1, #0
+ 170: d34000ff ubfm xzr, x7, #0, #0
+ 174: d3407cff ubfm xzr, x7, #0, #31
+ 178: d340fcff ubfm xzr, x7, #0, #63
+ 17c: d36000ff ubfm xzr, x7, #32, #0
+ 180: d3603cff ubfm xzr, x7, #32, #15
+ 184: d3607cff ubfm xzr, x7, #32, #31
+ 188: d34100ff ubfm xzr, x7, #1, #0
+ 18c: 530000ff ubfm wzr, w7, #0, #0
+ 190: 53003cff ubfm wzr, w7, #0, #15
+ 194: 53007cff ubfm wzr, w7, #0, #31
+ 198: 531040ff ubfm wzr, w7, #16, #16
+ 19c: 53105cff ubfm wzr, w7, #16, #23
+ 1a0: 53107cff ubfm wzr, w7, #16, #31
+ 1a4: 531f7cff ubfm wzr, w7, #31, #31
+ 1a8: d34000ff ubfm xzr, x7, #0, #0
+ 1ac: d3407cff ubfm xzr, x7, #0, #31
+ 1b0: d340fcff ubfm xzr, x7, #0, #63
+ 1b4: d36080ff ubfm xzr, x7, #32, #32
+ 1b8: d360bcff ubfm xzr, x7, #32, #47
+ 1bc: d360fcff ubfm xzr, x7, #32, #63
+ 1c0: d37ffcff ubfm xzr, x7, #63, #63
--- /dev/null
+#objdump: -dr
+#as: -march=armv8+crypto
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 4e284be7 aese v7.16b, v31.16b
+ 4: 4e285be7 aesd v7.16b, v31.16b
+ 8: 4e286be7 aesmc v7.16b, v31.16b
+ c: 4e287be7 aesimc v7.16b, v31.16b
+ 10: 5e280be7 sha1h s7, s31
+ 14: 5e281be7 sha1su1 v7.4s, v31.4s
+ 18: 5e282be7 sha256su0 v7.4s, v31.4s
+ 1c: 5e1f01e7 sha1c q7, s15, v31.4s
+ 20: 5e1f11e7 sha1p q7, s15, v31.4s
+ 24: 5e1f21e7 sha1m q7, s15, v31.4s
+ 28: 5e1f31e7 sha1su0 v7.4s, v15.4s, v31.4s
+ 2c: 5e1f41e7 sha256h q7, q15, v31.4s
+ 30: 5e1f51e7 sha256h2 q7, q15, v31.4s
+ 34: 5e1f61e7 sha256su1 v7.4s, v15.4s, v31.4s
+ 38: 0e3fe1e7 pmull v7.8h, v15.8b, v31.8b
+ 3c: 0effe1e7 pmull v7.1q, v15.1d, v31.1d
+ 40: 4e3fe1e7 pmull2 v7.8h, v15.16b, v31.16b
+ 44: 4effe1e7 pmull2 v7.1q, v15.2d, v31.2d
--- /dev/null
+/* crypto.s Test file for AArch64 Advanced-SIMD Crypto instructions.
+
+ Copyright 2012 Free Software Foundation, Inc. Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+
+ .text
+ aese v7.16b, v31.16b
+ aesd v7.16b, v31.16b
+ aesmc v7.16b, v31.16b
+ aesimc v7.16b, v31.16b
+
+ sha1h s7, s31
+ sha1su1 v7.4s, v31.4s
+ sha256su0 v7.4s, v31.4s
+
+ sha1c q7, s15, v31.4s
+ sha1p q7, s15, v31.4s
+ sha1m q7, s15, v31.4s
+
+ sha1su0 v7.4s, v15.4s, v31.4s
+ sha256h q7, q15, v31.4s
+ sha256h2 q7, q15, v31.4s
+ sha256su1 v7.4s, v15.4s, v31.4s
+
+ pmull v7.8h, v15.8b, v31.8b
+ pmull v7.1q, v15.1d, v31.1d
+ pmull2 v7.8h, v15.16b, v31.16b
+ pmull2 v7.1q, v15.2d, v31.2d
--- /dev/null
+#name: Diagnostics Quality
+#source: diagnostic.s
+#error-output: diagnostic.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:4: Error: unexpected comma after the mnemonic name `fmul' -- `fmul, s0,s1,s2'
+[^:]*:5: Error: unexpected comma after the mnemonic name `fmul' -- `fmul ,s0,s1,s2'
+[^:]*:6: Error: unexpected comma after the mnemonic name `fmul' -- `fmul ,s0,s1,s2'
+[^:]*:7: Error: unknown mnemonic `b\.random' -- `b\.random label1'
+[^:]*:8: Error: unknown mnemonic `fmull' -- `fmull s0'
+[^:]*:9: Error: unknown mnemonic `aaaaaaaaaaaaaaaaaaaaaaaaaaaa\.\.\.' -- `aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa'
+[^:]*:10: Error: unexpected comma before the omitted optional operand at operand 5 -- `sys 1,c1,c3,3,'
+[^:]*:11: Error: immediate value out of range 0 to 7 at operand 4 -- `ext v0.8b,v1.8b,v2.8b,8'
+[^:]*:12: Error: immediate value out of range 0 to 15 at operand 4 -- `ext v0.16b,v1.16b,v2.16b,20'
+[^:]*:13: Error: immediate value out of range 0 to 65535 at operand 1 -- `svc -1'
+[^:]*:14: Error: immediate value out of range 0 to 65535 at operand 1 -- `svc 65536'
+[^:]*:15: Error: immediate value out of range 0 to 31 at operand 2 -- `ccmp w0,32,10,le'
+[^:]*:16: Error: immediate value out of range 0 to 31 at operand 2 -- `ccmp x0,-1,10,le'
+[^:]*:17: Error: extraneous register at operand 2 -- `tlbi alle3is,x0'
+[^:]*:18: Error: missing register at operand 2 -- `tlbi vaale1is'
+[^:]*:19: Error: unexpected characters following instruction at operand 1 -- `tlbi vaale1is x0'
+[^:]*:20: Error: immediate value out of range 0 to 1 at operand 1 -- `msr spsel,3'
+[^:]*:21: Error: immediate value out of range 1 to 64 at operand 3 -- `fcvtzu x15,d31,#66'
+[^:]*:22: Error: immediate value out of range 1 to 32 at operand 3 -- `scvtf s0,w0,33'
+[^:]*:23: Error: immediate value out of range 1 to 32 at operand 3 -- `scvtf s0,w0,0'
+[^:]*:24: Error: register number out of range 0 to 15 at operand 3 -- `smlal v0.4s,v31.4h,v16.h\[1\]'
+[^:]*:25: Error: register element index out of range 0 to 7 at operand 3 -- `smlal v0.4s,v31.4h,v15.h\[8\]'
+[^:]*:26: Error: extend operator expected at operand 3 -- `add sp,x0,x7,lsr#2'
+[^:]*:27: Error: shift amount out of range 0 to 4 at operand 3 -- `add x0,x0,x7,uxtx#5'
+[^:]*:28: Error: 'ROR' operator not allowed at operand 3 -- `add x0,xzr,x7,ror#5'
+[^:]*:29: Error: shift amount out of range 0 to 31 at operand 3 -- `add w0,wzr,w7,asr#32'
+[^:]*:30: Error: invalid post-increment amount at operand 2 -- `st2 \{v0.4s,v1.4s\},\[sp\],#24'
+[^:]*:31: Error: invalid shift amount at operand 2 -- `ldr q0,\[x0,w0,uxtw#5\]'
+[^:]*:32: Error: invalid number of registers in the list; 2 registers are expected at operand 1 -- `st2 \{v0.4s,v1.4s,v2.4s,v3.4s\},\[sp\],#64'
+[^:]*:33: Error: shift amount expected to be 0 or 12 at operand 3 -- `adds x1,sp,2134,lsl#4'
+[^:]*:34: Error: shift amount should be a multiple of 16 at operand 2 -- `movz w0,2134,lsl#8'
+[^:]*:35: Error: shift amount out of range 0 to 16 at operand 2 -- `movz w0,2134,lsl#32'
+[^:]*:36: Error: shift amount should be a multiple of 16 at operand 2 -- `movz x0,2134,lsl#47'
+[^:]*:37: Error: immediate value out of range 1 to 17 at operand 4 -- `sbfiz w0,w7,15,18'
+[^:]*:38: Error: immediate value out of range 1 to 32 at operand 4 -- `sbfiz w0,w7,15,0'
+[^:]*:39: Error: invalid shift amount at operand 3 -- `shll v1.4s,v2.4h,#15'
+[^:]*:40: Error: invalid shift amount at operand 3 -- `shll v1.4s,v2.4h,#32'
+[^:]*:41: Error: immediate value out of range 0 to 31 at operand 3 -- `shl v1.2s,v2.2s,32'
+[^:]*:42: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrn2 v2.16b,v3.8h,#17'
+[^:]*:43: Error: immediate value out of range 0 to 255 at operand 2 -- `movi v1.4h,256'
+[^:]*:44: Error: immediate value out of range 0 to 255 at operand 2 -- `movi v1.4h,-1'
+[^:]*:45: Error: invalid shift operator at operand 2 -- `movi v1.4h,255,msl#8'
+[^:]*:46: Error: invalid value for immediate at operand 2 -- `movi d0,256'
+[^:]*:47: Error: immediate value should be a multiple of 8 at operand 2 -- `movi v1.4h,255,lsl#7'
+[^:]*:48: Error: immediate value out of range 0 to 8 at operand 2 -- `movi v1.4h,255,lsl#16'
+[^:]*:49: Error: shift amount expected to be 0 or 16 at operand 2 -- `movi v2.2s,255,msl#0'
+[^:]*:50: Error: shift amount expected to be 0 or 16 at operand 2 -- `movi v2.2s,255,msl#15'
+[^:]*:51: Error: invalid floating-point constant at operand 2 -- `fmov v1.2s,1.01'
+[^:]*:52: Error: invalid floating-point constant at operand 2 -- `fmov v1.2d,1.01'
+[^:]*:53: Error: invalid floating-point constant at operand 2 -- `fmov s3,1.01'
+[^:]*:54: Error: invalid floating-point constant at operand 2 -- `fmov d3,1.01'
+[^:]*:55: Error: immediate zero expected at operand 2 -- `fcmp d0,#1.0'
+[^:]*:56: Error: operand 2 should be a floating-point register -- `fcmp d0,x0'
+[^:]*:57: Error: immediate zero expected at operand 3 -- `cmgt v0.4s,v2.4s,#1'
+[^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl#3'
+[^:]*:59: Error: writeback value should be an immediate constant at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp'
+[^:]*:60: Error: writeback value should be an immediate constant at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],zr'
+[^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr#4\]'
+[^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw#12'
+[^:]*:63: Error: shift amount out of range 0 to 63 at operand 2 -- `movz x0,2134,lsl#64'
+[^:]*:64: Error: operand 1 should be an integer register -- `adds sp,sp,2134,lsl#12'
+[^:]*:65: Error: the optional immediate offset can only be 0 at operand 2 -- `ldxrb w2,\[x0,#1\]'
+[^:]*:66: Error: invalid addressing mode at operand 2 -- `ldrb w0,x1,x2,sxtx'
+[^:]*:67: Error: invalid shift amount at operand 2 -- `prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
+[^:]*:68: Error: C0 - C15 expected at operand 3 -- `sysl x7,#1,C16,C30,#1'
+[^:]*:69: Error: operand 4 should be a 4-bit opcode field named for historical reasons C0 - C15 -- `sysl x7,#1,C15,C77,#1'
+[^:]*:70: Error: extending shift is not permitted at operand 3 -- `add x0,xzr,x7,uxtx#5'
+[^:]*:71: Error: bad expression at operand 2 -- `mov x0,##5'
+[^:]*:72: Error: unknown mnemonic `bad' -- `bad expression'
+[^:]*:73: Error: unknown mnemonic `mockup' -- `mockup-op'
+[^:]*:74: Error: comma expected between operands at operand 2 -- `orr x0. x0,#0xff,lsl#1'
+[^:]*:75: Error: the specified relocation type is not allowed for MOVK at operand 2 -- `movk x1,#:abs_g1_s:s12'
+[^:]*:76: Error: can't mix relocation modifier with explicit shift at operand 2 -- `movz x1,#:abs_g1_s:s12,lsl#16'
+[^:]*:77: Error: register offset not allowed in pre-indexed addressing mode at operand 2 -- `prfm pldl3strm,\[sp,w0,sxtw#3\]!'
+[^:]*:78: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm 0x2f,LABEL1'
+[^:]*:79: Error: immediate value out of range 0 to 15 at operand 1 -- `dmb #16'
+[^:]*:80: Error: immediate value out of range 0 to 31 at operand 2 -- `tbz w0,#40,0x17c'
+[^:]*:81: Error: invalid number of registers in the list; 2 registers are expected at operand 1 -- `st2 \{v4.2d,v5.2d,v6.2d\},\[x3\]'
+[^:]*:82: Error: invalid register list at operand 1 -- `ld2 \{v1.4h,v0.4h\},\[x1\]'
+[^:]*:83: Error: the specified option is not accepted in ISB at operand 1 -- `isb osh'
+[^:]*:84: Error: invalid address at operand 2 -- `st2 \{v4.2d,v5.2d,v6.2d\},\\\[x3\\\]'
+[^:]*:85: Error: immediate value should be a multiple of 4 at operand 3 -- `ldnp w7,w15,\[x3,#3\]'
+[^:]*:86: Error: unexpected address writeback at operand 3 -- `stnp x7,x15,\[x3,#32\]!'
+[^:]*:87: Error: immediate offset out of range -256 to 252 at operand 3 -- `ldnp w7,w15,\[x3,#256\]'
+[^:]*:88: Error: shift is not permitted at operand 2 -- `movi v1.2d,4294967295,lsl#0'
+[^:]*:89: Error: shift amount non-zero at operand 2 -- `movi v1.8b,97,lsl#8'
--- /dev/null
+// diagnostic.s Test file for diagnostic quality.
+
+.text
+ fmul, s0, s1, s2
+ fmul , s0, s1, s2
+ fmul , s0, s1, s2
+ b.random label1
+ fmull s0
+ aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ sys 1,c1,c3,3,
+ ext v0.8b, v1.8b, v2.8b, 8
+ ext v0.16b, v1.16b, v2.16b, 20
+ svc -1
+ svc 65536
+ ccmp w0, 32, 10, le
+ ccmp x0, -1, 10, le
+ tlbi alle3is, x0
+ tlbi vaale1is
+ tlbi vaale1is x0
+ msr spsel, 3
+ fcvtzu x15, d31, #66
+ scvtf s0, w0, 33
+ scvtf s0, w0, 0
+ smlal v0.4s, v31.4h, v16.h[1]
+ smlal v0.4s, v31.4h, v15.h[8]
+ add sp, x0, x7, lsr #2
+ add x0, x0, x7, uxtx #5
+ add x0, xzr, x7, ror #5
+ add w0, wzr, w7, asr #32
+ st2 {v0.4s, v1.4s}, [sp], #24
+ ldr q0, [x0, w0, uxtw #5]
+ st2 {v0.4s, v1.4s, v2.4s, v3.4s}, [sp], #64
+ adds x1, sp, 2134, lsl #4
+ movz w0, 2134, lsl #8
+ movz w0, 2134, lsl #32
+ movz x0, 2134, lsl #47
+ sbfiz w0, w7, 15, 18
+ sbfiz w0, w7, 15, 0
+ shll v1.4s, v2.4h, #15
+ shll v1.4s, v2.4h, #32
+ shl v1.2s, v2.2s, 32
+ sqshrn2 v2.16b, v3.8h, #17
+ movi v1.4h, 256
+ movi v1.4h, -1
+ movi v1.4h, 255, msl #8
+ movi d0, 256
+ movi v1.4h, 255, lsl #7
+ movi v1.4h, 255, lsl #16
+ movi v2.2s, 255, msl #0
+ movi v2.2s, 255, msl #15
+ fmov v1.2s, 1.01
+ fmov v1.2d, 1.01
+ fmov s3, 1.01
+ fmov d3, 1.01
+ fcmp d0, #1.0
+ fcmp d0, x0
+ cmgt v0.4s, v2.4s, #1
+ fmov d3, 1.00, lsl #3
+ st2 {v0.4s, v1.4s}, [sp], sp
+ st2 {v0.4s, v1.4s}, [sp], zr
+ ldr q0, [x0, w0, lsr #4]
+ adds x1, sp, 2134, uxtw #12
+ movz x0, 2134, lsl #64
+ adds sp, sp, 2134, lsl #12
+ ldxrb w2, [x0, #1]
+ ldrb w0, x1, x2, sxtx
+ prfm PLDL3KEEP, [x9, x15, sxtx #2]
+ sysl x7, #1, C16, C30, #1
+ sysl x7, #1, C15, C77, #1
+ add x0, xzr, x7, uxtx #5
+ mov x0, ##5
+ bad expression
+ mockup-op
+ orr x0. x0, #0xff, lsl #1
+ movk x1, #:abs_g1_s:s12
+ movz x1, #:abs_g1_s:s12, lsl #16
+ prfm pldl3strm, [sp, w0, sxtw #3]!
+ prfm 0x2f, LABEL1
+ dmb #16
+ tbz w0, #40, 0x17c
+ st2 {v4.2d, v5.2d, v6.2d}, [x3]
+ ld2 {v1.4h, v0.4h}, [x1]
+ isb osh
+ st2 {v4.2d, v5.2d, v6.2d}, \[x3\]
+ ldnp w7, w15, [x3, #3]
+ stnp x7, x15, [x3, #32]!
+ ldnp w7, w15, [x3, #256]
+ movi v1.2d, 4294967295, lsl #0
+ movi v1.8b, 97, lsl #8
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 1e2f08e0 fmul s0, s7, s15
+ 4: 1e2f18e0 fdiv s0, s7, s15
+ 8: 1e2f28e0 fadd s0, s7, s15
+ c: 1e2f38e0 fsub s0, s7, s15
+ 10: 1e2f48e0 fmax s0, s7, s15
+ 14: 1e2f58e0 fmin s0, s7, s15
+ 18: 1e2f68e0 fmaxnm s0, s7, s15
+ 1c: 1e2f78e0 fminnm s0, s7, s15
+ 20: 1e2f88e0 fnmul s0, s7, s15
+ 24: 1e6f08e0 fmul d0, d7, d15
+ 28: 1e6f18e0 fdiv d0, d7, d15
+ 2c: 1e6f28e0 fadd d0, d7, d15
+ 30: 1e6f38e0 fsub d0, d7, d15
+ 34: 1e6f48e0 fmax d0, d7, d15
+ 38: 1e6f58e0 fmin d0, d7, d15
+ 3c: 1e6f68e0 fmaxnm d0, d7, d15
+ 40: 1e6f78e0 fminnm d0, d7, d15
+ 44: 1e6f88e0 fnmul d0, d7, d15
--- /dev/null
+/* floatdp2.s Test file for AArch64 Floating-point data-processing
+ (2 source) instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro floatdp2 op, type
+ \op \type\()0, \type\()7, \type\()15
+ .endm
+
+.text
+ .irp type, S, D
+ .irp op, FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
+ floatdp2 \op, \type
+ .endr
+ .endr
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 1e2000e7 fcvtns w7, s7
+ 4: 9e2000e7 fcvtns x7, s7
+ 8: 1e2100e7 fcvtnu w7, s7
+ c: 9e2100e7 fcvtnu x7, s7
+ 10: 1e2800e7 fcvtps w7, s7
+ 14: 9e2800e7 fcvtps x7, s7
+ 18: 1e2900e7 fcvtpu w7, s7
+ 1c: 9e2900e7 fcvtpu x7, s7
+ 20: 1e3000e7 fcvtms w7, s7
+ 24: 9e3000e7 fcvtms x7, s7
+ 28: 1e3100e7 fcvtmu w7, s7
+ 2c: 9e3100e7 fcvtmu x7, s7
+ 30: 1e3800e7 fcvtzs w7, s7
+ 34: 9e3800e7 fcvtzs x7, s7
+ 38: 1e3900e7 fcvtzu w7, s7
+ 3c: 9e3900e7 fcvtzu x7, s7
+ 40: 1e2200e7 scvtf s7, w7
+ 44: 9e2200e7 scvtf s7, x7
+ 48: 1e2300e7 ucvtf s7, w7
+ 4c: 9e2300e7 ucvtf s7, x7
+ 50: 1e2400e7 fcvtas w7, s7
+ 54: 9e2400e7 fcvtas x7, s7
+ 58: 1e2500e7 fcvtau w7, s7
+ 5c: 9e2500e7 fcvtau x7, s7
+ 60: 1e2600e7 fmov w7, s7
+ 64: 1e2700e7 fmov s7, w7
+ 68: 1e6000e7 fcvtns w7, d7
+ 6c: 9e6000e7 fcvtns x7, d7
+ 70: 1e6100e7 fcvtnu w7, d7
+ 74: 9e6100e7 fcvtnu x7, d7
+ 78: 1e6800e7 fcvtps w7, d7
+ 7c: 9e6800e7 fcvtps x7, d7
+ 80: 1e6900e7 fcvtpu w7, d7
+ 84: 9e6900e7 fcvtpu x7, d7
+ 88: 1e7000e7 fcvtms w7, d7
+ 8c: 9e7000e7 fcvtms x7, d7
+ 90: 1e7100e7 fcvtmu w7, d7
+ 94: 9e7100e7 fcvtmu x7, d7
+ 98: 1e7800e7 fcvtzs w7, d7
+ 9c: 9e7800e7 fcvtzs x7, d7
+ a0: 1e7900e7 fcvtzu w7, d7
+ a4: 9e7900e7 fcvtzu x7, d7
+ a8: 1e6200e7 scvtf d7, w7
+ ac: 9e6200e7 scvtf d7, x7
+ b0: 1e6300e7 ucvtf d7, w7
+ b4: 9e6300e7 ucvtf d7, x7
+ b8: 1e6400e7 fcvtas w7, d7
+ bc: 9e6400e7 fcvtas x7, d7
+ c0: 1e6500e7 fcvtau w7, d7
+ c4: 9e6500e7 fcvtau x7, d7
+ c8: 1e2600e7 fmov w7, s7
+ cc: 1e2700e7 fmov s7, w7
+ d0: 1e18fce7 fcvtzs w7, s7, #1
+ d4: 9e18fce7 fcvtzs x7, s7, #1
+ d8: 1e19fce7 fcvtzu w7, s7, #1
+ dc: 9e19fce7 fcvtzu x7, s7, #1
+ e0: 1e02fce7 scvtf s7, w7, #1
+ e4: 9e02fce7 scvtf s7, x7, #1
+ e8: 1e03fce7 ucvtf s7, w7, #1
+ ec: 9e03fce7 ucvtf s7, x7, #1
+ f0: 1e58fce7 fcvtzs w7, d7, #1
+ f4: 9e58fce7 fcvtzs x7, d7, #1
+ f8: 1e59fce7 fcvtzu w7, d7, #1
+ fc: 9e59fce7 fcvtzu x7, d7, #1
+ 100: 1e42fce7 scvtf d7, w7, #1
+ 104: 9e42fce7 scvtf d7, x7, #1
+ 108: 1e43fce7 ucvtf d7, w7, #1
+ 10c: 9e43fce7 ucvtf d7, x7, #1
+ 110: 1e18f8e7 fcvtzs w7, s7, #2
+ 114: 9e18f8e7 fcvtzs x7, s7, #2
+ 118: 1e19f8e7 fcvtzu w7, s7, #2
+ 11c: 9e19f8e7 fcvtzu x7, s7, #2
+ 120: 1e02f8e7 scvtf s7, w7, #2
+ 124: 9e02f8e7 scvtf s7, x7, #2
+ 128: 1e03f8e7 ucvtf s7, w7, #2
+ 12c: 9e03f8e7 ucvtf s7, x7, #2
+ 130: 1e58f8e7 fcvtzs w7, d7, #2
+ 134: 9e58f8e7 fcvtzs x7, d7, #2
+ 138: 1e59f8e7 fcvtzu w7, d7, #2
+ 13c: 9e59f8e7 fcvtzu x7, d7, #2
+ 140: 1e42f8e7 scvtf d7, w7, #2
+ 144: 9e42f8e7 scvtf d7, x7, #2
+ 148: 1e43f8e7 ucvtf d7, w7, #2
+ 14c: 9e43f8e7 ucvtf d7, x7, #2
+ 150: 1e18f4e7 fcvtzs w7, s7, #3
+ 154: 9e18f4e7 fcvtzs x7, s7, #3
+ 158: 1e19f4e7 fcvtzu w7, s7, #3
+ 15c: 9e19f4e7 fcvtzu x7, s7, #3
+ 160: 1e02f4e7 scvtf s7, w7, #3
+ 164: 9e02f4e7 scvtf s7, x7, #3
+ 168: 1e03f4e7 ucvtf s7, w7, #3
+ 16c: 9e03f4e7 ucvtf s7, x7, #3
+ 170: 1e58f4e7 fcvtzs w7, d7, #3
+ 174: 9e58f4e7 fcvtzs x7, d7, #3
+ 178: 1e59f4e7 fcvtzu w7, d7, #3
+ 17c: 9e59f4e7 fcvtzu x7, d7, #3
+ 180: 1e42f4e7 scvtf d7, w7, #3
+ 184: 9e42f4e7 scvtf d7, x7, #3
+ 188: 1e43f4e7 ucvtf d7, w7, #3
+ 18c: 9e43f4e7 ucvtf d7, x7, #3
+ 190: 1e18f0e7 fcvtzs w7, s7, #4
+ 194: 9e18f0e7 fcvtzs x7, s7, #4
+ 198: 1e19f0e7 fcvtzu w7, s7, #4
+ 19c: 9e19f0e7 fcvtzu x7, s7, #4
+ 1a0: 1e02f0e7 scvtf s7, w7, #4
+ 1a4: 9e02f0e7 scvtf s7, x7, #4
+ 1a8: 1e03f0e7 ucvtf s7, w7, #4
+ 1ac: 9e03f0e7 ucvtf s7, x7, #4
+ 1b0: 1e58f0e7 fcvtzs w7, d7, #4
+ 1b4: 9e58f0e7 fcvtzs x7, d7, #4
+ 1b8: 1e59f0e7 fcvtzu w7, d7, #4
+ 1bc: 9e59f0e7 fcvtzu x7, d7, #4
+ 1c0: 1e42f0e7 scvtf d7, w7, #4
+ 1c4: 9e42f0e7 scvtf d7, x7, #4
+ 1c8: 1e43f0e7 ucvtf d7, w7, #4
+ 1cc: 9e43f0e7 ucvtf d7, x7, #4
+ 1d0: 1e18ece7 fcvtzs w7, s7, #5
+ 1d4: 9e18ece7 fcvtzs x7, s7, #5
+ 1d8: 1e19ece7 fcvtzu w7, s7, #5
+ 1dc: 9e19ece7 fcvtzu x7, s7, #5
+ 1e0: 1e02ece7 scvtf s7, w7, #5
+ 1e4: 9e02ece7 scvtf s7, x7, #5
+ 1e8: 1e03ece7 ucvtf s7, w7, #5
+ 1ec: 9e03ece7 ucvtf s7, x7, #5
+ 1f0: 1e58ece7 fcvtzs w7, d7, #5
+ 1f4: 9e58ece7 fcvtzs x7, d7, #5
+ 1f8: 1e59ece7 fcvtzu w7, d7, #5
+ 1fc: 9e59ece7 fcvtzu x7, d7, #5
+ 200: 1e42ece7 scvtf d7, w7, #5
+ 204: 9e42ece7 scvtf d7, x7, #5
+ 208: 1e43ece7 ucvtf d7, w7, #5
+ 20c: 9e43ece7 ucvtf d7, x7, #5
+ 210: 1e18e8e7 fcvtzs w7, s7, #6
+ 214: 9e18e8e7 fcvtzs x7, s7, #6
+ 218: 1e19e8e7 fcvtzu w7, s7, #6
+ 21c: 9e19e8e7 fcvtzu x7, s7, #6
+ 220: 1e02e8e7 scvtf s7, w7, #6
+ 224: 9e02e8e7 scvtf s7, x7, #6
+ 228: 1e03e8e7 ucvtf s7, w7, #6
+ 22c: 9e03e8e7 ucvtf s7, x7, #6
+ 230: 1e58e8e7 fcvtzs w7, d7, #6
+ 234: 9e58e8e7 fcvtzs x7, d7, #6
+ 238: 1e59e8e7 fcvtzu w7, d7, #6
+ 23c: 9e59e8e7 fcvtzu x7, d7, #6
+ 240: 1e42e8e7 scvtf d7, w7, #6
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+ 790: 1e1890e7 fcvtzs w7, s7, #28
+ 794: 9e1890e7 fcvtzs x7, s7, #28
+ 798: 1e1990e7 fcvtzu w7, s7, #28
+ 79c: 9e1990e7 fcvtzu x7, s7, #28
+ 7a0: 1e0290e7 scvtf s7, w7, #28
+ 7a4: 9e0290e7 scvtf s7, x7, #28
+ 7a8: 1e0390e7 ucvtf s7, w7, #28
+ 7ac: 9e0390e7 ucvtf s7, x7, #28
+ 7b0: 1e5890e7 fcvtzs w7, d7, #28
+ 7b4: 9e5890e7 fcvtzs x7, d7, #28
+ 7b8: 1e5990e7 fcvtzu w7, d7, #28
+ 7bc: 9e5990e7 fcvtzu x7, d7, #28
+ 7c0: 1e4290e7 scvtf d7, w7, #28
+ 7c4: 9e4290e7 scvtf d7, x7, #28
+ 7c8: 1e4390e7 ucvtf d7, w7, #28
+ 7cc: 9e4390e7 ucvtf d7, x7, #28
+ 7d0: 1e188ce7 fcvtzs w7, s7, #29
+ 7d4: 9e188ce7 fcvtzs x7, s7, #29
+ 7d8: 1e198ce7 fcvtzu w7, s7, #29
+ 7dc: 9e198ce7 fcvtzu x7, s7, #29
+ 7e0: 1e028ce7 scvtf s7, w7, #29
+ 7e4: 9e028ce7 scvtf s7, x7, #29
+ 7e8: 1e038ce7 ucvtf s7, w7, #29
+ 7ec: 9e038ce7 ucvtf s7, x7, #29
+ 7f0: 1e588ce7 fcvtzs w7, d7, #29
+ 7f4: 9e588ce7 fcvtzs x7, d7, #29
+ 7f8: 1e598ce7 fcvtzu w7, d7, #29
+ 7fc: 9e598ce7 fcvtzu x7, d7, #29
+ 800: 1e428ce7 scvtf d7, w7, #29
+ 804: 9e428ce7 scvtf d7, x7, #29
+ 808: 1e438ce7 ucvtf d7, w7, #29
+ 80c: 9e438ce7 ucvtf d7, x7, #29
+ 810: 1e1888e7 fcvtzs w7, s7, #30
+ 814: 9e1888e7 fcvtzs x7, s7, #30
+ 818: 1e1988e7 fcvtzu w7, s7, #30
+ 81c: 9e1988e7 fcvtzu x7, s7, #30
+ 820: 1e0288e7 scvtf s7, w7, #30
+ 824: 9e0288e7 scvtf s7, x7, #30
+ 828: 1e0388e7 ucvtf s7, w7, #30
+ 82c: 9e0388e7 ucvtf s7, x7, #30
+ 830: 1e5888e7 fcvtzs w7, d7, #30
+ 834: 9e5888e7 fcvtzs x7, d7, #30
+ 838: 1e5988e7 fcvtzu w7, d7, #30
+ 83c: 9e5988e7 fcvtzu x7, d7, #30
+ 840: 1e4288e7 scvtf d7, w7, #30
+ 844: 9e4288e7 scvtf d7, x7, #30
+ 848: 1e4388e7 ucvtf d7, w7, #30
+ 84c: 9e4388e7 ucvtf d7, x7, #30
+ 850: 1e1884e7 fcvtzs w7, s7, #31
+ 854: 9e1884e7 fcvtzs x7, s7, #31
+ 858: 1e1984e7 fcvtzu w7, s7, #31
+ 85c: 9e1984e7 fcvtzu x7, s7, #31
+ 860: 1e0284e7 scvtf s7, w7, #31
+ 864: 9e0284e7 scvtf s7, x7, #31
+ 868: 1e0384e7 ucvtf s7, w7, #31
+ 86c: 9e0384e7 ucvtf s7, x7, #31
+ 870: 1e5884e7 fcvtzs w7, d7, #31
+ 874: 9e5884e7 fcvtzs x7, d7, #31
+ 878: 1e5984e7 fcvtzu w7, d7, #31
+ 87c: 9e5984e7 fcvtzu x7, d7, #31
+ 880: 1e4284e7 scvtf d7, w7, #31
+ 884: 9e4284e7 scvtf d7, x7, #31
+ 888: 1e4384e7 ucvtf d7, w7, #31
+ 88c: 9e4384e7 ucvtf d7, x7, #31
+ 890: 1e1880e7 fcvtzs w7, s7, #32
+ 894: 9e1880e7 fcvtzs x7, s7, #32
+ 898: 1e1980e7 fcvtzu w7, s7, #32
+ 89c: 9e1980e7 fcvtzu x7, s7, #32
+ 8a0: 1e0280e7 scvtf s7, w7, #32
+ 8a4: 9e0280e7 scvtf s7, x7, #32
+ 8a8: 1e0380e7 ucvtf s7, w7, #32
+ 8ac: 9e0380e7 ucvtf s7, x7, #32
+ 8b0: 1e5880e7 fcvtzs w7, d7, #32
+ 8b4: 9e5880e7 fcvtzs x7, d7, #32
+ 8b8: 1e5980e7 fcvtzu w7, d7, #32
+ 8bc: 9e5980e7 fcvtzu x7, d7, #32
+ 8c0: 1e4280e7 scvtf d7, w7, #32
+ 8c4: 9e4280e7 scvtf d7, x7, #32
+ 8c8: 1e4380e7 ucvtf d7, w7, #32
+ 8cc: 9e4380e7 ucvtf d7, x7, #32
+ 8d0: 9e187ce7 fcvtzs x7, s7, #33
+ 8d4: 9e197ce7 fcvtzu x7, s7, #33
+ 8d8: 9e027ce7 scvtf s7, x7, #33
+ 8dc: 9e037ce7 ucvtf s7, x7, #33
+ 8e0: 9e587ce7 fcvtzs x7, d7, #33
+ 8e4: 9e597ce7 fcvtzu x7, d7, #33
+ 8e8: 9e427ce7 scvtf d7, x7, #33
+ 8ec: 9e437ce7 ucvtf d7, x7, #33
+ 8f0: 9e1878e7 fcvtzs x7, s7, #34
+ 8f4: 9e1978e7 fcvtzu x7, s7, #34
+ 8f8: 9e0278e7 scvtf s7, x7, #34
+ 8fc: 9e0378e7 ucvtf s7, x7, #34
+ 900: 9e5878e7 fcvtzs x7, d7, #34
+ 904: 9e5978e7 fcvtzu x7, d7, #34
+ 908: 9e4278e7 scvtf d7, x7, #34
+ 90c: 9e4378e7 ucvtf d7, x7, #34
+ 910: 9e1874e7 fcvtzs x7, s7, #35
+ 914: 9e1974e7 fcvtzu x7, s7, #35
+ 918: 9e0274e7 scvtf s7, x7, #35
+ 91c: 9e0374e7 ucvtf s7, x7, #35
+ 920: 9e5874e7 fcvtzs x7, d7, #35
+ 924: 9e5974e7 fcvtzu x7, d7, #35
+ 928: 9e4274e7 scvtf d7, x7, #35
+ 92c: 9e4374e7 ucvtf d7, x7, #35
+ 930: 9e1870e7 fcvtzs x7, s7, #36
+ 934: 9e1970e7 fcvtzu x7, s7, #36
+ 938: 9e0270e7 scvtf s7, x7, #36
+ 93c: 9e0370e7 ucvtf s7, x7, #36
+ 940: 9e5870e7 fcvtzs x7, d7, #36
+ 944: 9e5970e7 fcvtzu x7, d7, #36
+ 948: 9e4270e7 scvtf d7, x7, #36
+ 94c: 9e4370e7 ucvtf d7, x7, #36
+ 950: 9e186ce7 fcvtzs x7, s7, #37
+ 954: 9e196ce7 fcvtzu x7, s7, #37
+ 958: 9e026ce7 scvtf s7, x7, #37
+ 95c: 9e036ce7 ucvtf s7, x7, #37
+ 960: 9e586ce7 fcvtzs x7, d7, #37
+ 964: 9e596ce7 fcvtzu x7, d7, #37
+ 968: 9e426ce7 scvtf d7, x7, #37
+ 96c: 9e436ce7 ucvtf d7, x7, #37
+ 970: 9e1868e7 fcvtzs x7, s7, #38
+ 974: 9e1968e7 fcvtzu x7, s7, #38
+ 978: 9e0268e7 scvtf s7, x7, #38
+ 97c: 9e0368e7 ucvtf s7, x7, #38
+ 980: 9e5868e7 fcvtzs x7, d7, #38
+ 984: 9e5968e7 fcvtzu x7, d7, #38
+ 988: 9e4268e7 scvtf d7, x7, #38
+ 98c: 9e4368e7 ucvtf d7, x7, #38
+ 990: 9e1864e7 fcvtzs x7, s7, #39
+ 994: 9e1964e7 fcvtzu x7, s7, #39
+ 998: 9e0264e7 scvtf s7, x7, #39
+ 99c: 9e0364e7 ucvtf s7, x7, #39
+ 9a0: 9e5864e7 fcvtzs x7, d7, #39
+ 9a4: 9e5964e7 fcvtzu x7, d7, #39
+ 9a8: 9e4264e7 scvtf d7, x7, #39
+ 9ac: 9e4364e7 ucvtf d7, x7, #39
+ 9b0: 9e1860e7 fcvtzs x7, s7, #40
+ 9b4: 9e1960e7 fcvtzu x7, s7, #40
+ 9b8: 9e0260e7 scvtf s7, x7, #40
+ 9bc: 9e0360e7 ucvtf s7, x7, #40
+ 9c0: 9e5860e7 fcvtzs x7, d7, #40
+ 9c4: 9e5960e7 fcvtzu x7, d7, #40
+ 9c8: 9e4260e7 scvtf d7, x7, #40
+ 9cc: 9e4360e7 ucvtf d7, x7, #40
+ 9d0: 9e185ce7 fcvtzs x7, s7, #41
+ 9d4: 9e195ce7 fcvtzu x7, s7, #41
+ 9d8: 9e025ce7 scvtf s7, x7, #41
+ 9dc: 9e035ce7 ucvtf s7, x7, #41
+ 9e0: 9e585ce7 fcvtzs x7, d7, #41
+ 9e4: 9e595ce7 fcvtzu x7, d7, #41
+ 9e8: 9e425ce7 scvtf d7, x7, #41
+ 9ec: 9e435ce7 ucvtf d7, x7, #41
+ 9f0: 9e1858e7 fcvtzs x7, s7, #42
+ 9f4: 9e1958e7 fcvtzu x7, s7, #42
+ 9f8: 9e0258e7 scvtf s7, x7, #42
+ 9fc: 9e0358e7 ucvtf s7, x7, #42
+ a00: 9e5858e7 fcvtzs x7, d7, #42
+ a04: 9e5958e7 fcvtzu x7, d7, #42
+ a08: 9e4258e7 scvtf d7, x7, #42
+ a0c: 9e4358e7 ucvtf d7, x7, #42
+ a10: 9e1854e7 fcvtzs x7, s7, #43
+ a14: 9e1954e7 fcvtzu x7, s7, #43
+ a18: 9e0254e7 scvtf s7, x7, #43
+ a1c: 9e0354e7 ucvtf s7, x7, #43
+ a20: 9e5854e7 fcvtzs x7, d7, #43
+ a24: 9e5954e7 fcvtzu x7, d7, #43
+ a28: 9e4254e7 scvtf d7, x7, #43
+ a2c: 9e4354e7 ucvtf d7, x7, #43
+ a30: 9e1850e7 fcvtzs x7, s7, #44
+ a34: 9e1950e7 fcvtzu x7, s7, #44
+ a38: 9e0250e7 scvtf s7, x7, #44
+ a3c: 9e0350e7 ucvtf s7, x7, #44
+ a40: 9e5850e7 fcvtzs x7, d7, #44
+ a44: 9e5950e7 fcvtzu x7, d7, #44
+ a48: 9e4250e7 scvtf d7, x7, #44
+ a4c: 9e4350e7 ucvtf d7, x7, #44
+ a50: 9e184ce7 fcvtzs x7, s7, #45
+ a54: 9e194ce7 fcvtzu x7, s7, #45
+ a58: 9e024ce7 scvtf s7, x7, #45
+ a5c: 9e034ce7 ucvtf s7, x7, #45
+ a60: 9e584ce7 fcvtzs x7, d7, #45
+ a64: 9e594ce7 fcvtzu x7, d7, #45
+ a68: 9e424ce7 scvtf d7, x7, #45
+ a6c: 9e434ce7 ucvtf d7, x7, #45
+ a70: 9e1848e7 fcvtzs x7, s7, #46
+ a74: 9e1948e7 fcvtzu x7, s7, #46
+ a78: 9e0248e7 scvtf s7, x7, #46
+ a7c: 9e0348e7 ucvtf s7, x7, #46
+ a80: 9e5848e7 fcvtzs x7, d7, #46
+ a84: 9e5948e7 fcvtzu x7, d7, #46
+ a88: 9e4248e7 scvtf d7, x7, #46
+ a8c: 9e4348e7 ucvtf d7, x7, #46
+ a90: 9e1844e7 fcvtzs x7, s7, #47
+ a94: 9e1944e7 fcvtzu x7, s7, #47
+ a98: 9e0244e7 scvtf s7, x7, #47
+ a9c: 9e0344e7 ucvtf s7, x7, #47
+ aa0: 9e5844e7 fcvtzs x7, d7, #47
+ aa4: 9e5944e7 fcvtzu x7, d7, #47
+ aa8: 9e4244e7 scvtf d7, x7, #47
+ aac: 9e4344e7 ucvtf d7, x7, #47
+ ab0: 9e1840e7 fcvtzs x7, s7, #48
+ ab4: 9e1940e7 fcvtzu x7, s7, #48
+ ab8: 9e0240e7 scvtf s7, x7, #48
+ abc: 9e0340e7 ucvtf s7, x7, #48
+ ac0: 9e5840e7 fcvtzs x7, d7, #48
+ ac4: 9e5940e7 fcvtzu x7, d7, #48
+ ac8: 9e4240e7 scvtf d7, x7, #48
+ acc: 9e4340e7 ucvtf d7, x7, #48
+ ad0: 9e183ce7 fcvtzs x7, s7, #49
+ ad4: 9e193ce7 fcvtzu x7, s7, #49
+ ad8: 9e023ce7 scvtf s7, x7, #49
+ adc: 9e033ce7 ucvtf s7, x7, #49
+ ae0: 9e583ce7 fcvtzs x7, d7, #49
+ ae4: 9e593ce7 fcvtzu x7, d7, #49
+ ae8: 9e423ce7 scvtf d7, x7, #49
+ aec: 9e433ce7 ucvtf d7, x7, #49
+ af0: 9e1838e7 fcvtzs x7, s7, #50
+ af4: 9e1938e7 fcvtzu x7, s7, #50
+ af8: 9e0238e7 scvtf s7, x7, #50
+ afc: 9e0338e7 ucvtf s7, x7, #50
+ b00: 9e5838e7 fcvtzs x7, d7, #50
+ b04: 9e5938e7 fcvtzu x7, d7, #50
+ b08: 9e4238e7 scvtf d7, x7, #50
+ b0c: 9e4338e7 ucvtf d7, x7, #50
+ b10: 9e1834e7 fcvtzs x7, s7, #51
+ b14: 9e1934e7 fcvtzu x7, s7, #51
+ b18: 9e0234e7 scvtf s7, x7, #51
+ b1c: 9e0334e7 ucvtf s7, x7, #51
+ b20: 9e5834e7 fcvtzs x7, d7, #51
+ b24: 9e5934e7 fcvtzu x7, d7, #51
+ b28: 9e4234e7 scvtf d7, x7, #51
+ b2c: 9e4334e7 ucvtf d7, x7, #51
+ b30: 9e1830e7 fcvtzs x7, s7, #52
+ b34: 9e1930e7 fcvtzu x7, s7, #52
+ b38: 9e0230e7 scvtf s7, x7, #52
+ b3c: 9e0330e7 ucvtf s7, x7, #52
+ b40: 9e5830e7 fcvtzs x7, d7, #52
+ b44: 9e5930e7 fcvtzu x7, d7, #52
+ b48: 9e4230e7 scvtf d7, x7, #52
+ b4c: 9e4330e7 ucvtf d7, x7, #52
+ b50: 9e182ce7 fcvtzs x7, s7, #53
+ b54: 9e192ce7 fcvtzu x7, s7, #53
+ b58: 9e022ce7 scvtf s7, x7, #53
+ b5c: 9e032ce7 ucvtf s7, x7, #53
+ b60: 9e582ce7 fcvtzs x7, d7, #53
+ b64: 9e592ce7 fcvtzu x7, d7, #53
+ b68: 9e422ce7 scvtf d7, x7, #53
+ b6c: 9e432ce7 ucvtf d7, x7, #53
+ b70: 9e1828e7 fcvtzs x7, s7, #54
+ b74: 9e1928e7 fcvtzu x7, s7, #54
+ b78: 9e0228e7 scvtf s7, x7, #54
+ b7c: 9e0328e7 ucvtf s7, x7, #54
+ b80: 9e5828e7 fcvtzs x7, d7, #54
+ b84: 9e5928e7 fcvtzu x7, d7, #54
+ b88: 9e4228e7 scvtf d7, x7, #54
+ b8c: 9e4328e7 ucvtf d7, x7, #54
+ b90: 9e1824e7 fcvtzs x7, s7, #55
+ b94: 9e1924e7 fcvtzu x7, s7, #55
+ b98: 9e0224e7 scvtf s7, x7, #55
+ b9c: 9e0324e7 ucvtf s7, x7, #55
+ ba0: 9e5824e7 fcvtzs x7, d7, #55
+ ba4: 9e5924e7 fcvtzu x7, d7, #55
+ ba8: 9e4224e7 scvtf d7, x7, #55
+ bac: 9e4324e7 ucvtf d7, x7, #55
+ bb0: 9e1820e7 fcvtzs x7, s7, #56
+ bb4: 9e1920e7 fcvtzu x7, s7, #56
+ bb8: 9e0220e7 scvtf s7, x7, #56
+ bbc: 9e0320e7 ucvtf s7, x7, #56
+ bc0: 9e5820e7 fcvtzs x7, d7, #56
+ bc4: 9e5920e7 fcvtzu x7, d7, #56
+ bc8: 9e4220e7 scvtf d7, x7, #56
+ bcc: 9e4320e7 ucvtf d7, x7, #56
+ bd0: 9e181ce7 fcvtzs x7, s7, #57
+ bd4: 9e191ce7 fcvtzu x7, s7, #57
+ bd8: 9e021ce7 scvtf s7, x7, #57
+ bdc: 9e031ce7 ucvtf s7, x7, #57
+ be0: 9e581ce7 fcvtzs x7, d7, #57
+ be4: 9e591ce7 fcvtzu x7, d7, #57
+ be8: 9e421ce7 scvtf d7, x7, #57
+ bec: 9e431ce7 ucvtf d7, x7, #57
+ bf0: 9e1818e7 fcvtzs x7, s7, #58
+ bf4: 9e1918e7 fcvtzu x7, s7, #58
+ bf8: 9e0218e7 scvtf s7, x7, #58
+ bfc: 9e0318e7 ucvtf s7, x7, #58
+ c00: 9e5818e7 fcvtzs x7, d7, #58
+ c04: 9e5918e7 fcvtzu x7, d7, #58
+ c08: 9e4218e7 scvtf d7, x7, #58
+ c0c: 9e4318e7 ucvtf d7, x7, #58
+ c10: 9e1814e7 fcvtzs x7, s7, #59
+ c14: 9e1914e7 fcvtzu x7, s7, #59
+ c18: 9e0214e7 scvtf s7, x7, #59
+ c1c: 9e0314e7 ucvtf s7, x7, #59
+ c20: 9e5814e7 fcvtzs x7, d7, #59
+ c24: 9e5914e7 fcvtzu x7, d7, #59
+ c28: 9e4214e7 scvtf d7, x7, #59
+ c2c: 9e4314e7 ucvtf d7, x7, #59
+ c30: 9e1810e7 fcvtzs x7, s7, #60
+ c34: 9e1910e7 fcvtzu x7, s7, #60
+ c38: 9e0210e7 scvtf s7, x7, #60
+ c3c: 9e0310e7 ucvtf s7, x7, #60
+ c40: 9e5810e7 fcvtzs x7, d7, #60
+ c44: 9e5910e7 fcvtzu x7, d7, #60
+ c48: 9e4210e7 scvtf d7, x7, #60
+ c4c: 9e4310e7 ucvtf d7, x7, #60
+ c50: 9e180ce7 fcvtzs x7, s7, #61
+ c54: 9e190ce7 fcvtzu x7, s7, #61
+ c58: 9e020ce7 scvtf s7, x7, #61
+ c5c: 9e030ce7 ucvtf s7, x7, #61
+ c60: 9e580ce7 fcvtzs x7, d7, #61
+ c64: 9e590ce7 fcvtzu x7, d7, #61
+ c68: 9e420ce7 scvtf d7, x7, #61
+ c6c: 9e430ce7 ucvtf d7, x7, #61
+ c70: 9e1808e7 fcvtzs x7, s7, #62
+ c74: 9e1908e7 fcvtzu x7, s7, #62
+ c78: 9e0208e7 scvtf s7, x7, #62
+ c7c: 9e0308e7 ucvtf s7, x7, #62
+ c80: 9e5808e7 fcvtzs x7, d7, #62
+ c84: 9e5908e7 fcvtzu x7, d7, #62
+ c88: 9e4208e7 scvtf d7, x7, #62
+ c8c: 9e4308e7 ucvtf d7, x7, #62
+ c90: 9e1804e7 fcvtzs x7, s7, #63
+ c94: 9e1904e7 fcvtzu x7, s7, #63
+ c98: 9e0204e7 scvtf s7, x7, #63
+ c9c: 9e0304e7 ucvtf s7, x7, #63
+ ca0: 9e5804e7 fcvtzs x7, d7, #63
+ ca4: 9e5904e7 fcvtzu x7, d7, #63
+ ca8: 9e4204e7 scvtf d7, x7, #63
+ cac: 9e4304e7 ucvtf d7, x7, #63
+ cb0: 9e1800e7 fcvtzs x7, s7, #64
+ cb4: 9e1900e7 fcvtzu x7, s7, #64
+ cb8: 9e0200e7 scvtf s7, x7, #64
+ cbc: 9e0300e7 ucvtf s7, x7, #64
+ cc0: 9e5800e7 fcvtzs x7, d7, #64
+ cc4: 9e5900e7 fcvtzu x7, d7, #64
+ cc8: 9e4200e7 scvtf d7, x7, #64
+ ccc: 9e4300e7 ucvtf d7, x7, #64
+ cd0: 9eae00e7 fmov x7, v7.d\[1\]
+ cd4: 9eaf00e7 fmov v7.d\[1\], x7
--- /dev/null
+/* fp_cvt_ins.s Test file for AArch64 floating-point<->fixed-point
+ conversion and floating-point<->integer conversion instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ // SCVTF & UCVTF
+ .macro do_cvtf fbits, reg
+ .ifc \fbits, 0
+ // Floating-point<->integer conversions
+ SCVTF \reg\()7, W7
+ SCVTF \reg\()7, X7
+ UCVTF \reg\()7, W7
+ UCVTF \reg\()7, X7
+ .else
+ // Floating-point<->fixed-point conversions
+ .ifle \fbits-32
+ SCVTF \reg\()7, W7, #\fbits
+ .endif
+ SCVTF \reg\()7, X7, #\fbits
+ .ifle \fbits-32
+ UCVTF \reg\()7, W7, #\fbits
+ .endif
+ UCVTF \reg\()7, X7, #\fbits
+ .endif
+ .endm
+
+ // FMOV
+ .macro do_fmov type
+ .ifc \type, S
+ // 32-bit
+ FMOV W7, S7
+ FMOV S7, W7
+ .elseif \type == D
+ // 64-bit
+ FMOV X7, D7
+ FMOV D7, X7
+ .else
+ // 64-bit with V reg element
+ FMOV X7, V7.D[1]
+ FMOV V7.D[1], X7
+ .endif
+ .endm
+
+ .macro do_fcvt suffix, fbits, reg
+ .ifc \fbits, 0
+ // Floating-point<->integer conversions
+ FCVT\suffix W7, \reg\()7
+ FCVT\suffix X7, \reg\()7
+ .else
+ // Floating-point<->fixed-point conversions
+ .ifle \fbits-32
+ FCVT\suffix W7, \reg\()7, #\fbits
+ .endif
+ FCVT\suffix X7, \reg\()7, #\fbits
+ .endif
+ .endm
+
+ .macro fcvts_with_fbits fbits
+ .ifc \fbits, 0
+ // fp <-> integer
+ .irp reg, S, D
+ // single-precision and double precision
+ do_fcvt NS, \fbits, \reg
+ do_fcvt NU, \fbits, \reg
+ do_fcvt PS, \fbits, \reg
+ do_fcvt PU, \fbits, \reg
+ do_fcvt MS, \fbits, \reg
+ do_fcvt MU, \fbits, \reg
+ do_fcvt ZS, \fbits, \reg
+ do_fcvt ZU, \fbits, \reg
+ do_cvtf \fbits, \reg
+ do_fcvt AS, \fbits, \reg
+ do_fcvt AU, \fbits, \reg
+ do_fmov S
+ .endr
+ .else
+ // fp <-> fixed-point
+ // After ISA 2.06, only FCVTZ[US] and [US]CVTF are available
+ .irp reg, S, D
+ // single-precision and double precision
+ do_fcvt ZS, \fbits, \reg
+ do_fcvt ZU, \fbits, \reg
+ do_cvtf \fbits, \reg
+ .endr
+ .endif
+ .endm
+
+ .macro fcvts_with_fbits_wrapper from=0, to=64
+ fcvts_with_fbits \from
+ .if \to-\from
+ fcvts_with_fbits_wrapper "(\from+1)", \to
+ .endif
+ .endm
+
+func:
+ // Generate fcvt instructions without fbits and
+ // with fbits from 1 to 64, also generate [us]cvtf
+ // and fmov.
+ fcvts_with_fbits_wrapper from=0, to=64
+ do_fmov V
--- /dev/null
+#name: Illegal Instructions - 2
+#as:
+#source: illegal-2.s
+#error-output: illegal-2.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:10: Error: .*$
+[^:]*:13: Error: .*$
+[^:]*:14: Error: .*$
+[^:]*:15: Error: .*$
+[^:]*:16: Error: .*$
+[^:]*:19: Error: .*$
+[^:]*:20: Error: .*$
--- /dev/null
+// illegal-2.s Test file for AArch64 instructions that should be rejected
+// by the assembler. This test is a complement to the illegal.s test.
+// md_apply_fix will not run if there is any error occurred in an earlier
+// stage, which means errors should be reported by md_apply_fix will not
+// be issued. This test hosts instructions that will only incur error
+// report from md_apply_fix.
+
+
+.text
+ mov x0, #deliberately_undefined_symbol
+
+ // immediate out of range
+ add wsp, w0, #0xfff0, LSL #12
+ add wsp, w0, #0xfff0, LSL #0
+ add wsp, w0, u16, LSL #12
+ add wsp, w0, u16, LSL #0
+
+ // immediate cannot be moved by a single instruction
+ mov wzr, #0x0f0f0f0f
+ mov wsp, #0x33030000
+
+.set u16, 0xfff0
--- /dev/null
+#name: Illegal Instructions
+#as:
+#source: illegal.s
+#error-output: illegal.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:24: Error: .*`urecpe v0.1d,v7.1d'
+[^:]*:25: Error: .*`urecpe v0.2d,v7.2d'
+[^:]*:26: Error: .*`ursqrte v0.1d,v7.1d'
+[^:]*:27: Error: .*`ursqrte v0.2d,v7.2d'
+[^:]*:30: Error: .*`saddlv b7,v31.8b'
+[^:]*:31: Error: .*`saddlv d7,v31.2s'
+[^:]*:32: Error: .*`saddlv q7,v31.2d'
+[^:]*:33: Error: .*`smaxv s7,v31.2s'
+[^:]*:34: Error: .*`sminv d7,v31.2d'
+[^:]*:35: Error: .*`fmaxv h7,v31.8h'
+[^:]*:36: Error: .*`fmaxv h7,v31.4h'
+[^:]*:37: Error: .*`fminv d7,v31.2d'
+[^:]*:39: Error: .*`abs b0,b31'
+[^:]*:40: Error: .*`neg b0,b31'
+[^:]*:41: Error: .*`abs h0,h31'
+[^:]*:42: Error: .*`neg h0,h31'
+[^:]*:43: Error: .*`abs s0,s31'
+[^:]*:44: Error: .*`neg s0,s31'
+[^:]*:46: Error: .*`fcvt s0,s0'
+[^:]*:48: Error: .*`bfm w0,w1,8,43'
+[^:]*:49: Error: .*`ubfm w0,x1,8,31'
+[^:]*:51: Error: .*`aese v1.8b,v2.8b'
+[^:]*:52: Error: .*`sha1h s7,d31'
+[^:]*:53: Error: .*`sha1h q7,d31'
+[^:]*:54: Error: .*`sha1su1 v7.4s,v7.2s'
+[^:]*:55: Error: .*`sha256su0 v7.2d,v7.2d'
+[^:]*:56: Error: .*`sha1c q7,q3,v7.4s'
+[^:]*:57: Error: .*`sha1p s7,q8,v9.4s'
+[^:]*:58: Error: .*`sha1m v8.4s,v7.4s,q8'
+[^:]*:59: Error: .*`sha1su0 v0.2d,v1.2d,v2.2d'
+[^:]*:60: Error: .*`sha256h q7,s2,v8.4s'
+[^:]*:62: Error: .*`pmull v7.8b,v15.8b,v31.8b'
+[^:]*:63: Error: .*`pmull v7.1q,v15.1q,v31.1d'
+[^:]*:64: Error: .*`pmull2 v7.8h,v15.8b,v31.8b'
+[^:]*:65: Error: .*`pmull2 v7.1q,v15.2d,v31.1q'
+[^:]*:67: Error: .*`ld2 {v1.4h,v0.4h},\[x1\]'
+[^:]*:68: Error: .*`strb x0,\[sp,x1,lsl#0\]'
+[^:]*:69: Error: .*`strb w7,\[x30,x0,lsl\]'
+[^:]*:70: Error: .*`strb w7,\[x30,x0,lsl#1\]'
+[^:]*:71: Error: .*`ldtr x7,\[x15,266\]'
+[^:]*:72: Error: .*`sttr x7,\[x15,#1\]!'
+[^:]*:73: Error: .*`stxrb x2,w1,\[sp\]'
+[^:]*:74: Error: .*`stxp w2,x3,w4,\[x0\]'
+[^:]*:75: Error: .*`ldxp w3,x4,\[x30\]'
+[^:]*:77: Error: .*`st2 {v4.2d,v5.2d},\[x3,#3\]'
+[^:]*:78: Error: .*`st2 {v4.2d,v5.2d,v6.2d},\[x3\]'
+[^:]*:79: Error: .*`st1 {v4.2d,v6.2d,v8.2d},\[x3\]'
+[^:]*:80: Error: .*`st3 {v4.2d,v6.2d},\[x3\]'
+[^:]*:81: Error: .*`st4 {v4.2d,v6.2d},\[x3\]'
+[^:]*:82: Error: .*`st2 {v4.2d,v6.2d,v8.2d,v10.2d},\[x3\]'
+[^:]*:83: Error: .*`st2 {v4.2d,v6.2d,v8.2d,v10.2d},\[x3\],48'
+[^:]*:85: Error: .*`ext v0.8b,v1.8b,v2.8b,8'
+[^:]*:86: Error: .*`ext v0.16b,v1.16b,v2.16b,20'
+[^:]*:88: Error: .*`tbz w0,#40,0x17c'
+[^:]*:90: Error: .*`svc'
+[^:]*:92: Error: .*`fmov v1.D\[0\],x0'
+[^:]*:93: Error: .*`fmov v2.S\[2\],x0'
+[^:]*:94: Error: .*`fmov v2.S\[1\],x0'
+[^:]*:95: Error: .*`fmov v2.D\[1\],w0'
+[^:]*:97: Error: .*`smaddl w0,w1,w2,x3'
+[^:]*:98: Error: .*`smaddl x0,x1,w2,x3'
+[^:]*:99: Error: .*`smaddl x0,w1,x2,x3'
+[^:]*:100: Error: .*`smaddl x0,w1,w2,w3'
+[^:]*:102: Error: .*`ld1 {v1.s,v2.s}\[1\],\[x3\]'
+[^:]*:103: Error: .*`st1 {v2.s,v3.s}\[1\],\[x4\]'
+[^:]*:104: Error: .*`ld2 {v1.s,v2.s,v3.s}\[1\],\[x3\]'
+[^:]*:105: Error: .*`st2 {v2.s,v2.s,v3.s}\[1\],\[x4\]'
+[^:]*:106: Error: .*`ld3 {v1.s,v2.s,v3.s,v4.s}\[1\],\[x3\]'
+[^:]*:107: Error: .*`st3 {v2.s,v3.s,v4.s,v5.s}\[1\],\[x4\]'
+[^:]*:108: Error: .*`ld4 {v1.s}\[1\],\[x3\]'
+[^:]*:109: Error: .*`st4 {v2.s}\[1\],\[x4\]'
+[^:]*:111: Error: .*`ld2 {v1.b,v3.b}\[1\],\[x3\]'
+[^:]*:112: Error: .*`st2 {v2.b,v4.b}\[1\],\[x4\]'
+[^:]*:113: Error: .*`ld3 {v1.b,v3.b,v5.b}\[1\],\[x3\]'
+[^:]*:114: Error: .*`st3 {v2.b,v4.b,v6.b}\[1\],\[x4\]'
+[^:]*:115: Error: .*`ld4 {v1.b,v3.b,v5.b,v7.b}\[1\],\[x3\]'
+[^:]*:116: Error: .*`st4 {v2.b,v4.b,v6.b,v8.b}\[1\],\[x4\]'
+[^:]*:118: Error: .*`ld1 {v1.q}\[1\],\[x3\]'
+[^:]*:120: Error: .*`ld1r {v1.4s,v3.4s},\[x3\]'
+[^:]*:121: Error: .*`ld1r {v1.4s,v2.4s,v3.4s},\[x3\]'
+[^:]*:122: Error: .*`ld2r {v1.4s,v2.4s,v3.4s},\[x3\]'
+[^:]*:123: Error: .*`ld3r {v1.4s,v2.4s,v3.4s,v4.4s},\[x3\]'
+[^:]*:124: Error: .*`ld4r {v1.4s},\[x3\]'
+[^:]*:126: Error: .*`ld1r {v1.4s,v3.4s},\[x3\],x4'
+[^:]*:127: Error: .*`ld1r {v1.4s,v2.4s,v3.4s},\[x3\],x4'
+[^:]*:128: Error: .*`ld2r {v1.4s,v2.4s,v3.4s},\[x3\],x4'
+[^:]*:129: Error: .*`ld3r {v1.4s,v2.4s,v3.4s,v4.4s},\[x3\],x4'
+[^:]*:130: Error: .*`ld4r {v1.4s},\[x3\],x4'
+[^:]*:132: Error: .*`ld1r {v1.4s},\[x3\],#1'
+[^:]*:133: Error: .*`ld1r {v1.4s,v2.4s},\[x3\],#8'
+[^:]*:134: Error: .*`ld2r {v1.4s,v2.4s},\[x3\],#4'
+[^:]*:135: Error: .*`ld3r {v1.4s,v2.4s,v3.4s},\[x3\],#16'
+[^:]*:136: Error: .*`ld4r {v1.4s,v2.4s,v3.4s,v4.4s},\[x3\],#32'
+[^:]*:138: Error: .*`addp s1,v2.2s'
+[^:]*:139: Error: .*`addp s1,v2.2d'
+[^:]*:140: Error: .*`addp d1,v2.2s'
+[^:]*:141: Error: .*`fmaxp s1,v2.4s'
+[^:]*:143: Error: .*`add s1,s2,s3'
+[^:]*:144: Error: .*`cmhi d1,d2,s3'
+[^:]*:146: Error: .*`shll v0.8h,v1.8b,16'
+[^:]*:147: Error: .*`shll2 v0.2d,v1.4s,16'
+[^:]*:149: Error: .*`dup s1,v2.d\[1\]'
+[^:]*:150: Error: .*`dup s1,v2.s\[4\]'
+[^:]*:151: Error: .*`mov s1,v2.h\[1\]'
+[^:]*:153: Error: .*`clrex #16'
+[^:]*:155: Error: .*`msr daif,w5'
+[^:]*:156: Error: .*`mrs w15,midr_el1'
+[^:]*:157: Error: .*`mrs x0,dummy'
+[^:]*:159: Error: .*`sshr v0.4s,v1.4s,#0'
+[^:]*:160: Error: .*`sshr v0.4s,v1.4s,#33'
+[^:]*:161: Error: .*`sshr v0.4h,v1.4h,#20'
+[^:]*:163: Error: .*`shl v0.4s,v1.4s,#32'
+[^:]*:164: Error: .*`fcvtzs v0.4h,v1.4h,#2'
+[^:]*:165: Error: .*`uqshrn v0.2s,v1.2d,33'
+[^:]*:166: Error: .*`uqrshrn v0.2s,v1.2s,32'
+[^:]*:167: Error: .*`sshll v8.8h,v2.8b,#8'
+[^:]*:169: Error: .*`sysl x7,#10,C15,C7,#11'
+[^:]*:170: Error: .*`sysl w7,#1,C15,C7,#1'
+[^:]*:172: Error: .*`dsb dummy'
+[^:]*:173: Error: .*`dmb #16'
+[^:]*:174: Error: .*`isb osh'
+[^:]*:176: Error: .*`prfm 0x2f,LABEL1'
+[^:]*:177: Error: .*`prfm pldl3strm,\[sp,#8\]!'
+[^:]*:178: Error: .*`prfm pldl3strm,\[sp\],#8'
+[^:]*:179: Error: .*`prfm pldl3strm,\[sp,w0,sxtw#3\]!'
+[^:]*:180: Error: .*`prfm pldl3strm,=0x100'
+[^:]*:182: Error: .*`sttr x0,LABEL1'
+[^:]*:183: Error: .*`sttr x0,\[sp,#16\]!'
+[^:]*:184: Error: .*`sttr x0,\[sp\],#16'
+[^:]*:185: Error: .*`sttr x0,\[sp,x1\]'
+[^:]*:187: Error: .*`ldur x0,LABEL1'
+[^:]*:188: Error: .*`ldur x0,\[sp,#16\]!'
+[^:]*:189: Error: .*`ldur x0,\[sp\],#16'
+[^:]*:190: Error: .*`ldur x0,\[sp,x1\]'
+[^:]*:192: Error: .*`ldr b0,=0x100'
+[^:]*:193: Error: .*`ldr h0,LABEL1'
+[^:]*:195: Error: .*`ic ivau'
+[^:]*:196: Error: .*`ic ivau,w0'
+[^:]*:197: Error: .*`ic ialluis,xzr'
+[^:]*:198: Error: .*`ic ialluis,x0'
+[^:]*:199: Error: .*`sys #0,c0,c0,0,w0'
+[^:]*:200: Error: .*`msr spsel,#16'
+[^:]*:201: Error: .*`msr cptr_el2,#15'
+[^:]*:203: Error: .*`movz x1,#:abs_g2:u48,lsl#16'
+[^:]*:204: Error: .*`movz x1,0xddee,lsl#8'
+[^:]*:205: Error: .*`movz w1,#:abs_g2:u48'
+[^:]*:206: Error: .*`movz w1,#:abs_g3:u48'
+[^:]*:207: Error: .*`movk x1,#:abs_g1_s:s12'
+[^:]*:209: Error: .*`movi v0.4s,#256'
+[^:]*:210: Error: .*`movi v0.2d,#0xabcdef'
+[^:]*:212: Error: .*`bic v0.4s,#255,msl#8'
+[^:]*:213: Error: .*`bic v0.4s,#512'
+[^:]*:214: Error: .*`bic v0.4s,#1,lsl#31'
+[^:]*:217: Error: .*`orr v0.4s,#255,msl#8'
+[^:]*:218: Error: .*`orr v0.4s,#512'
+[^:]*:220: Error: .*`movi v0.4s,#127,lsl#4'
+[^:]*:221: Error: .*`movi v0.4s,#127,msl#24'
+[^:]*:224: Error: .*`mvni v0.4s,#127,lsl#4'
+[^:]*:225: Error: .*`mvni v0.4s,#127,msl#24'
+[^:]*:228: Error: .*`fmov v0.2s,#3.1415926'
+[^:]*:229: Error: .*`fmov v0.4s,#3.1415926'
+[^:]*:230: Error: .*`fmov v0.2d,#3.1415926'
+[^:]*:231: Error: .*`fmov x0,#1.0'
+[^:]*:232: Error: .*`fmov w0,w1'
+[^:]*:234: Error: .*`msr #5,#0'
+[^:]*:235: Error: .*`msr SPSel,#2'
+[^:]*:237: Error: .*`tbl v0.16b,{v1.16b,v3.16b,v5.16b},v2.16b'
+[^:]*:238: Error: .*`tbx v0.8b,{v1.16b,v3.16b,v5.16b,v7.16b},v2.8b'
+[^:]*:264: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],#16'
+[^:]*:264: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
+[^:]*:264: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],x7'
+[^:]*:264: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
+[^:]*:264: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],#16'
+[^:]*:264: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
+[^:]*:264: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],x7'
+[^:]*:264: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
+[^:]*:264: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],#16'
+[^:]*:264: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
+[^:]*:264: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],x7'
+[^:]*:264: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
+[^:]*:264: Error: .*`st2 {v0.8b,v2.8b},\[x0\],#16'
+[^:]*:264: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
+[^:]*:264: Error: .*`st2 {v0.8b,v2.8b},\[x0\],x7'
+[^:]*:264: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
+[^:]*:264: Error: .*`st2 {v0.4h,v2.4h},\[x0\],#16'
+[^:]*:264: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
+[^:]*:264: Error: .*`st2 {v0.4h,v2.4h},\[x0\],x7'
+[^:]*:264: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
+[^:]*:264: Error: .*`st2 {v0.2s,v2.2s},\[x0\],#16'
+[^:]*:264: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
+[^:]*:264: Error: .*`st2 {v0.2s,v2.2s},\[x0\],x7'
+[^:]*:264: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
+[^:]*:270: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],#32'
+[^:]*:270: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
+[^:]*:270: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],x7'
+[^:]*:270: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
+[^:]*:270: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],#32'
+[^:]*:270: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
+[^:]*:270: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],x7'
+[^:]*:270: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
+[^:]*:270: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],#32'
+[^:]*:270: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
+[^:]*:270: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],x7'
+[^:]*:270: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
+[^:]*:270: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],#32'
+[^:]*:270: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
+[^:]*:270: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],x7'
+[^:]*:270: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
+[^:]*:270: Error: .*`st2 {v0.16b,v2.16b},\[x0\],#32'
+[^:]*:270: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
+[^:]*:270: Error: .*`st2 {v0.16b,v2.16b},\[x0\],x7'
+[^:]*:270: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
+[^:]*:270: Error: .*`st2 {v0.8h,v2.8h},\[x0\],#32'
+[^:]*:270: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
+[^:]*:270: Error: .*`st2 {v0.8h,v2.8h},\[x0\],x7'
+[^:]*:270: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
+[^:]*:270: Error: .*`st2 {v0.4s,v2.4s},\[x0\],#32'
+[^:]*:270: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
+[^:]*:270: Error: .*`st2 {v0.4s,v2.4s},\[x0\],x7'
+[^:]*:270: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
+[^:]*:270: Error: .*`st2 {v0.2d,v2.2d},\[x0\],#32'
+[^:]*:270: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
+[^:]*:270: Error: .*`st2 {v0.2d,v2.2d},\[x0\],x7'
+[^:]*:270: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
+[^:]*:290: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
+[^:]*:290: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
+[^:]*:290: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
+[^:]*:290: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
+[^:]*:290: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
+[^:]*:290: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
+[^:]*:290: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
+[^:]*:290: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
+[^:]*:290: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
+[^:]*:290: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
+[^:]*:290: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
+[^:]*:290: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
+[^:]*:290: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
+[^:]*:290: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
+[^:]*:290: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
+[^:]*:290: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
+[^:]*:290: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
+[^:]*:290: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
+[^:]*:290: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
+[^:]*:290: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
+[^:]*:290: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
+[^:]*:290: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
+[^:]*:290: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
+[^:]*:290: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
+[^:]*:296: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
+[^:]*:296: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
+[^:]*:296: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
+[^:]*:296: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
+[^:]*:296: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
+[^:]*:296: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
+[^:]*:296: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
+[^:]*:296: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
+[^:]*:296: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
+[^:]*:296: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
+[^:]*:296: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
+[^:]*:296: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
+[^:]*:296: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
+[^:]*:296: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
+[^:]*:296: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
+[^:]*:296: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
+[^:]*:296: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
+[^:]*:296: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
+[^:]*:296: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
+[^:]*:296: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
+[^:]*:296: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
+[^:]*:296: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
+[^:]*:296: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
+[^:]*:296: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
+[^:]*:296: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
+[^:]*:296: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
+[^:]*:296: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
+[^:]*:296: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
+[^:]*:296: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
+[^:]*:296: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
+[^:]*:296: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
+[^:]*:296: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
+[^:]*:300: Error: .*`ld1r {v0.8b,v1.8b},\[x0\],#1'
+[^:]*:301: Error: .*`ld1r {v0.16b,v1.16b},\[x0\],#1'
+[^:]*:302: Error: .*`ld1r {v0.4h,v1.4h},\[x0\],#2'
+[^:]*:303: Error: .*`ld1r {v0.8h,v1.8h},\[x0\],#2'
+[^:]*:304: Error: .*`ld1r {v0.2s,v1.2s},\[x0\],#4'
+[^:]*:305: Error: .*`ld1r {v0.4s,v1.4s},\[x0\],#4'
+[^:]*:306: Error: .*`ld1r {v0.1d,v1.1d},\[x0\],#8'
+[^:]*:307: Error: .*`ld1r {v0.2d,v1.2d},\[x0\],#8'
+[^:]*:322: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],#4'
+[^:]*:322: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
+[^:]*:322: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
+[^:]*:322: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],#4'
+[^:]*:322: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],#6'
+[^:]*:322: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#8'
+[^:]*:322: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],#4'
+[^:]*:322: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],#6'
+[^:]*:322: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#8'
+[^:]*:322: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],#4'
+[^:]*:322: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
+[^:]*:322: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
+[^:]*:337: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],#8'
+[^:]*:337: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
+[^:]*:337: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
+[^:]*:337: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],#8'
+[^:]*:337: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],#12'
+[^:]*:337: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#16'
+[^:]*:337: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],#8'
+[^:]*:337: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],#12'
+[^:]*:337: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#16'
+[^:]*:337: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],#8'
+[^:]*:337: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
+[^:]*:337: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
+[^:]*:352: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],#16'
+[^:]*:352: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
+[^:]*:352: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
+[^:]*:352: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],#16'
+[^:]*:352: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],#24'
+[^:]*:352: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],#32'
+[^:]*:352: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],#16'
+[^:]*:352: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],#24'
+[^:]*:352: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#32'
+[^:]*:352: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],#16'
+[^:]*:352: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
+[^:]*:352: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
+[^:]*:356: Error: .*`ld1r {v0.8b,v1.8b},\[x0\],x7'
+[^:]*:356: Error: .*`ld1r {v0.16b,v1.16b},\[x0\],x7'
+[^:]*:356: Error: .*`ld1r {v0.4h,v1.4h},\[x0\],x7'
+[^:]*:356: Error: .*`ld1r {v0.8h,v1.8h},\[x0\],x7'
+[^:]*:356: Error: .*`ld1r {v0.2s,v1.2s},\[x0\],x7'
+[^:]*:356: Error: .*`ld1r {v0.4s,v1.4s},\[x0\],x7'
+[^:]*:356: Error: .*`ld1r {v0.1d,v1.1d},\[x0\],x7'
+[^:]*:356: Error: .*`ld1r {v0.2d,v1.2d},\[x0\],x7'
+[^:]*:373: Error: .*`ld2 {v0.b,v2.b}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`ld2r {v0.8b,v2.8b},\[x0\],x7'
+[^:]*:373: Error: .*`ld3r {v0.8b,v2.8b,v4.8b},\[x0\],x7'
+[^:]*:373: Error: .*`ld4r {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
+[^:]*:373: Error: .*`ld2r {v0.16b,v2.16b},\[x0\],x7'
+[^:]*:373: Error: .*`ld3r {v0.16b,v2.16b,v4.16b},\[x0\],x7'
+[^:]*:373: Error: .*`ld4r {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
+[^:]*:373: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],x7'
+[^:]*:373: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],x7'
+[^:]*:373: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
+[^:]*:373: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],x7'
+[^:]*:373: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],x7'
+[^:]*:373: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
+[^:]*:373: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],x7'
+[^:]*:373: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],x7'
+[^:]*:373: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
+[^:]*:373: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],x7'
+[^:]*:373: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],x7'
+[^:]*:373: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
+[^:]*:373: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],x7'
+[^:]*:373: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],x7'
+[^:]*:373: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],x7'
+[^:]*:373: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],x7'
+[^:]*:373: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],x7'
+[^:]*:373: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
+[^:]*:373: Error: .*`st2 {v0.b,v2.b}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
+[^:]*:373: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
+[^:]*:396: Error: .*`ld2 {v0.8B,v2.8B},\[x0\]'
+[^:]*:396: Error: .*`ld3 {v0.8B,v2.8B,v4.8B},\[x0\]'
+[^:]*:396: Error: .*`ld4 {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
+[^:]*:397: Error: .*`st2 {v0.8B,v2.8B},\[x0\]'
+[^:]*:397: Error: .*`st3 {v0.8B,v2.8B,v4.8B},\[x0\]'
+[^:]*:397: Error: .*`st4 {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
+[^:]*:399: Error: .*`ld2 {v0.16B,v2.16B},\[x0\]'
+[^:]*:399: Error: .*`ld3 {v0.16B,v2.16B,v4.16B},\[x0\]'
+[^:]*:399: Error: .*`ld4 {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
+[^:]*:400: Error: .*`st2 {v0.16B,v2.16B},\[x0\]'
+[^:]*:400: Error: .*`st3 {v0.16B,v2.16B,v4.16B},\[x0\]'
+[^:]*:400: Error: .*`st4 {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
+[^:]*:402: Error: .*`ld2 {v0.4H,v2.4H},\[x0\]'
+[^:]*:402: Error: .*`ld3 {v0.4H,v2.4H,v4.4H},\[x0\]'
+[^:]*:402: Error: .*`ld4 {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
+[^:]*:403: Error: .*`st2 {v0.4H,v2.4H},\[x0\]'
+[^:]*:403: Error: .*`st3 {v0.4H,v2.4H,v4.4H},\[x0\]'
+[^:]*:403: Error: .*`st4 {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
+[^:]*:405: Error: .*`ld2 {v0.8H,v2.8H},\[x0\]'
+[^:]*:405: Error: .*`ld3 {v0.8H,v2.8H,v4.8H},\[x0\]'
+[^:]*:405: Error: .*`ld4 {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
+[^:]*:406: Error: .*`st2 {v0.8H,v2.8H},\[x0\]'
+[^:]*:406: Error: .*`st3 {v0.8H,v2.8H,v4.8H},\[x0\]'
+[^:]*:406: Error: .*`st4 {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
+[^:]*:408: Error: .*`ld2 {v0.2S,v2.2S},\[x0\]'
+[^:]*:408: Error: .*`ld3 {v0.2S,v2.2S,v4.2S},\[x0\]'
+[^:]*:408: Error: .*`ld4 {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
+[^:]*:409: Error: .*`st2 {v0.2S,v2.2S},\[x0\]'
+[^:]*:409: Error: .*`st3 {v0.2S,v2.2S,v4.2S},\[x0\]'
+[^:]*:409: Error: .*`st4 {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
+[^:]*:411: Error: .*`ld2 {v0.4S,v2.4S},\[x0\]'
+[^:]*:411: Error: .*`ld3 {v0.4S,v2.4S,v4.4S},\[x0\]'
+[^:]*:411: Error: .*`ld4 {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
+[^:]*:412: Error: .*`st2 {v0.4S,v2.4S},\[x0\]'
+[^:]*:412: Error: .*`st3 {v0.4S,v2.4S,v4.4S},\[x0\]'
+[^:]*:412: Error: .*`st4 {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
+[^:]*:414: Error: .*`ld2 {v0.2D,v2.2D},\[x0\]'
+[^:]*:414: Error: .*`ld3 {v0.2D,v2.2D,v4.2D},\[x0\]'
+[^:]*:414: Error: .*`ld4 {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
+[^:]*:415: Error: .*`st2 {v0.2D,v2.2D},\[x0\]'
+[^:]*:415: Error: .*`st3 {v0.2D,v2.2D,v4.2D},\[x0\]'
+[^:]*:415: Error: .*`st4 {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
+[^:]*:423: Error: .*`ld2 {v0.H,v2.H}\[1\],\[x0\]'
+[^:]*:423: Error: .*`ld3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
+[^:]*:423: Error: .*`ld4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
+[^:]*:424: Error: .*`st2 {v0.H,v2.H}\[1\],\[x0\]'
+[^:]*:424: Error: .*`st3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
+[^:]*:424: Error: .*`st4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
+[^:]*:426: Error: .*`ld2 {v0.H,v2.H}\[1\],\[x0\]'
+[^:]*:426: Error: .*`ld3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
+[^:]*:426: Error: .*`ld4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
+[^:]*:427: Error: .*`st2 {v0.H,v2.H}\[1\],\[x0\]'
+[^:]*:427: Error: .*`st3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
+[^:]*:427: Error: .*`st4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
+[^:]*:429: Error: .*`ld2 {v0.S,v2.S}\[1\],\[x0\]'
+[^:]*:429: Error: .*`ld3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
+[^:]*:429: Error: .*`ld4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
+[^:]*:430: Error: .*`st2 {v0.S,v2.S}\[1\],\[x0\]'
+[^:]*:430: Error: .*`st3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
+[^:]*:430: Error: .*`st4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
+[^:]*:432: Error: .*`ld2 {v0.S,v2.S}\[1\],\[x0\]'
+[^:]*:432: Error: .*`ld3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
+[^:]*:432: Error: .*`ld4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
+[^:]*:433: Error: .*`st2 {v0.S,v2.S}\[1\],\[x0\]'
+[^:]*:433: Error: .*`st3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
+[^:]*:433: Error: .*`st4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
+[^:]*:435: Error: .*`ld2 {v0.D,v2.D}\[1\],\[x0\]'
+[^:]*:435: Error: .*`ld3 {v0.D,v2.D,v4.D}\[1\],\[x0\]'
+[^:]*:435: Error: .*`ld4 {v0.D,v2.D,v4.D,v6.D}\[1\],\[x0\]'
+[^:]*:436: Error: .*`st2 {v0.D,v2.D}\[1\],\[x0\]'
+[^:]*:436: Error: .*`st3 {v0.D,v2.D,v4.D}\[1\],\[x0\]'
+[^:]*:436: Error: .*`st4 {v0.D,v2.D,v4.D,v6.D}\[1\],\[x0\]'
+[^:]*:438: Error: .*`ld1r {v0.8B,v1.8B},\[x0\]'
+[^:]*:438: Error: .*`ld2r {v0.8B,v2.8B},\[x0\]'
+[^:]*:438: Error: .*`ld3r {v0.8B,v2.8B,v4.8B},\[x0\]'
+[^:]*:438: Error: .*`ld4r {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
+[^:]*:440: Error: .*`ld1r {v0.16B,v1.16B},\[x0\]'
+[^:]*:440: Error: .*`ld2r {v0.16B,v2.16B},\[x0\]'
+[^:]*:440: Error: .*`ld3r {v0.16B,v2.16B,v4.16B},\[x0\]'
+[^:]*:440: Error: .*`ld4r {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
+[^:]*:442: Error: .*`ld1r {v0.4H,v1.4H},\[x0\]'
+[^:]*:442: Error: .*`ld2r {v0.4H,v2.4H},\[x0\]'
+[^:]*:442: Error: .*`ld3r {v0.4H,v2.4H,v4.4H},\[x0\]'
+[^:]*:442: Error: .*`ld4r {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
+[^:]*:444: Error: .*`ld1r {v0.8H,v1.8H},\[x0\]'
+[^:]*:444: Error: .*`ld2r {v0.8H,v2.8H},\[x0\]'
+[^:]*:444: Error: .*`ld3r {v0.8H,v2.8H,v4.8H},\[x0\]'
+[^:]*:444: Error: .*`ld4r {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
+[^:]*:446: Error: .*`ld1r {v0.2S,v1.2S},\[x0\]'
+[^:]*:446: Error: .*`ld2r {v0.2S,v2.2S},\[x0\]'
+[^:]*:446: Error: .*`ld3r {v0.2S,v2.2S,v4.2S},\[x0\]'
+[^:]*:446: Error: .*`ld4r {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
+[^:]*:448: Error: .*`ld1r {v0.4S,v1.4S},\[x0\]'
+[^:]*:448: Error: .*`ld2r {v0.4S,v2.4S},\[x0\]'
+[^:]*:448: Error: .*`ld3r {v0.4S,v2.4S,v4.4S},\[x0\]'
+[^:]*:448: Error: .*`ld4r {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
+[^:]*:450: Error: .*`ld1r {v0.1D,v1.1D},\[x0\]'
+[^:]*:450: Error: .*`ld2r {v0.1D,v2.1D},\[x0\]'
+[^:]*:450: Error: .*`ld3r {v0.1D,v2.1D,v4.1D},\[x0\]'
+[^:]*:450: Error: .*`ld4r {v0.1D,v2.1D,v4.1D,v6.1D},\[x0\]'
+[^:]*:452: Error: .*`ld1r {v0.2D,v1.2D},\[x0\]'
+[^:]*:452: Error: .*`ld2r {v0.2D,v2.2D},\[x0\]'
+[^:]*:452: Error: .*`ld3r {v0.2D,v2.2D,v4.2D},\[x0\]'
+[^:]*:452: Error: .*`ld4r {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
+[^:]*:454: Error: .*`pmull v0.1q,v1.1d,v2.1d'
+[^:]*:455: Error: .*`pmull2 v0.1q,v1.2d,v2.2d'
+[^:]*:463: Error: .*`scvtf d0,w1,33'
+[^:]*:463: Error: .*`scvtf s0,w0,33'
+[^:]*:463: Error: .*`scvtf d0,x1,65'
+[^:]*:463: Error: .*`scvtf s0,x1,65'
+[^:]*:463: Error: .*`ucvtf d0,w1,33'
+[^:]*:463: Error: .*`ucvtf s0,w0,33'
+[^:]*:463: Error: .*`ucvtf d0,x1,65'
+[^:]*:463: Error: .*`ucvtf s0,x1,65'
+[^:]*:469: Error: .*`fcvtzs w1,d0,33'
+[^:]*:469: Error: .*`fcvtzs w0,s0,33'
+[^:]*:469: Error: .*`fcvtzs x1,d0,65'
+[^:]*:469: Error: .*`fcvtzs x1,s0,65'
+[^:]*:469: Error: .*`fcvtzu w1,d0,33'
+[^:]*:469: Error: .*`fcvtzu w0,s0,33'
+[^:]*:469: Error: .*`fcvtzu x1,d0,65'
+[^:]*:469: Error: .*`fcvtzu x1,s0,65'
+[^:]*:472: Error: .*
+[^:]*:475: Error: .*`ldrh w0,\[x1,x2,lsr#1\]'
+[^:]*:477: Error: .*`add w0,w1,w2,ror#1'
+[^:]*:478: Error: .*`sub w0,w1,w2,asr#32'
+[^:]*:479: Error: .*`eor w0,w1,w2,ror#32'
+[^:]*:481: Error: .*`add x0,x1,#20,LSL#16'
+[^:]*:482: Error: .*`add x0,x1,#20,UXTX#12'
+[^:]*:483: Error: .*`add x0,x1,#20,LSR'
+[^:]*:484: Error: .*`add x0,x1,#20,LSL'
+[^:]*:486: Error: .*`ldnp h7,h15,\[x0,#2\]'
+[^:]*:487: Error: .*`ldnp b15,b31,\[x0\],#4'
+[^:]*:488: Error: .*`ldnp h0,h1,\[x0,#6\]!'
+[^:]*:490: Error: .*`uqrshrn h0,s1,#63'
+[^:]*:491: Error: .*`sqshl b7,b15,#8'
+[^:]*:493: Error: .*`bfxil w7,w15,#15,#30'
+[^:]*:494: Error: .*`bfi x3,x7,#31,#48'
+[^:]*:496: Error: .*`str x1,page_table_count'
+[^:]*:498: Error: .*`prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
+[^:]*:500: Error: .*`mrs x5,S1_0_C13_C8_0'
+[^:]*:501: Error: .*`msr S3_1_C13_C15_1,x7'
+[^:]*:502: Error: .*`msr S3_1_C11_C15_-1,x7'
+[^:]*:503: Error: .*`msr S3_1_11_15_1,x7'
+[^:]*:506: Error: .*`movi w1,#15'
+[^:]*:509: Error: .*`uxtb x7,x15'
+[^:]*:510: Error: .*`uxth x7,x15'
+[^:]*:511: Error: .*`uxtw x7,x15'
+[^:]*:512: Error: .*`sxtb w15,xzr'
+[^:]*:513: Error: .*`sxth w15,xzr'
+[^:]*:514: Error: .*`sxtw w15,xzr'
+[^:]*:516: Error: .*`mov w0,v0.b\[0\]'
+[^:]*:517: Error: .*`mov w0,v0.h\[0\]'
+[^:]*:518: Error: .*`mov w0,v0.d\[0\]'
+[^:]*:519: Error: .*`mov x0,v0.b\[0\]'
+[^:]*:520: Error: .*`mov x0,v0.h\[0\]'
+[^:]*:521: Error: .*`mov x0,v0.s\[0\]'
+[^:]*:523: Error: .*`uabdl2 v20\.4S,v12\.8H,v29\.8'
+[^:]*:525: Error: .*`movi d1,0xffff,lsl#16'
+[^:]*:527: Error: .*`st3 {v18.D-v20.D}\[0\],\[x28\],x'
+[^:]*:528: Error: .*`st1 {v7.B}\[2\],\[x4\],x'
+[^:]*:529: Error: .*`st1 {v22.1D-v25.1D},\[x10\],x'
+[^:]*:531: Error: .*`ldr w0,\[x0\]!'
+[^:]*:532: Error: .*`ldr w0,\[x0\],\{127\}'
+[^:]*:534: Error: .*`orr x0,x0,#0xff,lsl#1'
+[^:]*:535: Error: .*`orr x0. x0,#0xff,lsl#1'
+[^:]*:536: Error: .*`orr x0,x0,#0xff lsl#1'
+[^:]*:538: Error: .*`mov x0,##5'
--- /dev/null
+/* illegal.s Test file for AArch64 instructions that should be rejected
+ by the assembler.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc. Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+.text
+ // For urecpe and ursqrte, only 2s and 4s are accepted qualifiers.
+ urecpe v0.1d, v7.1d
+ urecpe v0.2d, v7.2d
+ ursqrte v0.1d, v7.1d
+ ursqrte v0.2d, v7.2d
+
+ // For AdvSIMD (across) instructions, there are restraints on the register type and qualifiers.
+ saddlv b7, v31.8b
+ saddlv d7, v31.2s
+ saddlv q7, v31.2d
+ smaxv s7, v31.2s
+ sminv d7, v31.2d
+ fmaxv h7, v31.8h
+ fmaxv h7, v31.4h
+ fminv d7, v31.2d
+
+ abs b0, b31
+ neg b0, b31
+ abs h0, h31
+ neg h0, h31
+ abs s0, s31
+ neg s0, s31
+
+ fcvt s0, s0
+
+ bfm w0, w1, 8, 43
+ ubfm w0, x1, 8, 31
+
+ aese v1.8b, v2.8b
+ sha1h s7, d31
+ sha1h q7, d31
+ sha1su1 v7.4s, v7.2s
+ sha256su0 v7.2d, v7.2d
+ sha1c q7, q3, v7.4s
+ sha1p s7, q8, v9.4s
+ sha1m v8.4s, v7.4s, q8
+ sha1su0 v0.2d, v1.2d, v2.2d
+ sha256h q7, s2, v8.4s
+
+ pmull v7.8b, v15.8b, v31.8b
+ pmull v7.1q, v15.1q, v31.1d
+ pmull2 v7.8h, v15.8b, v31.8b
+ pmull2 v7.1q, v15.2d, v31.1q
+
+ ld2 {v1.4h, v0.4h}, [x1]
+ strb x0, [sp, x1, lsl #0]
+ strb w7, [x30, x0, lsl]
+ strb w7, [x30, x0, lsl #1]
+ ldtr x7, [x15, 266]
+ sttr x7, [x15, #1]!
+ stxrb x2, w1, [sp]
+ stxp w2, x3, w4, [x0]
+ ldxp w3, x4, [x30]
+
+ st2 {v4.2d, v5.2d}, [x3, #3]
+ st2 {v4.2d, v5.2d, v6.2d}, [x3]
+ st1 {v4.2d, v6.2d, v8.2d}, [x3]
+ st3 {v4.2d, v6.2d}, [x3]
+ st4 {v4.2d, v6.2d}, [x3]
+ st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3]
+ st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3], 48
+
+ ext v0.8b, v1.8b, v2.8b, 8
+ ext v0.16b, v1.16b, v2.16b, 20
+
+ tbz w0, #40, 0x17c
+
+ svc
+
+ fmov v1.D[0], x0
+ fmov v2.S[2], x0
+ fmov v2.S[1], x0
+ fmov v2.D[1], w0
+
+ smaddl w0, w1, w2, x3
+ smaddl x0, x1, w2, x3
+ smaddl x0, w1, x2, x3
+ smaddl x0, w1, w2, w3
+
+ ld1 {v1.s, v2.s}[1], [x3]
+ st1 {v2.s, v3.s}[1], [x4]
+ ld2 {v1.s, v2.s, v3.s}[1], [x3]
+ st2 {v2.s, v2.s, v3.s}[1], [x4]
+ ld3 {v1.s, v2.s, v3.s, v4.s}[1], [x3]
+ st3 {v2.s, v3.s, v4.s, v5.s}[1], [x4]
+ ld4 {v1.s}[1], [x3]
+ st4 {v2.s}[1], [x4]
+
+ ld2 {v1.b, v3.b}[1], [x3]
+ st2 {v2.b, v4.b}[1], [x4]
+ ld3 {v1.b, v3.b, v5.b}[1], [x3]
+ st3 {v2.b, v4.b, v6.b}[1], [x4]
+ ld4 {v1.b, v3.b, v5.b, v7.b}[1], [x3]
+ st4 {v2.b, v4.b, v6.b, v8.b}[1], [x4]
+
+ ld1 {v1.q}[1], [x3]
+
+ ld1r {v1.4s, v3.4s}, [x3]
+ ld1r {v1.4s, v2.4s, v3.4s}, [x3]
+ ld2r {v1.4s, v2.4s, v3.4s}, [x3]
+ ld3r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3]
+ ld4r {v1.4s}, [x3]
+
+ ld1r {v1.4s, v3.4s}, [x3], x4
+ ld1r {v1.4s, v2.4s, v3.4s}, [x3], x4
+ ld2r {v1.4s, v2.4s, v3.4s}, [x3], x4
+ ld3r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], x4
+ ld4r {v1.4s}, [x3], x4
+
+ ld1r {v1.4s}, [x3], #1
+ ld1r {v1.4s, v2.4s}, [x3], #8
+ ld2r {v1.4s, v2.4s}, [x3], #4
+ ld3r {v1.4s, v2.4s, v3.4s}, [x3], #16
+ ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], #32
+
+ addp s1, v2.2s
+ addp s1, v2.2d
+ addp d1, v2.2s
+ fmaxp s1, v2.4s
+
+ add s1, s2, s3
+ cmhi d1, d2, s3
+
+ shll v0.8h, v1.8b, 16
+ shll2 v0.2d, v1.4s, 16
+
+ dup s1, v2.d[1]
+ dup s1, v2.s[4]
+ mov s1, v2.h[1]
+
+ clrex #16
+
+ msr daif, w5
+ mrs w15, midr_el1
+ mrs x0, dummy
+
+ sshr v0.4s, v1.4s, #0
+ sshr v0.4s, v1.4s, #33
+ sshr v0.4h, v1.4h, #20
+
+ shl v0.4s, v1.4s, #32
+ fcvtzs v0.4h, v1.4h, #2
+ uqshrn v0.2s, v1.2d, 33
+ uqrshrn v0.2s, v1.2s, 32
+ sshll v8.8h, v2.8b, #8
+
+ sysl x7, #10, C15, C7, #11
+ sysl w7, #1, C15, C7, #1
+
+ dsb dummy
+ dmb #16
+ isb osh
+
+ prfm 0x2f, LABEL1
+ prfm pldl3strm, [sp, #8]!
+ prfm pldl3strm, [sp], #8
+ prfm pldl3strm, [sp, w0, sxtw #3]!
+ prfm pldl3strm, =0x100
+
+ sttr x0, LABEL1
+ sttr x0, [sp, #16]!
+ sttr x0, [sp], #16
+ sttr x0, [sp, x1]
+
+ ldur x0, LABEL1
+ ldur x0, [sp, #16]!
+ ldur x0, [sp], #16
+ ldur x0, [sp, x1]
+
+ ldr b0, =0x100
+ ldr h0, LABEL1
+
+ ic ivau
+ ic ivau, w0
+ ic ialluis, xzr
+ ic ialluis, x0
+ sys #0, c0, c0, 0, w0
+ msr spsel, #16
+ msr cptr_el2, #15
+
+ movz x1,#:abs_g2:u48, lsl #16
+ movz x1, 0xddee, lsl #8
+ movz w1,#:abs_g2:u48
+ movz w1,#:abs_g3:u48
+ movk x1,#:abs_g1_s:s12
+
+ movi v0.4s, #256
+ movi v0.2d, #0xabcdef
+
+ bic v0.4s, #255, msl #8
+ bic v0.4s, #512
+ bic v0.4s, #1, lsl #31
+// bic v0.4h, #1, lsl #16
+
+ orr v0.4s, #255, msl #8
+ orr v0.4s, #512
+
+ movi v0.4s, #127, lsl #4
+ movi v0.4s, #127, msl #24
+// movi v0.4h, #127, lsl #16
+
+ mvni v0.4s, #127, lsl #4
+ mvni v0.4s, #127, msl #24
+// mvni v0.4h, #127, lsl #16
+
+ fmov v0.2s, #3.1415926
+ fmov v0.4s, #3.1415926
+ fmov v0.2d, #3.1415926
+ fmov x0, #1.0
+ fmov w0, w1
+
+ msr #5, #0
+ msr SPSel, #2
+
+ tbl v0.16b, {v1.16b, v3.16b, v5.16b}, v2.16b
+ tbx v0.8b, {v1.16b, v3.16b, v5.16b, v7.16b}, v2.8b
+
+ // Alternating register list forms are no longer available A64 ISA
+
+ .macro ldst2_reg_list_post_imm_reg_64 inst type postreg
+ \inst\()2 {v0.\type, v2.\type}, [x0], #16
+ \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
+ .ifnb \postreg
+ \inst\()2 {v0.\type, v2.\type}, [x0], \postreg
+ \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
+ .endif
+ .endm
+
+ .macro ldst2_reg_list_post_imm_reg_128 inst type postreg
+ \inst\()2 {v0.\type, v2.\type}, [x0], #32
+ \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
+ .ifnb \postreg
+ \inst\()2 {v0.\type, v2.\type}, [x0], \postreg
+ \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
+ .endif
+ .endm
+
+ .irp instr ld,st
+ .irp bits_64 8b, 4h, 2s
+ ldst2_reg_list_post_imm_reg_64 \instr \bits_64 x7
+ .endr
+ .endr
+
+ .irp instr ld,st
+ .irp bits_128 16b, 8h, 4s, 2d
+ ldst2_reg_list_post_imm_reg_128 \instr \bits_128 x7
+ .endr
+ .endr
+
+ .macro ldst34_reg_list_post_imm_reg_64 inst type postreg
+ \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], #24
+ \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #32
+ \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], \postreg
+ \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg
+ .endm
+
+ .macro ldst34_reg_list_post_imm_reg_128 inst type postreg
+ \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], #48
+ \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #64
+ \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], \postreg
+ \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg
+ .endm
+
+ .irp instr ld,st
+ .irp bits_64 8b, 4h, 2s
+ ldst34_reg_list_post_imm_reg_64 \instr \bits_64 x7
+ .endr
+ .endr
+
+ .irp instr ld,st
+ .irp bits_128 16b, 8h, 4s, 2d
+ ldst34_reg_list_post_imm_reg_128 \instr \bits_128 x7
+ .endr
+ .endr
+
+ // LD1R expects one register only.
+
+ ld1r {v0.8b, v1.8b}, [x0], #1
+ ld1r {v0.16b, v1.16b}, [x0], #1
+ ld1r {v0.4h, v1.4h}, [x0], #2
+ ld1r {v0.8h, v1.8h}, [x0], #2
+ ld1r {v0.2s, v1.2s}, [x0], #4
+ ld1r {v0.4s, v1.4s}, [x0], #4
+ ld1r {v0.1d, v1.1d}, [x0], #8
+ ld1r {v0.2d, v1.2d}, [x0], #8
+
+ .macro ldstn_index_rep_H_altreg_imm inst index type rep
+ \inst\()2\rep {v0.\type, v2.\type}\index, [x0], #4
+ \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #6
+ \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #8
+ .endm
+
+ .irp instr, ld, st
+ ldstn_index_rep_H_altreg_imm \instr index="[1]" type=h rep=""
+ .ifnc \instr, st
+ .irp types 4h, 8h
+ ldstn_index_rep_H_altreg_imm \instr index="" type=\types rep="r"
+ .endr
+ .endif
+ .endr
+
+ .macro ldstn_index_rep_S_altreg_imm inst index type rep
+ \inst\()2\rep {v0.\type, v2.\type}\index, [x0], #8
+ \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #12
+ \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #16
+ .endm
+
+ .irp instr, ld, st
+ ldstn_index_rep_S_altreg_imm \instr index="[1]" type=s rep=""
+ .ifnc \instr, st
+ .irp types 2s, 4s
+ ldstn_index_rep_S_altreg_imm \instr index="" type=\types rep="r"
+ .endr
+ .endif
+ .endr
+
+ .macro ldstn_index_rep_D_altreg_imm inst index type rep
+ \inst\()2\rep {v0.\type, v2.\type}\index, [x0], #16
+ \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #24
+ \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #32
+ .endm
+
+ .irp instr, ld, st
+ ldstn_index_rep_D_altreg_imm \instr index="[1]" type=d rep=""
+ .ifnc \instr, st
+ .irp types 1d, 2d
+ ldstn_index_rep_D_altreg_imm \instr index="" type=\types rep="r"
+ .endr
+ .endif
+ .endr
+
+ .irp type 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
+ ld1r {v0.\type, v1.\type}, [x0], x7
+ .endr
+
+ .macro ldstn_index_rep_reg_altreg inst index type rep postreg
+ \inst\()2\rep {v0.\type, v2.\type}\index, [x0], \postreg
+ \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], \postreg
+ \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], \postreg
+ .endm
+
+ .irp instr, ld, st
+ .irp itypes b,h,s,d
+ ldstn_index_rep_reg_altreg \instr index="[1]" type=\itypes rep="" postreg=x7
+ .endr
+ .ifnc \instr, st
+ .irp types 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
+ ldstn_index_rep_reg_altreg \instr index="" type=\types rep="r" postreg=x7
+ .endr
+ .endif
+ .endr
+
+ .macro ldnstn_reg_list type inst index rep
+ .ifb \index
+ .ifnb \rep
+ \inst\()1\rep {v0.\type, v1.\type}\index, [x0]
+ .endif
+ .endif
+
+ .ifnc \type, B
+ \inst\()2\rep {v0.\type, v2.\type}\index, [x0]
+ .endif
+
+ .ifnc \type, B
+ \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0]
+ .endif
+
+ .ifnc \type, B
+ \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0]
+ .endif
+
+ .endm
+
+ ldnstn_reg_list type="8B", inst="ld" index="" rep=""
+ ldnstn_reg_list type="8B", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="16B", inst="ld" index="" rep=""
+ ldnstn_reg_list type="16B", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="4H", inst="ld" index="" rep=""
+ ldnstn_reg_list type="4H", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="8H", inst="ld" index="" rep=""
+ ldnstn_reg_list type="8H", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="2S", inst="ld" index="" rep=""
+ ldnstn_reg_list type="2S", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="4S", inst="ld" index="" rep=""
+ ldnstn_reg_list type="4S", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="2D", inst="ld" index="" rep=""
+ ldnstn_reg_list type="2D", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="B", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="B", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="B", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="B", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="H", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="H", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="H", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="H", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="S", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="S", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="S", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="S", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="D", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="D", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="8B", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="16B", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="4H", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="8H", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="2S", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="4S", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="1D", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="2D", inst="ld" index="" rep="r"
+
+ pmull v0.1q, v1.1d, v2.1d
+ pmull2 v0.1q, v1.2d, v2.2d
+
+ // #<fbits> out of range
+ .irp instr, scvtf, ucvtf
+ \instr d0, w1, 33
+ \instr s0, w0, 33
+ \instr d0, x1, 65
+ \instr s0, x1, 65
+ .endr
+ .irp instr, fcvtzs, fcvtzu
+ \instr w1, d0, 33
+ \instr w0, s0, 33
+ \instr x1, d0, 65
+ \instr x1, s0, 65
+ .endr
+
+ // Invalid instruction.
+ mockup-op
+
+
+ ldrh w0, [x1, x2, lsr #1]
+
+ add w0, w1, w2, ror #1
+ sub w0, w1, w2, asr #32
+ eor w0, w1, w2, ror #32
+
+ add x0, x1, #20, LSL #16
+ add x0, x1, #20, UXTX #12
+ add x0, x1, #20, LSR
+ add x0, x1, #20, LSL
+
+ ldnp h7, h15, [x0, #2]
+ ldnp b15, b31, [x0], #4
+ ldnp h0, h1, [x0, #6]!
+
+ uqrshrn h0, s1, #63
+ sqshl b7, b15, #8
+
+ bfxil w7, w15, #15, #30
+ bfi x3, x7, #31, #48
+
+ str x1,page_table_count
+
+ prfm PLDL3KEEP, [x9, x15, sxtx #2]
+
+ mrs x5, S1_0_C13_C8_0
+ msr S3_1_C13_C15_1, x7
+ msr S3_1_C11_C15_-1, x7
+ msr S3_1_11_15_1, x7
+
+ // MOVI (alias of ORR immediate) is no longer supported.
+ movi w1, #15
+.set u48, 0xaabbccddeeff
+
+ uxtb x7, x15
+ uxth x7, x15
+ uxtw x7, x15
+ sxtb w15, xzr
+ sxth w15, xzr
+ sxtw w15, xzr
+
+ mov w0, v0.b[0]
+ mov w0, v0.h[0]
+ mov w0, v0.d[0]
+ mov x0, v0.b[0]
+ mov x0, v0.h[0]
+ mov x0, v0.s[0]
+
+ uabdl2 v20.4S, v12.8H, v29.8
+
+ movi d1, 0xffff, lsl #16
+
+ ST3 {v18.D-v20.D}[0],[x28],x
+ ST1 {v7.B}[2],[x4],x
+ ST1 {v22.1D-v25.1D},[x10],x
+
+ ldr w0, [x0]!
+ ldr w0, [x0], {127}
+
+ orr x0, x0, #0xff, lsl #1
+ orr x0. x0, #0xff, lsl #1
+ orr x0, x0, #0xff lsl #1
+
+ mov x0, ##5
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 3619194c tbz w12, #3, 2328 <\.text\+0x2328>
--- /dev/null
+// inst-directive.s Test file for AArch64 .inst directive.
+// This test file is also useful in testing the disassembler.
+
+.text
+ .inst 0x3619194c
--- /dev/null
+#objdump: -dr
+#as: -march=armv8
+
+.*: file format .*
+
+Disassembly of section .text:
+
+0000000000000000 <.*>:
+ 0: 9ac32041 lsl x1, x2, x3
+ 4: d340fc41 lsr x1, x2, #0
+ 8: d37ff841 lsl x1, x2, #1
+ c: 93c30441 extr x1, x2, x3, #1
+ 10: 93c3fc41 extr x1, x2, x3, #63
+ 14: 93c30041 extr x1, x2, x3, #0
+ 18: 13837c41 extr w1, w2, w3, #31
+ 1c: 9a9f17e1 cset x1, eq
+ 20: da9f13e1 csetm x1, eq
+ 24: 71000021 subs w1, w1, #0x0
+ 28: 7100003f cmp w1, #0x0
+ 2c: 4b0203e1 neg w1, w2
+ 30: 51000041 sub w1, w2, #0x0
+ 34: f100003f cmp x1, #0x0
+ 38: f1000021 subs x1, x1, #0x0
+ 3c: 32000fe1 orr w1, wzr, #0xf
+ 40: aa0203e1 mov x1, x2
+ 44: 18000061 ldr w1, 50 <sp>
+ 48: 18000621 ldr w1, 10c <sp\+0xbc>
+ 4c: 58000621 ldr x1, 110 <sp\+0xc0>
+
+0000000000000050 <sp>:
+ 50: 12345678 .word 0x12345678
+ 54: d65f03c0 ret
+ 58: d65f03c0 ret
+ 5c: d65f0040 ret x2
+ 60: 8b22603f add sp, x1, x2
+ 64: 91401ca5 add x5, x5, #0x7, lsl #12
+ 68: 8b430441 add x1, x2, x3, lsr #1
+ 6c: 91001ca5 add x5, x5, #0x7
+ 70: 71000421 subs w1, w1, #0x1
+ 74: d2800c82 movz x2, #0x64
+ 78: d2800c82 movz x2, #0x64
+ 7c: d2800c82 movz x2, #0x64
+ 80: d2a00c82 movz x2, #0x64, lsl #16
+ 84: d2a00c82 movz x2, #0x64, lsl #16
+ 88: d2c00c82 movz x2, #0x64, lsl #32
+ 8c: d2c00c82 movz x2, #0x64, lsl #32
+ 90: d2e00c82 movz x2, #0x64, lsl #48
+ 94: d2e00c82 movz x2, #0x64, lsl #48
+ 98: 52800c81 movz w1, #0x64
+ 9c: 52800c81 movz w1, #0x64
+ a0: 52a00c81 movz w1, #0x64, lsl #16
+ a4: 8a030041 and x1, x2, x3
+ a8: 0a0f015e and w30, w10, w15
+ ac: 12000041 and w1, w2, #0x1
+ b0: 8a430441 and x1, x2, x3, lsr #1
+ b4: 32000021 orr w1, w1, #0x1
+ b8: 32000021 orr w1, w1, #0x1
+ bc: b2400021 orr x1, x1, #0x1
+ c0: 92400c41 and x1, x2, #0xf
+ c4: 12000c41 and w1, w2, #0xf
+ c8: 92610041 and x1, x2, #0x80000000
+ cc: 12010041 and w1, w2, #0x80000000
+ d0: 925d0041 and x1, x2, #0x800000000
+ d4: 92400c85 and x5, x4, #0xf
+ d8: 0a230041 bic w1, w2, w3
+ dc: 8a230041 bic x1, x2, x3
+ e0: 54000001 b.ne e0 <sp\+0x90>
+ e4: 17ffffff b e0 <sp\+0x90>
+ e8: 14000001 b ec <sp\+0x9c>
+ ec: 54ffffa0 b.eq e0 <sp\+0x90>
+ f0: 54000001 b.ne f0 <sp\+0xa0>
+ f4: 17ffffff b f0 <sp\+0xa0>
+ f8: 14000001 b fc <sp\+0xac>
+ fc: 54ffffa0 b.eq f0 <sp\+0xa0>
+ 100: d61f0040 br x2
+ 104: 54ffffc2 b.cs fc <sp\+0xac>
+ 108: 54ffffa3 b.cc fc <sp\+0xac>
+ ...
+ 10c: R_AARCH64_ABS32 .text\+0x50
+ 110: R_AARCH64_ABS64 .text\+0x50
--- /dev/null
+// Test file for AArch64 GAS -- basic integer instructions
+
+func:
+ lsl x1, x2, x3
+ lsl x1, x2, #0
+ lsl x1, x2, #1
+
+ extr x1, x2, x3, #1
+ extr x1, x2, x3, #63
+
+ extr x1, x2, x3, #0
+ extr w1, w2, w3, #31
+
+ CSET x1, eq
+ CSETM x1, eq
+
+ subs w1,w1,#0
+ cmp w1,#0
+
+ neg w1,w2
+ sub w1,w2,#0
+
+ cmp x1,#0
+ subs x1,x1,#0
+
+ orr w1,wzr,#15
+ mov x1,x2
+
+ ldr w1, sp
+ ldr w1, =sp
+ ldr x1, =sp
+sp: .word 0x12345678
+
+ ret x30
+ ret
+ ret x2
+
+ add sp,x1,x2
+
+ add x5,x5,#0x7, lsl #12
+
+ add x1,x2,x3, lsr #1
+ add x5,x5,#0x7
+
+ subs w1,w1,#1
+
+ movz x2,#0x64
+ movz x2,#0x64, lsl #0
+ movz x2,#:abs_g0:0x64
+ movz x2,#0x64, lsl #16
+ movz x2,#:abs_g1:(0x64 << 16)
+ movz x2,#0x64, lsl #32
+ movz x2,#:abs_g2:(0x64 << 32)
+ movz x2,#0x64, lsl #48
+ movz x2,#:abs_g3:(0x64 << 48)
+ movz w1,#0x64
+ movz w1,#0x64, lsl #0
+ movz w1,#0x64, lsl #16
+
+ and x1,x2,x3
+ and w30,w10,w15
+ and w1,w2,#1
+
+ and x1,x2,x3, lsr #1
+
+ orr w1,w1,#1
+ orr w1,w1,#1
+ orr x1,x1,#1
+ and x1,x2,#0xf
+ and w1,w2,#0xf
+ and x1,x2,#0x80000000
+ and w1,w2,#0x80000000
+ and x1,x2,#0x800000000
+
+ // 00010010000101000000010100000011
+ // 1 2 1 4 0 5 0 3
+ and x5,x4,#0xf
+
+ bic w1,w2,w3
+ bic x1,x2,x3
+
+1: b.ne 1b
+ b 1b
+ b 2f
+2: b.eq 1b
+
+
+3: bne 3b
+ b 3b
+ b 4f
+4: beq 3b
+
+ br x2
+
+ bcs 4b
+ bcc 4b
+
+ .if 0
+
+ lsl x1, #0, #1
+
+ ext x1, x2, x3, #64
+ ext w1, w2, w3, #63
+ ext w1, w2, w3, #32
+
+ mov w1,#10
+ neg w1,#1
+
+ ldm {x1},[sp]
+ ldm {x1-x2},[sp]
+ ldm {x1,x2,x3,x4},sp
+ ldm {x1-x3},[x1,w2]
+
+ subs #0,#1
+
+ add x5,x5,#0x7, lsl #1
+ add x5,x5,#0x7, lsr #1
+
+ movz x0,#0x64, lsl #1
+ movz x0,#0x64, lsl #2
+ movz x0,#0x64, lsl #3
+ movz x0,#0x64, lsl #4
+ movz x0,#0x64, lsl #64
+ movz w1,#0x64, lsl #32
+ movz w1,#0x64, lsl #48
+
+ orr #0,w1
+ and sp,x1,x2
+ and x1,sp,x2
+ and x1,x2,sp
+
+ and w1,#0,x2
+ and x1,#0,w2
+
+ and x1,x2,w3
+ and x1,w2,x3
+ and x1,w2,w3
+ and w1,x2,x3
+ and w1,x2,w3
+ and w1,w2,x3
+ and w1,w2,w3
+
+ and x1,x2,#0
+ and w1,w2,#0x800000000
+ bic x1,x2,#1
+
+ br w2
+ br sp
+ .endif
+
+ .equ sh,2
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 080f7ce1 stxrb w15, w1, \[x7\]
+ 4: 080f7ce1 stxrb w15, w1, \[x7\]
+ 8: 080f7ce1 stxrb w15, w1, \[x7\]
+ c: 480f7ce1 stxrh w15, w1, \[x7\]
+ 10: 480f7ce1 stxrh w15, w1, \[x7\]
+ 14: 480f7ce1 stxrh w15, w1, \[x7\]
+ 18: 880f7ce1 stxr w15, w1, \[x7\]
+ 1c: 880f7ce1 stxr w15, w1, \[x7\]
+ 20: 880f7ce1 stxr w15, w1, \[x7\]
+ 24: c80f7ce1 stxr w15, x1, \[x7\]
+ 28: c80f7ce1 stxr w15, x1, \[x7\]
+ 2c: c80f7ce1 stxr w15, x1, \[x7\]
+ 30: 085f7ce1 ldxrb w1, \[x7\]
+ 34: 085f7ce1 ldxrb w1, \[x7\]
+ 38: 085f7ce1 ldxrb w1, \[x7\]
+ 3c: 485f7ce1 ldxrh w1, \[x7\]
+ 40: 485f7ce1 ldxrh w1, \[x7\]
+ 44: 485f7ce1 ldxrh w1, \[x7\]
+ 48: 885f7ce1 ldxr w1, \[x7\]
+ 4c: 885f7ce1 ldxr w1, \[x7\]
+ 50: 885f7ce1 ldxr w1, \[x7\]
+ 54: c85f7ce1 ldxr x1, \[x7\]
+ 58: c85f7ce1 ldxr x1, \[x7\]
+ 5c: c85f7ce1 ldxr x1, \[x7\]
+ 60: 882f08e1 stxp w15, w1, w2, \[x7\]
+ 64: 882f08e1 stxp w15, w1, w2, \[x7\]
+ 68: 882f08e1 stxp w15, w1, w2, \[x7\]
+ 6c: c82f08e1 stxp w15, x1, x2, \[x7\]
+ 70: c82f08e1 stxp w15, x1, x2, \[x7\]
+ 74: c82f08e1 stxp w15, x1, x2, \[x7\]
+ 78: 887f08e1 ldxp w1, w2, \[x7\]
+ 7c: 887f08e1 ldxp w1, w2, \[x7\]
+ 80: 887f08e1 ldxp w1, w2, \[x7\]
+ 84: c87f08e1 ldxp x1, x2, \[x7\]
+ 88: c87f08e1 ldxp x1, x2, \[x7\]
+ 8c: c87f08e1 ldxp x1, x2, \[x7\]
+ 90: 080ffce1 stlxrb w15, w1, \[x7\]
+ 94: 080ffce1 stlxrb w15, w1, \[x7\]
+ 98: 080ffce1 stlxrb w15, w1, \[x7\]
+ 9c: 480ffce1 stlxrh w15, w1, \[x7\]
+ a0: 480ffce1 stlxrh w15, w1, \[x7\]
+ a4: 480ffce1 stlxrh w15, w1, \[x7\]
+ a8: 880ffce1 stlxr w15, w1, \[x7\]
+ ac: 880ffce1 stlxr w15, w1, \[x7\]
+ b0: 880ffce1 stlxr w15, w1, \[x7\]
+ b4: c80ffce1 stlxr w15, x1, \[x7\]
+ b8: c80ffce1 stlxr w15, x1, \[x7\]
+ bc: c80ffce1 stlxr w15, x1, \[x7\]
+ c0: 085ffce1 ldaxrb w1, \[x7\]
+ c4: 085ffce1 ldaxrb w1, \[x7\]
+ c8: 085ffce1 ldaxrb w1, \[x7\]
+ cc: 485ffce1 ldaxrh w1, \[x7\]
+ d0: 485ffce1 ldaxrh w1, \[x7\]
+ d4: 485ffce1 ldaxrh w1, \[x7\]
+ d8: 885ffce1 ldaxr w1, \[x7\]
+ dc: 885ffce1 ldaxr w1, \[x7\]
+ e0: 885ffce1 ldaxr w1, \[x7\]
+ e4: c85ffce1 ldaxr x1, \[x7\]
+ e8: c85ffce1 ldaxr x1, \[x7\]
+ ec: c85ffce1 ldaxr x1, \[x7\]
+ f0: 882f88e1 stlxp w15, w1, w2, \[x7\]
+ f4: 882f88e1 stlxp w15, w1, w2, \[x7\]
+ f8: 882f88e1 stlxp w15, w1, w2, \[x7\]
+ fc: c82f88e1 stlxp w15, x1, x2, \[x7\]
+ 100: c82f88e1 stlxp w15, x1, x2, \[x7\]
+ 104: c82f88e1 stlxp w15, x1, x2, \[x7\]
+ 108: 887f88e1 ldaxp w1, w2, \[x7\]
+ 10c: 887f88e1 ldaxp w1, w2, \[x7\]
+ 110: 887f88e1 ldaxp w1, w2, \[x7\]
+ 114: c87f88e1 ldaxp x1, x2, \[x7\]
+ 118: c87f88e1 ldaxp x1, x2, \[x7\]
+ 11c: c87f88e1 ldaxp x1, x2, \[x7\]
+ 120: 089ffce1 stlrb w1, \[x7\]
+ 124: 089ffce1 stlrb w1, \[x7\]
+ 128: 089ffce1 stlrb w1, \[x7\]
+ 12c: 489ffce1 stlrh w1, \[x7\]
+ 130: 489ffce1 stlrh w1, \[x7\]
+ 134: 489ffce1 stlrh w1, \[x7\]
+ 138: 889ffce1 stlr w1, \[x7\]
+ 13c: 889ffce1 stlr w1, \[x7\]
+ 140: 889ffce1 stlr w1, \[x7\]
+ 144: c89ffce1 stlr x1, \[x7\]
+ 148: c89ffce1 stlr x1, \[x7\]
+ 14c: c89ffce1 stlr x1, \[x7\]
+ 150: 08dffce1 ldarb w1, \[x7\]
+ 154: 08dffce1 ldarb w1, \[x7\]
+ 158: 08dffce1 ldarb w1, \[x7\]
+ 15c: 48dffce1 ldarh w1, \[x7\]
+ 160: 48dffce1 ldarh w1, \[x7\]
+ 164: 48dffce1 ldarh w1, \[x7\]
+ 168: 88dffce1 ldar w1, \[x7\]
+ 16c: 88dffce1 ldar w1, \[x7\]
+ 170: 88dffce1 ldar w1, \[x7\]
+ 174: c8dffce1 ldar x1, \[x7\]
+ 178: c8dffce1 ldar x1, \[x7\]
+ 17c: c8dffce1 ldar x1, \[x7\]
--- /dev/null
+/* ldst-exclusive.s Test file for AArch64 load-store exclusive
+ instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+
+ /* <mnemonic> <Wt>, [<Xn|SP>]{,#0}] */
+ .macro LR32 op
+ \op w1, [x7]
+ \op w1, [x7, #0]
+ \op w1, [x7, 0]
+ .endm
+
+ /* <mnemonic> <Xt>, [<Xn|SP>]{,#0}] */
+ .macro LR64 op
+ \op x1, [x7]
+ \op x1, [x7, #0]
+ \op x1, [x7, 0]
+ .endm
+
+ /* <mnemonic> <Ws>, <Wt>, [<Xn|SP>]{,#0}] */
+ .macro SR32 op
+ \op w15, w1, [x7]
+ \op w15, w1, [x7, #0]
+ \op w15, w1, [x7, 0]
+ .endm
+
+ /* <mnemonic> <Ws>, <Xt>, [<Xn|SP>]{,#0}] */
+ .macro SR64 op
+ \op w15, x1, [x7]
+ \op w15, x1, [x7, #0]
+ \op w15, x1, [x7, 0]
+ .endm
+
+ /* <mnemonic> <Wt1>, <Wt2>, [<Xn|SP>]{,#0}] */
+ .macro LP32 op
+ \op w1, w2, [x7]
+ \op w1, w2, [x7, #0]
+ \op w1, w2, [x7, 0]
+ .endm
+
+ /* <mnemonic> <Xt1>, <Xt2>, [<Xn|SP>]{,#0}] */
+ .macro LP64 op
+ \op x1, x2, [x7]
+ \op x1, x2, [x7, #0]
+ \op x1, x2, [x7, 0]
+ .endm
+
+ /* <mnemonic> <Ws>, <Wt1>, <Wt2>, [<Xn|SP>]{,#0}] */
+ .macro SP32 op
+ \op w15, w1, w2, [x7]
+ \op w15, w1, w2, [x7, #0]
+ \op w15, w1, w2, [x7, 0]
+ .endm
+
+ /* <mnemonic> <Ws>, <Xt1>, <Xt2>, [<Xn|SP>]{,#0}] */
+ .macro SP64 op
+ \op w15, x1, x2, [x7]
+ \op w15, x1, x2, [x7, #0]
+ \op w15, x1, x2, [x7, 0]
+ .endm
+
+ /* <mnemonic> <Wt>, [<Xn|SP>]{,#0}] */
+ .macro SL32 op
+ \op w1, [x7]
+ \op w1, [x7, #0]
+ \op w1, [x7, 0]
+ .endm
+
+ /* <mnemonic> <Xt>, [<Xn|SP>]{,#0}] */
+ .macro SL64 op
+ \op x1, [x7]
+ \op x1, [x7, #0]
+ \op x1, [x7, 0]
+ .endm
+
+func:
+ .irp op, stxrb, stxrh, stxr
+ SR32 \op
+ .endr
+
+ SR64 stxr
+
+ .irp op, ldxrb, ldxrh, ldxr
+ LR32 \op
+ .endr
+
+ LR64 ldxr
+
+ SP32 stxp
+ SP64 stxp
+ LP32 ldxp
+ LP64 ldxp
+
+ .irp op, stlxrb, stlxrh, stlxr
+ SR32 \op
+ .endr
+
+ SR64 stlxr
+
+ .irp op, ldaxrb, ldaxrh, ldaxr
+ LR32 \op
+ .endr
+
+ LR64 ldaxr
+
+ SP32 stlxp
+ SP64 stlxp
+ LP32 ldaxp
+ LP64 ldaxp
+
+ .irp op, stlrb, stlrh, stlr
+ SL32 \op
+ .endr
+
+ SL64 stlr
+
+ .irp op, ldarb, ldarh, ldar
+ LR32 \op
+ .endr
+
+ LR64 ldar
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 3c1007e7 str b7, \[sp\],#-256
+ 4: 3c1557e7 str b7, \[sp\],#-171
+ 8: 3c0007e7 str b7, \[sp\],#0
+ c: 3c0027e7 str b7, \[sp\],#2
+ 10: 3c0047e7 str b7, \[sp\],#4
+ 14: 3c0087e7 str b7, \[sp\],#8
+ 18: 3c0107e7 str b7, \[sp\],#16
+ 1c: 3c0557e7 str b7, \[sp\],#85
+ 20: 3c0ff7e7 str b7, \[sp\],#255
+ 24: 7c1007e7 str h7, \[sp\],#-256
+ 28: 7c1557e7 str h7, \[sp\],#-171
+ 2c: 7c0007e7 str h7, \[sp\],#0
+ 30: 7c0027e7 str h7, \[sp\],#2
+ 34: 7c0047e7 str h7, \[sp\],#4
+ 38: 7c0087e7 str h7, \[sp\],#8
+ 3c: 7c0107e7 str h7, \[sp\],#16
+ 40: 7c0557e7 str h7, \[sp\],#85
+ 44: 7c0ff7e7 str h7, \[sp\],#255
+ 48: bc1007e7 str s7, \[sp\],#-256
+ 4c: bc1557e7 str s7, \[sp\],#-171
+ 50: bc0007e7 str s7, \[sp\],#0
+ 54: bc0027e7 str s7, \[sp\],#2
+ 58: bc0047e7 str s7, \[sp\],#4
+ 5c: bc0087e7 str s7, \[sp\],#8
+ 60: bc0107e7 str s7, \[sp\],#16
+ 64: bc0557e7 str s7, \[sp\],#85
+ 68: bc0ff7e7 str s7, \[sp\],#255
+ 6c: fc1007e7 str d7, \[sp\],#-256
+ 70: fc1557e7 str d7, \[sp\],#-171
+ 74: fc0007e7 str d7, \[sp\],#0
+ 78: fc0027e7 str d7, \[sp\],#2
+ 7c: fc0047e7 str d7, \[sp\],#4
+ 80: fc0087e7 str d7, \[sp\],#8
+ 84: fc0107e7 str d7, \[sp\],#16
+ 88: fc0557e7 str d7, \[sp\],#85
+ 8c: fc0ff7e7 str d7, \[sp\],#255
+ 90: 3c9007e7 str q7, \[sp\],#-256
+ 94: 3c9557e7 str q7, \[sp\],#-171
+ 98: 3c8007e7 str q7, \[sp\],#0
+ 9c: 3c8027e7 str q7, \[sp\],#2
+ a0: 3c8047e7 str q7, \[sp\],#4
+ a4: 3c8087e7 str q7, \[sp\],#8
+ a8: 3c8107e7 str q7, \[sp\],#16
+ ac: 3c8557e7 str q7, \[sp\],#85
+ b0: 3c8ff7e7 str q7, \[sp\],#255
+ b4: 3c5007e7 ldr b7, \[sp\],#-256
+ b8: 3c5557e7 ldr b7, \[sp\],#-171
+ bc: 3c4007e7 ldr b7, \[sp\],#0
+ c0: 3c4027e7 ldr b7, \[sp\],#2
+ c4: 3c4047e7 ldr b7, \[sp\],#4
+ c8: 3c4087e7 ldr b7, \[sp\],#8
+ cc: 3c4107e7 ldr b7, \[sp\],#16
+ d0: 3c4557e7 ldr b7, \[sp\],#85
+ d4: 3c4ff7e7 ldr b7, \[sp\],#255
+ d8: 7c5007e7 ldr h7, \[sp\],#-256
+ dc: 7c5557e7 ldr h7, \[sp\],#-171
+ e0: 7c4007e7 ldr h7, \[sp\],#0
+ e4: 7c4027e7 ldr h7, \[sp\],#2
+ e8: 7c4047e7 ldr h7, \[sp\],#4
+ ec: 7c4087e7 ldr h7, \[sp\],#8
+ f0: 7c4107e7 ldr h7, \[sp\],#16
+ f4: 7c4557e7 ldr h7, \[sp\],#85
+ f8: 7c4ff7e7 ldr h7, \[sp\],#255
+ fc: bc5007e7 ldr s7, \[sp\],#-256
+ 100: bc5557e7 ldr s7, \[sp\],#-171
+ 104: bc4007e7 ldr s7, \[sp\],#0
+ 108: bc4027e7 ldr s7, \[sp\],#2
+ 10c: bc4047e7 ldr s7, \[sp\],#4
+ 110: bc4087e7 ldr s7, \[sp\],#8
+ 114: bc4107e7 ldr s7, \[sp\],#16
+ 118: bc4557e7 ldr s7, \[sp\],#85
+ 11c: bc4ff7e7 ldr s7, \[sp\],#255
+ 120: fc5007e7 ldr d7, \[sp\],#-256
+ 124: fc5557e7 ldr d7, \[sp\],#-171
+ 128: fc4007e7 ldr d7, \[sp\],#0
+ 12c: fc4027e7 ldr d7, \[sp\],#2
+ 130: fc4047e7 ldr d7, \[sp\],#4
+ 134: fc4087e7 ldr d7, \[sp\],#8
+ 138: fc4107e7 ldr d7, \[sp\],#16
+ 13c: fc4557e7 ldr d7, \[sp\],#85
+ 140: fc4ff7e7 ldr d7, \[sp\],#255
+ 144: 3cd007e7 ldr q7, \[sp\],#-256
+ 148: 3cd557e7 ldr q7, \[sp\],#-171
+ 14c: 3cc007e7 ldr q7, \[sp\],#0
+ 150: 3cc027e7 ldr q7, \[sp\],#2
+ 154: 3cc047e7 ldr q7, \[sp\],#4
+ 158: 3cc087e7 ldr q7, \[sp\],#8
+ 15c: 3cc107e7 ldr q7, \[sp\],#16
+ 160: 3cc557e7 ldr q7, \[sp\],#85
+ 164: 3ccff7e7 ldr q7, \[sp\],#255
+ 168: 381007e7 strb w7, \[sp\],#-256
+ 16c: 381557e7 strb w7, \[sp\],#-171
+ 170: 380007e7 strb w7, \[sp\],#0
+ 174: 380027e7 strb w7, \[sp\],#2
+ 178: 380047e7 strb w7, \[sp\],#4
+ 17c: 380087e7 strb w7, \[sp\],#8
+ 180: 380107e7 strb w7, \[sp\],#16
+ 184: 380557e7 strb w7, \[sp\],#85
+ 188: 380ff7e7 strb w7, \[sp\],#255
+ 18c: 781007e7 strh w7, \[sp\],#-256
+ 190: 781557e7 strh w7, \[sp\],#-171
+ 194: 780007e7 strh w7, \[sp\],#0
+ 198: 780027e7 strh w7, \[sp\],#2
+ 19c: 780047e7 strh w7, \[sp\],#4
+ 1a0: 780087e7 strh w7, \[sp\],#8
+ 1a4: 780107e7 strh w7, \[sp\],#16
+ 1a8: 780557e7 strh w7, \[sp\],#85
+ 1ac: 780ff7e7 strh w7, \[sp\],#255
+ 1b0: b81007e7 str w7, \[sp\],#-256
+ 1b4: b81557e7 str w7, \[sp\],#-171
+ 1b8: b80007e7 str w7, \[sp\],#0
+ 1bc: b80027e7 str w7, \[sp\],#2
+ 1c0: b80047e7 str w7, \[sp\],#4
+ 1c4: b80087e7 str w7, \[sp\],#8
+ 1c8: b80107e7 str w7, \[sp\],#16
+ 1cc: b80557e7 str w7, \[sp\],#85
+ 1d0: b80ff7e7 str w7, \[sp\],#255
+ 1d4: f81007e7 str x7, \[sp\],#-256
+ 1d8: f81557e7 str x7, \[sp\],#-171
+ 1dc: f80007e7 str x7, \[sp\],#0
+ 1e0: f80027e7 str x7, \[sp\],#2
+ 1e4: f80047e7 str x7, \[sp\],#4
+ 1e8: f80087e7 str x7, \[sp\],#8
+ 1ec: f80107e7 str x7, \[sp\],#16
+ 1f0: f80557e7 str x7, \[sp\],#85
+ 1f4: f80ff7e7 str x7, \[sp\],#255
+ 1f8: 385007e7 ldrb w7, \[sp\],#-256
+ 1fc: 385557e7 ldrb w7, \[sp\],#-171
+ 200: 384007e7 ldrb w7, \[sp\],#0
+ 204: 384027e7 ldrb w7, \[sp\],#2
+ 208: 384047e7 ldrb w7, \[sp\],#4
+ 20c: 384087e7 ldrb w7, \[sp\],#8
+ 210: 384107e7 ldrb w7, \[sp\],#16
+ 214: 384557e7 ldrb w7, \[sp\],#85
+ 218: 384ff7e7 ldrb w7, \[sp\],#255
+ 21c: 785007e7 ldrh w7, \[sp\],#-256
+ 220: 785557e7 ldrh w7, \[sp\],#-171
+ 224: 784007e7 ldrh w7, \[sp\],#0
+ 228: 784027e7 ldrh w7, \[sp\],#2
+ 22c: 784047e7 ldrh w7, \[sp\],#4
+ 230: 784087e7 ldrh w7, \[sp\],#8
+ 234: 784107e7 ldrh w7, \[sp\],#16
+ 238: 784557e7 ldrh w7, \[sp\],#85
+ 23c: 784ff7e7 ldrh w7, \[sp\],#255
+ 240: b85007e7 ldr w7, \[sp\],#-256
+ 244: b85557e7 ldr w7, \[sp\],#-171
+ 248: b84007e7 ldr w7, \[sp\],#0
+ 24c: b84027e7 ldr w7, \[sp\],#2
+ 250: b84047e7 ldr w7, \[sp\],#4
+ 254: b84087e7 ldr w7, \[sp\],#8
+ 258: b84107e7 ldr w7, \[sp\],#16
+ 25c: b84557e7 ldr w7, \[sp\],#85
+ 260: b84ff7e7 ldr w7, \[sp\],#255
+ 264: f85007e7 ldr x7, \[sp\],#-256
+ 268: f85557e7 ldr x7, \[sp\],#-171
+ 26c: f84007e7 ldr x7, \[sp\],#0
+ 270: f84027e7 ldr x7, \[sp\],#2
+ 274: f84047e7 ldr x7, \[sp\],#4
+ 278: f84087e7 ldr x7, \[sp\],#8
+ 27c: f84107e7 ldr x7, \[sp\],#16
+ 280: f84557e7 ldr x7, \[sp\],#85
+ 284: f84ff7e7 ldr x7, \[sp\],#255
+ 288: 389007e7 ldrsb x7, \[sp\],#-256
+ 28c: 389557e7 ldrsb x7, \[sp\],#-171
+ 290: 388007e7 ldrsb x7, \[sp\],#0
+ 294: 388027e7 ldrsb x7, \[sp\],#2
+ 298: 388047e7 ldrsb x7, \[sp\],#4
+ 29c: 388087e7 ldrsb x7, \[sp\],#8
+ 2a0: 388107e7 ldrsb x7, \[sp\],#16
+ 2a4: 388557e7 ldrsb x7, \[sp\],#85
+ 2a8: 388ff7e7 ldrsb x7, \[sp\],#255
+ 2ac: 789007e7 ldrsh x7, \[sp\],#-256
+ 2b0: 789557e7 ldrsh x7, \[sp\],#-171
+ 2b4: 788007e7 ldrsh x7, \[sp\],#0
+ 2b8: 788027e7 ldrsh x7, \[sp\],#2
+ 2bc: 788047e7 ldrsh x7, \[sp\],#4
+ 2c0: 788087e7 ldrsh x7, \[sp\],#8
+ 2c4: 788107e7 ldrsh x7, \[sp\],#16
+ 2c8: 788557e7 ldrsh x7, \[sp\],#85
+ 2cc: 788ff7e7 ldrsh x7, \[sp\],#255
+ 2d0: b89007e7 ldrsw x7, \[sp\],#-256
+ 2d4: b89557e7 ldrsw x7, \[sp\],#-171
+ 2d8: b88007e7 ldrsw x7, \[sp\],#0
+ 2dc: b88027e7 ldrsw x7, \[sp\],#2
+ 2e0: b88047e7 ldrsw x7, \[sp\],#4
+ 2e4: b88087e7 ldrsw x7, \[sp\],#8
+ 2e8: b88107e7 ldrsw x7, \[sp\],#16
+ 2ec: b88557e7 ldrsw x7, \[sp\],#85
+ 2f0: b88ff7e7 ldrsw x7, \[sp\],#255
+ 2f4: 38d007e7 ldrsb w7, \[sp\],#-256
+ 2f8: 38d557e7 ldrsb w7, \[sp\],#-171
+ 2fc: 38c007e7 ldrsb w7, \[sp\],#0
+ 300: 38c027e7 ldrsb w7, \[sp\],#2
+ 304: 38c047e7 ldrsb w7, \[sp\],#4
+ 308: 38c087e7 ldrsb w7, \[sp\],#8
+ 30c: 38c107e7 ldrsb w7, \[sp\],#16
+ 310: 38c557e7 ldrsb w7, \[sp\],#85
+ 314: 38cff7e7 ldrsb w7, \[sp\],#255
+ 318: 78d007e7 ldrsh w7, \[sp\],#-256
+ 31c: 78d557e7 ldrsh w7, \[sp\],#-171
+ 320: 78c007e7 ldrsh w7, \[sp\],#0
+ 324: 78c027e7 ldrsh w7, \[sp\],#2
+ 328: 78c047e7 ldrsh w7, \[sp\],#4
+ 32c: 78c087e7 ldrsh w7, \[sp\],#8
+ 330: 78c107e7 ldrsh w7, \[sp\],#16
+ 334: 78c557e7 ldrsh w7, \[sp\],#85
+ 338: 78cff7e7 ldrsh w7, \[sp\],#255
--- /dev/null
+/* ldst-reg-imm-post-ind.s Test file for AArch64
+ load-store reg. (imm.post-ind.) instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro op2 op, reg, simm
+ \op \reg\()7, [sp], #\simm
+ .endm
+
+ // load to or store from core register
+ .macro ld_or_st op, suffix, reg
+ .irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
+ op2 \op\suffix, \reg, \simm
+ .endr
+ .endm
+
+ // load to or store from FP/SIMD register
+ .macro ld_or_st_v op
+ .irp reg, b, h, s, d, q
+ .irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
+ op2 \op, \reg, \simm
+ .endr
+ .endr
+ .endm
+
+func:
+ // load to or store from FP/SIMD register
+ ld_or_st_v str
+ ld_or_st_v ldr
+
+ // load to or store from core register
+ // op, suffix, reg
+ ld_or_st str, b, w
+ ld_or_st str, h, w
+ ld_or_st str, , w
+ ld_or_st str, , x
+ ld_or_st ldr, b, w
+ ld_or_st ldr, h, w
+ ld_or_st ldr, , w
+ ld_or_st ldr, , x
+ ld_or_st ldr, sb, x
+ ld_or_st ldr, sh, x
+ ld_or_st ldr, sw, x
+ ld_or_st ldr, sb, w
+ ld_or_st ldr, sh, w
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 3c100fe7 str b7, \[sp,#-256\]!
+ 4: 3c155fe7 str b7, \[sp,#-171\]!
+ 8: 3c000fe7 str b7, \[sp,#0\]!
+ c: 3c002fe7 str b7, \[sp,#2\]!
+ 10: 3c004fe7 str b7, \[sp,#4\]!
+ 14: 3c008fe7 str b7, \[sp,#8\]!
+ 18: 3c010fe7 str b7, \[sp,#16\]!
+ 1c: 3c055fe7 str b7, \[sp,#85\]!
+ 20: 3c0fffe7 str b7, \[sp,#255\]!
+ 24: 7c100fe7 str h7, \[sp,#-256\]!
+ 28: 7c155fe7 str h7, \[sp,#-171\]!
+ 2c: 7c000fe7 str h7, \[sp,#0\]!
+ 30: 7c002fe7 str h7, \[sp,#2\]!
+ 34: 7c004fe7 str h7, \[sp,#4\]!
+ 38: 7c008fe7 str h7, \[sp,#8\]!
+ 3c: 7c010fe7 str h7, \[sp,#16\]!
+ 40: 7c055fe7 str h7, \[sp,#85\]!
+ 44: 7c0fffe7 str h7, \[sp,#255\]!
+ 48: bc100fe7 str s7, \[sp,#-256\]!
+ 4c: bc155fe7 str s7, \[sp,#-171\]!
+ 50: bc000fe7 str s7, \[sp,#0\]!
+ 54: bc002fe7 str s7, \[sp,#2\]!
+ 58: bc004fe7 str s7, \[sp,#4\]!
+ 5c: bc008fe7 str s7, \[sp,#8\]!
+ 60: bc010fe7 str s7, \[sp,#16\]!
+ 64: bc055fe7 str s7, \[sp,#85\]!
+ 68: bc0fffe7 str s7, \[sp,#255\]!
+ 6c: fc100fe7 str d7, \[sp,#-256\]!
+ 70: fc155fe7 str d7, \[sp,#-171\]!
+ 74: fc000fe7 str d7, \[sp,#0\]!
+ 78: fc002fe7 str d7, \[sp,#2\]!
+ 7c: fc004fe7 str d7, \[sp,#4\]!
+ 80: fc008fe7 str d7, \[sp,#8\]!
+ 84: fc010fe7 str d7, \[sp,#16\]!
+ 88: fc055fe7 str d7, \[sp,#85\]!
+ 8c: fc0fffe7 str d7, \[sp,#255\]!
+ 90: 3c900fe7 str q7, \[sp,#-256\]!
+ 94: 3c955fe7 str q7, \[sp,#-171\]!
+ 98: 3c800fe7 str q7, \[sp,#0\]!
+ 9c: 3c802fe7 str q7, \[sp,#2\]!
+ a0: 3c804fe7 str q7, \[sp,#4\]!
+ a4: 3c808fe7 str q7, \[sp,#8\]!
+ a8: 3c810fe7 str q7, \[sp,#16\]!
+ ac: 3c855fe7 str q7, \[sp,#85\]!
+ b0: 3c8fffe7 str q7, \[sp,#255\]!
+ b4: 3c500fe7 ldr b7, \[sp,#-256\]!
+ b8: 3c555fe7 ldr b7, \[sp,#-171\]!
+ bc: 3c400fe7 ldr b7, \[sp,#0\]!
+ c0: 3c402fe7 ldr b7, \[sp,#2\]!
+ c4: 3c404fe7 ldr b7, \[sp,#4\]!
+ c8: 3c408fe7 ldr b7, \[sp,#8\]!
+ cc: 3c410fe7 ldr b7, \[sp,#16\]!
+ d0: 3c455fe7 ldr b7, \[sp,#85\]!
+ d4: 3c4fffe7 ldr b7, \[sp,#255\]!
+ d8: 7c500fe7 ldr h7, \[sp,#-256\]!
+ dc: 7c555fe7 ldr h7, \[sp,#-171\]!
+ e0: 7c400fe7 ldr h7, \[sp,#0\]!
+ e4: 7c402fe7 ldr h7, \[sp,#2\]!
+ e8: 7c404fe7 ldr h7, \[sp,#4\]!
+ ec: 7c408fe7 ldr h7, \[sp,#8\]!
+ f0: 7c410fe7 ldr h7, \[sp,#16\]!
+ f4: 7c455fe7 ldr h7, \[sp,#85\]!
+ f8: 7c4fffe7 ldr h7, \[sp,#255\]!
+ fc: bc500fe7 ldr s7, \[sp,#-256\]!
+ 100: bc555fe7 ldr s7, \[sp,#-171\]!
+ 104: bc400fe7 ldr s7, \[sp,#0\]!
+ 108: bc402fe7 ldr s7, \[sp,#2\]!
+ 10c: bc404fe7 ldr s7, \[sp,#4\]!
+ 110: bc408fe7 ldr s7, \[sp,#8\]!
+ 114: bc410fe7 ldr s7, \[sp,#16\]!
+ 118: bc455fe7 ldr s7, \[sp,#85\]!
+ 11c: bc4fffe7 ldr s7, \[sp,#255\]!
+ 120: fc500fe7 ldr d7, \[sp,#-256\]!
+ 124: fc555fe7 ldr d7, \[sp,#-171\]!
+ 128: fc400fe7 ldr d7, \[sp,#0\]!
+ 12c: fc402fe7 ldr d7, \[sp,#2\]!
+ 130: fc404fe7 ldr d7, \[sp,#4\]!
+ 134: fc408fe7 ldr d7, \[sp,#8\]!
+ 138: fc410fe7 ldr d7, \[sp,#16\]!
+ 13c: fc455fe7 ldr d7, \[sp,#85\]!
+ 140: fc4fffe7 ldr d7, \[sp,#255\]!
+ 144: 3cd00fe7 ldr q7, \[sp,#-256\]!
+ 148: 3cd55fe7 ldr q7, \[sp,#-171\]!
+ 14c: 3cc00fe7 ldr q7, \[sp,#0\]!
+ 150: 3cc02fe7 ldr q7, \[sp,#2\]!
+ 154: 3cc04fe7 ldr q7, \[sp,#4\]!
+ 158: 3cc08fe7 ldr q7, \[sp,#8\]!
+ 15c: 3cc10fe7 ldr q7, \[sp,#16\]!
+ 160: 3cc55fe7 ldr q7, \[sp,#85\]!
+ 164: 3ccfffe7 ldr q7, \[sp,#255\]!
+ 168: 38100fe7 strb w7, \[sp,#-256\]!
+ 16c: 38155fe7 strb w7, \[sp,#-171\]!
+ 170: 38000fe7 strb w7, \[sp,#0\]!
+ 174: 38002fe7 strb w7, \[sp,#2\]!
+ 178: 38004fe7 strb w7, \[sp,#4\]!
+ 17c: 38008fe7 strb w7, \[sp,#8\]!
+ 180: 38010fe7 strb w7, \[sp,#16\]!
+ 184: 38055fe7 strb w7, \[sp,#85\]!
+ 188: 380fffe7 strb w7, \[sp,#255\]!
+ 18c: 78100fe7 strh w7, \[sp,#-256\]!
+ 190: 78155fe7 strh w7, \[sp,#-171\]!
+ 194: 78000fe7 strh w7, \[sp,#0\]!
+ 198: 78002fe7 strh w7, \[sp,#2\]!
+ 19c: 78004fe7 strh w7, \[sp,#4\]!
+ 1a0: 78008fe7 strh w7, \[sp,#8\]!
+ 1a4: 78010fe7 strh w7, \[sp,#16\]!
+ 1a8: 78055fe7 strh w7, \[sp,#85\]!
+ 1ac: 780fffe7 strh w7, \[sp,#255\]!
+ 1b0: b8100fe7 str w7, \[sp,#-256\]!
+ 1b4: b8155fe7 str w7, \[sp,#-171\]!
+ 1b8: b8000fe7 str w7, \[sp,#0\]!
+ 1bc: b8002fe7 str w7, \[sp,#2\]!
+ 1c0: b8004fe7 str w7, \[sp,#4\]!
+ 1c4: b8008fe7 str w7, \[sp,#8\]!
+ 1c8: b8010fe7 str w7, \[sp,#16\]!
+ 1cc: b8055fe7 str w7, \[sp,#85\]!
+ 1d0: b80fffe7 str w7, \[sp,#255\]!
+ 1d4: f8100fe7 str x7, \[sp,#-256\]!
+ 1d8: f8155fe7 str x7, \[sp,#-171\]!
+ 1dc: f8000fe7 str x7, \[sp,#0\]!
+ 1e0: f8002fe7 str x7, \[sp,#2\]!
+ 1e4: f8004fe7 str x7, \[sp,#4\]!
+ 1e8: f8008fe7 str x7, \[sp,#8\]!
+ 1ec: f8010fe7 str x7, \[sp,#16\]!
+ 1f0: f8055fe7 str x7, \[sp,#85\]!
+ 1f4: f80fffe7 str x7, \[sp,#255\]!
+ 1f8: 38500fe7 ldrb w7, \[sp,#-256\]!
+ 1fc: 38555fe7 ldrb w7, \[sp,#-171\]!
+ 200: 38400fe7 ldrb w7, \[sp,#0\]!
+ 204: 38402fe7 ldrb w7, \[sp,#2\]!
+ 208: 38404fe7 ldrb w7, \[sp,#4\]!
+ 20c: 38408fe7 ldrb w7, \[sp,#8\]!
+ 210: 38410fe7 ldrb w7, \[sp,#16\]!
+ 214: 38455fe7 ldrb w7, \[sp,#85\]!
+ 218: 384fffe7 ldrb w7, \[sp,#255\]!
+ 21c: 78500fe7 ldrh w7, \[sp,#-256\]!
+ 220: 78555fe7 ldrh w7, \[sp,#-171\]!
+ 224: 78400fe7 ldrh w7, \[sp,#0\]!
+ 228: 78402fe7 ldrh w7, \[sp,#2\]!
+ 22c: 78404fe7 ldrh w7, \[sp,#4\]!
+ 230: 78408fe7 ldrh w7, \[sp,#8\]!
+ 234: 78410fe7 ldrh w7, \[sp,#16\]!
+ 238: 78455fe7 ldrh w7, \[sp,#85\]!
+ 23c: 784fffe7 ldrh w7, \[sp,#255\]!
+ 240: b8500fe7 ldr w7, \[sp,#-256\]!
+ 244: b8555fe7 ldr w7, \[sp,#-171\]!
+ 248: b8400fe7 ldr w7, \[sp,#0\]!
+ 24c: b8402fe7 ldr w7, \[sp,#2\]!
+ 250: b8404fe7 ldr w7, \[sp,#4\]!
+ 254: b8408fe7 ldr w7, \[sp,#8\]!
+ 258: b8410fe7 ldr w7, \[sp,#16\]!
+ 25c: b8455fe7 ldr w7, \[sp,#85\]!
+ 260: b84fffe7 ldr w7, \[sp,#255\]!
+ 264: f8500fe7 ldr x7, \[sp,#-256\]!
+ 268: f8555fe7 ldr x7, \[sp,#-171\]!
+ 26c: f8400fe7 ldr x7, \[sp,#0\]!
+ 270: f8402fe7 ldr x7, \[sp,#2\]!
+ 274: f8404fe7 ldr x7, \[sp,#4\]!
+ 278: f8408fe7 ldr x7, \[sp,#8\]!
+ 27c: f8410fe7 ldr x7, \[sp,#16\]!
+ 280: f8455fe7 ldr x7, \[sp,#85\]!
+ 284: f84fffe7 ldr x7, \[sp,#255\]!
+ 288: 38900fe7 ldrsb x7, \[sp,#-256\]!
+ 28c: 38955fe7 ldrsb x7, \[sp,#-171\]!
+ 290: 38800fe7 ldrsb x7, \[sp,#0\]!
+ 294: 38802fe7 ldrsb x7, \[sp,#2\]!
+ 298: 38804fe7 ldrsb x7, \[sp,#4\]!
+ 29c: 38808fe7 ldrsb x7, \[sp,#8\]!
+ 2a0: 38810fe7 ldrsb x7, \[sp,#16\]!
+ 2a4: 38855fe7 ldrsb x7, \[sp,#85\]!
+ 2a8: 388fffe7 ldrsb x7, \[sp,#255\]!
+ 2ac: 78900fe7 ldrsh x7, \[sp,#-256\]!
+ 2b0: 78955fe7 ldrsh x7, \[sp,#-171\]!
+ 2b4: 78800fe7 ldrsh x7, \[sp,#0\]!
+ 2b8: 78802fe7 ldrsh x7, \[sp,#2\]!
+ 2bc: 78804fe7 ldrsh x7, \[sp,#4\]!
+ 2c0: 78808fe7 ldrsh x7, \[sp,#8\]!
+ 2c4: 78810fe7 ldrsh x7, \[sp,#16\]!
+ 2c8: 78855fe7 ldrsh x7, \[sp,#85\]!
+ 2cc: 788fffe7 ldrsh x7, \[sp,#255\]!
+ 2d0: b8900fe7 ldrsw x7, \[sp,#-256\]!
+ 2d4: b8955fe7 ldrsw x7, \[sp,#-171\]!
+ 2d8: b8800fe7 ldrsw x7, \[sp,#0\]!
+ 2dc: b8802fe7 ldrsw x7, \[sp,#2\]!
+ 2e0: b8804fe7 ldrsw x7, \[sp,#4\]!
+ 2e4: b8808fe7 ldrsw x7, \[sp,#8\]!
+ 2e8: b8810fe7 ldrsw x7, \[sp,#16\]!
+ 2ec: b8855fe7 ldrsw x7, \[sp,#85\]!
+ 2f0: b88fffe7 ldrsw x7, \[sp,#255\]!
+ 2f4: 38d00fe7 ldrsb w7, \[sp,#-256\]!
+ 2f8: 38d55fe7 ldrsb w7, \[sp,#-171\]!
+ 2fc: 38c00fe7 ldrsb w7, \[sp,#0\]!
+ 300: 38c02fe7 ldrsb w7, \[sp,#2\]!
+ 304: 38c04fe7 ldrsb w7, \[sp,#4\]!
+ 308: 38c08fe7 ldrsb w7, \[sp,#8\]!
+ 30c: 38c10fe7 ldrsb w7, \[sp,#16\]!
+ 310: 38c55fe7 ldrsb w7, \[sp,#85\]!
+ 314: 38cfffe7 ldrsb w7, \[sp,#255\]!
+ 318: 78d00fe7 ldrsh w7, \[sp,#-256\]!
+ 31c: 78d55fe7 ldrsh w7, \[sp,#-171\]!
+ 320: 78c00fe7 ldrsh w7, \[sp,#0\]!
+ 324: 78c02fe7 ldrsh w7, \[sp,#2\]!
+ 328: 78c04fe7 ldrsh w7, \[sp,#4\]!
+ 32c: 78c08fe7 ldrsh w7, \[sp,#8\]!
+ 330: 78c10fe7 ldrsh w7, \[sp,#16\]!
+ 334: 78c55fe7 ldrsh w7, \[sp,#85\]!
+ 338: 78cfffe7 ldrsh w7, \[sp,#255\]!
--- /dev/null
+/* ldst-reg-imm-pre-ind.s Test file for AArch64
+ load-store reg. (imm.pre-ind.) instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro op2 op, reg, simm
+ \op \reg\()7, [sp, #\simm]!
+ .endm
+
+ // load to or store from core register
+ .macro ld_or_st op, suffix, reg
+ .irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
+ op2 \op\suffix, \reg, \simm
+ .endr
+ .endm
+
+ // load to or store from FP/SIMD register
+ .macro ld_or_st_v op
+ .irp reg, b, h, s, d, q
+ .irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
+ op2 \op, \reg, \simm
+ .endr
+ .endr
+ .endm
+
+func:
+ // load to or store from FP/SIMD register
+ ld_or_st_v str
+ ld_or_st_v ldr
+
+ // load to or store from core register
+ // op, suffix, reg
+ ld_or_st str, b, w
+ ld_or_st str, h, w
+ ld_or_st str, , w
+ ld_or_st str, , x
+ ld_or_st ldr, b, w
+ ld_or_st ldr, h, w
+ ld_or_st ldr, , w
+ ld_or_st ldr, , x
+ ld_or_st ldr, sb, x
+ ld_or_st ldr, sh, x
+ ld_or_st ldr, sw, x
+ ld_or_st ldr, sb, w
+ ld_or_st ldr, sh, w
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 29203fe7 stp w7, w15, \[sp,#-256\]
+ 4: 2930bfe7 stp w7, w15, \[sp,#-124\]
+ 8: 293fbfe7 stp w7, w15, \[sp,#-4\]
+ c: 29003fe7 stp w7, w15, \[sp\]
+ 10: 2907bfe7 stp w7, w15, \[sp,#60\]
+ 14: 291fbfe7 stp w7, w15, \[sp,#252\]
+ 18: 29603fe7 ldp w7, w15, \[sp,#-256\]
+ 1c: 2970bfe7 ldp w7, w15, \[sp,#-124\]
+ 20: 297fbfe7 ldp w7, w15, \[sp,#-4\]
+ 24: 29403fe7 ldp w7, w15, \[sp\]
+ 28: 2947bfe7 ldp w7, w15, \[sp,#60\]
+ 2c: 295fbfe7 ldp w7, w15, \[sp,#252\]
+ 30: 69603fe7 ldpsw x7, x15, \[sp,#-256\]
+ 34: 6970bfe7 ldpsw x7, x15, \[sp,#-124\]
+ 38: 697fbfe7 ldpsw x7, x15, \[sp,#-4\]
+ 3c: 69403fe7 ldpsw x7, x15, \[sp\]
+ 40: 6947bfe7 ldpsw x7, x15, \[sp,#60\]
+ 44: 695fbfe7 ldpsw x7, x15, \[sp,#252\]
+ 48: a9203fe7 stp x7, x15, \[sp,#-512\]
+ 4c: a930bfe7 stp x7, x15, \[sp,#-248\]
+ 50: a93fbfe7 stp x7, x15, \[sp,#-8\]
+ 54: a9003fe7 stp x7, x15, \[sp\]
+ 58: a907bfe7 stp x7, x15, \[sp,#120\]
+ 5c: a91fbfe7 stp x7, x15, \[sp,#504\]
+ 60: a9603fe7 ldp x7, x15, \[sp,#-512\]
+ 64: a970bfe7 ldp x7, x15, \[sp,#-248\]
+ 68: a97fbfe7 ldp x7, x15, \[sp,#-8\]
+ 6c: a9403fe7 ldp x7, x15, \[sp\]
+ 70: a947bfe7 ldp x7, x15, \[sp,#120\]
+ 74: a95fbfe7 ldp x7, x15, \[sp,#504\]
+ 78: 2d203fe7 stp s7, s15, \[sp,#-256\]
+ 7c: 2d30bfe7 stp s7, s15, \[sp,#-124\]
+ 80: 2d3fbfe7 stp s7, s15, \[sp,#-4\]
+ 84: 2d003fe7 stp s7, s15, \[sp\]
+ 88: 2d07bfe7 stp s7, s15, \[sp,#60\]
+ 8c: 2d1fbfe7 stp s7, s15, \[sp,#252\]
+ 90: 2d603fe7 ldp s7, s15, \[sp,#-256\]
+ 94: 2d70bfe7 ldp s7, s15, \[sp,#-124\]
+ 98: 2d7fbfe7 ldp s7, s15, \[sp,#-4\]
+ 9c: 2d403fe7 ldp s7, s15, \[sp\]
+ a0: 2d47bfe7 ldp s7, s15, \[sp,#60\]
+ a4: 2d5fbfe7 ldp s7, s15, \[sp,#252\]
+ a8: 6d203fe7 stp d7, d15, \[sp,#-512\]
+ ac: 6d30bfe7 stp d7, d15, \[sp,#-248\]
+ b0: 6d3fbfe7 stp d7, d15, \[sp,#-8\]
+ b4: 6d003fe7 stp d7, d15, \[sp\]
+ b8: 6d07bfe7 stp d7, d15, \[sp,#120\]
+ bc: 6d1fbfe7 stp d7, d15, \[sp,#504\]
+ c0: 6d603fe7 ldp d7, d15, \[sp,#-512\]
+ c4: 6d70bfe7 ldp d7, d15, \[sp,#-248\]
+ c8: 6d7fbfe7 ldp d7, d15, \[sp,#-8\]
+ cc: 6d403fe7 ldp d7, d15, \[sp\]
+ d0: 6d47bfe7 ldp d7, d15, \[sp,#120\]
+ d4: 6d5fbfe7 ldp d7, d15, \[sp,#504\]
+ d8: ad203fe7 stp q7, q15, \[sp,#-1024\]
+ dc: ad30bfe7 stp q7, q15, \[sp,#-496\]
+ e0: ad3fbfe7 stp q7, q15, \[sp,#-16\]
+ e4: ad003fe7 stp q7, q15, \[sp\]
+ e8: ad07bfe7 stp q7, q15, \[sp,#240\]
+ ec: ad1fbfe7 stp q7, q15, \[sp,#1008\]
+ f0: ad603fe7 ldp q7, q15, \[sp,#-1024\]
+ f4: ad70bfe7 ldp q7, q15, \[sp,#-496\]
+ f8: ad7fbfe7 ldp q7, q15, \[sp,#-16\]
+ fc: ad403fe7 ldp q7, q15, \[sp\]
+ 100: ad47bfe7 ldp q7, q15, \[sp,#240\]
+ 104: ad5fbfe7 ldp q7, q15, \[sp,#1008\]
+ 108: 28a03fe7 stp w7, w15, \[sp\],#-256
+ 10c: 28b0bfe7 stp w7, w15, \[sp\],#-124
+ 110: 28bfbfe7 stp w7, w15, \[sp\],#-4
+ 114: 28803fe7 stp w7, w15, \[sp\],#0
+ 118: 2887bfe7 stp w7, w15, \[sp\],#60
+ 11c: 289fbfe7 stp w7, w15, \[sp\],#252
+ 120: 28e03fe7 ldp w7, w15, \[sp\],#-256
+ 124: 28f0bfe7 ldp w7, w15, \[sp\],#-124
+ 128: 28ffbfe7 ldp w7, w15, \[sp\],#-4
+ 12c: 28c03fe7 ldp w7, w15, \[sp\],#0
+ 130: 28c7bfe7 ldp w7, w15, \[sp\],#60
+ 134: 28dfbfe7 ldp w7, w15, \[sp\],#252
+ 138: 68e03fe7 ldpsw x7, x15, \[sp\],#-256
+ 13c: 68f0bfe7 ldpsw x7, x15, \[sp\],#-124
+ 140: 68ffbfe7 ldpsw x7, x15, \[sp\],#-4
+ 144: 68c03fe7 ldpsw x7, x15, \[sp\],#0
+ 148: 68c7bfe7 ldpsw x7, x15, \[sp\],#60
+ 14c: 68dfbfe7 ldpsw x7, x15, \[sp\],#252
+ 150: a8a03fe7 stp x7, x15, \[sp\],#-512
+ 154: a8b0bfe7 stp x7, x15, \[sp\],#-248
+ 158: a8bfbfe7 stp x7, x15, \[sp\],#-8
+ 15c: a8803fe7 stp x7, x15, \[sp\],#0
+ 160: a887bfe7 stp x7, x15, \[sp\],#120
+ 164: a89fbfe7 stp x7, x15, \[sp\],#504
+ 168: a8e03fe7 ldp x7, x15, \[sp\],#-512
+ 16c: a8f0bfe7 ldp x7, x15, \[sp\],#-248
+ 170: a8ffbfe7 ldp x7, x15, \[sp\],#-8
+ 174: a8c03fe7 ldp x7, x15, \[sp\],#0
+ 178: a8c7bfe7 ldp x7, x15, \[sp\],#120
+ 17c: a8dfbfe7 ldp x7, x15, \[sp\],#504
+ 180: 2ca03fe7 stp s7, s15, \[sp\],#-256
+ 184: 2cb0bfe7 stp s7, s15, \[sp\],#-124
+ 188: 2cbfbfe7 stp s7, s15, \[sp\],#-4
+ 18c: 2c803fe7 stp s7, s15, \[sp\],#0
+ 190: 2c87bfe7 stp s7, s15, \[sp\],#60
+ 194: 2c9fbfe7 stp s7, s15, \[sp\],#252
+ 198: 2ce03fe7 ldp s7, s15, \[sp\],#-256
+ 19c: 2cf0bfe7 ldp s7, s15, \[sp\],#-124
+ 1a0: 2cffbfe7 ldp s7, s15, \[sp\],#-4
+ 1a4: 2cc03fe7 ldp s7, s15, \[sp\],#0
+ 1a8: 2cc7bfe7 ldp s7, s15, \[sp\],#60
+ 1ac: 2cdfbfe7 ldp s7, s15, \[sp\],#252
+ 1b0: 6ca03fe7 stp d7, d15, \[sp\],#-512
+ 1b4: 6cb0bfe7 stp d7, d15, \[sp\],#-248
+ 1b8: 6cbfbfe7 stp d7, d15, \[sp\],#-8
+ 1bc: 6c803fe7 stp d7, d15, \[sp\],#0
+ 1c0: 6c87bfe7 stp d7, d15, \[sp\],#120
+ 1c4: 6c9fbfe7 stp d7, d15, \[sp\],#504
+ 1c8: 6ce03fe7 ldp d7, d15, \[sp\],#-512
+ 1cc: 6cf0bfe7 ldp d7, d15, \[sp\],#-248
+ 1d0: 6cffbfe7 ldp d7, d15, \[sp\],#-8
+ 1d4: 6cc03fe7 ldp d7, d15, \[sp\],#0
+ 1d8: 6cc7bfe7 ldp d7, d15, \[sp\],#120
+ 1dc: 6cdfbfe7 ldp d7, d15, \[sp\],#504
+ 1e0: aca03fe7 stp q7, q15, \[sp\],#-1024
+ 1e4: acb0bfe7 stp q7, q15, \[sp\],#-496
+ 1e8: acbfbfe7 stp q7, q15, \[sp\],#-16
+ 1ec: ac803fe7 stp q7, q15, \[sp\],#0
+ 1f0: ac87bfe7 stp q7, q15, \[sp\],#240
+ 1f4: ac9fbfe7 stp q7, q15, \[sp\],#1008
+ 1f8: ace03fe7 ldp q7, q15, \[sp\],#-1024
+ 1fc: acf0bfe7 ldp q7, q15, \[sp\],#-496
+ 200: acffbfe7 ldp q7, q15, \[sp\],#-16
+ 204: acc03fe7 ldp q7, q15, \[sp\],#0
+ 208: acc7bfe7 ldp q7, q15, \[sp\],#240
+ 20c: acdfbfe7 ldp q7, q15, \[sp\],#1008
+ 210: 29a03fe7 stp w7, w15, \[sp,#-256\]!
+ 214: 29b0bfe7 stp w7, w15, \[sp,#-124\]!
+ 218: 29bfbfe7 stp w7, w15, \[sp,#-4\]!
+ 21c: 29803fe7 stp w7, w15, \[sp,#0\]!
+ 220: 2987bfe7 stp w7, w15, \[sp,#60\]!
+ 224: 299fbfe7 stp w7, w15, \[sp,#252\]!
+ 228: 29e03fe7 ldp w7, w15, \[sp,#-256\]!
+ 22c: 29f0bfe7 ldp w7, w15, \[sp,#-124\]!
+ 230: 29ffbfe7 ldp w7, w15, \[sp,#-4\]!
+ 234: 29c03fe7 ldp w7, w15, \[sp,#0\]!
+ 238: 29c7bfe7 ldp w7, w15, \[sp,#60\]!
+ 23c: 29dfbfe7 ldp w7, w15, \[sp,#252\]!
+ 240: 69e03fe7 ldpsw x7, x15, \[sp,#-256\]!
+ 244: 69f0bfe7 ldpsw x7, x15, \[sp,#-124\]!
+ 248: 69ffbfe7 ldpsw x7, x15, \[sp,#-4\]!
+ 24c: 69c03fe7 ldpsw x7, x15, \[sp,#0\]!
+ 250: 69c7bfe7 ldpsw x7, x15, \[sp,#60\]!
+ 254: 69dfbfe7 ldpsw x7, x15, \[sp,#252\]!
+ 258: a9a03fe7 stp x7, x15, \[sp,#-512\]!
+ 25c: a9b0bfe7 stp x7, x15, \[sp,#-248\]!
+ 260: a9bfbfe7 stp x7, x15, \[sp,#-8\]!
+ 264: a9803fe7 stp x7, x15, \[sp,#0\]!
+ 268: a987bfe7 stp x7, x15, \[sp,#120\]!
+ 26c: a99fbfe7 stp x7, x15, \[sp,#504\]!
+ 270: a9e03fe7 ldp x7, x15, \[sp,#-512\]!
+ 274: a9f0bfe7 ldp x7, x15, \[sp,#-248\]!
+ 278: a9ffbfe7 ldp x7, x15, \[sp,#-8\]!
+ 27c: a9c03fe7 ldp x7, x15, \[sp,#0\]!
+ 280: a9c7bfe7 ldp x7, x15, \[sp,#120\]!
+ 284: a9dfbfe7 ldp x7, x15, \[sp,#504\]!
+ 288: 2da03fe7 stp s7, s15, \[sp,#-256\]!
+ 28c: 2db0bfe7 stp s7, s15, \[sp,#-124\]!
+ 290: 2dbfbfe7 stp s7, s15, \[sp,#-4\]!
+ 294: 2d803fe7 stp s7, s15, \[sp,#0\]!
+ 298: 2d87bfe7 stp s7, s15, \[sp,#60\]!
+ 29c: 2d9fbfe7 stp s7, s15, \[sp,#252\]!
+ 2a0: 2de03fe7 ldp s7, s15, \[sp,#-256\]!
+ 2a4: 2df0bfe7 ldp s7, s15, \[sp,#-124\]!
+ 2a8: 2dffbfe7 ldp s7, s15, \[sp,#-4\]!
+ 2ac: 2dc03fe7 ldp s7, s15, \[sp,#0\]!
+ 2b0: 2dc7bfe7 ldp s7, s15, \[sp,#60\]!
+ 2b4: 2ddfbfe7 ldp s7, s15, \[sp,#252\]!
+ 2b8: 6da03fe7 stp d7, d15, \[sp,#-512\]!
+ 2bc: 6db0bfe7 stp d7, d15, \[sp,#-248\]!
+ 2c0: 6dbfbfe7 stp d7, d15, \[sp,#-8\]!
+ 2c4: 6d803fe7 stp d7, d15, \[sp,#0\]!
+ 2c8: 6d87bfe7 stp d7, d15, \[sp,#120\]!
+ 2cc: 6d9fbfe7 stp d7, d15, \[sp,#504\]!
+ 2d0: 6de03fe7 ldp d7, d15, \[sp,#-512\]!
+ 2d4: 6df0bfe7 ldp d7, d15, \[sp,#-248\]!
+ 2d8: 6dffbfe7 ldp d7, d15, \[sp,#-8\]!
+ 2dc: 6dc03fe7 ldp d7, d15, \[sp,#0\]!
+ 2e0: 6dc7bfe7 ldp d7, d15, \[sp,#120\]!
+ 2e4: 6ddfbfe7 ldp d7, d15, \[sp,#504\]!
+ 2e8: ada03fe7 stp q7, q15, \[sp,#-1024\]!
+ 2ec: adb0bfe7 stp q7, q15, \[sp,#-496\]!
+ 2f0: adbfbfe7 stp q7, q15, \[sp,#-16\]!
+ 2f4: ad803fe7 stp q7, q15, \[sp,#0\]!
+ 2f8: ad87bfe7 stp q7, q15, \[sp,#240\]!
+ 2fc: ad9fbfe7 stp q7, q15, \[sp,#1008\]!
+ 300: ade03fe7 ldp q7, q15, \[sp,#-1024\]!
+ 304: adf0bfe7 ldp q7, q15, \[sp,#-496\]!
+ 308: adffbfe7 ldp q7, q15, \[sp,#-16\]!
+ 30c: adc03fe7 ldp q7, q15, \[sp,#0\]!
+ 310: adc7bfe7 ldp q7, q15, \[sp,#240\]!
+ 314: addfbfe7 ldp q7, q15, \[sp,#1008\]!
+ 318: 28203fe7 stnp w7, w15, \[sp,#-256\]
+ 31c: 2830bfe7 stnp w7, w15, \[sp,#-124\]
+ 320: 283fbfe7 stnp w7, w15, \[sp,#-4\]
+ 324: 28003fe7 stnp w7, w15, \[sp\]
+ 328: 2807bfe7 stnp w7, w15, \[sp,#60\]
+ 32c: 281fbfe7 stnp w7, w15, \[sp,#252\]
+ 330: 28603fe7 ldnp w7, w15, \[sp,#-256\]
+ 334: 2870bfe7 ldnp w7, w15, \[sp,#-124\]
+ 338: 287fbfe7 ldnp w7, w15, \[sp,#-4\]
+ 33c: 28403fe7 ldnp w7, w15, \[sp\]
+ 340: 2847bfe7 ldnp w7, w15, \[sp,#60\]
+ 344: 285fbfe7 ldnp w7, w15, \[sp,#252\]
+ 348: a8203fe7 stnp x7, x15, \[sp,#-512\]
+ 34c: a830bfe7 stnp x7, x15, \[sp,#-248\]
+ 350: a83fbfe7 stnp x7, x15, \[sp,#-8\]
+ 354: a8003fe7 stnp x7, x15, \[sp\]
+ 358: a807bfe7 stnp x7, x15, \[sp,#120\]
+ 35c: a81fbfe7 stnp x7, x15, \[sp,#504\]
+ 360: a8603fe7 ldnp x7, x15, \[sp,#-512\]
+ 364: a870bfe7 ldnp x7, x15, \[sp,#-248\]
+ 368: a87fbfe7 ldnp x7, x15, \[sp,#-8\]
+ 36c: a8403fe7 ldnp x7, x15, \[sp\]
+ 370: a847bfe7 ldnp x7, x15, \[sp,#120\]
+ 374: a85fbfe7 ldnp x7, x15, \[sp,#504\]
+ 378: 2c203fe7 stnp s7, s15, \[sp,#-256\]
+ 37c: 2c30bfe7 stnp s7, s15, \[sp,#-124\]
+ 380: 2c3fbfe7 stnp s7, s15, \[sp,#-4\]
+ 384: 2c003fe7 stnp s7, s15, \[sp\]
+ 388: 2c07bfe7 stnp s7, s15, \[sp,#60\]
+ 38c: 2c1fbfe7 stnp s7, s15, \[sp,#252\]
+ 390: 2c603fe7 ldnp s7, s15, \[sp,#-256\]
+ 394: 2c70bfe7 ldnp s7, s15, \[sp,#-124\]
+ 398: 2c7fbfe7 ldnp s7, s15, \[sp,#-4\]
+ 39c: 2c403fe7 ldnp s7, s15, \[sp\]
+ 3a0: 2c47bfe7 ldnp s7, s15, \[sp,#60\]
+ 3a4: 2c5fbfe7 ldnp s7, s15, \[sp,#252\]
+ 3a8: 6c203fe7 stnp d7, d15, \[sp,#-512\]
+ 3ac: 6c30bfe7 stnp d7, d15, \[sp,#-248\]
+ 3b0: 6c3fbfe7 stnp d7, d15, \[sp,#-8\]
+ 3b4: 6c003fe7 stnp d7, d15, \[sp\]
+ 3b8: 6c07bfe7 stnp d7, d15, \[sp,#120\]
+ 3bc: 6c1fbfe7 stnp d7, d15, \[sp,#504\]
+ 3c0: 6c603fe7 ldnp d7, d15, \[sp,#-512\]
+ 3c4: 6c70bfe7 ldnp d7, d15, \[sp,#-248\]
+ 3c8: 6c7fbfe7 ldnp d7, d15, \[sp,#-8\]
+ 3cc: 6c403fe7 ldnp d7, d15, \[sp\]
+ 3d0: 6c47bfe7 ldnp d7, d15, \[sp,#120\]
+ 3d4: 6c5fbfe7 ldnp d7, d15, \[sp,#504\]
+ 3d8: ac203fe7 stnp q7, q15, \[sp,#-1024\]
+ 3dc: ac30bfe7 stnp q7, q15, \[sp,#-496\]
+ 3e0: ac3fbfe7 stnp q7, q15, \[sp,#-16\]
+ 3e4: ac003fe7 stnp q7, q15, \[sp\]
+ 3e8: ac07bfe7 stnp q7, q15, \[sp,#240\]
+ 3ec: ac1fbfe7 stnp q7, q15, \[sp,#1008\]
+ 3f0: ac603fe7 ldnp q7, q15, \[sp,#-1024\]
+ 3f4: ac70bfe7 ldnp q7, q15, \[sp,#-496\]
+ 3f8: ac7fbfe7 ldnp q7, q15, \[sp,#-16\]
+ 3fc: ac403fe7 ldnp q7, q15, \[sp\]
+ 400: ac47bfe7 ldnp q7, q15, \[sp,#240\]
+ 404: ac5fbfe7 ldnp q7, q15, \[sp,#1008\]
--- /dev/null
+/* ldst-reg-pair.s Test file for AArch64 load-store reg.pair instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+/* Includes:
+ * Load-store reg.pair (offset)
+ * Load-store reg.pair (post-ind.)
+ * Load-store reg.pair (pre-ind.)
+ * Load-store na.pair (pre-ind.)
+ */
+
+ // offset format
+ .macro op3_offset op, reg, imm
+ \op \reg\()7, \reg\()15, [sp, #\imm]
+ .endm
+
+ // post-ind. format
+ .macro op3_post_ind op, reg, imm
+ \op \reg\()7, \reg\()15, [sp], #\imm
+ .endm
+
+ // pre-ind. format
+ .macro op3_pre_ind op, reg, imm
+ \op \reg\()7, \reg\()15, [sp, #\imm]!
+ .endm
+
+ .macro op3 op, reg, size, type
+ // a variety of values for the imm7 field
+ .irp imm7, -64, -31, -1, 0, 15, 63
+ // offset format
+ .ifc \type, 1
+ op3_offset \op, \reg, "(\imm7*\size)"
+ .endif
+ // post-ind. format
+ .ifc \type, 2
+ op3_post_ind \op, \reg, "(\imm7*\size)"
+ .endif
+ // pre-ind. format
+ .ifc \type, 3
+ op3_pre_ind \op, \reg, "(\imm7*\size)"
+ .endif
+ .endr
+ .endm
+
+ .macro ldst_reg_pair type
+ // op, reg, size(in byte) of one of the pair, type
+ op3 stp, w, 4, \type
+ op3 ldp, w, 4, \type
+
+ op3 ldpsw, x, 4, \type
+
+ op3 stp, x, 8, \type
+ op3 ldp, x, 8, \type
+
+ op3 stp, s, 4, \type
+ op3 ldp, s, 4, \type
+
+ op3 stp, d, 8, \type
+ op3 ldp, d, 8, \type
+
+ op3 stp, q, 16, \type
+ op3 ldp, q, 16, \type
+ .endm
+
+ .macro ldst_reg_na_pair type
+ // op, reg, size(in byte) of one of the pair, type
+ op3 stnp, w, 4, \type
+ op3 ldnp, w, 4, \type
+
+ op3 stnp, x, 8, \type
+ op3 ldnp, x, 8, \type
+
+ op3 stnp, s, 4, \type
+ op3 ldnp, s, 4, \type
+
+ op3 stnp, d, 8, \type
+ op3 ldnp, d, 8, \type
+
+ op3 stnp, q, 16, \type
+ op3 ldnp, q, 16, \type
+ .endm
+
+func:
+ // Load-store reg.pair (offset)
+ ldst_reg_pair 1
+
+ // Load-store reg.pair (post-ind.)
+ ldst_reg_pair 2
+
+ // Load-store reg.pair (pre-ind.)
+ ldst_reg_pair 3
+
+ // Load-store na.pair (offset)
+ ldst_reg_na_pair 1
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 3c274be7 str b7, \[sp,w7,uxtw\]
+ 4: 3c275be7 str b7, \[sp,w7,uxtw #0\]
+ 8: 7c274be7 str h7, \[sp,w7,uxtw\]
+ c: 7c275be7 str h7, \[sp,w7,uxtw #1\]
+ 10: bc274be7 str s7, \[sp,w7,uxtw\]
+ 14: bc275be7 str s7, \[sp,w7,uxtw #2\]
+ 18: fc274be7 str d7, \[sp,w7,uxtw\]
+ 1c: fc275be7 str d7, \[sp,w7,uxtw #3\]
+ 20: 3ca74be7 str q7, \[sp,w7,uxtw\]
+ 24: 3ca75be7 str q7, \[sp,w7,uxtw #4\]
+ 28: 3c276be7 str b7, \[sp,x7\]
+ 2c: 3c277be7 str b7, \[sp,x7,lsl #0\]
+ 30: 7c276be7 str h7, \[sp,x7\]
+ 34: 7c277be7 str h7, \[sp,x7,lsl #1\]
+ 38: bc276be7 str s7, \[sp,x7\]
+ 3c: bc277be7 str s7, \[sp,x7,lsl #2\]
+ 40: fc276be7 str d7, \[sp,x7\]
+ 44: fc277be7 str d7, \[sp,x7,lsl #3\]
+ 48: 3ca76be7 str q7, \[sp,x7\]
+ 4c: 3ca77be7 str q7, \[sp,x7,lsl #4\]
+ 50: 3c27cbe7 str b7, \[sp,w7,sxtw\]
+ 54: 3c27dbe7 str b7, \[sp,w7,sxtw #0\]
+ 58: 7c27cbe7 str h7, \[sp,w7,sxtw\]
+ 5c: 7c27dbe7 str h7, \[sp,w7,sxtw #1\]
+ 60: bc27cbe7 str s7, \[sp,w7,sxtw\]
+ 64: bc27dbe7 str s7, \[sp,w7,sxtw #2\]
+ 68: fc27cbe7 str d7, \[sp,w7,sxtw\]
+ 6c: fc27dbe7 str d7, \[sp,w7,sxtw #3\]
+ 70: 3ca7cbe7 str q7, \[sp,w7,sxtw\]
+ 74: 3ca7dbe7 str q7, \[sp,w7,sxtw #4\]
+ 78: 3c27ebe7 str b7, \[sp,x7,sxtx\]
+ 7c: 3c27fbe7 str b7, \[sp,x7,sxtx #0\]
+ 80: 7c27ebe7 str h7, \[sp,x7,sxtx\]
+ 84: 7c27fbe7 str h7, \[sp,x7,sxtx #1\]
+ 88: bc27ebe7 str s7, \[sp,x7,sxtx\]
+ 8c: bc27fbe7 str s7, \[sp,x7,sxtx #2\]
+ 90: fc27ebe7 str d7, \[sp,x7,sxtx\]
+ 94: fc27fbe7 str d7, \[sp,x7,sxtx #3\]
+ 98: 3ca7ebe7 str q7, \[sp,x7,sxtx\]
+ 9c: 3ca7fbe7 str q7, \[sp,x7,sxtx #4\]
+ a0: 3c674be7 ldr b7, \[sp,w7,uxtw\]
+ a4: 3c675be7 ldr b7, \[sp,w7,uxtw #0\]
+ a8: 7c674be7 ldr h7, \[sp,w7,uxtw\]
+ ac: 7c675be7 ldr h7, \[sp,w7,uxtw #1\]
+ b0: bc674be7 ldr s7, \[sp,w7,uxtw\]
+ b4: bc675be7 ldr s7, \[sp,w7,uxtw #2\]
+ b8: fc674be7 ldr d7, \[sp,w7,uxtw\]
+ bc: fc675be7 ldr d7, \[sp,w7,uxtw #3\]
+ c0: 3ce74be7 ldr q7, \[sp,w7,uxtw\]
+ c4: 3ce75be7 ldr q7, \[sp,w7,uxtw #4\]
+ c8: 3c676be7 ldr b7, \[sp,x7\]
+ cc: 3c677be7 ldr b7, \[sp,x7,lsl #0\]
+ d0: 7c676be7 ldr h7, \[sp,x7\]
+ d4: 7c677be7 ldr h7, \[sp,x7,lsl #1\]
+ d8: bc676be7 ldr s7, \[sp,x7\]
+ dc: bc677be7 ldr s7, \[sp,x7,lsl #2\]
+ e0: fc676be7 ldr d7, \[sp,x7\]
+ e4: fc677be7 ldr d7, \[sp,x7,lsl #3\]
+ e8: 3ce76be7 ldr q7, \[sp,x7\]
+ ec: 3ce77be7 ldr q7, \[sp,x7,lsl #4\]
+ f0: 3c67cbe7 ldr b7, \[sp,w7,sxtw\]
+ f4: 3c67dbe7 ldr b7, \[sp,w7,sxtw #0\]
+ f8: 7c67cbe7 ldr h7, \[sp,w7,sxtw\]
+ fc: 7c67dbe7 ldr h7, \[sp,w7,sxtw #1\]
+ 100: bc67cbe7 ldr s7, \[sp,w7,sxtw\]
+ 104: bc67dbe7 ldr s7, \[sp,w7,sxtw #2\]
+ 108: fc67cbe7 ldr d7, \[sp,w7,sxtw\]
+ 10c: fc67dbe7 ldr d7, \[sp,w7,sxtw #3\]
+ 110: 3ce7cbe7 ldr q7, \[sp,w7,sxtw\]
+ 114: 3ce7dbe7 ldr q7, \[sp,w7,sxtw #4\]
+ 118: 3c67ebe7 ldr b7, \[sp,x7,sxtx\]
+ 11c: 3c67fbe7 ldr b7, \[sp,x7,sxtx #0\]
+ 120: 7c67ebe7 ldr h7, \[sp,x7,sxtx\]
+ 124: 7c67fbe7 ldr h7, \[sp,x7,sxtx #1\]
+ 128: bc67ebe7 ldr s7, \[sp,x7,sxtx\]
+ 12c: bc67fbe7 ldr s7, \[sp,x7,sxtx #2\]
+ 130: fc67ebe7 ldr d7, \[sp,x7,sxtx\]
+ 134: fc67fbe7 ldr d7, \[sp,x7,sxtx #3\]
+ 138: 3ce7ebe7 ldr q7, \[sp,x7,sxtx\]
+ 13c: 3ce7fbe7 ldr q7, \[sp,x7,sxtx #4\]
--- /dev/null
+/* ldst-reg-reg-offset.s Test file for AArch64 load-store reg. (reg.offset)
+ instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+/* Only instructions loading from/storing to FP/SIMD register are
+ tested here. */
+
+ .macro op3_32 op, reg, ext, imm
+ .ifc \imm, -1
+ \op \reg\()7, [sp, w7, \ext]
+ .else
+ \op \reg\()7, [sp, w7, \ext #\imm]
+ .endif
+ .endm
+
+ .macro op3_64 op, reg, ext, imm
+ .ifc \imm, -1
+ \op \reg\()7, [sp, x7, \ext]
+ .else
+ \op \reg\()7, [sp, x7, \ext #\imm]
+ .endif
+ .endm
+
+ .macro op3 op, reg, ext, imm=-1
+ .ifc \ext, uxtw
+ op3_32 \op, \reg, \ext, \imm
+ .endif
+ .ifc \ext, sxtw
+ op3_32 \op, \reg, \ext, \imm
+ .endif
+ .ifc \ext, lsl
+ .ifnc \imm, -1
+ // shift <amount> is mandatory when 'lsl' is used
+ op3_64 \op, \reg, \ext, \imm
+ .else
+ // absent shift; lsl by default
+ \op \reg\()7, [sp, x7]
+ .endif
+ .endif
+ .ifc \ext, sxtx
+ op3_64 \op, \reg, \ext, \imm
+ .endif
+ .endm
+
+ .macro shift op, ext
+ op3 \op, b, \ext
+ op3 \op, b, \ext, 0
+ op3 \op, h, \ext, 0
+ op3 \op, h, \ext, 1
+ op3 \op, s, \ext, 0
+ op3 \op, s, \ext, 2
+ op3 \op, d, \ext, 0
+ op3 \op, d, \ext, 3
+ op3 \op, q, \ext, 0
+ op3 \op, q, \ext, 4
+ .endm
+
+ .macro extend op
+ .irp ext, uxtw, lsl, sxtw, sxtx
+ shift \op, \ext
+ .endr
+ .endm
+
+ .macro ld_or_st op
+ extend \op
+ .endm
+
+func:
+ ld_or_st str
+ ld_or_st ldr
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 3c1003e7 str b7, \[sp,#-256\]
+ 4: 3c1553e7 str b7, \[sp,#-171\]
+ 8: 3d0003e7 str b7, \[sp\]
+ c: 3d0003e7 str b7, \[sp\]
+ 10: 3d000be7 str b7, \[sp,#2\]
+ 14: 3d0013e7 str b7, \[sp,#4\]
+ 18: 3d0023e7 str b7, \[sp,#8\]
+ 1c: 3d0043e7 str b7, \[sp,#16\]
+ 20: 3d0157e7 str b7, \[sp,#85\]
+ 24: 3d03ffe7 str b7, \[sp,#255\]
+ 28: 3d3fffe7 str b7, \[sp,#4095\]
+ 2c: 7c1003e7 str h7, \[sp,#-256\]
+ 30: 7c1553e7 str h7, \[sp,#-171\]
+ 34: 7d0003e7 str h7, \[sp\]
+ 38: 7d0003e7 str h7, \[sp\]
+ 3c: 7d0007e7 str h7, \[sp,#2\]
+ 40: 7d000be7 str h7, \[sp,#4\]
+ 44: 7d0013e7 str h7, \[sp,#8\]
+ 48: 7d0023e7 str h7, \[sp,#16\]
+ 4c: 7c0553e7 str h7, \[sp,#85\]
+ 50: 7c0ff3e7 str h7, \[sp,#255\]
+ 54: 7d3fffe7 str h7, \[sp,#8190\]
+ 58: bc1003e7 str s7, \[sp,#-256\]
+ 5c: bc1553e7 str s7, \[sp,#-171\]
+ 60: bd0003e7 str s7, \[sp\]
+ 64: bd0003e7 str s7, \[sp\]
+ 68: bc0023e7 str s7, \[sp,#2\]
+ 6c: bd0007e7 str s7, \[sp,#4\]
+ 70: bd000be7 str s7, \[sp,#8\]
+ 74: bd0013e7 str s7, \[sp,#16\]
+ 78: bc0553e7 str s7, \[sp,#85\]
+ 7c: bc0ff3e7 str s7, \[sp,#255\]
+ 80: bd3fffe7 str s7, \[sp,#16380\]
+ 84: fc1003e7 str d7, \[sp,#-256\]
+ 88: fc1553e7 str d7, \[sp,#-171\]
+ 8c: fd0003e7 str d7, \[sp\]
+ 90: fd0003e7 str d7, \[sp\]
+ 94: fc0023e7 str d7, \[sp,#2\]
+ 98: fc0043e7 str d7, \[sp,#4\]
+ 9c: fd0007e7 str d7, \[sp,#8\]
+ a0: fd000be7 str d7, \[sp,#16\]
+ a4: fc0553e7 str d7, \[sp,#85\]
+ a8: fc0ff3e7 str d7, \[sp,#255\]
+ ac: fd3fffe7 str d7, \[sp,#32760\]
+ b0: 3c9003e7 str q7, \[sp,#-256\]
+ b4: 3c9553e7 str q7, \[sp,#-171\]
+ b8: 3d8003e7 str q7, \[sp\]
+ bc: 3d8003e7 str q7, \[sp\]
+ c0: 3c8023e7 str q7, \[sp,#2\]
+ c4: 3c8043e7 str q7, \[sp,#4\]
+ c8: 3c8083e7 str q7, \[sp,#8\]
+ cc: 3d8007e7 str q7, \[sp,#16\]
+ d0: 3c8553e7 str q7, \[sp,#85\]
+ d4: 3c8ff3e7 str q7, \[sp,#255\]
+ d8: 3dbfffe7 str q7, \[sp,#65520\]
+ dc: 3c5003e7 ldr b7, \[sp,#-256\]
+ e0: 3c5553e7 ldr b7, \[sp,#-171\]
+ e4: 3d4003e7 ldr b7, \[sp\]
+ e8: 3d4003e7 ldr b7, \[sp\]
+ ec: 3d400be7 ldr b7, \[sp,#2\]
+ f0: 3d4013e7 ldr b7, \[sp,#4\]
+ f4: 3d4023e7 ldr b7, \[sp,#8\]
+ f8: 3d4043e7 ldr b7, \[sp,#16\]
+ fc: 3d4157e7 ldr b7, \[sp,#85\]
+ 100: 3d43ffe7 ldr b7, \[sp,#255\]
+ 104: 3d7fffe7 ldr b7, \[sp,#4095\]
+ 108: 7c5003e7 ldr h7, \[sp,#-256\]
+ 10c: 7c5553e7 ldr h7, \[sp,#-171\]
+ 110: 7d4003e7 ldr h7, \[sp\]
+ 114: 7d4003e7 ldr h7, \[sp\]
+ 118: 7d4007e7 ldr h7, \[sp,#2\]
+ 11c: 7d400be7 ldr h7, \[sp,#4\]
+ 120: 7d4013e7 ldr h7, \[sp,#8\]
+ 124: 7d4023e7 ldr h7, \[sp,#16\]
+ 128: 7c4553e7 ldr h7, \[sp,#85\]
+ 12c: 7c4ff3e7 ldr h7, \[sp,#255\]
+ 130: 7d7fffe7 ldr h7, \[sp,#8190\]
+ 134: bc5003e7 ldr s7, \[sp,#-256\]
+ 138: bc5553e7 ldr s7, \[sp,#-171\]
+ 13c: bd4003e7 ldr s7, \[sp\]
+ 140: bd4003e7 ldr s7, \[sp\]
+ 144: bc4023e7 ldr s7, \[sp,#2\]
+ 148: bd4007e7 ldr s7, \[sp,#4\]
+ 14c: bd400be7 ldr s7, \[sp,#8\]
+ 150: bd4013e7 ldr s7, \[sp,#16\]
+ 154: bc4553e7 ldr s7, \[sp,#85\]
+ 158: bc4ff3e7 ldr s7, \[sp,#255\]
+ 15c: bd7fffe7 ldr s7, \[sp,#16380\]
+ 160: fc5003e7 ldr d7, \[sp,#-256\]
+ 164: fc5553e7 ldr d7, \[sp,#-171\]
+ 168: fd4003e7 ldr d7, \[sp\]
+ 16c: fd4003e7 ldr d7, \[sp\]
+ 170: fc4023e7 ldr d7, \[sp,#2\]
+ 174: fc4043e7 ldr d7, \[sp,#4\]
+ 178: fd4007e7 ldr d7, \[sp,#8\]
+ 17c: fd400be7 ldr d7, \[sp,#16\]
+ 180: fc4553e7 ldr d7, \[sp,#85\]
+ 184: fc4ff3e7 ldr d7, \[sp,#255\]
+ 188: fd7fffe7 ldr d7, \[sp,#32760\]
+ 18c: 3cd003e7 ldr q7, \[sp,#-256\]
+ 190: 3cd553e7 ldr q7, \[sp,#-171\]
+ 194: 3dc003e7 ldr q7, \[sp\]
+ 198: 3dc003e7 ldr q7, \[sp\]
+ 19c: 3cc023e7 ldr q7, \[sp,#2\]
+ 1a0: 3cc043e7 ldr q7, \[sp,#4\]
+ 1a4: 3cc083e7 ldr q7, \[sp,#8\]
+ 1a8: 3dc007e7 ldr q7, \[sp,#16\]
+ 1ac: 3cc553e7 ldr q7, \[sp,#85\]
+ 1b0: 3ccff3e7 ldr q7, \[sp,#255\]
+ 1b4: 3dffffe7 ldr q7, \[sp,#65520\]
+ 1b8: 381003e7 strb w7, \[sp,#-256\]
+ 1bc: 381553e7 strb w7, \[sp,#-171\]
+ 1c0: 390003e7 strb w7, \[sp\]
+ 1c4: 390003e7 strb w7, \[sp\]
+ 1c8: 39000be7 strb w7, \[sp,#2\]
+ 1cc: 390013e7 strb w7, \[sp,#4\]
+ 1d0: 390023e7 strb w7, \[sp,#8\]
+ 1d4: 390043e7 strb w7, \[sp,#16\]
+ 1d8: 390157e7 strb w7, \[sp,#85\]
+ 1dc: 3903ffe7 strb w7, \[sp,#255\]
+ 1e0: 393fffe7 strb w7, \[sp,#4095\]
+ 1e4: 781003e7 strh w7, \[sp,#-256\]
+ 1e8: 781553e7 strh w7, \[sp,#-171\]
+ 1ec: 790003e7 strh w7, \[sp\]
+ 1f0: 790003e7 strh w7, \[sp\]
+ 1f4: 790007e7 strh w7, \[sp,#2\]
+ 1f8: 79000be7 strh w7, \[sp,#4\]
+ 1fc: 790013e7 strh w7, \[sp,#8\]
+ 200: 790023e7 strh w7, \[sp,#16\]
+ 204: 780553e7 strh w7, \[sp,#85\]
+ 208: 780ff3e7 strh w7, \[sp,#255\]
+ 20c: 793fffe7 strh w7, \[sp,#8190\]
+ 210: b81003e7 str w7, \[sp,#-256\]
+ 214: b81553e7 str w7, \[sp,#-171\]
+ 218: b90003e7 str w7, \[sp\]
+ 21c: b90003e7 str w7, \[sp\]
+ 220: b80023e7 str w7, \[sp,#2\]
+ 224: b90007e7 str w7, \[sp,#4\]
+ 228: b9000be7 str w7, \[sp,#8\]
+ 22c: b90013e7 str w7, \[sp,#16\]
+ 230: b80553e7 str w7, \[sp,#85\]
+ 234: b80ff3e7 str w7, \[sp,#255\]
+ 238: b93fffe7 str w7, \[sp,#16380\]
+ 23c: f81003e7 str x7, \[sp,#-256\]
+ 240: f81553e7 str x7, \[sp,#-171\]
+ 244: f90003e7 str x7, \[sp\]
+ 248: f90003e7 str x7, \[sp\]
+ 24c: f80023e7 str x7, \[sp,#2\]
+ 250: f80043e7 str x7, \[sp,#4\]
+ 254: f90007e7 str x7, \[sp,#8\]
+ 258: f9000be7 str x7, \[sp,#16\]
+ 25c: f80553e7 str x7, \[sp,#85\]
+ 260: f80ff3e7 str x7, \[sp,#255\]
+ 264: f93fffe7 str x7, \[sp,#32760\]
+ 268: 385003e7 ldrb w7, \[sp,#-256\]
+ 26c: 385553e7 ldrb w7, \[sp,#-171\]
+ 270: 394003e7 ldrb w7, \[sp\]
+ 274: 394003e7 ldrb w7, \[sp\]
+ 278: 39400be7 ldrb w7, \[sp,#2\]
+ 27c: 394013e7 ldrb w7, \[sp,#4\]
+ 280: 394023e7 ldrb w7, \[sp,#8\]
+ 284: 394043e7 ldrb w7, \[sp,#16\]
+ 288: 394157e7 ldrb w7, \[sp,#85\]
+ 28c: 3943ffe7 ldrb w7, \[sp,#255\]
+ 290: 397fffe7 ldrb w7, \[sp,#4095\]
+ 294: 785003e7 ldrh w7, \[sp,#-256\]
+ 298: 785553e7 ldrh w7, \[sp,#-171\]
+ 29c: 794003e7 ldrh w7, \[sp\]
+ 2a0: 794003e7 ldrh w7, \[sp\]
+ 2a4: 794007e7 ldrh w7, \[sp,#2\]
+ 2a8: 79400be7 ldrh w7, \[sp,#4\]
+ 2ac: 794013e7 ldrh w7, \[sp,#8\]
+ 2b0: 794023e7 ldrh w7, \[sp,#16\]
+ 2b4: 784553e7 ldrh w7, \[sp,#85\]
+ 2b8: 784ff3e7 ldrh w7, \[sp,#255\]
+ 2bc: 797fffe7 ldrh w7, \[sp,#8190\]
+ 2c0: b85003e7 ldr w7, \[sp,#-256\]
+ 2c4: b85553e7 ldr w7, \[sp,#-171\]
+ 2c8: b94003e7 ldr w7, \[sp\]
+ 2cc: b94003e7 ldr w7, \[sp\]
+ 2d0: b84023e7 ldr w7, \[sp,#2\]
+ 2d4: b94007e7 ldr w7, \[sp,#4\]
+ 2d8: b9400be7 ldr w7, \[sp,#8\]
+ 2dc: b94013e7 ldr w7, \[sp,#16\]
+ 2e0: b84553e7 ldr w7, \[sp,#85\]
+ 2e4: b84ff3e7 ldr w7, \[sp,#255\]
+ 2e8: b97fffe7 ldr w7, \[sp,#16380\]
+ 2ec: f85003e7 ldr x7, \[sp,#-256\]
+ 2f0: f85553e7 ldr x7, \[sp,#-171\]
+ 2f4: f94003e7 ldr x7, \[sp\]
+ 2f8: f94003e7 ldr x7, \[sp\]
+ 2fc: f84023e7 ldr x7, \[sp,#2\]
+ 300: f84043e7 ldr x7, \[sp,#4\]
+ 304: f94007e7 ldr x7, \[sp,#8\]
+ 308: f9400be7 ldr x7, \[sp,#16\]
+ 30c: f84553e7 ldr x7, \[sp,#85\]
+ 310: f84ff3e7 ldr x7, \[sp,#255\]
+ 314: f97fffe7 ldr x7, \[sp,#32760\]
+ 318: 389003e7 ldrsb x7, \[sp,#-256\]
+ 31c: 389553e7 ldrsb x7, \[sp,#-171\]
+ 320: 398003e7 ldrsb x7, \[sp\]
+ 324: 398003e7 ldrsb x7, \[sp\]
+ 328: 39800be7 ldrsb x7, \[sp,#2\]
+ 32c: 398013e7 ldrsb x7, \[sp,#4\]
+ 330: 398023e7 ldrsb x7, \[sp,#8\]
+ 334: 398043e7 ldrsb x7, \[sp,#16\]
+ 338: 398157e7 ldrsb x7, \[sp,#85\]
+ 33c: 3983ffe7 ldrsb x7, \[sp,#255\]
+ 340: 39bfffe7 ldrsb x7, \[sp,#4095\]
+ 344: 789003e7 ldrsh x7, \[sp,#-256\]
+ 348: 789553e7 ldrsh x7, \[sp,#-171\]
+ 34c: 798003e7 ldrsh x7, \[sp\]
+ 350: 798003e7 ldrsh x7, \[sp\]
+ 354: 798007e7 ldrsh x7, \[sp,#2\]
+ 358: 79800be7 ldrsh x7, \[sp,#4\]
+ 35c: 798013e7 ldrsh x7, \[sp,#8\]
+ 360: 798023e7 ldrsh x7, \[sp,#16\]
+ 364: 788553e7 ldrsh x7, \[sp,#85\]
+ 368: 788ff3e7 ldrsh x7, \[sp,#255\]
+ 36c: 79bfffe7 ldrsh x7, \[sp,#8190\]
+ 370: b89003e7 ldrsw x7, \[sp,#-256\]
+ 374: b89553e7 ldrsw x7, \[sp,#-171\]
+ 378: b98003e7 ldrsw x7, \[sp\]
+ 37c: b98003e7 ldrsw x7, \[sp\]
+ 380: b88023e7 ldrsw x7, \[sp,#2\]
+ 384: b98007e7 ldrsw x7, \[sp,#4\]
+ 388: b9800be7 ldrsw x7, \[sp,#8\]
+ 38c: b98013e7 ldrsw x7, \[sp,#16\]
+ 390: b88553e7 ldrsw x7, \[sp,#85\]
+ 394: b88ff3e7 ldrsw x7, \[sp,#255\]
+ 398: b9bfffe7 ldrsw x7, \[sp,#16380\]
+ 39c: 38d003e7 ldrsb w7, \[sp,#-256\]
+ 3a0: 38d553e7 ldrsb w7, \[sp,#-171\]
+ 3a4: 39c003e7 ldrsb w7, \[sp\]
+ 3a8: 39c003e7 ldrsb w7, \[sp\]
+ 3ac: 39c00be7 ldrsb w7, \[sp,#2\]
+ 3b0: 39c013e7 ldrsb w7, \[sp,#4\]
+ 3b4: 39c023e7 ldrsb w7, \[sp,#8\]
+ 3b8: 39c043e7 ldrsb w7, \[sp,#16\]
+ 3bc: 39c157e7 ldrsb w7, \[sp,#85\]
+ 3c0: 39c3ffe7 ldrsb w7, \[sp,#255\]
+ 3c4: 39ffffe7 ldrsb w7, \[sp,#4095\]
+ 3c8: 78d003e7 ldrsh w7, \[sp,#-256\]
+ 3cc: 78d553e7 ldrsh w7, \[sp,#-171\]
+ 3d0: 79c003e7 ldrsh w7, \[sp\]
+ 3d4: 79c003e7 ldrsh w7, \[sp\]
+ 3d8: 79c007e7 ldrsh w7, \[sp,#2\]
+ 3dc: 79c00be7 ldrsh w7, \[sp,#4\]
+ 3e0: 79c013e7 ldrsh w7, \[sp,#8\]
+ 3e4: 79c023e7 ldrsh w7, \[sp,#16\]
+ 3e8: 78c553e7 ldrsh w7, \[sp,#85\]
+ 3ec: 78cff3e7 ldrsh w7, \[sp,#255\]
+ 3f0: 79ffffe7 ldrsh w7, \[sp,#8190\]
--- /dev/null
+/* ld-reg-uns-imm.s Test file for AArch64 load-store reg. (uns.imm)
+ instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+/* Prefetch memory instruction is not tested here.
+
+ Also note that as a programmer-friendly assembler, GAS generates
+ LDUR/STUR instructions in response to the standard LDR/STR mnemonics
+ when the immediate offset is unambiguous, i.e. when it is negative
+ or unaligned. Similarly a disassembler could display these
+ instructions using the standard LDR/STR mnemonics when the encoded
+ immediate is negative or unaligned. However this behaviour is not
+ required by the architectural assembly language. */
+
+ .macro op2_no_imm op, reg
+ \op \reg\()7, [sp]
+ .endm
+
+ .macro op2 op, reg, simm
+ \op \reg\()7, [sp, #\simm]
+ .endm
+
+ // load to or store from core register
+ // size is the access size in byte
+ .macro ld_or_st op, suffix, reg, size
+ .irp simm, -256, -171
+ op2 \op\suffix, \reg, \simm
+ .endr
+ op2_no_imm \op\suffix, \reg
+ .irp simm, 0, 2, 4, 8, 16, 85, 255
+ op2 \op\suffix, \reg, \simm
+ .endr
+ op2 \op\suffix, \reg, "(4095*\size)"
+ .endm
+
+ // load to or store from FP/SIMD register
+ .macro ld_or_st_v op
+ .irp reg, b, h, s, d, q
+ .irp simm, -256, -171
+ op2 \op, \reg, \simm
+ .endr
+ op2_no_imm \op, \reg
+ .irp simm, 0, 2, 4, 8, 16, 85, 255
+ op2 \op, \reg, \simm
+ .endr
+ .ifc \reg, b
+ op2 \op, \reg, 4095
+ .endif
+ .ifc \reg, h
+ op2 \op, \reg, 8190
+ .endif
+ .ifc \reg, s
+ op2 \op, \reg, 16380
+ .endif
+ .ifc \reg, d
+ op2 \op, \reg, 32760
+ .endif
+ .ifc \reg, q
+ op2 \op, \reg, 65520
+ .endif
+ .endr
+ .endm
+
+func:
+ // load to or store from FP/SIMD register
+ ld_or_st_v str
+ ld_or_st_v ldr
+
+ // load to or store from core register
+ // op, suffix, reg, size(in byte)
+ ld_or_st str, b, w, 1
+ ld_or_st str, h, w, 2
+ ld_or_st str, , w, 4
+ ld_or_st str, , x, 8
+ ld_or_st ldr, b, w, 1
+ ld_or_st ldr, h, w, 2
+ ld_or_st ldr, , w, 4
+ ld_or_st ldr, , x, 8
+ ld_or_st ldr, sb, x, 1
+ ld_or_st ldr, sh, x, 2
+ ld_or_st ldr, sw, x, 4
+ ld_or_st ldr, sb, w, 1
+ ld_or_st ldr, sh, w, 2
+
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 3c1003e7 str b7, \[sp,#-256\]
+ 4: 3c1553e7 str b7, \[sp,#-171\]
+ 8: 3c0003e7 stur b7, \[sp\]
+ c: 3c0003e7 stur b7, \[sp\]
+ 10: 3c0023e7 stur b7, \[sp,#2\]
+ 14: 3c0043e7 stur b7, \[sp,#4\]
+ 18: 3c0083e7 stur b7, \[sp,#8\]
+ 1c: 3c0103e7 stur b7, \[sp,#16\]
+ 20: 3c0553e7 stur b7, \[sp,#85\]
+ 24: 3c0ff3e7 stur b7, \[sp,#255\]
+ 28: 7c1003e7 str h7, \[sp,#-256\]
+ 2c: 7c1553e7 str h7, \[sp,#-171\]
+ 30: 7c0003e7 stur h7, \[sp\]
+ 34: 7c0003e7 stur h7, \[sp\]
+ 38: 7c0023e7 stur h7, \[sp,#2\]
+ 3c: 7c0043e7 stur h7, \[sp,#4\]
+ 40: 7c0083e7 stur h7, \[sp,#8\]
+ 44: 7c0103e7 stur h7, \[sp,#16\]
+ 48: 7c0553e7 str h7, \[sp,#85\]
+ 4c: 7c0ff3e7 str h7, \[sp,#255\]
+ 50: bc1003e7 str s7, \[sp,#-256\]
+ 54: bc1553e7 str s7, \[sp,#-171\]
+ 58: bc0003e7 stur s7, \[sp\]
+ 5c: bc0003e7 stur s7, \[sp\]
+ 60: bc0023e7 str s7, \[sp,#2\]
+ 64: bc0043e7 stur s7, \[sp,#4\]
+ 68: bc0083e7 stur s7, \[sp,#8\]
+ 6c: bc0103e7 stur s7, \[sp,#16\]
+ 70: bc0553e7 str s7, \[sp,#85\]
+ 74: bc0ff3e7 str s7, \[sp,#255\]
+ 78: fc1003e7 str d7, \[sp,#-256\]
+ 7c: fc1553e7 str d7, \[sp,#-171\]
+ 80: fc0003e7 stur d7, \[sp\]
+ 84: fc0003e7 stur d7, \[sp\]
+ 88: fc0023e7 str d7, \[sp,#2\]
+ 8c: fc0043e7 str d7, \[sp,#4\]
+ 90: fc0083e7 stur d7, \[sp,#8\]
+ 94: fc0103e7 stur d7, \[sp,#16\]
+ 98: fc0553e7 str d7, \[sp,#85\]
+ 9c: fc0ff3e7 str d7, \[sp,#255\]
+ a0: 3c9003e7 str q7, \[sp,#-256\]
+ a4: 3c9553e7 str q7, \[sp,#-171\]
+ a8: 3c8003e7 stur q7, \[sp\]
+ ac: 3c8003e7 stur q7, \[sp\]
+ b0: 3c8023e7 str q7, \[sp,#2\]
+ b4: 3c8043e7 str q7, \[sp,#4\]
+ b8: 3c8083e7 str q7, \[sp,#8\]
+ bc: 3c8103e7 stur q7, \[sp,#16\]
+ c0: 3c8553e7 str q7, \[sp,#85\]
+ c4: 3c8ff3e7 str q7, \[sp,#255\]
+ c8: 3c5003e7 ldr b7, \[sp,#-256\]
+ cc: 3c5553e7 ldr b7, \[sp,#-171\]
+ d0: 3c4003e7 ldur b7, \[sp\]
+ d4: 3c4003e7 ldur b7, \[sp\]
+ d8: 3c4023e7 ldur b7, \[sp,#2\]
+ dc: 3c4043e7 ldur b7, \[sp,#4\]
+ e0: 3c4083e7 ldur b7, \[sp,#8\]
+ e4: 3c4103e7 ldur b7, \[sp,#16\]
+ e8: 3c4553e7 ldur b7, \[sp,#85\]
+ ec: 3c4ff3e7 ldur b7, \[sp,#255\]
+ f0: 7c5003e7 ldr h7, \[sp,#-256\]
+ f4: 7c5553e7 ldr h7, \[sp,#-171\]
+ f8: 7c4003e7 ldur h7, \[sp\]
+ fc: 7c4003e7 ldur h7, \[sp\]
+ 100: 7c4023e7 ldur h7, \[sp,#2\]
+ 104: 7c4043e7 ldur h7, \[sp,#4\]
+ 108: 7c4083e7 ldur h7, \[sp,#8\]
+ 10c: 7c4103e7 ldur h7, \[sp,#16\]
+ 110: 7c4553e7 ldr h7, \[sp,#85\]
+ 114: 7c4ff3e7 ldr h7, \[sp,#255\]
+ 118: bc5003e7 ldr s7, \[sp,#-256\]
+ 11c: bc5553e7 ldr s7, \[sp,#-171\]
+ 120: bc4003e7 ldur s7, \[sp\]
+ 124: bc4003e7 ldur s7, \[sp\]
+ 128: bc4023e7 ldr s7, \[sp,#2\]
+ 12c: bc4043e7 ldur s7, \[sp,#4\]
+ 130: bc4083e7 ldur s7, \[sp,#8\]
+ 134: bc4103e7 ldur s7, \[sp,#16\]
+ 138: bc4553e7 ldr s7, \[sp,#85\]
+ 13c: bc4ff3e7 ldr s7, \[sp,#255\]
+ 140: fc5003e7 ldr d7, \[sp,#-256\]
+ 144: fc5553e7 ldr d7, \[sp,#-171\]
+ 148: fc4003e7 ldur d7, \[sp\]
+ 14c: fc4003e7 ldur d7, \[sp\]
+ 150: fc4023e7 ldr d7, \[sp,#2\]
+ 154: fc4043e7 ldr d7, \[sp,#4\]
+ 158: fc4083e7 ldur d7, \[sp,#8\]
+ 15c: fc4103e7 ldur d7, \[sp,#16\]
+ 160: fc4553e7 ldr d7, \[sp,#85\]
+ 164: fc4ff3e7 ldr d7, \[sp,#255\]
+ 168: 3cd003e7 ldr q7, \[sp,#-256\]
+ 16c: 3cd553e7 ldr q7, \[sp,#-171\]
+ 170: 3cc003e7 ldur q7, \[sp\]
+ 174: 3cc003e7 ldur q7, \[sp\]
+ 178: 3cc023e7 ldr q7, \[sp,#2\]
+ 17c: 3cc043e7 ldr q7, \[sp,#4\]
+ 180: 3cc083e7 ldr q7, \[sp,#8\]
+ 184: 3cc103e7 ldur q7, \[sp,#16\]
+ 188: 3cc553e7 ldr q7, \[sp,#85\]
+ 18c: 3ccff3e7 ldr q7, \[sp,#255\]
+ 190: 381003e7 strb w7, \[sp,#-256\]
+ 194: 381553e7 strb w7, \[sp,#-171\]
+ 198: 380003e7 sturb w7, \[sp\]
+ 19c: 380003e7 sturb w7, \[sp\]
+ 1a0: 380023e7 sturb w7, \[sp,#2\]
+ 1a4: 380043e7 sturb w7, \[sp,#4\]
+ 1a8: 380083e7 sturb w7, \[sp,#8\]
+ 1ac: 380103e7 sturb w7, \[sp,#16\]
+ 1b0: 380553e7 sturb w7, \[sp,#85\]
+ 1b4: 380ff3e7 sturb w7, \[sp,#255\]
+ 1b8: 781003e7 strh w7, \[sp,#-256\]
+ 1bc: 781553e7 strh w7, \[sp,#-171\]
+ 1c0: 780003e7 sturh w7, \[sp\]
+ 1c4: 780003e7 sturh w7, \[sp\]
+ 1c8: 780023e7 sturh w7, \[sp,#2\]
+ 1cc: 780043e7 sturh w7, \[sp,#4\]
+ 1d0: 780083e7 sturh w7, \[sp,#8\]
+ 1d4: 780103e7 sturh w7, \[sp,#16\]
+ 1d8: 780553e7 strh w7, \[sp,#85\]
+ 1dc: 780ff3e7 strh w7, \[sp,#255\]
+ 1e0: b81003e7 str w7, \[sp,#-256\]
+ 1e4: b81553e7 str w7, \[sp,#-171\]
+ 1e8: b80003e7 stur w7, \[sp\]
+ 1ec: b80003e7 stur w7, \[sp\]
+ 1f0: b80023e7 str w7, \[sp,#2\]
+ 1f4: b80043e7 stur w7, \[sp,#4\]
+ 1f8: b80083e7 stur w7, \[sp,#8\]
+ 1fc: b80103e7 stur w7, \[sp,#16\]
+ 200: b80553e7 str w7, \[sp,#85\]
+ 204: b80ff3e7 str w7, \[sp,#255\]
+ 208: f81003e7 str x7, \[sp,#-256\]
+ 20c: f81553e7 str x7, \[sp,#-171\]
+ 210: f80003e7 stur x7, \[sp\]
+ 214: f80003e7 stur x7, \[sp\]
+ 218: f80023e7 str x7, \[sp,#2\]
+ 21c: f80043e7 str x7, \[sp,#4\]
+ 220: f80083e7 stur x7, \[sp,#8\]
+ 224: f80103e7 stur x7, \[sp,#16\]
+ 228: f80553e7 str x7, \[sp,#85\]
+ 22c: f80ff3e7 str x7, \[sp,#255\]
+ 230: 385003e7 ldrb w7, \[sp,#-256\]
+ 234: 385553e7 ldrb w7, \[sp,#-171\]
+ 238: 384003e7 ldurb w7, \[sp\]
+ 23c: 384003e7 ldurb w7, \[sp\]
+ 240: 384023e7 ldurb w7, \[sp,#2\]
+ 244: 384043e7 ldurb w7, \[sp,#4\]
+ 248: 384083e7 ldurb w7, \[sp,#8\]
+ 24c: 384103e7 ldurb w7, \[sp,#16\]
+ 250: 384553e7 ldurb w7, \[sp,#85\]
+ 254: 384ff3e7 ldurb w7, \[sp,#255\]
+ 258: 785003e7 ldrh w7, \[sp,#-256\]
+ 25c: 785553e7 ldrh w7, \[sp,#-171\]
+ 260: 784003e7 ldurh w7, \[sp\]
+ 264: 784003e7 ldurh w7, \[sp\]
+ 268: 784023e7 ldurh w7, \[sp,#2\]
+ 26c: 784043e7 ldurh w7, \[sp,#4\]
+ 270: 784083e7 ldurh w7, \[sp,#8\]
+ 274: 784103e7 ldurh w7, \[sp,#16\]
+ 278: 784553e7 ldrh w7, \[sp,#85\]
+ 27c: 784ff3e7 ldrh w7, \[sp,#255\]
+ 280: b85003e7 ldr w7, \[sp,#-256\]
+ 284: b85553e7 ldr w7, \[sp,#-171\]
+ 288: b84003e7 ldur w7, \[sp\]
+ 28c: b84003e7 ldur w7, \[sp\]
+ 290: b84023e7 ldr w7, \[sp,#2\]
+ 294: b84043e7 ldur w7, \[sp,#4\]
+ 298: b84083e7 ldur w7, \[sp,#8\]
+ 29c: b84103e7 ldur w7, \[sp,#16\]
+ 2a0: b84553e7 ldr w7, \[sp,#85\]
+ 2a4: b84ff3e7 ldr w7, \[sp,#255\]
+ 2a8: f85003e7 ldr x7, \[sp,#-256\]
+ 2ac: f85553e7 ldr x7, \[sp,#-171\]
+ 2b0: f84003e7 ldur x7, \[sp\]
+ 2b4: f84003e7 ldur x7, \[sp\]
+ 2b8: f84023e7 ldr x7, \[sp,#2\]
+ 2bc: f84043e7 ldr x7, \[sp,#4\]
+ 2c0: f84083e7 ldur x7, \[sp,#8\]
+ 2c4: f84103e7 ldur x7, \[sp,#16\]
+ 2c8: f84553e7 ldr x7, \[sp,#85\]
+ 2cc: f84ff3e7 ldr x7, \[sp,#255\]
+ 2d0: 389003e7 ldrsb x7, \[sp,#-256\]
+ 2d4: 389553e7 ldrsb x7, \[sp,#-171\]
+ 2d8: 388003e7 ldursb x7, \[sp\]
+ 2dc: 388003e7 ldursb x7, \[sp\]
+ 2e0: 388023e7 ldursb x7, \[sp,#2\]
+ 2e4: 388043e7 ldursb x7, \[sp,#4\]
+ 2e8: 388083e7 ldursb x7, \[sp,#8\]
+ 2ec: 388103e7 ldursb x7, \[sp,#16\]
+ 2f0: 388553e7 ldursb x7, \[sp,#85\]
+ 2f4: 388ff3e7 ldursb x7, \[sp,#255\]
+ 2f8: 789003e7 ldrsh x7, \[sp,#-256\]
+ 2fc: 789553e7 ldrsh x7, \[sp,#-171\]
+ 300: 788003e7 ldursh x7, \[sp\]
+ 304: 788003e7 ldursh x7, \[sp\]
+ 308: 788023e7 ldursh x7, \[sp,#2\]
+ 30c: 788043e7 ldursh x7, \[sp,#4\]
+ 310: 788083e7 ldursh x7, \[sp,#8\]
+ 314: 788103e7 ldursh x7, \[sp,#16\]
+ 318: 788553e7 ldrsh x7, \[sp,#85\]
+ 31c: 788ff3e7 ldrsh x7, \[sp,#255\]
+ 320: b89003e7 ldrsw x7, \[sp,#-256\]
+ 324: b89553e7 ldrsw x7, \[sp,#-171\]
+ 328: b88003e7 ldursw x7, \[sp\]
+ 32c: b88003e7 ldursw x7, \[sp\]
+ 330: b88023e7 ldrsw x7, \[sp,#2\]
+ 334: b88043e7 ldursw x7, \[sp,#4\]
+ 338: b88083e7 ldursw x7, \[sp,#8\]
+ 33c: b88103e7 ldursw x7, \[sp,#16\]
+ 340: b88553e7 ldrsw x7, \[sp,#85\]
+ 344: b88ff3e7 ldrsw x7, \[sp,#255\]
+ 348: 38d003e7 ldrsb w7, \[sp,#-256\]
+ 34c: 38d553e7 ldrsb w7, \[sp,#-171\]
+ 350: 38c003e7 ldursb w7, \[sp\]
+ 354: 38c003e7 ldursb w7, \[sp\]
+ 358: 38c023e7 ldursb w7, \[sp,#2\]
+ 35c: 38c043e7 ldursb w7, \[sp,#4\]
+ 360: 38c083e7 ldursb w7, \[sp,#8\]
+ 364: 38c103e7 ldursb w7, \[sp,#16\]
+ 368: 38c553e7 ldursb w7, \[sp,#85\]
+ 36c: 38cff3e7 ldursb w7, \[sp,#255\]
+ 370: 78d003e7 ldrsh w7, \[sp,#-256\]
+ 374: 78d553e7 ldrsh w7, \[sp,#-171\]
+ 378: 78c003e7 ldursh w7, \[sp\]
+ 37c: 78c003e7 ldursh w7, \[sp\]
+ 380: 78c023e7 ldursh w7, \[sp,#2\]
+ 384: 78c043e7 ldursh w7, \[sp,#4\]
+ 388: 78c083e7 ldursh w7, \[sp,#8\]
+ 38c: 78c103e7 ldursh w7, \[sp,#16\]
+ 390: 78c553e7 ldrsh w7, \[sp,#85\]
+ 394: 78cff3e7 ldrsh w7, \[sp,#255\]
--- /dev/null
+/* ldst-reg-unscaled-imm.s Test file for AArch64
+ load-store reg. (unscaled imm.) instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+
+/* Prefetch memory instruction is not tested here.
+
+ Also note that a programmer-friendly disassembler could display
+ LDUR/STUR instructions using the standard LDR/STR mnemonics when
+ the encoded immediate is negative or unaligned. However this behaviour
+ is not required by the architectural assembly language. */
+
+ .macro op2_no_imm op, reg
+ \op \reg\()7, [sp]
+ .endm
+
+ .macro op2 op, reg, simm
+ \op \reg\()7, [sp, #\simm]
+ .endm
+
+ // load to or store from core register
+ .macro ld_or_st op, suffix, reg
+ .irp simm, -256, -171
+ op2 \op\suffix, \reg, \simm
+ .endr
+ op2_no_imm \op\suffix, \reg
+ .irp simm, 0, 2, 4, 8, 16, 85, 255
+ op2 \op\suffix, \reg, \simm
+ .endr
+ .endm
+
+ // load to or store from FP/SIMD register
+ .macro ld_or_st_v op
+ .irp reg, b, h, s, d, q
+ .irp simm, -256, -171
+ op2 \op, \reg, \simm
+ .endr
+ op2_no_imm \op, \reg
+ .irp simm, 0, 2, 4, 8, 16, 85, 255
+ op2 \op, \reg, \simm
+ .endr
+ .endr
+ .endm
+
+func:
+ // load to or store from FP/SIMD register
+ ld_or_st_v stur
+ ld_or_st_v ldur
+
+ // load to or store from core register
+ // op, suffix, reg
+ ld_or_st stur, b, w
+ ld_or_st stur, h, w
+ ld_or_st stur, , w
+ ld_or_st stur, , x
+ ld_or_st ldur, b, w
+ ld_or_st ldur, h, w
+ ld_or_st ldur, , w
+ ld_or_st ldur, , x
+ ld_or_st ldur, sb, x
+ ld_or_st ldur, sh, x
+ ld_or_st ldur, sw, x
+ ld_or_st ldur, sb, w
+ ld_or_st ldur, sh, w
--- /dev/null
+#name: Legacy register names errors
+#error-output: legacy_reg_names.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: indexed vector register expected at operand 1 -- `dup v0.b,v1.b\[7\]'
+[^:]*:6: Error: operand 1 should be an integer register -- `mov r0.w,r1.w'
+[^:]*:7: Error: operand 2 should be a SIMD vector element -- `dup s0,s1\[3\]'
--- /dev/null
+
+ .text
+ .arch armv8
+
+ dup v0.b, v1.b[7]
+ mov r0.w, r1.w
+ dup s0, s1[3]
--- /dev/null
+#as: -EL -I$srcdir/$subdir
+#objdump: --syms --special-syms -d
+#name: AArch64 Mapping Symbols for miscellaneous directives
+#source: mapmisc.s
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+
+.*: +file format .*aarch64.*
+
+SYMBOL TABLE:
+0+00 l d .text 0000000000000000 .text
+0+00 l d .data 0000000000000000 .data
+0+00 l d .bss 0000000000000000 .bss
+0+00 l F .text 0000000000000000 foo
+0+00 l .text 0000000000000000 \$x
+0+04 l .text 0000000000000000 \$d
+0+08 l .text 0000000000000000 \$x
+0+0c l .text 0000000000000000 \$d
+0+10 l .text 0000000000000000 \$x
+0+14 l .text 0000000000000000 \$d
+0+18 l .text 0000000000000000 \$x
+0+1c l .text 0000000000000000 \$d
+0+20 l .text 0000000000000000 \$x
+0+24 l .text 0000000000000000 \$d
+0+28 l .text 0000000000000000 \$x
+0+2c l .text 0000000000000000 \$d
+0+34 l .text 0000000000000000 \$x
+0+38 l .text 0000000000000000 \$d
+0+48 l .text 0000000000000000 \$x
+0+4c l .text 0000000000000000 \$d
+0+50 l .text 0000000000000000 \$x
+0+54 l .text 0000000000000000 \$d
+0+58 l .text 0000000000000000 \$x
+0+5c l .text 0000000000000000 \$d
+0+64 l .text 0000000000000000 \$x
+0+68 l .text 0000000000000000 \$d
+0+70 l .text 0000000000000000 \$x
+0+74 l .text 0000000000000000 \$d
+0+84 l .text 0000000000000000 \$x
+0+88 l .text 0000000000000000 \$d
+0+8c l .text 0000000000000000 \$x
+0+90 l .text 0000000000000000 \$d
+0+94 l .text 0000000000000000 \$x
+0+98 l .text 0000000000000000 \$d
+0+9c l .text 0000000000000000 \$x
+0+a0 l .text 0000000000000000 \$d
+0+a4 l .text 0000000000000000 \$x
+0+a8 l .text 0000000000000000 \$x
+
+
+
+Disassembly of section .text:
+
+0000000000000000 <foo>:
+ 0: d503201f nop
+ 4: 64636261 .word 0x64636261
+ 8: d503201f nop
+ c: 00636261 .word 0x00636261
+ 10: d503201f nop
+ 14: 00676665 .word 0x00676665
+ 18: d503201f nop
+ 1c: 006a6968 .word 0x006a6968
+ 20: d503201f nop
+ 24: 0000006b .word 0x0000006b
+ 28: d503201f nop
+ 2c: 0000006c .word 0x0000006c
+ 30: 00000000 .word 0x00000000
+ 34: d503201f nop
+ 38: 0000006d .word 0x0000006d
+ ...
+ 48: d503201f nop
+ 4c: 3fc00000 .word 0x3fc00000
+ 50: d503201f nop
+ 54: 40200000 .word 0x40200000
+ 58: d503201f nop
+ 5c: 00000000 .word 0x00000000
+ 60: 400c0000 .word 0x400c0000
+ 64: d503201f nop
+ 68: 00000000 .word 0x00000000
+ 6c: 40120000 .word 0x40120000
+ 70: d503201f nop
+ 74: 00000004 .word 0x00000004
+ 78: 00000004 .word 0x00000004
+ 7c: 00000004 .word 0x00000004
+ 80: 00000004 .word 0x00000004
+ 84: d503201f nop
+ 88: 00000000 .word 0x00000000
+ 8c: d503201f nop
+ 90: 00000000 .word 0x00000000
+ 94: d503201f nop
+ 98: 00000000 .word 0x00000000
+ 9c: d503201f nop
+ a0: 7778797a .word 0x7778797a
+ a4: d503201f nop
+ a8: d503201f nop
--- /dev/null
+zyxw
\ No newline at end of file
--- /dev/null
+ .text
+ .type foo, %function
+foo:
+ .align 2
+ .fill 0, 0, 0
+ nop
+ .ascii "abcd"
+ nop
+ .asciz "abc"
+ nop
+ .string "efg"
+ nop
+ .string8 "hij"
+ nop
+ .string16 "k"
+ nop
+ .string32 "l"
+ nop
+ .string64 "m"
+ nop
+ .float 0e1.5
+ nop
+ .single 0e2.5
+ nop
+ .double 0e3.5
+ nop
+ .dcb.d 1, 4.5
+ nop
+ .fill 4, 4, 4
+ nop
+ .space 4
+ nop
+ .skip 4
+ nop
+ .zero 4
+ nop
+ .incbin "mapmisc.dat"
+ nop
+ .fill 0, 0, 0
+ nop
--- /dev/null
+#objdump: --syms --special-syms
+#name: AArch64 Mapping Symbols
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+# Test the generation of AArch64 ELF Mapping Symbols
+
+.*: +file format.*aarch64.*
+
+SYMBOL TABLE:
+0+00 l d .text 0+0 (|.text)
+0+00 l d .data 0+0 (|.data)
+0+00 l d .bss 0+0 (|.bss)
+0+00 l .text 0+0 \$x
+0+00 l d foo 0+0 (|foo)
+0+00 l foo 0+0 \$x
+#Maybe section symbol for .ARM.attributes
+#...
+0+00 g .text 0+0 mapping
+0+08 g .text 0+0 another_mapping
--- /dev/null
+ .text
+ .global mapping
+mapping:
+ nop
+ bl mapping
+
+ .global another_mapping
+another_mapping:
+ nop
+ bl another_mapping
+
+ .data
+ .word 0x123456
+
+ .section foo,"ax"
+ nop
--- /dev/null
+#objdump: --syms --special-syms
+#name: AArch64 Mapping Symbols Test 2
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*: +file format.*aarch64.*
+
+SYMBOL TABLE:
+[0]+00 l d .text 0[0]+00 .text
+[0]+00 l d .data 0[0]+00 .data
+[0]+00 l d .bss 0[0]+00 .bss
+[0]+00 l .text 0[0]+00 \$x
+[0]+04 l .text 0[0]+00 foo
+[0]+00 l d .comment 0[0]+00 .comment
+[0]+00 g F .text 0[0]+0c main
+
+
--- /dev/null
+ .text
+ .align 2
+ .global main
+ .type main, %function
+main:
+ nop
+foo:
+ nop
+ nop
+ .size main, .-main
+ .ident ""
+
+ nop
--- /dev/null
+#objdump: --syms --special-syms
+#name: AArch64 Mapping Symbols Test 3
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*: +file format.*aarch64.*
+
+SYMBOL TABLE:
+0[0]+00 l d .text 0[0]+00 .text
+0[0]+00 l d .data 0[0]+00 .data
+0[0]+00 l d .bss 0[0]+00 .bss
+0[0]+00 l .text 0[0]+00 \$d
+0[0]+04 l .text 0[0]+00 \$x
+
+
--- /dev/null
+.text
+.word 0
+ nop
--- /dev/null
+#objdump: --syms --special-syms
+#name: AArch64 Mapping Symbols Test 4
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*: +file format.*aarch64.*
+
+SYMBOL TABLE:
+0[0]+00 l d .text 0[0]+00 .text
+0[0]+00 l d .data 0[0]+00 .data
+0[0]+00 l d .bss 0[0]+00 .bss
+0[0]+00 l .text 0[0]+00 \$x
+
+
--- /dev/null
+ .text
+ nop
+ .data
+ .word 0
+ .text
+ nop
+
--- /dev/null
+#source: mov.s
+#objdump: -dr -Mno-aliases
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 110003ef add w15, wsp, #0x0
+ 4: 910003ef add x15, sp, #0x0
+ 8: 110000ff add wsp, w7, #0x0
+ c: 910000ff add sp, x7, #0x0
+ 10: 110003ff add wsp, wsp, #0x0
+ 14: 910003ff add sp, sp, #0x0
+ 18: aa0f03e7 orr x7, xzr, x15
+ 1c: 2a0f03e7 orr w7, wzr, w15
+ 20: 52800b01 movz w1, #0x58
+ 24: 12800000 movn w0, #0x0
+ 28: b2607fe0 orr x0, xzr, #0xffffffff00000000
+ 2c: b2400fff orr sp, xzr, #0xf
+ 30: 32000fff orr wsp, wzr, #0xf
+ 34: d28001ff movz xzr, #0xf
+ 38: 528001ff movz wzr, #0xf
+ 3c: 0e1c3de7 umov w7, v15\.s\[3\]
+ 40: 4e183fef umov x15, v31\.d\[1\]
+ 44: d2801fe0 movz x0, #0xff
+ 48: 320de400 orr w0, w0, #0x99999999
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 110003ef mov w15, wsp
+ 4: 910003ef mov x15, sp
+ 8: 110000ff mov wsp, w7
+ c: 910000ff mov sp, x7
+ 10: 110003ff mov wsp, wsp
+ 14: 910003ff mov sp, sp
+ 18: aa0f03e7 mov x7, x15
+ 1c: 2a0f03e7 mov w7, w15
+ 20: 52800b01 movz w1, #0x58
+ 24: 12800000 movn w0, #0x0
+ 28: b2607fe0 orr x0, xzr, #0xffffffff00000000
+ 2c: b2400fff orr sp, xzr, #0xf
+ 30: 32000fff orr wsp, wzr, #0xf
+ 34: d28001ff movz xzr, #0xf
+ 38: 528001ff movz wzr, #0xf
+ 3c: 0e1c3de7 mov w7, v15\.s\[3\]
+ 40: 4e183fef mov x15, v31\.d\[1\]
+ 44: d2801fe0 movz x0, #0xff
+ 48: 320de400 orr w0, w0, #0x99999999
--- /dev/null
+// mov.s Test file for AArch64 mov aliases.
+// This test file is also used for the mov-no-aliases test.
+
+ .text
+
+ // MOV/xr Xd|SP, Xn|SP
+ // Move (extended register) is an alias for ADD/xi Xd,Xn,#0, but
+ // only when one or other of the registers is SP. In other cases
+ // the ORR/xr Xd,#0,Xn instruction will be used.
+
+ mov w15, wsp
+ mov x15, sp
+ mov wsp, w7
+ mov sp, x7
+ mov wsp, wsp
+ mov sp, sp
+
+ mov x7, x15
+ mov w7, w15
+
+ mov w1, 88
+ mov w0, -1
+
+ mov x0, -4294967296
+
+ mov sp, #15
+ mov wsp, #15
+ mov xzr, #15
+ mov wzr, #15
+
+ mov w7, v15.s[3]
+ mov x15, v31.d[1]
+
+ mov x0, $$5
+.set $$5, 0xff
+
+ // ORR w0,w0,#0x99999999 with a non-standard encoding, i.e. the top
+ // 4 bits in the 'immr' field is non-zero. The top bits are ignored
+ // during the decoding.
+ .inst 0x320de400
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 2f00e41f movi d31, #0x0
+ 4: 2f00e43f movi d31, #0xff
+ 8: 2f00e45f movi d31, #0xff00
+ c: 2f00e47f movi d31, #0xffff
+ 10: 2f00e49f movi d31, #0xff0000
+ 14: 2f00e4bf movi d31, #0xff00ff
+ 18: 2f00e4df movi d31, #0xffff00
+ 1c: 2f00e4ff movi d31, #0xffffff
+ 20: 2f00e51f movi d31, #0xff000000
+ 24: 2f00e53f movi d31, #0xff0000ff
+ 28: 2f00e55f movi d31, #0xff00ff00
+ 2c: 2f00e57f movi d31, #0xff00ffff
+ 30: 2f00e59f movi d31, #0xffff0000
+ 34: 2f00e5bf movi d31, #0xffff00ff
+ 38: 2f00e5df movi d31, #0xffffff00
+ 3c: 2f00e5ff movi d31, #0xffffffff
+ 40: 2f00e61f movi d31, #0xff00000000
+ 44: 2f00e63f movi d31, #0xff000000ff
+ 48: 2f00e65f movi d31, #0xff0000ff00
+ 4c: 2f00e67f movi d31, #0xff0000ffff
+ 50: 2f00e69f movi d31, #0xff00ff0000
+ 54: 2f00e6bf movi d31, #0xff00ff00ff
+ 58: 2f00e6df movi d31, #0xff00ffff00
+ 5c: 2f00e6ff movi d31, #0xff00ffffff
+ 60: 2f00e71f movi d31, #0xffff000000
+ 64: 2f00e73f movi d31, #0xffff0000ff
+ 68: 2f00e75f movi d31, #0xffff00ff00
+ 6c: 2f00e77f movi d31, #0xffff00ffff
+ 70: 2f00e79f movi d31, #0xffffff0000
+ 74: 2f00e7bf movi d31, #0xffffff00ff
+ 78: 2f00e7df movi d31, #0xffffffff00
+ 7c: 2f00e7ff movi d31, #0xffffffffff
+ 80: 2f01e41f movi d31, #0xff0000000000
+ 84: 2f01e43f movi d31, #0xff00000000ff
+ 88: 2f01e45f movi d31, #0xff000000ff00
+ 8c: 2f01e47f movi d31, #0xff000000ffff
+ 90: 2f01e49f movi d31, #0xff0000ff0000
+ 94: 2f01e4bf movi d31, #0xff0000ff00ff
+ 98: 2f01e4df movi d31, #0xff0000ffff00
+ 9c: 2f01e4ff movi d31, #0xff0000ffffff
+ a0: 2f01e51f movi d31, #0xff00ff000000
+ a4: 2f01e53f movi d31, #0xff00ff0000ff
+ a8: 2f01e55f movi d31, #0xff00ff00ff00
+ ac: 2f01e57f movi d31, #0xff00ff00ffff
+ b0: 2f01e59f movi d31, #0xff00ffff0000
+ b4: 2f01e5bf movi d31, #0xff00ffff00ff
+ b8: 2f01e5df movi d31, #0xff00ffffff00
+ bc: 2f01e5ff movi d31, #0xff00ffffffff
+ c0: 2f01e61f movi d31, #0xffff00000000
+ c4: 2f01e63f movi d31, #0xffff000000ff
+ c8: 2f01e65f movi d31, #0xffff0000ff00
+ cc: 2f01e67f movi d31, #0xffff0000ffff
+ d0: 2f01e69f movi d31, #0xffff00ff0000
+ d4: 2f01e6bf movi d31, #0xffff00ff00ff
+ d8: 2f01e6df movi d31, #0xffff00ffff00
+ dc: 2f01e6ff movi d31, #0xffff00ffffff
+ e0: 2f01e71f movi d31, #0xffffff000000
+ e4: 2f01e73f movi d31, #0xffffff0000ff
+ e8: 2f01e75f movi d31, #0xffffff00ff00
+ ec: 2f01e77f movi d31, #0xffffff00ffff
+ f0: 2f01e79f movi d31, #0xffffffff0000
+ f4: 2f01e7bf movi d31, #0xffffffff00ff
+ f8: 2f01e7df movi d31, #0xffffffffff00
+ fc: 2f01e7ff movi d31, #0xffffffffffff
+ 100: 2f02e41f movi d31, #0xff000000000000
+ 104: 2f02e43f movi d31, #0xff0000000000ff
+ 108: 2f02e45f movi d31, #0xff00000000ff00
+ 10c: 2f02e47f movi d31, #0xff00000000ffff
+ 110: 2f02e49f movi d31, #0xff000000ff0000
+ 114: 2f02e4bf movi d31, #0xff000000ff00ff
+ 118: 2f02e4df movi d31, #0xff000000ffff00
+ 11c: 2f02e4ff movi d31, #0xff000000ffffff
+ 120: 2f02e51f movi d31, #0xff0000ff000000
+ 124: 2f02e53f movi d31, #0xff0000ff0000ff
+ 128: 2f02e55f movi d31, #0xff0000ff00ff00
+ 12c: 2f02e57f movi d31, #0xff0000ff00ffff
+ 130: 2f02e59f movi d31, #0xff0000ffff0000
+ 134: 2f02e5bf movi d31, #0xff0000ffff00ff
+ 138: 2f02e5df movi d31, #0xff0000ffffff00
+ 13c: 2f02e5ff movi d31, #0xff0000ffffffff
+ 140: 2f02e61f movi d31, #0xff00ff00000000
+ 144: 2f02e63f movi d31, #0xff00ff000000ff
+ 148: 2f02e65f movi d31, #0xff00ff0000ff00
+ 14c: 2f02e67f movi d31, #0xff00ff0000ffff
+ 150: 2f02e69f movi d31, #0xff00ff00ff0000
+ 154: 2f02e6bf movi d31, #0xff00ff00ff00ff
+ 158: 2f02e6df movi d31, #0xff00ff00ffff00
+ 15c: 2f02e6ff movi d31, #0xff00ff00ffffff
+ 160: 2f02e71f movi d31, #0xff00ffff000000
+ 164: 2f02e73f movi d31, #0xff00ffff0000ff
+ 168: 2f02e75f movi d31, #0xff00ffff00ff00
+ 16c: 2f02e77f movi d31, #0xff00ffff00ffff
+ 170: 2f02e79f movi d31, #0xff00ffffff0000
+ 174: 2f02e7bf movi d31, #0xff00ffffff00ff
+ 178: 2f02e7df movi d31, #0xff00ffffffff00
+ 17c: 2f02e7ff movi d31, #0xff00ffffffffff
+ 180: 2f03e41f movi d31, #0xffff0000000000
+ 184: 2f03e43f movi d31, #0xffff00000000ff
+ 188: 2f03e45f movi d31, #0xffff000000ff00
+ 18c: 2f03e47f movi d31, #0xffff000000ffff
+ 190: 2f03e49f movi d31, #0xffff0000ff0000
+ 194: 2f03e4bf movi d31, #0xffff0000ff00ff
+ 198: 2f03e4df movi d31, #0xffff0000ffff00
+ 19c: 2f03e4ff movi d31, #0xffff0000ffffff
+ 1a0: 2f03e51f movi d31, #0xffff00ff000000
+ 1a4: 2f03e53f movi d31, #0xffff00ff0000ff
+ 1a8: 2f03e55f movi d31, #0xffff00ff00ff00
+ 1ac: 2f03e57f movi d31, #0xffff00ff00ffff
+ 1b0: 2f03e59f movi d31, #0xffff00ffff0000
+ 1b4: 2f03e5bf movi d31, #0xffff00ffff00ff
+ 1b8: 2f03e5df movi d31, #0xffff00ffffff00
+ 1bc: 2f03e5ff movi d31, #0xffff00ffffffff
+ 1c0: 2f03e61f movi d31, #0xffffff00000000
+ 1c4: 2f03e63f movi d31, #0xffffff000000ff
+ 1c8: 2f03e65f movi d31, #0xffffff0000ff00
+ 1cc: 2f03e67f movi d31, #0xffffff0000ffff
+ 1d0: 2f03e69f movi d31, #0xffffff00ff0000
+ 1d4: 2f03e6bf movi d31, #0xffffff00ff00ff
+ 1d8: 2f03e6df movi d31, #0xffffff00ffff00
+ 1dc: 2f03e6ff movi d31, #0xffffff00ffffff
+ 1e0: 2f03e71f movi d31, #0xffffffff000000
+ 1e4: 2f03e73f movi d31, #0xffffffff0000ff
+ 1e8: 2f03e75f movi d31, #0xffffffff00ff00
+ 1ec: 2f03e77f movi d31, #0xffffffff00ffff
+ 1f0: 2f03e79f movi d31, #0xffffffffff0000
+ 1f4: 2f03e7bf movi d31, #0xffffffffff00ff
+ 1f8: 2f03e7df movi d31, #0xffffffffffff00
+ 1fc: 2f03e7ff movi d31, #0xffffffffffffff
+ 200: 2f04e41f movi d31, #0xff00000000000000
+ 204: 2f04e43f movi d31, #0xff000000000000ff
+ 208: 2f04e45f movi d31, #0xff0000000000ff00
+ 20c: 2f04e47f movi d31, #0xff0000000000ffff
+ 210: 2f04e49f movi d31, #0xff00000000ff0000
+ 214: 2f04e4bf movi d31, #0xff00000000ff00ff
+ 218: 2f04e4df movi d31, #0xff00000000ffff00
+ 21c: 2f04e4ff movi d31, #0xff00000000ffffff
+ 220: 2f04e51f movi d31, #0xff000000ff000000
+ 224: 2f04e53f movi d31, #0xff000000ff0000ff
+ 228: 2f04e55f movi d31, #0xff000000ff00ff00
+ 22c: 2f04e57f movi d31, #0xff000000ff00ffff
+ 230: 2f04e59f movi d31, #0xff000000ffff0000
+ 234: 2f04e5bf movi d31, #0xff000000ffff00ff
+ 238: 2f04e5df movi d31, #0xff000000ffffff00
+ 23c: 2f04e5ff movi d31, #0xff000000ffffffff
+ 240: 2f04e61f movi d31, #0xff0000ff00000000
+ 244: 2f04e63f movi d31, #0xff0000ff000000ff
+ 248: 2f04e65f movi d31, #0xff0000ff0000ff00
+ 24c: 2f04e67f movi d31, #0xff0000ff0000ffff
+ 250: 2f04e69f movi d31, #0xff0000ff00ff0000
+ 254: 2f04e6bf movi d31, #0xff0000ff00ff00ff
+ 258: 2f04e6df movi d31, #0xff0000ff00ffff00
+ 25c: 2f04e6ff movi d31, #0xff0000ff00ffffff
+ 260: 2f04e71f movi d31, #0xff0000ffff000000
+ 264: 2f04e73f movi d31, #0xff0000ffff0000ff
+ 268: 2f04e75f movi d31, #0xff0000ffff00ff00
+ 26c: 2f04e77f movi d31, #0xff0000ffff00ffff
+ 270: 2f04e79f movi d31, #0xff0000ffffff0000
+ 274: 2f04e7bf movi d31, #0xff0000ffffff00ff
+ 278: 2f04e7df movi d31, #0xff0000ffffffff00
+ 27c: 2f04e7ff movi d31, #0xff0000ffffffffff
+ 280: 2f05e41f movi d31, #0xff00ff0000000000
+ 284: 2f05e43f movi d31, #0xff00ff00000000ff
+ 288: 2f05e45f movi d31, #0xff00ff000000ff00
+ 28c: 2f05e47f movi d31, #0xff00ff000000ffff
+ 290: 2f05e49f movi d31, #0xff00ff0000ff0000
+ 294: 2f05e4bf movi d31, #0xff00ff0000ff00ff
+ 298: 2f05e4df movi d31, #0xff00ff0000ffff00
+ 29c: 2f05e4ff movi d31, #0xff00ff0000ffffff
+ 2a0: 2f05e51f movi d31, #0xff00ff00ff000000
+ 2a4: 2f05e53f movi d31, #0xff00ff00ff0000ff
+ 2a8: 2f05e55f movi d31, #0xff00ff00ff00ff00
+ 2ac: 2f05e57f movi d31, #0xff00ff00ff00ffff
+ 2b0: 2f05e59f movi d31, #0xff00ff00ffff0000
+ 2b4: 2f05e5bf movi d31, #0xff00ff00ffff00ff
+ 2b8: 2f05e5df movi d31, #0xff00ff00ffffff00
+ 2bc: 2f05e5ff movi d31, #0xff00ff00ffffffff
+ 2c0: 2f05e61f movi d31, #0xff00ffff00000000
+ 2c4: 2f05e63f movi d31, #0xff00ffff000000ff
+ 2c8: 2f05e65f movi d31, #0xff00ffff0000ff00
+ 2cc: 2f05e67f movi d31, #0xff00ffff0000ffff
+ 2d0: 2f05e69f movi d31, #0xff00ffff00ff0000
+ 2d4: 2f05e6bf movi d31, #0xff00ffff00ff00ff
+ 2d8: 2f05e6df movi d31, #0xff00ffff00ffff00
+ 2dc: 2f05e6ff movi d31, #0xff00ffff00ffffff
+ 2e0: 2f05e71f movi d31, #0xff00ffffff000000
+ 2e4: 2f05e73f movi d31, #0xff00ffffff0000ff
+ 2e8: 2f05e75f movi d31, #0xff00ffffff00ff00
+ 2ec: 2f05e77f movi d31, #0xff00ffffff00ffff
+ 2f0: 2f05e79f movi d31, #0xff00ffffffff0000
+ 2f4: 2f05e7bf movi d31, #0xff00ffffffff00ff
+ 2f8: 2f05e7df movi d31, #0xff00ffffffffff00
+ 2fc: 2f05e7ff movi d31, #0xff00ffffffffffff
+ 300: 2f06e41f movi d31, #0xffff000000000000
+ 304: 2f06e43f movi d31, #0xffff0000000000ff
+ 308: 2f06e45f movi d31, #0xffff00000000ff00
+ 30c: 2f06e47f movi d31, #0xffff00000000ffff
+ 310: 2f06e49f movi d31, #0xffff000000ff0000
+ 314: 2f06e4bf movi d31, #0xffff000000ff00ff
+ 318: 2f06e4df movi d31, #0xffff000000ffff00
+ 31c: 2f06e4ff movi d31, #0xffff000000ffffff
+ 320: 2f06e51f movi d31, #0xffff0000ff000000
+ 324: 2f06e53f movi d31, #0xffff0000ff0000ff
+ 328: 2f06e55f movi d31, #0xffff0000ff00ff00
+ 32c: 2f06e57f movi d31, #0xffff0000ff00ffff
+ 330: 2f06e59f movi d31, #0xffff0000ffff0000
+ 334: 2f06e5bf movi d31, #0xffff0000ffff00ff
+ 338: 2f06e5df movi d31, #0xffff0000ffffff00
+ 33c: 2f06e5ff movi d31, #0xffff0000ffffffff
+ 340: 2f06e61f movi d31, #0xffff00ff00000000
+ 344: 2f06e63f movi d31, #0xffff00ff000000ff
+ 348: 2f06e65f movi d31, #0xffff00ff0000ff00
+ 34c: 2f06e67f movi d31, #0xffff00ff0000ffff
+ 350: 2f06e69f movi d31, #0xffff00ff00ff0000
+ 354: 2f06e6bf movi d31, #0xffff00ff00ff00ff
+ 358: 2f06e6df movi d31, #0xffff00ff00ffff00
+ 35c: 2f06e6ff movi d31, #0xffff00ff00ffffff
+ 360: 2f06e71f movi d31, #0xffff00ffff000000
+ 364: 2f06e73f movi d31, #0xffff00ffff0000ff
+ 368: 2f06e75f movi d31, #0xffff00ffff00ff00
+ 36c: 2f06e77f movi d31, #0xffff00ffff00ffff
+ 370: 2f06e79f movi d31, #0xffff00ffffff0000
+ 374: 2f06e7bf movi d31, #0xffff00ffffff00ff
+ 378: 2f06e7df movi d31, #0xffff00ffffffff00
+ 37c: 2f06e7ff movi d31, #0xffff00ffffffffff
+ 380: 2f07e41f movi d31, #0xffffff0000000000
+ 384: 2f07e43f movi d31, #0xffffff00000000ff
+ 388: 2f07e45f movi d31, #0xffffff000000ff00
+ 38c: 2f07e47f movi d31, #0xffffff000000ffff
+ 390: 2f07e49f movi d31, #0xffffff0000ff0000
+ 394: 2f07e4bf movi d31, #0xffffff0000ff00ff
+ 398: 2f07e4df movi d31, #0xffffff0000ffff00
+ 39c: 2f07e4ff movi d31, #0xffffff0000ffffff
+ 3a0: 2f07e51f movi d31, #0xffffff00ff000000
+ 3a4: 2f07e53f movi d31, #0xffffff00ff0000ff
+ 3a8: 2f07e55f movi d31, #0xffffff00ff00ff00
+ 3ac: 2f07e57f movi d31, #0xffffff00ff00ffff
+ 3b0: 2f07e59f movi d31, #0xffffff00ffff0000
+ 3b4: 2f07e5bf movi d31, #0xffffff00ffff00ff
+ 3b8: 2f07e5df movi d31, #0xffffff00ffffff00
+ 3bc: 2f07e5ff movi d31, #0xffffff00ffffffff
+ 3c0: 2f07e61f movi d31, #0xffffffff00000000
+ 3c4: 2f07e63f movi d31, #0xffffffff000000ff
+ 3c8: 2f07e65f movi d31, #0xffffffff0000ff00
+ 3cc: 2f07e67f movi d31, #0xffffffff0000ffff
+ 3d0: 2f07e69f movi d31, #0xffffffff00ff0000
+ 3d4: 2f07e6bf movi d31, #0xffffffff00ff00ff
+ 3d8: 2f07e6df movi d31, #0xffffffff00ffff00
+ 3dc: 2f07e6ff movi d31, #0xffffffff00ffffff
+ 3e0: 2f07e71f movi d31, #0xffffffffff000000
+ 3e4: 2f07e73f movi d31, #0xffffffffff0000ff
+ 3e8: 2f07e75f movi d31, #0xffffffffff00ff00
+ 3ec: 2f07e77f movi d31, #0xffffffffff00ffff
+ 3f0: 2f07e79f movi d31, #0xffffffffffff0000
+ 3f4: 2f07e7bf movi d31, #0xffffffffffff00ff
+ 3f8: 2f07e7df movi d31, #0xffffffffffffff00
+ 3fc: 2f07e7ff movi d31, #0xffffffffffffffff
+ 400: 6f00e40f movi v15.2d, #0x0
+ 404: 6f00e42f movi v15.2d, #0xff
+ 408: 6f00e44f movi v15.2d, #0xff00
+ 40c: 6f00e46f movi v15.2d, #0xffff
+ 410: 6f00e48f movi v15.2d, #0xff0000
+ 414: 6f00e4af movi v15.2d, #0xff00ff
+ 418: 6f00e4cf movi v15.2d, #0xffff00
+ 41c: 6f00e4ef movi v15.2d, #0xffffff
+ 420: 6f00e50f movi v15.2d, #0xff000000
+ 424: 6f00e52f movi v15.2d, #0xff0000ff
+ 428: 6f00e54f movi v15.2d, #0xff00ff00
+ 42c: 6f00e56f movi v15.2d, #0xff00ffff
+ 430: 6f00e58f movi v15.2d, #0xffff0000
+ 434: 6f00e5af movi v15.2d, #0xffff00ff
+ 438: 6f00e5cf movi v15.2d, #0xffffff00
+ 43c: 6f00e5ef movi v15.2d, #0xffffffff
+ 440: 6f00e60f movi v15.2d, #0xff00000000
+ 444: 6f00e62f movi v15.2d, #0xff000000ff
+ 448: 6f00e64f movi v15.2d, #0xff0000ff00
+ 44c: 6f00e66f movi v15.2d, #0xff0000ffff
+ 450: 6f00e68f movi v15.2d, #0xff00ff0000
+ 454: 6f00e6af movi v15.2d, #0xff00ff00ff
+ 458: 6f00e6cf movi v15.2d, #0xff00ffff00
+ 45c: 6f00e6ef movi v15.2d, #0xff00ffffff
+ 460: 6f00e70f movi v15.2d, #0xffff000000
+ 464: 6f00e72f movi v15.2d, #0xffff0000ff
+ 468: 6f00e74f movi v15.2d, #0xffff00ff00
+ 46c: 6f00e76f movi v15.2d, #0xffff00ffff
+ 470: 6f00e78f movi v15.2d, #0xffffff0000
+ 474: 6f00e7af movi v15.2d, #0xffffff00ff
+ 478: 6f00e7cf movi v15.2d, #0xffffffff00
+ 47c: 6f00e7ef movi v15.2d, #0xffffffffff
+ 480: 6f01e40f movi v15.2d, #0xff0000000000
+ 484: 6f01e42f movi v15.2d, #0xff00000000ff
+ 488: 6f01e44f movi v15.2d, #0xff000000ff00
+ 48c: 6f01e46f movi v15.2d, #0xff000000ffff
+ 490: 6f01e48f movi v15.2d, #0xff0000ff0000
+ 494: 6f01e4af movi v15.2d, #0xff0000ff00ff
+ 498: 6f01e4cf movi v15.2d, #0xff0000ffff00
+ 49c: 6f01e4ef movi v15.2d, #0xff0000ffffff
+ 4a0: 6f01e50f movi v15.2d, #0xff00ff000000
+ 4a4: 6f01e52f movi v15.2d, #0xff00ff0000ff
+ 4a8: 6f01e54f movi v15.2d, #0xff00ff00ff00
+ 4ac: 6f01e56f movi v15.2d, #0xff00ff00ffff
+ 4b0: 6f01e58f movi v15.2d, #0xff00ffff0000
+ 4b4: 6f01e5af movi v15.2d, #0xff00ffff00ff
+ 4b8: 6f01e5cf movi v15.2d, #0xff00ffffff00
+ 4bc: 6f01e5ef movi v15.2d, #0xff00ffffffff
+ 4c0: 6f01e60f movi v15.2d, #0xffff00000000
+ 4c4: 6f01e62f movi v15.2d, #0xffff000000ff
+ 4c8: 6f01e64f movi v15.2d, #0xffff0000ff00
+ 4cc: 6f01e66f movi v15.2d, #0xffff0000ffff
+ 4d0: 6f01e68f movi v15.2d, #0xffff00ff0000
+ 4d4: 6f01e6af movi v15.2d, #0xffff00ff00ff
+ 4d8: 6f01e6cf movi v15.2d, #0xffff00ffff00
+ 4dc: 6f01e6ef movi v15.2d, #0xffff00ffffff
+ 4e0: 6f01e70f movi v15.2d, #0xffffff000000
+ 4e4: 6f01e72f movi v15.2d, #0xffffff0000ff
+ 4e8: 6f01e74f movi v15.2d, #0xffffff00ff00
+ 4ec: 6f01e76f movi v15.2d, #0xffffff00ffff
+ 4f0: 6f01e78f movi v15.2d, #0xffffffff0000
+ 4f4: 6f01e7af movi v15.2d, #0xffffffff00ff
+ 4f8: 6f01e7cf movi v15.2d, #0xffffffffff00
+ 4fc: 6f01e7ef movi v15.2d, #0xffffffffffff
+ 500: 6f02e40f movi v15.2d, #0xff000000000000
+ 504: 6f02e42f movi v15.2d, #0xff0000000000ff
+ 508: 6f02e44f movi v15.2d, #0xff00000000ff00
+ 50c: 6f02e46f movi v15.2d, #0xff00000000ffff
+ 510: 6f02e48f movi v15.2d, #0xff000000ff0000
+ 514: 6f02e4af movi v15.2d, #0xff000000ff00ff
+ 518: 6f02e4cf movi v15.2d, #0xff000000ffff00
+ 51c: 6f02e4ef movi v15.2d, #0xff000000ffffff
+ 520: 6f02e50f movi v15.2d, #0xff0000ff000000
+ 524: 6f02e52f movi v15.2d, #0xff0000ff0000ff
+ 528: 6f02e54f movi v15.2d, #0xff0000ff00ff00
+ 52c: 6f02e56f movi v15.2d, #0xff0000ff00ffff
+ 530: 6f02e58f movi v15.2d, #0xff0000ffff0000
+ 534: 6f02e5af movi v15.2d, #0xff0000ffff00ff
+ 538: 6f02e5cf movi v15.2d, #0xff0000ffffff00
+ 53c: 6f02e5ef movi v15.2d, #0xff0000ffffffff
+ 540: 6f02e60f movi v15.2d, #0xff00ff00000000
+ 544: 6f02e62f movi v15.2d, #0xff00ff000000ff
+ 548: 6f02e64f movi v15.2d, #0xff00ff0000ff00
+ 54c: 6f02e66f movi v15.2d, #0xff00ff0000ffff
+ 550: 6f02e68f movi v15.2d, #0xff00ff00ff0000
+ 554: 6f02e6af movi v15.2d, #0xff00ff00ff00ff
+ 558: 6f02e6cf movi v15.2d, #0xff00ff00ffff00
+ 55c: 6f02e6ef movi v15.2d, #0xff00ff00ffffff
+ 560: 6f02e70f movi v15.2d, #0xff00ffff000000
+ 564: 6f02e72f movi v15.2d, #0xff00ffff0000ff
+ 568: 6f02e74f movi v15.2d, #0xff00ffff00ff00
+ 56c: 6f02e76f movi v15.2d, #0xff00ffff00ffff
+ 570: 6f02e78f movi v15.2d, #0xff00ffffff0000
+ 574: 6f02e7af movi v15.2d, #0xff00ffffff00ff
+ 578: 6f02e7cf movi v15.2d, #0xff00ffffffff00
+ 57c: 6f02e7ef movi v15.2d, #0xff00ffffffffff
+ 580: 6f03e40f movi v15.2d, #0xffff0000000000
+ 584: 6f03e42f movi v15.2d, #0xffff00000000ff
+ 588: 6f03e44f movi v15.2d, #0xffff000000ff00
+ 58c: 6f03e46f movi v15.2d, #0xffff000000ffff
+ 590: 6f03e48f movi v15.2d, #0xffff0000ff0000
+ 594: 6f03e4af movi v15.2d, #0xffff0000ff00ff
+ 598: 6f03e4cf movi v15.2d, #0xffff0000ffff00
+ 59c: 6f03e4ef movi v15.2d, #0xffff0000ffffff
+ 5a0: 6f03e50f movi v15.2d, #0xffff00ff000000
+ 5a4: 6f03e52f movi v15.2d, #0xffff00ff0000ff
+ 5a8: 6f03e54f movi v15.2d, #0xffff00ff00ff00
+ 5ac: 6f03e56f movi v15.2d, #0xffff00ff00ffff
+ 5b0: 6f03e58f movi v15.2d, #0xffff00ffff0000
+ 5b4: 6f03e5af movi v15.2d, #0xffff00ffff00ff
+ 5b8: 6f03e5cf movi v15.2d, #0xffff00ffffff00
+ 5bc: 6f03e5ef movi v15.2d, #0xffff00ffffffff
+ 5c0: 6f03e60f movi v15.2d, #0xffffff00000000
+ 5c4: 6f03e62f movi v15.2d, #0xffffff000000ff
+ 5c8: 6f03e64f movi v15.2d, #0xffffff0000ff00
+ 5cc: 6f03e66f movi v15.2d, #0xffffff0000ffff
+ 5d0: 6f03e68f movi v15.2d, #0xffffff00ff0000
+ 5d4: 6f03e6af movi v15.2d, #0xffffff00ff00ff
+ 5d8: 6f03e6cf movi v15.2d, #0xffffff00ffff00
+ 5dc: 6f03e6ef movi v15.2d, #0xffffff00ffffff
+ 5e0: 6f03e70f movi v15.2d, #0xffffffff000000
+ 5e4: 6f03e72f movi v15.2d, #0xffffffff0000ff
+ 5e8: 6f03e74f movi v15.2d, #0xffffffff00ff00
+ 5ec: 6f03e76f movi v15.2d, #0xffffffff00ffff
+ 5f0: 6f03e78f movi v15.2d, #0xffffffffff0000
+ 5f4: 6f03e7af movi v15.2d, #0xffffffffff00ff
+ 5f8: 6f03e7cf movi v15.2d, #0xffffffffffff00
+ 5fc: 6f03e7ef movi v15.2d, #0xffffffffffffff
+ 600: 6f04e40f movi v15.2d, #0xff00000000000000
+ 604: 6f04e42f movi v15.2d, #0xff000000000000ff
+ 608: 6f04e44f movi v15.2d, #0xff0000000000ff00
+ 60c: 6f04e46f movi v15.2d, #0xff0000000000ffff
+ 610: 6f04e48f movi v15.2d, #0xff00000000ff0000
+ 614: 6f04e4af movi v15.2d, #0xff00000000ff00ff
+ 618: 6f04e4cf movi v15.2d, #0xff00000000ffff00
+ 61c: 6f04e4ef movi v15.2d, #0xff00000000ffffff
+ 620: 6f04e50f movi v15.2d, #0xff000000ff000000
+ 624: 6f04e52f movi v15.2d, #0xff000000ff0000ff
+ 628: 6f04e54f movi v15.2d, #0xff000000ff00ff00
+ 62c: 6f04e56f movi v15.2d, #0xff000000ff00ffff
+ 630: 6f04e58f movi v15.2d, #0xff000000ffff0000
+ 634: 6f04e5af movi v15.2d, #0xff000000ffff00ff
+ 638: 6f04e5cf movi v15.2d, #0xff000000ffffff00
+ 63c: 6f04e5ef movi v15.2d, #0xff000000ffffffff
+ 640: 6f04e60f movi v15.2d, #0xff0000ff00000000
+ 644: 6f04e62f movi v15.2d, #0xff0000ff000000ff
+ 648: 6f04e64f movi v15.2d, #0xff0000ff0000ff00
+ 64c: 6f04e66f movi v15.2d, #0xff0000ff0000ffff
+ 650: 6f04e68f movi v15.2d, #0xff0000ff00ff0000
+ 654: 6f04e6af movi v15.2d, #0xff0000ff00ff00ff
+ 658: 6f04e6cf movi v15.2d, #0xff0000ff00ffff00
+ 65c: 6f04e6ef movi v15.2d, #0xff0000ff00ffffff
+ 660: 6f04e70f movi v15.2d, #0xff0000ffff000000
+ 664: 6f04e72f movi v15.2d, #0xff0000ffff0000ff
+ 668: 6f04e74f movi v15.2d, #0xff0000ffff00ff00
+ 66c: 6f04e76f movi v15.2d, #0xff0000ffff00ffff
+ 670: 6f04e78f movi v15.2d, #0xff0000ffffff0000
+ 674: 6f04e7af movi v15.2d, #0xff0000ffffff00ff
+ 678: 6f04e7cf movi v15.2d, #0xff0000ffffffff00
+ 67c: 6f04e7ef movi v15.2d, #0xff0000ffffffffff
+ 680: 6f05e40f movi v15.2d, #0xff00ff0000000000
+ 684: 6f05e42f movi v15.2d, #0xff00ff00000000ff
+ 688: 6f05e44f movi v15.2d, #0xff00ff000000ff00
+ 68c: 6f05e46f movi v15.2d, #0xff00ff000000ffff
+ 690: 6f05e48f movi v15.2d, #0xff00ff0000ff0000
+ 694: 6f05e4af movi v15.2d, #0xff00ff0000ff00ff
+ 698: 6f05e4cf movi v15.2d, #0xff00ff0000ffff00
+ 69c: 6f05e4ef movi v15.2d, #0xff00ff0000ffffff
+ 6a0: 6f05e50f movi v15.2d, #0xff00ff00ff000000
+ 6a4: 6f05e52f movi v15.2d, #0xff00ff00ff0000ff
+ 6a8: 6f05e54f movi v15.2d, #0xff00ff00ff00ff00
+ 6ac: 6f05e56f movi v15.2d, #0xff00ff00ff00ffff
+ 6b0: 6f05e58f movi v15.2d, #0xff00ff00ffff0000
+ 6b4: 6f05e5af movi v15.2d, #0xff00ff00ffff00ff
+ 6b8: 6f05e5cf movi v15.2d, #0xff00ff00ffffff00
+ 6bc: 6f05e5ef movi v15.2d, #0xff00ff00ffffffff
+ 6c0: 6f05e60f movi v15.2d, #0xff00ffff00000000
+ 6c4: 6f05e62f movi v15.2d, #0xff00ffff000000ff
+ 6c8: 6f05e64f movi v15.2d, #0xff00ffff0000ff00
+ 6cc: 6f05e66f movi v15.2d, #0xff00ffff0000ffff
+ 6d0: 6f05e68f movi v15.2d, #0xff00ffff00ff0000
+ 6d4: 6f05e6af movi v15.2d, #0xff00ffff00ff00ff
+ 6d8: 6f05e6cf movi v15.2d, #0xff00ffff00ffff00
+ 6dc: 6f05e6ef movi v15.2d, #0xff00ffff00ffffff
+ 6e0: 6f05e70f movi v15.2d, #0xff00ffffff000000
+ 6e4: 6f05e72f movi v15.2d, #0xff00ffffff0000ff
+ 6e8: 6f05e74f movi v15.2d, #0xff00ffffff00ff00
+ 6ec: 6f05e76f movi v15.2d, #0xff00ffffff00ffff
+ 6f0: 6f05e78f movi v15.2d, #0xff00ffffffff0000
+ 6f4: 6f05e7af movi v15.2d, #0xff00ffffffff00ff
+ 6f8: 6f05e7cf movi v15.2d, #0xff00ffffffffff00
+ 6fc: 6f05e7ef movi v15.2d, #0xff00ffffffffffff
+ 700: 6f06e40f movi v15.2d, #0xffff000000000000
+ 704: 6f06e42f movi v15.2d, #0xffff0000000000ff
+ 708: 6f06e44f movi v15.2d, #0xffff00000000ff00
+ 70c: 6f06e46f movi v15.2d, #0xffff00000000ffff
+ 710: 6f06e48f movi v15.2d, #0xffff000000ff0000
+ 714: 6f06e4af movi v15.2d, #0xffff000000ff00ff
+ 718: 6f06e4cf movi v15.2d, #0xffff000000ffff00
+ 71c: 6f06e4ef movi v15.2d, #0xffff000000ffffff
+ 720: 6f06e50f movi v15.2d, #0xffff0000ff000000
+ 724: 6f06e52f movi v15.2d, #0xffff0000ff0000ff
+ 728: 6f06e54f movi v15.2d, #0xffff0000ff00ff00
+ 72c: 6f06e56f movi v15.2d, #0xffff0000ff00ffff
+ 730: 6f06e58f movi v15.2d, #0xffff0000ffff0000
+ 734: 6f06e5af movi v15.2d, #0xffff0000ffff00ff
+ 738: 6f06e5cf movi v15.2d, #0xffff0000ffffff00
+ 73c: 6f06e5ef movi v15.2d, #0xffff0000ffffffff
+ 740: 6f06e60f movi v15.2d, #0xffff00ff00000000
+ 744: 6f06e62f movi v15.2d, #0xffff00ff000000ff
+ 748: 6f06e64f movi v15.2d, #0xffff00ff0000ff00
+ 74c: 6f06e66f movi v15.2d, #0xffff00ff0000ffff
+ 750: 6f06e68f movi v15.2d, #0xffff00ff00ff0000
+ 754: 6f06e6af movi v15.2d, #0xffff00ff00ff00ff
+ 758: 6f06e6cf movi v15.2d, #0xffff00ff00ffff00
+ 75c: 6f06e6ef movi v15.2d, #0xffff00ff00ffffff
+ 760: 6f06e70f movi v15.2d, #0xffff00ffff000000
+ 764: 6f06e72f movi v15.2d, #0xffff00ffff0000ff
+ 768: 6f06e74f movi v15.2d, #0xffff00ffff00ff00
+ 76c: 6f06e76f movi v15.2d, #0xffff00ffff00ffff
+ 770: 6f06e78f movi v15.2d, #0xffff00ffffff0000
+ 774: 6f06e7af movi v15.2d, #0xffff00ffffff00ff
+ 778: 6f06e7cf movi v15.2d, #0xffff00ffffffff00
+ 77c: 6f06e7ef movi v15.2d, #0xffff00ffffffffff
+ 780: 6f07e40f movi v15.2d, #0xffffff0000000000
+ 784: 6f07e42f movi v15.2d, #0xffffff00000000ff
+ 788: 6f07e44f movi v15.2d, #0xffffff000000ff00
+ 78c: 6f07e46f movi v15.2d, #0xffffff000000ffff
+ 790: 6f07e48f movi v15.2d, #0xffffff0000ff0000
+ 794: 6f07e4af movi v15.2d, #0xffffff0000ff00ff
+ 798: 6f07e4cf movi v15.2d, #0xffffff0000ffff00
+ 79c: 6f07e4ef movi v15.2d, #0xffffff0000ffffff
+ 7a0: 6f07e50f movi v15.2d, #0xffffff00ff000000
+ 7a4: 6f07e52f movi v15.2d, #0xffffff00ff0000ff
+ 7a8: 6f07e54f movi v15.2d, #0xffffff00ff00ff00
+ 7ac: 6f07e56f movi v15.2d, #0xffffff00ff00ffff
+ 7b0: 6f07e58f movi v15.2d, #0xffffff00ffff0000
+ 7b4: 6f07e5af movi v15.2d, #0xffffff00ffff00ff
+ 7b8: 6f07e5cf movi v15.2d, #0xffffff00ffffff00
+ 7bc: 6f07e5ef movi v15.2d, #0xffffff00ffffffff
+ 7c0: 6f07e60f movi v15.2d, #0xffffffff00000000
+ 7c4: 6f07e62f movi v15.2d, #0xffffffff000000ff
+ 7c8: 6f07e64f movi v15.2d, #0xffffffff0000ff00
+ 7cc: 6f07e66f movi v15.2d, #0xffffffff0000ffff
+ 7d0: 6f07e68f movi v15.2d, #0xffffffff00ff0000
+ 7d4: 6f07e6af movi v15.2d, #0xffffffff00ff00ff
+ 7d8: 6f07e6cf movi v15.2d, #0xffffffff00ffff00
+ 7dc: 6f07e6ef movi v15.2d, #0xffffffff00ffffff
+ 7e0: 6f07e70f movi v15.2d, #0xffffffffff000000
+ 7e4: 6f07e72f movi v15.2d, #0xffffffffff0000ff
+ 7e8: 6f07e74f movi v15.2d, #0xffffffffff00ff00
+ 7ec: 6f07e76f movi v15.2d, #0xffffffffff00ffff
+ 7f0: 6f07e78f movi v15.2d, #0xffffffffffff0000
+ 7f4: 6f07e7af movi v15.2d, #0xffffffffffff00ff
+ 7f8: 6f07e7cf movi v15.2d, #0xffffffffffffff00
+ 7fc: 6f07e7ef movi v15.2d, #0xffffffffffffffff
+ 800: 0f00e40f movi v15.8b, #0x0
+ 804: 0f00e42f movi v15.8b, #0x1
+ 808: 0f00e44f movi v15.8b, #0x2
+ 80c: 0f00e46f movi v15.8b, #0x3
+ 810: 0f00e48f movi v15.8b, #0x4
+ 814: 0f00e4af movi v15.8b, #0x5
+ 818: 0f00e4cf movi v15.8b, #0x6
+ 81c: 0f00e4ef movi v15.8b, #0x7
+ 820: 0f00e50f movi v15.8b, #0x8
+ 824: 0f00e52f movi v15.8b, #0x9
+ 828: 0f00e54f movi v15.8b, #0xa
+ 82c: 0f00e56f movi v15.8b, #0xb
+ 830: 0f00e58f movi v15.8b, #0xc
+ 834: 0f00e5af movi v15.8b, #0xd
+ 838: 0f00e5cf movi v15.8b, #0xe
+ 83c: 0f00e5ef movi v15.8b, #0xf
+ 840: 0f00e60f movi v15.8b, #0x10
+ 844: 0f00e62f movi v15.8b, #0x11
+ 848: 0f00e64f movi v15.8b, #0x12
+ 84c: 0f00e66f movi v15.8b, #0x13
+ 850: 0f00e68f movi v15.8b, #0x14
+ 854: 0f00e6af movi v15.8b, #0x15
+ 858: 0f00e6cf movi v15.8b, #0x16
+ 85c: 0f00e6ef movi v15.8b, #0x17
+ 860: 0f00e70f movi v15.8b, #0x18
+ 864: 0f00e72f movi v15.8b, #0x19
+ 868: 0f00e74f movi v15.8b, #0x1a
+ 86c: 0f00e76f movi v15.8b, #0x1b
+ 870: 0f00e78f movi v15.8b, #0x1c
+ 874: 0f00e7af movi v15.8b, #0x1d
+ 878: 0f00e7cf movi v15.8b, #0x1e
+ 87c: 0f00e7ef movi v15.8b, #0x1f
+ 880: 0f01e40f movi v15.8b, #0x20
+ 884: 0f01e42f movi v15.8b, #0x21
+ 888: 0f01e44f movi v15.8b, #0x22
+ 88c: 0f01e46f movi v15.8b, #0x23
+ 890: 0f01e48f movi v15.8b, #0x24
+ 894: 0f01e4af movi v15.8b, #0x25
+ 898: 0f01e4cf movi v15.8b, #0x26
+ 89c: 0f01e4ef movi v15.8b, #0x27
+ 8a0: 0f01e50f movi v15.8b, #0x28
+ 8a4: 0f01e52f movi v15.8b, #0x29
+ 8a8: 0f01e54f movi v15.8b, #0x2a
+ 8ac: 0f01e56f movi v15.8b, #0x2b
+ 8b0: 0f01e58f movi v15.8b, #0x2c
+ 8b4: 0f01e5af movi v15.8b, #0x2d
+ 8b8: 0f01e5cf movi v15.8b, #0x2e
+ 8bc: 0f01e5ef movi v15.8b, #0x2f
+ 8c0: 0f01e60f movi v15.8b, #0x30
+ 8c4: 0f01e62f movi v15.8b, #0x31
+ 8c8: 0f01e64f movi v15.8b, #0x32
+ 8cc: 0f01e66f movi v15.8b, #0x33
+ 8d0: 0f01e68f movi v15.8b, #0x34
+ 8d4: 0f01e6af movi v15.8b, #0x35
+ 8d8: 0f01e6cf movi v15.8b, #0x36
+ 8dc: 0f01e6ef movi v15.8b, #0x37
+ 8e0: 0f01e70f movi v15.8b, #0x38
+ 8e4: 0f01e72f movi v15.8b, #0x39
+ 8e8: 0f01e74f movi v15.8b, #0x3a
+ 8ec: 0f01e76f movi v15.8b, #0x3b
+ 8f0: 0f01e78f movi v15.8b, #0x3c
+ 8f4: 0f01e7af movi v15.8b, #0x3d
+ 8f8: 0f01e7cf movi v15.8b, #0x3e
+ 8fc: 0f01e7ef movi v15.8b, #0x3f
+ 900: 0f02e40f movi v15.8b, #0x40
+ 904: 0f02e42f movi v15.8b, #0x41
+ 908: 0f02e44f movi v15.8b, #0x42
+ 90c: 0f02e46f movi v15.8b, #0x43
+ 910: 0f02e48f movi v15.8b, #0x44
+ 914: 0f02e4af movi v15.8b, #0x45
+ 918: 0f02e4cf movi v15.8b, #0x46
+ 91c: 0f02e4ef movi v15.8b, #0x47
+ 920: 0f02e50f movi v15.8b, #0x48
+ 924: 0f02e52f movi v15.8b, #0x49
+ 928: 0f02e54f movi v15.8b, #0x4a
+ 92c: 0f02e56f movi v15.8b, #0x4b
+ 930: 0f02e58f movi v15.8b, #0x4c
+ 934: 0f02e5af movi v15.8b, #0x4d
+ 938: 0f02e5cf movi v15.8b, #0x4e
+ 93c: 0f02e5ef movi v15.8b, #0x4f
+ 940: 0f02e60f movi v15.8b, #0x50
+ 944: 0f02e62f movi v15.8b, #0x51
+ 948: 0f02e64f movi v15.8b, #0x52
+ 94c: 0f02e66f movi v15.8b, #0x53
+ 950: 0f02e68f movi v15.8b, #0x54
+ 954: 0f02e6af movi v15.8b, #0x55
+ 958: 0f02e6cf movi v15.8b, #0x56
+ 95c: 0f02e6ef movi v15.8b, #0x57
+ 960: 0f02e70f movi v15.8b, #0x58
+ 964: 0f02e72f movi v15.8b, #0x59
+ 968: 0f02e74f movi v15.8b, #0x5a
+ 96c: 0f02e76f movi v15.8b, #0x5b
+ 970: 0f02e78f movi v15.8b, #0x5c
+ 974: 0f02e7af movi v15.8b, #0x5d
+ 978: 0f02e7cf movi v15.8b, #0x5e
+ 97c: 0f02e7ef movi v15.8b, #0x5f
+ 980: 0f03e40f movi v15.8b, #0x60
+ 984: 0f03e42f movi v15.8b, #0x61
+ 988: 0f03e44f movi v15.8b, #0x62
+ 98c: 0f03e46f movi v15.8b, #0x63
+ 990: 0f03e48f movi v15.8b, #0x64
+ 994: 0f03e4af movi v15.8b, #0x65
+ 998: 0f03e4cf movi v15.8b, #0x66
+ 99c: 0f03e4ef movi v15.8b, #0x67
+ 9a0: 0f03e50f movi v15.8b, #0x68
+ 9a4: 0f03e52f movi v15.8b, #0x69
+ 9a8: 0f03e54f movi v15.8b, #0x6a
+ 9ac: 0f03e56f movi v15.8b, #0x6b
+ 9b0: 0f03e58f movi v15.8b, #0x6c
+ 9b4: 0f03e5af movi v15.8b, #0x6d
+ 9b8: 0f03e5cf movi v15.8b, #0x6e
+ 9bc: 0f03e5ef movi v15.8b, #0x6f
+ 9c0: 0f03e60f movi v15.8b, #0x70
+ 9c4: 0f03e62f movi v15.8b, #0x71
+ 9c8: 0f03e64f movi v15.8b, #0x72
+ 9cc: 0f03e66f movi v15.8b, #0x73
+ 9d0: 0f03e68f movi v15.8b, #0x74
+ 9d4: 0f03e6af movi v15.8b, #0x75
+ 9d8: 0f03e6cf movi v15.8b, #0x76
+ 9dc: 0f03e6ef movi v15.8b, #0x77
+ 9e0: 0f03e70f movi v15.8b, #0x78
+ 9e4: 0f03e72f movi v15.8b, #0x79
+ 9e8: 0f03e74f movi v15.8b, #0x7a
+ 9ec: 0f03e76f movi v15.8b, #0x7b
+ 9f0: 0f03e78f movi v15.8b, #0x7c
+ 9f4: 0f03e7af movi v15.8b, #0x7d
+ 9f8: 0f03e7cf movi v15.8b, #0x7e
+ 9fc: 0f03e7ef movi v15.8b, #0x7f
+ a00: 0f04e40f movi v15.8b, #0x80
+ a04: 0f04e42f movi v15.8b, #0x81
+ a08: 0f04e44f movi v15.8b, #0x82
+ a0c: 0f04e46f movi v15.8b, #0x83
+ a10: 0f04e48f movi v15.8b, #0x84
+ a14: 0f04e4af movi v15.8b, #0x85
+ a18: 0f04e4cf movi v15.8b, #0x86
+ a1c: 0f04e4ef movi v15.8b, #0x87
+ a20: 0f04e50f movi v15.8b, #0x88
+ a24: 0f04e52f movi v15.8b, #0x89
+ a28: 0f04e54f movi v15.8b, #0x8a
+ a2c: 0f04e56f movi v15.8b, #0x8b
+ a30: 0f04e58f movi v15.8b, #0x8c
+ a34: 0f04e5af movi v15.8b, #0x8d
+ a38: 0f04e5cf movi v15.8b, #0x8e
+ a3c: 0f04e5ef movi v15.8b, #0x8f
+ a40: 0f04e60f movi v15.8b, #0x90
+ a44: 0f04e62f movi v15.8b, #0x91
+ a48: 0f04e64f movi v15.8b, #0x92
+ a4c: 0f04e66f movi v15.8b, #0x93
+ a50: 0f04e68f movi v15.8b, #0x94
+ a54: 0f04e6af movi v15.8b, #0x95
+ a58: 0f04e6cf movi v15.8b, #0x96
+ a5c: 0f04e6ef movi v15.8b, #0x97
+ a60: 0f04e70f movi v15.8b, #0x98
+ a64: 0f04e72f movi v15.8b, #0x99
+ a68: 0f04e74f movi v15.8b, #0x9a
+ a6c: 0f04e76f movi v15.8b, #0x9b
+ a70: 0f04e78f movi v15.8b, #0x9c
+ a74: 0f04e7af movi v15.8b, #0x9d
+ a78: 0f04e7cf movi v15.8b, #0x9e
+ a7c: 0f04e7ef movi v15.8b, #0x9f
+ a80: 0f05e40f movi v15.8b, #0xa0
+ a84: 0f05e42f movi v15.8b, #0xa1
+ a88: 0f05e44f movi v15.8b, #0xa2
+ a8c: 0f05e46f movi v15.8b, #0xa3
+ a90: 0f05e48f movi v15.8b, #0xa4
+ a94: 0f05e4af movi v15.8b, #0xa5
+ a98: 0f05e4cf movi v15.8b, #0xa6
+ a9c: 0f05e4ef movi v15.8b, #0xa7
+ aa0: 0f05e50f movi v15.8b, #0xa8
+ aa4: 0f05e52f movi v15.8b, #0xa9
+ aa8: 0f05e54f movi v15.8b, #0xaa
+ aac: 0f05e56f movi v15.8b, #0xab
+ ab0: 0f05e58f movi v15.8b, #0xac
+ ab4: 0f05e5af movi v15.8b, #0xad
+ ab8: 0f05e5cf movi v15.8b, #0xae
+ abc: 0f05e5ef movi v15.8b, #0xaf
+ ac0: 0f05e60f movi v15.8b, #0xb0
+ ac4: 0f05e62f movi v15.8b, #0xb1
+ ac8: 0f05e64f movi v15.8b, #0xb2
+ acc: 0f05e66f movi v15.8b, #0xb3
+ ad0: 0f05e68f movi v15.8b, #0xb4
+ ad4: 0f05e6af movi v15.8b, #0xb5
+ ad8: 0f05e6cf movi v15.8b, #0xb6
+ adc: 0f05e6ef movi v15.8b, #0xb7
+ ae0: 0f05e70f movi v15.8b, #0xb8
+ ae4: 0f05e72f movi v15.8b, #0xb9
+ ae8: 0f05e74f movi v15.8b, #0xba
+ aec: 0f05e76f movi v15.8b, #0xbb
+ af0: 0f05e78f movi v15.8b, #0xbc
+ af4: 0f05e7af movi v15.8b, #0xbd
+ af8: 0f05e7cf movi v15.8b, #0xbe
+ afc: 0f05e7ef movi v15.8b, #0xbf
+ b00: 0f06e40f movi v15.8b, #0xc0
+ b04: 0f06e42f movi v15.8b, #0xc1
+ b08: 0f06e44f movi v15.8b, #0xc2
+ b0c: 0f06e46f movi v15.8b, #0xc3
+ b10: 0f06e48f movi v15.8b, #0xc4
+ b14: 0f06e4af movi v15.8b, #0xc5
+ b18: 0f06e4cf movi v15.8b, #0xc6
+ b1c: 0f06e4ef movi v15.8b, #0xc7
+ b20: 0f06e50f movi v15.8b, #0xc8
+ b24: 0f06e52f movi v15.8b, #0xc9
+ b28: 0f06e54f movi v15.8b, #0xca
+ b2c: 0f06e56f movi v15.8b, #0xcb
+ b30: 0f06e58f movi v15.8b, #0xcc
+ b34: 0f06e5af movi v15.8b, #0xcd
+ b38: 0f06e5cf movi v15.8b, #0xce
+ b3c: 0f06e5ef movi v15.8b, #0xcf
+ b40: 0f06e60f movi v15.8b, #0xd0
+ b44: 0f06e62f movi v15.8b, #0xd1
+ b48: 0f06e64f movi v15.8b, #0xd2
+ b4c: 0f06e66f movi v15.8b, #0xd3
+ b50: 0f06e68f movi v15.8b, #0xd4
+ b54: 0f06e6af movi v15.8b, #0xd5
+ b58: 0f06e6cf movi v15.8b, #0xd6
+ b5c: 0f06e6ef movi v15.8b, #0xd7
+ b60: 0f06e70f movi v15.8b, #0xd8
+ b64: 0f06e72f movi v15.8b, #0xd9
+ b68: 0f06e74f movi v15.8b, #0xda
+ b6c: 0f06e76f movi v15.8b, #0xdb
+ b70: 0f06e78f movi v15.8b, #0xdc
+ b74: 0f06e7af movi v15.8b, #0xdd
+ b78: 0f06e7cf movi v15.8b, #0xde
+ b7c: 0f06e7ef movi v15.8b, #0xdf
+ b80: 0f07e40f movi v15.8b, #0xe0
+ b84: 0f07e42f movi v15.8b, #0xe1
+ b88: 0f07e44f movi v15.8b, #0xe2
+ b8c: 0f07e46f movi v15.8b, #0xe3
+ b90: 0f07e48f movi v15.8b, #0xe4
+ b94: 0f07e4af movi v15.8b, #0xe5
+ b98: 0f07e4cf movi v15.8b, #0xe6
+ b9c: 0f07e4ef movi v15.8b, #0xe7
+ ba0: 0f07e50f movi v15.8b, #0xe8
+ ba4: 0f07e52f movi v15.8b, #0xe9
+ ba8: 0f07e54f movi v15.8b, #0xea
+ bac: 0f07e56f movi v15.8b, #0xeb
+ bb0: 0f07e58f movi v15.8b, #0xec
+ bb4: 0f07e5af movi v15.8b, #0xed
+ bb8: 0f07e5cf movi v15.8b, #0xee
+ bbc: 0f07e5ef movi v15.8b, #0xef
+ bc0: 0f07e60f movi v15.8b, #0xf0
+ bc4: 0f07e62f movi v15.8b, #0xf1
+ bc8: 0f07e64f movi v15.8b, #0xf2
+ bcc: 0f07e66f movi v15.8b, #0xf3
+ bd0: 0f07e68f movi v15.8b, #0xf4
+ bd4: 0f07e6af movi v15.8b, #0xf5
+ bd8: 0f07e6cf movi v15.8b, #0xf6
+ bdc: 0f07e6ef movi v15.8b, #0xf7
+ be0: 0f07e70f movi v15.8b, #0xf8
+ be4: 0f07e72f movi v15.8b, #0xf9
+ be8: 0f07e74f movi v15.8b, #0xfa
+ bec: 0f07e76f movi v15.8b, #0xfb
+ bf0: 0f07e78f movi v15.8b, #0xfc
+ bf4: 0f07e7af movi v15.8b, #0xfd
+ bf8: 0f07e7cf movi v15.8b, #0xfe
+ bfc: 0f07e7ef movi v15.8b, #0xff
+ c00: 4f00e40f movi v15.16b, #0x0
+ c04: 4f00e42f movi v15.16b, #0x1
+ c08: 4f00e44f movi v15.16b, #0x2
+ c0c: 4f00e46f movi v15.16b, #0x3
+ c10: 4f00e48f movi v15.16b, #0x4
+ c14: 4f00e4af movi v15.16b, #0x5
+ c18: 4f00e4cf movi v15.16b, #0x6
+ c1c: 4f00e4ef movi v15.16b, #0x7
+ c20: 4f00e50f movi v15.16b, #0x8
+ c24: 4f00e52f movi v15.16b, #0x9
+ c28: 4f00e54f movi v15.16b, #0xa
+ c2c: 4f00e56f movi v15.16b, #0xb
+ c30: 4f00e58f movi v15.16b, #0xc
+ c34: 4f00e5af movi v15.16b, #0xd
+ c38: 4f00e5cf movi v15.16b, #0xe
+ c3c: 4f00e5ef movi v15.16b, #0xf
+ c40: 4f00e60f movi v15.16b, #0x10
+ c44: 4f00e62f movi v15.16b, #0x11
+ c48: 4f00e64f movi v15.16b, #0x12
+ c4c: 4f00e66f movi v15.16b, #0x13
+ c50: 4f00e68f movi v15.16b, #0x14
+ c54: 4f00e6af movi v15.16b, #0x15
+ c58: 4f00e6cf movi v15.16b, #0x16
+ c5c: 4f00e6ef movi v15.16b, #0x17
+ c60: 4f00e70f movi v15.16b, #0x18
+ c64: 4f00e72f movi v15.16b, #0x19
+ c68: 4f00e74f movi v15.16b, #0x1a
+ c6c: 4f00e76f movi v15.16b, #0x1b
+ c70: 4f00e78f movi v15.16b, #0x1c
+ c74: 4f00e7af movi v15.16b, #0x1d
+ c78: 4f00e7cf movi v15.16b, #0x1e
+ c7c: 4f00e7ef movi v15.16b, #0x1f
+ c80: 4f01e40f movi v15.16b, #0x20
+ c84: 4f01e42f movi v15.16b, #0x21
+ c88: 4f01e44f movi v15.16b, #0x22
+ c8c: 4f01e46f movi v15.16b, #0x23
+ c90: 4f01e48f movi v15.16b, #0x24
+ c94: 4f01e4af movi v15.16b, #0x25
+ c98: 4f01e4cf movi v15.16b, #0x26
+ c9c: 4f01e4ef movi v15.16b, #0x27
+ ca0: 4f01e50f movi v15.16b, #0x28
+ ca4: 4f01e52f movi v15.16b, #0x29
+ ca8: 4f01e54f movi v15.16b, #0x2a
+ cac: 4f01e56f movi v15.16b, #0x2b
+ cb0: 4f01e58f movi v15.16b, #0x2c
+ cb4: 4f01e5af movi v15.16b, #0x2d
+ cb8: 4f01e5cf movi v15.16b, #0x2e
+ cbc: 4f01e5ef movi v15.16b, #0x2f
+ cc0: 4f01e60f movi v15.16b, #0x30
+ cc4: 4f01e62f movi v15.16b, #0x31
+ cc8: 4f01e64f movi v15.16b, #0x32
+ ccc: 4f01e66f movi v15.16b, #0x33
+ cd0: 4f01e68f movi v15.16b, #0x34
+ cd4: 4f01e6af movi v15.16b, #0x35
+ cd8: 4f01e6cf movi v15.16b, #0x36
+ cdc: 4f01e6ef movi v15.16b, #0x37
+ ce0: 4f01e70f movi v15.16b, #0x38
+ ce4: 4f01e72f movi v15.16b, #0x39
+ ce8: 4f01e74f movi v15.16b, #0x3a
+ cec: 4f01e76f movi v15.16b, #0x3b
+ cf0: 4f01e78f movi v15.16b, #0x3c
+ cf4: 4f01e7af movi v15.16b, #0x3d
+ cf8: 4f01e7cf movi v15.16b, #0x3e
+ cfc: 4f01e7ef movi v15.16b, #0x3f
+ d00: 4f02e40f movi v15.16b, #0x40
+ d04: 4f02e42f movi v15.16b, #0x41
+ d08: 4f02e44f movi v15.16b, #0x42
+ d0c: 4f02e46f movi v15.16b, #0x43
+ d10: 4f02e48f movi v15.16b, #0x44
+ d14: 4f02e4af movi v15.16b, #0x45
+ d18: 4f02e4cf movi v15.16b, #0x46
+ d1c: 4f02e4ef movi v15.16b, #0x47
+ d20: 4f02e50f movi v15.16b, #0x48
+ d24: 4f02e52f movi v15.16b, #0x49
+ d28: 4f02e54f movi v15.16b, #0x4a
+ d2c: 4f02e56f movi v15.16b, #0x4b
+ d30: 4f02e58f movi v15.16b, #0x4c
+ d34: 4f02e5af movi v15.16b, #0x4d
+ d38: 4f02e5cf movi v15.16b, #0x4e
+ d3c: 4f02e5ef movi v15.16b, #0x4f
+ d40: 4f02e60f movi v15.16b, #0x50
+ d44: 4f02e62f movi v15.16b, #0x51
+ d48: 4f02e64f movi v15.16b, #0x52
+ d4c: 4f02e66f movi v15.16b, #0x53
+ d50: 4f02e68f movi v15.16b, #0x54
+ d54: 4f02e6af movi v15.16b, #0x55
+ d58: 4f02e6cf movi v15.16b, #0x56
+ d5c: 4f02e6ef movi v15.16b, #0x57
+ d60: 4f02e70f movi v15.16b, #0x58
+ d64: 4f02e72f movi v15.16b, #0x59
+ d68: 4f02e74f movi v15.16b, #0x5a
+ d6c: 4f02e76f movi v15.16b, #0x5b
+ d70: 4f02e78f movi v15.16b, #0x5c
+ d74: 4f02e7af movi v15.16b, #0x5d
+ d78: 4f02e7cf movi v15.16b, #0x5e
+ d7c: 4f02e7ef movi v15.16b, #0x5f
+ d80: 4f03e40f movi v15.16b, #0x60
+ d84: 4f03e42f movi v15.16b, #0x61
+ d88: 4f03e44f movi v15.16b, #0x62
+ d8c: 4f03e46f movi v15.16b, #0x63
+ d90: 4f03e48f movi v15.16b, #0x64
+ d94: 4f03e4af movi v15.16b, #0x65
+ d98: 4f03e4cf movi v15.16b, #0x66
+ d9c: 4f03e4ef movi v15.16b, #0x67
+ da0: 4f03e50f movi v15.16b, #0x68
+ da4: 4f03e52f movi v15.16b, #0x69
+ da8: 4f03e54f movi v15.16b, #0x6a
+ dac: 4f03e56f movi v15.16b, #0x6b
+ db0: 4f03e58f movi v15.16b, #0x6c
+ db4: 4f03e5af movi v15.16b, #0x6d
+ db8: 4f03e5cf movi v15.16b, #0x6e
+ dbc: 4f03e5ef movi v15.16b, #0x6f
+ dc0: 4f03e60f movi v15.16b, #0x70
+ dc4: 4f03e62f movi v15.16b, #0x71
+ dc8: 4f03e64f movi v15.16b, #0x72
+ dcc: 4f03e66f movi v15.16b, #0x73
+ dd0: 4f03e68f movi v15.16b, #0x74
+ dd4: 4f03e6af movi v15.16b, #0x75
+ dd8: 4f03e6cf movi v15.16b, #0x76
+ ddc: 4f03e6ef movi v15.16b, #0x77
+ de0: 4f03e70f movi v15.16b, #0x78
+ de4: 4f03e72f movi v15.16b, #0x79
+ de8: 4f03e74f movi v15.16b, #0x7a
+ dec: 4f03e76f movi v15.16b, #0x7b
+ df0: 4f03e78f movi v15.16b, #0x7c
+ df4: 4f03e7af movi v15.16b, #0x7d
+ df8: 4f03e7cf movi v15.16b, #0x7e
+ dfc: 4f03e7ef movi v15.16b, #0x7f
+ e00: 4f04e40f movi v15.16b, #0x80
+ e04: 4f04e42f movi v15.16b, #0x81
+ e08: 4f04e44f movi v15.16b, #0x82
+ e0c: 4f04e46f movi v15.16b, #0x83
+ e10: 4f04e48f movi v15.16b, #0x84
+ e14: 4f04e4af movi v15.16b, #0x85
+ e18: 4f04e4cf movi v15.16b, #0x86
+ e1c: 4f04e4ef movi v15.16b, #0x87
+ e20: 4f04e50f movi v15.16b, #0x88
+ e24: 4f04e52f movi v15.16b, #0x89
+ e28: 4f04e54f movi v15.16b, #0x8a
+ e2c: 4f04e56f movi v15.16b, #0x8b
+ e30: 4f04e58f movi v15.16b, #0x8c
+ e34: 4f04e5af movi v15.16b, #0x8d
+ e38: 4f04e5cf movi v15.16b, #0x8e
+ e3c: 4f04e5ef movi v15.16b, #0x8f
+ e40: 4f04e60f movi v15.16b, #0x90
+ e44: 4f04e62f movi v15.16b, #0x91
+ e48: 4f04e64f movi v15.16b, #0x92
+ e4c: 4f04e66f movi v15.16b, #0x93
+ e50: 4f04e68f movi v15.16b, #0x94
+ e54: 4f04e6af movi v15.16b, #0x95
+ e58: 4f04e6cf movi v15.16b, #0x96
+ e5c: 4f04e6ef movi v15.16b, #0x97
+ e60: 4f04e70f movi v15.16b, #0x98
+ e64: 4f04e72f movi v15.16b, #0x99
+ e68: 4f04e74f movi v15.16b, #0x9a
+ e6c: 4f04e76f movi v15.16b, #0x9b
+ e70: 4f04e78f movi v15.16b, #0x9c
+ e74: 4f04e7af movi v15.16b, #0x9d
+ e78: 4f04e7cf movi v15.16b, #0x9e
+ e7c: 4f04e7ef movi v15.16b, #0x9f
+ e80: 4f05e40f movi v15.16b, #0xa0
+ e84: 4f05e42f movi v15.16b, #0xa1
+ e88: 4f05e44f movi v15.16b, #0xa2
+ e8c: 4f05e46f movi v15.16b, #0xa3
+ e90: 4f05e48f movi v15.16b, #0xa4
+ e94: 4f05e4af movi v15.16b, #0xa5
+ e98: 4f05e4cf movi v15.16b, #0xa6
+ e9c: 4f05e4ef movi v15.16b, #0xa7
+ ea0: 4f05e50f movi v15.16b, #0xa8
+ ea4: 4f05e52f movi v15.16b, #0xa9
+ ea8: 4f05e54f movi v15.16b, #0xaa
+ eac: 4f05e56f movi v15.16b, #0xab
+ eb0: 4f05e58f movi v15.16b, #0xac
+ eb4: 4f05e5af movi v15.16b, #0xad
+ eb8: 4f05e5cf movi v15.16b, #0xae
+ ebc: 4f05e5ef movi v15.16b, #0xaf
+ ec0: 4f05e60f movi v15.16b, #0xb0
+ ec4: 4f05e62f movi v15.16b, #0xb1
+ ec8: 4f05e64f movi v15.16b, #0xb2
+ ecc: 4f05e66f movi v15.16b, #0xb3
+ ed0: 4f05e68f movi v15.16b, #0xb4
+ ed4: 4f05e6af movi v15.16b, #0xb5
+ ed8: 4f05e6cf movi v15.16b, #0xb6
+ edc: 4f05e6ef movi v15.16b, #0xb7
+ ee0: 4f05e70f movi v15.16b, #0xb8
+ ee4: 4f05e72f movi v15.16b, #0xb9
+ ee8: 4f05e74f movi v15.16b, #0xba
+ eec: 4f05e76f movi v15.16b, #0xbb
+ ef0: 4f05e78f movi v15.16b, #0xbc
+ ef4: 4f05e7af movi v15.16b, #0xbd
+ ef8: 4f05e7cf movi v15.16b, #0xbe
+ efc: 4f05e7ef movi v15.16b, #0xbf
+ f00: 4f06e40f movi v15.16b, #0xc0
+ f04: 4f06e42f movi v15.16b, #0xc1
+ f08: 4f06e44f movi v15.16b, #0xc2
+ f0c: 4f06e46f movi v15.16b, #0xc3
+ f10: 4f06e48f movi v15.16b, #0xc4
+ f14: 4f06e4af movi v15.16b, #0xc5
+ f18: 4f06e4cf movi v15.16b, #0xc6
+ f1c: 4f06e4ef movi v15.16b, #0xc7
+ f20: 4f06e50f movi v15.16b, #0xc8
+ f24: 4f06e52f movi v15.16b, #0xc9
+ f28: 4f06e54f movi v15.16b, #0xca
+ f2c: 4f06e56f movi v15.16b, #0xcb
+ f30: 4f06e58f movi v15.16b, #0xcc
+ f34: 4f06e5af movi v15.16b, #0xcd
+ f38: 4f06e5cf movi v15.16b, #0xce
+ f3c: 4f06e5ef movi v15.16b, #0xcf
+ f40: 4f06e60f movi v15.16b, #0xd0
+ f44: 4f06e62f movi v15.16b, #0xd1
+ f48: 4f06e64f movi v15.16b, #0xd2
+ f4c: 4f06e66f movi v15.16b, #0xd3
+ f50: 4f06e68f movi v15.16b, #0xd4
+ f54: 4f06e6af movi v15.16b, #0xd5
+ f58: 4f06e6cf movi v15.16b, #0xd6
+ f5c: 4f06e6ef movi v15.16b, #0xd7
+ f60: 4f06e70f movi v15.16b, #0xd8
+ f64: 4f06e72f movi v15.16b, #0xd9
+ f68: 4f06e74f movi v15.16b, #0xda
+ f6c: 4f06e76f movi v15.16b, #0xdb
+ f70: 4f06e78f movi v15.16b, #0xdc
+ f74: 4f06e7af movi v15.16b, #0xdd
+ f78: 4f06e7cf movi v15.16b, #0xde
+ f7c: 4f06e7ef movi v15.16b, #0xdf
+ f80: 4f07e40f movi v15.16b, #0xe0
+ f84: 4f07e42f movi v15.16b, #0xe1
+ f88: 4f07e44f movi v15.16b, #0xe2
+ f8c: 4f07e46f movi v15.16b, #0xe3
+ f90: 4f07e48f movi v15.16b, #0xe4
+ f94: 4f07e4af movi v15.16b, #0xe5
+ f98: 4f07e4cf movi v15.16b, #0xe6
+ f9c: 4f07e4ef movi v15.16b, #0xe7
+ fa0: 4f07e50f movi v15.16b, #0xe8
+ fa4: 4f07e52f movi v15.16b, #0xe9
+ fa8: 4f07e54f movi v15.16b, #0xea
+ fac: 4f07e56f movi v15.16b, #0xeb
+ fb0: 4f07e58f movi v15.16b, #0xec
+ fb4: 4f07e5af movi v15.16b, #0xed
+ fb8: 4f07e5cf movi v15.16b, #0xee
+ fbc: 4f07e5ef movi v15.16b, #0xef
+ fc0: 4f07e60f movi v15.16b, #0xf0
+ fc4: 4f07e62f movi v15.16b, #0xf1
+ fc8: 4f07e64f movi v15.16b, #0xf2
+ fcc: 4f07e66f movi v15.16b, #0xf3
+ fd0: 4f07e68f movi v15.16b, #0xf4
+ fd4: 4f07e6af movi v15.16b, #0xf5
+ fd8: 4f07e6cf movi v15.16b, #0xf6
+ fdc: 4f07e6ef movi v15.16b, #0xf7
+ fe0: 4f07e70f movi v15.16b, #0xf8
+ fe4: 4f07e72f movi v15.16b, #0xf9
+ fe8: 4f07e74f movi v15.16b, #0xfa
+ fec: 4f07e76f movi v15.16b, #0xfb
+ ff0: 4f07e78f movi v15.16b, #0xfc
+ ff4: 4f07e7af movi v15.16b, #0xfd
+ ff8: 4f07e7cf movi v15.16b, #0xfe
+ ffc: 4f07e7ef movi v15.16b, #0xff
+ 1000: 0f00c407 movi v7.2s, #0x0, msl #8
+ 1004: 0f00c427 movi v7.2s, #0x1, msl #8
+ 1008: 0f00c447 movi v7.2s, #0x2, msl #8
+ 100c: 0f00c467 movi v7.2s, #0x3, msl #8
+ 1010: 0f00c487 movi v7.2s, #0x4, msl #8
+ 1014: 0f00c4a7 movi v7.2s, #0x5, msl #8
+ 1018: 0f00c4c7 movi v7.2s, #0x6, msl #8
+ 101c: 0f00c4e7 movi v7.2s, #0x7, msl #8
+ 1020: 0f00c507 movi v7.2s, #0x8, msl #8
+ 1024: 0f00c527 movi v7.2s, #0x9, msl #8
+ 1028: 0f00c547 movi v7.2s, #0xa, msl #8
+ 102c: 0f00c567 movi v7.2s, #0xb, msl #8
+ 1030: 0f00c587 movi v7.2s, #0xc, msl #8
+ 1034: 0f00c5a7 movi v7.2s, #0xd, msl #8
+ 1038: 0f00c5c7 movi v7.2s, #0xe, msl #8
+ 103c: 0f00c5e7 movi v7.2s, #0xf, msl #8
+ 1040: 0f00c607 movi v7.2s, #0x10, msl #8
+ 1044: 0f00c627 movi v7.2s, #0x11, msl #8
+ 1048: 0f00c647 movi v7.2s, #0x12, msl #8
+ 104c: 0f00c667 movi v7.2s, #0x13, msl #8
+ 1050: 0f00c687 movi v7.2s, #0x14, msl #8
+ 1054: 0f00c6a7 movi v7.2s, #0x15, msl #8
+ 1058: 0f00c6c7 movi v7.2s, #0x16, msl #8
+ 105c: 0f00c6e7 movi v7.2s, #0x17, msl #8
+ 1060: 0f00c707 movi v7.2s, #0x18, msl #8
+ 1064: 0f00c727 movi v7.2s, #0x19, msl #8
+ 1068: 0f00c747 movi v7.2s, #0x1a, msl #8
+ 106c: 0f00c767 movi v7.2s, #0x1b, msl #8
+ 1070: 0f00c787 movi v7.2s, #0x1c, msl #8
+ 1074: 0f00c7a7 movi v7.2s, #0x1d, msl #8
+ 1078: 0f00c7c7 movi v7.2s, #0x1e, msl #8
+ 107c: 0f00c7e7 movi v7.2s, #0x1f, msl #8
+ 1080: 0f01c407 movi v7.2s, #0x20, msl #8
+ 1084: 0f01c427 movi v7.2s, #0x21, msl #8
+ 1088: 0f01c447 movi v7.2s, #0x22, msl #8
+ 108c: 0f01c467 movi v7.2s, #0x23, msl #8
+ 1090: 0f01c487 movi v7.2s, #0x24, msl #8
+ 1094: 0f01c4a7 movi v7.2s, #0x25, msl #8
+ 1098: 0f01c4c7 movi v7.2s, #0x26, msl #8
+ 109c: 0f01c4e7 movi v7.2s, #0x27, msl #8
+ 10a0: 0f01c507 movi v7.2s, #0x28, msl #8
+ 10a4: 0f01c527 movi v7.2s, #0x29, msl #8
+ 10a8: 0f01c547 movi v7.2s, #0x2a, msl #8
+ 10ac: 0f01c567 movi v7.2s, #0x2b, msl #8
+ 10b0: 0f01c587 movi v7.2s, #0x2c, msl #8
+ 10b4: 0f01c5a7 movi v7.2s, #0x2d, msl #8
+ 10b8: 0f01c5c7 movi v7.2s, #0x2e, msl #8
+ 10bc: 0f01c5e7 movi v7.2s, #0x2f, msl #8
+ 10c0: 0f01c607 movi v7.2s, #0x30, msl #8
+ 10c4: 0f01c627 movi v7.2s, #0x31, msl #8
+ 10c8: 0f01c647 movi v7.2s, #0x32, msl #8
+ 10cc: 0f01c667 movi v7.2s, #0x33, msl #8
+ 10d0: 0f01c687 movi v7.2s, #0x34, msl #8
+ 10d4: 0f01c6a7 movi v7.2s, #0x35, msl #8
+ 10d8: 0f01c6c7 movi v7.2s, #0x36, msl #8
+ 10dc: 0f01c6e7 movi v7.2s, #0x37, msl #8
+ 10e0: 0f01c707 movi v7.2s, #0x38, msl #8
+ 10e4: 0f01c727 movi v7.2s, #0x39, msl #8
+ 10e8: 0f01c747 movi v7.2s, #0x3a, msl #8
+ 10ec: 0f01c767 movi v7.2s, #0x3b, msl #8
+ 10f0: 0f01c787 movi v7.2s, #0x3c, msl #8
+ 10f4: 0f01c7a7 movi v7.2s, #0x3d, msl #8
+ 10f8: 0f01c7c7 movi v7.2s, #0x3e, msl #8
+ 10fc: 0f01c7e7 movi v7.2s, #0x3f, msl #8
+ 1100: 0f02c407 movi v7.2s, #0x40, msl #8
+ 1104: 0f02c427 movi v7.2s, #0x41, msl #8
+ 1108: 0f02c447 movi v7.2s, #0x42, msl #8
+ 110c: 0f02c467 movi v7.2s, #0x43, msl #8
+ 1110: 0f02c487 movi v7.2s, #0x44, msl #8
+ 1114: 0f02c4a7 movi v7.2s, #0x45, msl #8
+ 1118: 0f02c4c7 movi v7.2s, #0x46, msl #8
+ 111c: 0f02c4e7 movi v7.2s, #0x47, msl #8
+ 1120: 0f02c507 movi v7.2s, #0x48, msl #8
+ 1124: 0f02c527 movi v7.2s, #0x49, msl #8
+ 1128: 0f02c547 movi v7.2s, #0x4a, msl #8
+ 112c: 0f02c567 movi v7.2s, #0x4b, msl #8
+ 1130: 0f02c587 movi v7.2s, #0x4c, msl #8
+ 1134: 0f02c5a7 movi v7.2s, #0x4d, msl #8
+ 1138: 0f02c5c7 movi v7.2s, #0x4e, msl #8
+ 113c: 0f02c5e7 movi v7.2s, #0x4f, msl #8
+ 1140: 0f02c607 movi v7.2s, #0x50, msl #8
+ 1144: 0f02c627 movi v7.2s, #0x51, msl #8
+ 1148: 0f02c647 movi v7.2s, #0x52, msl #8
+ 114c: 0f02c667 movi v7.2s, #0x53, msl #8
+ 1150: 0f02c687 movi v7.2s, #0x54, msl #8
+ 1154: 0f02c6a7 movi v7.2s, #0x55, msl #8
+ 1158: 0f02c6c7 movi v7.2s, #0x56, msl #8
+ 115c: 0f02c6e7 movi v7.2s, #0x57, msl #8
+ 1160: 0f02c707 movi v7.2s, #0x58, msl #8
+ 1164: 0f02c727 movi v7.2s, #0x59, msl #8
+ 1168: 0f02c747 movi v7.2s, #0x5a, msl #8
+ 116c: 0f02c767 movi v7.2s, #0x5b, msl #8
+ 1170: 0f02c787 movi v7.2s, #0x5c, msl #8
+ 1174: 0f02c7a7 movi v7.2s, #0x5d, msl #8
+ 1178: 0f02c7c7 movi v7.2s, #0x5e, msl #8
+ 117c: 0f02c7e7 movi v7.2s, #0x5f, msl #8
+ 1180: 0f03c407 movi v7.2s, #0x60, msl #8
+ 1184: 0f03c427 movi v7.2s, #0x61, msl #8
+ 1188: 0f03c447 movi v7.2s, #0x62, msl #8
+ 118c: 0f03c467 movi v7.2s, #0x63, msl #8
+ 1190: 0f03c487 movi v7.2s, #0x64, msl #8
+ 1194: 0f03c4a7 movi v7.2s, #0x65, msl #8
+ 1198: 0f03c4c7 movi v7.2s, #0x66, msl #8
+ 119c: 0f03c4e7 movi v7.2s, #0x67, msl #8
+ 11a0: 0f03c507 movi v7.2s, #0x68, msl #8
+ 11a4: 0f03c527 movi v7.2s, #0x69, msl #8
+ 11a8: 0f03c547 movi v7.2s, #0x6a, msl #8
+ 11ac: 0f03c567 movi v7.2s, #0x6b, msl #8
+ 11b0: 0f03c587 movi v7.2s, #0x6c, msl #8
+ 11b4: 0f03c5a7 movi v7.2s, #0x6d, msl #8
+ 11b8: 0f03c5c7 movi v7.2s, #0x6e, msl #8
+ 11bc: 0f03c5e7 movi v7.2s, #0x6f, msl #8
+ 11c0: 0f03c607 movi v7.2s, #0x70, msl #8
+ 11c4: 0f03c627 movi v7.2s, #0x71, msl #8
+ 11c8: 0f03c647 movi v7.2s, #0x72, msl #8
+ 11cc: 0f03c667 movi v7.2s, #0x73, msl #8
+ 11d0: 0f03c687 movi v7.2s, #0x74, msl #8
+ 11d4: 0f03c6a7 movi v7.2s, #0x75, msl #8
+ 11d8: 0f03c6c7 movi v7.2s, #0x76, msl #8
+ 11dc: 0f03c6e7 movi v7.2s, #0x77, msl #8
+ 11e0: 0f03c707 movi v7.2s, #0x78, msl #8
+ 11e4: 0f03c727 movi v7.2s, #0x79, msl #8
+ 11e8: 0f03c747 movi v7.2s, #0x7a, msl #8
+ 11ec: 0f03c767 movi v7.2s, #0x7b, msl #8
+ 11f0: 0f03c787 movi v7.2s, #0x7c, msl #8
+ 11f4: 0f03c7a7 movi v7.2s, #0x7d, msl #8
+ 11f8: 0f03c7c7 movi v7.2s, #0x7e, msl #8
+ 11fc: 0f03c7e7 movi v7.2s, #0x7f, msl #8
+ 1200: 0f04c407 movi v7.2s, #0x80, msl #8
+ 1204: 0f04c427 movi v7.2s, #0x81, msl #8
+ 1208: 0f04c447 movi v7.2s, #0x82, msl #8
+ 120c: 0f04c467 movi v7.2s, #0x83, msl #8
+ 1210: 0f04c487 movi v7.2s, #0x84, msl #8
+ 1214: 0f04c4a7 movi v7.2s, #0x85, msl #8
+ 1218: 0f04c4c7 movi v7.2s, #0x86, msl #8
+ 121c: 0f04c4e7 movi v7.2s, #0x87, msl #8
+ 1220: 0f04c507 movi v7.2s, #0x88, msl #8
+ 1224: 0f04c527 movi v7.2s, #0x89, msl #8
+ 1228: 0f04c547 movi v7.2s, #0x8a, msl #8
+ 122c: 0f04c567 movi v7.2s, #0x8b, msl #8
+ 1230: 0f04c587 movi v7.2s, #0x8c, msl #8
+ 1234: 0f04c5a7 movi v7.2s, #0x8d, msl #8
+ 1238: 0f04c5c7 movi v7.2s, #0x8e, msl #8
+ 123c: 0f04c5e7 movi v7.2s, #0x8f, msl #8
+ 1240: 0f04c607 movi v7.2s, #0x90, msl #8
+ 1244: 0f04c627 movi v7.2s, #0x91, msl #8
+ 1248: 0f04c647 movi v7.2s, #0x92, msl #8
+ 124c: 0f04c667 movi v7.2s, #0x93, msl #8
+ 1250: 0f04c687 movi v7.2s, #0x94, msl #8
+ 1254: 0f04c6a7 movi v7.2s, #0x95, msl #8
+ 1258: 0f04c6c7 movi v7.2s, #0x96, msl #8
+ 125c: 0f04c6e7 movi v7.2s, #0x97, msl #8
+ 1260: 0f04c707 movi v7.2s, #0x98, msl #8
+ 1264: 0f04c727 movi v7.2s, #0x99, msl #8
+ 1268: 0f04c747 movi v7.2s, #0x9a, msl #8
+ 126c: 0f04c767 movi v7.2s, #0x9b, msl #8
+ 1270: 0f04c787 movi v7.2s, #0x9c, msl #8
+ 1274: 0f04c7a7 movi v7.2s, #0x9d, msl #8
+ 1278: 0f04c7c7 movi v7.2s, #0x9e, msl #8
+ 127c: 0f04c7e7 movi v7.2s, #0x9f, msl #8
+ 1280: 0f05c407 movi v7.2s, #0xa0, msl #8
+ 1284: 0f05c427 movi v7.2s, #0xa1, msl #8
+ 1288: 0f05c447 movi v7.2s, #0xa2, msl #8
+ 128c: 0f05c467 movi v7.2s, #0xa3, msl #8
+ 1290: 0f05c487 movi v7.2s, #0xa4, msl #8
+ 1294: 0f05c4a7 movi v7.2s, #0xa5, msl #8
+ 1298: 0f05c4c7 movi v7.2s, #0xa6, msl #8
+ 129c: 0f05c4e7 movi v7.2s, #0xa7, msl #8
+ 12a0: 0f05c507 movi v7.2s, #0xa8, msl #8
+ 12a4: 0f05c527 movi v7.2s, #0xa9, msl #8
+ 12a8: 0f05c547 movi v7.2s, #0xaa, msl #8
+ 12ac: 0f05c567 movi v7.2s, #0xab, msl #8
+ 12b0: 0f05c587 movi v7.2s, #0xac, msl #8
+ 12b4: 0f05c5a7 movi v7.2s, #0xad, msl #8
+ 12b8: 0f05c5c7 movi v7.2s, #0xae, msl #8
+ 12bc: 0f05c5e7 movi v7.2s, #0xaf, msl #8
+ 12c0: 0f05c607 movi v7.2s, #0xb0, msl #8
+ 12c4: 0f05c627 movi v7.2s, #0xb1, msl #8
+ 12c8: 0f05c647 movi v7.2s, #0xb2, msl #8
+ 12cc: 0f05c667 movi v7.2s, #0xb3, msl #8
+ 12d0: 0f05c687 movi v7.2s, #0xb4, msl #8
+ 12d4: 0f05c6a7 movi v7.2s, #0xb5, msl #8
+ 12d8: 0f05c6c7 movi v7.2s, #0xb6, msl #8
+ 12dc: 0f05c6e7 movi v7.2s, #0xb7, msl #8
+ 12e0: 0f05c707 movi v7.2s, #0xb8, msl #8
+ 12e4: 0f05c727 movi v7.2s, #0xb9, msl #8
+ 12e8: 0f05c747 movi v7.2s, #0xba, msl #8
+ 12ec: 0f05c767 movi v7.2s, #0xbb, msl #8
+ 12f0: 0f05c787 movi v7.2s, #0xbc, msl #8
+ 12f4: 0f05c7a7 movi v7.2s, #0xbd, msl #8
+ 12f8: 0f05c7c7 movi v7.2s, #0xbe, msl #8
+ 12fc: 0f05c7e7 movi v7.2s, #0xbf, msl #8
+ 1300: 0f06c407 movi v7.2s, #0xc0, msl #8
+ 1304: 0f06c427 movi v7.2s, #0xc1, msl #8
+ 1308: 0f06c447 movi v7.2s, #0xc2, msl #8
+ 130c: 0f06c467 movi v7.2s, #0xc3, msl #8
+ 1310: 0f06c487 movi v7.2s, #0xc4, msl #8
+ 1314: 0f06c4a7 movi v7.2s, #0xc5, msl #8
+ 1318: 0f06c4c7 movi v7.2s, #0xc6, msl #8
+ 131c: 0f06c4e7 movi v7.2s, #0xc7, msl #8
+ 1320: 0f06c507 movi v7.2s, #0xc8, msl #8
+ 1324: 0f06c527 movi v7.2s, #0xc9, msl #8
+ 1328: 0f06c547 movi v7.2s, #0xca, msl #8
+ 132c: 0f06c567 movi v7.2s, #0xcb, msl #8
+ 1330: 0f06c587 movi v7.2s, #0xcc, msl #8
+ 1334: 0f06c5a7 movi v7.2s, #0xcd, msl #8
+ 1338: 0f06c5c7 movi v7.2s, #0xce, msl #8
+ 133c: 0f06c5e7 movi v7.2s, #0xcf, msl #8
+ 1340: 0f06c607 movi v7.2s, #0xd0, msl #8
+ 1344: 0f06c627 movi v7.2s, #0xd1, msl #8
+ 1348: 0f06c647 movi v7.2s, #0xd2, msl #8
+ 134c: 0f06c667 movi v7.2s, #0xd3, msl #8
+ 1350: 0f06c687 movi v7.2s, #0xd4, msl #8
+ 1354: 0f06c6a7 movi v7.2s, #0xd5, msl #8
+ 1358: 0f06c6c7 movi v7.2s, #0xd6, msl #8
+ 135c: 0f06c6e7 movi v7.2s, #0xd7, msl #8
+ 1360: 0f06c707 movi v7.2s, #0xd8, msl #8
+ 1364: 0f06c727 movi v7.2s, #0xd9, msl #8
+ 1368: 0f06c747 movi v7.2s, #0xda, msl #8
+ 136c: 0f06c767 movi v7.2s, #0xdb, msl #8
+ 1370: 0f06c787 movi v7.2s, #0xdc, msl #8
+ 1374: 0f06c7a7 movi v7.2s, #0xdd, msl #8
+ 1378: 0f06c7c7 movi v7.2s, #0xde, msl #8
+ 137c: 0f06c7e7 movi v7.2s, #0xdf, msl #8
+ 1380: 0f07c407 movi v7.2s, #0xe0, msl #8
+ 1384: 0f07c427 movi v7.2s, #0xe1, msl #8
+ 1388: 0f07c447 movi v7.2s, #0xe2, msl #8
+ 138c: 0f07c467 movi v7.2s, #0xe3, msl #8
+ 1390: 0f07c487 movi v7.2s, #0xe4, msl #8
+ 1394: 0f07c4a7 movi v7.2s, #0xe5, msl #8
+ 1398: 0f07c4c7 movi v7.2s, #0xe6, msl #8
+ 139c: 0f07c4e7 movi v7.2s, #0xe7, msl #8
+ 13a0: 0f07c507 movi v7.2s, #0xe8, msl #8
+ 13a4: 0f07c527 movi v7.2s, #0xe9, msl #8
+ 13a8: 0f07c547 movi v7.2s, #0xea, msl #8
+ 13ac: 0f07c567 movi v7.2s, #0xeb, msl #8
+ 13b0: 0f07c587 movi v7.2s, #0xec, msl #8
+ 13b4: 0f07c5a7 movi v7.2s, #0xed, msl #8
+ 13b8: 0f07c5c7 movi v7.2s, #0xee, msl #8
+ 13bc: 0f07c5e7 movi v7.2s, #0xef, msl #8
+ 13c0: 0f07c607 movi v7.2s, #0xf0, msl #8
+ 13c4: 0f07c627 movi v7.2s, #0xf1, msl #8
+ 13c8: 0f07c647 movi v7.2s, #0xf2, msl #8
+ 13cc: 0f07c667 movi v7.2s, #0xf3, msl #8
+ 13d0: 0f07c687 movi v7.2s, #0xf4, msl #8
+ 13d4: 0f07c6a7 movi v7.2s, #0xf5, msl #8
+ 13d8: 0f07c6c7 movi v7.2s, #0xf6, msl #8
+ 13dc: 0f07c6e7 movi v7.2s, #0xf7, msl #8
+ 13e0: 0f07c707 movi v7.2s, #0xf8, msl #8
+ 13e4: 0f07c727 movi v7.2s, #0xf9, msl #8
+ 13e8: 0f07c747 movi v7.2s, #0xfa, msl #8
+ 13ec: 0f07c767 movi v7.2s, #0xfb, msl #8
+ 13f0: 0f07c787 movi v7.2s, #0xfc, msl #8
+ 13f4: 0f07c7a7 movi v7.2s, #0xfd, msl #8
+ 13f8: 0f07c7c7 movi v7.2s, #0xfe, msl #8
+ 13fc: 0f07c7e7 movi v7.2s, #0xff, msl #8
+ 1400: 0f00d407 movi v7.2s, #0x0, msl #16
+ 1404: 0f00d427 movi v7.2s, #0x1, msl #16
+ 1408: 0f00d447 movi v7.2s, #0x2, msl #16
+ 140c: 0f00d467 movi v7.2s, #0x3, msl #16
+ 1410: 0f00d487 movi v7.2s, #0x4, msl #16
+ 1414: 0f00d4a7 movi v7.2s, #0x5, msl #16
+ 1418: 0f00d4c7 movi v7.2s, #0x6, msl #16
+ 141c: 0f00d4e7 movi v7.2s, #0x7, msl #16
+ 1420: 0f00d507 movi v7.2s, #0x8, msl #16
+ 1424: 0f00d527 movi v7.2s, #0x9, msl #16
+ 1428: 0f00d547 movi v7.2s, #0xa, msl #16
+ 142c: 0f00d567 movi v7.2s, #0xb, msl #16
+ 1430: 0f00d587 movi v7.2s, #0xc, msl #16
+ 1434: 0f00d5a7 movi v7.2s, #0xd, msl #16
+ 1438: 0f00d5c7 movi v7.2s, #0xe, msl #16
+ 143c: 0f00d5e7 movi v7.2s, #0xf, msl #16
+ 1440: 0f00d607 movi v7.2s, #0x10, msl #16
+ 1444: 0f00d627 movi v7.2s, #0x11, msl #16
+ 1448: 0f00d647 movi v7.2s, #0x12, msl #16
+ 144c: 0f00d667 movi v7.2s, #0x13, msl #16
+ 1450: 0f00d687 movi v7.2s, #0x14, msl #16
+ 1454: 0f00d6a7 movi v7.2s, #0x15, msl #16
+ 1458: 0f00d6c7 movi v7.2s, #0x16, msl #16
+ 145c: 0f00d6e7 movi v7.2s, #0x17, msl #16
+ 1460: 0f00d707 movi v7.2s, #0x18, msl #16
+ 1464: 0f00d727 movi v7.2s, #0x19, msl #16
+ 1468: 0f00d747 movi v7.2s, #0x1a, msl #16
+ 146c: 0f00d767 movi v7.2s, #0x1b, msl #16
+ 1470: 0f00d787 movi v7.2s, #0x1c, msl #16
+ 1474: 0f00d7a7 movi v7.2s, #0x1d, msl #16
+ 1478: 0f00d7c7 movi v7.2s, #0x1e, msl #16
+ 147c: 0f00d7e7 movi v7.2s, #0x1f, msl #16
+ 1480: 0f01d407 movi v7.2s, #0x20, msl #16
+ 1484: 0f01d427 movi v7.2s, #0x21, msl #16
+ 1488: 0f01d447 movi v7.2s, #0x22, msl #16
+ 148c: 0f01d467 movi v7.2s, #0x23, msl #16
+ 1490: 0f01d487 movi v7.2s, #0x24, msl #16
+ 1494: 0f01d4a7 movi v7.2s, #0x25, msl #16
+ 1498: 0f01d4c7 movi v7.2s, #0x26, msl #16
+ 149c: 0f01d4e7 movi v7.2s, #0x27, msl #16
+ 14a0: 0f01d507 movi v7.2s, #0x28, msl #16
+ 14a4: 0f01d527 movi v7.2s, #0x29, msl #16
+ 14a8: 0f01d547 movi v7.2s, #0x2a, msl #16
+ 14ac: 0f01d567 movi v7.2s, #0x2b, msl #16
+ 14b0: 0f01d587 movi v7.2s, #0x2c, msl #16
+ 14b4: 0f01d5a7 movi v7.2s, #0x2d, msl #16
+ 14b8: 0f01d5c7 movi v7.2s, #0x2e, msl #16
+ 14bc: 0f01d5e7 movi v7.2s, #0x2f, msl #16
+ 14c0: 0f01d607 movi v7.2s, #0x30, msl #16
+ 14c4: 0f01d627 movi v7.2s, #0x31, msl #16
+ 14c8: 0f01d647 movi v7.2s, #0x32, msl #16
+ 14cc: 0f01d667 movi v7.2s, #0x33, msl #16
+ 14d0: 0f01d687 movi v7.2s, #0x34, msl #16
+ 14d4: 0f01d6a7 movi v7.2s, #0x35, msl #16
+ 14d8: 0f01d6c7 movi v7.2s, #0x36, msl #16
+ 14dc: 0f01d6e7 movi v7.2s, #0x37, msl #16
+ 14e0: 0f01d707 movi v7.2s, #0x38, msl #16
+ 14e4: 0f01d727 movi v7.2s, #0x39, msl #16
+ 14e8: 0f01d747 movi v7.2s, #0x3a, msl #16
+ 14ec: 0f01d767 movi v7.2s, #0x3b, msl #16
+ 14f0: 0f01d787 movi v7.2s, #0x3c, msl #16
+ 14f4: 0f01d7a7 movi v7.2s, #0x3d, msl #16
+ 14f8: 0f01d7c7 movi v7.2s, #0x3e, msl #16
+ 14fc: 0f01d7e7 movi v7.2s, #0x3f, msl #16
+ 1500: 0f02d407 movi v7.2s, #0x40, msl #16
+ 1504: 0f02d427 movi v7.2s, #0x41, msl #16
+ 1508: 0f02d447 movi v7.2s, #0x42, msl #16
+ 150c: 0f02d467 movi v7.2s, #0x43, msl #16
+ 1510: 0f02d487 movi v7.2s, #0x44, msl #16
+ 1514: 0f02d4a7 movi v7.2s, #0x45, msl #16
+ 1518: 0f02d4c7 movi v7.2s, #0x46, msl #16
+ 151c: 0f02d4e7 movi v7.2s, #0x47, msl #16
+ 1520: 0f02d507 movi v7.2s, #0x48, msl #16
+ 1524: 0f02d527 movi v7.2s, #0x49, msl #16
+ 1528: 0f02d547 movi v7.2s, #0x4a, msl #16
+ 152c: 0f02d567 movi v7.2s, #0x4b, msl #16
+ 1530: 0f02d587 movi v7.2s, #0x4c, msl #16
+ 1534: 0f02d5a7 movi v7.2s, #0x4d, msl #16
+ 1538: 0f02d5c7 movi v7.2s, #0x4e, msl #16
+ 153c: 0f02d5e7 movi v7.2s, #0x4f, msl #16
+ 1540: 0f02d607 movi v7.2s, #0x50, msl #16
+ 1544: 0f02d627 movi v7.2s, #0x51, msl #16
+ 1548: 0f02d647 movi v7.2s, #0x52, msl #16
+ 154c: 0f02d667 movi v7.2s, #0x53, msl #16
+ 1550: 0f02d687 movi v7.2s, #0x54, msl #16
+ 1554: 0f02d6a7 movi v7.2s, #0x55, msl #16
+ 1558: 0f02d6c7 movi v7.2s, #0x56, msl #16
+ 155c: 0f02d6e7 movi v7.2s, #0x57, msl #16
+ 1560: 0f02d707 movi v7.2s, #0x58, msl #16
+ 1564: 0f02d727 movi v7.2s, #0x59, msl #16
+ 1568: 0f02d747 movi v7.2s, #0x5a, msl #16
+ 156c: 0f02d767 movi v7.2s, #0x5b, msl #16
+ 1570: 0f02d787 movi v7.2s, #0x5c, msl #16
+ 1574: 0f02d7a7 movi v7.2s, #0x5d, msl #16
+ 1578: 0f02d7c7 movi v7.2s, #0x5e, msl #16
+ 157c: 0f02d7e7 movi v7.2s, #0x5f, msl #16
+ 1580: 0f03d407 movi v7.2s, #0x60, msl #16
+ 1584: 0f03d427 movi v7.2s, #0x61, msl #16
+ 1588: 0f03d447 movi v7.2s, #0x62, msl #16
+ 158c: 0f03d467 movi v7.2s, #0x63, msl #16
+ 1590: 0f03d487 movi v7.2s, #0x64, msl #16
+ 1594: 0f03d4a7 movi v7.2s, #0x65, msl #16
+ 1598: 0f03d4c7 movi v7.2s, #0x66, msl #16
+ 159c: 0f03d4e7 movi v7.2s, #0x67, msl #16
+ 15a0: 0f03d507 movi v7.2s, #0x68, msl #16
+ 15a4: 0f03d527 movi v7.2s, #0x69, msl #16
+ 15a8: 0f03d547 movi v7.2s, #0x6a, msl #16
+ 15ac: 0f03d567 movi v7.2s, #0x6b, msl #16
+ 15b0: 0f03d587 movi v7.2s, #0x6c, msl #16
+ 15b4: 0f03d5a7 movi v7.2s, #0x6d, msl #16
+ 15b8: 0f03d5c7 movi v7.2s, #0x6e, msl #16
+ 15bc: 0f03d5e7 movi v7.2s, #0x6f, msl #16
+ 15c0: 0f03d607 movi v7.2s, #0x70, msl #16
+ 15c4: 0f03d627 movi v7.2s, #0x71, msl #16
+ 15c8: 0f03d647 movi v7.2s, #0x72, msl #16
+ 15cc: 0f03d667 movi v7.2s, #0x73, msl #16
+ 15d0: 0f03d687 movi v7.2s, #0x74, msl #16
+ 15d4: 0f03d6a7 movi v7.2s, #0x75, msl #16
+ 15d8: 0f03d6c7 movi v7.2s, #0x76, msl #16
+ 15dc: 0f03d6e7 movi v7.2s, #0x77, msl #16
+ 15e0: 0f03d707 movi v7.2s, #0x78, msl #16
+ 15e4: 0f03d727 movi v7.2s, #0x79, msl #16
+ 15e8: 0f03d747 movi v7.2s, #0x7a, msl #16
+ 15ec: 0f03d767 movi v7.2s, #0x7b, msl #16
+ 15f0: 0f03d787 movi v7.2s, #0x7c, msl #16
+ 15f4: 0f03d7a7 movi v7.2s, #0x7d, msl #16
+ 15f8: 0f03d7c7 movi v7.2s, #0x7e, msl #16
+ 15fc: 0f03d7e7 movi v7.2s, #0x7f, msl #16
+ 1600: 0f04d407 movi v7.2s, #0x80, msl #16
+ 1604: 0f04d427 movi v7.2s, #0x81, msl #16
+ 1608: 0f04d447 movi v7.2s, #0x82, msl #16
+ 160c: 0f04d467 movi v7.2s, #0x83, msl #16
+ 1610: 0f04d487 movi v7.2s, #0x84, msl #16
+ 1614: 0f04d4a7 movi v7.2s, #0x85, msl #16
+ 1618: 0f04d4c7 movi v7.2s, #0x86, msl #16
+ 161c: 0f04d4e7 movi v7.2s, #0x87, msl #16
+ 1620: 0f04d507 movi v7.2s, #0x88, msl #16
+ 1624: 0f04d527 movi v7.2s, #0x89, msl #16
+ 1628: 0f04d547 movi v7.2s, #0x8a, msl #16
+ 162c: 0f04d567 movi v7.2s, #0x8b, msl #16
+ 1630: 0f04d587 movi v7.2s, #0x8c, msl #16
+ 1634: 0f04d5a7 movi v7.2s, #0x8d, msl #16
+ 1638: 0f04d5c7 movi v7.2s, #0x8e, msl #16
+ 163c: 0f04d5e7 movi v7.2s, #0x8f, msl #16
+ 1640: 0f04d607 movi v7.2s, #0x90, msl #16
+ 1644: 0f04d627 movi v7.2s, #0x91, msl #16
+ 1648: 0f04d647 movi v7.2s, #0x92, msl #16
+ 164c: 0f04d667 movi v7.2s, #0x93, msl #16
+ 1650: 0f04d687 movi v7.2s, #0x94, msl #16
+ 1654: 0f04d6a7 movi v7.2s, #0x95, msl #16
+ 1658: 0f04d6c7 movi v7.2s, #0x96, msl #16
+ 165c: 0f04d6e7 movi v7.2s, #0x97, msl #16
+ 1660: 0f04d707 movi v7.2s, #0x98, msl #16
+ 1664: 0f04d727 movi v7.2s, #0x99, msl #16
+ 1668: 0f04d747 movi v7.2s, #0x9a, msl #16
+ 166c: 0f04d767 movi v7.2s, #0x9b, msl #16
+ 1670: 0f04d787 movi v7.2s, #0x9c, msl #16
+ 1674: 0f04d7a7 movi v7.2s, #0x9d, msl #16
+ 1678: 0f04d7c7 movi v7.2s, #0x9e, msl #16
+ 167c: 0f04d7e7 movi v7.2s, #0x9f, msl #16
+ 1680: 0f05d407 movi v7.2s, #0xa0, msl #16
+ 1684: 0f05d427 movi v7.2s, #0xa1, msl #16
+ 1688: 0f05d447 movi v7.2s, #0xa2, msl #16
+ 168c: 0f05d467 movi v7.2s, #0xa3, msl #16
+ 1690: 0f05d487 movi v7.2s, #0xa4, msl #16
+ 1694: 0f05d4a7 movi v7.2s, #0xa5, msl #16
+ 1698: 0f05d4c7 movi v7.2s, #0xa6, msl #16
+ 169c: 0f05d4e7 movi v7.2s, #0xa7, msl #16
+ 16a0: 0f05d507 movi v7.2s, #0xa8, msl #16
+ 16a4: 0f05d527 movi v7.2s, #0xa9, msl #16
+ 16a8: 0f05d547 movi v7.2s, #0xaa, msl #16
+ 16ac: 0f05d567 movi v7.2s, #0xab, msl #16
+ 16b0: 0f05d587 movi v7.2s, #0xac, msl #16
+ 16b4: 0f05d5a7 movi v7.2s, #0xad, msl #16
+ 16b8: 0f05d5c7 movi v7.2s, #0xae, msl #16
+ 16bc: 0f05d5e7 movi v7.2s, #0xaf, msl #16
+ 16c0: 0f05d607 movi v7.2s, #0xb0, msl #16
+ 16c4: 0f05d627 movi v7.2s, #0xb1, msl #16
+ 16c8: 0f05d647 movi v7.2s, #0xb2, msl #16
+ 16cc: 0f05d667 movi v7.2s, #0xb3, msl #16
+ 16d0: 0f05d687 movi v7.2s, #0xb4, msl #16
+ 16d4: 0f05d6a7 movi v7.2s, #0xb5, msl #16
+ 16d8: 0f05d6c7 movi v7.2s, #0xb6, msl #16
+ 16dc: 0f05d6e7 movi v7.2s, #0xb7, msl #16
+ 16e0: 0f05d707 movi v7.2s, #0xb8, msl #16
+ 16e4: 0f05d727 movi v7.2s, #0xb9, msl #16
+ 16e8: 0f05d747 movi v7.2s, #0xba, msl #16
+ 16ec: 0f05d767 movi v7.2s, #0xbb, msl #16
+ 16f0: 0f05d787 movi v7.2s, #0xbc, msl #16
+ 16f4: 0f05d7a7 movi v7.2s, #0xbd, msl #16
+ 16f8: 0f05d7c7 movi v7.2s, #0xbe, msl #16
+ 16fc: 0f05d7e7 movi v7.2s, #0xbf, msl #16
+ 1700: 0f06d407 movi v7.2s, #0xc0, msl #16
+ 1704: 0f06d427 movi v7.2s, #0xc1, msl #16
+ 1708: 0f06d447 movi v7.2s, #0xc2, msl #16
+ 170c: 0f06d467 movi v7.2s, #0xc3, msl #16
+ 1710: 0f06d487 movi v7.2s, #0xc4, msl #16
+ 1714: 0f06d4a7 movi v7.2s, #0xc5, msl #16
+ 1718: 0f06d4c7 movi v7.2s, #0xc6, msl #16
+ 171c: 0f06d4e7 movi v7.2s, #0xc7, msl #16
+ 1720: 0f06d507 movi v7.2s, #0xc8, msl #16
+ 1724: 0f06d527 movi v7.2s, #0xc9, msl #16
+ 1728: 0f06d547 movi v7.2s, #0xca, msl #16
+ 172c: 0f06d567 movi v7.2s, #0xcb, msl #16
+ 1730: 0f06d587 movi v7.2s, #0xcc, msl #16
+ 1734: 0f06d5a7 movi v7.2s, #0xcd, msl #16
+ 1738: 0f06d5c7 movi v7.2s, #0xce, msl #16
+ 173c: 0f06d5e7 movi v7.2s, #0xcf, msl #16
+ 1740: 0f06d607 movi v7.2s, #0xd0, msl #16
+ 1744: 0f06d627 movi v7.2s, #0xd1, msl #16
+ 1748: 0f06d647 movi v7.2s, #0xd2, msl #16
+ 174c: 0f06d667 movi v7.2s, #0xd3, msl #16
+ 1750: 0f06d687 movi v7.2s, #0xd4, msl #16
+ 1754: 0f06d6a7 movi v7.2s, #0xd5, msl #16
+ 1758: 0f06d6c7 movi v7.2s, #0xd6, msl #16
+ 175c: 0f06d6e7 movi v7.2s, #0xd7, msl #16
+ 1760: 0f06d707 movi v7.2s, #0xd8, msl #16
+ 1764: 0f06d727 movi v7.2s, #0xd9, msl #16
+ 1768: 0f06d747 movi v7.2s, #0xda, msl #16
+ 176c: 0f06d767 movi v7.2s, #0xdb, msl #16
+ 1770: 0f06d787 movi v7.2s, #0xdc, msl #16
+ 1774: 0f06d7a7 movi v7.2s, #0xdd, msl #16
+ 1778: 0f06d7c7 movi v7.2s, #0xde, msl #16
+ 177c: 0f06d7e7 movi v7.2s, #0xdf, msl #16
+ 1780: 0f07d407 movi v7.2s, #0xe0, msl #16
+ 1784: 0f07d427 movi v7.2s, #0xe1, msl #16
+ 1788: 0f07d447 movi v7.2s, #0xe2, msl #16
+ 178c: 0f07d467 movi v7.2s, #0xe3, msl #16
+ 1790: 0f07d487 movi v7.2s, #0xe4, msl #16
+ 1794: 0f07d4a7 movi v7.2s, #0xe5, msl #16
+ 1798: 0f07d4c7 movi v7.2s, #0xe6, msl #16
+ 179c: 0f07d4e7 movi v7.2s, #0xe7, msl #16
+ 17a0: 0f07d507 movi v7.2s, #0xe8, msl #16
+ 17a4: 0f07d527 movi v7.2s, #0xe9, msl #16
+ 17a8: 0f07d547 movi v7.2s, #0xea, msl #16
+ 17ac: 0f07d567 movi v7.2s, #0xeb, msl #16
+ 17b0: 0f07d587 movi v7.2s, #0xec, msl #16
+ 17b4: 0f07d5a7 movi v7.2s, #0xed, msl #16
+ 17b8: 0f07d5c7 movi v7.2s, #0xee, msl #16
+ 17bc: 0f07d5e7 movi v7.2s, #0xef, msl #16
+ 17c0: 0f07d607 movi v7.2s, #0xf0, msl #16
+ 17c4: 0f07d627 movi v7.2s, #0xf1, msl #16
+ 17c8: 0f07d647 movi v7.2s, #0xf2, msl #16
+ 17cc: 0f07d667 movi v7.2s, #0xf3, msl #16
+ 17d0: 0f07d687 movi v7.2s, #0xf4, msl #16
+ 17d4: 0f07d6a7 movi v7.2s, #0xf5, msl #16
+ 17d8: 0f07d6c7 movi v7.2s, #0xf6, msl #16
+ 17dc: 0f07d6e7 movi v7.2s, #0xf7, msl #16
+ 17e0: 0f07d707 movi v7.2s, #0xf8, msl #16
+ 17e4: 0f07d727 movi v7.2s, #0xf9, msl #16
+ 17e8: 0f07d747 movi v7.2s, #0xfa, msl #16
+ 17ec: 0f07d767 movi v7.2s, #0xfb, msl #16
+ 17f0: 0f07d787 movi v7.2s, #0xfc, msl #16
+ 17f4: 0f07d7a7 movi v7.2s, #0xfd, msl #16
+ 17f8: 0f07d7c7 movi v7.2s, #0xfe, msl #16
+ 17fc: 0f07d7e7 movi v7.2s, #0xff, msl #16
+ 1800: 4f00c407 movi v7.4s, #0x0, msl #8
+ 1804: 4f00c427 movi v7.4s, #0x1, msl #8
+ 1808: 4f00c447 movi v7.4s, #0x2, msl #8
+ 180c: 4f00c467 movi v7.4s, #0x3, msl #8
+ 1810: 4f00c487 movi v7.4s, #0x4, msl #8
+ 1814: 4f00c4a7 movi v7.4s, #0x5, msl #8
+ 1818: 4f00c4c7 movi v7.4s, #0x6, msl #8
+ 181c: 4f00c4e7 movi v7.4s, #0x7, msl #8
+ 1820: 4f00c507 movi v7.4s, #0x8, msl #8
+ 1824: 4f00c527 movi v7.4s, #0x9, msl #8
+ 1828: 4f00c547 movi v7.4s, #0xa, msl #8
+ 182c: 4f00c567 movi v7.4s, #0xb, msl #8
+ 1830: 4f00c587 movi v7.4s, #0xc, msl #8
+ 1834: 4f00c5a7 movi v7.4s, #0xd, msl #8
+ 1838: 4f00c5c7 movi v7.4s, #0xe, msl #8
+ 183c: 4f00c5e7 movi v7.4s, #0xf, msl #8
+ 1840: 4f00c607 movi v7.4s, #0x10, msl #8
+ 1844: 4f00c627 movi v7.4s, #0x11, msl #8
+ 1848: 4f00c647 movi v7.4s, #0x12, msl #8
+ 184c: 4f00c667 movi v7.4s, #0x13, msl #8
+ 1850: 4f00c687 movi v7.4s, #0x14, msl #8
+ 1854: 4f00c6a7 movi v7.4s, #0x15, msl #8
+ 1858: 4f00c6c7 movi v7.4s, #0x16, msl #8
+ 185c: 4f00c6e7 movi v7.4s, #0x17, msl #8
+ 1860: 4f00c707 movi v7.4s, #0x18, msl #8
+ 1864: 4f00c727 movi v7.4s, #0x19, msl #8
+ 1868: 4f00c747 movi v7.4s, #0x1a, msl #8
+ 186c: 4f00c767 movi v7.4s, #0x1b, msl #8
+ 1870: 4f00c787 movi v7.4s, #0x1c, msl #8
+ 1874: 4f00c7a7 movi v7.4s, #0x1d, msl #8
+ 1878: 4f00c7c7 movi v7.4s, #0x1e, msl #8
+ 187c: 4f00c7e7 movi v7.4s, #0x1f, msl #8
+ 1880: 4f01c407 movi v7.4s, #0x20, msl #8
+ 1884: 4f01c427 movi v7.4s, #0x21, msl #8
+ 1888: 4f01c447 movi v7.4s, #0x22, msl #8
+ 188c: 4f01c467 movi v7.4s, #0x23, msl #8
+ 1890: 4f01c487 movi v7.4s, #0x24, msl #8
+ 1894: 4f01c4a7 movi v7.4s, #0x25, msl #8
+ 1898: 4f01c4c7 movi v7.4s, #0x26, msl #8
+ 189c: 4f01c4e7 movi v7.4s, #0x27, msl #8
+ 18a0: 4f01c507 movi v7.4s, #0x28, msl #8
+ 18a4: 4f01c527 movi v7.4s, #0x29, msl #8
+ 18a8: 4f01c547 movi v7.4s, #0x2a, msl #8
+ 18ac: 4f01c567 movi v7.4s, #0x2b, msl #8
+ 18b0: 4f01c587 movi v7.4s, #0x2c, msl #8
+ 18b4: 4f01c5a7 movi v7.4s, #0x2d, msl #8
+ 18b8: 4f01c5c7 movi v7.4s, #0x2e, msl #8
+ 18bc: 4f01c5e7 movi v7.4s, #0x2f, msl #8
+ 18c0: 4f01c607 movi v7.4s, #0x30, msl #8
+ 18c4: 4f01c627 movi v7.4s, #0x31, msl #8
+ 18c8: 4f01c647 movi v7.4s, #0x32, msl #8
+ 18cc: 4f01c667 movi v7.4s, #0x33, msl #8
+ 18d0: 4f01c687 movi v7.4s, #0x34, msl #8
+ 18d4: 4f01c6a7 movi v7.4s, #0x35, msl #8
+ 18d8: 4f01c6c7 movi v7.4s, #0x36, msl #8
+ 18dc: 4f01c6e7 movi v7.4s, #0x37, msl #8
+ 18e0: 4f01c707 movi v7.4s, #0x38, msl #8
+ 18e4: 4f01c727 movi v7.4s, #0x39, msl #8
+ 18e8: 4f01c747 movi v7.4s, #0x3a, msl #8
+ 18ec: 4f01c767 movi v7.4s, #0x3b, msl #8
+ 18f0: 4f01c787 movi v7.4s, #0x3c, msl #8
+ 18f4: 4f01c7a7 movi v7.4s, #0x3d, msl #8
+ 18f8: 4f01c7c7 movi v7.4s, #0x3e, msl #8
+ 18fc: 4f01c7e7 movi v7.4s, #0x3f, msl #8
+ 1900: 4f02c407 movi v7.4s, #0x40, msl #8
+ 1904: 4f02c427 movi v7.4s, #0x41, msl #8
+ 1908: 4f02c447 movi v7.4s, #0x42, msl #8
+ 190c: 4f02c467 movi v7.4s, #0x43, msl #8
+ 1910: 4f02c487 movi v7.4s, #0x44, msl #8
+ 1914: 4f02c4a7 movi v7.4s, #0x45, msl #8
+ 1918: 4f02c4c7 movi v7.4s, #0x46, msl #8
+ 191c: 4f02c4e7 movi v7.4s, #0x47, msl #8
+ 1920: 4f02c507 movi v7.4s, #0x48, msl #8
+ 1924: 4f02c527 movi v7.4s, #0x49, msl #8
+ 1928: 4f02c547 movi v7.4s, #0x4a, msl #8
+ 192c: 4f02c567 movi v7.4s, #0x4b, msl #8
+ 1930: 4f02c587 movi v7.4s, #0x4c, msl #8
+ 1934: 4f02c5a7 movi v7.4s, #0x4d, msl #8
+ 1938: 4f02c5c7 movi v7.4s, #0x4e, msl #8
+ 193c: 4f02c5e7 movi v7.4s, #0x4f, msl #8
+ 1940: 4f02c607 movi v7.4s, #0x50, msl #8
+ 1944: 4f02c627 movi v7.4s, #0x51, msl #8
+ 1948: 4f02c647 movi v7.4s, #0x52, msl #8
+ 194c: 4f02c667 movi v7.4s, #0x53, msl #8
+ 1950: 4f02c687 movi v7.4s, #0x54, msl #8
+ 1954: 4f02c6a7 movi v7.4s, #0x55, msl #8
+ 1958: 4f02c6c7 movi v7.4s, #0x56, msl #8
+ 195c: 4f02c6e7 movi v7.4s, #0x57, msl #8
+ 1960: 4f02c707 movi v7.4s, #0x58, msl #8
+ 1964: 4f02c727 movi v7.4s, #0x59, msl #8
+ 1968: 4f02c747 movi v7.4s, #0x5a, msl #8
+ 196c: 4f02c767 movi v7.4s, #0x5b, msl #8
+ 1970: 4f02c787 movi v7.4s, #0x5c, msl #8
+ 1974: 4f02c7a7 movi v7.4s, #0x5d, msl #8
+ 1978: 4f02c7c7 movi v7.4s, #0x5e, msl #8
+ 197c: 4f02c7e7 movi v7.4s, #0x5f, msl #8
+ 1980: 4f03c407 movi v7.4s, #0x60, msl #8
+ 1984: 4f03c427 movi v7.4s, #0x61, msl #8
+ 1988: 4f03c447 movi v7.4s, #0x62, msl #8
+ 198c: 4f03c467 movi v7.4s, #0x63, msl #8
+ 1990: 4f03c487 movi v7.4s, #0x64, msl #8
+ 1994: 4f03c4a7 movi v7.4s, #0x65, msl #8
+ 1998: 4f03c4c7 movi v7.4s, #0x66, msl #8
+ 199c: 4f03c4e7 movi v7.4s, #0x67, msl #8
+ 19a0: 4f03c507 movi v7.4s, #0x68, msl #8
+ 19a4: 4f03c527 movi v7.4s, #0x69, msl #8
+ 19a8: 4f03c547 movi v7.4s, #0x6a, msl #8
+ 19ac: 4f03c567 movi v7.4s, #0x6b, msl #8
+ 19b0: 4f03c587 movi v7.4s, #0x6c, msl #8
+ 19b4: 4f03c5a7 movi v7.4s, #0x6d, msl #8
+ 19b8: 4f03c5c7 movi v7.4s, #0x6e, msl #8
+ 19bc: 4f03c5e7 movi v7.4s, #0x6f, msl #8
+ 19c0: 4f03c607 movi v7.4s, #0x70, msl #8
+ 19c4: 4f03c627 movi v7.4s, #0x71, msl #8
+ 19c8: 4f03c647 movi v7.4s, #0x72, msl #8
+ 19cc: 4f03c667 movi v7.4s, #0x73, msl #8
+ 19d0: 4f03c687 movi v7.4s, #0x74, msl #8
+ 19d4: 4f03c6a7 movi v7.4s, #0x75, msl #8
+ 19d8: 4f03c6c7 movi v7.4s, #0x76, msl #8
+ 19dc: 4f03c6e7 movi v7.4s, #0x77, msl #8
+ 19e0: 4f03c707 movi v7.4s, #0x78, msl #8
+ 19e4: 4f03c727 movi v7.4s, #0x79, msl #8
+ 19e8: 4f03c747 movi v7.4s, #0x7a, msl #8
+ 19ec: 4f03c767 movi v7.4s, #0x7b, msl #8
+ 19f0: 4f03c787 movi v7.4s, #0x7c, msl #8
+ 19f4: 4f03c7a7 movi v7.4s, #0x7d, msl #8
+ 19f8: 4f03c7c7 movi v7.4s, #0x7e, msl #8
+ 19fc: 4f03c7e7 movi v7.4s, #0x7f, msl #8
+ 1a00: 4f04c407 movi v7.4s, #0x80, msl #8
+ 1a04: 4f04c427 movi v7.4s, #0x81, msl #8
+ 1a08: 4f04c447 movi v7.4s, #0x82, msl #8
+ 1a0c: 4f04c467 movi v7.4s, #0x83, msl #8
+ 1a10: 4f04c487 movi v7.4s, #0x84, msl #8
+ 1a14: 4f04c4a7 movi v7.4s, #0x85, msl #8
+ 1a18: 4f04c4c7 movi v7.4s, #0x86, msl #8
+ 1a1c: 4f04c4e7 movi v7.4s, #0x87, msl #8
+ 1a20: 4f04c507 movi v7.4s, #0x88, msl #8
+ 1a24: 4f04c527 movi v7.4s, #0x89, msl #8
+ 1a28: 4f04c547 movi v7.4s, #0x8a, msl #8
+ 1a2c: 4f04c567 movi v7.4s, #0x8b, msl #8
+ 1a30: 4f04c587 movi v7.4s, #0x8c, msl #8
+ 1a34: 4f04c5a7 movi v7.4s, #0x8d, msl #8
+ 1a38: 4f04c5c7 movi v7.4s, #0x8e, msl #8
+ 1a3c: 4f04c5e7 movi v7.4s, #0x8f, msl #8
+ 1a40: 4f04c607 movi v7.4s, #0x90, msl #8
+ 1a44: 4f04c627 movi v7.4s, #0x91, msl #8
+ 1a48: 4f04c647 movi v7.4s, #0x92, msl #8
+ 1a4c: 4f04c667 movi v7.4s, #0x93, msl #8
+ 1a50: 4f04c687 movi v7.4s, #0x94, msl #8
+ 1a54: 4f04c6a7 movi v7.4s, #0x95, msl #8
+ 1a58: 4f04c6c7 movi v7.4s, #0x96, msl #8
+ 1a5c: 4f04c6e7 movi v7.4s, #0x97, msl #8
+ 1a60: 4f04c707 movi v7.4s, #0x98, msl #8
+ 1a64: 4f04c727 movi v7.4s, #0x99, msl #8
+ 1a68: 4f04c747 movi v7.4s, #0x9a, msl #8
+ 1a6c: 4f04c767 movi v7.4s, #0x9b, msl #8
+ 1a70: 4f04c787 movi v7.4s, #0x9c, msl #8
+ 1a74: 4f04c7a7 movi v7.4s, #0x9d, msl #8
+ 1a78: 4f04c7c7 movi v7.4s, #0x9e, msl #8
+ 1a7c: 4f04c7e7 movi v7.4s, #0x9f, msl #8
+ 1a80: 4f05c407 movi v7.4s, #0xa0, msl #8
+ 1a84: 4f05c427 movi v7.4s, #0xa1, msl #8
+ 1a88: 4f05c447 movi v7.4s, #0xa2, msl #8
+ 1a8c: 4f05c467 movi v7.4s, #0xa3, msl #8
+ 1a90: 4f05c487 movi v7.4s, #0xa4, msl #8
+ 1a94: 4f05c4a7 movi v7.4s, #0xa5, msl #8
+ 1a98: 4f05c4c7 movi v7.4s, #0xa6, msl #8
+ 1a9c: 4f05c4e7 movi v7.4s, #0xa7, msl #8
+ 1aa0: 4f05c507 movi v7.4s, #0xa8, msl #8
+ 1aa4: 4f05c527 movi v7.4s, #0xa9, msl #8
+ 1aa8: 4f05c547 movi v7.4s, #0xaa, msl #8
+ 1aac: 4f05c567 movi v7.4s, #0xab, msl #8
+ 1ab0: 4f05c587 movi v7.4s, #0xac, msl #8
+ 1ab4: 4f05c5a7 movi v7.4s, #0xad, msl #8
+ 1ab8: 4f05c5c7 movi v7.4s, #0xae, msl #8
+ 1abc: 4f05c5e7 movi v7.4s, #0xaf, msl #8
+ 1ac0: 4f05c607 movi v7.4s, #0xb0, msl #8
+ 1ac4: 4f05c627 movi v7.4s, #0xb1, msl #8
+ 1ac8: 4f05c647 movi v7.4s, #0xb2, msl #8
+ 1acc: 4f05c667 movi v7.4s, #0xb3, msl #8
+ 1ad0: 4f05c687 movi v7.4s, #0xb4, msl #8
+ 1ad4: 4f05c6a7 movi v7.4s, #0xb5, msl #8
+ 1ad8: 4f05c6c7 movi v7.4s, #0xb6, msl #8
+ 1adc: 4f05c6e7 movi v7.4s, #0xb7, msl #8
+ 1ae0: 4f05c707 movi v7.4s, #0xb8, msl #8
+ 1ae4: 4f05c727 movi v7.4s, #0xb9, msl #8
+ 1ae8: 4f05c747 movi v7.4s, #0xba, msl #8
+ 1aec: 4f05c767 movi v7.4s, #0xbb, msl #8
+ 1af0: 4f05c787 movi v7.4s, #0xbc, msl #8
+ 1af4: 4f05c7a7 movi v7.4s, #0xbd, msl #8
+ 1af8: 4f05c7c7 movi v7.4s, #0xbe, msl #8
+ 1afc: 4f05c7e7 movi v7.4s, #0xbf, msl #8
+ 1b00: 4f06c407 movi v7.4s, #0xc0, msl #8
+ 1b04: 4f06c427 movi v7.4s, #0xc1, msl #8
+ 1b08: 4f06c447 movi v7.4s, #0xc2, msl #8
+ 1b0c: 4f06c467 movi v7.4s, #0xc3, msl #8
+ 1b10: 4f06c487 movi v7.4s, #0xc4, msl #8
+ 1b14: 4f06c4a7 movi v7.4s, #0xc5, msl #8
+ 1b18: 4f06c4c7 movi v7.4s, #0xc6, msl #8
+ 1b1c: 4f06c4e7 movi v7.4s, #0xc7, msl #8
+ 1b20: 4f06c507 movi v7.4s, #0xc8, msl #8
+ 1b24: 4f06c527 movi v7.4s, #0xc9, msl #8
+ 1b28: 4f06c547 movi v7.4s, #0xca, msl #8
+ 1b2c: 4f06c567 movi v7.4s, #0xcb, msl #8
+ 1b30: 4f06c587 movi v7.4s, #0xcc, msl #8
+ 1b34: 4f06c5a7 movi v7.4s, #0xcd, msl #8
+ 1b38: 4f06c5c7 movi v7.4s, #0xce, msl #8
+ 1b3c: 4f06c5e7 movi v7.4s, #0xcf, msl #8
+ 1b40: 4f06c607 movi v7.4s, #0xd0, msl #8
+ 1b44: 4f06c627 movi v7.4s, #0xd1, msl #8
+ 1b48: 4f06c647 movi v7.4s, #0xd2, msl #8
+ 1b4c: 4f06c667 movi v7.4s, #0xd3, msl #8
+ 1b50: 4f06c687 movi v7.4s, #0xd4, msl #8
+ 1b54: 4f06c6a7 movi v7.4s, #0xd5, msl #8
+ 1b58: 4f06c6c7 movi v7.4s, #0xd6, msl #8
+ 1b5c: 4f06c6e7 movi v7.4s, #0xd7, msl #8
+ 1b60: 4f06c707 movi v7.4s, #0xd8, msl #8
+ 1b64: 4f06c727 movi v7.4s, #0xd9, msl #8
+ 1b68: 4f06c747 movi v7.4s, #0xda, msl #8
+ 1b6c: 4f06c767 movi v7.4s, #0xdb, msl #8
+ 1b70: 4f06c787 movi v7.4s, #0xdc, msl #8
+ 1b74: 4f06c7a7 movi v7.4s, #0xdd, msl #8
+ 1b78: 4f06c7c7 movi v7.4s, #0xde, msl #8
+ 1b7c: 4f06c7e7 movi v7.4s, #0xdf, msl #8
+ 1b80: 4f07c407 movi v7.4s, #0xe0, msl #8
+ 1b84: 4f07c427 movi v7.4s, #0xe1, msl #8
+ 1b88: 4f07c447 movi v7.4s, #0xe2, msl #8
+ 1b8c: 4f07c467 movi v7.4s, #0xe3, msl #8
+ 1b90: 4f07c487 movi v7.4s, #0xe4, msl #8
+ 1b94: 4f07c4a7 movi v7.4s, #0xe5, msl #8
+ 1b98: 4f07c4c7 movi v7.4s, #0xe6, msl #8
+ 1b9c: 4f07c4e7 movi v7.4s, #0xe7, msl #8
+ 1ba0: 4f07c507 movi v7.4s, #0xe8, msl #8
+ 1ba4: 4f07c527 movi v7.4s, #0xe9, msl #8
+ 1ba8: 4f07c547 movi v7.4s, #0xea, msl #8
+ 1bac: 4f07c567 movi v7.4s, #0xeb, msl #8
+ 1bb0: 4f07c587 movi v7.4s, #0xec, msl #8
+ 1bb4: 4f07c5a7 movi v7.4s, #0xed, msl #8
+ 1bb8: 4f07c5c7 movi v7.4s, #0xee, msl #8
+ 1bbc: 4f07c5e7 movi v7.4s, #0xef, msl #8
+ 1bc0: 4f07c607 movi v7.4s, #0xf0, msl #8
+ 1bc4: 4f07c627 movi v7.4s, #0xf1, msl #8
+ 1bc8: 4f07c647 movi v7.4s, #0xf2, msl #8
+ 1bcc: 4f07c667 movi v7.4s, #0xf3, msl #8
+ 1bd0: 4f07c687 movi v7.4s, #0xf4, msl #8
+ 1bd4: 4f07c6a7 movi v7.4s, #0xf5, msl #8
+ 1bd8: 4f07c6c7 movi v7.4s, #0xf6, msl #8
+ 1bdc: 4f07c6e7 movi v7.4s, #0xf7, msl #8
+ 1be0: 4f07c707 movi v7.4s, #0xf8, msl #8
+ 1be4: 4f07c727 movi v7.4s, #0xf9, msl #8
+ 1be8: 4f07c747 movi v7.4s, #0xfa, msl #8
+ 1bec: 4f07c767 movi v7.4s, #0xfb, msl #8
+ 1bf0: 4f07c787 movi v7.4s, #0xfc, msl #8
+ 1bf4: 4f07c7a7 movi v7.4s, #0xfd, msl #8
+ 1bf8: 4f07c7c7 movi v7.4s, #0xfe, msl #8
+ 1bfc: 4f07c7e7 movi v7.4s, #0xff, msl #8
+ 1c00: 4f00d407 movi v7.4s, #0x0, msl #16
+ 1c04: 4f00d427 movi v7.4s, #0x1, msl #16
+ 1c08: 4f00d447 movi v7.4s, #0x2, msl #16
+ 1c0c: 4f00d467 movi v7.4s, #0x3, msl #16
+ 1c10: 4f00d487 movi v7.4s, #0x4, msl #16
+ 1c14: 4f00d4a7 movi v7.4s, #0x5, msl #16
+ 1c18: 4f00d4c7 movi v7.4s, #0x6, msl #16
+ 1c1c: 4f00d4e7 movi v7.4s, #0x7, msl #16
+ 1c20: 4f00d507 movi v7.4s, #0x8, msl #16
+ 1c24: 4f00d527 movi v7.4s, #0x9, msl #16
+ 1c28: 4f00d547 movi v7.4s, #0xa, msl #16
+ 1c2c: 4f00d567 movi v7.4s, #0xb, msl #16
+ 1c30: 4f00d587 movi v7.4s, #0xc, msl #16
+ 1c34: 4f00d5a7 movi v7.4s, #0xd, msl #16
+ 1c38: 4f00d5c7 movi v7.4s, #0xe, msl #16
+ 1c3c: 4f00d5e7 movi v7.4s, #0xf, msl #16
+ 1c40: 4f00d607 movi v7.4s, #0x10, msl #16
+ 1c44: 4f00d627 movi v7.4s, #0x11, msl #16
+ 1c48: 4f00d647 movi v7.4s, #0x12, msl #16
+ 1c4c: 4f00d667 movi v7.4s, #0x13, msl #16
+ 1c50: 4f00d687 movi v7.4s, #0x14, msl #16
+ 1c54: 4f00d6a7 movi v7.4s, #0x15, msl #16
+ 1c58: 4f00d6c7 movi v7.4s, #0x16, msl #16
+ 1c5c: 4f00d6e7 movi v7.4s, #0x17, msl #16
+ 1c60: 4f00d707 movi v7.4s, #0x18, msl #16
+ 1c64: 4f00d727 movi v7.4s, #0x19, msl #16
+ 1c68: 4f00d747 movi v7.4s, #0x1a, msl #16
+ 1c6c: 4f00d767 movi v7.4s, #0x1b, msl #16
+ 1c70: 4f00d787 movi v7.4s, #0x1c, msl #16
+ 1c74: 4f00d7a7 movi v7.4s, #0x1d, msl #16
+ 1c78: 4f00d7c7 movi v7.4s, #0x1e, msl #16
+ 1c7c: 4f00d7e7 movi v7.4s, #0x1f, msl #16
+ 1c80: 4f01d407 movi v7.4s, #0x20, msl #16
+ 1c84: 4f01d427 movi v7.4s, #0x21, msl #16
+ 1c88: 4f01d447 movi v7.4s, #0x22, msl #16
+ 1c8c: 4f01d467 movi v7.4s, #0x23, msl #16
+ 1c90: 4f01d487 movi v7.4s, #0x24, msl #16
+ 1c94: 4f01d4a7 movi v7.4s, #0x25, msl #16
+ 1c98: 4f01d4c7 movi v7.4s, #0x26, msl #16
+ 1c9c: 4f01d4e7 movi v7.4s, #0x27, msl #16
+ 1ca0: 4f01d507 movi v7.4s, #0x28, msl #16
+ 1ca4: 4f01d527 movi v7.4s, #0x29, msl #16
+ 1ca8: 4f01d547 movi v7.4s, #0x2a, msl #16
+ 1cac: 4f01d567 movi v7.4s, #0x2b, msl #16
+ 1cb0: 4f01d587 movi v7.4s, #0x2c, msl #16
+ 1cb4: 4f01d5a7 movi v7.4s, #0x2d, msl #16
+ 1cb8: 4f01d5c7 movi v7.4s, #0x2e, msl #16
+ 1cbc: 4f01d5e7 movi v7.4s, #0x2f, msl #16
+ 1cc0: 4f01d607 movi v7.4s, #0x30, msl #16
+ 1cc4: 4f01d627 movi v7.4s, #0x31, msl #16
+ 1cc8: 4f01d647 movi v7.4s, #0x32, msl #16
+ 1ccc: 4f01d667 movi v7.4s, #0x33, msl #16
+ 1cd0: 4f01d687 movi v7.4s, #0x34, msl #16
+ 1cd4: 4f01d6a7 movi v7.4s, #0x35, msl #16
+ 1cd8: 4f01d6c7 movi v7.4s, #0x36, msl #16
+ 1cdc: 4f01d6e7 movi v7.4s, #0x37, msl #16
+ 1ce0: 4f01d707 movi v7.4s, #0x38, msl #16
+ 1ce4: 4f01d727 movi v7.4s, #0x39, msl #16
+ 1ce8: 4f01d747 movi v7.4s, #0x3a, msl #16
+ 1cec: 4f01d767 movi v7.4s, #0x3b, msl #16
+ 1cf0: 4f01d787 movi v7.4s, #0x3c, msl #16
+ 1cf4: 4f01d7a7 movi v7.4s, #0x3d, msl #16
+ 1cf8: 4f01d7c7 movi v7.4s, #0x3e, msl #16
+ 1cfc: 4f01d7e7 movi v7.4s, #0x3f, msl #16
+ 1d00: 4f02d407 movi v7.4s, #0x40, msl #16
+ 1d04: 4f02d427 movi v7.4s, #0x41, msl #16
+ 1d08: 4f02d447 movi v7.4s, #0x42, msl #16
+ 1d0c: 4f02d467 movi v7.4s, #0x43, msl #16
+ 1d10: 4f02d487 movi v7.4s, #0x44, msl #16
+ 1d14: 4f02d4a7 movi v7.4s, #0x45, msl #16
+ 1d18: 4f02d4c7 movi v7.4s, #0x46, msl #16
+ 1d1c: 4f02d4e7 movi v7.4s, #0x47, msl #16
+ 1d20: 4f02d507 movi v7.4s, #0x48, msl #16
+ 1d24: 4f02d527 movi v7.4s, #0x49, msl #16
+ 1d28: 4f02d547 movi v7.4s, #0x4a, msl #16
+ 1d2c: 4f02d567 movi v7.4s, #0x4b, msl #16
+ 1d30: 4f02d587 movi v7.4s, #0x4c, msl #16
+ 1d34: 4f02d5a7 movi v7.4s, #0x4d, msl #16
+ 1d38: 4f02d5c7 movi v7.4s, #0x4e, msl #16
+ 1d3c: 4f02d5e7 movi v7.4s, #0x4f, msl #16
+ 1d40: 4f02d607 movi v7.4s, #0x50, msl #16
+ 1d44: 4f02d627 movi v7.4s, #0x51, msl #16
+ 1d48: 4f02d647 movi v7.4s, #0x52, msl #16
+ 1d4c: 4f02d667 movi v7.4s, #0x53, msl #16
+ 1d50: 4f02d687 movi v7.4s, #0x54, msl #16
+ 1d54: 4f02d6a7 movi v7.4s, #0x55, msl #16
+ 1d58: 4f02d6c7 movi v7.4s, #0x56, msl #16
+ 1d5c: 4f02d6e7 movi v7.4s, #0x57, msl #16
+ 1d60: 4f02d707 movi v7.4s, #0x58, msl #16
+ 1d64: 4f02d727 movi v7.4s, #0x59, msl #16
+ 1d68: 4f02d747 movi v7.4s, #0x5a, msl #16
+ 1d6c: 4f02d767 movi v7.4s, #0x5b, msl #16
+ 1d70: 4f02d787 movi v7.4s, #0x5c, msl #16
+ 1d74: 4f02d7a7 movi v7.4s, #0x5d, msl #16
+ 1d78: 4f02d7c7 movi v7.4s, #0x5e, msl #16
+ 1d7c: 4f02d7e7 movi v7.4s, #0x5f, msl #16
+ 1d80: 4f03d407 movi v7.4s, #0x60, msl #16
+ 1d84: 4f03d427 movi v7.4s, #0x61, msl #16
+ 1d88: 4f03d447 movi v7.4s, #0x62, msl #16
+ 1d8c: 4f03d467 movi v7.4s, #0x63, msl #16
+ 1d90: 4f03d487 movi v7.4s, #0x64, msl #16
+ 1d94: 4f03d4a7 movi v7.4s, #0x65, msl #16
+ 1d98: 4f03d4c7 movi v7.4s, #0x66, msl #16
+ 1d9c: 4f03d4e7 movi v7.4s, #0x67, msl #16
+ 1da0: 4f03d507 movi v7.4s, #0x68, msl #16
+ 1da4: 4f03d527 movi v7.4s, #0x69, msl #16
+ 1da8: 4f03d547 movi v7.4s, #0x6a, msl #16
+ 1dac: 4f03d567 movi v7.4s, #0x6b, msl #16
+ 1db0: 4f03d587 movi v7.4s, #0x6c, msl #16
+ 1db4: 4f03d5a7 movi v7.4s, #0x6d, msl #16
+ 1db8: 4f03d5c7 movi v7.4s, #0x6e, msl #16
+ 1dbc: 4f03d5e7 movi v7.4s, #0x6f, msl #16
+ 1dc0: 4f03d607 movi v7.4s, #0x70, msl #16
+ 1dc4: 4f03d627 movi v7.4s, #0x71, msl #16
+ 1dc8: 4f03d647 movi v7.4s, #0x72, msl #16
+ 1dcc: 4f03d667 movi v7.4s, #0x73, msl #16
+ 1dd0: 4f03d687 movi v7.4s, #0x74, msl #16
+ 1dd4: 4f03d6a7 movi v7.4s, #0x75, msl #16
+ 1dd8: 4f03d6c7 movi v7.4s, #0x76, msl #16
+ 1ddc: 4f03d6e7 movi v7.4s, #0x77, msl #16
+ 1de0: 4f03d707 movi v7.4s, #0x78, msl #16
+ 1de4: 4f03d727 movi v7.4s, #0x79, msl #16
+ 1de8: 4f03d747 movi v7.4s, #0x7a, msl #16
+ 1dec: 4f03d767 movi v7.4s, #0x7b, msl #16
+ 1df0: 4f03d787 movi v7.4s, #0x7c, msl #16
+ 1df4: 4f03d7a7 movi v7.4s, #0x7d, msl #16
+ 1df8: 4f03d7c7 movi v7.4s, #0x7e, msl #16
+ 1dfc: 4f03d7e7 movi v7.4s, #0x7f, msl #16
+ 1e00: 4f04d407 movi v7.4s, #0x80, msl #16
+ 1e04: 4f04d427 movi v7.4s, #0x81, msl #16
+ 1e08: 4f04d447 movi v7.4s, #0x82, msl #16
+ 1e0c: 4f04d467 movi v7.4s, #0x83, msl #16
+ 1e10: 4f04d487 movi v7.4s, #0x84, msl #16
+ 1e14: 4f04d4a7 movi v7.4s, #0x85, msl #16
+ 1e18: 4f04d4c7 movi v7.4s, #0x86, msl #16
+ 1e1c: 4f04d4e7 movi v7.4s, #0x87, msl #16
+ 1e20: 4f04d507 movi v7.4s, #0x88, msl #16
+ 1e24: 4f04d527 movi v7.4s, #0x89, msl #16
+ 1e28: 4f04d547 movi v7.4s, #0x8a, msl #16
+ 1e2c: 4f04d567 movi v7.4s, #0x8b, msl #16
+ 1e30: 4f04d587 movi v7.4s, #0x8c, msl #16
+ 1e34: 4f04d5a7 movi v7.4s, #0x8d, msl #16
+ 1e38: 4f04d5c7 movi v7.4s, #0x8e, msl #16
+ 1e3c: 4f04d5e7 movi v7.4s, #0x8f, msl #16
+ 1e40: 4f04d607 movi v7.4s, #0x90, msl #16
+ 1e44: 4f04d627 movi v7.4s, #0x91, msl #16
+ 1e48: 4f04d647 movi v7.4s, #0x92, msl #16
+ 1e4c: 4f04d667 movi v7.4s, #0x93, msl #16
+ 1e50: 4f04d687 movi v7.4s, #0x94, msl #16
+ 1e54: 4f04d6a7 movi v7.4s, #0x95, msl #16
+ 1e58: 4f04d6c7 movi v7.4s, #0x96, msl #16
+ 1e5c: 4f04d6e7 movi v7.4s, #0x97, msl #16
+ 1e60: 4f04d707 movi v7.4s, #0x98, msl #16
+ 1e64: 4f04d727 movi v7.4s, #0x99, msl #16
+ 1e68: 4f04d747 movi v7.4s, #0x9a, msl #16
+ 1e6c: 4f04d767 movi v7.4s, #0x9b, msl #16
+ 1e70: 4f04d787 movi v7.4s, #0x9c, msl #16
+ 1e74: 4f04d7a7 movi v7.4s, #0x9d, msl #16
+ 1e78: 4f04d7c7 movi v7.4s, #0x9e, msl #16
+ 1e7c: 4f04d7e7 movi v7.4s, #0x9f, msl #16
+ 1e80: 4f05d407 movi v7.4s, #0xa0, msl #16
+ 1e84: 4f05d427 movi v7.4s, #0xa1, msl #16
+ 1e88: 4f05d447 movi v7.4s, #0xa2, msl #16
+ 1e8c: 4f05d467 movi v7.4s, #0xa3, msl #16
+ 1e90: 4f05d487 movi v7.4s, #0xa4, msl #16
+ 1e94: 4f05d4a7 movi v7.4s, #0xa5, msl #16
+ 1e98: 4f05d4c7 movi v7.4s, #0xa6, msl #16
+ 1e9c: 4f05d4e7 movi v7.4s, #0xa7, msl #16
+ 1ea0: 4f05d507 movi v7.4s, #0xa8, msl #16
+ 1ea4: 4f05d527 movi v7.4s, #0xa9, msl #16
+ 1ea8: 4f05d547 movi v7.4s, #0xaa, msl #16
+ 1eac: 4f05d567 movi v7.4s, #0xab, msl #16
+ 1eb0: 4f05d587 movi v7.4s, #0xac, msl #16
+ 1eb4: 4f05d5a7 movi v7.4s, #0xad, msl #16
+ 1eb8: 4f05d5c7 movi v7.4s, #0xae, msl #16
+ 1ebc: 4f05d5e7 movi v7.4s, #0xaf, msl #16
+ 1ec0: 4f05d607 movi v7.4s, #0xb0, msl #16
+ 1ec4: 4f05d627 movi v7.4s, #0xb1, msl #16
+ 1ec8: 4f05d647 movi v7.4s, #0xb2, msl #16
+ 1ecc: 4f05d667 movi v7.4s, #0xb3, msl #16
+ 1ed0: 4f05d687 movi v7.4s, #0xb4, msl #16
+ 1ed4: 4f05d6a7 movi v7.4s, #0xb5, msl #16
+ 1ed8: 4f05d6c7 movi v7.4s, #0xb6, msl #16
+ 1edc: 4f05d6e7 movi v7.4s, #0xb7, msl #16
+ 1ee0: 4f05d707 movi v7.4s, #0xb8, msl #16
+ 1ee4: 4f05d727 movi v7.4s, #0xb9, msl #16
+ 1ee8: 4f05d747 movi v7.4s, #0xba, msl #16
+ 1eec: 4f05d767 movi v7.4s, #0xbb, msl #16
+ 1ef0: 4f05d787 movi v7.4s, #0xbc, msl #16
+ 1ef4: 4f05d7a7 movi v7.4s, #0xbd, msl #16
+ 1ef8: 4f05d7c7 movi v7.4s, #0xbe, msl #16
+ 1efc: 4f05d7e7 movi v7.4s, #0xbf, msl #16
+ 1f00: 4f06d407 movi v7.4s, #0xc0, msl #16
+ 1f04: 4f06d427 movi v7.4s, #0xc1, msl #16
+ 1f08: 4f06d447 movi v7.4s, #0xc2, msl #16
+ 1f0c: 4f06d467 movi v7.4s, #0xc3, msl #16
+ 1f10: 4f06d487 movi v7.4s, #0xc4, msl #16
+ 1f14: 4f06d4a7 movi v7.4s, #0xc5, msl #16
+ 1f18: 4f06d4c7 movi v7.4s, #0xc6, msl #16
+ 1f1c: 4f06d4e7 movi v7.4s, #0xc7, msl #16
+ 1f20: 4f06d507 movi v7.4s, #0xc8, msl #16
+ 1f24: 4f06d527 movi v7.4s, #0xc9, msl #16
+ 1f28: 4f06d547 movi v7.4s, #0xca, msl #16
+ 1f2c: 4f06d567 movi v7.4s, #0xcb, msl #16
+ 1f30: 4f06d587 movi v7.4s, #0xcc, msl #16
+ 1f34: 4f06d5a7 movi v7.4s, #0xcd, msl #16
+ 1f38: 4f06d5c7 movi v7.4s, #0xce, msl #16
+ 1f3c: 4f06d5e7 movi v7.4s, #0xcf, msl #16
+ 1f40: 4f06d607 movi v7.4s, #0xd0, msl #16
+ 1f44: 4f06d627 movi v7.4s, #0xd1, msl #16
+ 1f48: 4f06d647 movi v7.4s, #0xd2, msl #16
+ 1f4c: 4f06d667 movi v7.4s, #0xd3, msl #16
+ 1f50: 4f06d687 movi v7.4s, #0xd4, msl #16
+ 1f54: 4f06d6a7 movi v7.4s, #0xd5, msl #16
+ 1f58: 4f06d6c7 movi v7.4s, #0xd6, msl #16
+ 1f5c: 4f06d6e7 movi v7.4s, #0xd7, msl #16
+ 1f60: 4f06d707 movi v7.4s, #0xd8, msl #16
+ 1f64: 4f06d727 movi v7.4s, #0xd9, msl #16
+ 1f68: 4f06d747 movi v7.4s, #0xda, msl #16
+ 1f6c: 4f06d767 movi v7.4s, #0xdb, msl #16
+ 1f70: 4f06d787 movi v7.4s, #0xdc, msl #16
+ 1f74: 4f06d7a7 movi v7.4s, #0xdd, msl #16
+ 1f78: 4f06d7c7 movi v7.4s, #0xde, msl #16
+ 1f7c: 4f06d7e7 movi v7.4s, #0xdf, msl #16
+ 1f80: 4f07d407 movi v7.4s, #0xe0, msl #16
+ 1f84: 4f07d427 movi v7.4s, #0xe1, msl #16
+ 1f88: 4f07d447 movi v7.4s, #0xe2, msl #16
+ 1f8c: 4f07d467 movi v7.4s, #0xe3, msl #16
+ 1f90: 4f07d487 movi v7.4s, #0xe4, msl #16
+ 1f94: 4f07d4a7 movi v7.4s, #0xe5, msl #16
+ 1f98: 4f07d4c7 movi v7.4s, #0xe6, msl #16
+ 1f9c: 4f07d4e7 movi v7.4s, #0xe7, msl #16
+ 1fa0: 4f07d507 movi v7.4s, #0xe8, msl #16
+ 1fa4: 4f07d527 movi v7.4s, #0xe9, msl #16
+ 1fa8: 4f07d547 movi v7.4s, #0xea, msl #16
+ 1fac: 4f07d567 movi v7.4s, #0xeb, msl #16
+ 1fb0: 4f07d587 movi v7.4s, #0xec, msl #16
+ 1fb4: 4f07d5a7 movi v7.4s, #0xed, msl #16
+ 1fb8: 4f07d5c7 movi v7.4s, #0xee, msl #16
+ 1fbc: 4f07d5e7 movi v7.4s, #0xef, msl #16
+ 1fc0: 4f07d607 movi v7.4s, #0xf0, msl #16
+ 1fc4: 4f07d627 movi v7.4s, #0xf1, msl #16
+ 1fc8: 4f07d647 movi v7.4s, #0xf2, msl #16
+ 1fcc: 4f07d667 movi v7.4s, #0xf3, msl #16
+ 1fd0: 4f07d687 movi v7.4s, #0xf4, msl #16
+ 1fd4: 4f07d6a7 movi v7.4s, #0xf5, msl #16
+ 1fd8: 4f07d6c7 movi v7.4s, #0xf6, msl #16
+ 1fdc: 4f07d6e7 movi v7.4s, #0xf7, msl #16
+ 1fe0: 4f07d707 movi v7.4s, #0xf8, msl #16
+ 1fe4: 4f07d727 movi v7.4s, #0xf9, msl #16
+ 1fe8: 4f07d747 movi v7.4s, #0xfa, msl #16
+ 1fec: 4f07d767 movi v7.4s, #0xfb, msl #16
+ 1ff0: 4f07d787 movi v7.4s, #0xfc, msl #16
+ 1ff4: 4f07d7a7 movi v7.4s, #0xfd, msl #16
+ 1ff8: 4f07d7c7 movi v7.4s, #0xfe, msl #16
+ 1ffc: 4f07d7e7 movi v7.4s, #0xff, msl #16
+ 2000: 0f008407 movi v7.4h, #0x0
+ 2004: 0f008427 movi v7.4h, #0x1
+ 2008: 0f008447 movi v7.4h, #0x2
+ 200c: 0f008467 movi v7.4h, #0x3
+ 2010: 0f008487 movi v7.4h, #0x4
+ 2014: 0f0084a7 movi v7.4h, #0x5
+ 2018: 0f0084c7 movi v7.4h, #0x6
+ 201c: 0f0084e7 movi v7.4h, #0x7
+ 2020: 0f008507 movi v7.4h, #0x8
+ 2024: 0f008527 movi v7.4h, #0x9
+ 2028: 0f008547 movi v7.4h, #0xa
+ 202c: 0f008567 movi v7.4h, #0xb
+ 2030: 0f008587 movi v7.4h, #0xc
+ 2034: 0f0085a7 movi v7.4h, #0xd
+ 2038: 0f0085c7 movi v7.4h, #0xe
+ 203c: 0f0085e7 movi v7.4h, #0xf
+ 2040: 0f008607 movi v7.4h, #0x10
+ 2044: 0f008627 movi v7.4h, #0x11
+ 2048: 0f008647 movi v7.4h, #0x12
+ 204c: 0f008667 movi v7.4h, #0x13
+ 2050: 0f008687 movi v7.4h, #0x14
+ 2054: 0f0086a7 movi v7.4h, #0x15
+ 2058: 0f0086c7 movi v7.4h, #0x16
+ 205c: 0f0086e7 movi v7.4h, #0x17
+ 2060: 0f008707 movi v7.4h, #0x18
+ 2064: 0f008727 movi v7.4h, #0x19
+ 2068: 0f008747 movi v7.4h, #0x1a
+ 206c: 0f008767 movi v7.4h, #0x1b
+ 2070: 0f008787 movi v7.4h, #0x1c
+ 2074: 0f0087a7 movi v7.4h, #0x1d
+ 2078: 0f0087c7 movi v7.4h, #0x1e
+ 207c: 0f0087e7 movi v7.4h, #0x1f
+ 2080: 0f018407 movi v7.4h, #0x20
+ 2084: 0f018427 movi v7.4h, #0x21
+ 2088: 0f018447 movi v7.4h, #0x22
+ 208c: 0f018467 movi v7.4h, #0x23
+ 2090: 0f018487 movi v7.4h, #0x24
+ 2094: 0f0184a7 movi v7.4h, #0x25
+ 2098: 0f0184c7 movi v7.4h, #0x26
+ 209c: 0f0184e7 movi v7.4h, #0x27
+ 20a0: 0f018507 movi v7.4h, #0x28
+ 20a4: 0f018527 movi v7.4h, #0x29
+ 20a8: 0f018547 movi v7.4h, #0x2a
+ 20ac: 0f018567 movi v7.4h, #0x2b
+ 20b0: 0f018587 movi v7.4h, #0x2c
+ 20b4: 0f0185a7 movi v7.4h, #0x2d
+ 20b8: 0f0185c7 movi v7.4h, #0x2e
+ 20bc: 0f0185e7 movi v7.4h, #0x2f
+ 20c0: 0f018607 movi v7.4h, #0x30
+ 20c4: 0f018627 movi v7.4h, #0x31
+ 20c8: 0f018647 movi v7.4h, #0x32
+ 20cc: 0f018667 movi v7.4h, #0x33
+ 20d0: 0f018687 movi v7.4h, #0x34
+ 20d4: 0f0186a7 movi v7.4h, #0x35
+ 20d8: 0f0186c7 movi v7.4h, #0x36
+ 20dc: 0f0186e7 movi v7.4h, #0x37
+ 20e0: 0f018707 movi v7.4h, #0x38
+ 20e4: 0f018727 movi v7.4h, #0x39
+ 20e8: 0f018747 movi v7.4h, #0x3a
+ 20ec: 0f018767 movi v7.4h, #0x3b
+ 20f0: 0f018787 movi v7.4h, #0x3c
+ 20f4: 0f0187a7 movi v7.4h, #0x3d
+ 20f8: 0f0187c7 movi v7.4h, #0x3e
+ 20fc: 0f0187e7 movi v7.4h, #0x3f
+ 2100: 0f028407 movi v7.4h, #0x40
+ 2104: 0f028427 movi v7.4h, #0x41
+ 2108: 0f028447 movi v7.4h, #0x42
+ 210c: 0f028467 movi v7.4h, #0x43
+ 2110: 0f028487 movi v7.4h, #0x44
+ 2114: 0f0284a7 movi v7.4h, #0x45
+ 2118: 0f0284c7 movi v7.4h, #0x46
+ 211c: 0f0284e7 movi v7.4h, #0x47
+ 2120: 0f028507 movi v7.4h, #0x48
+ 2124: 0f028527 movi v7.4h, #0x49
+ 2128: 0f028547 movi v7.4h, #0x4a
+ 212c: 0f028567 movi v7.4h, #0x4b
+ 2130: 0f028587 movi v7.4h, #0x4c
+ 2134: 0f0285a7 movi v7.4h, #0x4d
+ 2138: 0f0285c7 movi v7.4h, #0x4e
+ 213c: 0f0285e7 movi v7.4h, #0x4f
+ 2140: 0f028607 movi v7.4h, #0x50
+ 2144: 0f028627 movi v7.4h, #0x51
+ 2148: 0f028647 movi v7.4h, #0x52
+ 214c: 0f028667 movi v7.4h, #0x53
+ 2150: 0f028687 movi v7.4h, #0x54
+ 2154: 0f0286a7 movi v7.4h, #0x55
+ 2158: 0f0286c7 movi v7.4h, #0x56
+ 215c: 0f0286e7 movi v7.4h, #0x57
+ 2160: 0f028707 movi v7.4h, #0x58
+ 2164: 0f028727 movi v7.4h, #0x59
+ 2168: 0f028747 movi v7.4h, #0x5a
+ 216c: 0f028767 movi v7.4h, #0x5b
+ 2170: 0f028787 movi v7.4h, #0x5c
+ 2174: 0f0287a7 movi v7.4h, #0x5d
+ 2178: 0f0287c7 movi v7.4h, #0x5e
+ 217c: 0f0287e7 movi v7.4h, #0x5f
+ 2180: 0f038407 movi v7.4h, #0x60
+ 2184: 0f038427 movi v7.4h, #0x61
+ 2188: 0f038447 movi v7.4h, #0x62
+ 218c: 0f038467 movi v7.4h, #0x63
+ 2190: 0f038487 movi v7.4h, #0x64
+ 2194: 0f0384a7 movi v7.4h, #0x65
+ 2198: 0f0384c7 movi v7.4h, #0x66
+ 219c: 0f0384e7 movi v7.4h, #0x67
+ 21a0: 0f038507 movi v7.4h, #0x68
+ 21a4: 0f038527 movi v7.4h, #0x69
+ 21a8: 0f038547 movi v7.4h, #0x6a
+ 21ac: 0f038567 movi v7.4h, #0x6b
+ 21b0: 0f038587 movi v7.4h, #0x6c
+ 21b4: 0f0385a7 movi v7.4h, #0x6d
+ 21b8: 0f0385c7 movi v7.4h, #0x6e
+ 21bc: 0f0385e7 movi v7.4h, #0x6f
+ 21c0: 0f038607 movi v7.4h, #0x70
+ 21c4: 0f038627 movi v7.4h, #0x71
+ 21c8: 0f038647 movi v7.4h, #0x72
+ 21cc: 0f038667 movi v7.4h, #0x73
+ 21d0: 0f038687 movi v7.4h, #0x74
+ 21d4: 0f0386a7 movi v7.4h, #0x75
+ 21d8: 0f0386c7 movi v7.4h, #0x76
+ 21dc: 0f0386e7 movi v7.4h, #0x77
+ 21e0: 0f038707 movi v7.4h, #0x78
+ 21e4: 0f038727 movi v7.4h, #0x79
+ 21e8: 0f038747 movi v7.4h, #0x7a
+ 21ec: 0f038767 movi v7.4h, #0x7b
+ 21f0: 0f038787 movi v7.4h, #0x7c
+ 21f4: 0f0387a7 movi v7.4h, #0x7d
+ 21f8: 0f0387c7 movi v7.4h, #0x7e
+ 21fc: 0f0387e7 movi v7.4h, #0x7f
+ 2200: 0f048407 movi v7.4h, #0x80
+ 2204: 0f048427 movi v7.4h, #0x81
+ 2208: 0f048447 movi v7.4h, #0x82
+ 220c: 0f048467 movi v7.4h, #0x83
+ 2210: 0f048487 movi v7.4h, #0x84
+ 2214: 0f0484a7 movi v7.4h, #0x85
+ 2218: 0f0484c7 movi v7.4h, #0x86
+ 221c: 0f0484e7 movi v7.4h, #0x87
+ 2220: 0f048507 movi v7.4h, #0x88
+ 2224: 0f048527 movi v7.4h, #0x89
+ 2228: 0f048547 movi v7.4h, #0x8a
+ 222c: 0f048567 movi v7.4h, #0x8b
+ 2230: 0f048587 movi v7.4h, #0x8c
+ 2234: 0f0485a7 movi v7.4h, #0x8d
+ 2238: 0f0485c7 movi v7.4h, #0x8e
+ 223c: 0f0485e7 movi v7.4h, #0x8f
+ 2240: 0f048607 movi v7.4h, #0x90
+ 2244: 0f048627 movi v7.4h, #0x91
+ 2248: 0f048647 movi v7.4h, #0x92
+ 224c: 0f048667 movi v7.4h, #0x93
+ 2250: 0f048687 movi v7.4h, #0x94
+ 2254: 0f0486a7 movi v7.4h, #0x95
+ 2258: 0f0486c7 movi v7.4h, #0x96
+ 225c: 0f0486e7 movi v7.4h, #0x97
+ 2260: 0f048707 movi v7.4h, #0x98
+ 2264: 0f048727 movi v7.4h, #0x99
+ 2268: 0f048747 movi v7.4h, #0x9a
+ 226c: 0f048767 movi v7.4h, #0x9b
+ 2270: 0f048787 movi v7.4h, #0x9c
+ 2274: 0f0487a7 movi v7.4h, #0x9d
+ 2278: 0f0487c7 movi v7.4h, #0x9e
+ 227c: 0f0487e7 movi v7.4h, #0x9f
+ 2280: 0f058407 movi v7.4h, #0xa0
+ 2284: 0f058427 movi v7.4h, #0xa1
+ 2288: 0f058447 movi v7.4h, #0xa2
+ 228c: 0f058467 movi v7.4h, #0xa3
+ 2290: 0f058487 movi v7.4h, #0xa4
+ 2294: 0f0584a7 movi v7.4h, #0xa5
+ 2298: 0f0584c7 movi v7.4h, #0xa6
+ 229c: 0f0584e7 movi v7.4h, #0xa7
+ 22a0: 0f058507 movi v7.4h, #0xa8
+ 22a4: 0f058527 movi v7.4h, #0xa9
+ 22a8: 0f058547 movi v7.4h, #0xaa
+ 22ac: 0f058567 movi v7.4h, #0xab
+ 22b0: 0f058587 movi v7.4h, #0xac
+ 22b4: 0f0585a7 movi v7.4h, #0xad
+ 22b8: 0f0585c7 movi v7.4h, #0xae
+ 22bc: 0f0585e7 movi v7.4h, #0xaf
+ 22c0: 0f058607 movi v7.4h, #0xb0
+ 22c4: 0f058627 movi v7.4h, #0xb1
+ 22c8: 0f058647 movi v7.4h, #0xb2
+ 22cc: 0f058667 movi v7.4h, #0xb3
+ 22d0: 0f058687 movi v7.4h, #0xb4
+ 22d4: 0f0586a7 movi v7.4h, #0xb5
+ 22d8: 0f0586c7 movi v7.4h, #0xb6
+ 22dc: 0f0586e7 movi v7.4h, #0xb7
+ 22e0: 0f058707 movi v7.4h, #0xb8
+ 22e4: 0f058727 movi v7.4h, #0xb9
+ 22e8: 0f058747 movi v7.4h, #0xba
+ 22ec: 0f058767 movi v7.4h, #0xbb
+ 22f0: 0f058787 movi v7.4h, #0xbc
+ 22f4: 0f0587a7 movi v7.4h, #0xbd
+ 22f8: 0f0587c7 movi v7.4h, #0xbe
+ 22fc: 0f0587e7 movi v7.4h, #0xbf
+ 2300: 0f068407 movi v7.4h, #0xc0
+ 2304: 0f068427 movi v7.4h, #0xc1
+ 2308: 0f068447 movi v7.4h, #0xc2
+ 230c: 0f068467 movi v7.4h, #0xc3
+ 2310: 0f068487 movi v7.4h, #0xc4
+ 2314: 0f0684a7 movi v7.4h, #0xc5
+ 2318: 0f0684c7 movi v7.4h, #0xc6
+ 231c: 0f0684e7 movi v7.4h, #0xc7
+ 2320: 0f068507 movi v7.4h, #0xc8
+ 2324: 0f068527 movi v7.4h, #0xc9
+ 2328: 0f068547 movi v7.4h, #0xca
+ 232c: 0f068567 movi v7.4h, #0xcb
+ 2330: 0f068587 movi v7.4h, #0xcc
+ 2334: 0f0685a7 movi v7.4h, #0xcd
+ 2338: 0f0685c7 movi v7.4h, #0xce
+ 233c: 0f0685e7 movi v7.4h, #0xcf
+ 2340: 0f068607 movi v7.4h, #0xd0
+ 2344: 0f068627 movi v7.4h, #0xd1
+ 2348: 0f068647 movi v7.4h, #0xd2
+ 234c: 0f068667 movi v7.4h, #0xd3
+ 2350: 0f068687 movi v7.4h, #0xd4
+ 2354: 0f0686a7 movi v7.4h, #0xd5
+ 2358: 0f0686c7 movi v7.4h, #0xd6
+ 235c: 0f0686e7 movi v7.4h, #0xd7
+ 2360: 0f068707 movi v7.4h, #0xd8
+ 2364: 0f068727 movi v7.4h, #0xd9
+ 2368: 0f068747 movi v7.4h, #0xda
+ 236c: 0f068767 movi v7.4h, #0xdb
+ 2370: 0f068787 movi v7.4h, #0xdc
+ 2374: 0f0687a7 movi v7.4h, #0xdd
+ 2378: 0f0687c7 movi v7.4h, #0xde
+ 237c: 0f0687e7 movi v7.4h, #0xdf
+ 2380: 0f078407 movi v7.4h, #0xe0
+ 2384: 0f078427 movi v7.4h, #0xe1
+ 2388: 0f078447 movi v7.4h, #0xe2
+ 238c: 0f078467 movi v7.4h, #0xe3
+ 2390: 0f078487 movi v7.4h, #0xe4
+ 2394: 0f0784a7 movi v7.4h, #0xe5
+ 2398: 0f0784c7 movi v7.4h, #0xe6
+ 239c: 0f0784e7 movi v7.4h, #0xe7
+ 23a0: 0f078507 movi v7.4h, #0xe8
+ 23a4: 0f078527 movi v7.4h, #0xe9
+ 23a8: 0f078547 movi v7.4h, #0xea
+ 23ac: 0f078567 movi v7.4h, #0xeb
+ 23b0: 0f078587 movi v7.4h, #0xec
+ 23b4: 0f0785a7 movi v7.4h, #0xed
+ 23b8: 0f0785c7 movi v7.4h, #0xee
+ 23bc: 0f0785e7 movi v7.4h, #0xef
+ 23c0: 0f078607 movi v7.4h, #0xf0
+ 23c4: 0f078627 movi v7.4h, #0xf1
+ 23c8: 0f078647 movi v7.4h, #0xf2
+ 23cc: 0f078667 movi v7.4h, #0xf3
+ 23d0: 0f078687 movi v7.4h, #0xf4
+ 23d4: 0f0786a7 movi v7.4h, #0xf5
+ 23d8: 0f0786c7 movi v7.4h, #0xf6
+ 23dc: 0f0786e7 movi v7.4h, #0xf7
+ 23e0: 0f078707 movi v7.4h, #0xf8
+ 23e4: 0f078727 movi v7.4h, #0xf9
+ 23e8: 0f078747 movi v7.4h, #0xfa
+ 23ec: 0f078767 movi v7.4h, #0xfb
+ 23f0: 0f078787 movi v7.4h, #0xfc
+ 23f4: 0f0787a7 movi v7.4h, #0xfd
+ 23f8: 0f0787c7 movi v7.4h, #0xfe
+ 23fc: 0f0787e7 movi v7.4h, #0xff
+ 2400: 0f00840f movi v15.4h, #0x0
+ 2404: 0f00842f movi v15.4h, #0x1
+ 2408: 0f00844f movi v15.4h, #0x2
+ 240c: 0f00846f movi v15.4h, #0x3
+ 2410: 0f00848f movi v15.4h, #0x4
+ 2414: 0f0084af movi v15.4h, #0x5
+ 2418: 0f0084cf movi v15.4h, #0x6
+ 241c: 0f0084ef movi v15.4h, #0x7
+ 2420: 0f00850f movi v15.4h, #0x8
+ 2424: 0f00852f movi v15.4h, #0x9
+ 2428: 0f00854f movi v15.4h, #0xa
+ 242c: 0f00856f movi v15.4h, #0xb
+ 2430: 0f00858f movi v15.4h, #0xc
+ 2434: 0f0085af movi v15.4h, #0xd
+ 2438: 0f0085cf movi v15.4h, #0xe
+ 243c: 0f0085ef movi v15.4h, #0xf
+ 2440: 0f00860f movi v15.4h, #0x10
+ 2444: 0f00862f movi v15.4h, #0x11
+ 2448: 0f00864f movi v15.4h, #0x12
+ 244c: 0f00866f movi v15.4h, #0x13
+ 2450: 0f00868f movi v15.4h, #0x14
+ 2454: 0f0086af movi v15.4h, #0x15
+ 2458: 0f0086cf movi v15.4h, #0x16
+ 245c: 0f0086ef movi v15.4h, #0x17
+ 2460: 0f00870f movi v15.4h, #0x18
+ 2464: 0f00872f movi v15.4h, #0x19
+ 2468: 0f00874f movi v15.4h, #0x1a
+ 246c: 0f00876f movi v15.4h, #0x1b
+ 2470: 0f00878f movi v15.4h, #0x1c
+ 2474: 0f0087af movi v15.4h, #0x1d
+ 2478: 0f0087cf movi v15.4h, #0x1e
+ 247c: 0f0087ef movi v15.4h, #0x1f
+ 2480: 0f01840f movi v15.4h, #0x20
+ 2484: 0f01842f movi v15.4h, #0x21
+ 2488: 0f01844f movi v15.4h, #0x22
+ 248c: 0f01846f movi v15.4h, #0x23
+ 2490: 0f01848f movi v15.4h, #0x24
+ 2494: 0f0184af movi v15.4h, #0x25
+ 2498: 0f0184cf movi v15.4h, #0x26
+ 249c: 0f0184ef movi v15.4h, #0x27
+ 24a0: 0f01850f movi v15.4h, #0x28
+ 24a4: 0f01852f movi v15.4h, #0x29
+ 24a8: 0f01854f movi v15.4h, #0x2a
+ 24ac: 0f01856f movi v15.4h, #0x2b
+ 24b0: 0f01858f movi v15.4h, #0x2c
+ 24b4: 0f0185af movi v15.4h, #0x2d
+ 24b8: 0f0185cf movi v15.4h, #0x2e
+ 24bc: 0f0185ef movi v15.4h, #0x2f
+ 24c0: 0f01860f movi v15.4h, #0x30
+ 24c4: 0f01862f movi v15.4h, #0x31
+ 24c8: 0f01864f movi v15.4h, #0x32
+ 24cc: 0f01866f movi v15.4h, #0x33
+ 24d0: 0f01868f movi v15.4h, #0x34
+ 24d4: 0f0186af movi v15.4h, #0x35
+ 24d8: 0f0186cf movi v15.4h, #0x36
+ 24dc: 0f0186ef movi v15.4h, #0x37
+ 24e0: 0f01870f movi v15.4h, #0x38
+ 24e4: 0f01872f movi v15.4h, #0x39
+ 24e8: 0f01874f movi v15.4h, #0x3a
+ 24ec: 0f01876f movi v15.4h, #0x3b
+ 24f0: 0f01878f movi v15.4h, #0x3c
+ 24f4: 0f0187af movi v15.4h, #0x3d
+ 24f8: 0f0187cf movi v15.4h, #0x3e
+ 24fc: 0f0187ef movi v15.4h, #0x3f
+ 2500: 0f02840f movi v15.4h, #0x40
+ 2504: 0f02842f movi v15.4h, #0x41
+ 2508: 0f02844f movi v15.4h, #0x42
+ 250c: 0f02846f movi v15.4h, #0x43
+ 2510: 0f02848f movi v15.4h, #0x44
+ 2514: 0f0284af movi v15.4h, #0x45
+ 2518: 0f0284cf movi v15.4h, #0x46
+ 251c: 0f0284ef movi v15.4h, #0x47
+ 2520: 0f02850f movi v15.4h, #0x48
+ 2524: 0f02852f movi v15.4h, #0x49
+ 2528: 0f02854f movi v15.4h, #0x4a
+ 252c: 0f02856f movi v15.4h, #0x4b
+ 2530: 0f02858f movi v15.4h, #0x4c
+ 2534: 0f0285af movi v15.4h, #0x4d
+ 2538: 0f0285cf movi v15.4h, #0x4e
+ 253c: 0f0285ef movi v15.4h, #0x4f
+ 2540: 0f02860f movi v15.4h, #0x50
+ 2544: 0f02862f movi v15.4h, #0x51
+ 2548: 0f02864f movi v15.4h, #0x52
+ 254c: 0f02866f movi v15.4h, #0x53
+ 2550: 0f02868f movi v15.4h, #0x54
+ 2554: 0f0286af movi v15.4h, #0x55
+ 2558: 0f0286cf movi v15.4h, #0x56
+ 255c: 0f0286ef movi v15.4h, #0x57
+ 2560: 0f02870f movi v15.4h, #0x58
+ 2564: 0f02872f movi v15.4h, #0x59
+ 2568: 0f02874f movi v15.4h, #0x5a
+ 256c: 0f02876f movi v15.4h, #0x5b
+ 2570: 0f02878f movi v15.4h, #0x5c
+ 2574: 0f0287af movi v15.4h, #0x5d
+ 2578: 0f0287cf movi v15.4h, #0x5e
+ 257c: 0f0287ef movi v15.4h, #0x5f
+ 2580: 0f03840f movi v15.4h, #0x60
+ 2584: 0f03842f movi v15.4h, #0x61
+ 2588: 0f03844f movi v15.4h, #0x62
+ 258c: 0f03846f movi v15.4h, #0x63
+ 2590: 0f03848f movi v15.4h, #0x64
+ 2594: 0f0384af movi v15.4h, #0x65
+ 2598: 0f0384cf movi v15.4h, #0x66
+ 259c: 0f0384ef movi v15.4h, #0x67
+ 25a0: 0f03850f movi v15.4h, #0x68
+ 25a4: 0f03852f movi v15.4h, #0x69
+ 25a8: 0f03854f movi v15.4h, #0x6a
+ 25ac: 0f03856f movi v15.4h, #0x6b
+ 25b0: 0f03858f movi v15.4h, #0x6c
+ 25b4: 0f0385af movi v15.4h, #0x6d
+ 25b8: 0f0385cf movi v15.4h, #0x6e
+ 25bc: 0f0385ef movi v15.4h, #0x6f
+ 25c0: 0f03860f movi v15.4h, #0x70
+ 25c4: 0f03862f movi v15.4h, #0x71
+ 25c8: 0f03864f movi v15.4h, #0x72
+ 25cc: 0f03866f movi v15.4h, #0x73
+ 25d0: 0f03868f movi v15.4h, #0x74
+ 25d4: 0f0386af movi v15.4h, #0x75
+ 25d8: 0f0386cf movi v15.4h, #0x76
+ 25dc: 0f0386ef movi v15.4h, #0x77
+ 25e0: 0f03870f movi v15.4h, #0x78
+ 25e4: 0f03872f movi v15.4h, #0x79
+ 25e8: 0f03874f movi v15.4h, #0x7a
+ 25ec: 0f03876f movi v15.4h, #0x7b
+ 25f0: 0f03878f movi v15.4h, #0x7c
+ 25f4: 0f0387af movi v15.4h, #0x7d
+ 25f8: 0f0387cf movi v15.4h, #0x7e
+ 25fc: 0f0387ef movi v15.4h, #0x7f
+ 2600: 0f04840f movi v15.4h, #0x80
+ 2604: 0f04842f movi v15.4h, #0x81
+ 2608: 0f04844f movi v15.4h, #0x82
+ 260c: 0f04846f movi v15.4h, #0x83
+ 2610: 0f04848f movi v15.4h, #0x84
+ 2614: 0f0484af movi v15.4h, #0x85
+ 2618: 0f0484cf movi v15.4h, #0x86
+ 261c: 0f0484ef movi v15.4h, #0x87
+ 2620: 0f04850f movi v15.4h, #0x88
+ 2624: 0f04852f movi v15.4h, #0x89
+ 2628: 0f04854f movi v15.4h, #0x8a
+ 262c: 0f04856f movi v15.4h, #0x8b
+ 2630: 0f04858f movi v15.4h, #0x8c
+ 2634: 0f0485af movi v15.4h, #0x8d
+ 2638: 0f0485cf movi v15.4h, #0x8e
+ 263c: 0f0485ef movi v15.4h, #0x8f
+ 2640: 0f04860f movi v15.4h, #0x90
+ 2644: 0f04862f movi v15.4h, #0x91
+ 2648: 0f04864f movi v15.4h, #0x92
+ 264c: 0f04866f movi v15.4h, #0x93
+ 2650: 0f04868f movi v15.4h, #0x94
+ 2654: 0f0486af movi v15.4h, #0x95
+ 2658: 0f0486cf movi v15.4h, #0x96
+ 265c: 0f0486ef movi v15.4h, #0x97
+ 2660: 0f04870f movi v15.4h, #0x98
+ 2664: 0f04872f movi v15.4h, #0x99
+ 2668: 0f04874f movi v15.4h, #0x9a
+ 266c: 0f04876f movi v15.4h, #0x9b
+ 2670: 0f04878f movi v15.4h, #0x9c
+ 2674: 0f0487af movi v15.4h, #0x9d
+ 2678: 0f0487cf movi v15.4h, #0x9e
+ 267c: 0f0487ef movi v15.4h, #0x9f
+ 2680: 0f05840f movi v15.4h, #0xa0
+ 2684: 0f05842f movi v15.4h, #0xa1
+ 2688: 0f05844f movi v15.4h, #0xa2
+ 268c: 0f05846f movi v15.4h, #0xa3
+ 2690: 0f05848f movi v15.4h, #0xa4
+ 2694: 0f0584af movi v15.4h, #0xa5
+ 2698: 0f0584cf movi v15.4h, #0xa6
+ 269c: 0f0584ef movi v15.4h, #0xa7
+ 26a0: 0f05850f movi v15.4h, #0xa8
+ 26a4: 0f05852f movi v15.4h, #0xa9
+ 26a8: 0f05854f movi v15.4h, #0xaa
+ 26ac: 0f05856f movi v15.4h, #0xab
+ 26b0: 0f05858f movi v15.4h, #0xac
+ 26b4: 0f0585af movi v15.4h, #0xad
+ 26b8: 0f0585cf movi v15.4h, #0xae
+ 26bc: 0f0585ef movi v15.4h, #0xaf
+ 26c0: 0f05860f movi v15.4h, #0xb0
+ 26c4: 0f05862f movi v15.4h, #0xb1
+ 26c8: 0f05864f movi v15.4h, #0xb2
+ 26cc: 0f05866f movi v15.4h, #0xb3
+ 26d0: 0f05868f movi v15.4h, #0xb4
+ 26d4: 0f0586af movi v15.4h, #0xb5
+ 26d8: 0f0586cf movi v15.4h, #0xb6
+ 26dc: 0f0586ef movi v15.4h, #0xb7
+ 26e0: 0f05870f movi v15.4h, #0xb8
+ 26e4: 0f05872f movi v15.4h, #0xb9
+ 26e8: 0f05874f movi v15.4h, #0xba
+ 26ec: 0f05876f movi v15.4h, #0xbb
+ 26f0: 0f05878f movi v15.4h, #0xbc
+ 26f4: 0f0587af movi v15.4h, #0xbd
+ 26f8: 0f0587cf movi v15.4h, #0xbe
+ 26fc: 0f0587ef movi v15.4h, #0xbf
+ 2700: 0f06840f movi v15.4h, #0xc0
+ 2704: 0f06842f movi v15.4h, #0xc1
+ 2708: 0f06844f movi v15.4h, #0xc2
+ 270c: 0f06846f movi v15.4h, #0xc3
+ 2710: 0f06848f movi v15.4h, #0xc4
+ 2714: 0f0684af movi v15.4h, #0xc5
+ 2718: 0f0684cf movi v15.4h, #0xc6
+ 271c: 0f0684ef movi v15.4h, #0xc7
+ 2720: 0f06850f movi v15.4h, #0xc8
+ 2724: 0f06852f movi v15.4h, #0xc9
+ 2728: 0f06854f movi v15.4h, #0xca
+ 272c: 0f06856f movi v15.4h, #0xcb
+ 2730: 0f06858f movi v15.4h, #0xcc
+ 2734: 0f0685af movi v15.4h, #0xcd
+ 2738: 0f0685cf movi v15.4h, #0xce
+ 273c: 0f0685ef movi v15.4h, #0xcf
+ 2740: 0f06860f movi v15.4h, #0xd0
+ 2744: 0f06862f movi v15.4h, #0xd1
+ 2748: 0f06864f movi v15.4h, #0xd2
+ 274c: 0f06866f movi v15.4h, #0xd3
+ 2750: 0f06868f movi v15.4h, #0xd4
+ 2754: 0f0686af movi v15.4h, #0xd5
+ 2758: 0f0686cf movi v15.4h, #0xd6
+ 275c: 0f0686ef movi v15.4h, #0xd7
+ 2760: 0f06870f movi v15.4h, #0xd8
+ 2764: 0f06872f movi v15.4h, #0xd9
+ 2768: 0f06874f movi v15.4h, #0xda
+ 276c: 0f06876f movi v15.4h, #0xdb
+ 2770: 0f06878f movi v15.4h, #0xdc
+ 2774: 0f0687af movi v15.4h, #0xdd
+ 2778: 0f0687cf movi v15.4h, #0xde
+ 277c: 0f0687ef movi v15.4h, #0xdf
+ 2780: 0f07840f movi v15.4h, #0xe0
+ 2784: 0f07842f movi v15.4h, #0xe1
+ 2788: 0f07844f movi v15.4h, #0xe2
+ 278c: 0f07846f movi v15.4h, #0xe3
+ 2790: 0f07848f movi v15.4h, #0xe4
+ 2794: 0f0784af movi v15.4h, #0xe5
+ 2798: 0f0784cf movi v15.4h, #0xe6
+ 279c: 0f0784ef movi v15.4h, #0xe7
+ 27a0: 0f07850f movi v15.4h, #0xe8
+ 27a4: 0f07852f movi v15.4h, #0xe9
+ 27a8: 0f07854f movi v15.4h, #0xea
+ 27ac: 0f07856f movi v15.4h, #0xeb
+ 27b0: 0f07858f movi v15.4h, #0xec
+ 27b4: 0f0785af movi v15.4h, #0xed
+ 27b8: 0f0785cf movi v15.4h, #0xee
+ 27bc: 0f0785ef movi v15.4h, #0xef
+ 27c0: 0f07860f movi v15.4h, #0xf0
+ 27c4: 0f07862f movi v15.4h, #0xf1
+ 27c8: 0f07864f movi v15.4h, #0xf2
+ 27cc: 0f07866f movi v15.4h, #0xf3
+ 27d0: 0f07868f movi v15.4h, #0xf4
+ 27d4: 0f0786af movi v15.4h, #0xf5
+ 27d8: 0f0786cf movi v15.4h, #0xf6
+ 27dc: 0f0786ef movi v15.4h, #0xf7
+ 27e0: 0f07870f movi v15.4h, #0xf8
+ 27e4: 0f07872f movi v15.4h, #0xf9
+ 27e8: 0f07874f movi v15.4h, #0xfa
+ 27ec: 0f07876f movi v15.4h, #0xfb
+ 27f0: 0f07878f movi v15.4h, #0xfc
+ 27f4: 0f0787af movi v15.4h, #0xfd
+ 27f8: 0f0787cf movi v15.4h, #0xfe
+ 27fc: 0f0787ef movi v15.4h, #0xff
+ 2800: 0f00a407 movi v7.4h, #0x0, lsl #8
+ 2804: 0f00a427 movi v7.4h, #0x1, lsl #8
+ 2808: 0f00a447 movi v7.4h, #0x2, lsl #8
+ 280c: 0f00a467 movi v7.4h, #0x3, lsl #8
+ 2810: 0f00a487 movi v7.4h, #0x4, lsl #8
+ 2814: 0f00a4a7 movi v7.4h, #0x5, lsl #8
+ 2818: 0f00a4c7 movi v7.4h, #0x6, lsl #8
+ 281c: 0f00a4e7 movi v7.4h, #0x7, lsl #8
+ 2820: 0f00a507 movi v7.4h, #0x8, lsl #8
+ 2824: 0f00a527 movi v7.4h, #0x9, lsl #8
+ 2828: 0f00a547 movi v7.4h, #0xa, lsl #8
+ 282c: 0f00a567 movi v7.4h, #0xb, lsl #8
+ 2830: 0f00a587 movi v7.4h, #0xc, lsl #8
+ 2834: 0f00a5a7 movi v7.4h, #0xd, lsl #8
+ 2838: 0f00a5c7 movi v7.4h, #0xe, lsl #8
+ 283c: 0f00a5e7 movi v7.4h, #0xf, lsl #8
+ 2840: 0f00a607 movi v7.4h, #0x10, lsl #8
+ 2844: 0f00a627 movi v7.4h, #0x11, lsl #8
+ 2848: 0f00a647 movi v7.4h, #0x12, lsl #8
+ 284c: 0f00a667 movi v7.4h, #0x13, lsl #8
+ 2850: 0f00a687 movi v7.4h, #0x14, lsl #8
+ 2854: 0f00a6a7 movi v7.4h, #0x15, lsl #8
+ 2858: 0f00a6c7 movi v7.4h, #0x16, lsl #8
+ 285c: 0f00a6e7 movi v7.4h, #0x17, lsl #8
+ 2860: 0f00a707 movi v7.4h, #0x18, lsl #8
+ 2864: 0f00a727 movi v7.4h, #0x19, lsl #8
+ 2868: 0f00a747 movi v7.4h, #0x1a, lsl #8
+ 286c: 0f00a767 movi v7.4h, #0x1b, lsl #8
+ 2870: 0f00a787 movi v7.4h, #0x1c, lsl #8
+ 2874: 0f00a7a7 movi v7.4h, #0x1d, lsl #8
+ 2878: 0f00a7c7 movi v7.4h, #0x1e, lsl #8
+ 287c: 0f00a7e7 movi v7.4h, #0x1f, lsl #8
+ 2880: 0f01a407 movi v7.4h, #0x20, lsl #8
+ 2884: 0f01a427 movi v7.4h, #0x21, lsl #8
+ 2888: 0f01a447 movi v7.4h, #0x22, lsl #8
+ 288c: 0f01a467 movi v7.4h, #0x23, lsl #8
+ 2890: 0f01a487 movi v7.4h, #0x24, lsl #8
+ 2894: 0f01a4a7 movi v7.4h, #0x25, lsl #8
+ 2898: 0f01a4c7 movi v7.4h, #0x26, lsl #8
+ 289c: 0f01a4e7 movi v7.4h, #0x27, lsl #8
+ 28a0: 0f01a507 movi v7.4h, #0x28, lsl #8
+ 28a4: 0f01a527 movi v7.4h, #0x29, lsl #8
+ 28a8: 0f01a547 movi v7.4h, #0x2a, lsl #8
+ 28ac: 0f01a567 movi v7.4h, #0x2b, lsl #8
+ 28b0: 0f01a587 movi v7.4h, #0x2c, lsl #8
+ 28b4: 0f01a5a7 movi v7.4h, #0x2d, lsl #8
+ 28b8: 0f01a5c7 movi v7.4h, #0x2e, lsl #8
+ 28bc: 0f01a5e7 movi v7.4h, #0x2f, lsl #8
+ 28c0: 0f01a607 movi v7.4h, #0x30, lsl #8
+ 28c4: 0f01a627 movi v7.4h, #0x31, lsl #8
+ 28c8: 0f01a647 movi v7.4h, #0x32, lsl #8
+ 28cc: 0f01a667 movi v7.4h, #0x33, lsl #8
+ 28d0: 0f01a687 movi v7.4h, #0x34, lsl #8
+ 28d4: 0f01a6a7 movi v7.4h, #0x35, lsl #8
+ 28d8: 0f01a6c7 movi v7.4h, #0x36, lsl #8
+ 28dc: 0f01a6e7 movi v7.4h, #0x37, lsl #8
+ 28e0: 0f01a707 movi v7.4h, #0x38, lsl #8
+ 28e4: 0f01a727 movi v7.4h, #0x39, lsl #8
+ 28e8: 0f01a747 movi v7.4h, #0x3a, lsl #8
+ 28ec: 0f01a767 movi v7.4h, #0x3b, lsl #8
+ 28f0: 0f01a787 movi v7.4h, #0x3c, lsl #8
+ 28f4: 0f01a7a7 movi v7.4h, #0x3d, lsl #8
+ 28f8: 0f01a7c7 movi v7.4h, #0x3e, lsl #8
+ 28fc: 0f01a7e7 movi v7.4h, #0x3f, lsl #8
+ 2900: 0f02a407 movi v7.4h, #0x40, lsl #8
+ 2904: 0f02a427 movi v7.4h, #0x41, lsl #8
+ 2908: 0f02a447 movi v7.4h, #0x42, lsl #8
+ 290c: 0f02a467 movi v7.4h, #0x43, lsl #8
+ 2910: 0f02a487 movi v7.4h, #0x44, lsl #8
+ 2914: 0f02a4a7 movi v7.4h, #0x45, lsl #8
+ 2918: 0f02a4c7 movi v7.4h, #0x46, lsl #8
+ 291c: 0f02a4e7 movi v7.4h, #0x47, lsl #8
+ 2920: 0f02a507 movi v7.4h, #0x48, lsl #8
+ 2924: 0f02a527 movi v7.4h, #0x49, lsl #8
+ 2928: 0f02a547 movi v7.4h, #0x4a, lsl #8
+ 292c: 0f02a567 movi v7.4h, #0x4b, lsl #8
+ 2930: 0f02a587 movi v7.4h, #0x4c, lsl #8
+ 2934: 0f02a5a7 movi v7.4h, #0x4d, lsl #8
+ 2938: 0f02a5c7 movi v7.4h, #0x4e, lsl #8
+ 293c: 0f02a5e7 movi v7.4h, #0x4f, lsl #8
+ 2940: 0f02a607 movi v7.4h, #0x50, lsl #8
+ 2944: 0f02a627 movi v7.4h, #0x51, lsl #8
+ 2948: 0f02a647 movi v7.4h, #0x52, lsl #8
+ 294c: 0f02a667 movi v7.4h, #0x53, lsl #8
+ 2950: 0f02a687 movi v7.4h, #0x54, lsl #8
+ 2954: 0f02a6a7 movi v7.4h, #0x55, lsl #8
+ 2958: 0f02a6c7 movi v7.4h, #0x56, lsl #8
+ 295c: 0f02a6e7 movi v7.4h, #0x57, lsl #8
+ 2960: 0f02a707 movi v7.4h, #0x58, lsl #8
+ 2964: 0f02a727 movi v7.4h, #0x59, lsl #8
+ 2968: 0f02a747 movi v7.4h, #0x5a, lsl #8
+ 296c: 0f02a767 movi v7.4h, #0x5b, lsl #8
+ 2970: 0f02a787 movi v7.4h, #0x5c, lsl #8
+ 2974: 0f02a7a7 movi v7.4h, #0x5d, lsl #8
+ 2978: 0f02a7c7 movi v7.4h, #0x5e, lsl #8
+ 297c: 0f02a7e7 movi v7.4h, #0x5f, lsl #8
+ 2980: 0f03a407 movi v7.4h, #0x60, lsl #8
+ 2984: 0f03a427 movi v7.4h, #0x61, lsl #8
+ 2988: 0f03a447 movi v7.4h, #0x62, lsl #8
+ 298c: 0f03a467 movi v7.4h, #0x63, lsl #8
+ 2990: 0f03a487 movi v7.4h, #0x64, lsl #8
+ 2994: 0f03a4a7 movi v7.4h, #0x65, lsl #8
+ 2998: 0f03a4c7 movi v7.4h, #0x66, lsl #8
+ 299c: 0f03a4e7 movi v7.4h, #0x67, lsl #8
+ 29a0: 0f03a507 movi v7.4h, #0x68, lsl #8
+ 29a4: 0f03a527 movi v7.4h, #0x69, lsl #8
+ 29a8: 0f03a547 movi v7.4h, #0x6a, lsl #8
+ 29ac: 0f03a567 movi v7.4h, #0x6b, lsl #8
+ 29b0: 0f03a587 movi v7.4h, #0x6c, lsl #8
+ 29b4: 0f03a5a7 movi v7.4h, #0x6d, lsl #8
+ 29b8: 0f03a5c7 movi v7.4h, #0x6e, lsl #8
+ 29bc: 0f03a5e7 movi v7.4h, #0x6f, lsl #8
+ 29c0: 0f03a607 movi v7.4h, #0x70, lsl #8
+ 29c4: 0f03a627 movi v7.4h, #0x71, lsl #8
+ 29c8: 0f03a647 movi v7.4h, #0x72, lsl #8
+ 29cc: 0f03a667 movi v7.4h, #0x73, lsl #8
+ 29d0: 0f03a687 movi v7.4h, #0x74, lsl #8
+ 29d4: 0f03a6a7 movi v7.4h, #0x75, lsl #8
+ 29d8: 0f03a6c7 movi v7.4h, #0x76, lsl #8
+ 29dc: 0f03a6e7 movi v7.4h, #0x77, lsl #8
+ 29e0: 0f03a707 movi v7.4h, #0x78, lsl #8
+ 29e4: 0f03a727 movi v7.4h, #0x79, lsl #8
+ 29e8: 0f03a747 movi v7.4h, #0x7a, lsl #8
+ 29ec: 0f03a767 movi v7.4h, #0x7b, lsl #8
+ 29f0: 0f03a787 movi v7.4h, #0x7c, lsl #8
+ 29f4: 0f03a7a7 movi v7.4h, #0x7d, lsl #8
+ 29f8: 0f03a7c7 movi v7.4h, #0x7e, lsl #8
+ 29fc: 0f03a7e7 movi v7.4h, #0x7f, lsl #8
+ 2a00: 0f04a407 movi v7.4h, #0x80, lsl #8
+ 2a04: 0f04a427 movi v7.4h, #0x81, lsl #8
+ 2a08: 0f04a447 movi v7.4h, #0x82, lsl #8
+ 2a0c: 0f04a467 movi v7.4h, #0x83, lsl #8
+ 2a10: 0f04a487 movi v7.4h, #0x84, lsl #8
+ 2a14: 0f04a4a7 movi v7.4h, #0x85, lsl #8
+ 2a18: 0f04a4c7 movi v7.4h, #0x86, lsl #8
+ 2a1c: 0f04a4e7 movi v7.4h, #0x87, lsl #8
+ 2a20: 0f04a507 movi v7.4h, #0x88, lsl #8
+ 2a24: 0f04a527 movi v7.4h, #0x89, lsl #8
+ 2a28: 0f04a547 movi v7.4h, #0x8a, lsl #8
+ 2a2c: 0f04a567 movi v7.4h, #0x8b, lsl #8
+ 2a30: 0f04a587 movi v7.4h, #0x8c, lsl #8
+ 2a34: 0f04a5a7 movi v7.4h, #0x8d, lsl #8
+ 2a38: 0f04a5c7 movi v7.4h, #0x8e, lsl #8
+ 2a3c: 0f04a5e7 movi v7.4h, #0x8f, lsl #8
+ 2a40: 0f04a607 movi v7.4h, #0x90, lsl #8
+ 2a44: 0f04a627 movi v7.4h, #0x91, lsl #8
+ 2a48: 0f04a647 movi v7.4h, #0x92, lsl #8
+ 2a4c: 0f04a667 movi v7.4h, #0x93, lsl #8
+ 2a50: 0f04a687 movi v7.4h, #0x94, lsl #8
+ 2a54: 0f04a6a7 movi v7.4h, #0x95, lsl #8
+ 2a58: 0f04a6c7 movi v7.4h, #0x96, lsl #8
+ 2a5c: 0f04a6e7 movi v7.4h, #0x97, lsl #8
+ 2a60: 0f04a707 movi v7.4h, #0x98, lsl #8
+ 2a64: 0f04a727 movi v7.4h, #0x99, lsl #8
+ 2a68: 0f04a747 movi v7.4h, #0x9a, lsl #8
+ 2a6c: 0f04a767 movi v7.4h, #0x9b, lsl #8
+ 2a70: 0f04a787 movi v7.4h, #0x9c, lsl #8
+ 2a74: 0f04a7a7 movi v7.4h, #0x9d, lsl #8
+ 2a78: 0f04a7c7 movi v7.4h, #0x9e, lsl #8
+ 2a7c: 0f04a7e7 movi v7.4h, #0x9f, lsl #8
+ 2a80: 0f05a407 movi v7.4h, #0xa0, lsl #8
+ 2a84: 0f05a427 movi v7.4h, #0xa1, lsl #8
+ 2a88: 0f05a447 movi v7.4h, #0xa2, lsl #8
+ 2a8c: 0f05a467 movi v7.4h, #0xa3, lsl #8
+ 2a90: 0f05a487 movi v7.4h, #0xa4, lsl #8
+ 2a94: 0f05a4a7 movi v7.4h, #0xa5, lsl #8
+ 2a98: 0f05a4c7 movi v7.4h, #0xa6, lsl #8
+ 2a9c: 0f05a4e7 movi v7.4h, #0xa7, lsl #8
+ 2aa0: 0f05a507 movi v7.4h, #0xa8, lsl #8
+ 2aa4: 0f05a527 movi v7.4h, #0xa9, lsl #8
+ 2aa8: 0f05a547 movi v7.4h, #0xaa, lsl #8
+ 2aac: 0f05a567 movi v7.4h, #0xab, lsl #8
+ 2ab0: 0f05a587 movi v7.4h, #0xac, lsl #8
+ 2ab4: 0f05a5a7 movi v7.4h, #0xad, lsl #8
+ 2ab8: 0f05a5c7 movi v7.4h, #0xae, lsl #8
+ 2abc: 0f05a5e7 movi v7.4h, #0xaf, lsl #8
+ 2ac0: 0f05a607 movi v7.4h, #0xb0, lsl #8
+ 2ac4: 0f05a627 movi v7.4h, #0xb1, lsl #8
+ 2ac8: 0f05a647 movi v7.4h, #0xb2, lsl #8
+ 2acc: 0f05a667 movi v7.4h, #0xb3, lsl #8
+ 2ad0: 0f05a687 movi v7.4h, #0xb4, lsl #8
+ 2ad4: 0f05a6a7 movi v7.4h, #0xb5, lsl #8
+ 2ad8: 0f05a6c7 movi v7.4h, #0xb6, lsl #8
+ 2adc: 0f05a6e7 movi v7.4h, #0xb7, lsl #8
+ 2ae0: 0f05a707 movi v7.4h, #0xb8, lsl #8
+ 2ae4: 0f05a727 movi v7.4h, #0xb9, lsl #8
+ 2ae8: 0f05a747 movi v7.4h, #0xba, lsl #8
+ 2aec: 0f05a767 movi v7.4h, #0xbb, lsl #8
+ 2af0: 0f05a787 movi v7.4h, #0xbc, lsl #8
+ 2af4: 0f05a7a7 movi v7.4h, #0xbd, lsl #8
+ 2af8: 0f05a7c7 movi v7.4h, #0xbe, lsl #8
+ 2afc: 0f05a7e7 movi v7.4h, #0xbf, lsl #8
+ 2b00: 0f06a407 movi v7.4h, #0xc0, lsl #8
+ 2b04: 0f06a427 movi v7.4h, #0xc1, lsl #8
+ 2b08: 0f06a447 movi v7.4h, #0xc2, lsl #8
+ 2b0c: 0f06a467 movi v7.4h, #0xc3, lsl #8
+ 2b10: 0f06a487 movi v7.4h, #0xc4, lsl #8
+ 2b14: 0f06a4a7 movi v7.4h, #0xc5, lsl #8
+ 2b18: 0f06a4c7 movi v7.4h, #0xc6, lsl #8
+ 2b1c: 0f06a4e7 movi v7.4h, #0xc7, lsl #8
+ 2b20: 0f06a507 movi v7.4h, #0xc8, lsl #8
+ 2b24: 0f06a527 movi v7.4h, #0xc9, lsl #8
+ 2b28: 0f06a547 movi v7.4h, #0xca, lsl #8
+ 2b2c: 0f06a567 movi v7.4h, #0xcb, lsl #8
+ 2b30: 0f06a587 movi v7.4h, #0xcc, lsl #8
+ 2b34: 0f06a5a7 movi v7.4h, #0xcd, lsl #8
+ 2b38: 0f06a5c7 movi v7.4h, #0xce, lsl #8
+ 2b3c: 0f06a5e7 movi v7.4h, #0xcf, lsl #8
+ 2b40: 0f06a607 movi v7.4h, #0xd0, lsl #8
+ 2b44: 0f06a627 movi v7.4h, #0xd1, lsl #8
+ 2b48: 0f06a647 movi v7.4h, #0xd2, lsl #8
+ 2b4c: 0f06a667 movi v7.4h, #0xd3, lsl #8
+ 2b50: 0f06a687 movi v7.4h, #0xd4, lsl #8
+ 2b54: 0f06a6a7 movi v7.4h, #0xd5, lsl #8
+ 2b58: 0f06a6c7 movi v7.4h, #0xd6, lsl #8
+ 2b5c: 0f06a6e7 movi v7.4h, #0xd7, lsl #8
+ 2b60: 0f06a707 movi v7.4h, #0xd8, lsl #8
+ 2b64: 0f06a727 movi v7.4h, #0xd9, lsl #8
+ 2b68: 0f06a747 movi v7.4h, #0xda, lsl #8
+ 2b6c: 0f06a767 movi v7.4h, #0xdb, lsl #8
+ 2b70: 0f06a787 movi v7.4h, #0xdc, lsl #8
+ 2b74: 0f06a7a7 movi v7.4h, #0xdd, lsl #8
+ 2b78: 0f06a7c7 movi v7.4h, #0xde, lsl #8
+ 2b7c: 0f06a7e7 movi v7.4h, #0xdf, lsl #8
+ 2b80: 0f07a407 movi v7.4h, #0xe0, lsl #8
+ 2b84: 0f07a427 movi v7.4h, #0xe1, lsl #8
+ 2b88: 0f07a447 movi v7.4h, #0xe2, lsl #8
+ 2b8c: 0f07a467 movi v7.4h, #0xe3, lsl #8
+ 2b90: 0f07a487 movi v7.4h, #0xe4, lsl #8
+ 2b94: 0f07a4a7 movi v7.4h, #0xe5, lsl #8
+ 2b98: 0f07a4c7 movi v7.4h, #0xe6, lsl #8
+ 2b9c: 0f07a4e7 movi v7.4h, #0xe7, lsl #8
+ 2ba0: 0f07a507 movi v7.4h, #0xe8, lsl #8
+ 2ba4: 0f07a527 movi v7.4h, #0xe9, lsl #8
+ 2ba8: 0f07a547 movi v7.4h, #0xea, lsl #8
+ 2bac: 0f07a567 movi v7.4h, #0xeb, lsl #8
+ 2bb0: 0f07a587 movi v7.4h, #0xec, lsl #8
+ 2bb4: 0f07a5a7 movi v7.4h, #0xed, lsl #8
+ 2bb8: 0f07a5c7 movi v7.4h, #0xee, lsl #8
+ 2bbc: 0f07a5e7 movi v7.4h, #0xef, lsl #8
+ 2bc0: 0f07a607 movi v7.4h, #0xf0, lsl #8
+ 2bc4: 0f07a627 movi v7.4h, #0xf1, lsl #8
+ 2bc8: 0f07a647 movi v7.4h, #0xf2, lsl #8
+ 2bcc: 0f07a667 movi v7.4h, #0xf3, lsl #8
+ 2bd0: 0f07a687 movi v7.4h, #0xf4, lsl #8
+ 2bd4: 0f07a6a7 movi v7.4h, #0xf5, lsl #8
+ 2bd8: 0f07a6c7 movi v7.4h, #0xf6, lsl #8
+ 2bdc: 0f07a6e7 movi v7.4h, #0xf7, lsl #8
+ 2be0: 0f07a707 movi v7.4h, #0xf8, lsl #8
+ 2be4: 0f07a727 movi v7.4h, #0xf9, lsl #8
+ 2be8: 0f07a747 movi v7.4h, #0xfa, lsl #8
+ 2bec: 0f07a767 movi v7.4h, #0xfb, lsl #8
+ 2bf0: 0f07a787 movi v7.4h, #0xfc, lsl #8
+ 2bf4: 0f07a7a7 movi v7.4h, #0xfd, lsl #8
+ 2bf8: 0f07a7c7 movi v7.4h, #0xfe, lsl #8
+ 2bfc: 0f07a7e7 movi v7.4h, #0xff, lsl #8
+ 2c00: 0f00840f movi v15.4h, #0x0
+ 2c04: 0f00842f movi v15.4h, #0x1
+ 2c08: 0f00844f movi v15.4h, #0x2
+ 2c0c: 0f00846f movi v15.4h, #0x3
+ 2c10: 0f00848f movi v15.4h, #0x4
+ 2c14: 0f0084af movi v15.4h, #0x5
+ 2c18: 0f0084cf movi v15.4h, #0x6
+ 2c1c: 0f0084ef movi v15.4h, #0x7
+ 2c20: 0f00850f movi v15.4h, #0x8
+ 2c24: 0f00852f movi v15.4h, #0x9
+ 2c28: 0f00854f movi v15.4h, #0xa
+ 2c2c: 0f00856f movi v15.4h, #0xb
+ 2c30: 0f00858f movi v15.4h, #0xc
+ 2c34: 0f0085af movi v15.4h, #0xd
+ 2c38: 0f0085cf movi v15.4h, #0xe
+ 2c3c: 0f0085ef movi v15.4h, #0xf
+ 2c40: 0f00860f movi v15.4h, #0x10
+ 2c44: 0f00862f movi v15.4h, #0x11
+ 2c48: 0f00864f movi v15.4h, #0x12
+ 2c4c: 0f00866f movi v15.4h, #0x13
+ 2c50: 0f00868f movi v15.4h, #0x14
+ 2c54: 0f0086af movi v15.4h, #0x15
+ 2c58: 0f0086cf movi v15.4h, #0x16
+ 2c5c: 0f0086ef movi v15.4h, #0x17
+ 2c60: 0f00870f movi v15.4h, #0x18
+ 2c64: 0f00872f movi v15.4h, #0x19
+ 2c68: 0f00874f movi v15.4h, #0x1a
+ 2c6c: 0f00876f movi v15.4h, #0x1b
+ 2c70: 0f00878f movi v15.4h, #0x1c
+ 2c74: 0f0087af movi v15.4h, #0x1d
+ 2c78: 0f0087cf movi v15.4h, #0x1e
+ 2c7c: 0f0087ef movi v15.4h, #0x1f
+ 2c80: 0f01840f movi v15.4h, #0x20
+ 2c84: 0f01842f movi v15.4h, #0x21
+ 2c88: 0f01844f movi v15.4h, #0x22
+ 2c8c: 0f01846f movi v15.4h, #0x23
+ 2c90: 0f01848f movi v15.4h, #0x24
+ 2c94: 0f0184af movi v15.4h, #0x25
+ 2c98: 0f0184cf movi v15.4h, #0x26
+ 2c9c: 0f0184ef movi v15.4h, #0x27
+ 2ca0: 0f01850f movi v15.4h, #0x28
+ 2ca4: 0f01852f movi v15.4h, #0x29
+ 2ca8: 0f01854f movi v15.4h, #0x2a
+ 2cac: 0f01856f movi v15.4h, #0x2b
+ 2cb0: 0f01858f movi v15.4h, #0x2c
+ 2cb4: 0f0185af movi v15.4h, #0x2d
+ 2cb8: 0f0185cf movi v15.4h, #0x2e
+ 2cbc: 0f0185ef movi v15.4h, #0x2f
+ 2cc0: 0f01860f movi v15.4h, #0x30
+ 2cc4: 0f01862f movi v15.4h, #0x31
+ 2cc8: 0f01864f movi v15.4h, #0x32
+ 2ccc: 0f01866f movi v15.4h, #0x33
+ 2cd0: 0f01868f movi v15.4h, #0x34
+ 2cd4: 0f0186af movi v15.4h, #0x35
+ 2cd8: 0f0186cf movi v15.4h, #0x36
+ 2cdc: 0f0186ef movi v15.4h, #0x37
+ 2ce0: 0f01870f movi v15.4h, #0x38
+ 2ce4: 0f01872f movi v15.4h, #0x39
+ 2ce8: 0f01874f movi v15.4h, #0x3a
+ 2cec: 0f01876f movi v15.4h, #0x3b
+ 2cf0: 0f01878f movi v15.4h, #0x3c
+ 2cf4: 0f0187af movi v15.4h, #0x3d
+ 2cf8: 0f0187cf movi v15.4h, #0x3e
+ 2cfc: 0f0187ef movi v15.4h, #0x3f
+ 2d00: 0f02840f movi v15.4h, #0x40
+ 2d04: 0f02842f movi v15.4h, #0x41
+ 2d08: 0f02844f movi v15.4h, #0x42
+ 2d0c: 0f02846f movi v15.4h, #0x43
+ 2d10: 0f02848f movi v15.4h, #0x44
+ 2d14: 0f0284af movi v15.4h, #0x45
+ 2d18: 0f0284cf movi v15.4h, #0x46
+ 2d1c: 0f0284ef movi v15.4h, #0x47
+ 2d20: 0f02850f movi v15.4h, #0x48
+ 2d24: 0f02852f movi v15.4h, #0x49
+ 2d28: 0f02854f movi v15.4h, #0x4a
+ 2d2c: 0f02856f movi v15.4h, #0x4b
+ 2d30: 0f02858f movi v15.4h, #0x4c
+ 2d34: 0f0285af movi v15.4h, #0x4d
+ 2d38: 0f0285cf movi v15.4h, #0x4e
+ 2d3c: 0f0285ef movi v15.4h, #0x4f
+ 2d40: 0f02860f movi v15.4h, #0x50
+ 2d44: 0f02862f movi v15.4h, #0x51
+ 2d48: 0f02864f movi v15.4h, #0x52
+ 2d4c: 0f02866f movi v15.4h, #0x53
+ 2d50: 0f02868f movi v15.4h, #0x54
+ 2d54: 0f0286af movi v15.4h, #0x55
+ 2d58: 0f0286cf movi v15.4h, #0x56
+ 2d5c: 0f0286ef movi v15.4h, #0x57
+ 2d60: 0f02870f movi v15.4h, #0x58
+ 2d64: 0f02872f movi v15.4h, #0x59
+ 2d68: 0f02874f movi v15.4h, #0x5a
+ 2d6c: 0f02876f movi v15.4h, #0x5b
+ 2d70: 0f02878f movi v15.4h, #0x5c
+ 2d74: 0f0287af movi v15.4h, #0x5d
+ 2d78: 0f0287cf movi v15.4h, #0x5e
+ 2d7c: 0f0287ef movi v15.4h, #0x5f
+ 2d80: 0f03840f movi v15.4h, #0x60
+ 2d84: 0f03842f movi v15.4h, #0x61
+ 2d88: 0f03844f movi v15.4h, #0x62
+ 2d8c: 0f03846f movi v15.4h, #0x63
+ 2d90: 0f03848f movi v15.4h, #0x64
+ 2d94: 0f0384af movi v15.4h, #0x65
+ 2d98: 0f0384cf movi v15.4h, #0x66
+ 2d9c: 0f0384ef movi v15.4h, #0x67
+ 2da0: 0f03850f movi v15.4h, #0x68
+ 2da4: 0f03852f movi v15.4h, #0x69
+ 2da8: 0f03854f movi v15.4h, #0x6a
+ 2dac: 0f03856f movi v15.4h, #0x6b
+ 2db0: 0f03858f movi v15.4h, #0x6c
+ 2db4: 0f0385af movi v15.4h, #0x6d
+ 2db8: 0f0385cf movi v15.4h, #0x6e
+ 2dbc: 0f0385ef movi v15.4h, #0x6f
+ 2dc0: 0f03860f movi v15.4h, #0x70
+ 2dc4: 0f03862f movi v15.4h, #0x71
+ 2dc8: 0f03864f movi v15.4h, #0x72
+ 2dcc: 0f03866f movi v15.4h, #0x73
+ 2dd0: 0f03868f movi v15.4h, #0x74
+ 2dd4: 0f0386af movi v15.4h, #0x75
+ 2dd8: 0f0386cf movi v15.4h, #0x76
+ 2ddc: 0f0386ef movi v15.4h, #0x77
+ 2de0: 0f03870f movi v15.4h, #0x78
+ 2de4: 0f03872f movi v15.4h, #0x79
+ 2de8: 0f03874f movi v15.4h, #0x7a
+ 2dec: 0f03876f movi v15.4h, #0x7b
+ 2df0: 0f03878f movi v15.4h, #0x7c
+ 2df4: 0f0387af movi v15.4h, #0x7d
+ 2df8: 0f0387cf movi v15.4h, #0x7e
+ 2dfc: 0f0387ef movi v15.4h, #0x7f
+ 2e00: 0f04840f movi v15.4h, #0x80
+ 2e04: 0f04842f movi v15.4h, #0x81
+ 2e08: 0f04844f movi v15.4h, #0x82
+ 2e0c: 0f04846f movi v15.4h, #0x83
+ 2e10: 0f04848f movi v15.4h, #0x84
+ 2e14: 0f0484af movi v15.4h, #0x85
+ 2e18: 0f0484cf movi v15.4h, #0x86
+ 2e1c: 0f0484ef movi v15.4h, #0x87
+ 2e20: 0f04850f movi v15.4h, #0x88
+ 2e24: 0f04852f movi v15.4h, #0x89
+ 2e28: 0f04854f movi v15.4h, #0x8a
+ 2e2c: 0f04856f movi v15.4h, #0x8b
+ 2e30: 0f04858f movi v15.4h, #0x8c
+ 2e34: 0f0485af movi v15.4h, #0x8d
+ 2e38: 0f0485cf movi v15.4h, #0x8e
+ 2e3c: 0f0485ef movi v15.4h, #0x8f
+ 2e40: 0f04860f movi v15.4h, #0x90
+ 2e44: 0f04862f movi v15.4h, #0x91
+ 2e48: 0f04864f movi v15.4h, #0x92
+ 2e4c: 0f04866f movi v15.4h, #0x93
+ 2e50: 0f04868f movi v15.4h, #0x94
+ 2e54: 0f0486af movi v15.4h, #0x95
+ 2e58: 0f0486cf movi v15.4h, #0x96
+ 2e5c: 0f0486ef movi v15.4h, #0x97
+ 2e60: 0f04870f movi v15.4h, #0x98
+ 2e64: 0f04872f movi v15.4h, #0x99
+ 2e68: 0f04874f movi v15.4h, #0x9a
+ 2e6c: 0f04876f movi v15.4h, #0x9b
+ 2e70: 0f04878f movi v15.4h, #0x9c
+ 2e74: 0f0487af movi v15.4h, #0x9d
+ 2e78: 0f0487cf movi v15.4h, #0x9e
+ 2e7c: 0f0487ef movi v15.4h, #0x9f
+ 2e80: 0f05840f movi v15.4h, #0xa0
+ 2e84: 0f05842f movi v15.4h, #0xa1
+ 2e88: 0f05844f movi v15.4h, #0xa2
+ 2e8c: 0f05846f movi v15.4h, #0xa3
+ 2e90: 0f05848f movi v15.4h, #0xa4
+ 2e94: 0f0584af movi v15.4h, #0xa5
+ 2e98: 0f0584cf movi v15.4h, #0xa6
+ 2e9c: 0f0584ef movi v15.4h, #0xa7
+ 2ea0: 0f05850f movi v15.4h, #0xa8
+ 2ea4: 0f05852f movi v15.4h, #0xa9
+ 2ea8: 0f05854f movi v15.4h, #0xaa
+ 2eac: 0f05856f movi v15.4h, #0xab
+ 2eb0: 0f05858f movi v15.4h, #0xac
+ 2eb4: 0f0585af movi v15.4h, #0xad
+ 2eb8: 0f0585cf movi v15.4h, #0xae
+ 2ebc: 0f0585ef movi v15.4h, #0xaf
+ 2ec0: 0f05860f movi v15.4h, #0xb0
+ 2ec4: 0f05862f movi v15.4h, #0xb1
+ 2ec8: 0f05864f movi v15.4h, #0xb2
+ 2ecc: 0f05866f movi v15.4h, #0xb3
+ 2ed0: 0f05868f movi v15.4h, #0xb4
+ 2ed4: 0f0586af movi v15.4h, #0xb5
+ 2ed8: 0f0586cf movi v15.4h, #0xb6
+ 2edc: 0f0586ef movi v15.4h, #0xb7
+ 2ee0: 0f05870f movi v15.4h, #0xb8
+ 2ee4: 0f05872f movi v15.4h, #0xb9
+ 2ee8: 0f05874f movi v15.4h, #0xba
+ 2eec: 0f05876f movi v15.4h, #0xbb
+ 2ef0: 0f05878f movi v15.4h, #0xbc
+ 2ef4: 0f0587af movi v15.4h, #0xbd
+ 2ef8: 0f0587cf movi v15.4h, #0xbe
+ 2efc: 0f0587ef movi v15.4h, #0xbf
+ 2f00: 0f06840f movi v15.4h, #0xc0
+ 2f04: 0f06842f movi v15.4h, #0xc1
+ 2f08: 0f06844f movi v15.4h, #0xc2
+ 2f0c: 0f06846f movi v15.4h, #0xc3
+ 2f10: 0f06848f movi v15.4h, #0xc4
+ 2f14: 0f0684af movi v15.4h, #0xc5
+ 2f18: 0f0684cf movi v15.4h, #0xc6
+ 2f1c: 0f0684ef movi v15.4h, #0xc7
+ 2f20: 0f06850f movi v15.4h, #0xc8
+ 2f24: 0f06852f movi v15.4h, #0xc9
+ 2f28: 0f06854f movi v15.4h, #0xca
+ 2f2c: 0f06856f movi v15.4h, #0xcb
+ 2f30: 0f06858f movi v15.4h, #0xcc
+ 2f34: 0f0685af movi v15.4h, #0xcd
+ 2f38: 0f0685cf movi v15.4h, #0xce
+ 2f3c: 0f0685ef movi v15.4h, #0xcf
+ 2f40: 0f06860f movi v15.4h, #0xd0
+ 2f44: 0f06862f movi v15.4h, #0xd1
+ 2f48: 0f06864f movi v15.4h, #0xd2
+ 2f4c: 0f06866f movi v15.4h, #0xd3
+ 2f50: 0f06868f movi v15.4h, #0xd4
+ 2f54: 0f0686af movi v15.4h, #0xd5
+ 2f58: 0f0686cf movi v15.4h, #0xd6
+ 2f5c: 0f0686ef movi v15.4h, #0xd7
+ 2f60: 0f06870f movi v15.4h, #0xd8
+ 2f64: 0f06872f movi v15.4h, #0xd9
+ 2f68: 0f06874f movi v15.4h, #0xda
+ 2f6c: 0f06876f movi v15.4h, #0xdb
+ 2f70: 0f06878f movi v15.4h, #0xdc
+ 2f74: 0f0687af movi v15.4h, #0xdd
+ 2f78: 0f0687cf movi v15.4h, #0xde
+ 2f7c: 0f0687ef movi v15.4h, #0xdf
+ 2f80: 0f07840f movi v15.4h, #0xe0
+ 2f84: 0f07842f movi v15.4h, #0xe1
+ 2f88: 0f07844f movi v15.4h, #0xe2
+ 2f8c: 0f07846f movi v15.4h, #0xe3
+ 2f90: 0f07848f movi v15.4h, #0xe4
+ 2f94: 0f0784af movi v15.4h, #0xe5
+ 2f98: 0f0784cf movi v15.4h, #0xe6
+ 2f9c: 0f0784ef movi v15.4h, #0xe7
+ 2fa0: 0f07850f movi v15.4h, #0xe8
+ 2fa4: 0f07852f movi v15.4h, #0xe9
+ 2fa8: 0f07854f movi v15.4h, #0xea
+ 2fac: 0f07856f movi v15.4h, #0xeb
+ 2fb0: 0f07858f movi v15.4h, #0xec
+ 2fb4: 0f0785af movi v15.4h, #0xed
+ 2fb8: 0f0785cf movi v15.4h, #0xee
+ 2fbc: 0f0785ef movi v15.4h, #0xef
+ 2fc0: 0f07860f movi v15.4h, #0xf0
+ 2fc4: 0f07862f movi v15.4h, #0xf1
+ 2fc8: 0f07864f movi v15.4h, #0xf2
+ 2fcc: 0f07866f movi v15.4h, #0xf3
+ 2fd0: 0f07868f movi v15.4h, #0xf4
+ 2fd4: 0f0786af movi v15.4h, #0xf5
+ 2fd8: 0f0786cf movi v15.4h, #0xf6
+ 2fdc: 0f0786ef movi v15.4h, #0xf7
+ 2fe0: 0f07870f movi v15.4h, #0xf8
+ 2fe4: 0f07872f movi v15.4h, #0xf9
+ 2fe8: 0f07874f movi v15.4h, #0xfa
+ 2fec: 0f07876f movi v15.4h, #0xfb
+ 2ff0: 0f07878f movi v15.4h, #0xfc
+ 2ff4: 0f0787af movi v15.4h, #0xfd
+ 2ff8: 0f0787cf movi v15.4h, #0xfe
+ 2ffc: 0f0787ef movi v15.4h, #0xff
+ 3000: 4f008407 movi v7.8h, #0x0
+ 3004: 4f008427 movi v7.8h, #0x1
+ 3008: 4f008447 movi v7.8h, #0x2
+ 300c: 4f008467 movi v7.8h, #0x3
+ 3010: 4f008487 movi v7.8h, #0x4
+ 3014: 4f0084a7 movi v7.8h, #0x5
+ 3018: 4f0084c7 movi v7.8h, #0x6
+ 301c: 4f0084e7 movi v7.8h, #0x7
+ 3020: 4f008507 movi v7.8h, #0x8
+ 3024: 4f008527 movi v7.8h, #0x9
+ 3028: 4f008547 movi v7.8h, #0xa
+ 302c: 4f008567 movi v7.8h, #0xb
+ 3030: 4f008587 movi v7.8h, #0xc
+ 3034: 4f0085a7 movi v7.8h, #0xd
+ 3038: 4f0085c7 movi v7.8h, #0xe
+ 303c: 4f0085e7 movi v7.8h, #0xf
+ 3040: 4f008607 movi v7.8h, #0x10
+ 3044: 4f008627 movi v7.8h, #0x11
+ 3048: 4f008647 movi v7.8h, #0x12
+ 304c: 4f008667 movi v7.8h, #0x13
+ 3050: 4f008687 movi v7.8h, #0x14
+ 3054: 4f0086a7 movi v7.8h, #0x15
+ 3058: 4f0086c7 movi v7.8h, #0x16
+ 305c: 4f0086e7 movi v7.8h, #0x17
+ 3060: 4f008707 movi v7.8h, #0x18
+ 3064: 4f008727 movi v7.8h, #0x19
+ 3068: 4f008747 movi v7.8h, #0x1a
+ 306c: 4f008767 movi v7.8h, #0x1b
+ 3070: 4f008787 movi v7.8h, #0x1c
+ 3074: 4f0087a7 movi v7.8h, #0x1d
+ 3078: 4f0087c7 movi v7.8h, #0x1e
+ 307c: 4f0087e7 movi v7.8h, #0x1f
+ 3080: 4f018407 movi v7.8h, #0x20
+ 3084: 4f018427 movi v7.8h, #0x21
+ 3088: 4f018447 movi v7.8h, #0x22
+ 308c: 4f018467 movi v7.8h, #0x23
+ 3090: 4f018487 movi v7.8h, #0x24
+ 3094: 4f0184a7 movi v7.8h, #0x25
+ 3098: 4f0184c7 movi v7.8h, #0x26
+ 309c: 4f0184e7 movi v7.8h, #0x27
+ 30a0: 4f018507 movi v7.8h, #0x28
+ 30a4: 4f018527 movi v7.8h, #0x29
+ 30a8: 4f018547 movi v7.8h, #0x2a
+ 30ac: 4f018567 movi v7.8h, #0x2b
+ 30b0: 4f018587 movi v7.8h, #0x2c
+ 30b4: 4f0185a7 movi v7.8h, #0x2d
+ 30b8: 4f0185c7 movi v7.8h, #0x2e
+ 30bc: 4f0185e7 movi v7.8h, #0x2f
+ 30c0: 4f018607 movi v7.8h, #0x30
+ 30c4: 4f018627 movi v7.8h, #0x31
+ 30c8: 4f018647 movi v7.8h, #0x32
+ 30cc: 4f018667 movi v7.8h, #0x33
+ 30d0: 4f018687 movi v7.8h, #0x34
+ 30d4: 4f0186a7 movi v7.8h, #0x35
+ 30d8: 4f0186c7 movi v7.8h, #0x36
+ 30dc: 4f0186e7 movi v7.8h, #0x37
+ 30e0: 4f018707 movi v7.8h, #0x38
+ 30e4: 4f018727 movi v7.8h, #0x39
+ 30e8: 4f018747 movi v7.8h, #0x3a
+ 30ec: 4f018767 movi v7.8h, #0x3b
+ 30f0: 4f018787 movi v7.8h, #0x3c
+ 30f4: 4f0187a7 movi v7.8h, #0x3d
+ 30f8: 4f0187c7 movi v7.8h, #0x3e
+ 30fc: 4f0187e7 movi v7.8h, #0x3f
+ 3100: 4f028407 movi v7.8h, #0x40
+ 3104: 4f028427 movi v7.8h, #0x41
+ 3108: 4f028447 movi v7.8h, #0x42
+ 310c: 4f028467 movi v7.8h, #0x43
+ 3110: 4f028487 movi v7.8h, #0x44
+ 3114: 4f0284a7 movi v7.8h, #0x45
+ 3118: 4f0284c7 movi v7.8h, #0x46
+ 311c: 4f0284e7 movi v7.8h, #0x47
+ 3120: 4f028507 movi v7.8h, #0x48
+ 3124: 4f028527 movi v7.8h, #0x49
+ 3128: 4f028547 movi v7.8h, #0x4a
+ 312c: 4f028567 movi v7.8h, #0x4b
+ 3130: 4f028587 movi v7.8h, #0x4c
+ 3134: 4f0285a7 movi v7.8h, #0x4d
+ 3138: 4f0285c7 movi v7.8h, #0x4e
+ 313c: 4f0285e7 movi v7.8h, #0x4f
+ 3140: 4f028607 movi v7.8h, #0x50
+ 3144: 4f028627 movi v7.8h, #0x51
+ 3148: 4f028647 movi v7.8h, #0x52
+ 314c: 4f028667 movi v7.8h, #0x53
+ 3150: 4f028687 movi v7.8h, #0x54
+ 3154: 4f0286a7 movi v7.8h, #0x55
+ 3158: 4f0286c7 movi v7.8h, #0x56
+ 315c: 4f0286e7 movi v7.8h, #0x57
+ 3160: 4f028707 movi v7.8h, #0x58
+ 3164: 4f028727 movi v7.8h, #0x59
+ 3168: 4f028747 movi v7.8h, #0x5a
+ 316c: 4f028767 movi v7.8h, #0x5b
+ 3170: 4f028787 movi v7.8h, #0x5c
+ 3174: 4f0287a7 movi v7.8h, #0x5d
+ 3178: 4f0287c7 movi v7.8h, #0x5e
+ 317c: 4f0287e7 movi v7.8h, #0x5f
+ 3180: 4f038407 movi v7.8h, #0x60
+ 3184: 4f038427 movi v7.8h, #0x61
+ 3188: 4f038447 movi v7.8h, #0x62
+ 318c: 4f038467 movi v7.8h, #0x63
+ 3190: 4f038487 movi v7.8h, #0x64
+ 3194: 4f0384a7 movi v7.8h, #0x65
+ 3198: 4f0384c7 movi v7.8h, #0x66
+ 319c: 4f0384e7 movi v7.8h, #0x67
+ 31a0: 4f038507 movi v7.8h, #0x68
+ 31a4: 4f038527 movi v7.8h, #0x69
+ 31a8: 4f038547 movi v7.8h, #0x6a
+ 31ac: 4f038567 movi v7.8h, #0x6b
+ 31b0: 4f038587 movi v7.8h, #0x6c
+ 31b4: 4f0385a7 movi v7.8h, #0x6d
+ 31b8: 4f0385c7 movi v7.8h, #0x6e
+ 31bc: 4f0385e7 movi v7.8h, #0x6f
+ 31c0: 4f038607 movi v7.8h, #0x70
+ 31c4: 4f038627 movi v7.8h, #0x71
+ 31c8: 4f038647 movi v7.8h, #0x72
+ 31cc: 4f038667 movi v7.8h, #0x73
+ 31d0: 4f038687 movi v7.8h, #0x74
+ 31d4: 4f0386a7 movi v7.8h, #0x75
+ 31d8: 4f0386c7 movi v7.8h, #0x76
+ 31dc: 4f0386e7 movi v7.8h, #0x77
+ 31e0: 4f038707 movi v7.8h, #0x78
+ 31e4: 4f038727 movi v7.8h, #0x79
+ 31e8: 4f038747 movi v7.8h, #0x7a
+ 31ec: 4f038767 movi v7.8h, #0x7b
+ 31f0: 4f038787 movi v7.8h, #0x7c
+ 31f4: 4f0387a7 movi v7.8h, #0x7d
+ 31f8: 4f0387c7 movi v7.8h, #0x7e
+ 31fc: 4f0387e7 movi v7.8h, #0x7f
+ 3200: 4f048407 movi v7.8h, #0x80
+ 3204: 4f048427 movi v7.8h, #0x81
+ 3208: 4f048447 movi v7.8h, #0x82
+ 320c: 4f048467 movi v7.8h, #0x83
+ 3210: 4f048487 movi v7.8h, #0x84
+ 3214: 4f0484a7 movi v7.8h, #0x85
+ 3218: 4f0484c7 movi v7.8h, #0x86
+ 321c: 4f0484e7 movi v7.8h, #0x87
+ 3220: 4f048507 movi v7.8h, #0x88
+ 3224: 4f048527 movi v7.8h, #0x89
+ 3228: 4f048547 movi v7.8h, #0x8a
+ 322c: 4f048567 movi v7.8h, #0x8b
+ 3230: 4f048587 movi v7.8h, #0x8c
+ 3234: 4f0485a7 movi v7.8h, #0x8d
+ 3238: 4f0485c7 movi v7.8h, #0x8e
+ 323c: 4f0485e7 movi v7.8h, #0x8f
+ 3240: 4f048607 movi v7.8h, #0x90
+ 3244: 4f048627 movi v7.8h, #0x91
+ 3248: 4f048647 movi v7.8h, #0x92
+ 324c: 4f048667 movi v7.8h, #0x93
+ 3250: 4f048687 movi v7.8h, #0x94
+ 3254: 4f0486a7 movi v7.8h, #0x95
+ 3258: 4f0486c7 movi v7.8h, #0x96
+ 325c: 4f0486e7 movi v7.8h, #0x97
+ 3260: 4f048707 movi v7.8h, #0x98
+ 3264: 4f048727 movi v7.8h, #0x99
+ 3268: 4f048747 movi v7.8h, #0x9a
+ 326c: 4f048767 movi v7.8h, #0x9b
+ 3270: 4f048787 movi v7.8h, #0x9c
+ 3274: 4f0487a7 movi v7.8h, #0x9d
+ 3278: 4f0487c7 movi v7.8h, #0x9e
+ 327c: 4f0487e7 movi v7.8h, #0x9f
+ 3280: 4f058407 movi v7.8h, #0xa0
+ 3284: 4f058427 movi v7.8h, #0xa1
+ 3288: 4f058447 movi v7.8h, #0xa2
+ 328c: 4f058467 movi v7.8h, #0xa3
+ 3290: 4f058487 movi v7.8h, #0xa4
+ 3294: 4f0584a7 movi v7.8h, #0xa5
+ 3298: 4f0584c7 movi v7.8h, #0xa6
+ 329c: 4f0584e7 movi v7.8h, #0xa7
+ 32a0: 4f058507 movi v7.8h, #0xa8
+ 32a4: 4f058527 movi v7.8h, #0xa9
+ 32a8: 4f058547 movi v7.8h, #0xaa
+ 32ac: 4f058567 movi v7.8h, #0xab
+ 32b0: 4f058587 movi v7.8h, #0xac
+ 32b4: 4f0585a7 movi v7.8h, #0xad
+ 32b8: 4f0585c7 movi v7.8h, #0xae
+ 32bc: 4f0585e7 movi v7.8h, #0xaf
+ 32c0: 4f058607 movi v7.8h, #0xb0
+ 32c4: 4f058627 movi v7.8h, #0xb1
+ 32c8: 4f058647 movi v7.8h, #0xb2
+ 32cc: 4f058667 movi v7.8h, #0xb3
+ 32d0: 4f058687 movi v7.8h, #0xb4
+ 32d4: 4f0586a7 movi v7.8h, #0xb5
+ 32d8: 4f0586c7 movi v7.8h, #0xb6
+ 32dc: 4f0586e7 movi v7.8h, #0xb7
+ 32e0: 4f058707 movi v7.8h, #0xb8
+ 32e4: 4f058727 movi v7.8h, #0xb9
+ 32e8: 4f058747 movi v7.8h, #0xba
+ 32ec: 4f058767 movi v7.8h, #0xbb
+ 32f0: 4f058787 movi v7.8h, #0xbc
+ 32f4: 4f0587a7 movi v7.8h, #0xbd
+ 32f8: 4f0587c7 movi v7.8h, #0xbe
+ 32fc: 4f0587e7 movi v7.8h, #0xbf
+ 3300: 4f068407 movi v7.8h, #0xc0
+ 3304: 4f068427 movi v7.8h, #0xc1
+ 3308: 4f068447 movi v7.8h, #0xc2
+ 330c: 4f068467 movi v7.8h, #0xc3
+ 3310: 4f068487 movi v7.8h, #0xc4
+ 3314: 4f0684a7 movi v7.8h, #0xc5
+ 3318: 4f0684c7 movi v7.8h, #0xc6
+ 331c: 4f0684e7 movi v7.8h, #0xc7
+ 3320: 4f068507 movi v7.8h, #0xc8
+ 3324: 4f068527 movi v7.8h, #0xc9
+ 3328: 4f068547 movi v7.8h, #0xca
+ 332c: 4f068567 movi v7.8h, #0xcb
+ 3330: 4f068587 movi v7.8h, #0xcc
+ 3334: 4f0685a7 movi v7.8h, #0xcd
+ 3338: 4f0685c7 movi v7.8h, #0xce
+ 333c: 4f0685e7 movi v7.8h, #0xcf
+ 3340: 4f068607 movi v7.8h, #0xd0
+ 3344: 4f068627 movi v7.8h, #0xd1
+ 3348: 4f068647 movi v7.8h, #0xd2
+ 334c: 4f068667 movi v7.8h, #0xd3
+ 3350: 4f068687 movi v7.8h, #0xd4
+ 3354: 4f0686a7 movi v7.8h, #0xd5
+ 3358: 4f0686c7 movi v7.8h, #0xd6
+ 335c: 4f0686e7 movi v7.8h, #0xd7
+ 3360: 4f068707 movi v7.8h, #0xd8
+ 3364: 4f068727 movi v7.8h, #0xd9
+ 3368: 4f068747 movi v7.8h, #0xda
+ 336c: 4f068767 movi v7.8h, #0xdb
+ 3370: 4f068787 movi v7.8h, #0xdc
+ 3374: 4f0687a7 movi v7.8h, #0xdd
+ 3378: 4f0687c7 movi v7.8h, #0xde
+ 337c: 4f0687e7 movi v7.8h, #0xdf
+ 3380: 4f078407 movi v7.8h, #0xe0
+ 3384: 4f078427 movi v7.8h, #0xe1
+ 3388: 4f078447 movi v7.8h, #0xe2
+ 338c: 4f078467 movi v7.8h, #0xe3
+ 3390: 4f078487 movi v7.8h, #0xe4
+ 3394: 4f0784a7 movi v7.8h, #0xe5
+ 3398: 4f0784c7 movi v7.8h, #0xe6
+ 339c: 4f0784e7 movi v7.8h, #0xe7
+ 33a0: 4f078507 movi v7.8h, #0xe8
+ 33a4: 4f078527 movi v7.8h, #0xe9
+ 33a8: 4f078547 movi v7.8h, #0xea
+ 33ac: 4f078567 movi v7.8h, #0xeb
+ 33b0: 4f078587 movi v7.8h, #0xec
+ 33b4: 4f0785a7 movi v7.8h, #0xed
+ 33b8: 4f0785c7 movi v7.8h, #0xee
+ 33bc: 4f0785e7 movi v7.8h, #0xef
+ 33c0: 4f078607 movi v7.8h, #0xf0
+ 33c4: 4f078627 movi v7.8h, #0xf1
+ 33c8: 4f078647 movi v7.8h, #0xf2
+ 33cc: 4f078667 movi v7.8h, #0xf3
+ 33d0: 4f078687 movi v7.8h, #0xf4
+ 33d4: 4f0786a7 movi v7.8h, #0xf5
+ 33d8: 4f0786c7 movi v7.8h, #0xf6
+ 33dc: 4f0786e7 movi v7.8h, #0xf7
+ 33e0: 4f078707 movi v7.8h, #0xf8
+ 33e4: 4f078727 movi v7.8h, #0xf9
+ 33e8: 4f078747 movi v7.8h, #0xfa
+ 33ec: 4f078767 movi v7.8h, #0xfb
+ 33f0: 4f078787 movi v7.8h, #0xfc
+ 33f4: 4f0787a7 movi v7.8h, #0xfd
+ 33f8: 4f0787c7 movi v7.8h, #0xfe
+ 33fc: 4f0787e7 movi v7.8h, #0xff
+ 3400: 4f00840f movi v15.8h, #0x0
+ 3404: 4f00842f movi v15.8h, #0x1
+ 3408: 4f00844f movi v15.8h, #0x2
+ 340c: 4f00846f movi v15.8h, #0x3
+ 3410: 4f00848f movi v15.8h, #0x4
+ 3414: 4f0084af movi v15.8h, #0x5
+ 3418: 4f0084cf movi v15.8h, #0x6
+ 341c: 4f0084ef movi v15.8h, #0x7
+ 3420: 4f00850f movi v15.8h, #0x8
+ 3424: 4f00852f movi v15.8h, #0x9
+ 3428: 4f00854f movi v15.8h, #0xa
+ 342c: 4f00856f movi v15.8h, #0xb
+ 3430: 4f00858f movi v15.8h, #0xc
+ 3434: 4f0085af movi v15.8h, #0xd
+ 3438: 4f0085cf movi v15.8h, #0xe
+ 343c: 4f0085ef movi v15.8h, #0xf
+ 3440: 4f00860f movi v15.8h, #0x10
+ 3444: 4f00862f movi v15.8h, #0x11
+ 3448: 4f00864f movi v15.8h, #0x12
+ 344c: 4f00866f movi v15.8h, #0x13
+ 3450: 4f00868f movi v15.8h, #0x14
+ 3454: 4f0086af movi v15.8h, #0x15
+ 3458: 4f0086cf movi v15.8h, #0x16
+ 345c: 4f0086ef movi v15.8h, #0x17
+ 3460: 4f00870f movi v15.8h, #0x18
+ 3464: 4f00872f movi v15.8h, #0x19
+ 3468: 4f00874f movi v15.8h, #0x1a
+ 346c: 4f00876f movi v15.8h, #0x1b
+ 3470: 4f00878f movi v15.8h, #0x1c
+ 3474: 4f0087af movi v15.8h, #0x1d
+ 3478: 4f0087cf movi v15.8h, #0x1e
+ 347c: 4f0087ef movi v15.8h, #0x1f
+ 3480: 4f01840f movi v15.8h, #0x20
+ 3484: 4f01842f movi v15.8h, #0x21
+ 3488: 4f01844f movi v15.8h, #0x22
+ 348c: 4f01846f movi v15.8h, #0x23
+ 3490: 4f01848f movi v15.8h, #0x24
+ 3494: 4f0184af movi v15.8h, #0x25
+ 3498: 4f0184cf movi v15.8h, #0x26
+ 349c: 4f0184ef movi v15.8h, #0x27
+ 34a0: 4f01850f movi v15.8h, #0x28
+ 34a4: 4f01852f movi v15.8h, #0x29
+ 34a8: 4f01854f movi v15.8h, #0x2a
+ 34ac: 4f01856f movi v15.8h, #0x2b
+ 34b0: 4f01858f movi v15.8h, #0x2c
+ 34b4: 4f0185af movi v15.8h, #0x2d
+ 34b8: 4f0185cf movi v15.8h, #0x2e
+ 34bc: 4f0185ef movi v15.8h, #0x2f
+ 34c0: 4f01860f movi v15.8h, #0x30
+ 34c4: 4f01862f movi v15.8h, #0x31
+ 34c8: 4f01864f movi v15.8h, #0x32
+ 34cc: 4f01866f movi v15.8h, #0x33
+ 34d0: 4f01868f movi v15.8h, #0x34
+ 34d4: 4f0186af movi v15.8h, #0x35
+ 34d8: 4f0186cf movi v15.8h, #0x36
+ 34dc: 4f0186ef movi v15.8h, #0x37
+ 34e0: 4f01870f movi v15.8h, #0x38
+ 34e4: 4f01872f movi v15.8h, #0x39
+ 34e8: 4f01874f movi v15.8h, #0x3a
+ 34ec: 4f01876f movi v15.8h, #0x3b
+ 34f0: 4f01878f movi v15.8h, #0x3c
+ 34f4: 4f0187af movi v15.8h, #0x3d
+ 34f8: 4f0187cf movi v15.8h, #0x3e
+ 34fc: 4f0187ef movi v15.8h, #0x3f
+ 3500: 4f02840f movi v15.8h, #0x40
+ 3504: 4f02842f movi v15.8h, #0x41
+ 3508: 4f02844f movi v15.8h, #0x42
+ 350c: 4f02846f movi v15.8h, #0x43
+ 3510: 4f02848f movi v15.8h, #0x44
+ 3514: 4f0284af movi v15.8h, #0x45
+ 3518: 4f0284cf movi v15.8h, #0x46
+ 351c: 4f0284ef movi v15.8h, #0x47
+ 3520: 4f02850f movi v15.8h, #0x48
+ 3524: 4f02852f movi v15.8h, #0x49
+ 3528: 4f02854f movi v15.8h, #0x4a
+ 352c: 4f02856f movi v15.8h, #0x4b
+ 3530: 4f02858f movi v15.8h, #0x4c
+ 3534: 4f0285af movi v15.8h, #0x4d
+ 3538: 4f0285cf movi v15.8h, #0x4e
+ 353c: 4f0285ef movi v15.8h, #0x4f
+ 3540: 4f02860f movi v15.8h, #0x50
+ 3544: 4f02862f movi v15.8h, #0x51
+ 3548: 4f02864f movi v15.8h, #0x52
+ 354c: 4f02866f movi v15.8h, #0x53
+ 3550: 4f02868f movi v15.8h, #0x54
+ 3554: 4f0286af movi v15.8h, #0x55
+ 3558: 4f0286cf movi v15.8h, #0x56
+ 355c: 4f0286ef movi v15.8h, #0x57
+ 3560: 4f02870f movi v15.8h, #0x58
+ 3564: 4f02872f movi v15.8h, #0x59
+ 3568: 4f02874f movi v15.8h, #0x5a
+ 356c: 4f02876f movi v15.8h, #0x5b
+ 3570: 4f02878f movi v15.8h, #0x5c
+ 3574: 4f0287af movi v15.8h, #0x5d
+ 3578: 4f0287cf movi v15.8h, #0x5e
+ 357c: 4f0287ef movi v15.8h, #0x5f
+ 3580: 4f03840f movi v15.8h, #0x60
+ 3584: 4f03842f movi v15.8h, #0x61
+ 3588: 4f03844f movi v15.8h, #0x62
+ 358c: 4f03846f movi v15.8h, #0x63
+ 3590: 4f03848f movi v15.8h, #0x64
+ 3594: 4f0384af movi v15.8h, #0x65
+ 3598: 4f0384cf movi v15.8h, #0x66
+ 359c: 4f0384ef movi v15.8h, #0x67
+ 35a0: 4f03850f movi v15.8h, #0x68
+ 35a4: 4f03852f movi v15.8h, #0x69
+ 35a8: 4f03854f movi v15.8h, #0x6a
+ 35ac: 4f03856f movi v15.8h, #0x6b
+ 35b0: 4f03858f movi v15.8h, #0x6c
+ 35b4: 4f0385af movi v15.8h, #0x6d
+ 35b8: 4f0385cf movi v15.8h, #0x6e
+ 35bc: 4f0385ef movi v15.8h, #0x6f
+ 35c0: 4f03860f movi v15.8h, #0x70
+ 35c4: 4f03862f movi v15.8h, #0x71
+ 35c8: 4f03864f movi v15.8h, #0x72
+ 35cc: 4f03866f movi v15.8h, #0x73
+ 35d0: 4f03868f movi v15.8h, #0x74
+ 35d4: 4f0386af movi v15.8h, #0x75
+ 35d8: 4f0386cf movi v15.8h, #0x76
+ 35dc: 4f0386ef movi v15.8h, #0x77
+ 35e0: 4f03870f movi v15.8h, #0x78
+ 35e4: 4f03872f movi v15.8h, #0x79
+ 35e8: 4f03874f movi v15.8h, #0x7a
+ 35ec: 4f03876f movi v15.8h, #0x7b
+ 35f0: 4f03878f movi v15.8h, #0x7c
+ 35f4: 4f0387af movi v15.8h, #0x7d
+ 35f8: 4f0387cf movi v15.8h, #0x7e
+ 35fc: 4f0387ef movi v15.8h, #0x7f
+ 3600: 4f04840f movi v15.8h, #0x80
+ 3604: 4f04842f movi v15.8h, #0x81
+ 3608: 4f04844f movi v15.8h, #0x82
+ 360c: 4f04846f movi v15.8h, #0x83
+ 3610: 4f04848f movi v15.8h, #0x84
+ 3614: 4f0484af movi v15.8h, #0x85
+ 3618: 4f0484cf movi v15.8h, #0x86
+ 361c: 4f0484ef movi v15.8h, #0x87
+ 3620: 4f04850f movi v15.8h, #0x88
+ 3624: 4f04852f movi v15.8h, #0x89
+ 3628: 4f04854f movi v15.8h, #0x8a
+ 362c: 4f04856f movi v15.8h, #0x8b
+ 3630: 4f04858f movi v15.8h, #0x8c
+ 3634: 4f0485af movi v15.8h, #0x8d
+ 3638: 4f0485cf movi v15.8h, #0x8e
+ 363c: 4f0485ef movi v15.8h, #0x8f
+ 3640: 4f04860f movi v15.8h, #0x90
+ 3644: 4f04862f movi v15.8h, #0x91
+ 3648: 4f04864f movi v15.8h, #0x92
+ 364c: 4f04866f movi v15.8h, #0x93
+ 3650: 4f04868f movi v15.8h, #0x94
+ 3654: 4f0486af movi v15.8h, #0x95
+ 3658: 4f0486cf movi v15.8h, #0x96
+ 365c: 4f0486ef movi v15.8h, #0x97
+ 3660: 4f04870f movi v15.8h, #0x98
+ 3664: 4f04872f movi v15.8h, #0x99
+ 3668: 4f04874f movi v15.8h, #0x9a
+ 366c: 4f04876f movi v15.8h, #0x9b
+ 3670: 4f04878f movi v15.8h, #0x9c
+ 3674: 4f0487af movi v15.8h, #0x9d
+ 3678: 4f0487cf movi v15.8h, #0x9e
+ 367c: 4f0487ef movi v15.8h, #0x9f
+ 3680: 4f05840f movi v15.8h, #0xa0
+ 3684: 4f05842f movi v15.8h, #0xa1
+ 3688: 4f05844f movi v15.8h, #0xa2
+ 368c: 4f05846f movi v15.8h, #0xa3
+ 3690: 4f05848f movi v15.8h, #0xa4
+ 3694: 4f0584af movi v15.8h, #0xa5
+ 3698: 4f0584cf movi v15.8h, #0xa6
+ 369c: 4f0584ef movi v15.8h, #0xa7
+ 36a0: 4f05850f movi v15.8h, #0xa8
+ 36a4: 4f05852f movi v15.8h, #0xa9
+ 36a8: 4f05854f movi v15.8h, #0xaa
+ 36ac: 4f05856f movi v15.8h, #0xab
+ 36b0: 4f05858f movi v15.8h, #0xac
+ 36b4: 4f0585af movi v15.8h, #0xad
+ 36b8: 4f0585cf movi v15.8h, #0xae
+ 36bc: 4f0585ef movi v15.8h, #0xaf
+ 36c0: 4f05860f movi v15.8h, #0xb0
+ 36c4: 4f05862f movi v15.8h, #0xb1
+ 36c8: 4f05864f movi v15.8h, #0xb2
+ 36cc: 4f05866f movi v15.8h, #0xb3
+ 36d0: 4f05868f movi v15.8h, #0xb4
+ 36d4: 4f0586af movi v15.8h, #0xb5
+ 36d8: 4f0586cf movi v15.8h, #0xb6
+ 36dc: 4f0586ef movi v15.8h, #0xb7
+ 36e0: 4f05870f movi v15.8h, #0xb8
+ 36e4: 4f05872f movi v15.8h, #0xb9
+ 36e8: 4f05874f movi v15.8h, #0xba
+ 36ec: 4f05876f movi v15.8h, #0xbb
+ 36f0: 4f05878f movi v15.8h, #0xbc
+ 36f4: 4f0587af movi v15.8h, #0xbd
+ 36f8: 4f0587cf movi v15.8h, #0xbe
+ 36fc: 4f0587ef movi v15.8h, #0xbf
+ 3700: 4f06840f movi v15.8h, #0xc0
+ 3704: 4f06842f movi v15.8h, #0xc1
+ 3708: 4f06844f movi v15.8h, #0xc2
+ 370c: 4f06846f movi v15.8h, #0xc3
+ 3710: 4f06848f movi v15.8h, #0xc4
+ 3714: 4f0684af movi v15.8h, #0xc5
+ 3718: 4f0684cf movi v15.8h, #0xc6
+ 371c: 4f0684ef movi v15.8h, #0xc7
+ 3720: 4f06850f movi v15.8h, #0xc8
+ 3724: 4f06852f movi v15.8h, #0xc9
+ 3728: 4f06854f movi v15.8h, #0xca
+ 372c: 4f06856f movi v15.8h, #0xcb
+ 3730: 4f06858f movi v15.8h, #0xcc
+ 3734: 4f0685af movi v15.8h, #0xcd
+ 3738: 4f0685cf movi v15.8h, #0xce
+ 373c: 4f0685ef movi v15.8h, #0xcf
+ 3740: 4f06860f movi v15.8h, #0xd0
+ 3744: 4f06862f movi v15.8h, #0xd1
+ 3748: 4f06864f movi v15.8h, #0xd2
+ 374c: 4f06866f movi v15.8h, #0xd3
+ 3750: 4f06868f movi v15.8h, #0xd4
+ 3754: 4f0686af movi v15.8h, #0xd5
+ 3758: 4f0686cf movi v15.8h, #0xd6
+ 375c: 4f0686ef movi v15.8h, #0xd7
+ 3760: 4f06870f movi v15.8h, #0xd8
+ 3764: 4f06872f movi v15.8h, #0xd9
+ 3768: 4f06874f movi v15.8h, #0xda
+ 376c: 4f06876f movi v15.8h, #0xdb
+ 3770: 4f06878f movi v15.8h, #0xdc
+ 3774: 4f0687af movi v15.8h, #0xdd
+ 3778: 4f0687cf movi v15.8h, #0xde
+ 377c: 4f0687ef movi v15.8h, #0xdf
+ 3780: 4f07840f movi v15.8h, #0xe0
+ 3784: 4f07842f movi v15.8h, #0xe1
+ 3788: 4f07844f movi v15.8h, #0xe2
+ 378c: 4f07846f movi v15.8h, #0xe3
+ 3790: 4f07848f movi v15.8h, #0xe4
+ 3794: 4f0784af movi v15.8h, #0xe5
+ 3798: 4f0784cf movi v15.8h, #0xe6
+ 379c: 4f0784ef movi v15.8h, #0xe7
+ 37a0: 4f07850f movi v15.8h, #0xe8
+ 37a4: 4f07852f movi v15.8h, #0xe9
+ 37a8: 4f07854f movi v15.8h, #0xea
+ 37ac: 4f07856f movi v15.8h, #0xeb
+ 37b0: 4f07858f movi v15.8h, #0xec
+ 37b4: 4f0785af movi v15.8h, #0xed
+ 37b8: 4f0785cf movi v15.8h, #0xee
+ 37bc: 4f0785ef movi v15.8h, #0xef
+ 37c0: 4f07860f movi v15.8h, #0xf0
+ 37c4: 4f07862f movi v15.8h, #0xf1
+ 37c8: 4f07864f movi v15.8h, #0xf2
+ 37cc: 4f07866f movi v15.8h, #0xf3
+ 37d0: 4f07868f movi v15.8h, #0xf4
+ 37d4: 4f0786af movi v15.8h, #0xf5
+ 37d8: 4f0786cf movi v15.8h, #0xf6
+ 37dc: 4f0786ef movi v15.8h, #0xf7
+ 37e0: 4f07870f movi v15.8h, #0xf8
+ 37e4: 4f07872f movi v15.8h, #0xf9
+ 37e8: 4f07874f movi v15.8h, #0xfa
+ 37ec: 4f07876f movi v15.8h, #0xfb
+ 37f0: 4f07878f movi v15.8h, #0xfc
+ 37f4: 4f0787af movi v15.8h, #0xfd
+ 37f8: 4f0787cf movi v15.8h, #0xfe
+ 37fc: 4f0787ef movi v15.8h, #0xff
+ 3800: 4f00a407 movi v7.8h, #0x0, lsl #8
+ 3804: 4f00a427 movi v7.8h, #0x1, lsl #8
+ 3808: 4f00a447 movi v7.8h, #0x2, lsl #8
+ 380c: 4f00a467 movi v7.8h, #0x3, lsl #8
+ 3810: 4f00a487 movi v7.8h, #0x4, lsl #8
+ 3814: 4f00a4a7 movi v7.8h, #0x5, lsl #8
+ 3818: 4f00a4c7 movi v7.8h, #0x6, lsl #8
+ 381c: 4f00a4e7 movi v7.8h, #0x7, lsl #8
+ 3820: 4f00a507 movi v7.8h, #0x8, lsl #8
+ 3824: 4f00a527 movi v7.8h, #0x9, lsl #8
+ 3828: 4f00a547 movi v7.8h, #0xa, lsl #8
+ 382c: 4f00a567 movi v7.8h, #0xb, lsl #8
+ 3830: 4f00a587 movi v7.8h, #0xc, lsl #8
+ 3834: 4f00a5a7 movi v7.8h, #0xd, lsl #8
+ 3838: 4f00a5c7 movi v7.8h, #0xe, lsl #8
+ 383c: 4f00a5e7 movi v7.8h, #0xf, lsl #8
+ 3840: 4f00a607 movi v7.8h, #0x10, lsl #8
+ 3844: 4f00a627 movi v7.8h, #0x11, lsl #8
+ 3848: 4f00a647 movi v7.8h, #0x12, lsl #8
+ 384c: 4f00a667 movi v7.8h, #0x13, lsl #8
+ 3850: 4f00a687 movi v7.8h, #0x14, lsl #8
+ 3854: 4f00a6a7 movi v7.8h, #0x15, lsl #8
+ 3858: 4f00a6c7 movi v7.8h, #0x16, lsl #8
+ 385c: 4f00a6e7 movi v7.8h, #0x17, lsl #8
+ 3860: 4f00a707 movi v7.8h, #0x18, lsl #8
+ 3864: 4f00a727 movi v7.8h, #0x19, lsl #8
+ 3868: 4f00a747 movi v7.8h, #0x1a, lsl #8
+ 386c: 4f00a767 movi v7.8h, #0x1b, lsl #8
+ 3870: 4f00a787 movi v7.8h, #0x1c, lsl #8
+ 3874: 4f00a7a7 movi v7.8h, #0x1d, lsl #8
+ 3878: 4f00a7c7 movi v7.8h, #0x1e, lsl #8
+ 387c: 4f00a7e7 movi v7.8h, #0x1f, lsl #8
+ 3880: 4f01a407 movi v7.8h, #0x20, lsl #8
+ 3884: 4f01a427 movi v7.8h, #0x21, lsl #8
+ 3888: 4f01a447 movi v7.8h, #0x22, lsl #8
+ 388c: 4f01a467 movi v7.8h, #0x23, lsl #8
+ 3890: 4f01a487 movi v7.8h, #0x24, lsl #8
+ 3894: 4f01a4a7 movi v7.8h, #0x25, lsl #8
+ 3898: 4f01a4c7 movi v7.8h, #0x26, lsl #8
+ 389c: 4f01a4e7 movi v7.8h, #0x27, lsl #8
+ 38a0: 4f01a507 movi v7.8h, #0x28, lsl #8
+ 38a4: 4f01a527 movi v7.8h, #0x29, lsl #8
+ 38a8: 4f01a547 movi v7.8h, #0x2a, lsl #8
+ 38ac: 4f01a567 movi v7.8h, #0x2b, lsl #8
+ 38b0: 4f01a587 movi v7.8h, #0x2c, lsl #8
+ 38b4: 4f01a5a7 movi v7.8h, #0x2d, lsl #8
+ 38b8: 4f01a5c7 movi v7.8h, #0x2e, lsl #8
+ 38bc: 4f01a5e7 movi v7.8h, #0x2f, lsl #8
+ 38c0: 4f01a607 movi v7.8h, #0x30, lsl #8
+ 38c4: 4f01a627 movi v7.8h, #0x31, lsl #8
+ 38c8: 4f01a647 movi v7.8h, #0x32, lsl #8
+ 38cc: 4f01a667 movi v7.8h, #0x33, lsl #8
+ 38d0: 4f01a687 movi v7.8h, #0x34, lsl #8
+ 38d4: 4f01a6a7 movi v7.8h, #0x35, lsl #8
+ 38d8: 4f01a6c7 movi v7.8h, #0x36, lsl #8
+ 38dc: 4f01a6e7 movi v7.8h, #0x37, lsl #8
+ 38e0: 4f01a707 movi v7.8h, #0x38, lsl #8
+ 38e4: 4f01a727 movi v7.8h, #0x39, lsl #8
+ 38e8: 4f01a747 movi v7.8h, #0x3a, lsl #8
+ 38ec: 4f01a767 movi v7.8h, #0x3b, lsl #8
+ 38f0: 4f01a787 movi v7.8h, #0x3c, lsl #8
+ 38f4: 4f01a7a7 movi v7.8h, #0x3d, lsl #8
+ 38f8: 4f01a7c7 movi v7.8h, #0x3e, lsl #8
+ 38fc: 4f01a7e7 movi v7.8h, #0x3f, lsl #8
+ 3900: 4f02a407 movi v7.8h, #0x40, lsl #8
+ 3904: 4f02a427 movi v7.8h, #0x41, lsl #8
+ 3908: 4f02a447 movi v7.8h, #0x42, lsl #8
+ 390c: 4f02a467 movi v7.8h, #0x43, lsl #8
+ 3910: 4f02a487 movi v7.8h, #0x44, lsl #8
+ 3914: 4f02a4a7 movi v7.8h, #0x45, lsl #8
+ 3918: 4f02a4c7 movi v7.8h, #0x46, lsl #8
+ 391c: 4f02a4e7 movi v7.8h, #0x47, lsl #8
+ 3920: 4f02a507 movi v7.8h, #0x48, lsl #8
+ 3924: 4f02a527 movi v7.8h, #0x49, lsl #8
+ 3928: 4f02a547 movi v7.8h, #0x4a, lsl #8
+ 392c: 4f02a567 movi v7.8h, #0x4b, lsl #8
+ 3930: 4f02a587 movi v7.8h, #0x4c, lsl #8
+ 3934: 4f02a5a7 movi v7.8h, #0x4d, lsl #8
+ 3938: 4f02a5c7 movi v7.8h, #0x4e, lsl #8
+ 393c: 4f02a5e7 movi v7.8h, #0x4f, lsl #8
+ 3940: 4f02a607 movi v7.8h, #0x50, lsl #8
+ 3944: 4f02a627 movi v7.8h, #0x51, lsl #8
+ 3948: 4f02a647 movi v7.8h, #0x52, lsl #8
+ 394c: 4f02a667 movi v7.8h, #0x53, lsl #8
+ 3950: 4f02a687 movi v7.8h, #0x54, lsl #8
+ 3954: 4f02a6a7 movi v7.8h, #0x55, lsl #8
+ 3958: 4f02a6c7 movi v7.8h, #0x56, lsl #8
+ 395c: 4f02a6e7 movi v7.8h, #0x57, lsl #8
+ 3960: 4f02a707 movi v7.8h, #0x58, lsl #8
+ 3964: 4f02a727 movi v7.8h, #0x59, lsl #8
+ 3968: 4f02a747 movi v7.8h, #0x5a, lsl #8
+ 396c: 4f02a767 movi v7.8h, #0x5b, lsl #8
+ 3970: 4f02a787 movi v7.8h, #0x5c, lsl #8
+ 3974: 4f02a7a7 movi v7.8h, #0x5d, lsl #8
+ 3978: 4f02a7c7 movi v7.8h, #0x5e, lsl #8
+ 397c: 4f02a7e7 movi v7.8h, #0x5f, lsl #8
+ 3980: 4f03a407 movi v7.8h, #0x60, lsl #8
+ 3984: 4f03a427 movi v7.8h, #0x61, lsl #8
+ 3988: 4f03a447 movi v7.8h, #0x62, lsl #8
+ 398c: 4f03a467 movi v7.8h, #0x63, lsl #8
+ 3990: 4f03a487 movi v7.8h, #0x64, lsl #8
+ 3994: 4f03a4a7 movi v7.8h, #0x65, lsl #8
+ 3998: 4f03a4c7 movi v7.8h, #0x66, lsl #8
+ 399c: 4f03a4e7 movi v7.8h, #0x67, lsl #8
+ 39a0: 4f03a507 movi v7.8h, #0x68, lsl #8
+ 39a4: 4f03a527 movi v7.8h, #0x69, lsl #8
+ 39a8: 4f03a547 movi v7.8h, #0x6a, lsl #8
+ 39ac: 4f03a567 movi v7.8h, #0x6b, lsl #8
+ 39b0: 4f03a587 movi v7.8h, #0x6c, lsl #8
+ 39b4: 4f03a5a7 movi v7.8h, #0x6d, lsl #8
+ 39b8: 4f03a5c7 movi v7.8h, #0x6e, lsl #8
+ 39bc: 4f03a5e7 movi v7.8h, #0x6f, lsl #8
+ 39c0: 4f03a607 movi v7.8h, #0x70, lsl #8
+ 39c4: 4f03a627 movi v7.8h, #0x71, lsl #8
+ 39c8: 4f03a647 movi v7.8h, #0x72, lsl #8
+ 39cc: 4f03a667 movi v7.8h, #0x73, lsl #8
+ 39d0: 4f03a687 movi v7.8h, #0x74, lsl #8
+ 39d4: 4f03a6a7 movi v7.8h, #0x75, lsl #8
+ 39d8: 4f03a6c7 movi v7.8h, #0x76, lsl #8
+ 39dc: 4f03a6e7 movi v7.8h, #0x77, lsl #8
+ 39e0: 4f03a707 movi v7.8h, #0x78, lsl #8
+ 39e4: 4f03a727 movi v7.8h, #0x79, lsl #8
+ 39e8: 4f03a747 movi v7.8h, #0x7a, lsl #8
+ 39ec: 4f03a767 movi v7.8h, #0x7b, lsl #8
+ 39f0: 4f03a787 movi v7.8h, #0x7c, lsl #8
+ 39f4: 4f03a7a7 movi v7.8h, #0x7d, lsl #8
+ 39f8: 4f03a7c7 movi v7.8h, #0x7e, lsl #8
+ 39fc: 4f03a7e7 movi v7.8h, #0x7f, lsl #8
+ 3a00: 4f04a407 movi v7.8h, #0x80, lsl #8
+ 3a04: 4f04a427 movi v7.8h, #0x81, lsl #8
+ 3a08: 4f04a447 movi v7.8h, #0x82, lsl #8
+ 3a0c: 4f04a467 movi v7.8h, #0x83, lsl #8
+ 3a10: 4f04a487 movi v7.8h, #0x84, lsl #8
+ 3a14: 4f04a4a7 movi v7.8h, #0x85, lsl #8
+ 3a18: 4f04a4c7 movi v7.8h, #0x86, lsl #8
+ 3a1c: 4f04a4e7 movi v7.8h, #0x87, lsl #8
+ 3a20: 4f04a507 movi v7.8h, #0x88, lsl #8
+ 3a24: 4f04a527 movi v7.8h, #0x89, lsl #8
+ 3a28: 4f04a547 movi v7.8h, #0x8a, lsl #8
+ 3a2c: 4f04a567 movi v7.8h, #0x8b, lsl #8
+ 3a30: 4f04a587 movi v7.8h, #0x8c, lsl #8
+ 3a34: 4f04a5a7 movi v7.8h, #0x8d, lsl #8
+ 3a38: 4f04a5c7 movi v7.8h, #0x8e, lsl #8
+ 3a3c: 4f04a5e7 movi v7.8h, #0x8f, lsl #8
+ 3a40: 4f04a607 movi v7.8h, #0x90, lsl #8
+ 3a44: 4f04a627 movi v7.8h, #0x91, lsl #8
+ 3a48: 4f04a647 movi v7.8h, #0x92, lsl #8
+ 3a4c: 4f04a667 movi v7.8h, #0x93, lsl #8
+ 3a50: 4f04a687 movi v7.8h, #0x94, lsl #8
+ 3a54: 4f04a6a7 movi v7.8h, #0x95, lsl #8
+ 3a58: 4f04a6c7 movi v7.8h, #0x96, lsl #8
+ 3a5c: 4f04a6e7 movi v7.8h, #0x97, lsl #8
+ 3a60: 4f04a707 movi v7.8h, #0x98, lsl #8
+ 3a64: 4f04a727 movi v7.8h, #0x99, lsl #8
+ 3a68: 4f04a747 movi v7.8h, #0x9a, lsl #8
+ 3a6c: 4f04a767 movi v7.8h, #0x9b, lsl #8
+ 3a70: 4f04a787 movi v7.8h, #0x9c, lsl #8
+ 3a74: 4f04a7a7 movi v7.8h, #0x9d, lsl #8
+ 3a78: 4f04a7c7 movi v7.8h, #0x9e, lsl #8
+ 3a7c: 4f04a7e7 movi v7.8h, #0x9f, lsl #8
+ 3a80: 4f05a407 movi v7.8h, #0xa0, lsl #8
+ 3a84: 4f05a427 movi v7.8h, #0xa1, lsl #8
+ 3a88: 4f05a447 movi v7.8h, #0xa2, lsl #8
+ 3a8c: 4f05a467 movi v7.8h, #0xa3, lsl #8
+ 3a90: 4f05a487 movi v7.8h, #0xa4, lsl #8
+ 3a94: 4f05a4a7 movi v7.8h, #0xa5, lsl #8
+ 3a98: 4f05a4c7 movi v7.8h, #0xa6, lsl #8
+ 3a9c: 4f05a4e7 movi v7.8h, #0xa7, lsl #8
+ 3aa0: 4f05a507 movi v7.8h, #0xa8, lsl #8
+ 3aa4: 4f05a527 movi v7.8h, #0xa9, lsl #8
+ 3aa8: 4f05a547 movi v7.8h, #0xaa, lsl #8
+ 3aac: 4f05a567 movi v7.8h, #0xab, lsl #8
+ 3ab0: 4f05a587 movi v7.8h, #0xac, lsl #8
+ 3ab4: 4f05a5a7 movi v7.8h, #0xad, lsl #8
+ 3ab8: 4f05a5c7 movi v7.8h, #0xae, lsl #8
+ 3abc: 4f05a5e7 movi v7.8h, #0xaf, lsl #8
+ 3ac0: 4f05a607 movi v7.8h, #0xb0, lsl #8
+ 3ac4: 4f05a627 movi v7.8h, #0xb1, lsl #8
+ 3ac8: 4f05a647 movi v7.8h, #0xb2, lsl #8
+ 3acc: 4f05a667 movi v7.8h, #0xb3, lsl #8
+ 3ad0: 4f05a687 movi v7.8h, #0xb4, lsl #8
+ 3ad4: 4f05a6a7 movi v7.8h, #0xb5, lsl #8
+ 3ad8: 4f05a6c7 movi v7.8h, #0xb6, lsl #8
+ 3adc: 4f05a6e7 movi v7.8h, #0xb7, lsl #8
+ 3ae0: 4f05a707 movi v7.8h, #0xb8, lsl #8
+ 3ae4: 4f05a727 movi v7.8h, #0xb9, lsl #8
+ 3ae8: 4f05a747 movi v7.8h, #0xba, lsl #8
+ 3aec: 4f05a767 movi v7.8h, #0xbb, lsl #8
+ 3af0: 4f05a787 movi v7.8h, #0xbc, lsl #8
+ 3af4: 4f05a7a7 movi v7.8h, #0xbd, lsl #8
+ 3af8: 4f05a7c7 movi v7.8h, #0xbe, lsl #8
+ 3afc: 4f05a7e7 movi v7.8h, #0xbf, lsl #8
+ 3b00: 4f06a407 movi v7.8h, #0xc0, lsl #8
+ 3b04: 4f06a427 movi v7.8h, #0xc1, lsl #8
+ 3b08: 4f06a447 movi v7.8h, #0xc2, lsl #8
+ 3b0c: 4f06a467 movi v7.8h, #0xc3, lsl #8
+ 3b10: 4f06a487 movi v7.8h, #0xc4, lsl #8
+ 3b14: 4f06a4a7 movi v7.8h, #0xc5, lsl #8
+ 3b18: 4f06a4c7 movi v7.8h, #0xc6, lsl #8
+ 3b1c: 4f06a4e7 movi v7.8h, #0xc7, lsl #8
+ 3b20: 4f06a507 movi v7.8h, #0xc8, lsl #8
+ 3b24: 4f06a527 movi v7.8h, #0xc9, lsl #8
+ 3b28: 4f06a547 movi v7.8h, #0xca, lsl #8
+ 3b2c: 4f06a567 movi v7.8h, #0xcb, lsl #8
+ 3b30: 4f06a587 movi v7.8h, #0xcc, lsl #8
+ 3b34: 4f06a5a7 movi v7.8h, #0xcd, lsl #8
+ 3b38: 4f06a5c7 movi v7.8h, #0xce, lsl #8
+ 3b3c: 4f06a5e7 movi v7.8h, #0xcf, lsl #8
+ 3b40: 4f06a607 movi v7.8h, #0xd0, lsl #8
+ 3b44: 4f06a627 movi v7.8h, #0xd1, lsl #8
+ 3b48: 4f06a647 movi v7.8h, #0xd2, lsl #8
+ 3b4c: 4f06a667 movi v7.8h, #0xd3, lsl #8
+ 3b50: 4f06a687 movi v7.8h, #0xd4, lsl #8
+ 3b54: 4f06a6a7 movi v7.8h, #0xd5, lsl #8
+ 3b58: 4f06a6c7 movi v7.8h, #0xd6, lsl #8
+ 3b5c: 4f06a6e7 movi v7.8h, #0xd7, lsl #8
+ 3b60: 4f06a707 movi v7.8h, #0xd8, lsl #8
+ 3b64: 4f06a727 movi v7.8h, #0xd9, lsl #8
+ 3b68: 4f06a747 movi v7.8h, #0xda, lsl #8
+ 3b6c: 4f06a767 movi v7.8h, #0xdb, lsl #8
+ 3b70: 4f06a787 movi v7.8h, #0xdc, lsl #8
+ 3b74: 4f06a7a7 movi v7.8h, #0xdd, lsl #8
+ 3b78: 4f06a7c7 movi v7.8h, #0xde, lsl #8
+ 3b7c: 4f06a7e7 movi v7.8h, #0xdf, lsl #8
+ 3b80: 4f07a407 movi v7.8h, #0xe0, lsl #8
+ 3b84: 4f07a427 movi v7.8h, #0xe1, lsl #8
+ 3b88: 4f07a447 movi v7.8h, #0xe2, lsl #8
+ 3b8c: 4f07a467 movi v7.8h, #0xe3, lsl #8
+ 3b90: 4f07a487 movi v7.8h, #0xe4, lsl #8
+ 3b94: 4f07a4a7 movi v7.8h, #0xe5, lsl #8
+ 3b98: 4f07a4c7 movi v7.8h, #0xe6, lsl #8
+ 3b9c: 4f07a4e7 movi v7.8h, #0xe7, lsl #8
+ 3ba0: 4f07a507 movi v7.8h, #0xe8, lsl #8
+ 3ba4: 4f07a527 movi v7.8h, #0xe9, lsl #8
+ 3ba8: 4f07a547 movi v7.8h, #0xea, lsl #8
+ 3bac: 4f07a567 movi v7.8h, #0xeb, lsl #8
+ 3bb0: 4f07a587 movi v7.8h, #0xec, lsl #8
+ 3bb4: 4f07a5a7 movi v7.8h, #0xed, lsl #8
+ 3bb8: 4f07a5c7 movi v7.8h, #0xee, lsl #8
+ 3bbc: 4f07a5e7 movi v7.8h, #0xef, lsl #8
+ 3bc0: 4f07a607 movi v7.8h, #0xf0, lsl #8
+ 3bc4: 4f07a627 movi v7.8h, #0xf1, lsl #8
+ 3bc8: 4f07a647 movi v7.8h, #0xf2, lsl #8
+ 3bcc: 4f07a667 movi v7.8h, #0xf3, lsl #8
+ 3bd0: 4f07a687 movi v7.8h, #0xf4, lsl #8
+ 3bd4: 4f07a6a7 movi v7.8h, #0xf5, lsl #8
+ 3bd8: 4f07a6c7 movi v7.8h, #0xf6, lsl #8
+ 3bdc: 4f07a6e7 movi v7.8h, #0xf7, lsl #8
+ 3be0: 4f07a707 movi v7.8h, #0xf8, lsl #8
+ 3be4: 4f07a727 movi v7.8h, #0xf9, lsl #8
+ 3be8: 4f07a747 movi v7.8h, #0xfa, lsl #8
+ 3bec: 4f07a767 movi v7.8h, #0xfb, lsl #8
+ 3bf0: 4f07a787 movi v7.8h, #0xfc, lsl #8
+ 3bf4: 4f07a7a7 movi v7.8h, #0xfd, lsl #8
+ 3bf8: 4f07a7c7 movi v7.8h, #0xfe, lsl #8
+ 3bfc: 4f07a7e7 movi v7.8h, #0xff, lsl #8
+ 3c00: 4f00840f movi v15.8h, #0x0
+ 3c04: 4f00842f movi v15.8h, #0x1
+ 3c08: 4f00844f movi v15.8h, #0x2
+ 3c0c: 4f00846f movi v15.8h, #0x3
+ 3c10: 4f00848f movi v15.8h, #0x4
+ 3c14: 4f0084af movi v15.8h, #0x5
+ 3c18: 4f0084cf movi v15.8h, #0x6
+ 3c1c: 4f0084ef movi v15.8h, #0x7
+ 3c20: 4f00850f movi v15.8h, #0x8
+ 3c24: 4f00852f movi v15.8h, #0x9
+ 3c28: 4f00854f movi v15.8h, #0xa
+ 3c2c: 4f00856f movi v15.8h, #0xb
+ 3c30: 4f00858f movi v15.8h, #0xc
+ 3c34: 4f0085af movi v15.8h, #0xd
+ 3c38: 4f0085cf movi v15.8h, #0xe
+ 3c3c: 4f0085ef movi v15.8h, #0xf
+ 3c40: 4f00860f movi v15.8h, #0x10
+ 3c44: 4f00862f movi v15.8h, #0x11
+ 3c48: 4f00864f movi v15.8h, #0x12
+ 3c4c: 4f00866f movi v15.8h, #0x13
+ 3c50: 4f00868f movi v15.8h, #0x14
+ 3c54: 4f0086af movi v15.8h, #0x15
+ 3c58: 4f0086cf movi v15.8h, #0x16
+ 3c5c: 4f0086ef movi v15.8h, #0x17
+ 3c60: 4f00870f movi v15.8h, #0x18
+ 3c64: 4f00872f movi v15.8h, #0x19
+ 3c68: 4f00874f movi v15.8h, #0x1a
+ 3c6c: 4f00876f movi v15.8h, #0x1b
+ 3c70: 4f00878f movi v15.8h, #0x1c
+ 3c74: 4f0087af movi v15.8h, #0x1d
+ 3c78: 4f0087cf movi v15.8h, #0x1e
+ 3c7c: 4f0087ef movi v15.8h, #0x1f
+ 3c80: 4f01840f movi v15.8h, #0x20
+ 3c84: 4f01842f movi v15.8h, #0x21
+ 3c88: 4f01844f movi v15.8h, #0x22
+ 3c8c: 4f01846f movi v15.8h, #0x23
+ 3c90: 4f01848f movi v15.8h, #0x24
+ 3c94: 4f0184af movi v15.8h, #0x25
+ 3c98: 4f0184cf movi v15.8h, #0x26
+ 3c9c: 4f0184ef movi v15.8h, #0x27
+ 3ca0: 4f01850f movi v15.8h, #0x28
+ 3ca4: 4f01852f movi v15.8h, #0x29
+ 3ca8: 4f01854f movi v15.8h, #0x2a
+ 3cac: 4f01856f movi v15.8h, #0x2b
+ 3cb0: 4f01858f movi v15.8h, #0x2c
+ 3cb4: 4f0185af movi v15.8h, #0x2d
+ 3cb8: 4f0185cf movi v15.8h, #0x2e
+ 3cbc: 4f0185ef movi v15.8h, #0x2f
+ 3cc0: 4f01860f movi v15.8h, #0x30
+ 3cc4: 4f01862f movi v15.8h, #0x31
+ 3cc8: 4f01864f movi v15.8h, #0x32
+ 3ccc: 4f01866f movi v15.8h, #0x33
+ 3cd0: 4f01868f movi v15.8h, #0x34
+ 3cd4: 4f0186af movi v15.8h, #0x35
+ 3cd8: 4f0186cf movi v15.8h, #0x36
+ 3cdc: 4f0186ef movi v15.8h, #0x37
+ 3ce0: 4f01870f movi v15.8h, #0x38
+ 3ce4: 4f01872f movi v15.8h, #0x39
+ 3ce8: 4f01874f movi v15.8h, #0x3a
+ 3cec: 4f01876f movi v15.8h, #0x3b
+ 3cf0: 4f01878f movi v15.8h, #0x3c
+ 3cf4: 4f0187af movi v15.8h, #0x3d
+ 3cf8: 4f0187cf movi v15.8h, #0x3e
+ 3cfc: 4f0187ef movi v15.8h, #0x3f
+ 3d00: 4f02840f movi v15.8h, #0x40
+ 3d04: 4f02842f movi v15.8h, #0x41
+ 3d08: 4f02844f movi v15.8h, #0x42
+ 3d0c: 4f02846f movi v15.8h, #0x43
+ 3d10: 4f02848f movi v15.8h, #0x44
+ 3d14: 4f0284af movi v15.8h, #0x45
+ 3d18: 4f0284cf movi v15.8h, #0x46
+ 3d1c: 4f0284ef movi v15.8h, #0x47
+ 3d20: 4f02850f movi v15.8h, #0x48
+ 3d24: 4f02852f movi v15.8h, #0x49
+ 3d28: 4f02854f movi v15.8h, #0x4a
+ 3d2c: 4f02856f movi v15.8h, #0x4b
+ 3d30: 4f02858f movi v15.8h, #0x4c
+ 3d34: 4f0285af movi v15.8h, #0x4d
+ 3d38: 4f0285cf movi v15.8h, #0x4e
+ 3d3c: 4f0285ef movi v15.8h, #0x4f
+ 3d40: 4f02860f movi v15.8h, #0x50
+ 3d44: 4f02862f movi v15.8h, #0x51
+ 3d48: 4f02864f movi v15.8h, #0x52
+ 3d4c: 4f02866f movi v15.8h, #0x53
+ 3d50: 4f02868f movi v15.8h, #0x54
+ 3d54: 4f0286af movi v15.8h, #0x55
+ 3d58: 4f0286cf movi v15.8h, #0x56
+ 3d5c: 4f0286ef movi v15.8h, #0x57
+ 3d60: 4f02870f movi v15.8h, #0x58
+ 3d64: 4f02872f movi v15.8h, #0x59
+ 3d68: 4f02874f movi v15.8h, #0x5a
+ 3d6c: 4f02876f movi v15.8h, #0x5b
+ 3d70: 4f02878f movi v15.8h, #0x5c
+ 3d74: 4f0287af movi v15.8h, #0x5d
+ 3d78: 4f0287cf movi v15.8h, #0x5e
+ 3d7c: 4f0287ef movi v15.8h, #0x5f
+ 3d80: 4f03840f movi v15.8h, #0x60
+ 3d84: 4f03842f movi v15.8h, #0x61
+ 3d88: 4f03844f movi v15.8h, #0x62
+ 3d8c: 4f03846f movi v15.8h, #0x63
+ 3d90: 4f03848f movi v15.8h, #0x64
+ 3d94: 4f0384af movi v15.8h, #0x65
+ 3d98: 4f0384cf movi v15.8h, #0x66
+ 3d9c: 4f0384ef movi v15.8h, #0x67
+ 3da0: 4f03850f movi v15.8h, #0x68
+ 3da4: 4f03852f movi v15.8h, #0x69
+ 3da8: 4f03854f movi v15.8h, #0x6a
+ 3dac: 4f03856f movi v15.8h, #0x6b
+ 3db0: 4f03858f movi v15.8h, #0x6c
+ 3db4: 4f0385af movi v15.8h, #0x6d
+ 3db8: 4f0385cf movi v15.8h, #0x6e
+ 3dbc: 4f0385ef movi v15.8h, #0x6f
+ 3dc0: 4f03860f movi v15.8h, #0x70
+ 3dc4: 4f03862f movi v15.8h, #0x71
+ 3dc8: 4f03864f movi v15.8h, #0x72
+ 3dcc: 4f03866f movi v15.8h, #0x73
+ 3dd0: 4f03868f movi v15.8h, #0x74
+ 3dd4: 4f0386af movi v15.8h, #0x75
+ 3dd8: 4f0386cf movi v15.8h, #0x76
+ 3ddc: 4f0386ef movi v15.8h, #0x77
+ 3de0: 4f03870f movi v15.8h, #0x78
+ 3de4: 4f03872f movi v15.8h, #0x79
+ 3de8: 4f03874f movi v15.8h, #0x7a
+ 3dec: 4f03876f movi v15.8h, #0x7b
+ 3df0: 4f03878f movi v15.8h, #0x7c
+ 3df4: 4f0387af movi v15.8h, #0x7d
+ 3df8: 4f0387cf movi v15.8h, #0x7e
+ 3dfc: 4f0387ef movi v15.8h, #0x7f
+ 3e00: 4f04840f movi v15.8h, #0x80
+ 3e04: 4f04842f movi v15.8h, #0x81
+ 3e08: 4f04844f movi v15.8h, #0x82
+ 3e0c: 4f04846f movi v15.8h, #0x83
+ 3e10: 4f04848f movi v15.8h, #0x84
+ 3e14: 4f0484af movi v15.8h, #0x85
+ 3e18: 4f0484cf movi v15.8h, #0x86
+ 3e1c: 4f0484ef movi v15.8h, #0x87
+ 3e20: 4f04850f movi v15.8h, #0x88
+ 3e24: 4f04852f movi v15.8h, #0x89
+ 3e28: 4f04854f movi v15.8h, #0x8a
+ 3e2c: 4f04856f movi v15.8h, #0x8b
+ 3e30: 4f04858f movi v15.8h, #0x8c
+ 3e34: 4f0485af movi v15.8h, #0x8d
+ 3e38: 4f0485cf movi v15.8h, #0x8e
+ 3e3c: 4f0485ef movi v15.8h, #0x8f
+ 3e40: 4f04860f movi v15.8h, #0x90
+ 3e44: 4f04862f movi v15.8h, #0x91
+ 3e48: 4f04864f movi v15.8h, #0x92
+ 3e4c: 4f04866f movi v15.8h, #0x93
+ 3e50: 4f04868f movi v15.8h, #0x94
+ 3e54: 4f0486af movi v15.8h, #0x95
+ 3e58: 4f0486cf movi v15.8h, #0x96
+ 3e5c: 4f0486ef movi v15.8h, #0x97
+ 3e60: 4f04870f movi v15.8h, #0x98
+ 3e64: 4f04872f movi v15.8h, #0x99
+ 3e68: 4f04874f movi v15.8h, #0x9a
+ 3e6c: 4f04876f movi v15.8h, #0x9b
+ 3e70: 4f04878f movi v15.8h, #0x9c
+ 3e74: 4f0487af movi v15.8h, #0x9d
+ 3e78: 4f0487cf movi v15.8h, #0x9e
+ 3e7c: 4f0487ef movi v15.8h, #0x9f
+ 3e80: 4f05840f movi v15.8h, #0xa0
+ 3e84: 4f05842f movi v15.8h, #0xa1
+ 3e88: 4f05844f movi v15.8h, #0xa2
+ 3e8c: 4f05846f movi v15.8h, #0xa3
+ 3e90: 4f05848f movi v15.8h, #0xa4
+ 3e94: 4f0584af movi v15.8h, #0xa5
+ 3e98: 4f0584cf movi v15.8h, #0xa6
+ 3e9c: 4f0584ef movi v15.8h, #0xa7
+ 3ea0: 4f05850f movi v15.8h, #0xa8
+ 3ea4: 4f05852f movi v15.8h, #0xa9
+ 3ea8: 4f05854f movi v15.8h, #0xaa
+ 3eac: 4f05856f movi v15.8h, #0xab
+ 3eb0: 4f05858f movi v15.8h, #0xac
+ 3eb4: 4f0585af movi v15.8h, #0xad
+ 3eb8: 4f0585cf movi v15.8h, #0xae
+ 3ebc: 4f0585ef movi v15.8h, #0xaf
+ 3ec0: 4f05860f movi v15.8h, #0xb0
+ 3ec4: 4f05862f movi v15.8h, #0xb1
+ 3ec8: 4f05864f movi v15.8h, #0xb2
+ 3ecc: 4f05866f movi v15.8h, #0xb3
+ 3ed0: 4f05868f movi v15.8h, #0xb4
+ 3ed4: 4f0586af movi v15.8h, #0xb5
+ 3ed8: 4f0586cf movi v15.8h, #0xb6
+ 3edc: 4f0586ef movi v15.8h, #0xb7
+ 3ee0: 4f05870f movi v15.8h, #0xb8
+ 3ee4: 4f05872f movi v15.8h, #0xb9
+ 3ee8: 4f05874f movi v15.8h, #0xba
+ 3eec: 4f05876f movi v15.8h, #0xbb
+ 3ef0: 4f05878f movi v15.8h, #0xbc
+ 3ef4: 4f0587af movi v15.8h, #0xbd
+ 3ef8: 4f0587cf movi v15.8h, #0xbe
+ 3efc: 4f0587ef movi v15.8h, #0xbf
+ 3f00: 4f06840f movi v15.8h, #0xc0
+ 3f04: 4f06842f movi v15.8h, #0xc1
+ 3f08: 4f06844f movi v15.8h, #0xc2
+ 3f0c: 4f06846f movi v15.8h, #0xc3
+ 3f10: 4f06848f movi v15.8h, #0xc4
+ 3f14: 4f0684af movi v15.8h, #0xc5
+ 3f18: 4f0684cf movi v15.8h, #0xc6
+ 3f1c: 4f0684ef movi v15.8h, #0xc7
+ 3f20: 4f06850f movi v15.8h, #0xc8
+ 3f24: 4f06852f movi v15.8h, #0xc9
+ 3f28: 4f06854f movi v15.8h, #0xca
+ 3f2c: 4f06856f movi v15.8h, #0xcb
+ 3f30: 4f06858f movi v15.8h, #0xcc
+ 3f34: 4f0685af movi v15.8h, #0xcd
+ 3f38: 4f0685cf movi v15.8h, #0xce
+ 3f3c: 4f0685ef movi v15.8h, #0xcf
+ 3f40: 4f06860f movi v15.8h, #0xd0
+ 3f44: 4f06862f movi v15.8h, #0xd1
+ 3f48: 4f06864f movi v15.8h, #0xd2
+ 3f4c: 4f06866f movi v15.8h, #0xd3
+ 3f50: 4f06868f movi v15.8h, #0xd4
+ 3f54: 4f0686af movi v15.8h, #0xd5
+ 3f58: 4f0686cf movi v15.8h, #0xd6
+ 3f5c: 4f0686ef movi v15.8h, #0xd7
+ 3f60: 4f06870f movi v15.8h, #0xd8
+ 3f64: 4f06872f movi v15.8h, #0xd9
+ 3f68: 4f06874f movi v15.8h, #0xda
+ 3f6c: 4f06876f movi v15.8h, #0xdb
+ 3f70: 4f06878f movi v15.8h, #0xdc
+ 3f74: 4f0687af movi v15.8h, #0xdd
+ 3f78: 4f0687cf movi v15.8h, #0xde
+ 3f7c: 4f0687ef movi v15.8h, #0xdf
+ 3f80: 4f07840f movi v15.8h, #0xe0
+ 3f84: 4f07842f movi v15.8h, #0xe1
+ 3f88: 4f07844f movi v15.8h, #0xe2
+ 3f8c: 4f07846f movi v15.8h, #0xe3
+ 3f90: 4f07848f movi v15.8h, #0xe4
+ 3f94: 4f0784af movi v15.8h, #0xe5
+ 3f98: 4f0784cf movi v15.8h, #0xe6
+ 3f9c: 4f0784ef movi v15.8h, #0xe7
+ 3fa0: 4f07850f movi v15.8h, #0xe8
+ 3fa4: 4f07852f movi v15.8h, #0xe9
+ 3fa8: 4f07854f movi v15.8h, #0xea
+ 3fac: 4f07856f movi v15.8h, #0xeb
+ 3fb0: 4f07858f movi v15.8h, #0xec
+ 3fb4: 4f0785af movi v15.8h, #0xed
+ 3fb8: 4f0785cf movi v15.8h, #0xee
+ 3fbc: 4f0785ef movi v15.8h, #0xef
+ 3fc0: 4f07860f movi v15.8h, #0xf0
+ 3fc4: 4f07862f movi v15.8h, #0xf1
+ 3fc8: 4f07864f movi v15.8h, #0xf2
+ 3fcc: 4f07866f movi v15.8h, #0xf3
+ 3fd0: 4f07868f movi v15.8h, #0xf4
+ 3fd4: 4f0786af movi v15.8h, #0xf5
+ 3fd8: 4f0786cf movi v15.8h, #0xf6
+ 3fdc: 4f0786ef movi v15.8h, #0xf7
+ 3fe0: 4f07870f movi v15.8h, #0xf8
+ 3fe4: 4f07872f movi v15.8h, #0xf9
+ 3fe8: 4f07874f movi v15.8h, #0xfa
+ 3fec: 4f07876f movi v15.8h, #0xfb
+ 3ff0: 4f07878f movi v15.8h, #0xfc
+ 3ff4: 4f0787af movi v15.8h, #0xfd
+ 3ff8: 4f0787cf movi v15.8h, #0xfe
+ 3ffc: 4f0787ef movi v15.8h, #0xff
+ 4000: 0f000407 movi v7.2s, #0x0
+ 4004: 0f000427 movi v7.2s, #0x1
+ 4008: 0f000447 movi v7.2s, #0x2
+ 400c: 0f000467 movi v7.2s, #0x3
+ 4010: 0f000487 movi v7.2s, #0x4
+ 4014: 0f0004a7 movi v7.2s, #0x5
+ 4018: 0f0004c7 movi v7.2s, #0x6
+ 401c: 0f0004e7 movi v7.2s, #0x7
+ 4020: 0f000507 movi v7.2s, #0x8
+ 4024: 0f000527 movi v7.2s, #0x9
+ 4028: 0f000547 movi v7.2s, #0xa
+ 402c: 0f000567 movi v7.2s, #0xb
+ 4030: 0f000587 movi v7.2s, #0xc
+ 4034: 0f0005a7 movi v7.2s, #0xd
+ 4038: 0f0005c7 movi v7.2s, #0xe
+ 403c: 0f0005e7 movi v7.2s, #0xf
+ 4040: 0f000607 movi v7.2s, #0x10
+ 4044: 0f000627 movi v7.2s, #0x11
+ 4048: 0f000647 movi v7.2s, #0x12
+ 404c: 0f000667 movi v7.2s, #0x13
+ 4050: 0f000687 movi v7.2s, #0x14
+ 4054: 0f0006a7 movi v7.2s, #0x15
+ 4058: 0f0006c7 movi v7.2s, #0x16
+ 405c: 0f0006e7 movi v7.2s, #0x17
+ 4060: 0f000707 movi v7.2s, #0x18
+ 4064: 0f000727 movi v7.2s, #0x19
+ 4068: 0f000747 movi v7.2s, #0x1a
+ 406c: 0f000767 movi v7.2s, #0x1b
+ 4070: 0f000787 movi v7.2s, #0x1c
+ 4074: 0f0007a7 movi v7.2s, #0x1d
+ 4078: 0f0007c7 movi v7.2s, #0x1e
+ 407c: 0f0007e7 movi v7.2s, #0x1f
+ 4080: 0f010407 movi v7.2s, #0x20
+ 4084: 0f010427 movi v7.2s, #0x21
+ 4088: 0f010447 movi v7.2s, #0x22
+ 408c: 0f010467 movi v7.2s, #0x23
+ 4090: 0f010487 movi v7.2s, #0x24
+ 4094: 0f0104a7 movi v7.2s, #0x25
+ 4098: 0f0104c7 movi v7.2s, #0x26
+ 409c: 0f0104e7 movi v7.2s, #0x27
+ 40a0: 0f010507 movi v7.2s, #0x28
+ 40a4: 0f010527 movi v7.2s, #0x29
+ 40a8: 0f010547 movi v7.2s, #0x2a
+ 40ac: 0f010567 movi v7.2s, #0x2b
+ 40b0: 0f010587 movi v7.2s, #0x2c
+ 40b4: 0f0105a7 movi v7.2s, #0x2d
+ 40b8: 0f0105c7 movi v7.2s, #0x2e
+ 40bc: 0f0105e7 movi v7.2s, #0x2f
+ 40c0: 0f010607 movi v7.2s, #0x30
+ 40c4: 0f010627 movi v7.2s, #0x31
+ 40c8: 0f010647 movi v7.2s, #0x32
+ 40cc: 0f010667 movi v7.2s, #0x33
+ 40d0: 0f010687 movi v7.2s, #0x34
+ 40d4: 0f0106a7 movi v7.2s, #0x35
+ 40d8: 0f0106c7 movi v7.2s, #0x36
+ 40dc: 0f0106e7 movi v7.2s, #0x37
+ 40e0: 0f010707 movi v7.2s, #0x38
+ 40e4: 0f010727 movi v7.2s, #0x39
+ 40e8: 0f010747 movi v7.2s, #0x3a
+ 40ec: 0f010767 movi v7.2s, #0x3b
+ 40f0: 0f010787 movi v7.2s, #0x3c
+ 40f4: 0f0107a7 movi v7.2s, #0x3d
+ 40f8: 0f0107c7 movi v7.2s, #0x3e
+ 40fc: 0f0107e7 movi v7.2s, #0x3f
+ 4100: 0f020407 movi v7.2s, #0x40
+ 4104: 0f020427 movi v7.2s, #0x41
+ 4108: 0f020447 movi v7.2s, #0x42
+ 410c: 0f020467 movi v7.2s, #0x43
+ 4110: 0f020487 movi v7.2s, #0x44
+ 4114: 0f0204a7 movi v7.2s, #0x45
+ 4118: 0f0204c7 movi v7.2s, #0x46
+ 411c: 0f0204e7 movi v7.2s, #0x47
+ 4120: 0f020507 movi v7.2s, #0x48
+ 4124: 0f020527 movi v7.2s, #0x49
+ 4128: 0f020547 movi v7.2s, #0x4a
+ 412c: 0f020567 movi v7.2s, #0x4b
+ 4130: 0f020587 movi v7.2s, #0x4c
+ 4134: 0f0205a7 movi v7.2s, #0x4d
+ 4138: 0f0205c7 movi v7.2s, #0x4e
+ 413c: 0f0205e7 movi v7.2s, #0x4f
+ 4140: 0f020607 movi v7.2s, #0x50
+ 4144: 0f020627 movi v7.2s, #0x51
+ 4148: 0f020647 movi v7.2s, #0x52
+ 414c: 0f020667 movi v7.2s, #0x53
+ 4150: 0f020687 movi v7.2s, #0x54
+ 4154: 0f0206a7 movi v7.2s, #0x55
+ 4158: 0f0206c7 movi v7.2s, #0x56
+ 415c: 0f0206e7 movi v7.2s, #0x57
+ 4160: 0f020707 movi v7.2s, #0x58
+ 4164: 0f020727 movi v7.2s, #0x59
+ 4168: 0f020747 movi v7.2s, #0x5a
+ 416c: 0f020767 movi v7.2s, #0x5b
+ 4170: 0f020787 movi v7.2s, #0x5c
+ 4174: 0f0207a7 movi v7.2s, #0x5d
+ 4178: 0f0207c7 movi v7.2s, #0x5e
+ 417c: 0f0207e7 movi v7.2s, #0x5f
+ 4180: 0f030407 movi v7.2s, #0x60
+ 4184: 0f030427 movi v7.2s, #0x61
+ 4188: 0f030447 movi v7.2s, #0x62
+ 418c: 0f030467 movi v7.2s, #0x63
+ 4190: 0f030487 movi v7.2s, #0x64
+ 4194: 0f0304a7 movi v7.2s, #0x65
+ 4198: 0f0304c7 movi v7.2s, #0x66
+ 419c: 0f0304e7 movi v7.2s, #0x67
+ 41a0: 0f030507 movi v7.2s, #0x68
+ 41a4: 0f030527 movi v7.2s, #0x69
+ 41a8: 0f030547 movi v7.2s, #0x6a
+ 41ac: 0f030567 movi v7.2s, #0x6b
+ 41b0: 0f030587 movi v7.2s, #0x6c
+ 41b4: 0f0305a7 movi v7.2s, #0x6d
+ 41b8: 0f0305c7 movi v7.2s, #0x6e
+ 41bc: 0f0305e7 movi v7.2s, #0x6f
+ 41c0: 0f030607 movi v7.2s, #0x70
+ 41c4: 0f030627 movi v7.2s, #0x71
+ 41c8: 0f030647 movi v7.2s, #0x72
+ 41cc: 0f030667 movi v7.2s, #0x73
+ 41d0: 0f030687 movi v7.2s, #0x74
+ 41d4: 0f0306a7 movi v7.2s, #0x75
+ 41d8: 0f0306c7 movi v7.2s, #0x76
+ 41dc: 0f0306e7 movi v7.2s, #0x77
+ 41e0: 0f030707 movi v7.2s, #0x78
+ 41e4: 0f030727 movi v7.2s, #0x79
+ 41e8: 0f030747 movi v7.2s, #0x7a
+ 41ec: 0f030767 movi v7.2s, #0x7b
+ 41f0: 0f030787 movi v7.2s, #0x7c
+ 41f4: 0f0307a7 movi v7.2s, #0x7d
+ 41f8: 0f0307c7 movi v7.2s, #0x7e
+ 41fc: 0f0307e7 movi v7.2s, #0x7f
+ 4200: 0f040407 movi v7.2s, #0x80
+ 4204: 0f040427 movi v7.2s, #0x81
+ 4208: 0f040447 movi v7.2s, #0x82
+ 420c: 0f040467 movi v7.2s, #0x83
+ 4210: 0f040487 movi v7.2s, #0x84
+ 4214: 0f0404a7 movi v7.2s, #0x85
+ 4218: 0f0404c7 movi v7.2s, #0x86
+ 421c: 0f0404e7 movi v7.2s, #0x87
+ 4220: 0f040507 movi v7.2s, #0x88
+ 4224: 0f040527 movi v7.2s, #0x89
+ 4228: 0f040547 movi v7.2s, #0x8a
+ 422c: 0f040567 movi v7.2s, #0x8b
+ 4230: 0f040587 movi v7.2s, #0x8c
+ 4234: 0f0405a7 movi v7.2s, #0x8d
+ 4238: 0f0405c7 movi v7.2s, #0x8e
+ 423c: 0f0405e7 movi v7.2s, #0x8f
+ 4240: 0f040607 movi v7.2s, #0x90
+ 4244: 0f040627 movi v7.2s, #0x91
+ 4248: 0f040647 movi v7.2s, #0x92
+ 424c: 0f040667 movi v7.2s, #0x93
+ 4250: 0f040687 movi v7.2s, #0x94
+ 4254: 0f0406a7 movi v7.2s, #0x95
+ 4258: 0f0406c7 movi v7.2s, #0x96
+ 425c: 0f0406e7 movi v7.2s, #0x97
+ 4260: 0f040707 movi v7.2s, #0x98
+ 4264: 0f040727 movi v7.2s, #0x99
+ 4268: 0f040747 movi v7.2s, #0x9a
+ 426c: 0f040767 movi v7.2s, #0x9b
+ 4270: 0f040787 movi v7.2s, #0x9c
+ 4274: 0f0407a7 movi v7.2s, #0x9d
+ 4278: 0f0407c7 movi v7.2s, #0x9e
+ 427c: 0f0407e7 movi v7.2s, #0x9f
+ 4280: 0f050407 movi v7.2s, #0xa0
+ 4284: 0f050427 movi v7.2s, #0xa1
+ 4288: 0f050447 movi v7.2s, #0xa2
+ 428c: 0f050467 movi v7.2s, #0xa3
+ 4290: 0f050487 movi v7.2s, #0xa4
+ 4294: 0f0504a7 movi v7.2s, #0xa5
+ 4298: 0f0504c7 movi v7.2s, #0xa6
+ 429c: 0f0504e7 movi v7.2s, #0xa7
+ 42a0: 0f050507 movi v7.2s, #0xa8
+ 42a4: 0f050527 movi v7.2s, #0xa9
+ 42a8: 0f050547 movi v7.2s, #0xaa
+ 42ac: 0f050567 movi v7.2s, #0xab
+ 42b0: 0f050587 movi v7.2s, #0xac
+ 42b4: 0f0505a7 movi v7.2s, #0xad
+ 42b8: 0f0505c7 movi v7.2s, #0xae
+ 42bc: 0f0505e7 movi v7.2s, #0xaf
+ 42c0: 0f050607 movi v7.2s, #0xb0
+ 42c4: 0f050627 movi v7.2s, #0xb1
+ 42c8: 0f050647 movi v7.2s, #0xb2
+ 42cc: 0f050667 movi v7.2s, #0xb3
+ 42d0: 0f050687 movi v7.2s, #0xb4
+ 42d4: 0f0506a7 movi v7.2s, #0xb5
+ 42d8: 0f0506c7 movi v7.2s, #0xb6
+ 42dc: 0f0506e7 movi v7.2s, #0xb7
+ 42e0: 0f050707 movi v7.2s, #0xb8
+ 42e4: 0f050727 movi v7.2s, #0xb9
+ 42e8: 0f050747 movi v7.2s, #0xba
+ 42ec: 0f050767 movi v7.2s, #0xbb
+ 42f0: 0f050787 movi v7.2s, #0xbc
+ 42f4: 0f0507a7 movi v7.2s, #0xbd
+ 42f8: 0f0507c7 movi v7.2s, #0xbe
+ 42fc: 0f0507e7 movi v7.2s, #0xbf
+ 4300: 0f060407 movi v7.2s, #0xc0
+ 4304: 0f060427 movi v7.2s, #0xc1
+ 4308: 0f060447 movi v7.2s, #0xc2
+ 430c: 0f060467 movi v7.2s, #0xc3
+ 4310: 0f060487 movi v7.2s, #0xc4
+ 4314: 0f0604a7 movi v7.2s, #0xc5
+ 4318: 0f0604c7 movi v7.2s, #0xc6
+ 431c: 0f0604e7 movi v7.2s, #0xc7
+ 4320: 0f060507 movi v7.2s, #0xc8
+ 4324: 0f060527 movi v7.2s, #0xc9
+ 4328: 0f060547 movi v7.2s, #0xca
+ 432c: 0f060567 movi v7.2s, #0xcb
+ 4330: 0f060587 movi v7.2s, #0xcc
+ 4334: 0f0605a7 movi v7.2s, #0xcd
+ 4338: 0f0605c7 movi v7.2s, #0xce
+ 433c: 0f0605e7 movi v7.2s, #0xcf
+ 4340: 0f060607 movi v7.2s, #0xd0
+ 4344: 0f060627 movi v7.2s, #0xd1
+ 4348: 0f060647 movi v7.2s, #0xd2
+ 434c: 0f060667 movi v7.2s, #0xd3
+ 4350: 0f060687 movi v7.2s, #0xd4
+ 4354: 0f0606a7 movi v7.2s, #0xd5
+ 4358: 0f0606c7 movi v7.2s, #0xd6
+ 435c: 0f0606e7 movi v7.2s, #0xd7
+ 4360: 0f060707 movi v7.2s, #0xd8
+ 4364: 0f060727 movi v7.2s, #0xd9
+ 4368: 0f060747 movi v7.2s, #0xda
+ 436c: 0f060767 movi v7.2s, #0xdb
+ 4370: 0f060787 movi v7.2s, #0xdc
+ 4374: 0f0607a7 movi v7.2s, #0xdd
+ 4378: 0f0607c7 movi v7.2s, #0xde
+ 437c: 0f0607e7 movi v7.2s, #0xdf
+ 4380: 0f070407 movi v7.2s, #0xe0
+ 4384: 0f070427 movi v7.2s, #0xe1
+ 4388: 0f070447 movi v7.2s, #0xe2
+ 438c: 0f070467 movi v7.2s, #0xe3
+ 4390: 0f070487 movi v7.2s, #0xe4
+ 4394: 0f0704a7 movi v7.2s, #0xe5
+ 4398: 0f0704c7 movi v7.2s, #0xe6
+ 439c: 0f0704e7 movi v7.2s, #0xe7
+ 43a0: 0f070507 movi v7.2s, #0xe8
+ 43a4: 0f070527 movi v7.2s, #0xe9
+ 43a8: 0f070547 movi v7.2s, #0xea
+ 43ac: 0f070567 movi v7.2s, #0xeb
+ 43b0: 0f070587 movi v7.2s, #0xec
+ 43b4: 0f0705a7 movi v7.2s, #0xed
+ 43b8: 0f0705c7 movi v7.2s, #0xee
+ 43bc: 0f0705e7 movi v7.2s, #0xef
+ 43c0: 0f070607 movi v7.2s, #0xf0
+ 43c4: 0f070627 movi v7.2s, #0xf1
+ 43c8: 0f070647 movi v7.2s, #0xf2
+ 43cc: 0f070667 movi v7.2s, #0xf3
+ 43d0: 0f070687 movi v7.2s, #0xf4
+ 43d4: 0f0706a7 movi v7.2s, #0xf5
+ 43d8: 0f0706c7 movi v7.2s, #0xf6
+ 43dc: 0f0706e7 movi v7.2s, #0xf7
+ 43e0: 0f070707 movi v7.2s, #0xf8
+ 43e4: 0f070727 movi v7.2s, #0xf9
+ 43e8: 0f070747 movi v7.2s, #0xfa
+ 43ec: 0f070767 movi v7.2s, #0xfb
+ 43f0: 0f070787 movi v7.2s, #0xfc
+ 43f4: 0f0707a7 movi v7.2s, #0xfd
+ 43f8: 0f0707c7 movi v7.2s, #0xfe
+ 43fc: 0f0707e7 movi v7.2s, #0xff
+ 4400: 0f00040f movi v15.2s, #0x0
+ 4404: 0f00042f movi v15.2s, #0x1
+ 4408: 0f00044f movi v15.2s, #0x2
+ 440c: 0f00046f movi v15.2s, #0x3
+ 4410: 0f00048f movi v15.2s, #0x4
+ 4414: 0f0004af movi v15.2s, #0x5
+ 4418: 0f0004cf movi v15.2s, #0x6
+ 441c: 0f0004ef movi v15.2s, #0x7
+ 4420: 0f00050f movi v15.2s, #0x8
+ 4424: 0f00052f movi v15.2s, #0x9
+ 4428: 0f00054f movi v15.2s, #0xa
+ 442c: 0f00056f movi v15.2s, #0xb
+ 4430: 0f00058f movi v15.2s, #0xc
+ 4434: 0f0005af movi v15.2s, #0xd
+ 4438: 0f0005cf movi v15.2s, #0xe
+ 443c: 0f0005ef movi v15.2s, #0xf
+ 4440: 0f00060f movi v15.2s, #0x10
+ 4444: 0f00062f movi v15.2s, #0x11
+ 4448: 0f00064f movi v15.2s, #0x12
+ 444c: 0f00066f movi v15.2s, #0x13
+ 4450: 0f00068f movi v15.2s, #0x14
+ 4454: 0f0006af movi v15.2s, #0x15
+ 4458: 0f0006cf movi v15.2s, #0x16
+ 445c: 0f0006ef movi v15.2s, #0x17
+ 4460: 0f00070f movi v15.2s, #0x18
+ 4464: 0f00072f movi v15.2s, #0x19
+ 4468: 0f00074f movi v15.2s, #0x1a
+ 446c: 0f00076f movi v15.2s, #0x1b
+ 4470: 0f00078f movi v15.2s, #0x1c
+ 4474: 0f0007af movi v15.2s, #0x1d
+ 4478: 0f0007cf movi v15.2s, #0x1e
+ 447c: 0f0007ef movi v15.2s, #0x1f
+ 4480: 0f01040f movi v15.2s, #0x20
+ 4484: 0f01042f movi v15.2s, #0x21
+ 4488: 0f01044f movi v15.2s, #0x22
+ 448c: 0f01046f movi v15.2s, #0x23
+ 4490: 0f01048f movi v15.2s, #0x24
+ 4494: 0f0104af movi v15.2s, #0x25
+ 4498: 0f0104cf movi v15.2s, #0x26
+ 449c: 0f0104ef movi v15.2s, #0x27
+ 44a0: 0f01050f movi v15.2s, #0x28
+ 44a4: 0f01052f movi v15.2s, #0x29
+ 44a8: 0f01054f movi v15.2s, #0x2a
+ 44ac: 0f01056f movi v15.2s, #0x2b
+ 44b0: 0f01058f movi v15.2s, #0x2c
+ 44b4: 0f0105af movi v15.2s, #0x2d
+ 44b8: 0f0105cf movi v15.2s, #0x2e
+ 44bc: 0f0105ef movi v15.2s, #0x2f
+ 44c0: 0f01060f movi v15.2s, #0x30
+ 44c4: 0f01062f movi v15.2s, #0x31
+ 44c8: 0f01064f movi v15.2s, #0x32
+ 44cc: 0f01066f movi v15.2s, #0x33
+ 44d0: 0f01068f movi v15.2s, #0x34
+ 44d4: 0f0106af movi v15.2s, #0x35
+ 44d8: 0f0106cf movi v15.2s, #0x36
+ 44dc: 0f0106ef movi v15.2s, #0x37
+ 44e0: 0f01070f movi v15.2s, #0x38
+ 44e4: 0f01072f movi v15.2s, #0x39
+ 44e8: 0f01074f movi v15.2s, #0x3a
+ 44ec: 0f01076f movi v15.2s, #0x3b
+ 44f0: 0f01078f movi v15.2s, #0x3c
+ 44f4: 0f0107af movi v15.2s, #0x3d
+ 44f8: 0f0107cf movi v15.2s, #0x3e
+ 44fc: 0f0107ef movi v15.2s, #0x3f
+ 4500: 0f02040f movi v15.2s, #0x40
+ 4504: 0f02042f movi v15.2s, #0x41
+ 4508: 0f02044f movi v15.2s, #0x42
+ 450c: 0f02046f movi v15.2s, #0x43
+ 4510: 0f02048f movi v15.2s, #0x44
+ 4514: 0f0204af movi v15.2s, #0x45
+ 4518: 0f0204cf movi v15.2s, #0x46
+ 451c: 0f0204ef movi v15.2s, #0x47
+ 4520: 0f02050f movi v15.2s, #0x48
+ 4524: 0f02052f movi v15.2s, #0x49
+ 4528: 0f02054f movi v15.2s, #0x4a
+ 452c: 0f02056f movi v15.2s, #0x4b
+ 4530: 0f02058f movi v15.2s, #0x4c
+ 4534: 0f0205af movi v15.2s, #0x4d
+ 4538: 0f0205cf movi v15.2s, #0x4e
+ 453c: 0f0205ef movi v15.2s, #0x4f
+ 4540: 0f02060f movi v15.2s, #0x50
+ 4544: 0f02062f movi v15.2s, #0x51
+ 4548: 0f02064f movi v15.2s, #0x52
+ 454c: 0f02066f movi v15.2s, #0x53
+ 4550: 0f02068f movi v15.2s, #0x54
+ 4554: 0f0206af movi v15.2s, #0x55
+ 4558: 0f0206cf movi v15.2s, #0x56
+ 455c: 0f0206ef movi v15.2s, #0x57
+ 4560: 0f02070f movi v15.2s, #0x58
+ 4564: 0f02072f movi v15.2s, #0x59
+ 4568: 0f02074f movi v15.2s, #0x5a
+ 456c: 0f02076f movi v15.2s, #0x5b
+ 4570: 0f02078f movi v15.2s, #0x5c
+ 4574: 0f0207af movi v15.2s, #0x5d
+ 4578: 0f0207cf movi v15.2s, #0x5e
+ 457c: 0f0207ef movi v15.2s, #0x5f
+ 4580: 0f03040f movi v15.2s, #0x60
+ 4584: 0f03042f movi v15.2s, #0x61
+ 4588: 0f03044f movi v15.2s, #0x62
+ 458c: 0f03046f movi v15.2s, #0x63
+ 4590: 0f03048f movi v15.2s, #0x64
+ 4594: 0f0304af movi v15.2s, #0x65
+ 4598: 0f0304cf movi v15.2s, #0x66
+ 459c: 0f0304ef movi v15.2s, #0x67
+ 45a0: 0f03050f movi v15.2s, #0x68
+ 45a4: 0f03052f movi v15.2s, #0x69
+ 45a8: 0f03054f movi v15.2s, #0x6a
+ 45ac: 0f03056f movi v15.2s, #0x6b
+ 45b0: 0f03058f movi v15.2s, #0x6c
+ 45b4: 0f0305af movi v15.2s, #0x6d
+ 45b8: 0f0305cf movi v15.2s, #0x6e
+ 45bc: 0f0305ef movi v15.2s, #0x6f
+ 45c0: 0f03060f movi v15.2s, #0x70
+ 45c4: 0f03062f movi v15.2s, #0x71
+ 45c8: 0f03064f movi v15.2s, #0x72
+ 45cc: 0f03066f movi v15.2s, #0x73
+ 45d0: 0f03068f movi v15.2s, #0x74
+ 45d4: 0f0306af movi v15.2s, #0x75
+ 45d8: 0f0306cf movi v15.2s, #0x76
+ 45dc: 0f0306ef movi v15.2s, #0x77
+ 45e0: 0f03070f movi v15.2s, #0x78
+ 45e4: 0f03072f movi v15.2s, #0x79
+ 45e8: 0f03074f movi v15.2s, #0x7a
+ 45ec: 0f03076f movi v15.2s, #0x7b
+ 45f0: 0f03078f movi v15.2s, #0x7c
+ 45f4: 0f0307af movi v15.2s, #0x7d
+ 45f8: 0f0307cf movi v15.2s, #0x7e
+ 45fc: 0f0307ef movi v15.2s, #0x7f
+ 4600: 0f04040f movi v15.2s, #0x80
+ 4604: 0f04042f movi v15.2s, #0x81
+ 4608: 0f04044f movi v15.2s, #0x82
+ 460c: 0f04046f movi v15.2s, #0x83
+ 4610: 0f04048f movi v15.2s, #0x84
+ 4614: 0f0404af movi v15.2s, #0x85
+ 4618: 0f0404cf movi v15.2s, #0x86
+ 461c: 0f0404ef movi v15.2s, #0x87
+ 4620: 0f04050f movi v15.2s, #0x88
+ 4624: 0f04052f movi v15.2s, #0x89
+ 4628: 0f04054f movi v15.2s, #0x8a
+ 462c: 0f04056f movi v15.2s, #0x8b
+ 4630: 0f04058f movi v15.2s, #0x8c
+ 4634: 0f0405af movi v15.2s, #0x8d
+ 4638: 0f0405cf movi v15.2s, #0x8e
+ 463c: 0f0405ef movi v15.2s, #0x8f
+ 4640: 0f04060f movi v15.2s, #0x90
+ 4644: 0f04062f movi v15.2s, #0x91
+ 4648: 0f04064f movi v15.2s, #0x92
+ 464c: 0f04066f movi v15.2s, #0x93
+ 4650: 0f04068f movi v15.2s, #0x94
+ 4654: 0f0406af movi v15.2s, #0x95
+ 4658: 0f0406cf movi v15.2s, #0x96
+ 465c: 0f0406ef movi v15.2s, #0x97
+ 4660: 0f04070f movi v15.2s, #0x98
+ 4664: 0f04072f movi v15.2s, #0x99
+ 4668: 0f04074f movi v15.2s, #0x9a
+ 466c: 0f04076f movi v15.2s, #0x9b
+ 4670: 0f04078f movi v15.2s, #0x9c
+ 4674: 0f0407af movi v15.2s, #0x9d
+ 4678: 0f0407cf movi v15.2s, #0x9e
+ 467c: 0f0407ef movi v15.2s, #0x9f
+ 4680: 0f05040f movi v15.2s, #0xa0
+ 4684: 0f05042f movi v15.2s, #0xa1
+ 4688: 0f05044f movi v15.2s, #0xa2
+ 468c: 0f05046f movi v15.2s, #0xa3
+ 4690: 0f05048f movi v15.2s, #0xa4
+ 4694: 0f0504af movi v15.2s, #0xa5
+ 4698: 0f0504cf movi v15.2s, #0xa6
+ 469c: 0f0504ef movi v15.2s, #0xa7
+ 46a0: 0f05050f movi v15.2s, #0xa8
+ 46a4: 0f05052f movi v15.2s, #0xa9
+ 46a8: 0f05054f movi v15.2s, #0xaa
+ 46ac: 0f05056f movi v15.2s, #0xab
+ 46b0: 0f05058f movi v15.2s, #0xac
+ 46b4: 0f0505af movi v15.2s, #0xad
+ 46b8: 0f0505cf movi v15.2s, #0xae
+ 46bc: 0f0505ef movi v15.2s, #0xaf
+ 46c0: 0f05060f movi v15.2s, #0xb0
+ 46c4: 0f05062f movi v15.2s, #0xb1
+ 46c8: 0f05064f movi v15.2s, #0xb2
+ 46cc: 0f05066f movi v15.2s, #0xb3
+ 46d0: 0f05068f movi v15.2s, #0xb4
+ 46d4: 0f0506af movi v15.2s, #0xb5
+ 46d8: 0f0506cf movi v15.2s, #0xb6
+ 46dc: 0f0506ef movi v15.2s, #0xb7
+ 46e0: 0f05070f movi v15.2s, #0xb8
+ 46e4: 0f05072f movi v15.2s, #0xb9
+ 46e8: 0f05074f movi v15.2s, #0xba
+ 46ec: 0f05076f movi v15.2s, #0xbb
+ 46f0: 0f05078f movi v15.2s, #0xbc
+ 46f4: 0f0507af movi v15.2s, #0xbd
+ 46f8: 0f0507cf movi v15.2s, #0xbe
+ 46fc: 0f0507ef movi v15.2s, #0xbf
+ 4700: 0f06040f movi v15.2s, #0xc0
+ 4704: 0f06042f movi v15.2s, #0xc1
+ 4708: 0f06044f movi v15.2s, #0xc2
+ 470c: 0f06046f movi v15.2s, #0xc3
+ 4710: 0f06048f movi v15.2s, #0xc4
+ 4714: 0f0604af movi v15.2s, #0xc5
+ 4718: 0f0604cf movi v15.2s, #0xc6
+ 471c: 0f0604ef movi v15.2s, #0xc7
+ 4720: 0f06050f movi v15.2s, #0xc8
+ 4724: 0f06052f movi v15.2s, #0xc9
+ 4728: 0f06054f movi v15.2s, #0xca
+ 472c: 0f06056f movi v15.2s, #0xcb
+ 4730: 0f06058f movi v15.2s, #0xcc
+ 4734: 0f0605af movi v15.2s, #0xcd
+ 4738: 0f0605cf movi v15.2s, #0xce
+ 473c: 0f0605ef movi v15.2s, #0xcf
+ 4740: 0f06060f movi v15.2s, #0xd0
+ 4744: 0f06062f movi v15.2s, #0xd1
+ 4748: 0f06064f movi v15.2s, #0xd2
+ 474c: 0f06066f movi v15.2s, #0xd3
+ 4750: 0f06068f movi v15.2s, #0xd4
+ 4754: 0f0606af movi v15.2s, #0xd5
+ 4758: 0f0606cf movi v15.2s, #0xd6
+ 475c: 0f0606ef movi v15.2s, #0xd7
+ 4760: 0f06070f movi v15.2s, #0xd8
+ 4764: 0f06072f movi v15.2s, #0xd9
+ 4768: 0f06074f movi v15.2s, #0xda
+ 476c: 0f06076f movi v15.2s, #0xdb
+ 4770: 0f06078f movi v15.2s, #0xdc
+ 4774: 0f0607af movi v15.2s, #0xdd
+ 4778: 0f0607cf movi v15.2s, #0xde
+ 477c: 0f0607ef movi v15.2s, #0xdf
+ 4780: 0f07040f movi v15.2s, #0xe0
+ 4784: 0f07042f movi v15.2s, #0xe1
+ 4788: 0f07044f movi v15.2s, #0xe2
+ 478c: 0f07046f movi v15.2s, #0xe3
+ 4790: 0f07048f movi v15.2s, #0xe4
+ 4794: 0f0704af movi v15.2s, #0xe5
+ 4798: 0f0704cf movi v15.2s, #0xe6
+ 479c: 0f0704ef movi v15.2s, #0xe7
+ 47a0: 0f07050f movi v15.2s, #0xe8
+ 47a4: 0f07052f movi v15.2s, #0xe9
+ 47a8: 0f07054f movi v15.2s, #0xea
+ 47ac: 0f07056f movi v15.2s, #0xeb
+ 47b0: 0f07058f movi v15.2s, #0xec
+ 47b4: 0f0705af movi v15.2s, #0xed
+ 47b8: 0f0705cf movi v15.2s, #0xee
+ 47bc: 0f0705ef movi v15.2s, #0xef
+ 47c0: 0f07060f movi v15.2s, #0xf0
+ 47c4: 0f07062f movi v15.2s, #0xf1
+ 47c8: 0f07064f movi v15.2s, #0xf2
+ 47cc: 0f07066f movi v15.2s, #0xf3
+ 47d0: 0f07068f movi v15.2s, #0xf4
+ 47d4: 0f0706af movi v15.2s, #0xf5
+ 47d8: 0f0706cf movi v15.2s, #0xf6
+ 47dc: 0f0706ef movi v15.2s, #0xf7
+ 47e0: 0f07070f movi v15.2s, #0xf8
+ 47e4: 0f07072f movi v15.2s, #0xf9
+ 47e8: 0f07074f movi v15.2s, #0xfa
+ 47ec: 0f07076f movi v15.2s, #0xfb
+ 47f0: 0f07078f movi v15.2s, #0xfc
+ 47f4: 0f0707af movi v15.2s, #0xfd
+ 47f8: 0f0707cf movi v15.2s, #0xfe
+ 47fc: 0f0707ef movi v15.2s, #0xff
+ 4800: 0f002407 movi v7.2s, #0x0, lsl #8
+ 4804: 0f002427 movi v7.2s, #0x1, lsl #8
+ 4808: 0f002447 movi v7.2s, #0x2, lsl #8
+ 480c: 0f002467 movi v7.2s, #0x3, lsl #8
+ 4810: 0f002487 movi v7.2s, #0x4, lsl #8
+ 4814: 0f0024a7 movi v7.2s, #0x5, lsl #8
+ 4818: 0f0024c7 movi v7.2s, #0x6, lsl #8
+ 481c: 0f0024e7 movi v7.2s, #0x7, lsl #8
+ 4820: 0f002507 movi v7.2s, #0x8, lsl #8
+ 4824: 0f002527 movi v7.2s, #0x9, lsl #8
+ 4828: 0f002547 movi v7.2s, #0xa, lsl #8
+ 482c: 0f002567 movi v7.2s, #0xb, lsl #8
+ 4830: 0f002587 movi v7.2s, #0xc, lsl #8
+ 4834: 0f0025a7 movi v7.2s, #0xd, lsl #8
+ 4838: 0f0025c7 movi v7.2s, #0xe, lsl #8
+ 483c: 0f0025e7 movi v7.2s, #0xf, lsl #8
+ 4840: 0f002607 movi v7.2s, #0x10, lsl #8
+ 4844: 0f002627 movi v7.2s, #0x11, lsl #8
+ 4848: 0f002647 movi v7.2s, #0x12, lsl #8
+ 484c: 0f002667 movi v7.2s, #0x13, lsl #8
+ 4850: 0f002687 movi v7.2s, #0x14, lsl #8
+ 4854: 0f0026a7 movi v7.2s, #0x15, lsl #8
+ 4858: 0f0026c7 movi v7.2s, #0x16, lsl #8
+ 485c: 0f0026e7 movi v7.2s, #0x17, lsl #8
+ 4860: 0f002707 movi v7.2s, #0x18, lsl #8
+ 4864: 0f002727 movi v7.2s, #0x19, lsl #8
+ 4868: 0f002747 movi v7.2s, #0x1a, lsl #8
+ 486c: 0f002767 movi v7.2s, #0x1b, lsl #8
+ 4870: 0f002787 movi v7.2s, #0x1c, lsl #8
+ 4874: 0f0027a7 movi v7.2s, #0x1d, lsl #8
+ 4878: 0f0027c7 movi v7.2s, #0x1e, lsl #8
+ 487c: 0f0027e7 movi v7.2s, #0x1f, lsl #8
+ 4880: 0f012407 movi v7.2s, #0x20, lsl #8
+ 4884: 0f012427 movi v7.2s, #0x21, lsl #8
+ 4888: 0f012447 movi v7.2s, #0x22, lsl #8
+ 488c: 0f012467 movi v7.2s, #0x23, lsl #8
+ 4890: 0f012487 movi v7.2s, #0x24, lsl #8
+ 4894: 0f0124a7 movi v7.2s, #0x25, lsl #8
+ 4898: 0f0124c7 movi v7.2s, #0x26, lsl #8
+ 489c: 0f0124e7 movi v7.2s, #0x27, lsl #8
+ 48a0: 0f012507 movi v7.2s, #0x28, lsl #8
+ 48a4: 0f012527 movi v7.2s, #0x29, lsl #8
+ 48a8: 0f012547 movi v7.2s, #0x2a, lsl #8
+ 48ac: 0f012567 movi v7.2s, #0x2b, lsl #8
+ 48b0: 0f012587 movi v7.2s, #0x2c, lsl #8
+ 48b4: 0f0125a7 movi v7.2s, #0x2d, lsl #8
+ 48b8: 0f0125c7 movi v7.2s, #0x2e, lsl #8
+ 48bc: 0f0125e7 movi v7.2s, #0x2f, lsl #8
+ 48c0: 0f012607 movi v7.2s, #0x30, lsl #8
+ 48c4: 0f012627 movi v7.2s, #0x31, lsl #8
+ 48c8: 0f012647 movi v7.2s, #0x32, lsl #8
+ 48cc: 0f012667 movi v7.2s, #0x33, lsl #8
+ 48d0: 0f012687 movi v7.2s, #0x34, lsl #8
+ 48d4: 0f0126a7 movi v7.2s, #0x35, lsl #8
+ 48d8: 0f0126c7 movi v7.2s, #0x36, lsl #8
+ 48dc: 0f0126e7 movi v7.2s, #0x37, lsl #8
+ 48e0: 0f012707 movi v7.2s, #0x38, lsl #8
+ 48e4: 0f012727 movi v7.2s, #0x39, lsl #8
+ 48e8: 0f012747 movi v7.2s, #0x3a, lsl #8
+ 48ec: 0f012767 movi v7.2s, #0x3b, lsl #8
+ 48f0: 0f012787 movi v7.2s, #0x3c, lsl #8
+ 48f4: 0f0127a7 movi v7.2s, #0x3d, lsl #8
+ 48f8: 0f0127c7 movi v7.2s, #0x3e, lsl #8
+ 48fc: 0f0127e7 movi v7.2s, #0x3f, lsl #8
+ 4900: 0f022407 movi v7.2s, #0x40, lsl #8
+ 4904: 0f022427 movi v7.2s, #0x41, lsl #8
+ 4908: 0f022447 movi v7.2s, #0x42, lsl #8
+ 490c: 0f022467 movi v7.2s, #0x43, lsl #8
+ 4910: 0f022487 movi v7.2s, #0x44, lsl #8
+ 4914: 0f0224a7 movi v7.2s, #0x45, lsl #8
+ 4918: 0f0224c7 movi v7.2s, #0x46, lsl #8
+ 491c: 0f0224e7 movi v7.2s, #0x47, lsl #8
+ 4920: 0f022507 movi v7.2s, #0x48, lsl #8
+ 4924: 0f022527 movi v7.2s, #0x49, lsl #8
+ 4928: 0f022547 movi v7.2s, #0x4a, lsl #8
+ 492c: 0f022567 movi v7.2s, #0x4b, lsl #8
+ 4930: 0f022587 movi v7.2s, #0x4c, lsl #8
+ 4934: 0f0225a7 movi v7.2s, #0x4d, lsl #8
+ 4938: 0f0225c7 movi v7.2s, #0x4e, lsl #8
+ 493c: 0f0225e7 movi v7.2s, #0x4f, lsl #8
+ 4940: 0f022607 movi v7.2s, #0x50, lsl #8
+ 4944: 0f022627 movi v7.2s, #0x51, lsl #8
+ 4948: 0f022647 movi v7.2s, #0x52, lsl #8
+ 494c: 0f022667 movi v7.2s, #0x53, lsl #8
+ 4950: 0f022687 movi v7.2s, #0x54, lsl #8
+ 4954: 0f0226a7 movi v7.2s, #0x55, lsl #8
+ 4958: 0f0226c7 movi v7.2s, #0x56, lsl #8
+ 495c: 0f0226e7 movi v7.2s, #0x57, lsl #8
+ 4960: 0f022707 movi v7.2s, #0x58, lsl #8
+ 4964: 0f022727 movi v7.2s, #0x59, lsl #8
+ 4968: 0f022747 movi v7.2s, #0x5a, lsl #8
+ 496c: 0f022767 movi v7.2s, #0x5b, lsl #8
+ 4970: 0f022787 movi v7.2s, #0x5c, lsl #8
+ 4974: 0f0227a7 movi v7.2s, #0x5d, lsl #8
+ 4978: 0f0227c7 movi v7.2s, #0x5e, lsl #8
+ 497c: 0f0227e7 movi v7.2s, #0x5f, lsl #8
+ 4980: 0f032407 movi v7.2s, #0x60, lsl #8
+ 4984: 0f032427 movi v7.2s, #0x61, lsl #8
+ 4988: 0f032447 movi v7.2s, #0x62, lsl #8
+ 498c: 0f032467 movi v7.2s, #0x63, lsl #8
+ 4990: 0f032487 movi v7.2s, #0x64, lsl #8
+ 4994: 0f0324a7 movi v7.2s, #0x65, lsl #8
+ 4998: 0f0324c7 movi v7.2s, #0x66, lsl #8
+ 499c: 0f0324e7 movi v7.2s, #0x67, lsl #8
+ 49a0: 0f032507 movi v7.2s, #0x68, lsl #8
+ 49a4: 0f032527 movi v7.2s, #0x69, lsl #8
+ 49a8: 0f032547 movi v7.2s, #0x6a, lsl #8
+ 49ac: 0f032567 movi v7.2s, #0x6b, lsl #8
+ 49b0: 0f032587 movi v7.2s, #0x6c, lsl #8
+ 49b4: 0f0325a7 movi v7.2s, #0x6d, lsl #8
+ 49b8: 0f0325c7 movi v7.2s, #0x6e, lsl #8
+ 49bc: 0f0325e7 movi v7.2s, #0x6f, lsl #8
+ 49c0: 0f032607 movi v7.2s, #0x70, lsl #8
+ 49c4: 0f032627 movi v7.2s, #0x71, lsl #8
+ 49c8: 0f032647 movi v7.2s, #0x72, lsl #8
+ 49cc: 0f032667 movi v7.2s, #0x73, lsl #8
+ 49d0: 0f032687 movi v7.2s, #0x74, lsl #8
+ 49d4: 0f0326a7 movi v7.2s, #0x75, lsl #8
+ 49d8: 0f0326c7 movi v7.2s, #0x76, lsl #8
+ 49dc: 0f0326e7 movi v7.2s, #0x77, lsl #8
+ 49e0: 0f032707 movi v7.2s, #0x78, lsl #8
+ 49e4: 0f032727 movi v7.2s, #0x79, lsl #8
+ 49e8: 0f032747 movi v7.2s, #0x7a, lsl #8
+ 49ec: 0f032767 movi v7.2s, #0x7b, lsl #8
+ 49f0: 0f032787 movi v7.2s, #0x7c, lsl #8
+ 49f4: 0f0327a7 movi v7.2s, #0x7d, lsl #8
+ 49f8: 0f0327c7 movi v7.2s, #0x7e, lsl #8
+ 49fc: 0f0327e7 movi v7.2s, #0x7f, lsl #8
+ 4a00: 0f042407 movi v7.2s, #0x80, lsl #8
+ 4a04: 0f042427 movi v7.2s, #0x81, lsl #8
+ 4a08: 0f042447 movi v7.2s, #0x82, lsl #8
+ 4a0c: 0f042467 movi v7.2s, #0x83, lsl #8
+ 4a10: 0f042487 movi v7.2s, #0x84, lsl #8
+ 4a14: 0f0424a7 movi v7.2s, #0x85, lsl #8
+ 4a18: 0f0424c7 movi v7.2s, #0x86, lsl #8
+ 4a1c: 0f0424e7 movi v7.2s, #0x87, lsl #8
+ 4a20: 0f042507 movi v7.2s, #0x88, lsl #8
+ 4a24: 0f042527 movi v7.2s, #0x89, lsl #8
+ 4a28: 0f042547 movi v7.2s, #0x8a, lsl #8
+ 4a2c: 0f042567 movi v7.2s, #0x8b, lsl #8
+ 4a30: 0f042587 movi v7.2s, #0x8c, lsl #8
+ 4a34: 0f0425a7 movi v7.2s, #0x8d, lsl #8
+ 4a38: 0f0425c7 movi v7.2s, #0x8e, lsl #8
+ 4a3c: 0f0425e7 movi v7.2s, #0x8f, lsl #8
+ 4a40: 0f042607 movi v7.2s, #0x90, lsl #8
+ 4a44: 0f042627 movi v7.2s, #0x91, lsl #8
+ 4a48: 0f042647 movi v7.2s, #0x92, lsl #8
+ 4a4c: 0f042667 movi v7.2s, #0x93, lsl #8
+ 4a50: 0f042687 movi v7.2s, #0x94, lsl #8
+ 4a54: 0f0426a7 movi v7.2s, #0x95, lsl #8
+ 4a58: 0f0426c7 movi v7.2s, #0x96, lsl #8
+ 4a5c: 0f0426e7 movi v7.2s, #0x97, lsl #8
+ 4a60: 0f042707 movi v7.2s, #0x98, lsl #8
+ 4a64: 0f042727 movi v7.2s, #0x99, lsl #8
+ 4a68: 0f042747 movi v7.2s, #0x9a, lsl #8
+ 4a6c: 0f042767 movi v7.2s, #0x9b, lsl #8
+ 4a70: 0f042787 movi v7.2s, #0x9c, lsl #8
+ 4a74: 0f0427a7 movi v7.2s, #0x9d, lsl #8
+ 4a78: 0f0427c7 movi v7.2s, #0x9e, lsl #8
+ 4a7c: 0f0427e7 movi v7.2s, #0x9f, lsl #8
+ 4a80: 0f052407 movi v7.2s, #0xa0, lsl #8
+ 4a84: 0f052427 movi v7.2s, #0xa1, lsl #8
+ 4a88: 0f052447 movi v7.2s, #0xa2, lsl #8
+ 4a8c: 0f052467 movi v7.2s, #0xa3, lsl #8
+ 4a90: 0f052487 movi v7.2s, #0xa4, lsl #8
+ 4a94: 0f0524a7 movi v7.2s, #0xa5, lsl #8
+ 4a98: 0f0524c7 movi v7.2s, #0xa6, lsl #8
+ 4a9c: 0f0524e7 movi v7.2s, #0xa7, lsl #8
+ 4aa0: 0f052507 movi v7.2s, #0xa8, lsl #8
+ 4aa4: 0f052527 movi v7.2s, #0xa9, lsl #8
+ 4aa8: 0f052547 movi v7.2s, #0xaa, lsl #8
+ 4aac: 0f052567 movi v7.2s, #0xab, lsl #8
+ 4ab0: 0f052587 movi v7.2s, #0xac, lsl #8
+ 4ab4: 0f0525a7 movi v7.2s, #0xad, lsl #8
+ 4ab8: 0f0525c7 movi v7.2s, #0xae, lsl #8
+ 4abc: 0f0525e7 movi v7.2s, #0xaf, lsl #8
+ 4ac0: 0f052607 movi v7.2s, #0xb0, lsl #8
+ 4ac4: 0f052627 movi v7.2s, #0xb1, lsl #8
+ 4ac8: 0f052647 movi v7.2s, #0xb2, lsl #8
+ 4acc: 0f052667 movi v7.2s, #0xb3, lsl #8
+ 4ad0: 0f052687 movi v7.2s, #0xb4, lsl #8
+ 4ad4: 0f0526a7 movi v7.2s, #0xb5, lsl #8
+ 4ad8: 0f0526c7 movi v7.2s, #0xb6, lsl #8
+ 4adc: 0f0526e7 movi v7.2s, #0xb7, lsl #8
+ 4ae0: 0f052707 movi v7.2s, #0xb8, lsl #8
+ 4ae4: 0f052727 movi v7.2s, #0xb9, lsl #8
+ 4ae8: 0f052747 movi v7.2s, #0xba, lsl #8
+ 4aec: 0f052767 movi v7.2s, #0xbb, lsl #8
+ 4af0: 0f052787 movi v7.2s, #0xbc, lsl #8
+ 4af4: 0f0527a7 movi v7.2s, #0xbd, lsl #8
+ 4af8: 0f0527c7 movi v7.2s, #0xbe, lsl #8
+ 4afc: 0f0527e7 movi v7.2s, #0xbf, lsl #8
+ 4b00: 0f062407 movi v7.2s, #0xc0, lsl #8
+ 4b04: 0f062427 movi v7.2s, #0xc1, lsl #8
+ 4b08: 0f062447 movi v7.2s, #0xc2, lsl #8
+ 4b0c: 0f062467 movi v7.2s, #0xc3, lsl #8
+ 4b10: 0f062487 movi v7.2s, #0xc4, lsl #8
+ 4b14: 0f0624a7 movi v7.2s, #0xc5, lsl #8
+ 4b18: 0f0624c7 movi v7.2s, #0xc6, lsl #8
+ 4b1c: 0f0624e7 movi v7.2s, #0xc7, lsl #8
+ 4b20: 0f062507 movi v7.2s, #0xc8, lsl #8
+ 4b24: 0f062527 movi v7.2s, #0xc9, lsl #8
+ 4b28: 0f062547 movi v7.2s, #0xca, lsl #8
+ 4b2c: 0f062567 movi v7.2s, #0xcb, lsl #8
+ 4b30: 0f062587 movi v7.2s, #0xcc, lsl #8
+ 4b34: 0f0625a7 movi v7.2s, #0xcd, lsl #8
+ 4b38: 0f0625c7 movi v7.2s, #0xce, lsl #8
+ 4b3c: 0f0625e7 movi v7.2s, #0xcf, lsl #8
+ 4b40: 0f062607 movi v7.2s, #0xd0, lsl #8
+ 4b44: 0f062627 movi v7.2s, #0xd1, lsl #8
+ 4b48: 0f062647 movi v7.2s, #0xd2, lsl #8
+ 4b4c: 0f062667 movi v7.2s, #0xd3, lsl #8
+ 4b50: 0f062687 movi v7.2s, #0xd4, lsl #8
+ 4b54: 0f0626a7 movi v7.2s, #0xd5, lsl #8
+ 4b58: 0f0626c7 movi v7.2s, #0xd6, lsl #8
+ 4b5c: 0f0626e7 movi v7.2s, #0xd7, lsl #8
+ 4b60: 0f062707 movi v7.2s, #0xd8, lsl #8
+ 4b64: 0f062727 movi v7.2s, #0xd9, lsl #8
+ 4b68: 0f062747 movi v7.2s, #0xda, lsl #8
+ 4b6c: 0f062767 movi v7.2s, #0xdb, lsl #8
+ 4b70: 0f062787 movi v7.2s, #0xdc, lsl #8
+ 4b74: 0f0627a7 movi v7.2s, #0xdd, lsl #8
+ 4b78: 0f0627c7 movi v7.2s, #0xde, lsl #8
+ 4b7c: 0f0627e7 movi v7.2s, #0xdf, lsl #8
+ 4b80: 0f072407 movi v7.2s, #0xe0, lsl #8
+ 4b84: 0f072427 movi v7.2s, #0xe1, lsl #8
+ 4b88: 0f072447 movi v7.2s, #0xe2, lsl #8
+ 4b8c: 0f072467 movi v7.2s, #0xe3, lsl #8
+ 4b90: 0f072487 movi v7.2s, #0xe4, lsl #8
+ 4b94: 0f0724a7 movi v7.2s, #0xe5, lsl #8
+ 4b98: 0f0724c7 movi v7.2s, #0xe6, lsl #8
+ 4b9c: 0f0724e7 movi v7.2s, #0xe7, lsl #8
+ 4ba0: 0f072507 movi v7.2s, #0xe8, lsl #8
+ 4ba4: 0f072527 movi v7.2s, #0xe9, lsl #8
+ 4ba8: 0f072547 movi v7.2s, #0xea, lsl #8
+ 4bac: 0f072567 movi v7.2s, #0xeb, lsl #8
+ 4bb0: 0f072587 movi v7.2s, #0xec, lsl #8
+ 4bb4: 0f0725a7 movi v7.2s, #0xed, lsl #8
+ 4bb8: 0f0725c7 movi v7.2s, #0xee, lsl #8
+ 4bbc: 0f0725e7 movi v7.2s, #0xef, lsl #8
+ 4bc0: 0f072607 movi v7.2s, #0xf0, lsl #8
+ 4bc4: 0f072627 movi v7.2s, #0xf1, lsl #8
+ 4bc8: 0f072647 movi v7.2s, #0xf2, lsl #8
+ 4bcc: 0f072667 movi v7.2s, #0xf3, lsl #8
+ 4bd0: 0f072687 movi v7.2s, #0xf4, lsl #8
+ 4bd4: 0f0726a7 movi v7.2s, #0xf5, lsl #8
+ 4bd8: 0f0726c7 movi v7.2s, #0xf6, lsl #8
+ 4bdc: 0f0726e7 movi v7.2s, #0xf7, lsl #8
+ 4be0: 0f072707 movi v7.2s, #0xf8, lsl #8
+ 4be4: 0f072727 movi v7.2s, #0xf9, lsl #8
+ 4be8: 0f072747 movi v7.2s, #0xfa, lsl #8
+ 4bec: 0f072767 movi v7.2s, #0xfb, lsl #8
+ 4bf0: 0f072787 movi v7.2s, #0xfc, lsl #8
+ 4bf4: 0f0727a7 movi v7.2s, #0xfd, lsl #8
+ 4bf8: 0f0727c7 movi v7.2s, #0xfe, lsl #8
+ 4bfc: 0f0727e7 movi v7.2s, #0xff, lsl #8
+ 4c00: 0f00040f movi v15.2s, #0x0
+ 4c04: 0f00042f movi v15.2s, #0x1
+ 4c08: 0f00044f movi v15.2s, #0x2
+ 4c0c: 0f00046f movi v15.2s, #0x3
+ 4c10: 0f00048f movi v15.2s, #0x4
+ 4c14: 0f0004af movi v15.2s, #0x5
+ 4c18: 0f0004cf movi v15.2s, #0x6
+ 4c1c: 0f0004ef movi v15.2s, #0x7
+ 4c20: 0f00050f movi v15.2s, #0x8
+ 4c24: 0f00052f movi v15.2s, #0x9
+ 4c28: 0f00054f movi v15.2s, #0xa
+ 4c2c: 0f00056f movi v15.2s, #0xb
+ 4c30: 0f00058f movi v15.2s, #0xc
+ 4c34: 0f0005af movi v15.2s, #0xd
+ 4c38: 0f0005cf movi v15.2s, #0xe
+ 4c3c: 0f0005ef movi v15.2s, #0xf
+ 4c40: 0f00060f movi v15.2s, #0x10
+ 4c44: 0f00062f movi v15.2s, #0x11
+ 4c48: 0f00064f movi v15.2s, #0x12
+ 4c4c: 0f00066f movi v15.2s, #0x13
+ 4c50: 0f00068f movi v15.2s, #0x14
+ 4c54: 0f0006af movi v15.2s, #0x15
+ 4c58: 0f0006cf movi v15.2s, #0x16
+ 4c5c: 0f0006ef movi v15.2s, #0x17
+ 4c60: 0f00070f movi v15.2s, #0x18
+ 4c64: 0f00072f movi v15.2s, #0x19
+ 4c68: 0f00074f movi v15.2s, #0x1a
+ 4c6c: 0f00076f movi v15.2s, #0x1b
+ 4c70: 0f00078f movi v15.2s, #0x1c
+ 4c74: 0f0007af movi v15.2s, #0x1d
+ 4c78: 0f0007cf movi v15.2s, #0x1e
+ 4c7c: 0f0007ef movi v15.2s, #0x1f
+ 4c80: 0f01040f movi v15.2s, #0x20
+ 4c84: 0f01042f movi v15.2s, #0x21
+ 4c88: 0f01044f movi v15.2s, #0x22
+ 4c8c: 0f01046f movi v15.2s, #0x23
+ 4c90: 0f01048f movi v15.2s, #0x24
+ 4c94: 0f0104af movi v15.2s, #0x25
+ 4c98: 0f0104cf movi v15.2s, #0x26
+ 4c9c: 0f0104ef movi v15.2s, #0x27
+ 4ca0: 0f01050f movi v15.2s, #0x28
+ 4ca4: 0f01052f movi v15.2s, #0x29
+ 4ca8: 0f01054f movi v15.2s, #0x2a
+ 4cac: 0f01056f movi v15.2s, #0x2b
+ 4cb0: 0f01058f movi v15.2s, #0x2c
+ 4cb4: 0f0105af movi v15.2s, #0x2d
+ 4cb8: 0f0105cf movi v15.2s, #0x2e
+ 4cbc: 0f0105ef movi v15.2s, #0x2f
+ 4cc0: 0f01060f movi v15.2s, #0x30
+ 4cc4: 0f01062f movi v15.2s, #0x31
+ 4cc8: 0f01064f movi v15.2s, #0x32
+ 4ccc: 0f01066f movi v15.2s, #0x33
+ 4cd0: 0f01068f movi v15.2s, #0x34
+ 4cd4: 0f0106af movi v15.2s, #0x35
+ 4cd8: 0f0106cf movi v15.2s, #0x36
+ 4cdc: 0f0106ef movi v15.2s, #0x37
+ 4ce0: 0f01070f movi v15.2s, #0x38
+ 4ce4: 0f01072f movi v15.2s, #0x39
+ 4ce8: 0f01074f movi v15.2s, #0x3a
+ 4cec: 0f01076f movi v15.2s, #0x3b
+ 4cf0: 0f01078f movi v15.2s, #0x3c
+ 4cf4: 0f0107af movi v15.2s, #0x3d
+ 4cf8: 0f0107cf movi v15.2s, #0x3e
+ 4cfc: 0f0107ef movi v15.2s, #0x3f
+ 4d00: 0f02040f movi v15.2s, #0x40
+ 4d04: 0f02042f movi v15.2s, #0x41
+ 4d08: 0f02044f movi v15.2s, #0x42
+ 4d0c: 0f02046f movi v15.2s, #0x43
+ 4d10: 0f02048f movi v15.2s, #0x44
+ 4d14: 0f0204af movi v15.2s, #0x45
+ 4d18: 0f0204cf movi v15.2s, #0x46
+ 4d1c: 0f0204ef movi v15.2s, #0x47
+ 4d20: 0f02050f movi v15.2s, #0x48
+ 4d24: 0f02052f movi v15.2s, #0x49
+ 4d28: 0f02054f movi v15.2s, #0x4a
+ 4d2c: 0f02056f movi v15.2s, #0x4b
+ 4d30: 0f02058f movi v15.2s, #0x4c
+ 4d34: 0f0205af movi v15.2s, #0x4d
+ 4d38: 0f0205cf movi v15.2s, #0x4e
+ 4d3c: 0f0205ef movi v15.2s, #0x4f
+ 4d40: 0f02060f movi v15.2s, #0x50
+ 4d44: 0f02062f movi v15.2s, #0x51
+ 4d48: 0f02064f movi v15.2s, #0x52
+ 4d4c: 0f02066f movi v15.2s, #0x53
+ 4d50: 0f02068f movi v15.2s, #0x54
+ 4d54: 0f0206af movi v15.2s, #0x55
+ 4d58: 0f0206cf movi v15.2s, #0x56
+ 4d5c: 0f0206ef movi v15.2s, #0x57
+ 4d60: 0f02070f movi v15.2s, #0x58
+ 4d64: 0f02072f movi v15.2s, #0x59
+ 4d68: 0f02074f movi v15.2s, #0x5a
+ 4d6c: 0f02076f movi v15.2s, #0x5b
+ 4d70: 0f02078f movi v15.2s, #0x5c
+ 4d74: 0f0207af movi v15.2s, #0x5d
+ 4d78: 0f0207cf movi v15.2s, #0x5e
+ 4d7c: 0f0207ef movi v15.2s, #0x5f
+ 4d80: 0f03040f movi v15.2s, #0x60
+ 4d84: 0f03042f movi v15.2s, #0x61
+ 4d88: 0f03044f movi v15.2s, #0x62
+ 4d8c: 0f03046f movi v15.2s, #0x63
+ 4d90: 0f03048f movi v15.2s, #0x64
+ 4d94: 0f0304af movi v15.2s, #0x65
+ 4d98: 0f0304cf movi v15.2s, #0x66
+ 4d9c: 0f0304ef movi v15.2s, #0x67
+ 4da0: 0f03050f movi v15.2s, #0x68
+ 4da4: 0f03052f movi v15.2s, #0x69
+ 4da8: 0f03054f movi v15.2s, #0x6a
+ 4dac: 0f03056f movi v15.2s, #0x6b
+ 4db0: 0f03058f movi v15.2s, #0x6c
+ 4db4: 0f0305af movi v15.2s, #0x6d
+ 4db8: 0f0305cf movi v15.2s, #0x6e
+ 4dbc: 0f0305ef movi v15.2s, #0x6f
+ 4dc0: 0f03060f movi v15.2s, #0x70
+ 4dc4: 0f03062f movi v15.2s, #0x71
+ 4dc8: 0f03064f movi v15.2s, #0x72
+ 4dcc: 0f03066f movi v15.2s, #0x73
+ 4dd0: 0f03068f movi v15.2s, #0x74
+ 4dd4: 0f0306af movi v15.2s, #0x75
+ 4dd8: 0f0306cf movi v15.2s, #0x76
+ 4ddc: 0f0306ef movi v15.2s, #0x77
+ 4de0: 0f03070f movi v15.2s, #0x78
+ 4de4: 0f03072f movi v15.2s, #0x79
+ 4de8: 0f03074f movi v15.2s, #0x7a
+ 4dec: 0f03076f movi v15.2s, #0x7b
+ 4df0: 0f03078f movi v15.2s, #0x7c
+ 4df4: 0f0307af movi v15.2s, #0x7d
+ 4df8: 0f0307cf movi v15.2s, #0x7e
+ 4dfc: 0f0307ef movi v15.2s, #0x7f
+ 4e00: 0f04040f movi v15.2s, #0x80
+ 4e04: 0f04042f movi v15.2s, #0x81
+ 4e08: 0f04044f movi v15.2s, #0x82
+ 4e0c: 0f04046f movi v15.2s, #0x83
+ 4e10: 0f04048f movi v15.2s, #0x84
+ 4e14: 0f0404af movi v15.2s, #0x85
+ 4e18: 0f0404cf movi v15.2s, #0x86
+ 4e1c: 0f0404ef movi v15.2s, #0x87
+ 4e20: 0f04050f movi v15.2s, #0x88
+ 4e24: 0f04052f movi v15.2s, #0x89
+ 4e28: 0f04054f movi v15.2s, #0x8a
+ 4e2c: 0f04056f movi v15.2s, #0x8b
+ 4e30: 0f04058f movi v15.2s, #0x8c
+ 4e34: 0f0405af movi v15.2s, #0x8d
+ 4e38: 0f0405cf movi v15.2s, #0x8e
+ 4e3c: 0f0405ef movi v15.2s, #0x8f
+ 4e40: 0f04060f movi v15.2s, #0x90
+ 4e44: 0f04062f movi v15.2s, #0x91
+ 4e48: 0f04064f movi v15.2s, #0x92
+ 4e4c: 0f04066f movi v15.2s, #0x93
+ 4e50: 0f04068f movi v15.2s, #0x94
+ 4e54: 0f0406af movi v15.2s, #0x95
+ 4e58: 0f0406cf movi v15.2s, #0x96
+ 4e5c: 0f0406ef movi v15.2s, #0x97
+ 4e60: 0f04070f movi v15.2s, #0x98
+ 4e64: 0f04072f movi v15.2s, #0x99
+ 4e68: 0f04074f movi v15.2s, #0x9a
+ 4e6c: 0f04076f movi v15.2s, #0x9b
+ 4e70: 0f04078f movi v15.2s, #0x9c
+ 4e74: 0f0407af movi v15.2s, #0x9d
+ 4e78: 0f0407cf movi v15.2s, #0x9e
+ 4e7c: 0f0407ef movi v15.2s, #0x9f
+ 4e80: 0f05040f movi v15.2s, #0xa0
+ 4e84: 0f05042f movi v15.2s, #0xa1
+ 4e88: 0f05044f movi v15.2s, #0xa2
+ 4e8c: 0f05046f movi v15.2s, #0xa3
+ 4e90: 0f05048f movi v15.2s, #0xa4
+ 4e94: 0f0504af movi v15.2s, #0xa5
+ 4e98: 0f0504cf movi v15.2s, #0xa6
+ 4e9c: 0f0504ef movi v15.2s, #0xa7
+ 4ea0: 0f05050f movi v15.2s, #0xa8
+ 4ea4: 0f05052f movi v15.2s, #0xa9
+ 4ea8: 0f05054f movi v15.2s, #0xaa
+ 4eac: 0f05056f movi v15.2s, #0xab
+ 4eb0: 0f05058f movi v15.2s, #0xac
+ 4eb4: 0f0505af movi v15.2s, #0xad
+ 4eb8: 0f0505cf movi v15.2s, #0xae
+ 4ebc: 0f0505ef movi v15.2s, #0xaf
+ 4ec0: 0f05060f movi v15.2s, #0xb0
+ 4ec4: 0f05062f movi v15.2s, #0xb1
+ 4ec8: 0f05064f movi v15.2s, #0xb2
+ 4ecc: 0f05066f movi v15.2s, #0xb3
+ 4ed0: 0f05068f movi v15.2s, #0xb4
+ 4ed4: 0f0506af movi v15.2s, #0xb5
+ 4ed8: 0f0506cf movi v15.2s, #0xb6
+ 4edc: 0f0506ef movi v15.2s, #0xb7
+ 4ee0: 0f05070f movi v15.2s, #0xb8
+ 4ee4: 0f05072f movi v15.2s, #0xb9
+ 4ee8: 0f05074f movi v15.2s, #0xba
+ 4eec: 0f05076f movi v15.2s, #0xbb
+ 4ef0: 0f05078f movi v15.2s, #0xbc
+ 4ef4: 0f0507af movi v15.2s, #0xbd
+ 4ef8: 0f0507cf movi v15.2s, #0xbe
+ 4efc: 0f0507ef movi v15.2s, #0xbf
+ 4f00: 0f06040f movi v15.2s, #0xc0
+ 4f04: 0f06042f movi v15.2s, #0xc1
+ 4f08: 0f06044f movi v15.2s, #0xc2
+ 4f0c: 0f06046f movi v15.2s, #0xc3
+ 4f10: 0f06048f movi v15.2s, #0xc4
+ 4f14: 0f0604af movi v15.2s, #0xc5
+ 4f18: 0f0604cf movi v15.2s, #0xc6
+ 4f1c: 0f0604ef movi v15.2s, #0xc7
+ 4f20: 0f06050f movi v15.2s, #0xc8
+ 4f24: 0f06052f movi v15.2s, #0xc9
+ 4f28: 0f06054f movi v15.2s, #0xca
+ 4f2c: 0f06056f movi v15.2s, #0xcb
+ 4f30: 0f06058f movi v15.2s, #0xcc
+ 4f34: 0f0605af movi v15.2s, #0xcd
+ 4f38: 0f0605cf movi v15.2s, #0xce
+ 4f3c: 0f0605ef movi v15.2s, #0xcf
+ 4f40: 0f06060f movi v15.2s, #0xd0
+ 4f44: 0f06062f movi v15.2s, #0xd1
+ 4f48: 0f06064f movi v15.2s, #0xd2
+ 4f4c: 0f06066f movi v15.2s, #0xd3
+ 4f50: 0f06068f movi v15.2s, #0xd4
+ 4f54: 0f0606af movi v15.2s, #0xd5
+ 4f58: 0f0606cf movi v15.2s, #0xd6
+ 4f5c: 0f0606ef movi v15.2s, #0xd7
+ 4f60: 0f06070f movi v15.2s, #0xd8
+ 4f64: 0f06072f movi v15.2s, #0xd9
+ 4f68: 0f06074f movi v15.2s, #0xda
+ 4f6c: 0f06076f movi v15.2s, #0xdb
+ 4f70: 0f06078f movi v15.2s, #0xdc
+ 4f74: 0f0607af movi v15.2s, #0xdd
+ 4f78: 0f0607cf movi v15.2s, #0xde
+ 4f7c: 0f0607ef movi v15.2s, #0xdf
+ 4f80: 0f07040f movi v15.2s, #0xe0
+ 4f84: 0f07042f movi v15.2s, #0xe1
+ 4f88: 0f07044f movi v15.2s, #0xe2
+ 4f8c: 0f07046f movi v15.2s, #0xe3
+ 4f90: 0f07048f movi v15.2s, #0xe4
+ 4f94: 0f0704af movi v15.2s, #0xe5
+ 4f98: 0f0704cf movi v15.2s, #0xe6
+ 4f9c: 0f0704ef movi v15.2s, #0xe7
+ 4fa0: 0f07050f movi v15.2s, #0xe8
+ 4fa4: 0f07052f movi v15.2s, #0xe9
+ 4fa8: 0f07054f movi v15.2s, #0xea
+ 4fac: 0f07056f movi v15.2s, #0xeb
+ 4fb0: 0f07058f movi v15.2s, #0xec
+ 4fb4: 0f0705af movi v15.2s, #0xed
+ 4fb8: 0f0705cf movi v15.2s, #0xee
+ 4fbc: 0f0705ef movi v15.2s, #0xef
+ 4fc0: 0f07060f movi v15.2s, #0xf0
+ 4fc4: 0f07062f movi v15.2s, #0xf1
+ 4fc8: 0f07064f movi v15.2s, #0xf2
+ 4fcc: 0f07066f movi v15.2s, #0xf3
+ 4fd0: 0f07068f movi v15.2s, #0xf4
+ 4fd4: 0f0706af movi v15.2s, #0xf5
+ 4fd8: 0f0706cf movi v15.2s, #0xf6
+ 4fdc: 0f0706ef movi v15.2s, #0xf7
+ 4fe0: 0f07070f movi v15.2s, #0xf8
+ 4fe4: 0f07072f movi v15.2s, #0xf9
+ 4fe8: 0f07074f movi v15.2s, #0xfa
+ 4fec: 0f07076f movi v15.2s, #0xfb
+ 4ff0: 0f07078f movi v15.2s, #0xfc
+ 4ff4: 0f0707af movi v15.2s, #0xfd
+ 4ff8: 0f0707cf movi v15.2s, #0xfe
+ 4ffc: 0f0707ef movi v15.2s, #0xff
+ 5000: 0f004407 movi v7.2s, #0x0, lsl #16
+ 5004: 0f004427 movi v7.2s, #0x1, lsl #16
+ 5008: 0f004447 movi v7.2s, #0x2, lsl #16
+ 500c: 0f004467 movi v7.2s, #0x3, lsl #16
+ 5010: 0f004487 movi v7.2s, #0x4, lsl #16
+ 5014: 0f0044a7 movi v7.2s, #0x5, lsl #16
+ 5018: 0f0044c7 movi v7.2s, #0x6, lsl #16
+ 501c: 0f0044e7 movi v7.2s, #0x7, lsl #16
+ 5020: 0f004507 movi v7.2s, #0x8, lsl #16
+ 5024: 0f004527 movi v7.2s, #0x9, lsl #16
+ 5028: 0f004547 movi v7.2s, #0xa, lsl #16
+ 502c: 0f004567 movi v7.2s, #0xb, lsl #16
+ 5030: 0f004587 movi v7.2s, #0xc, lsl #16
+ 5034: 0f0045a7 movi v7.2s, #0xd, lsl #16
+ 5038: 0f0045c7 movi v7.2s, #0xe, lsl #16
+ 503c: 0f0045e7 movi v7.2s, #0xf, lsl #16
+ 5040: 0f004607 movi v7.2s, #0x10, lsl #16
+ 5044: 0f004627 movi v7.2s, #0x11, lsl #16
+ 5048: 0f004647 movi v7.2s, #0x12, lsl #16
+ 504c: 0f004667 movi v7.2s, #0x13, lsl #16
+ 5050: 0f004687 movi v7.2s, #0x14, lsl #16
+ 5054: 0f0046a7 movi v7.2s, #0x15, lsl #16
+ 5058: 0f0046c7 movi v7.2s, #0x16, lsl #16
+ 505c: 0f0046e7 movi v7.2s, #0x17, lsl #16
+ 5060: 0f004707 movi v7.2s, #0x18, lsl #16
+ 5064: 0f004727 movi v7.2s, #0x19, lsl #16
+ 5068: 0f004747 movi v7.2s, #0x1a, lsl #16
+ 506c: 0f004767 movi v7.2s, #0x1b, lsl #16
+ 5070: 0f004787 movi v7.2s, #0x1c, lsl #16
+ 5074: 0f0047a7 movi v7.2s, #0x1d, lsl #16
+ 5078: 0f0047c7 movi v7.2s, #0x1e, lsl #16
+ 507c: 0f0047e7 movi v7.2s, #0x1f, lsl #16
+ 5080: 0f014407 movi v7.2s, #0x20, lsl #16
+ 5084: 0f014427 movi v7.2s, #0x21, lsl #16
+ 5088: 0f014447 movi v7.2s, #0x22, lsl #16
+ 508c: 0f014467 movi v7.2s, #0x23, lsl #16
+ 5090: 0f014487 movi v7.2s, #0x24, lsl #16
+ 5094: 0f0144a7 movi v7.2s, #0x25, lsl #16
+ 5098: 0f0144c7 movi v7.2s, #0x26, lsl #16
+ 509c: 0f0144e7 movi v7.2s, #0x27, lsl #16
+ 50a0: 0f014507 movi v7.2s, #0x28, lsl #16
+ 50a4: 0f014527 movi v7.2s, #0x29, lsl #16
+ 50a8: 0f014547 movi v7.2s, #0x2a, lsl #16
+ 50ac: 0f014567 movi v7.2s, #0x2b, lsl #16
+ 50b0: 0f014587 movi v7.2s, #0x2c, lsl #16
+ 50b4: 0f0145a7 movi v7.2s, #0x2d, lsl #16
+ 50b8: 0f0145c7 movi v7.2s, #0x2e, lsl #16
+ 50bc: 0f0145e7 movi v7.2s, #0x2f, lsl #16
+ 50c0: 0f014607 movi v7.2s, #0x30, lsl #16
+ 50c4: 0f014627 movi v7.2s, #0x31, lsl #16
+ 50c8: 0f014647 movi v7.2s, #0x32, lsl #16
+ 50cc: 0f014667 movi v7.2s, #0x33, lsl #16
+ 50d0: 0f014687 movi v7.2s, #0x34, lsl #16
+ 50d4: 0f0146a7 movi v7.2s, #0x35, lsl #16
+ 50d8: 0f0146c7 movi v7.2s, #0x36, lsl #16
+ 50dc: 0f0146e7 movi v7.2s, #0x37, lsl #16
+ 50e0: 0f014707 movi v7.2s, #0x38, lsl #16
+ 50e4: 0f014727 movi v7.2s, #0x39, lsl #16
+ 50e8: 0f014747 movi v7.2s, #0x3a, lsl #16
+ 50ec: 0f014767 movi v7.2s, #0x3b, lsl #16
+ 50f0: 0f014787 movi v7.2s, #0x3c, lsl #16
+ 50f4: 0f0147a7 movi v7.2s, #0x3d, lsl #16
+ 50f8: 0f0147c7 movi v7.2s, #0x3e, lsl #16
+ 50fc: 0f0147e7 movi v7.2s, #0x3f, lsl #16
+ 5100: 0f024407 movi v7.2s, #0x40, lsl #16
+ 5104: 0f024427 movi v7.2s, #0x41, lsl #16
+ 5108: 0f024447 movi v7.2s, #0x42, lsl #16
+ 510c: 0f024467 movi v7.2s, #0x43, lsl #16
+ 5110: 0f024487 movi v7.2s, #0x44, lsl #16
+ 5114: 0f0244a7 movi v7.2s, #0x45, lsl #16
+ 5118: 0f0244c7 movi v7.2s, #0x46, lsl #16
+ 511c: 0f0244e7 movi v7.2s, #0x47, lsl #16
+ 5120: 0f024507 movi v7.2s, #0x48, lsl #16
+ 5124: 0f024527 movi v7.2s, #0x49, lsl #16
+ 5128: 0f024547 movi v7.2s, #0x4a, lsl #16
+ 512c: 0f024567 movi v7.2s, #0x4b, lsl #16
+ 5130: 0f024587 movi v7.2s, #0x4c, lsl #16
+ 5134: 0f0245a7 movi v7.2s, #0x4d, lsl #16
+ 5138: 0f0245c7 movi v7.2s, #0x4e, lsl #16
+ 513c: 0f0245e7 movi v7.2s, #0x4f, lsl #16
+ 5140: 0f024607 movi v7.2s, #0x50, lsl #16
+ 5144: 0f024627 movi v7.2s, #0x51, lsl #16
+ 5148: 0f024647 movi v7.2s, #0x52, lsl #16
+ 514c: 0f024667 movi v7.2s, #0x53, lsl #16
+ 5150: 0f024687 movi v7.2s, #0x54, lsl #16
+ 5154: 0f0246a7 movi v7.2s, #0x55, lsl #16
+ 5158: 0f0246c7 movi v7.2s, #0x56, lsl #16
+ 515c: 0f0246e7 movi v7.2s, #0x57, lsl #16
+ 5160: 0f024707 movi v7.2s, #0x58, lsl #16
+ 5164: 0f024727 movi v7.2s, #0x59, lsl #16
+ 5168: 0f024747 movi v7.2s, #0x5a, lsl #16
+ 516c: 0f024767 movi v7.2s, #0x5b, lsl #16
+ 5170: 0f024787 movi v7.2s, #0x5c, lsl #16
+ 5174: 0f0247a7 movi v7.2s, #0x5d, lsl #16
+ 5178: 0f0247c7 movi v7.2s, #0x5e, lsl #16
+ 517c: 0f0247e7 movi v7.2s, #0x5f, lsl #16
+ 5180: 0f034407 movi v7.2s, #0x60, lsl #16
+ 5184: 0f034427 movi v7.2s, #0x61, lsl #16
+ 5188: 0f034447 movi v7.2s, #0x62, lsl #16
+ 518c: 0f034467 movi v7.2s, #0x63, lsl #16
+ 5190: 0f034487 movi v7.2s, #0x64, lsl #16
+ 5194: 0f0344a7 movi v7.2s, #0x65, lsl #16
+ 5198: 0f0344c7 movi v7.2s, #0x66, lsl #16
+ 519c: 0f0344e7 movi v7.2s, #0x67, lsl #16
+ 51a0: 0f034507 movi v7.2s, #0x68, lsl #16
+ 51a4: 0f034527 movi v7.2s, #0x69, lsl #16
+ 51a8: 0f034547 movi v7.2s, #0x6a, lsl #16
+ 51ac: 0f034567 movi v7.2s, #0x6b, lsl #16
+ 51b0: 0f034587 movi v7.2s, #0x6c, lsl #16
+ 51b4: 0f0345a7 movi v7.2s, #0x6d, lsl #16
+ 51b8: 0f0345c7 movi v7.2s, #0x6e, lsl #16
+ 51bc: 0f0345e7 movi v7.2s, #0x6f, lsl #16
+ 51c0: 0f034607 movi v7.2s, #0x70, lsl #16
+ 51c4: 0f034627 movi v7.2s, #0x71, lsl #16
+ 51c8: 0f034647 movi v7.2s, #0x72, lsl #16
+ 51cc: 0f034667 movi v7.2s, #0x73, lsl #16
+ 51d0: 0f034687 movi v7.2s, #0x74, lsl #16
+ 51d4: 0f0346a7 movi v7.2s, #0x75, lsl #16
+ 51d8: 0f0346c7 movi v7.2s, #0x76, lsl #16
+ 51dc: 0f0346e7 movi v7.2s, #0x77, lsl #16
+ 51e0: 0f034707 movi v7.2s, #0x78, lsl #16
+ 51e4: 0f034727 movi v7.2s, #0x79, lsl #16
+ 51e8: 0f034747 movi v7.2s, #0x7a, lsl #16
+ 51ec: 0f034767 movi v7.2s, #0x7b, lsl #16
+ 51f0: 0f034787 movi v7.2s, #0x7c, lsl #16
+ 51f4: 0f0347a7 movi v7.2s, #0x7d, lsl #16
+ 51f8: 0f0347c7 movi v7.2s, #0x7e, lsl #16
+ 51fc: 0f0347e7 movi v7.2s, #0x7f, lsl #16
+ 5200: 0f044407 movi v7.2s, #0x80, lsl #16
+ 5204: 0f044427 movi v7.2s, #0x81, lsl #16
+ 5208: 0f044447 movi v7.2s, #0x82, lsl #16
+ 520c: 0f044467 movi v7.2s, #0x83, lsl #16
+ 5210: 0f044487 movi v7.2s, #0x84, lsl #16
+ 5214: 0f0444a7 movi v7.2s, #0x85, lsl #16
+ 5218: 0f0444c7 movi v7.2s, #0x86, lsl #16
+ 521c: 0f0444e7 movi v7.2s, #0x87, lsl #16
+ 5220: 0f044507 movi v7.2s, #0x88, lsl #16
+ 5224: 0f044527 movi v7.2s, #0x89, lsl #16
+ 5228: 0f044547 movi v7.2s, #0x8a, lsl #16
+ 522c: 0f044567 movi v7.2s, #0x8b, lsl #16
+ 5230: 0f044587 movi v7.2s, #0x8c, lsl #16
+ 5234: 0f0445a7 movi v7.2s, #0x8d, lsl #16
+ 5238: 0f0445c7 movi v7.2s, #0x8e, lsl #16
+ 523c: 0f0445e7 movi v7.2s, #0x8f, lsl #16
+ 5240: 0f044607 movi v7.2s, #0x90, lsl #16
+ 5244: 0f044627 movi v7.2s, #0x91, lsl #16
+ 5248: 0f044647 movi v7.2s, #0x92, lsl #16
+ 524c: 0f044667 movi v7.2s, #0x93, lsl #16
+ 5250: 0f044687 movi v7.2s, #0x94, lsl #16
+ 5254: 0f0446a7 movi v7.2s, #0x95, lsl #16
+ 5258: 0f0446c7 movi v7.2s, #0x96, lsl #16
+ 525c: 0f0446e7 movi v7.2s, #0x97, lsl #16
+ 5260: 0f044707 movi v7.2s, #0x98, lsl #16
+ 5264: 0f044727 movi v7.2s, #0x99, lsl #16
+ 5268: 0f044747 movi v7.2s, #0x9a, lsl #16
+ 526c: 0f044767 movi v7.2s, #0x9b, lsl #16
+ 5270: 0f044787 movi v7.2s, #0x9c, lsl #16
+ 5274: 0f0447a7 movi v7.2s, #0x9d, lsl #16
+ 5278: 0f0447c7 movi v7.2s, #0x9e, lsl #16
+ 527c: 0f0447e7 movi v7.2s, #0x9f, lsl #16
+ 5280: 0f054407 movi v7.2s, #0xa0, lsl #16
+ 5284: 0f054427 movi v7.2s, #0xa1, lsl #16
+ 5288: 0f054447 movi v7.2s, #0xa2, lsl #16
+ 528c: 0f054467 movi v7.2s, #0xa3, lsl #16
+ 5290: 0f054487 movi v7.2s, #0xa4, lsl #16
+ 5294: 0f0544a7 movi v7.2s, #0xa5, lsl #16
+ 5298: 0f0544c7 movi v7.2s, #0xa6, lsl #16
+ 529c: 0f0544e7 movi v7.2s, #0xa7, lsl #16
+ 52a0: 0f054507 movi v7.2s, #0xa8, lsl #16
+ 52a4: 0f054527 movi v7.2s, #0xa9, lsl #16
+ 52a8: 0f054547 movi v7.2s, #0xaa, lsl #16
+ 52ac: 0f054567 movi v7.2s, #0xab, lsl #16
+ 52b0: 0f054587 movi v7.2s, #0xac, lsl #16
+ 52b4: 0f0545a7 movi v7.2s, #0xad, lsl #16
+ 52b8: 0f0545c7 movi v7.2s, #0xae, lsl #16
+ 52bc: 0f0545e7 movi v7.2s, #0xaf, lsl #16
+ 52c0: 0f054607 movi v7.2s, #0xb0, lsl #16
+ 52c4: 0f054627 movi v7.2s, #0xb1, lsl #16
+ 52c8: 0f054647 movi v7.2s, #0xb2, lsl #16
+ 52cc: 0f054667 movi v7.2s, #0xb3, lsl #16
+ 52d0: 0f054687 movi v7.2s, #0xb4, lsl #16
+ 52d4: 0f0546a7 movi v7.2s, #0xb5, lsl #16
+ 52d8: 0f0546c7 movi v7.2s, #0xb6, lsl #16
+ 52dc: 0f0546e7 movi v7.2s, #0xb7, lsl #16
+ 52e0: 0f054707 movi v7.2s, #0xb8, lsl #16
+ 52e4: 0f054727 movi v7.2s, #0xb9, lsl #16
+ 52e8: 0f054747 movi v7.2s, #0xba, lsl #16
+ 52ec: 0f054767 movi v7.2s, #0xbb, lsl #16
+ 52f0: 0f054787 movi v7.2s, #0xbc, lsl #16
+ 52f4: 0f0547a7 movi v7.2s, #0xbd, lsl #16
+ 52f8: 0f0547c7 movi v7.2s, #0xbe, lsl #16
+ 52fc: 0f0547e7 movi v7.2s, #0xbf, lsl #16
+ 5300: 0f064407 movi v7.2s, #0xc0, lsl #16
+ 5304: 0f064427 movi v7.2s, #0xc1, lsl #16
+ 5308: 0f064447 movi v7.2s, #0xc2, lsl #16
+ 530c: 0f064467 movi v7.2s, #0xc3, lsl #16
+ 5310: 0f064487 movi v7.2s, #0xc4, lsl #16
+ 5314: 0f0644a7 movi v7.2s, #0xc5, lsl #16
+ 5318: 0f0644c7 movi v7.2s, #0xc6, lsl #16
+ 531c: 0f0644e7 movi v7.2s, #0xc7, lsl #16
+ 5320: 0f064507 movi v7.2s, #0xc8, lsl #16
+ 5324: 0f064527 movi v7.2s, #0xc9, lsl #16
+ 5328: 0f064547 movi v7.2s, #0xca, lsl #16
+ 532c: 0f064567 movi v7.2s, #0xcb, lsl #16
+ 5330: 0f064587 movi v7.2s, #0xcc, lsl #16
+ 5334: 0f0645a7 movi v7.2s, #0xcd, lsl #16
+ 5338: 0f0645c7 movi v7.2s, #0xce, lsl #16
+ 533c: 0f0645e7 movi v7.2s, #0xcf, lsl #16
+ 5340: 0f064607 movi v7.2s, #0xd0, lsl #16
+ 5344: 0f064627 movi v7.2s, #0xd1, lsl #16
+ 5348: 0f064647 movi v7.2s, #0xd2, lsl #16
+ 534c: 0f064667 movi v7.2s, #0xd3, lsl #16
+ 5350: 0f064687 movi v7.2s, #0xd4, lsl #16
+ 5354: 0f0646a7 movi v7.2s, #0xd5, lsl #16
+ 5358: 0f0646c7 movi v7.2s, #0xd6, lsl #16
+ 535c: 0f0646e7 movi v7.2s, #0xd7, lsl #16
+ 5360: 0f064707 movi v7.2s, #0xd8, lsl #16
+ 5364: 0f064727 movi v7.2s, #0xd9, lsl #16
+ 5368: 0f064747 movi v7.2s, #0xda, lsl #16
+ 536c: 0f064767 movi v7.2s, #0xdb, lsl #16
+ 5370: 0f064787 movi v7.2s, #0xdc, lsl #16
+ 5374: 0f0647a7 movi v7.2s, #0xdd, lsl #16
+ 5378: 0f0647c7 movi v7.2s, #0xde, lsl #16
+ 537c: 0f0647e7 movi v7.2s, #0xdf, lsl #16
+ 5380: 0f074407 movi v7.2s, #0xe0, lsl #16
+ 5384: 0f074427 movi v7.2s, #0xe1, lsl #16
+ 5388: 0f074447 movi v7.2s, #0xe2, lsl #16
+ 538c: 0f074467 movi v7.2s, #0xe3, lsl #16
+ 5390: 0f074487 movi v7.2s, #0xe4, lsl #16
+ 5394: 0f0744a7 movi v7.2s, #0xe5, lsl #16
+ 5398: 0f0744c7 movi v7.2s, #0xe6, lsl #16
+ 539c: 0f0744e7 movi v7.2s, #0xe7, lsl #16
+ 53a0: 0f074507 movi v7.2s, #0xe8, lsl #16
+ 53a4: 0f074527 movi v7.2s, #0xe9, lsl #16
+ 53a8: 0f074547 movi v7.2s, #0xea, lsl #16
+ 53ac: 0f074567 movi v7.2s, #0xeb, lsl #16
+ 53b0: 0f074587 movi v7.2s, #0xec, lsl #16
+ 53b4: 0f0745a7 movi v7.2s, #0xed, lsl #16
+ 53b8: 0f0745c7 movi v7.2s, #0xee, lsl #16
+ 53bc: 0f0745e7 movi v7.2s, #0xef, lsl #16
+ 53c0: 0f074607 movi v7.2s, #0xf0, lsl #16
+ 53c4: 0f074627 movi v7.2s, #0xf1, lsl #16
+ 53c8: 0f074647 movi v7.2s, #0xf2, lsl #16
+ 53cc: 0f074667 movi v7.2s, #0xf3, lsl #16
+ 53d0: 0f074687 movi v7.2s, #0xf4, lsl #16
+ 53d4: 0f0746a7 movi v7.2s, #0xf5, lsl #16
+ 53d8: 0f0746c7 movi v7.2s, #0xf6, lsl #16
+ 53dc: 0f0746e7 movi v7.2s, #0xf7, lsl #16
+ 53e0: 0f074707 movi v7.2s, #0xf8, lsl #16
+ 53e4: 0f074727 movi v7.2s, #0xf9, lsl #16
+ 53e8: 0f074747 movi v7.2s, #0xfa, lsl #16
+ 53ec: 0f074767 movi v7.2s, #0xfb, lsl #16
+ 53f0: 0f074787 movi v7.2s, #0xfc, lsl #16
+ 53f4: 0f0747a7 movi v7.2s, #0xfd, lsl #16
+ 53f8: 0f0747c7 movi v7.2s, #0xfe, lsl #16
+ 53fc: 0f0747e7 movi v7.2s, #0xff, lsl #16
+ 5400: 0f00040f movi v15.2s, #0x0
+ 5404: 0f00042f movi v15.2s, #0x1
+ 5408: 0f00044f movi v15.2s, #0x2
+ 540c: 0f00046f movi v15.2s, #0x3
+ 5410: 0f00048f movi v15.2s, #0x4
+ 5414: 0f0004af movi v15.2s, #0x5
+ 5418: 0f0004cf movi v15.2s, #0x6
+ 541c: 0f0004ef movi v15.2s, #0x7
+ 5420: 0f00050f movi v15.2s, #0x8
+ 5424: 0f00052f movi v15.2s, #0x9
+ 5428: 0f00054f movi v15.2s, #0xa
+ 542c: 0f00056f movi v15.2s, #0xb
+ 5430: 0f00058f movi v15.2s, #0xc
+ 5434: 0f0005af movi v15.2s, #0xd
+ 5438: 0f0005cf movi v15.2s, #0xe
+ 543c: 0f0005ef movi v15.2s, #0xf
+ 5440: 0f00060f movi v15.2s, #0x10
+ 5444: 0f00062f movi v15.2s, #0x11
+ 5448: 0f00064f movi v15.2s, #0x12
+ 544c: 0f00066f movi v15.2s, #0x13
+ 5450: 0f00068f movi v15.2s, #0x14
+ 5454: 0f0006af movi v15.2s, #0x15
+ 5458: 0f0006cf movi v15.2s, #0x16
+ 545c: 0f0006ef movi v15.2s, #0x17
+ 5460: 0f00070f movi v15.2s, #0x18
+ 5464: 0f00072f movi v15.2s, #0x19
+ 5468: 0f00074f movi v15.2s, #0x1a
+ 546c: 0f00076f movi v15.2s, #0x1b
+ 5470: 0f00078f movi v15.2s, #0x1c
+ 5474: 0f0007af movi v15.2s, #0x1d
+ 5478: 0f0007cf movi v15.2s, #0x1e
+ 547c: 0f0007ef movi v15.2s, #0x1f
+ 5480: 0f01040f movi v15.2s, #0x20
+ 5484: 0f01042f movi v15.2s, #0x21
+ 5488: 0f01044f movi v15.2s, #0x22
+ 548c: 0f01046f movi v15.2s, #0x23
+ 5490: 0f01048f movi v15.2s, #0x24
+ 5494: 0f0104af movi v15.2s, #0x25
+ 5498: 0f0104cf movi v15.2s, #0x26
+ 549c: 0f0104ef movi v15.2s, #0x27
+ 54a0: 0f01050f movi v15.2s, #0x28
+ 54a4: 0f01052f movi v15.2s, #0x29
+ 54a8: 0f01054f movi v15.2s, #0x2a
+ 54ac: 0f01056f movi v15.2s, #0x2b
+ 54b0: 0f01058f movi v15.2s, #0x2c
+ 54b4: 0f0105af movi v15.2s, #0x2d
+ 54b8: 0f0105cf movi v15.2s, #0x2e
+ 54bc: 0f0105ef movi v15.2s, #0x2f
+ 54c0: 0f01060f movi v15.2s, #0x30
+ 54c4: 0f01062f movi v15.2s, #0x31
+ 54c8: 0f01064f movi v15.2s, #0x32
+ 54cc: 0f01066f movi v15.2s, #0x33
+ 54d0: 0f01068f movi v15.2s, #0x34
+ 54d4: 0f0106af movi v15.2s, #0x35
+ 54d8: 0f0106cf movi v15.2s, #0x36
+ 54dc: 0f0106ef movi v15.2s, #0x37
+ 54e0: 0f01070f movi v15.2s, #0x38
+ 54e4: 0f01072f movi v15.2s, #0x39
+ 54e8: 0f01074f movi v15.2s, #0x3a
+ 54ec: 0f01076f movi v15.2s, #0x3b
+ 54f0: 0f01078f movi v15.2s, #0x3c
+ 54f4: 0f0107af movi v15.2s, #0x3d
+ 54f8: 0f0107cf movi v15.2s, #0x3e
+ 54fc: 0f0107ef movi v15.2s, #0x3f
+ 5500: 0f02040f movi v15.2s, #0x40
+ 5504: 0f02042f movi v15.2s, #0x41
+ 5508: 0f02044f movi v15.2s, #0x42
+ 550c: 0f02046f movi v15.2s, #0x43
+ 5510: 0f02048f movi v15.2s, #0x44
+ 5514: 0f0204af movi v15.2s, #0x45
+ 5518: 0f0204cf movi v15.2s, #0x46
+ 551c: 0f0204ef movi v15.2s, #0x47
+ 5520: 0f02050f movi v15.2s, #0x48
+ 5524: 0f02052f movi v15.2s, #0x49
+ 5528: 0f02054f movi v15.2s, #0x4a
+ 552c: 0f02056f movi v15.2s, #0x4b
+ 5530: 0f02058f movi v15.2s, #0x4c
+ 5534: 0f0205af movi v15.2s, #0x4d
+ 5538: 0f0205cf movi v15.2s, #0x4e
+ 553c: 0f0205ef movi v15.2s, #0x4f
+ 5540: 0f02060f movi v15.2s, #0x50
+ 5544: 0f02062f movi v15.2s, #0x51
+ 5548: 0f02064f movi v15.2s, #0x52
+ 554c: 0f02066f movi v15.2s, #0x53
+ 5550: 0f02068f movi v15.2s, #0x54
+ 5554: 0f0206af movi v15.2s, #0x55
+ 5558: 0f0206cf movi v15.2s, #0x56
+ 555c: 0f0206ef movi v15.2s, #0x57
+ 5560: 0f02070f movi v15.2s, #0x58
+ 5564: 0f02072f movi v15.2s, #0x59
+ 5568: 0f02074f movi v15.2s, #0x5a
+ 556c: 0f02076f movi v15.2s, #0x5b
+ 5570: 0f02078f movi v15.2s, #0x5c
+ 5574: 0f0207af movi v15.2s, #0x5d
+ 5578: 0f0207cf movi v15.2s, #0x5e
+ 557c: 0f0207ef movi v15.2s, #0x5f
+ 5580: 0f03040f movi v15.2s, #0x60
+ 5584: 0f03042f movi v15.2s, #0x61
+ 5588: 0f03044f movi v15.2s, #0x62
+ 558c: 0f03046f movi v15.2s, #0x63
+ 5590: 0f03048f movi v15.2s, #0x64
+ 5594: 0f0304af movi v15.2s, #0x65
+ 5598: 0f0304cf movi v15.2s, #0x66
+ 559c: 0f0304ef movi v15.2s, #0x67
+ 55a0: 0f03050f movi v15.2s, #0x68
+ 55a4: 0f03052f movi v15.2s, #0x69
+ 55a8: 0f03054f movi v15.2s, #0x6a
+ 55ac: 0f03056f movi v15.2s, #0x6b
+ 55b0: 0f03058f movi v15.2s, #0x6c
+ 55b4: 0f0305af movi v15.2s, #0x6d
+ 55b8: 0f0305cf movi v15.2s, #0x6e
+ 55bc: 0f0305ef movi v15.2s, #0x6f
+ 55c0: 0f03060f movi v15.2s, #0x70
+ 55c4: 0f03062f movi v15.2s, #0x71
+ 55c8: 0f03064f movi v15.2s, #0x72
+ 55cc: 0f03066f movi v15.2s, #0x73
+ 55d0: 0f03068f movi v15.2s, #0x74
+ 55d4: 0f0306af movi v15.2s, #0x75
+ 55d8: 0f0306cf movi v15.2s, #0x76
+ 55dc: 0f0306ef movi v15.2s, #0x77
+ 55e0: 0f03070f movi v15.2s, #0x78
+ 55e4: 0f03072f movi v15.2s, #0x79
+ 55e8: 0f03074f movi v15.2s, #0x7a
+ 55ec: 0f03076f movi v15.2s, #0x7b
+ 55f0: 0f03078f movi v15.2s, #0x7c
+ 55f4: 0f0307af movi v15.2s, #0x7d
+ 55f8: 0f0307cf movi v15.2s, #0x7e
+ 55fc: 0f0307ef movi v15.2s, #0x7f
+ 5600: 0f04040f movi v15.2s, #0x80
+ 5604: 0f04042f movi v15.2s, #0x81
+ 5608: 0f04044f movi v15.2s, #0x82
+ 560c: 0f04046f movi v15.2s, #0x83
+ 5610: 0f04048f movi v15.2s, #0x84
+ 5614: 0f0404af movi v15.2s, #0x85
+ 5618: 0f0404cf movi v15.2s, #0x86
+ 561c: 0f0404ef movi v15.2s, #0x87
+ 5620: 0f04050f movi v15.2s, #0x88
+ 5624: 0f04052f movi v15.2s, #0x89
+ 5628: 0f04054f movi v15.2s, #0x8a
+ 562c: 0f04056f movi v15.2s, #0x8b
+ 5630: 0f04058f movi v15.2s, #0x8c
+ 5634: 0f0405af movi v15.2s, #0x8d
+ 5638: 0f0405cf movi v15.2s, #0x8e
+ 563c: 0f0405ef movi v15.2s, #0x8f
+ 5640: 0f04060f movi v15.2s, #0x90
+ 5644: 0f04062f movi v15.2s, #0x91
+ 5648: 0f04064f movi v15.2s, #0x92
+ 564c: 0f04066f movi v15.2s, #0x93
+ 5650: 0f04068f movi v15.2s, #0x94
+ 5654: 0f0406af movi v15.2s, #0x95
+ 5658: 0f0406cf movi v15.2s, #0x96
+ 565c: 0f0406ef movi v15.2s, #0x97
+ 5660: 0f04070f movi v15.2s, #0x98
+ 5664: 0f04072f movi v15.2s, #0x99
+ 5668: 0f04074f movi v15.2s, #0x9a
+ 566c: 0f04076f movi v15.2s, #0x9b
+ 5670: 0f04078f movi v15.2s, #0x9c
+ 5674: 0f0407af movi v15.2s, #0x9d
+ 5678: 0f0407cf movi v15.2s, #0x9e
+ 567c: 0f0407ef movi v15.2s, #0x9f
+ 5680: 0f05040f movi v15.2s, #0xa0
+ 5684: 0f05042f movi v15.2s, #0xa1
+ 5688: 0f05044f movi v15.2s, #0xa2
+ 568c: 0f05046f movi v15.2s, #0xa3
+ 5690: 0f05048f movi v15.2s, #0xa4
+ 5694: 0f0504af movi v15.2s, #0xa5
+ 5698: 0f0504cf movi v15.2s, #0xa6
+ 569c: 0f0504ef movi v15.2s, #0xa7
+ 56a0: 0f05050f movi v15.2s, #0xa8
+ 56a4: 0f05052f movi v15.2s, #0xa9
+ 56a8: 0f05054f movi v15.2s, #0xaa
+ 56ac: 0f05056f movi v15.2s, #0xab
+ 56b0: 0f05058f movi v15.2s, #0xac
+ 56b4: 0f0505af movi v15.2s, #0xad
+ 56b8: 0f0505cf movi v15.2s, #0xae
+ 56bc: 0f0505ef movi v15.2s, #0xaf
+ 56c0: 0f05060f movi v15.2s, #0xb0
+ 56c4: 0f05062f movi v15.2s, #0xb1
+ 56c8: 0f05064f movi v15.2s, #0xb2
+ 56cc: 0f05066f movi v15.2s, #0xb3
+ 56d0: 0f05068f movi v15.2s, #0xb4
+ 56d4: 0f0506af movi v15.2s, #0xb5
+ 56d8: 0f0506cf movi v15.2s, #0xb6
+ 56dc: 0f0506ef movi v15.2s, #0xb7
+ 56e0: 0f05070f movi v15.2s, #0xb8
+ 56e4: 0f05072f movi v15.2s, #0xb9
+ 56e8: 0f05074f movi v15.2s, #0xba
+ 56ec: 0f05076f movi v15.2s, #0xbb
+ 56f0: 0f05078f movi v15.2s, #0xbc
+ 56f4: 0f0507af movi v15.2s, #0xbd
+ 56f8: 0f0507cf movi v15.2s, #0xbe
+ 56fc: 0f0507ef movi v15.2s, #0xbf
+ 5700: 0f06040f movi v15.2s, #0xc0
+ 5704: 0f06042f movi v15.2s, #0xc1
+ 5708: 0f06044f movi v15.2s, #0xc2
+ 570c: 0f06046f movi v15.2s, #0xc3
+ 5710: 0f06048f movi v15.2s, #0xc4
+ 5714: 0f0604af movi v15.2s, #0xc5
+ 5718: 0f0604cf movi v15.2s, #0xc6
+ 571c: 0f0604ef movi v15.2s, #0xc7
+ 5720: 0f06050f movi v15.2s, #0xc8
+ 5724: 0f06052f movi v15.2s, #0xc9
+ 5728: 0f06054f movi v15.2s, #0xca
+ 572c: 0f06056f movi v15.2s, #0xcb
+ 5730: 0f06058f movi v15.2s, #0xcc
+ 5734: 0f0605af movi v15.2s, #0xcd
+ 5738: 0f0605cf movi v15.2s, #0xce
+ 573c: 0f0605ef movi v15.2s, #0xcf
+ 5740: 0f06060f movi v15.2s, #0xd0
+ 5744: 0f06062f movi v15.2s, #0xd1
+ 5748: 0f06064f movi v15.2s, #0xd2
+ 574c: 0f06066f movi v15.2s, #0xd3
+ 5750: 0f06068f movi v15.2s, #0xd4
+ 5754: 0f0606af movi v15.2s, #0xd5
+ 5758: 0f0606cf movi v15.2s, #0xd6
+ 575c: 0f0606ef movi v15.2s, #0xd7
+ 5760: 0f06070f movi v15.2s, #0xd8
+ 5764: 0f06072f movi v15.2s, #0xd9
+ 5768: 0f06074f movi v15.2s, #0xda
+ 576c: 0f06076f movi v15.2s, #0xdb
+ 5770: 0f06078f movi v15.2s, #0xdc
+ 5774: 0f0607af movi v15.2s, #0xdd
+ 5778: 0f0607cf movi v15.2s, #0xde
+ 577c: 0f0607ef movi v15.2s, #0xdf
+ 5780: 0f07040f movi v15.2s, #0xe0
+ 5784: 0f07042f movi v15.2s, #0xe1
+ 5788: 0f07044f movi v15.2s, #0xe2
+ 578c: 0f07046f movi v15.2s, #0xe3
+ 5790: 0f07048f movi v15.2s, #0xe4
+ 5794: 0f0704af movi v15.2s, #0xe5
+ 5798: 0f0704cf movi v15.2s, #0xe6
+ 579c: 0f0704ef movi v15.2s, #0xe7
+ 57a0: 0f07050f movi v15.2s, #0xe8
+ 57a4: 0f07052f movi v15.2s, #0xe9
+ 57a8: 0f07054f movi v15.2s, #0xea
+ 57ac: 0f07056f movi v15.2s, #0xeb
+ 57b0: 0f07058f movi v15.2s, #0xec
+ 57b4: 0f0705af movi v15.2s, #0xed
+ 57b8: 0f0705cf movi v15.2s, #0xee
+ 57bc: 0f0705ef movi v15.2s, #0xef
+ 57c0: 0f07060f movi v15.2s, #0xf0
+ 57c4: 0f07062f movi v15.2s, #0xf1
+ 57c8: 0f07064f movi v15.2s, #0xf2
+ 57cc: 0f07066f movi v15.2s, #0xf3
+ 57d0: 0f07068f movi v15.2s, #0xf4
+ 57d4: 0f0706af movi v15.2s, #0xf5
+ 57d8: 0f0706cf movi v15.2s, #0xf6
+ 57dc: 0f0706ef movi v15.2s, #0xf7
+ 57e0: 0f07070f movi v15.2s, #0xf8
+ 57e4: 0f07072f movi v15.2s, #0xf9
+ 57e8: 0f07074f movi v15.2s, #0xfa
+ 57ec: 0f07076f movi v15.2s, #0xfb
+ 57f0: 0f07078f movi v15.2s, #0xfc
+ 57f4: 0f0707af movi v15.2s, #0xfd
+ 57f8: 0f0707cf movi v15.2s, #0xfe
+ 57fc: 0f0707ef movi v15.2s, #0xff
+ 5800: 0f006407 movi v7.2s, #0x0, lsl #24
+ 5804: 0f006427 movi v7.2s, #0x1, lsl #24
+ 5808: 0f006447 movi v7.2s, #0x2, lsl #24
+ 580c: 0f006467 movi v7.2s, #0x3, lsl #24
+ 5810: 0f006487 movi v7.2s, #0x4, lsl #24
+ 5814: 0f0064a7 movi v7.2s, #0x5, lsl #24
+ 5818: 0f0064c7 movi v7.2s, #0x6, lsl #24
+ 581c: 0f0064e7 movi v7.2s, #0x7, lsl #24
+ 5820: 0f006507 movi v7.2s, #0x8, lsl #24
+ 5824: 0f006527 movi v7.2s, #0x9, lsl #24
+ 5828: 0f006547 movi v7.2s, #0xa, lsl #24
+ 582c: 0f006567 movi v7.2s, #0xb, lsl #24
+ 5830: 0f006587 movi v7.2s, #0xc, lsl #24
+ 5834: 0f0065a7 movi v7.2s, #0xd, lsl #24
+ 5838: 0f0065c7 movi v7.2s, #0xe, lsl #24
+ 583c: 0f0065e7 movi v7.2s, #0xf, lsl #24
+ 5840: 0f006607 movi v7.2s, #0x10, lsl #24
+ 5844: 0f006627 movi v7.2s, #0x11, lsl #24
+ 5848: 0f006647 movi v7.2s, #0x12, lsl #24
+ 584c: 0f006667 movi v7.2s, #0x13, lsl #24
+ 5850: 0f006687 movi v7.2s, #0x14, lsl #24
+ 5854: 0f0066a7 movi v7.2s, #0x15, lsl #24
+ 5858: 0f0066c7 movi v7.2s, #0x16, lsl #24
+ 585c: 0f0066e7 movi v7.2s, #0x17, lsl #24
+ 5860: 0f006707 movi v7.2s, #0x18, lsl #24
+ 5864: 0f006727 movi v7.2s, #0x19, lsl #24
+ 5868: 0f006747 movi v7.2s, #0x1a, lsl #24
+ 586c: 0f006767 movi v7.2s, #0x1b, lsl #24
+ 5870: 0f006787 movi v7.2s, #0x1c, lsl #24
+ 5874: 0f0067a7 movi v7.2s, #0x1d, lsl #24
+ 5878: 0f0067c7 movi v7.2s, #0x1e, lsl #24
+ 587c: 0f0067e7 movi v7.2s, #0x1f, lsl #24
+ 5880: 0f016407 movi v7.2s, #0x20, lsl #24
+ 5884: 0f016427 movi v7.2s, #0x21, lsl #24
+ 5888: 0f016447 movi v7.2s, #0x22, lsl #24
+ 588c: 0f016467 movi v7.2s, #0x23, lsl #24
+ 5890: 0f016487 movi v7.2s, #0x24, lsl #24
+ 5894: 0f0164a7 movi v7.2s, #0x25, lsl #24
+ 5898: 0f0164c7 movi v7.2s, #0x26, lsl #24
+ 589c: 0f0164e7 movi v7.2s, #0x27, lsl #24
+ 58a0: 0f016507 movi v7.2s, #0x28, lsl #24
+ 58a4: 0f016527 movi v7.2s, #0x29, lsl #24
+ 58a8: 0f016547 movi v7.2s, #0x2a, lsl #24
+ 58ac: 0f016567 movi v7.2s, #0x2b, lsl #24
+ 58b0: 0f016587 movi v7.2s, #0x2c, lsl #24
+ 58b4: 0f0165a7 movi v7.2s, #0x2d, lsl #24
+ 58b8: 0f0165c7 movi v7.2s, #0x2e, lsl #24
+ 58bc: 0f0165e7 movi v7.2s, #0x2f, lsl #24
+ 58c0: 0f016607 movi v7.2s, #0x30, lsl #24
+ 58c4: 0f016627 movi v7.2s, #0x31, lsl #24
+ 58c8: 0f016647 movi v7.2s, #0x32, lsl #24
+ 58cc: 0f016667 movi v7.2s, #0x33, lsl #24
+ 58d0: 0f016687 movi v7.2s, #0x34, lsl #24
+ 58d4: 0f0166a7 movi v7.2s, #0x35, lsl #24
+ 58d8: 0f0166c7 movi v7.2s, #0x36, lsl #24
+ 58dc: 0f0166e7 movi v7.2s, #0x37, lsl #24
+ 58e0: 0f016707 movi v7.2s, #0x38, lsl #24
+ 58e4: 0f016727 movi v7.2s, #0x39, lsl #24
+ 58e8: 0f016747 movi v7.2s, #0x3a, lsl #24
+ 58ec: 0f016767 movi v7.2s, #0x3b, lsl #24
+ 58f0: 0f016787 movi v7.2s, #0x3c, lsl #24
+ 58f4: 0f0167a7 movi v7.2s, #0x3d, lsl #24
+ 58f8: 0f0167c7 movi v7.2s, #0x3e, lsl #24
+ 58fc: 0f0167e7 movi v7.2s, #0x3f, lsl #24
+ 5900: 0f026407 movi v7.2s, #0x40, lsl #24
+ 5904: 0f026427 movi v7.2s, #0x41, lsl #24
+ 5908: 0f026447 movi v7.2s, #0x42, lsl #24
+ 590c: 0f026467 movi v7.2s, #0x43, lsl #24
+ 5910: 0f026487 movi v7.2s, #0x44, lsl #24
+ 5914: 0f0264a7 movi v7.2s, #0x45, lsl #24
+ 5918: 0f0264c7 movi v7.2s, #0x46, lsl #24
+ 591c: 0f0264e7 movi v7.2s, #0x47, lsl #24
+ 5920: 0f026507 movi v7.2s, #0x48, lsl #24
+ 5924: 0f026527 movi v7.2s, #0x49, lsl #24
+ 5928: 0f026547 movi v7.2s, #0x4a, lsl #24
+ 592c: 0f026567 movi v7.2s, #0x4b, lsl #24
+ 5930: 0f026587 movi v7.2s, #0x4c, lsl #24
+ 5934: 0f0265a7 movi v7.2s, #0x4d, lsl #24
+ 5938: 0f0265c7 movi v7.2s, #0x4e, lsl #24
+ 593c: 0f0265e7 movi v7.2s, #0x4f, lsl #24
+ 5940: 0f026607 movi v7.2s, #0x50, lsl #24
+ 5944: 0f026627 movi v7.2s, #0x51, lsl #24
+ 5948: 0f026647 movi v7.2s, #0x52, lsl #24
+ 594c: 0f026667 movi v7.2s, #0x53, lsl #24
+ 5950: 0f026687 movi v7.2s, #0x54, lsl #24
+ 5954: 0f0266a7 movi v7.2s, #0x55, lsl #24
+ 5958: 0f0266c7 movi v7.2s, #0x56, lsl #24
+ 595c: 0f0266e7 movi v7.2s, #0x57, lsl #24
+ 5960: 0f026707 movi v7.2s, #0x58, lsl #24
+ 5964: 0f026727 movi v7.2s, #0x59, lsl #24
+ 5968: 0f026747 movi v7.2s, #0x5a, lsl #24
+ 596c: 0f026767 movi v7.2s, #0x5b, lsl #24
+ 5970: 0f026787 movi v7.2s, #0x5c, lsl #24
+ 5974: 0f0267a7 movi v7.2s, #0x5d, lsl #24
+ 5978: 0f0267c7 movi v7.2s, #0x5e, lsl #24
+ 597c: 0f0267e7 movi v7.2s, #0x5f, lsl #24
+ 5980: 0f036407 movi v7.2s, #0x60, lsl #24
+ 5984: 0f036427 movi v7.2s, #0x61, lsl #24
+ 5988: 0f036447 movi v7.2s, #0x62, lsl #24
+ 598c: 0f036467 movi v7.2s, #0x63, lsl #24
+ 5990: 0f036487 movi v7.2s, #0x64, lsl #24
+ 5994: 0f0364a7 movi v7.2s, #0x65, lsl #24
+ 5998: 0f0364c7 movi v7.2s, #0x66, lsl #24
+ 599c: 0f0364e7 movi v7.2s, #0x67, lsl #24
+ 59a0: 0f036507 movi v7.2s, #0x68, lsl #24
+ 59a4: 0f036527 movi v7.2s, #0x69, lsl #24
+ 59a8: 0f036547 movi v7.2s, #0x6a, lsl #24
+ 59ac: 0f036567 movi v7.2s, #0x6b, lsl #24
+ 59b0: 0f036587 movi v7.2s, #0x6c, lsl #24
+ 59b4: 0f0365a7 movi v7.2s, #0x6d, lsl #24
+ 59b8: 0f0365c7 movi v7.2s, #0x6e, lsl #24
+ 59bc: 0f0365e7 movi v7.2s, #0x6f, lsl #24
+ 59c0: 0f036607 movi v7.2s, #0x70, lsl #24
+ 59c4: 0f036627 movi v7.2s, #0x71, lsl #24
+ 59c8: 0f036647 movi v7.2s, #0x72, lsl #24
+ 59cc: 0f036667 movi v7.2s, #0x73, lsl #24
+ 59d0: 0f036687 movi v7.2s, #0x74, lsl #24
+ 59d4: 0f0366a7 movi v7.2s, #0x75, lsl #24
+ 59d8: 0f0366c7 movi v7.2s, #0x76, lsl #24
+ 59dc: 0f0366e7 movi v7.2s, #0x77, lsl #24
+ 59e0: 0f036707 movi v7.2s, #0x78, lsl #24
+ 59e4: 0f036727 movi v7.2s, #0x79, lsl #24
+ 59e8: 0f036747 movi v7.2s, #0x7a, lsl #24
+ 59ec: 0f036767 movi v7.2s, #0x7b, lsl #24
+ 59f0: 0f036787 movi v7.2s, #0x7c, lsl #24
+ 59f4: 0f0367a7 movi v7.2s, #0x7d, lsl #24
+ 59f8: 0f0367c7 movi v7.2s, #0x7e, lsl #24
+ 59fc: 0f0367e7 movi v7.2s, #0x7f, lsl #24
+ 5a00: 0f046407 movi v7.2s, #0x80, lsl #24
+ 5a04: 0f046427 movi v7.2s, #0x81, lsl #24
+ 5a08: 0f046447 movi v7.2s, #0x82, lsl #24
+ 5a0c: 0f046467 movi v7.2s, #0x83, lsl #24
+ 5a10: 0f046487 movi v7.2s, #0x84, lsl #24
+ 5a14: 0f0464a7 movi v7.2s, #0x85, lsl #24
+ 5a18: 0f0464c7 movi v7.2s, #0x86, lsl #24
+ 5a1c: 0f0464e7 movi v7.2s, #0x87, lsl #24
+ 5a20: 0f046507 movi v7.2s, #0x88, lsl #24
+ 5a24: 0f046527 movi v7.2s, #0x89, lsl #24
+ 5a28: 0f046547 movi v7.2s, #0x8a, lsl #24
+ 5a2c: 0f046567 movi v7.2s, #0x8b, lsl #24
+ 5a30: 0f046587 movi v7.2s, #0x8c, lsl #24
+ 5a34: 0f0465a7 movi v7.2s, #0x8d, lsl #24
+ 5a38: 0f0465c7 movi v7.2s, #0x8e, lsl #24
+ 5a3c: 0f0465e7 movi v7.2s, #0x8f, lsl #24
+ 5a40: 0f046607 movi v7.2s, #0x90, lsl #24
+ 5a44: 0f046627 movi v7.2s, #0x91, lsl #24
+ 5a48: 0f046647 movi v7.2s, #0x92, lsl #24
+ 5a4c: 0f046667 movi v7.2s, #0x93, lsl #24
+ 5a50: 0f046687 movi v7.2s, #0x94, lsl #24
+ 5a54: 0f0466a7 movi v7.2s, #0x95, lsl #24
+ 5a58: 0f0466c7 movi v7.2s, #0x96, lsl #24
+ 5a5c: 0f0466e7 movi v7.2s, #0x97, lsl #24
+ 5a60: 0f046707 movi v7.2s, #0x98, lsl #24
+ 5a64: 0f046727 movi v7.2s, #0x99, lsl #24
+ 5a68: 0f046747 movi v7.2s, #0x9a, lsl #24
+ 5a6c: 0f046767 movi v7.2s, #0x9b, lsl #24
+ 5a70: 0f046787 movi v7.2s, #0x9c, lsl #24
+ 5a74: 0f0467a7 movi v7.2s, #0x9d, lsl #24
+ 5a78: 0f0467c7 movi v7.2s, #0x9e, lsl #24
+ 5a7c: 0f0467e7 movi v7.2s, #0x9f, lsl #24
+ 5a80: 0f056407 movi v7.2s, #0xa0, lsl #24
+ 5a84: 0f056427 movi v7.2s, #0xa1, lsl #24
+ 5a88: 0f056447 movi v7.2s, #0xa2, lsl #24
+ 5a8c: 0f056467 movi v7.2s, #0xa3, lsl #24
+ 5a90: 0f056487 movi v7.2s, #0xa4, lsl #24
+ 5a94: 0f0564a7 movi v7.2s, #0xa5, lsl #24
+ 5a98: 0f0564c7 movi v7.2s, #0xa6, lsl #24
+ 5a9c: 0f0564e7 movi v7.2s, #0xa7, lsl #24
+ 5aa0: 0f056507 movi v7.2s, #0xa8, lsl #24
+ 5aa4: 0f056527 movi v7.2s, #0xa9, lsl #24
+ 5aa8: 0f056547 movi v7.2s, #0xaa, lsl #24
+ 5aac: 0f056567 movi v7.2s, #0xab, lsl #24
+ 5ab0: 0f056587 movi v7.2s, #0xac, lsl #24
+ 5ab4: 0f0565a7 movi v7.2s, #0xad, lsl #24
+ 5ab8: 0f0565c7 movi v7.2s, #0xae, lsl #24
+ 5abc: 0f0565e7 movi v7.2s, #0xaf, lsl #24
+ 5ac0: 0f056607 movi v7.2s, #0xb0, lsl #24
+ 5ac4: 0f056627 movi v7.2s, #0xb1, lsl #24
+ 5ac8: 0f056647 movi v7.2s, #0xb2, lsl #24
+ 5acc: 0f056667 movi v7.2s, #0xb3, lsl #24
+ 5ad0: 0f056687 movi v7.2s, #0xb4, lsl #24
+ 5ad4: 0f0566a7 movi v7.2s, #0xb5, lsl #24
+ 5ad8: 0f0566c7 movi v7.2s, #0xb6, lsl #24
+ 5adc: 0f0566e7 movi v7.2s, #0xb7, lsl #24
+ 5ae0: 0f056707 movi v7.2s, #0xb8, lsl #24
+ 5ae4: 0f056727 movi v7.2s, #0xb9, lsl #24
+ 5ae8: 0f056747 movi v7.2s, #0xba, lsl #24
+ 5aec: 0f056767 movi v7.2s, #0xbb, lsl #24
+ 5af0: 0f056787 movi v7.2s, #0xbc, lsl #24
+ 5af4: 0f0567a7 movi v7.2s, #0xbd, lsl #24
+ 5af8: 0f0567c7 movi v7.2s, #0xbe, lsl #24
+ 5afc: 0f0567e7 movi v7.2s, #0xbf, lsl #24
+ 5b00: 0f066407 movi v7.2s, #0xc0, lsl #24
+ 5b04: 0f066427 movi v7.2s, #0xc1, lsl #24
+ 5b08: 0f066447 movi v7.2s, #0xc2, lsl #24
+ 5b0c: 0f066467 movi v7.2s, #0xc3, lsl #24
+ 5b10: 0f066487 movi v7.2s, #0xc4, lsl #24
+ 5b14: 0f0664a7 movi v7.2s, #0xc5, lsl #24
+ 5b18: 0f0664c7 movi v7.2s, #0xc6, lsl #24
+ 5b1c: 0f0664e7 movi v7.2s, #0xc7, lsl #24
+ 5b20: 0f066507 movi v7.2s, #0xc8, lsl #24
+ 5b24: 0f066527 movi v7.2s, #0xc9, lsl #24
+ 5b28: 0f066547 movi v7.2s, #0xca, lsl #24
+ 5b2c: 0f066567 movi v7.2s, #0xcb, lsl #24
+ 5b30: 0f066587 movi v7.2s, #0xcc, lsl #24
+ 5b34: 0f0665a7 movi v7.2s, #0xcd, lsl #24
+ 5b38: 0f0665c7 movi v7.2s, #0xce, lsl #24
+ 5b3c: 0f0665e7 movi v7.2s, #0xcf, lsl #24
+ 5b40: 0f066607 movi v7.2s, #0xd0, lsl #24
+ 5b44: 0f066627 movi v7.2s, #0xd1, lsl #24
+ 5b48: 0f066647 movi v7.2s, #0xd2, lsl #24
+ 5b4c: 0f066667 movi v7.2s, #0xd3, lsl #24
+ 5b50: 0f066687 movi v7.2s, #0xd4, lsl #24
+ 5b54: 0f0666a7 movi v7.2s, #0xd5, lsl #24
+ 5b58: 0f0666c7 movi v7.2s, #0xd6, lsl #24
+ 5b5c: 0f0666e7 movi v7.2s, #0xd7, lsl #24
+ 5b60: 0f066707 movi v7.2s, #0xd8, lsl #24
+ 5b64: 0f066727 movi v7.2s, #0xd9, lsl #24
+ 5b68: 0f066747 movi v7.2s, #0xda, lsl #24
+ 5b6c: 0f066767 movi v7.2s, #0xdb, lsl #24
+ 5b70: 0f066787 movi v7.2s, #0xdc, lsl #24
+ 5b74: 0f0667a7 movi v7.2s, #0xdd, lsl #24
+ 5b78: 0f0667c7 movi v7.2s, #0xde, lsl #24
+ 5b7c: 0f0667e7 movi v7.2s, #0xdf, lsl #24
+ 5b80: 0f076407 movi v7.2s, #0xe0, lsl #24
+ 5b84: 0f076427 movi v7.2s, #0xe1, lsl #24
+ 5b88: 0f076447 movi v7.2s, #0xe2, lsl #24
+ 5b8c: 0f076467 movi v7.2s, #0xe3, lsl #24
+ 5b90: 0f076487 movi v7.2s, #0xe4, lsl #24
+ 5b94: 0f0764a7 movi v7.2s, #0xe5, lsl #24
+ 5b98: 0f0764c7 movi v7.2s, #0xe6, lsl #24
+ 5b9c: 0f0764e7 movi v7.2s, #0xe7, lsl #24
+ 5ba0: 0f076507 movi v7.2s, #0xe8, lsl #24
+ 5ba4: 0f076527 movi v7.2s, #0xe9, lsl #24
+ 5ba8: 0f076547 movi v7.2s, #0xea, lsl #24
+ 5bac: 0f076567 movi v7.2s, #0xeb, lsl #24
+ 5bb0: 0f076587 movi v7.2s, #0xec, lsl #24
+ 5bb4: 0f0765a7 movi v7.2s, #0xed, lsl #24
+ 5bb8: 0f0765c7 movi v7.2s, #0xee, lsl #24
+ 5bbc: 0f0765e7 movi v7.2s, #0xef, lsl #24
+ 5bc0: 0f076607 movi v7.2s, #0xf0, lsl #24
+ 5bc4: 0f076627 movi v7.2s, #0xf1, lsl #24
+ 5bc8: 0f076647 movi v7.2s, #0xf2, lsl #24
+ 5bcc: 0f076667 movi v7.2s, #0xf3, lsl #24
+ 5bd0: 0f076687 movi v7.2s, #0xf4, lsl #24
+ 5bd4: 0f0766a7 movi v7.2s, #0xf5, lsl #24
+ 5bd8: 0f0766c7 movi v7.2s, #0xf6, lsl #24
+ 5bdc: 0f0766e7 movi v7.2s, #0xf7, lsl #24
+ 5be0: 0f076707 movi v7.2s, #0xf8, lsl #24
+ 5be4: 0f076727 movi v7.2s, #0xf9, lsl #24
+ 5be8: 0f076747 movi v7.2s, #0xfa, lsl #24
+ 5bec: 0f076767 movi v7.2s, #0xfb, lsl #24
+ 5bf0: 0f076787 movi v7.2s, #0xfc, lsl #24
+ 5bf4: 0f0767a7 movi v7.2s, #0xfd, lsl #24
+ 5bf8: 0f0767c7 movi v7.2s, #0xfe, lsl #24
+ 5bfc: 0f0767e7 movi v7.2s, #0xff, lsl #24
+ 5c00: 0f00040f movi v15.2s, #0x0
+ 5c04: 0f00042f movi v15.2s, #0x1
+ 5c08: 0f00044f movi v15.2s, #0x2
+ 5c0c: 0f00046f movi v15.2s, #0x3
+ 5c10: 0f00048f movi v15.2s, #0x4
+ 5c14: 0f0004af movi v15.2s, #0x5
+ 5c18: 0f0004cf movi v15.2s, #0x6
+ 5c1c: 0f0004ef movi v15.2s, #0x7
+ 5c20: 0f00050f movi v15.2s, #0x8
+ 5c24: 0f00052f movi v15.2s, #0x9
+ 5c28: 0f00054f movi v15.2s, #0xa
+ 5c2c: 0f00056f movi v15.2s, #0xb
+ 5c30: 0f00058f movi v15.2s, #0xc
+ 5c34: 0f0005af movi v15.2s, #0xd
+ 5c38: 0f0005cf movi v15.2s, #0xe
+ 5c3c: 0f0005ef movi v15.2s, #0xf
+ 5c40: 0f00060f movi v15.2s, #0x10
+ 5c44: 0f00062f movi v15.2s, #0x11
+ 5c48: 0f00064f movi v15.2s, #0x12
+ 5c4c: 0f00066f movi v15.2s, #0x13
+ 5c50: 0f00068f movi v15.2s, #0x14
+ 5c54: 0f0006af movi v15.2s, #0x15
+ 5c58: 0f0006cf movi v15.2s, #0x16
+ 5c5c: 0f0006ef movi v15.2s, #0x17
+ 5c60: 0f00070f movi v15.2s, #0x18
+ 5c64: 0f00072f movi v15.2s, #0x19
+ 5c68: 0f00074f movi v15.2s, #0x1a
+ 5c6c: 0f00076f movi v15.2s, #0x1b
+ 5c70: 0f00078f movi v15.2s, #0x1c
+ 5c74: 0f0007af movi v15.2s, #0x1d
+ 5c78: 0f0007cf movi v15.2s, #0x1e
+ 5c7c: 0f0007ef movi v15.2s, #0x1f
+ 5c80: 0f01040f movi v15.2s, #0x20
+ 5c84: 0f01042f movi v15.2s, #0x21
+ 5c88: 0f01044f movi v15.2s, #0x22
+ 5c8c: 0f01046f movi v15.2s, #0x23
+ 5c90: 0f01048f movi v15.2s, #0x24
+ 5c94: 0f0104af movi v15.2s, #0x25
+ 5c98: 0f0104cf movi v15.2s, #0x26
+ 5c9c: 0f0104ef movi v15.2s, #0x27
+ 5ca0: 0f01050f movi v15.2s, #0x28
+ 5ca4: 0f01052f movi v15.2s, #0x29
+ 5ca8: 0f01054f movi v15.2s, #0x2a
+ 5cac: 0f01056f movi v15.2s, #0x2b
+ 5cb0: 0f01058f movi v15.2s, #0x2c
+ 5cb4: 0f0105af movi v15.2s, #0x2d
+ 5cb8: 0f0105cf movi v15.2s, #0x2e
+ 5cbc: 0f0105ef movi v15.2s, #0x2f
+ 5cc0: 0f01060f movi v15.2s, #0x30
+ 5cc4: 0f01062f movi v15.2s, #0x31
+ 5cc8: 0f01064f movi v15.2s, #0x32
+ 5ccc: 0f01066f movi v15.2s, #0x33
+ 5cd0: 0f01068f movi v15.2s, #0x34
+ 5cd4: 0f0106af movi v15.2s, #0x35
+ 5cd8: 0f0106cf movi v15.2s, #0x36
+ 5cdc: 0f0106ef movi v15.2s, #0x37
+ 5ce0: 0f01070f movi v15.2s, #0x38
+ 5ce4: 0f01072f movi v15.2s, #0x39
+ 5ce8: 0f01074f movi v15.2s, #0x3a
+ 5cec: 0f01076f movi v15.2s, #0x3b
+ 5cf0: 0f01078f movi v15.2s, #0x3c
+ 5cf4: 0f0107af movi v15.2s, #0x3d
+ 5cf8: 0f0107cf movi v15.2s, #0x3e
+ 5cfc: 0f0107ef movi v15.2s, #0x3f
+ 5d00: 0f02040f movi v15.2s, #0x40
+ 5d04: 0f02042f movi v15.2s, #0x41
+ 5d08: 0f02044f movi v15.2s, #0x42
+ 5d0c: 0f02046f movi v15.2s, #0x43
+ 5d10: 0f02048f movi v15.2s, #0x44
+ 5d14: 0f0204af movi v15.2s, #0x45
+ 5d18: 0f0204cf movi v15.2s, #0x46
+ 5d1c: 0f0204ef movi v15.2s, #0x47
+ 5d20: 0f02050f movi v15.2s, #0x48
+ 5d24: 0f02052f movi v15.2s, #0x49
+ 5d28: 0f02054f movi v15.2s, #0x4a
+ 5d2c: 0f02056f movi v15.2s, #0x4b
+ 5d30: 0f02058f movi v15.2s, #0x4c
+ 5d34: 0f0205af movi v15.2s, #0x4d
+ 5d38: 0f0205cf movi v15.2s, #0x4e
+ 5d3c: 0f0205ef movi v15.2s, #0x4f
+ 5d40: 0f02060f movi v15.2s, #0x50
+ 5d44: 0f02062f movi v15.2s, #0x51
+ 5d48: 0f02064f movi v15.2s, #0x52
+ 5d4c: 0f02066f movi v15.2s, #0x53
+ 5d50: 0f02068f movi v15.2s, #0x54
+ 5d54: 0f0206af movi v15.2s, #0x55
+ 5d58: 0f0206cf movi v15.2s, #0x56
+ 5d5c: 0f0206ef movi v15.2s, #0x57
+ 5d60: 0f02070f movi v15.2s, #0x58
+ 5d64: 0f02072f movi v15.2s, #0x59
+ 5d68: 0f02074f movi v15.2s, #0x5a
+ 5d6c: 0f02076f movi v15.2s, #0x5b
+ 5d70: 0f02078f movi v15.2s, #0x5c
+ 5d74: 0f0207af movi v15.2s, #0x5d
+ 5d78: 0f0207cf movi v15.2s, #0x5e
+ 5d7c: 0f0207ef movi v15.2s, #0x5f
+ 5d80: 0f03040f movi v15.2s, #0x60
+ 5d84: 0f03042f movi v15.2s, #0x61
+ 5d88: 0f03044f movi v15.2s, #0x62
+ 5d8c: 0f03046f movi v15.2s, #0x63
+ 5d90: 0f03048f movi v15.2s, #0x64
+ 5d94: 0f0304af movi v15.2s, #0x65
+ 5d98: 0f0304cf movi v15.2s, #0x66
+ 5d9c: 0f0304ef movi v15.2s, #0x67
+ 5da0: 0f03050f movi v15.2s, #0x68
+ 5da4: 0f03052f movi v15.2s, #0x69
+ 5da8: 0f03054f movi v15.2s, #0x6a
+ 5dac: 0f03056f movi v15.2s, #0x6b
+ 5db0: 0f03058f movi v15.2s, #0x6c
+ 5db4: 0f0305af movi v15.2s, #0x6d
+ 5db8: 0f0305cf movi v15.2s, #0x6e
+ 5dbc: 0f0305ef movi v15.2s, #0x6f
+ 5dc0: 0f03060f movi v15.2s, #0x70
+ 5dc4: 0f03062f movi v15.2s, #0x71
+ 5dc8: 0f03064f movi v15.2s, #0x72
+ 5dcc: 0f03066f movi v15.2s, #0x73
+ 5dd0: 0f03068f movi v15.2s, #0x74
+ 5dd4: 0f0306af movi v15.2s, #0x75
+ 5dd8: 0f0306cf movi v15.2s, #0x76
+ 5ddc: 0f0306ef movi v15.2s, #0x77
+ 5de0: 0f03070f movi v15.2s, #0x78
+ 5de4: 0f03072f movi v15.2s, #0x79
+ 5de8: 0f03074f movi v15.2s, #0x7a
+ 5dec: 0f03076f movi v15.2s, #0x7b
+ 5df0: 0f03078f movi v15.2s, #0x7c
+ 5df4: 0f0307af movi v15.2s, #0x7d
+ 5df8: 0f0307cf movi v15.2s, #0x7e
+ 5dfc: 0f0307ef movi v15.2s, #0x7f
+ 5e00: 0f04040f movi v15.2s, #0x80
+ 5e04: 0f04042f movi v15.2s, #0x81
+ 5e08: 0f04044f movi v15.2s, #0x82
+ 5e0c: 0f04046f movi v15.2s, #0x83
+ 5e10: 0f04048f movi v15.2s, #0x84
+ 5e14: 0f0404af movi v15.2s, #0x85
+ 5e18: 0f0404cf movi v15.2s, #0x86
+ 5e1c: 0f0404ef movi v15.2s, #0x87
+ 5e20: 0f04050f movi v15.2s, #0x88
+ 5e24: 0f04052f movi v15.2s, #0x89
+ 5e28: 0f04054f movi v15.2s, #0x8a
+ 5e2c: 0f04056f movi v15.2s, #0x8b
+ 5e30: 0f04058f movi v15.2s, #0x8c
+ 5e34: 0f0405af movi v15.2s, #0x8d
+ 5e38: 0f0405cf movi v15.2s, #0x8e
+ 5e3c: 0f0405ef movi v15.2s, #0x8f
+ 5e40: 0f04060f movi v15.2s, #0x90
+ 5e44: 0f04062f movi v15.2s, #0x91
+ 5e48: 0f04064f movi v15.2s, #0x92
+ 5e4c: 0f04066f movi v15.2s, #0x93
+ 5e50: 0f04068f movi v15.2s, #0x94
+ 5e54: 0f0406af movi v15.2s, #0x95
+ 5e58: 0f0406cf movi v15.2s, #0x96
+ 5e5c: 0f0406ef movi v15.2s, #0x97
+ 5e60: 0f04070f movi v15.2s, #0x98
+ 5e64: 0f04072f movi v15.2s, #0x99
+ 5e68: 0f04074f movi v15.2s, #0x9a
+ 5e6c: 0f04076f movi v15.2s, #0x9b
+ 5e70: 0f04078f movi v15.2s, #0x9c
+ 5e74: 0f0407af movi v15.2s, #0x9d
+ 5e78: 0f0407cf movi v15.2s, #0x9e
+ 5e7c: 0f0407ef movi v15.2s, #0x9f
+ 5e80: 0f05040f movi v15.2s, #0xa0
+ 5e84: 0f05042f movi v15.2s, #0xa1
+ 5e88: 0f05044f movi v15.2s, #0xa2
+ 5e8c: 0f05046f movi v15.2s, #0xa3
+ 5e90: 0f05048f movi v15.2s, #0xa4
+ 5e94: 0f0504af movi v15.2s, #0xa5
+ 5e98: 0f0504cf movi v15.2s, #0xa6
+ 5e9c: 0f0504ef movi v15.2s, #0xa7
+ 5ea0: 0f05050f movi v15.2s, #0xa8
+ 5ea4: 0f05052f movi v15.2s, #0xa9
+ 5ea8: 0f05054f movi v15.2s, #0xaa
+ 5eac: 0f05056f movi v15.2s, #0xab
+ 5eb0: 0f05058f movi v15.2s, #0xac
+ 5eb4: 0f0505af movi v15.2s, #0xad
+ 5eb8: 0f0505cf movi v15.2s, #0xae
+ 5ebc: 0f0505ef movi v15.2s, #0xaf
+ 5ec0: 0f05060f movi v15.2s, #0xb0
+ 5ec4: 0f05062f movi v15.2s, #0xb1
+ 5ec8: 0f05064f movi v15.2s, #0xb2
+ 5ecc: 0f05066f movi v15.2s, #0xb3
+ 5ed0: 0f05068f movi v15.2s, #0xb4
+ 5ed4: 0f0506af movi v15.2s, #0xb5
+ 5ed8: 0f0506cf movi v15.2s, #0xb6
+ 5edc: 0f0506ef movi v15.2s, #0xb7
+ 5ee0: 0f05070f movi v15.2s, #0xb8
+ 5ee4: 0f05072f movi v15.2s, #0xb9
+ 5ee8: 0f05074f movi v15.2s, #0xba
+ 5eec: 0f05076f movi v15.2s, #0xbb
+ 5ef0: 0f05078f movi v15.2s, #0xbc
+ 5ef4: 0f0507af movi v15.2s, #0xbd
+ 5ef8: 0f0507cf movi v15.2s, #0xbe
+ 5efc: 0f0507ef movi v15.2s, #0xbf
+ 5f00: 0f06040f movi v15.2s, #0xc0
+ 5f04: 0f06042f movi v15.2s, #0xc1
+ 5f08: 0f06044f movi v15.2s, #0xc2
+ 5f0c: 0f06046f movi v15.2s, #0xc3
+ 5f10: 0f06048f movi v15.2s, #0xc4
+ 5f14: 0f0604af movi v15.2s, #0xc5
+ 5f18: 0f0604cf movi v15.2s, #0xc6
+ 5f1c: 0f0604ef movi v15.2s, #0xc7
+ 5f20: 0f06050f movi v15.2s, #0xc8
+ 5f24: 0f06052f movi v15.2s, #0xc9
+ 5f28: 0f06054f movi v15.2s, #0xca
+ 5f2c: 0f06056f movi v15.2s, #0xcb
+ 5f30: 0f06058f movi v15.2s, #0xcc
+ 5f34: 0f0605af movi v15.2s, #0xcd
+ 5f38: 0f0605cf movi v15.2s, #0xce
+ 5f3c: 0f0605ef movi v15.2s, #0xcf
+ 5f40: 0f06060f movi v15.2s, #0xd0
+ 5f44: 0f06062f movi v15.2s, #0xd1
+ 5f48: 0f06064f movi v15.2s, #0xd2
+ 5f4c: 0f06066f movi v15.2s, #0xd3
+ 5f50: 0f06068f movi v15.2s, #0xd4
+ 5f54: 0f0606af movi v15.2s, #0xd5
+ 5f58: 0f0606cf movi v15.2s, #0xd6
+ 5f5c: 0f0606ef movi v15.2s, #0xd7
+ 5f60: 0f06070f movi v15.2s, #0xd8
+ 5f64: 0f06072f movi v15.2s, #0xd9
+ 5f68: 0f06074f movi v15.2s, #0xda
+ 5f6c: 0f06076f movi v15.2s, #0xdb
+ 5f70: 0f06078f movi v15.2s, #0xdc
+ 5f74: 0f0607af movi v15.2s, #0xdd
+ 5f78: 0f0607cf movi v15.2s, #0xde
+ 5f7c: 0f0607ef movi v15.2s, #0xdf
+ 5f80: 0f07040f movi v15.2s, #0xe0
+ 5f84: 0f07042f movi v15.2s, #0xe1
+ 5f88: 0f07044f movi v15.2s, #0xe2
+ 5f8c: 0f07046f movi v15.2s, #0xe3
+ 5f90: 0f07048f movi v15.2s, #0xe4
+ 5f94: 0f0704af movi v15.2s, #0xe5
+ 5f98: 0f0704cf movi v15.2s, #0xe6
+ 5f9c: 0f0704ef movi v15.2s, #0xe7
+ 5fa0: 0f07050f movi v15.2s, #0xe8
+ 5fa4: 0f07052f movi v15.2s, #0xe9
+ 5fa8: 0f07054f movi v15.2s, #0xea
+ 5fac: 0f07056f movi v15.2s, #0xeb
+ 5fb0: 0f07058f movi v15.2s, #0xec
+ 5fb4: 0f0705af movi v15.2s, #0xed
+ 5fb8: 0f0705cf movi v15.2s, #0xee
+ 5fbc: 0f0705ef movi v15.2s, #0xef
+ 5fc0: 0f07060f movi v15.2s, #0xf0
+ 5fc4: 0f07062f movi v15.2s, #0xf1
+ 5fc8: 0f07064f movi v15.2s, #0xf2
+ 5fcc: 0f07066f movi v15.2s, #0xf3
+ 5fd0: 0f07068f movi v15.2s, #0xf4
+ 5fd4: 0f0706af movi v15.2s, #0xf5
+ 5fd8: 0f0706cf movi v15.2s, #0xf6
+ 5fdc: 0f0706ef movi v15.2s, #0xf7
+ 5fe0: 0f07070f movi v15.2s, #0xf8
+ 5fe4: 0f07072f movi v15.2s, #0xf9
+ 5fe8: 0f07074f movi v15.2s, #0xfa
+ 5fec: 0f07076f movi v15.2s, #0xfb
+ 5ff0: 0f07078f movi v15.2s, #0xfc
+ 5ff4: 0f0707af movi v15.2s, #0xfd
+ 5ff8: 0f0707cf movi v15.2s, #0xfe
+ 5ffc: 0f0707ef movi v15.2s, #0xff
+ 6000: 4f000407 movi v7.4s, #0x0
+ 6004: 4f000427 movi v7.4s, #0x1
+ 6008: 4f000447 movi v7.4s, #0x2
+ 600c: 4f000467 movi v7.4s, #0x3
+ 6010: 4f000487 movi v7.4s, #0x4
+ 6014: 4f0004a7 movi v7.4s, #0x5
+ 6018: 4f0004c7 movi v7.4s, #0x6
+ 601c: 4f0004e7 movi v7.4s, #0x7
+ 6020: 4f000507 movi v7.4s, #0x8
+ 6024: 4f000527 movi v7.4s, #0x9
+ 6028: 4f000547 movi v7.4s, #0xa
+ 602c: 4f000567 movi v7.4s, #0xb
+ 6030: 4f000587 movi v7.4s, #0xc
+ 6034: 4f0005a7 movi v7.4s, #0xd
+ 6038: 4f0005c7 movi v7.4s, #0xe
+ 603c: 4f0005e7 movi v7.4s, #0xf
+ 6040: 4f000607 movi v7.4s, #0x10
+ 6044: 4f000627 movi v7.4s, #0x11
+ 6048: 4f000647 movi v7.4s, #0x12
+ 604c: 4f000667 movi v7.4s, #0x13
+ 6050: 4f000687 movi v7.4s, #0x14
+ 6054: 4f0006a7 movi v7.4s, #0x15
+ 6058: 4f0006c7 movi v7.4s, #0x16
+ 605c: 4f0006e7 movi v7.4s, #0x17
+ 6060: 4f000707 movi v7.4s, #0x18
+ 6064: 4f000727 movi v7.4s, #0x19
+ 6068: 4f000747 movi v7.4s, #0x1a
+ 606c: 4f000767 movi v7.4s, #0x1b
+ 6070: 4f000787 movi v7.4s, #0x1c
+ 6074: 4f0007a7 movi v7.4s, #0x1d
+ 6078: 4f0007c7 movi v7.4s, #0x1e
+ 607c: 4f0007e7 movi v7.4s, #0x1f
+ 6080: 4f010407 movi v7.4s, #0x20
+ 6084: 4f010427 movi v7.4s, #0x21
+ 6088: 4f010447 movi v7.4s, #0x22
+ 608c: 4f010467 movi v7.4s, #0x23
+ 6090: 4f010487 movi v7.4s, #0x24
+ 6094: 4f0104a7 movi v7.4s, #0x25
+ 6098: 4f0104c7 movi v7.4s, #0x26
+ 609c: 4f0104e7 movi v7.4s, #0x27
+ 60a0: 4f010507 movi v7.4s, #0x28
+ 60a4: 4f010527 movi v7.4s, #0x29
+ 60a8: 4f010547 movi v7.4s, #0x2a
+ 60ac: 4f010567 movi v7.4s, #0x2b
+ 60b0: 4f010587 movi v7.4s, #0x2c
+ 60b4: 4f0105a7 movi v7.4s, #0x2d
+ 60b8: 4f0105c7 movi v7.4s, #0x2e
+ 60bc: 4f0105e7 movi v7.4s, #0x2f
+ 60c0: 4f010607 movi v7.4s, #0x30
+ 60c4: 4f010627 movi v7.4s, #0x31
+ 60c8: 4f010647 movi v7.4s, #0x32
+ 60cc: 4f010667 movi v7.4s, #0x33
+ 60d0: 4f010687 movi v7.4s, #0x34
+ 60d4: 4f0106a7 movi v7.4s, #0x35
+ 60d8: 4f0106c7 movi v7.4s, #0x36
+ 60dc: 4f0106e7 movi v7.4s, #0x37
+ 60e0: 4f010707 movi v7.4s, #0x38
+ 60e4: 4f010727 movi v7.4s, #0x39
+ 60e8: 4f010747 movi v7.4s, #0x3a
+ 60ec: 4f010767 movi v7.4s, #0x3b
+ 60f0: 4f010787 movi v7.4s, #0x3c
+ 60f4: 4f0107a7 movi v7.4s, #0x3d
+ 60f8: 4f0107c7 movi v7.4s, #0x3e
+ 60fc: 4f0107e7 movi v7.4s, #0x3f
+ 6100: 4f020407 movi v7.4s, #0x40
+ 6104: 4f020427 movi v7.4s, #0x41
+ 6108: 4f020447 movi v7.4s, #0x42
+ 610c: 4f020467 movi v7.4s, #0x43
+ 6110: 4f020487 movi v7.4s, #0x44
+ 6114: 4f0204a7 movi v7.4s, #0x45
+ 6118: 4f0204c7 movi v7.4s, #0x46
+ 611c: 4f0204e7 movi v7.4s, #0x47
+ 6120: 4f020507 movi v7.4s, #0x48
+ 6124: 4f020527 movi v7.4s, #0x49
+ 6128: 4f020547 movi v7.4s, #0x4a
+ 612c: 4f020567 movi v7.4s, #0x4b
+ 6130: 4f020587 movi v7.4s, #0x4c
+ 6134: 4f0205a7 movi v7.4s, #0x4d
+ 6138: 4f0205c7 movi v7.4s, #0x4e
+ 613c: 4f0205e7 movi v7.4s, #0x4f
+ 6140: 4f020607 movi v7.4s, #0x50
+ 6144: 4f020627 movi v7.4s, #0x51
+ 6148: 4f020647 movi v7.4s, #0x52
+ 614c: 4f020667 movi v7.4s, #0x53
+ 6150: 4f020687 movi v7.4s, #0x54
+ 6154: 4f0206a7 movi v7.4s, #0x55
+ 6158: 4f0206c7 movi v7.4s, #0x56
+ 615c: 4f0206e7 movi v7.4s, #0x57
+ 6160: 4f020707 movi v7.4s, #0x58
+ 6164: 4f020727 movi v7.4s, #0x59
+ 6168: 4f020747 movi v7.4s, #0x5a
+ 616c: 4f020767 movi v7.4s, #0x5b
+ 6170: 4f020787 movi v7.4s, #0x5c
+ 6174: 4f0207a7 movi v7.4s, #0x5d
+ 6178: 4f0207c7 movi v7.4s, #0x5e
+ 617c: 4f0207e7 movi v7.4s, #0x5f
+ 6180: 4f030407 movi v7.4s, #0x60
+ 6184: 4f030427 movi v7.4s, #0x61
+ 6188: 4f030447 movi v7.4s, #0x62
+ 618c: 4f030467 movi v7.4s, #0x63
+ 6190: 4f030487 movi v7.4s, #0x64
+ 6194: 4f0304a7 movi v7.4s, #0x65
+ 6198: 4f0304c7 movi v7.4s, #0x66
+ 619c: 4f0304e7 movi v7.4s, #0x67
+ 61a0: 4f030507 movi v7.4s, #0x68
+ 61a4: 4f030527 movi v7.4s, #0x69
+ 61a8: 4f030547 movi v7.4s, #0x6a
+ 61ac: 4f030567 movi v7.4s, #0x6b
+ 61b0: 4f030587 movi v7.4s, #0x6c
+ 61b4: 4f0305a7 movi v7.4s, #0x6d
+ 61b8: 4f0305c7 movi v7.4s, #0x6e
+ 61bc: 4f0305e7 movi v7.4s, #0x6f
+ 61c0: 4f030607 movi v7.4s, #0x70
+ 61c4: 4f030627 movi v7.4s, #0x71
+ 61c8: 4f030647 movi v7.4s, #0x72
+ 61cc: 4f030667 movi v7.4s, #0x73
+ 61d0: 4f030687 movi v7.4s, #0x74
+ 61d4: 4f0306a7 movi v7.4s, #0x75
+ 61d8: 4f0306c7 movi v7.4s, #0x76
+ 61dc: 4f0306e7 movi v7.4s, #0x77
+ 61e0: 4f030707 movi v7.4s, #0x78
+ 61e4: 4f030727 movi v7.4s, #0x79
+ 61e8: 4f030747 movi v7.4s, #0x7a
+ 61ec: 4f030767 movi v7.4s, #0x7b
+ 61f0: 4f030787 movi v7.4s, #0x7c
+ 61f4: 4f0307a7 movi v7.4s, #0x7d
+ 61f8: 4f0307c7 movi v7.4s, #0x7e
+ 61fc: 4f0307e7 movi v7.4s, #0x7f
+ 6200: 4f040407 movi v7.4s, #0x80
+ 6204: 4f040427 movi v7.4s, #0x81
+ 6208: 4f040447 movi v7.4s, #0x82
+ 620c: 4f040467 movi v7.4s, #0x83
+ 6210: 4f040487 movi v7.4s, #0x84
+ 6214: 4f0404a7 movi v7.4s, #0x85
+ 6218: 4f0404c7 movi v7.4s, #0x86
+ 621c: 4f0404e7 movi v7.4s, #0x87
+ 6220: 4f040507 movi v7.4s, #0x88
+ 6224: 4f040527 movi v7.4s, #0x89
+ 6228: 4f040547 movi v7.4s, #0x8a
+ 622c: 4f040567 movi v7.4s, #0x8b
+ 6230: 4f040587 movi v7.4s, #0x8c
+ 6234: 4f0405a7 movi v7.4s, #0x8d
+ 6238: 4f0405c7 movi v7.4s, #0x8e
+ 623c: 4f0405e7 movi v7.4s, #0x8f
+ 6240: 4f040607 movi v7.4s, #0x90
+ 6244: 4f040627 movi v7.4s, #0x91
+ 6248: 4f040647 movi v7.4s, #0x92
+ 624c: 4f040667 movi v7.4s, #0x93
+ 6250: 4f040687 movi v7.4s, #0x94
+ 6254: 4f0406a7 movi v7.4s, #0x95
+ 6258: 4f0406c7 movi v7.4s, #0x96
+ 625c: 4f0406e7 movi v7.4s, #0x97
+ 6260: 4f040707 movi v7.4s, #0x98
+ 6264: 4f040727 movi v7.4s, #0x99
+ 6268: 4f040747 movi v7.4s, #0x9a
+ 626c: 4f040767 movi v7.4s, #0x9b
+ 6270: 4f040787 movi v7.4s, #0x9c
+ 6274: 4f0407a7 movi v7.4s, #0x9d
+ 6278: 4f0407c7 movi v7.4s, #0x9e
+ 627c: 4f0407e7 movi v7.4s, #0x9f
+ 6280: 4f050407 movi v7.4s, #0xa0
+ 6284: 4f050427 movi v7.4s, #0xa1
+ 6288: 4f050447 movi v7.4s, #0xa2
+ 628c: 4f050467 movi v7.4s, #0xa3
+ 6290: 4f050487 movi v7.4s, #0xa4
+ 6294: 4f0504a7 movi v7.4s, #0xa5
+ 6298: 4f0504c7 movi v7.4s, #0xa6
+ 629c: 4f0504e7 movi v7.4s, #0xa7
+ 62a0: 4f050507 movi v7.4s, #0xa8
+ 62a4: 4f050527 movi v7.4s, #0xa9
+ 62a8: 4f050547 movi v7.4s, #0xaa
+ 62ac: 4f050567 movi v7.4s, #0xab
+ 62b0: 4f050587 movi v7.4s, #0xac
+ 62b4: 4f0505a7 movi v7.4s, #0xad
+ 62b8: 4f0505c7 movi v7.4s, #0xae
+ 62bc: 4f0505e7 movi v7.4s, #0xaf
+ 62c0: 4f050607 movi v7.4s, #0xb0
+ 62c4: 4f050627 movi v7.4s, #0xb1
+ 62c8: 4f050647 movi v7.4s, #0xb2
+ 62cc: 4f050667 movi v7.4s, #0xb3
+ 62d0: 4f050687 movi v7.4s, #0xb4
+ 62d4: 4f0506a7 movi v7.4s, #0xb5
+ 62d8: 4f0506c7 movi v7.4s, #0xb6
+ 62dc: 4f0506e7 movi v7.4s, #0xb7
+ 62e0: 4f050707 movi v7.4s, #0xb8
+ 62e4: 4f050727 movi v7.4s, #0xb9
+ 62e8: 4f050747 movi v7.4s, #0xba
+ 62ec: 4f050767 movi v7.4s, #0xbb
+ 62f0: 4f050787 movi v7.4s, #0xbc
+ 62f4: 4f0507a7 movi v7.4s, #0xbd
+ 62f8: 4f0507c7 movi v7.4s, #0xbe
+ 62fc: 4f0507e7 movi v7.4s, #0xbf
+ 6300: 4f060407 movi v7.4s, #0xc0
+ 6304: 4f060427 movi v7.4s, #0xc1
+ 6308: 4f060447 movi v7.4s, #0xc2
+ 630c: 4f060467 movi v7.4s, #0xc3
+ 6310: 4f060487 movi v7.4s, #0xc4
+ 6314: 4f0604a7 movi v7.4s, #0xc5
+ 6318: 4f0604c7 movi v7.4s, #0xc6
+ 631c: 4f0604e7 movi v7.4s, #0xc7
+ 6320: 4f060507 movi v7.4s, #0xc8
+ 6324: 4f060527 movi v7.4s, #0xc9
+ 6328: 4f060547 movi v7.4s, #0xca
+ 632c: 4f060567 movi v7.4s, #0xcb
+ 6330: 4f060587 movi v7.4s, #0xcc
+ 6334: 4f0605a7 movi v7.4s, #0xcd
+ 6338: 4f0605c7 movi v7.4s, #0xce
+ 633c: 4f0605e7 movi v7.4s, #0xcf
+ 6340: 4f060607 movi v7.4s, #0xd0
+ 6344: 4f060627 movi v7.4s, #0xd1
+ 6348: 4f060647 movi v7.4s, #0xd2
+ 634c: 4f060667 movi v7.4s, #0xd3
+ 6350: 4f060687 movi v7.4s, #0xd4
+ 6354: 4f0606a7 movi v7.4s, #0xd5
+ 6358: 4f0606c7 movi v7.4s, #0xd6
+ 635c: 4f0606e7 movi v7.4s, #0xd7
+ 6360: 4f060707 movi v7.4s, #0xd8
+ 6364: 4f060727 movi v7.4s, #0xd9
+ 6368: 4f060747 movi v7.4s, #0xda
+ 636c: 4f060767 movi v7.4s, #0xdb
+ 6370: 4f060787 movi v7.4s, #0xdc
+ 6374: 4f0607a7 movi v7.4s, #0xdd
+ 6378: 4f0607c7 movi v7.4s, #0xde
+ 637c: 4f0607e7 movi v7.4s, #0xdf
+ 6380: 4f070407 movi v7.4s, #0xe0
+ 6384: 4f070427 movi v7.4s, #0xe1
+ 6388: 4f070447 movi v7.4s, #0xe2
+ 638c: 4f070467 movi v7.4s, #0xe3
+ 6390: 4f070487 movi v7.4s, #0xe4
+ 6394: 4f0704a7 movi v7.4s, #0xe5
+ 6398: 4f0704c7 movi v7.4s, #0xe6
+ 639c: 4f0704e7 movi v7.4s, #0xe7
+ 63a0: 4f070507 movi v7.4s, #0xe8
+ 63a4: 4f070527 movi v7.4s, #0xe9
+ 63a8: 4f070547 movi v7.4s, #0xea
+ 63ac: 4f070567 movi v7.4s, #0xeb
+ 63b0: 4f070587 movi v7.4s, #0xec
+ 63b4: 4f0705a7 movi v7.4s, #0xed
+ 63b8: 4f0705c7 movi v7.4s, #0xee
+ 63bc: 4f0705e7 movi v7.4s, #0xef
+ 63c0: 4f070607 movi v7.4s, #0xf0
+ 63c4: 4f070627 movi v7.4s, #0xf1
+ 63c8: 4f070647 movi v7.4s, #0xf2
+ 63cc: 4f070667 movi v7.4s, #0xf3
+ 63d0: 4f070687 movi v7.4s, #0xf4
+ 63d4: 4f0706a7 movi v7.4s, #0xf5
+ 63d8: 4f0706c7 movi v7.4s, #0xf6
+ 63dc: 4f0706e7 movi v7.4s, #0xf7
+ 63e0: 4f070707 movi v7.4s, #0xf8
+ 63e4: 4f070727 movi v7.4s, #0xf9
+ 63e8: 4f070747 movi v7.4s, #0xfa
+ 63ec: 4f070767 movi v7.4s, #0xfb
+ 63f0: 4f070787 movi v7.4s, #0xfc
+ 63f4: 4f0707a7 movi v7.4s, #0xfd
+ 63f8: 4f0707c7 movi v7.4s, #0xfe
+ 63fc: 4f0707e7 movi v7.4s, #0xff
+ 6400: 4f00040f movi v15.4s, #0x0
+ 6404: 4f00042f movi v15.4s, #0x1
+ 6408: 4f00044f movi v15.4s, #0x2
+ 640c: 4f00046f movi v15.4s, #0x3
+ 6410: 4f00048f movi v15.4s, #0x4
+ 6414: 4f0004af movi v15.4s, #0x5
+ 6418: 4f0004cf movi v15.4s, #0x6
+ 641c: 4f0004ef movi v15.4s, #0x7
+ 6420: 4f00050f movi v15.4s, #0x8
+ 6424: 4f00052f movi v15.4s, #0x9
+ 6428: 4f00054f movi v15.4s, #0xa
+ 642c: 4f00056f movi v15.4s, #0xb
+ 6430: 4f00058f movi v15.4s, #0xc
+ 6434: 4f0005af movi v15.4s, #0xd
+ 6438: 4f0005cf movi v15.4s, #0xe
+ 643c: 4f0005ef movi v15.4s, #0xf
+ 6440: 4f00060f movi v15.4s, #0x10
+ 6444: 4f00062f movi v15.4s, #0x11
+ 6448: 4f00064f movi v15.4s, #0x12
+ 644c: 4f00066f movi v15.4s, #0x13
+ 6450: 4f00068f movi v15.4s, #0x14
+ 6454: 4f0006af movi v15.4s, #0x15
+ 6458: 4f0006cf movi v15.4s, #0x16
+ 645c: 4f0006ef movi v15.4s, #0x17
+ 6460: 4f00070f movi v15.4s, #0x18
+ 6464: 4f00072f movi v15.4s, #0x19
+ 6468: 4f00074f movi v15.4s, #0x1a
+ 646c: 4f00076f movi v15.4s, #0x1b
+ 6470: 4f00078f movi v15.4s, #0x1c
+ 6474: 4f0007af movi v15.4s, #0x1d
+ 6478: 4f0007cf movi v15.4s, #0x1e
+ 647c: 4f0007ef movi v15.4s, #0x1f
+ 6480: 4f01040f movi v15.4s, #0x20
+ 6484: 4f01042f movi v15.4s, #0x21
+ 6488: 4f01044f movi v15.4s, #0x22
+ 648c: 4f01046f movi v15.4s, #0x23
+ 6490: 4f01048f movi v15.4s, #0x24
+ 6494: 4f0104af movi v15.4s, #0x25
+ 6498: 4f0104cf movi v15.4s, #0x26
+ 649c: 4f0104ef movi v15.4s, #0x27
+ 64a0: 4f01050f movi v15.4s, #0x28
+ 64a4: 4f01052f movi v15.4s, #0x29
+ 64a8: 4f01054f movi v15.4s, #0x2a
+ 64ac: 4f01056f movi v15.4s, #0x2b
+ 64b0: 4f01058f movi v15.4s, #0x2c
+ 64b4: 4f0105af movi v15.4s, #0x2d
+ 64b8: 4f0105cf movi v15.4s, #0x2e
+ 64bc: 4f0105ef movi v15.4s, #0x2f
+ 64c0: 4f01060f movi v15.4s, #0x30
+ 64c4: 4f01062f movi v15.4s, #0x31
+ 64c8: 4f01064f movi v15.4s, #0x32
+ 64cc: 4f01066f movi v15.4s, #0x33
+ 64d0: 4f01068f movi v15.4s, #0x34
+ 64d4: 4f0106af movi v15.4s, #0x35
+ 64d8: 4f0106cf movi v15.4s, #0x36
+ 64dc: 4f0106ef movi v15.4s, #0x37
+ 64e0: 4f01070f movi v15.4s, #0x38
+ 64e4: 4f01072f movi v15.4s, #0x39
+ 64e8: 4f01074f movi v15.4s, #0x3a
+ 64ec: 4f01076f movi v15.4s, #0x3b
+ 64f0: 4f01078f movi v15.4s, #0x3c
+ 64f4: 4f0107af movi v15.4s, #0x3d
+ 64f8: 4f0107cf movi v15.4s, #0x3e
+ 64fc: 4f0107ef movi v15.4s, #0x3f
+ 6500: 4f02040f movi v15.4s, #0x40
+ 6504: 4f02042f movi v15.4s, #0x41
+ 6508: 4f02044f movi v15.4s, #0x42
+ 650c: 4f02046f movi v15.4s, #0x43
+ 6510: 4f02048f movi v15.4s, #0x44
+ 6514: 4f0204af movi v15.4s, #0x45
+ 6518: 4f0204cf movi v15.4s, #0x46
+ 651c: 4f0204ef movi v15.4s, #0x47
+ 6520: 4f02050f movi v15.4s, #0x48
+ 6524: 4f02052f movi v15.4s, #0x49
+ 6528: 4f02054f movi v15.4s, #0x4a
+ 652c: 4f02056f movi v15.4s, #0x4b
+ 6530: 4f02058f movi v15.4s, #0x4c
+ 6534: 4f0205af movi v15.4s, #0x4d
+ 6538: 4f0205cf movi v15.4s, #0x4e
+ 653c: 4f0205ef movi v15.4s, #0x4f
+ 6540: 4f02060f movi v15.4s, #0x50
+ 6544: 4f02062f movi v15.4s, #0x51
+ 6548: 4f02064f movi v15.4s, #0x52
+ 654c: 4f02066f movi v15.4s, #0x53
+ 6550: 4f02068f movi v15.4s, #0x54
+ 6554: 4f0206af movi v15.4s, #0x55
+ 6558: 4f0206cf movi v15.4s, #0x56
+ 655c: 4f0206ef movi v15.4s, #0x57
+ 6560: 4f02070f movi v15.4s, #0x58
+ 6564: 4f02072f movi v15.4s, #0x59
+ 6568: 4f02074f movi v15.4s, #0x5a
+ 656c: 4f02076f movi v15.4s, #0x5b
+ 6570: 4f02078f movi v15.4s, #0x5c
+ 6574: 4f0207af movi v15.4s, #0x5d
+ 6578: 4f0207cf movi v15.4s, #0x5e
+ 657c: 4f0207ef movi v15.4s, #0x5f
+ 6580: 4f03040f movi v15.4s, #0x60
+ 6584: 4f03042f movi v15.4s, #0x61
+ 6588: 4f03044f movi v15.4s, #0x62
+ 658c: 4f03046f movi v15.4s, #0x63
+ 6590: 4f03048f movi v15.4s, #0x64
+ 6594: 4f0304af movi v15.4s, #0x65
+ 6598: 4f0304cf movi v15.4s, #0x66
+ 659c: 4f0304ef movi v15.4s, #0x67
+ 65a0: 4f03050f movi v15.4s, #0x68
+ 65a4: 4f03052f movi v15.4s, #0x69
+ 65a8: 4f03054f movi v15.4s, #0x6a
+ 65ac: 4f03056f movi v15.4s, #0x6b
+ 65b0: 4f03058f movi v15.4s, #0x6c
+ 65b4: 4f0305af movi v15.4s, #0x6d
+ 65b8: 4f0305cf movi v15.4s, #0x6e
+ 65bc: 4f0305ef movi v15.4s, #0x6f
+ 65c0: 4f03060f movi v15.4s, #0x70
+ 65c4: 4f03062f movi v15.4s, #0x71
+ 65c8: 4f03064f movi v15.4s, #0x72
+ 65cc: 4f03066f movi v15.4s, #0x73
+ 65d0: 4f03068f movi v15.4s, #0x74
+ 65d4: 4f0306af movi v15.4s, #0x75
+ 65d8: 4f0306cf movi v15.4s, #0x76
+ 65dc: 4f0306ef movi v15.4s, #0x77
+ 65e0: 4f03070f movi v15.4s, #0x78
+ 65e4: 4f03072f movi v15.4s, #0x79
+ 65e8: 4f03074f movi v15.4s, #0x7a
+ 65ec: 4f03076f movi v15.4s, #0x7b
+ 65f0: 4f03078f movi v15.4s, #0x7c
+ 65f4: 4f0307af movi v15.4s, #0x7d
+ 65f8: 4f0307cf movi v15.4s, #0x7e
+ 65fc: 4f0307ef movi v15.4s, #0x7f
+ 6600: 4f04040f movi v15.4s, #0x80
+ 6604: 4f04042f movi v15.4s, #0x81
+ 6608: 4f04044f movi v15.4s, #0x82
+ 660c: 4f04046f movi v15.4s, #0x83
+ 6610: 4f04048f movi v15.4s, #0x84
+ 6614: 4f0404af movi v15.4s, #0x85
+ 6618: 4f0404cf movi v15.4s, #0x86
+ 661c: 4f0404ef movi v15.4s, #0x87
+ 6620: 4f04050f movi v15.4s, #0x88
+ 6624: 4f04052f movi v15.4s, #0x89
+ 6628: 4f04054f movi v15.4s, #0x8a
+ 662c: 4f04056f movi v15.4s, #0x8b
+ 6630: 4f04058f movi v15.4s, #0x8c
+ 6634: 4f0405af movi v15.4s, #0x8d
+ 6638: 4f0405cf movi v15.4s, #0x8e
+ 663c: 4f0405ef movi v15.4s, #0x8f
+ 6640: 4f04060f movi v15.4s, #0x90
+ 6644: 4f04062f movi v15.4s, #0x91
+ 6648: 4f04064f movi v15.4s, #0x92
+ 664c: 4f04066f movi v15.4s, #0x93
+ 6650: 4f04068f movi v15.4s, #0x94
+ 6654: 4f0406af movi v15.4s, #0x95
+ 6658: 4f0406cf movi v15.4s, #0x96
+ 665c: 4f0406ef movi v15.4s, #0x97
+ 6660: 4f04070f movi v15.4s, #0x98
+ 6664: 4f04072f movi v15.4s, #0x99
+ 6668: 4f04074f movi v15.4s, #0x9a
+ 666c: 4f04076f movi v15.4s, #0x9b
+ 6670: 4f04078f movi v15.4s, #0x9c
+ 6674: 4f0407af movi v15.4s, #0x9d
+ 6678: 4f0407cf movi v15.4s, #0x9e
+ 667c: 4f0407ef movi v15.4s, #0x9f
+ 6680: 4f05040f movi v15.4s, #0xa0
+ 6684: 4f05042f movi v15.4s, #0xa1
+ 6688: 4f05044f movi v15.4s, #0xa2
+ 668c: 4f05046f movi v15.4s, #0xa3
+ 6690: 4f05048f movi v15.4s, #0xa4
+ 6694: 4f0504af movi v15.4s, #0xa5
+ 6698: 4f0504cf movi v15.4s, #0xa6
+ 669c: 4f0504ef movi v15.4s, #0xa7
+ 66a0: 4f05050f movi v15.4s, #0xa8
+ 66a4: 4f05052f movi v15.4s, #0xa9
+ 66a8: 4f05054f movi v15.4s, #0xaa
+ 66ac: 4f05056f movi v15.4s, #0xab
+ 66b0: 4f05058f movi v15.4s, #0xac
+ 66b4: 4f0505af movi v15.4s, #0xad
+ 66b8: 4f0505cf movi v15.4s, #0xae
+ 66bc: 4f0505ef movi v15.4s, #0xaf
+ 66c0: 4f05060f movi v15.4s, #0xb0
+ 66c4: 4f05062f movi v15.4s, #0xb1
+ 66c8: 4f05064f movi v15.4s, #0xb2
+ 66cc: 4f05066f movi v15.4s, #0xb3
+ 66d0: 4f05068f movi v15.4s, #0xb4
+ 66d4: 4f0506af movi v15.4s, #0xb5
+ 66d8: 4f0506cf movi v15.4s, #0xb6
+ 66dc: 4f0506ef movi v15.4s, #0xb7
+ 66e0: 4f05070f movi v15.4s, #0xb8
+ 66e4: 4f05072f movi v15.4s, #0xb9
+ 66e8: 4f05074f movi v15.4s, #0xba
+ 66ec: 4f05076f movi v15.4s, #0xbb
+ 66f0: 4f05078f movi v15.4s, #0xbc
+ 66f4: 4f0507af movi v15.4s, #0xbd
+ 66f8: 4f0507cf movi v15.4s, #0xbe
+ 66fc: 4f0507ef movi v15.4s, #0xbf
+ 6700: 4f06040f movi v15.4s, #0xc0
+ 6704: 4f06042f movi v15.4s, #0xc1
+ 6708: 4f06044f movi v15.4s, #0xc2
+ 670c: 4f06046f movi v15.4s, #0xc3
+ 6710: 4f06048f movi v15.4s, #0xc4
+ 6714: 4f0604af movi v15.4s, #0xc5
+ 6718: 4f0604cf movi v15.4s, #0xc6
+ 671c: 4f0604ef movi v15.4s, #0xc7
+ 6720: 4f06050f movi v15.4s, #0xc8
+ 6724: 4f06052f movi v15.4s, #0xc9
+ 6728: 4f06054f movi v15.4s, #0xca
+ 672c: 4f06056f movi v15.4s, #0xcb
+ 6730: 4f06058f movi v15.4s, #0xcc
+ 6734: 4f0605af movi v15.4s, #0xcd
+ 6738: 4f0605cf movi v15.4s, #0xce
+ 673c: 4f0605ef movi v15.4s, #0xcf
+ 6740: 4f06060f movi v15.4s, #0xd0
+ 6744: 4f06062f movi v15.4s, #0xd1
+ 6748: 4f06064f movi v15.4s, #0xd2
+ 674c: 4f06066f movi v15.4s, #0xd3
+ 6750: 4f06068f movi v15.4s, #0xd4
+ 6754: 4f0606af movi v15.4s, #0xd5
+ 6758: 4f0606cf movi v15.4s, #0xd6
+ 675c: 4f0606ef movi v15.4s, #0xd7
+ 6760: 4f06070f movi v15.4s, #0xd8
+ 6764: 4f06072f movi v15.4s, #0xd9
+ 6768: 4f06074f movi v15.4s, #0xda
+ 676c: 4f06076f movi v15.4s, #0xdb
+ 6770: 4f06078f movi v15.4s, #0xdc
+ 6774: 4f0607af movi v15.4s, #0xdd
+ 6778: 4f0607cf movi v15.4s, #0xde
+ 677c: 4f0607ef movi v15.4s, #0xdf
+ 6780: 4f07040f movi v15.4s, #0xe0
+ 6784: 4f07042f movi v15.4s, #0xe1
+ 6788: 4f07044f movi v15.4s, #0xe2
+ 678c: 4f07046f movi v15.4s, #0xe3
+ 6790: 4f07048f movi v15.4s, #0xe4
+ 6794: 4f0704af movi v15.4s, #0xe5
+ 6798: 4f0704cf movi v15.4s, #0xe6
+ 679c: 4f0704ef movi v15.4s, #0xe7
+ 67a0: 4f07050f movi v15.4s, #0xe8
+ 67a4: 4f07052f movi v15.4s, #0xe9
+ 67a8: 4f07054f movi v15.4s, #0xea
+ 67ac: 4f07056f movi v15.4s, #0xeb
+ 67b0: 4f07058f movi v15.4s, #0xec
+ 67b4: 4f0705af movi v15.4s, #0xed
+ 67b8: 4f0705cf movi v15.4s, #0xee
+ 67bc: 4f0705ef movi v15.4s, #0xef
+ 67c0: 4f07060f movi v15.4s, #0xf0
+ 67c4: 4f07062f movi v15.4s, #0xf1
+ 67c8: 4f07064f movi v15.4s, #0xf2
+ 67cc: 4f07066f movi v15.4s, #0xf3
+ 67d0: 4f07068f movi v15.4s, #0xf4
+ 67d4: 4f0706af movi v15.4s, #0xf5
+ 67d8: 4f0706cf movi v15.4s, #0xf6
+ 67dc: 4f0706ef movi v15.4s, #0xf7
+ 67e0: 4f07070f movi v15.4s, #0xf8
+ 67e4: 4f07072f movi v15.4s, #0xf9
+ 67e8: 4f07074f movi v15.4s, #0xfa
+ 67ec: 4f07076f movi v15.4s, #0xfb
+ 67f0: 4f07078f movi v15.4s, #0xfc
+ 67f4: 4f0707af movi v15.4s, #0xfd
+ 67f8: 4f0707cf movi v15.4s, #0xfe
+ 67fc: 4f0707ef movi v15.4s, #0xff
+ 6800: 4f002407 movi v7.4s, #0x0, lsl #8
+ 6804: 4f002427 movi v7.4s, #0x1, lsl #8
+ 6808: 4f002447 movi v7.4s, #0x2, lsl #8
+ 680c: 4f002467 movi v7.4s, #0x3, lsl #8
+ 6810: 4f002487 movi v7.4s, #0x4, lsl #8
+ 6814: 4f0024a7 movi v7.4s, #0x5, lsl #8
+ 6818: 4f0024c7 movi v7.4s, #0x6, lsl #8
+ 681c: 4f0024e7 movi v7.4s, #0x7, lsl #8
+ 6820: 4f002507 movi v7.4s, #0x8, lsl #8
+ 6824: 4f002527 movi v7.4s, #0x9, lsl #8
+ 6828: 4f002547 movi v7.4s, #0xa, lsl #8
+ 682c: 4f002567 movi v7.4s, #0xb, lsl #8
+ 6830: 4f002587 movi v7.4s, #0xc, lsl #8
+ 6834: 4f0025a7 movi v7.4s, #0xd, lsl #8
+ 6838: 4f0025c7 movi v7.4s, #0xe, lsl #8
+ 683c: 4f0025e7 movi v7.4s, #0xf, lsl #8
+ 6840: 4f002607 movi v7.4s, #0x10, lsl #8
+ 6844: 4f002627 movi v7.4s, #0x11, lsl #8
+ 6848: 4f002647 movi v7.4s, #0x12, lsl #8
+ 684c: 4f002667 movi v7.4s, #0x13, lsl #8
+ 6850: 4f002687 movi v7.4s, #0x14, lsl #8
+ 6854: 4f0026a7 movi v7.4s, #0x15, lsl #8
+ 6858: 4f0026c7 movi v7.4s, #0x16, lsl #8
+ 685c: 4f0026e7 movi v7.4s, #0x17, lsl #8
+ 6860: 4f002707 movi v7.4s, #0x18, lsl #8
+ 6864: 4f002727 movi v7.4s, #0x19, lsl #8
+ 6868: 4f002747 movi v7.4s, #0x1a, lsl #8
+ 686c: 4f002767 movi v7.4s, #0x1b, lsl #8
+ 6870: 4f002787 movi v7.4s, #0x1c, lsl #8
+ 6874: 4f0027a7 movi v7.4s, #0x1d, lsl #8
+ 6878: 4f0027c7 movi v7.4s, #0x1e, lsl #8
+ 687c: 4f0027e7 movi v7.4s, #0x1f, lsl #8
+ 6880: 4f012407 movi v7.4s, #0x20, lsl #8
+ 6884: 4f012427 movi v7.4s, #0x21, lsl #8
+ 6888: 4f012447 movi v7.4s, #0x22, lsl #8
+ 688c: 4f012467 movi v7.4s, #0x23, lsl #8
+ 6890: 4f012487 movi v7.4s, #0x24, lsl #8
+ 6894: 4f0124a7 movi v7.4s, #0x25, lsl #8
+ 6898: 4f0124c7 movi v7.4s, #0x26, lsl #8
+ 689c: 4f0124e7 movi v7.4s, #0x27, lsl #8
+ 68a0: 4f012507 movi v7.4s, #0x28, lsl #8
+ 68a4: 4f012527 movi v7.4s, #0x29, lsl #8
+ 68a8: 4f012547 movi v7.4s, #0x2a, lsl #8
+ 68ac: 4f012567 movi v7.4s, #0x2b, lsl #8
+ 68b0: 4f012587 movi v7.4s, #0x2c, lsl #8
+ 68b4: 4f0125a7 movi v7.4s, #0x2d, lsl #8
+ 68b8: 4f0125c7 movi v7.4s, #0x2e, lsl #8
+ 68bc: 4f0125e7 movi v7.4s, #0x2f, lsl #8
+ 68c0: 4f012607 movi v7.4s, #0x30, lsl #8
+ 68c4: 4f012627 movi v7.4s, #0x31, lsl #8
+ 68c8: 4f012647 movi v7.4s, #0x32, lsl #8
+ 68cc: 4f012667 movi v7.4s, #0x33, lsl #8
+ 68d0: 4f012687 movi v7.4s, #0x34, lsl #8
+ 68d4: 4f0126a7 movi v7.4s, #0x35, lsl #8
+ 68d8: 4f0126c7 movi v7.4s, #0x36, lsl #8
+ 68dc: 4f0126e7 movi v7.4s, #0x37, lsl #8
+ 68e0: 4f012707 movi v7.4s, #0x38, lsl #8
+ 68e4: 4f012727 movi v7.4s, #0x39, lsl #8
+ 68e8: 4f012747 movi v7.4s, #0x3a, lsl #8
+ 68ec: 4f012767 movi v7.4s, #0x3b, lsl #8
+ 68f0: 4f012787 movi v7.4s, #0x3c, lsl #8
+ 68f4: 4f0127a7 movi v7.4s, #0x3d, lsl #8
+ 68f8: 4f0127c7 movi v7.4s, #0x3e, lsl #8
+ 68fc: 4f0127e7 movi v7.4s, #0x3f, lsl #8
+ 6900: 4f022407 movi v7.4s, #0x40, lsl #8
+ 6904: 4f022427 movi v7.4s, #0x41, lsl #8
+ 6908: 4f022447 movi v7.4s, #0x42, lsl #8
+ 690c: 4f022467 movi v7.4s, #0x43, lsl #8
+ 6910: 4f022487 movi v7.4s, #0x44, lsl #8
+ 6914: 4f0224a7 movi v7.4s, #0x45, lsl #8
+ 6918: 4f0224c7 movi v7.4s, #0x46, lsl #8
+ 691c: 4f0224e7 movi v7.4s, #0x47, lsl #8
+ 6920: 4f022507 movi v7.4s, #0x48, lsl #8
+ 6924: 4f022527 movi v7.4s, #0x49, lsl #8
+ 6928: 4f022547 movi v7.4s, #0x4a, lsl #8
+ 692c: 4f022567 movi v7.4s, #0x4b, lsl #8
+ 6930: 4f022587 movi v7.4s, #0x4c, lsl #8
+ 6934: 4f0225a7 movi v7.4s, #0x4d, lsl #8
+ 6938: 4f0225c7 movi v7.4s, #0x4e, lsl #8
+ 693c: 4f0225e7 movi v7.4s, #0x4f, lsl #8
+ 6940: 4f022607 movi v7.4s, #0x50, lsl #8
+ 6944: 4f022627 movi v7.4s, #0x51, lsl #8
+ 6948: 4f022647 movi v7.4s, #0x52, lsl #8
+ 694c: 4f022667 movi v7.4s, #0x53, lsl #8
+ 6950: 4f022687 movi v7.4s, #0x54, lsl #8
+ 6954: 4f0226a7 movi v7.4s, #0x55, lsl #8
+ 6958: 4f0226c7 movi v7.4s, #0x56, lsl #8
+ 695c: 4f0226e7 movi v7.4s, #0x57, lsl #8
+ 6960: 4f022707 movi v7.4s, #0x58, lsl #8
+ 6964: 4f022727 movi v7.4s, #0x59, lsl #8
+ 6968: 4f022747 movi v7.4s, #0x5a, lsl #8
+ 696c: 4f022767 movi v7.4s, #0x5b, lsl #8
+ 6970: 4f022787 movi v7.4s, #0x5c, lsl #8
+ 6974: 4f0227a7 movi v7.4s, #0x5d, lsl #8
+ 6978: 4f0227c7 movi v7.4s, #0x5e, lsl #8
+ 697c: 4f0227e7 movi v7.4s, #0x5f, lsl #8
+ 6980: 4f032407 movi v7.4s, #0x60, lsl #8
+ 6984: 4f032427 movi v7.4s, #0x61, lsl #8
+ 6988: 4f032447 movi v7.4s, #0x62, lsl #8
+ 698c: 4f032467 movi v7.4s, #0x63, lsl #8
+ 6990: 4f032487 movi v7.4s, #0x64, lsl #8
+ 6994: 4f0324a7 movi v7.4s, #0x65, lsl #8
+ 6998: 4f0324c7 movi v7.4s, #0x66, lsl #8
+ 699c: 4f0324e7 movi v7.4s, #0x67, lsl #8
+ 69a0: 4f032507 movi v7.4s, #0x68, lsl #8
+ 69a4: 4f032527 movi v7.4s, #0x69, lsl #8
+ 69a8: 4f032547 movi v7.4s, #0x6a, lsl #8
+ 69ac: 4f032567 movi v7.4s, #0x6b, lsl #8
+ 69b0: 4f032587 movi v7.4s, #0x6c, lsl #8
+ 69b4: 4f0325a7 movi v7.4s, #0x6d, lsl #8
+ 69b8: 4f0325c7 movi v7.4s, #0x6e, lsl #8
+ 69bc: 4f0325e7 movi v7.4s, #0x6f, lsl #8
+ 69c0: 4f032607 movi v7.4s, #0x70, lsl #8
+ 69c4: 4f032627 movi v7.4s, #0x71, lsl #8
+ 69c8: 4f032647 movi v7.4s, #0x72, lsl #8
+ 69cc: 4f032667 movi v7.4s, #0x73, lsl #8
+ 69d0: 4f032687 movi v7.4s, #0x74, lsl #8
+ 69d4: 4f0326a7 movi v7.4s, #0x75, lsl #8
+ 69d8: 4f0326c7 movi v7.4s, #0x76, lsl #8
+ 69dc: 4f0326e7 movi v7.4s, #0x77, lsl #8
+ 69e0: 4f032707 movi v7.4s, #0x78, lsl #8
+ 69e4: 4f032727 movi v7.4s, #0x79, lsl #8
+ 69e8: 4f032747 movi v7.4s, #0x7a, lsl #8
+ 69ec: 4f032767 movi v7.4s, #0x7b, lsl #8
+ 69f0: 4f032787 movi v7.4s, #0x7c, lsl #8
+ 69f4: 4f0327a7 movi v7.4s, #0x7d, lsl #8
+ 69f8: 4f0327c7 movi v7.4s, #0x7e, lsl #8
+ 69fc: 4f0327e7 movi v7.4s, #0x7f, lsl #8
+ 6a00: 4f042407 movi v7.4s, #0x80, lsl #8
+ 6a04: 4f042427 movi v7.4s, #0x81, lsl #8
+ 6a08: 4f042447 movi v7.4s, #0x82, lsl #8
+ 6a0c: 4f042467 movi v7.4s, #0x83, lsl #8
+ 6a10: 4f042487 movi v7.4s, #0x84, lsl #8
+ 6a14: 4f0424a7 movi v7.4s, #0x85, lsl #8
+ 6a18: 4f0424c7 movi v7.4s, #0x86, lsl #8
+ 6a1c: 4f0424e7 movi v7.4s, #0x87, lsl #8
+ 6a20: 4f042507 movi v7.4s, #0x88, lsl #8
+ 6a24: 4f042527 movi v7.4s, #0x89, lsl #8
+ 6a28: 4f042547 movi v7.4s, #0x8a, lsl #8
+ 6a2c: 4f042567 movi v7.4s, #0x8b, lsl #8
+ 6a30: 4f042587 movi v7.4s, #0x8c, lsl #8
+ 6a34: 4f0425a7 movi v7.4s, #0x8d, lsl #8
+ 6a38: 4f0425c7 movi v7.4s, #0x8e, lsl #8
+ 6a3c: 4f0425e7 movi v7.4s, #0x8f, lsl #8
+ 6a40: 4f042607 movi v7.4s, #0x90, lsl #8
+ 6a44: 4f042627 movi v7.4s, #0x91, lsl #8
+ 6a48: 4f042647 movi v7.4s, #0x92, lsl #8
+ 6a4c: 4f042667 movi v7.4s, #0x93, lsl #8
+ 6a50: 4f042687 movi v7.4s, #0x94, lsl #8
+ 6a54: 4f0426a7 movi v7.4s, #0x95, lsl #8
+ 6a58: 4f0426c7 movi v7.4s, #0x96, lsl #8
+ 6a5c: 4f0426e7 movi v7.4s, #0x97, lsl #8
+ 6a60: 4f042707 movi v7.4s, #0x98, lsl #8
+ 6a64: 4f042727 movi v7.4s, #0x99, lsl #8
+ 6a68: 4f042747 movi v7.4s, #0x9a, lsl #8
+ 6a6c: 4f042767 movi v7.4s, #0x9b, lsl #8
+ 6a70: 4f042787 movi v7.4s, #0x9c, lsl #8
+ 6a74: 4f0427a7 movi v7.4s, #0x9d, lsl #8
+ 6a78: 4f0427c7 movi v7.4s, #0x9e, lsl #8
+ 6a7c: 4f0427e7 movi v7.4s, #0x9f, lsl #8
+ 6a80: 4f052407 movi v7.4s, #0xa0, lsl #8
+ 6a84: 4f052427 movi v7.4s, #0xa1, lsl #8
+ 6a88: 4f052447 movi v7.4s, #0xa2, lsl #8
+ 6a8c: 4f052467 movi v7.4s, #0xa3, lsl #8
+ 6a90: 4f052487 movi v7.4s, #0xa4, lsl #8
+ 6a94: 4f0524a7 movi v7.4s, #0xa5, lsl #8
+ 6a98: 4f0524c7 movi v7.4s, #0xa6, lsl #8
+ 6a9c: 4f0524e7 movi v7.4s, #0xa7, lsl #8
+ 6aa0: 4f052507 movi v7.4s, #0xa8, lsl #8
+ 6aa4: 4f052527 movi v7.4s, #0xa9, lsl #8
+ 6aa8: 4f052547 movi v7.4s, #0xaa, lsl #8
+ 6aac: 4f052567 movi v7.4s, #0xab, lsl #8
+ 6ab0: 4f052587 movi v7.4s, #0xac, lsl #8
+ 6ab4: 4f0525a7 movi v7.4s, #0xad, lsl #8
+ 6ab8: 4f0525c7 movi v7.4s, #0xae, lsl #8
+ 6abc: 4f0525e7 movi v7.4s, #0xaf, lsl #8
+ 6ac0: 4f052607 movi v7.4s, #0xb0, lsl #8
+ 6ac4: 4f052627 movi v7.4s, #0xb1, lsl #8
+ 6ac8: 4f052647 movi v7.4s, #0xb2, lsl #8
+ 6acc: 4f052667 movi v7.4s, #0xb3, lsl #8
+ 6ad0: 4f052687 movi v7.4s, #0xb4, lsl #8
+ 6ad4: 4f0526a7 movi v7.4s, #0xb5, lsl #8
+ 6ad8: 4f0526c7 movi v7.4s, #0xb6, lsl #8
+ 6adc: 4f0526e7 movi v7.4s, #0xb7, lsl #8
+ 6ae0: 4f052707 movi v7.4s, #0xb8, lsl #8
+ 6ae4: 4f052727 movi v7.4s, #0xb9, lsl #8
+ 6ae8: 4f052747 movi v7.4s, #0xba, lsl #8
+ 6aec: 4f052767 movi v7.4s, #0xbb, lsl #8
+ 6af0: 4f052787 movi v7.4s, #0xbc, lsl #8
+ 6af4: 4f0527a7 movi v7.4s, #0xbd, lsl #8
+ 6af8: 4f0527c7 movi v7.4s, #0xbe, lsl #8
+ 6afc: 4f0527e7 movi v7.4s, #0xbf, lsl #8
+ 6b00: 4f062407 movi v7.4s, #0xc0, lsl #8
+ 6b04: 4f062427 movi v7.4s, #0xc1, lsl #8
+ 6b08: 4f062447 movi v7.4s, #0xc2, lsl #8
+ 6b0c: 4f062467 movi v7.4s, #0xc3, lsl #8
+ 6b10: 4f062487 movi v7.4s, #0xc4, lsl #8
+ 6b14: 4f0624a7 movi v7.4s, #0xc5, lsl #8
+ 6b18: 4f0624c7 movi v7.4s, #0xc6, lsl #8
+ 6b1c: 4f0624e7 movi v7.4s, #0xc7, lsl #8
+ 6b20: 4f062507 movi v7.4s, #0xc8, lsl #8
+ 6b24: 4f062527 movi v7.4s, #0xc9, lsl #8
+ 6b28: 4f062547 movi v7.4s, #0xca, lsl #8
+ 6b2c: 4f062567 movi v7.4s, #0xcb, lsl #8
+ 6b30: 4f062587 movi v7.4s, #0xcc, lsl #8
+ 6b34: 4f0625a7 movi v7.4s, #0xcd, lsl #8
+ 6b38: 4f0625c7 movi v7.4s, #0xce, lsl #8
+ 6b3c: 4f0625e7 movi v7.4s, #0xcf, lsl #8
+ 6b40: 4f062607 movi v7.4s, #0xd0, lsl #8
+ 6b44: 4f062627 movi v7.4s, #0xd1, lsl #8
+ 6b48: 4f062647 movi v7.4s, #0xd2, lsl #8
+ 6b4c: 4f062667 movi v7.4s, #0xd3, lsl #8
+ 6b50: 4f062687 movi v7.4s, #0xd4, lsl #8
+ 6b54: 4f0626a7 movi v7.4s, #0xd5, lsl #8
+ 6b58: 4f0626c7 movi v7.4s, #0xd6, lsl #8
+ 6b5c: 4f0626e7 movi v7.4s, #0xd7, lsl #8
+ 6b60: 4f062707 movi v7.4s, #0xd8, lsl #8
+ 6b64: 4f062727 movi v7.4s, #0xd9, lsl #8
+ 6b68: 4f062747 movi v7.4s, #0xda, lsl #8
+ 6b6c: 4f062767 movi v7.4s, #0xdb, lsl #8
+ 6b70: 4f062787 movi v7.4s, #0xdc, lsl #8
+ 6b74: 4f0627a7 movi v7.4s, #0xdd, lsl #8
+ 6b78: 4f0627c7 movi v7.4s, #0xde, lsl #8
+ 6b7c: 4f0627e7 movi v7.4s, #0xdf, lsl #8
+ 6b80: 4f072407 movi v7.4s, #0xe0, lsl #8
+ 6b84: 4f072427 movi v7.4s, #0xe1, lsl #8
+ 6b88: 4f072447 movi v7.4s, #0xe2, lsl #8
+ 6b8c: 4f072467 movi v7.4s, #0xe3, lsl #8
+ 6b90: 4f072487 movi v7.4s, #0xe4, lsl #8
+ 6b94: 4f0724a7 movi v7.4s, #0xe5, lsl #8
+ 6b98: 4f0724c7 movi v7.4s, #0xe6, lsl #8
+ 6b9c: 4f0724e7 movi v7.4s, #0xe7, lsl #8
+ 6ba0: 4f072507 movi v7.4s, #0xe8, lsl #8
+ 6ba4: 4f072527 movi v7.4s, #0xe9, lsl #8
+ 6ba8: 4f072547 movi v7.4s, #0xea, lsl #8
+ 6bac: 4f072567 movi v7.4s, #0xeb, lsl #8
+ 6bb0: 4f072587 movi v7.4s, #0xec, lsl #8
+ 6bb4: 4f0725a7 movi v7.4s, #0xed, lsl #8
+ 6bb8: 4f0725c7 movi v7.4s, #0xee, lsl #8
+ 6bbc: 4f0725e7 movi v7.4s, #0xef, lsl #8
+ 6bc0: 4f072607 movi v7.4s, #0xf0, lsl #8
+ 6bc4: 4f072627 movi v7.4s, #0xf1, lsl #8
+ 6bc8: 4f072647 movi v7.4s, #0xf2, lsl #8
+ 6bcc: 4f072667 movi v7.4s, #0xf3, lsl #8
+ 6bd0: 4f072687 movi v7.4s, #0xf4, lsl #8
+ 6bd4: 4f0726a7 movi v7.4s, #0xf5, lsl #8
+ 6bd8: 4f0726c7 movi v7.4s, #0xf6, lsl #8
+ 6bdc: 4f0726e7 movi v7.4s, #0xf7, lsl #8
+ 6be0: 4f072707 movi v7.4s, #0xf8, lsl #8
+ 6be4: 4f072727 movi v7.4s, #0xf9, lsl #8
+ 6be8: 4f072747 movi v7.4s, #0xfa, lsl #8
+ 6bec: 4f072767 movi v7.4s, #0xfb, lsl #8
+ 6bf0: 4f072787 movi v7.4s, #0xfc, lsl #8
+ 6bf4: 4f0727a7 movi v7.4s, #0xfd, lsl #8
+ 6bf8: 4f0727c7 movi v7.4s, #0xfe, lsl #8
+ 6bfc: 4f0727e7 movi v7.4s, #0xff, lsl #8
+ 6c00: 4f00040f movi v15.4s, #0x0
+ 6c04: 4f00042f movi v15.4s, #0x1
+ 6c08: 4f00044f movi v15.4s, #0x2
+ 6c0c: 4f00046f movi v15.4s, #0x3
+ 6c10: 4f00048f movi v15.4s, #0x4
+ 6c14: 4f0004af movi v15.4s, #0x5
+ 6c18: 4f0004cf movi v15.4s, #0x6
+ 6c1c: 4f0004ef movi v15.4s, #0x7
+ 6c20: 4f00050f movi v15.4s, #0x8
+ 6c24: 4f00052f movi v15.4s, #0x9
+ 6c28: 4f00054f movi v15.4s, #0xa
+ 6c2c: 4f00056f movi v15.4s, #0xb
+ 6c30: 4f00058f movi v15.4s, #0xc
+ 6c34: 4f0005af movi v15.4s, #0xd
+ 6c38: 4f0005cf movi v15.4s, #0xe
+ 6c3c: 4f0005ef movi v15.4s, #0xf
+ 6c40: 4f00060f movi v15.4s, #0x10
+ 6c44: 4f00062f movi v15.4s, #0x11
+ 6c48: 4f00064f movi v15.4s, #0x12
+ 6c4c: 4f00066f movi v15.4s, #0x13
+ 6c50: 4f00068f movi v15.4s, #0x14
+ 6c54: 4f0006af movi v15.4s, #0x15
+ 6c58: 4f0006cf movi v15.4s, #0x16
+ 6c5c: 4f0006ef movi v15.4s, #0x17
+ 6c60: 4f00070f movi v15.4s, #0x18
+ 6c64: 4f00072f movi v15.4s, #0x19
+ 6c68: 4f00074f movi v15.4s, #0x1a
+ 6c6c: 4f00076f movi v15.4s, #0x1b
+ 6c70: 4f00078f movi v15.4s, #0x1c
+ 6c74: 4f0007af movi v15.4s, #0x1d
+ 6c78: 4f0007cf movi v15.4s, #0x1e
+ 6c7c: 4f0007ef movi v15.4s, #0x1f
+ 6c80: 4f01040f movi v15.4s, #0x20
+ 6c84: 4f01042f movi v15.4s, #0x21
+ 6c88: 4f01044f movi v15.4s, #0x22
+ 6c8c: 4f01046f movi v15.4s, #0x23
+ 6c90: 4f01048f movi v15.4s, #0x24
+ 6c94: 4f0104af movi v15.4s, #0x25
+ 6c98: 4f0104cf movi v15.4s, #0x26
+ 6c9c: 4f0104ef movi v15.4s, #0x27
+ 6ca0: 4f01050f movi v15.4s, #0x28
+ 6ca4: 4f01052f movi v15.4s, #0x29
+ 6ca8: 4f01054f movi v15.4s, #0x2a
+ 6cac: 4f01056f movi v15.4s, #0x2b
+ 6cb0: 4f01058f movi v15.4s, #0x2c
+ 6cb4: 4f0105af movi v15.4s, #0x2d
+ 6cb8: 4f0105cf movi v15.4s, #0x2e
+ 6cbc: 4f0105ef movi v15.4s, #0x2f
+ 6cc0: 4f01060f movi v15.4s, #0x30
+ 6cc4: 4f01062f movi v15.4s, #0x31
+ 6cc8: 4f01064f movi v15.4s, #0x32
+ 6ccc: 4f01066f movi v15.4s, #0x33
+ 6cd0: 4f01068f movi v15.4s, #0x34
+ 6cd4: 4f0106af movi v15.4s, #0x35
+ 6cd8: 4f0106cf movi v15.4s, #0x36
+ 6cdc: 4f0106ef movi v15.4s, #0x37
+ 6ce0: 4f01070f movi v15.4s, #0x38
+ 6ce4: 4f01072f movi v15.4s, #0x39
+ 6ce8: 4f01074f movi v15.4s, #0x3a
+ 6cec: 4f01076f movi v15.4s, #0x3b
+ 6cf0: 4f01078f movi v15.4s, #0x3c
+ 6cf4: 4f0107af movi v15.4s, #0x3d
+ 6cf8: 4f0107cf movi v15.4s, #0x3e
+ 6cfc: 4f0107ef movi v15.4s, #0x3f
+ 6d00: 4f02040f movi v15.4s, #0x40
+ 6d04: 4f02042f movi v15.4s, #0x41
+ 6d08: 4f02044f movi v15.4s, #0x42
+ 6d0c: 4f02046f movi v15.4s, #0x43
+ 6d10: 4f02048f movi v15.4s, #0x44
+ 6d14: 4f0204af movi v15.4s, #0x45
+ 6d18: 4f0204cf movi v15.4s, #0x46
+ 6d1c: 4f0204ef movi v15.4s, #0x47
+ 6d20: 4f02050f movi v15.4s, #0x48
+ 6d24: 4f02052f movi v15.4s, #0x49
+ 6d28: 4f02054f movi v15.4s, #0x4a
+ 6d2c: 4f02056f movi v15.4s, #0x4b
+ 6d30: 4f02058f movi v15.4s, #0x4c
+ 6d34: 4f0205af movi v15.4s, #0x4d
+ 6d38: 4f0205cf movi v15.4s, #0x4e
+ 6d3c: 4f0205ef movi v15.4s, #0x4f
+ 6d40: 4f02060f movi v15.4s, #0x50
+ 6d44: 4f02062f movi v15.4s, #0x51
+ 6d48: 4f02064f movi v15.4s, #0x52
+ 6d4c: 4f02066f movi v15.4s, #0x53
+ 6d50: 4f02068f movi v15.4s, #0x54
+ 6d54: 4f0206af movi v15.4s, #0x55
+ 6d58: 4f0206cf movi v15.4s, #0x56
+ 6d5c: 4f0206ef movi v15.4s, #0x57
+ 6d60: 4f02070f movi v15.4s, #0x58
+ 6d64: 4f02072f movi v15.4s, #0x59
+ 6d68: 4f02074f movi v15.4s, #0x5a
+ 6d6c: 4f02076f movi v15.4s, #0x5b
+ 6d70: 4f02078f movi v15.4s, #0x5c
+ 6d74: 4f0207af movi v15.4s, #0x5d
+ 6d78: 4f0207cf movi v15.4s, #0x5e
+ 6d7c: 4f0207ef movi v15.4s, #0x5f
+ 6d80: 4f03040f movi v15.4s, #0x60
+ 6d84: 4f03042f movi v15.4s, #0x61
+ 6d88: 4f03044f movi v15.4s, #0x62
+ 6d8c: 4f03046f movi v15.4s, #0x63
+ 6d90: 4f03048f movi v15.4s, #0x64
+ 6d94: 4f0304af movi v15.4s, #0x65
+ 6d98: 4f0304cf movi v15.4s, #0x66
+ 6d9c: 4f0304ef movi v15.4s, #0x67
+ 6da0: 4f03050f movi v15.4s, #0x68
+ 6da4: 4f03052f movi v15.4s, #0x69
+ 6da8: 4f03054f movi v15.4s, #0x6a
+ 6dac: 4f03056f movi v15.4s, #0x6b
+ 6db0: 4f03058f movi v15.4s, #0x6c
+ 6db4: 4f0305af movi v15.4s, #0x6d
+ 6db8: 4f0305cf movi v15.4s, #0x6e
+ 6dbc: 4f0305ef movi v15.4s, #0x6f
+ 6dc0: 4f03060f movi v15.4s, #0x70
+ 6dc4: 4f03062f movi v15.4s, #0x71
+ 6dc8: 4f03064f movi v15.4s, #0x72
+ 6dcc: 4f03066f movi v15.4s, #0x73
+ 6dd0: 4f03068f movi v15.4s, #0x74
+ 6dd4: 4f0306af movi v15.4s, #0x75
+ 6dd8: 4f0306cf movi v15.4s, #0x76
+ 6ddc: 4f0306ef movi v15.4s, #0x77
+ 6de0: 4f03070f movi v15.4s, #0x78
+ 6de4: 4f03072f movi v15.4s, #0x79
+ 6de8: 4f03074f movi v15.4s, #0x7a
+ 6dec: 4f03076f movi v15.4s, #0x7b
+ 6df0: 4f03078f movi v15.4s, #0x7c
+ 6df4: 4f0307af movi v15.4s, #0x7d
+ 6df8: 4f0307cf movi v15.4s, #0x7e
+ 6dfc: 4f0307ef movi v15.4s, #0x7f
+ 6e00: 4f04040f movi v15.4s, #0x80
+ 6e04: 4f04042f movi v15.4s, #0x81
+ 6e08: 4f04044f movi v15.4s, #0x82
+ 6e0c: 4f04046f movi v15.4s, #0x83
+ 6e10: 4f04048f movi v15.4s, #0x84
+ 6e14: 4f0404af movi v15.4s, #0x85
+ 6e18: 4f0404cf movi v15.4s, #0x86
+ 6e1c: 4f0404ef movi v15.4s, #0x87
+ 6e20: 4f04050f movi v15.4s, #0x88
+ 6e24: 4f04052f movi v15.4s, #0x89
+ 6e28: 4f04054f movi v15.4s, #0x8a
+ 6e2c: 4f04056f movi v15.4s, #0x8b
+ 6e30: 4f04058f movi v15.4s, #0x8c
+ 6e34: 4f0405af movi v15.4s, #0x8d
+ 6e38: 4f0405cf movi v15.4s, #0x8e
+ 6e3c: 4f0405ef movi v15.4s, #0x8f
+ 6e40: 4f04060f movi v15.4s, #0x90
+ 6e44: 4f04062f movi v15.4s, #0x91
+ 6e48: 4f04064f movi v15.4s, #0x92
+ 6e4c: 4f04066f movi v15.4s, #0x93
+ 6e50: 4f04068f movi v15.4s, #0x94
+ 6e54: 4f0406af movi v15.4s, #0x95
+ 6e58: 4f0406cf movi v15.4s, #0x96
+ 6e5c: 4f0406ef movi v15.4s, #0x97
+ 6e60: 4f04070f movi v15.4s, #0x98
+ 6e64: 4f04072f movi v15.4s, #0x99
+ 6e68: 4f04074f movi v15.4s, #0x9a
+ 6e6c: 4f04076f movi v15.4s, #0x9b
+ 6e70: 4f04078f movi v15.4s, #0x9c
+ 6e74: 4f0407af movi v15.4s, #0x9d
+ 6e78: 4f0407cf movi v15.4s, #0x9e
+ 6e7c: 4f0407ef movi v15.4s, #0x9f
+ 6e80: 4f05040f movi v15.4s, #0xa0
+ 6e84: 4f05042f movi v15.4s, #0xa1
+ 6e88: 4f05044f movi v15.4s, #0xa2
+ 6e8c: 4f05046f movi v15.4s, #0xa3
+ 6e90: 4f05048f movi v15.4s, #0xa4
+ 6e94: 4f0504af movi v15.4s, #0xa5
+ 6e98: 4f0504cf movi v15.4s, #0xa6
+ 6e9c: 4f0504ef movi v15.4s, #0xa7
+ 6ea0: 4f05050f movi v15.4s, #0xa8
+ 6ea4: 4f05052f movi v15.4s, #0xa9
+ 6ea8: 4f05054f movi v15.4s, #0xaa
+ 6eac: 4f05056f movi v15.4s, #0xab
+ 6eb0: 4f05058f movi v15.4s, #0xac
+ 6eb4: 4f0505af movi v15.4s, #0xad
+ 6eb8: 4f0505cf movi v15.4s, #0xae
+ 6ebc: 4f0505ef movi v15.4s, #0xaf
+ 6ec0: 4f05060f movi v15.4s, #0xb0
+ 6ec4: 4f05062f movi v15.4s, #0xb1
+ 6ec8: 4f05064f movi v15.4s, #0xb2
+ 6ecc: 4f05066f movi v15.4s, #0xb3
+ 6ed0: 4f05068f movi v15.4s, #0xb4
+ 6ed4: 4f0506af movi v15.4s, #0xb5
+ 6ed8: 4f0506cf movi v15.4s, #0xb6
+ 6edc: 4f0506ef movi v15.4s, #0xb7
+ 6ee0: 4f05070f movi v15.4s, #0xb8
+ 6ee4: 4f05072f movi v15.4s, #0xb9
+ 6ee8: 4f05074f movi v15.4s, #0xba
+ 6eec: 4f05076f movi v15.4s, #0xbb
+ 6ef0: 4f05078f movi v15.4s, #0xbc
+ 6ef4: 4f0507af movi v15.4s, #0xbd
+ 6ef8: 4f0507cf movi v15.4s, #0xbe
+ 6efc: 4f0507ef movi v15.4s, #0xbf
+ 6f00: 4f06040f movi v15.4s, #0xc0
+ 6f04: 4f06042f movi v15.4s, #0xc1
+ 6f08: 4f06044f movi v15.4s, #0xc2
+ 6f0c: 4f06046f movi v15.4s, #0xc3
+ 6f10: 4f06048f movi v15.4s, #0xc4
+ 6f14: 4f0604af movi v15.4s, #0xc5
+ 6f18: 4f0604cf movi v15.4s, #0xc6
+ 6f1c: 4f0604ef movi v15.4s, #0xc7
+ 6f20: 4f06050f movi v15.4s, #0xc8
+ 6f24: 4f06052f movi v15.4s, #0xc9
+ 6f28: 4f06054f movi v15.4s, #0xca
+ 6f2c: 4f06056f movi v15.4s, #0xcb
+ 6f30: 4f06058f movi v15.4s, #0xcc
+ 6f34: 4f0605af movi v15.4s, #0xcd
+ 6f38: 4f0605cf movi v15.4s, #0xce
+ 6f3c: 4f0605ef movi v15.4s, #0xcf
+ 6f40: 4f06060f movi v15.4s, #0xd0
+ 6f44: 4f06062f movi v15.4s, #0xd1
+ 6f48: 4f06064f movi v15.4s, #0xd2
+ 6f4c: 4f06066f movi v15.4s, #0xd3
+ 6f50: 4f06068f movi v15.4s, #0xd4
+ 6f54: 4f0606af movi v15.4s, #0xd5
+ 6f58: 4f0606cf movi v15.4s, #0xd6
+ 6f5c: 4f0606ef movi v15.4s, #0xd7
+ 6f60: 4f06070f movi v15.4s, #0xd8
+ 6f64: 4f06072f movi v15.4s, #0xd9
+ 6f68: 4f06074f movi v15.4s, #0xda
+ 6f6c: 4f06076f movi v15.4s, #0xdb
+ 6f70: 4f06078f movi v15.4s, #0xdc
+ 6f74: 4f0607af movi v15.4s, #0xdd
+ 6f78: 4f0607cf movi v15.4s, #0xde
+ 6f7c: 4f0607ef movi v15.4s, #0xdf
+ 6f80: 4f07040f movi v15.4s, #0xe0
+ 6f84: 4f07042f movi v15.4s, #0xe1
+ 6f88: 4f07044f movi v15.4s, #0xe2
+ 6f8c: 4f07046f movi v15.4s, #0xe3
+ 6f90: 4f07048f movi v15.4s, #0xe4
+ 6f94: 4f0704af movi v15.4s, #0xe5
+ 6f98: 4f0704cf movi v15.4s, #0xe6
+ 6f9c: 4f0704ef movi v15.4s, #0xe7
+ 6fa0: 4f07050f movi v15.4s, #0xe8
+ 6fa4: 4f07052f movi v15.4s, #0xe9
+ 6fa8: 4f07054f movi v15.4s, #0xea
+ 6fac: 4f07056f movi v15.4s, #0xeb
+ 6fb0: 4f07058f movi v15.4s, #0xec
+ 6fb4: 4f0705af movi v15.4s, #0xed
+ 6fb8: 4f0705cf movi v15.4s, #0xee
+ 6fbc: 4f0705ef movi v15.4s, #0xef
+ 6fc0: 4f07060f movi v15.4s, #0xf0
+ 6fc4: 4f07062f movi v15.4s, #0xf1
+ 6fc8: 4f07064f movi v15.4s, #0xf2
+ 6fcc: 4f07066f movi v15.4s, #0xf3
+ 6fd0: 4f07068f movi v15.4s, #0xf4
+ 6fd4: 4f0706af movi v15.4s, #0xf5
+ 6fd8: 4f0706cf movi v15.4s, #0xf6
+ 6fdc: 4f0706ef movi v15.4s, #0xf7
+ 6fe0: 4f07070f movi v15.4s, #0xf8
+ 6fe4: 4f07072f movi v15.4s, #0xf9
+ 6fe8: 4f07074f movi v15.4s, #0xfa
+ 6fec: 4f07076f movi v15.4s, #0xfb
+ 6ff0: 4f07078f movi v15.4s, #0xfc
+ 6ff4: 4f0707af movi v15.4s, #0xfd
+ 6ff8: 4f0707cf movi v15.4s, #0xfe
+ 6ffc: 4f0707ef movi v15.4s, #0xff
+ 7000: 4f004407 movi v7.4s, #0x0, lsl #16
+ 7004: 4f004427 movi v7.4s, #0x1, lsl #16
+ 7008: 4f004447 movi v7.4s, #0x2, lsl #16
+ 700c: 4f004467 movi v7.4s, #0x3, lsl #16
+ 7010: 4f004487 movi v7.4s, #0x4, lsl #16
+ 7014: 4f0044a7 movi v7.4s, #0x5, lsl #16
+ 7018: 4f0044c7 movi v7.4s, #0x6, lsl #16
+ 701c: 4f0044e7 movi v7.4s, #0x7, lsl #16
+ 7020: 4f004507 movi v7.4s, #0x8, lsl #16
+ 7024: 4f004527 movi v7.4s, #0x9, lsl #16
+ 7028: 4f004547 movi v7.4s, #0xa, lsl #16
+ 702c: 4f004567 movi v7.4s, #0xb, lsl #16
+ 7030: 4f004587 movi v7.4s, #0xc, lsl #16
+ 7034: 4f0045a7 movi v7.4s, #0xd, lsl #16
+ 7038: 4f0045c7 movi v7.4s, #0xe, lsl #16
+ 703c: 4f0045e7 movi v7.4s, #0xf, lsl #16
+ 7040: 4f004607 movi v7.4s, #0x10, lsl #16
+ 7044: 4f004627 movi v7.4s, #0x11, lsl #16
+ 7048: 4f004647 movi v7.4s, #0x12, lsl #16
+ 704c: 4f004667 movi v7.4s, #0x13, lsl #16
+ 7050: 4f004687 movi v7.4s, #0x14, lsl #16
+ 7054: 4f0046a7 movi v7.4s, #0x15, lsl #16
+ 7058: 4f0046c7 movi v7.4s, #0x16, lsl #16
+ 705c: 4f0046e7 movi v7.4s, #0x17, lsl #16
+ 7060: 4f004707 movi v7.4s, #0x18, lsl #16
+ 7064: 4f004727 movi v7.4s, #0x19, lsl #16
+ 7068: 4f004747 movi v7.4s, #0x1a, lsl #16
+ 706c: 4f004767 movi v7.4s, #0x1b, lsl #16
+ 7070: 4f004787 movi v7.4s, #0x1c, lsl #16
+ 7074: 4f0047a7 movi v7.4s, #0x1d, lsl #16
+ 7078: 4f0047c7 movi v7.4s, #0x1e, lsl #16
+ 707c: 4f0047e7 movi v7.4s, #0x1f, lsl #16
+ 7080: 4f014407 movi v7.4s, #0x20, lsl #16
+ 7084: 4f014427 movi v7.4s, #0x21, lsl #16
+ 7088: 4f014447 movi v7.4s, #0x22, lsl #16
+ 708c: 4f014467 movi v7.4s, #0x23, lsl #16
+ 7090: 4f014487 movi v7.4s, #0x24, lsl #16
+ 7094: 4f0144a7 movi v7.4s, #0x25, lsl #16
+ 7098: 4f0144c7 movi v7.4s, #0x26, lsl #16
+ 709c: 4f0144e7 movi v7.4s, #0x27, lsl #16
+ 70a0: 4f014507 movi v7.4s, #0x28, lsl #16
+ 70a4: 4f014527 movi v7.4s, #0x29, lsl #16
+ 70a8: 4f014547 movi v7.4s, #0x2a, lsl #16
+ 70ac: 4f014567 movi v7.4s, #0x2b, lsl #16
+ 70b0: 4f014587 movi v7.4s, #0x2c, lsl #16
+ 70b4: 4f0145a7 movi v7.4s, #0x2d, lsl #16
+ 70b8: 4f0145c7 movi v7.4s, #0x2e, lsl #16
+ 70bc: 4f0145e7 movi v7.4s, #0x2f, lsl #16
+ 70c0: 4f014607 movi v7.4s, #0x30, lsl #16
+ 70c4: 4f014627 movi v7.4s, #0x31, lsl #16
+ 70c8: 4f014647 movi v7.4s, #0x32, lsl #16
+ 70cc: 4f014667 movi v7.4s, #0x33, lsl #16
+ 70d0: 4f014687 movi v7.4s, #0x34, lsl #16
+ 70d4: 4f0146a7 movi v7.4s, #0x35, lsl #16
+ 70d8: 4f0146c7 movi v7.4s, #0x36, lsl #16
+ 70dc: 4f0146e7 movi v7.4s, #0x37, lsl #16
+ 70e0: 4f014707 movi v7.4s, #0x38, lsl #16
+ 70e4: 4f014727 movi v7.4s, #0x39, lsl #16
+ 70e8: 4f014747 movi v7.4s, #0x3a, lsl #16
+ 70ec: 4f014767 movi v7.4s, #0x3b, lsl #16
+ 70f0: 4f014787 movi v7.4s, #0x3c, lsl #16
+ 70f4: 4f0147a7 movi v7.4s, #0x3d, lsl #16
+ 70f8: 4f0147c7 movi v7.4s, #0x3e, lsl #16
+ 70fc: 4f0147e7 movi v7.4s, #0x3f, lsl #16
+ 7100: 4f024407 movi v7.4s, #0x40, lsl #16
+ 7104: 4f024427 movi v7.4s, #0x41, lsl #16
+ 7108: 4f024447 movi v7.4s, #0x42, lsl #16
+ 710c: 4f024467 movi v7.4s, #0x43, lsl #16
+ 7110: 4f024487 movi v7.4s, #0x44, lsl #16
+ 7114: 4f0244a7 movi v7.4s, #0x45, lsl #16
+ 7118: 4f0244c7 movi v7.4s, #0x46, lsl #16
+ 711c: 4f0244e7 movi v7.4s, #0x47, lsl #16
+ 7120: 4f024507 movi v7.4s, #0x48, lsl #16
+ 7124: 4f024527 movi v7.4s, #0x49, lsl #16
+ 7128: 4f024547 movi v7.4s, #0x4a, lsl #16
+ 712c: 4f024567 movi v7.4s, #0x4b, lsl #16
+ 7130: 4f024587 movi v7.4s, #0x4c, lsl #16
+ 7134: 4f0245a7 movi v7.4s, #0x4d, lsl #16
+ 7138: 4f0245c7 movi v7.4s, #0x4e, lsl #16
+ 713c: 4f0245e7 movi v7.4s, #0x4f, lsl #16
+ 7140: 4f024607 movi v7.4s, #0x50, lsl #16
+ 7144: 4f024627 movi v7.4s, #0x51, lsl #16
+ 7148: 4f024647 movi v7.4s, #0x52, lsl #16
+ 714c: 4f024667 movi v7.4s, #0x53, lsl #16
+ 7150: 4f024687 movi v7.4s, #0x54, lsl #16
+ 7154: 4f0246a7 movi v7.4s, #0x55, lsl #16
+ 7158: 4f0246c7 movi v7.4s, #0x56, lsl #16
+ 715c: 4f0246e7 movi v7.4s, #0x57, lsl #16
+ 7160: 4f024707 movi v7.4s, #0x58, lsl #16
+ 7164: 4f024727 movi v7.4s, #0x59, lsl #16
+ 7168: 4f024747 movi v7.4s, #0x5a, lsl #16
+ 716c: 4f024767 movi v7.4s, #0x5b, lsl #16
+ 7170: 4f024787 movi v7.4s, #0x5c, lsl #16
+ 7174: 4f0247a7 movi v7.4s, #0x5d, lsl #16
+ 7178: 4f0247c7 movi v7.4s, #0x5e, lsl #16
+ 717c: 4f0247e7 movi v7.4s, #0x5f, lsl #16
+ 7180: 4f034407 movi v7.4s, #0x60, lsl #16
+ 7184: 4f034427 movi v7.4s, #0x61, lsl #16
+ 7188: 4f034447 movi v7.4s, #0x62, lsl #16
+ 718c: 4f034467 movi v7.4s, #0x63, lsl #16
+ 7190: 4f034487 movi v7.4s, #0x64, lsl #16
+ 7194: 4f0344a7 movi v7.4s, #0x65, lsl #16
+ 7198: 4f0344c7 movi v7.4s, #0x66, lsl #16
+ 719c: 4f0344e7 movi v7.4s, #0x67, lsl #16
+ 71a0: 4f034507 movi v7.4s, #0x68, lsl #16
+ 71a4: 4f034527 movi v7.4s, #0x69, lsl #16
+ 71a8: 4f034547 movi v7.4s, #0x6a, lsl #16
+ 71ac: 4f034567 movi v7.4s, #0x6b, lsl #16
+ 71b0: 4f034587 movi v7.4s, #0x6c, lsl #16
+ 71b4: 4f0345a7 movi v7.4s, #0x6d, lsl #16
+ 71b8: 4f0345c7 movi v7.4s, #0x6e, lsl #16
+ 71bc: 4f0345e7 movi v7.4s, #0x6f, lsl #16
+ 71c0: 4f034607 movi v7.4s, #0x70, lsl #16
+ 71c4: 4f034627 movi v7.4s, #0x71, lsl #16
+ 71c8: 4f034647 movi v7.4s, #0x72, lsl #16
+ 71cc: 4f034667 movi v7.4s, #0x73, lsl #16
+ 71d0: 4f034687 movi v7.4s, #0x74, lsl #16
+ 71d4: 4f0346a7 movi v7.4s, #0x75, lsl #16
+ 71d8: 4f0346c7 movi v7.4s, #0x76, lsl #16
+ 71dc: 4f0346e7 movi v7.4s, #0x77, lsl #16
+ 71e0: 4f034707 movi v7.4s, #0x78, lsl #16
+ 71e4: 4f034727 movi v7.4s, #0x79, lsl #16
+ 71e8: 4f034747 movi v7.4s, #0x7a, lsl #16
+ 71ec: 4f034767 movi v7.4s, #0x7b, lsl #16
+ 71f0: 4f034787 movi v7.4s, #0x7c, lsl #16
+ 71f4: 4f0347a7 movi v7.4s, #0x7d, lsl #16
+ 71f8: 4f0347c7 movi v7.4s, #0x7e, lsl #16
+ 71fc: 4f0347e7 movi v7.4s, #0x7f, lsl #16
+ 7200: 4f044407 movi v7.4s, #0x80, lsl #16
+ 7204: 4f044427 movi v7.4s, #0x81, lsl #16
+ 7208: 4f044447 movi v7.4s, #0x82, lsl #16
+ 720c: 4f044467 movi v7.4s, #0x83, lsl #16
+ 7210: 4f044487 movi v7.4s, #0x84, lsl #16
+ 7214: 4f0444a7 movi v7.4s, #0x85, lsl #16
+ 7218: 4f0444c7 movi v7.4s, #0x86, lsl #16
+ 721c: 4f0444e7 movi v7.4s, #0x87, lsl #16
+ 7220: 4f044507 movi v7.4s, #0x88, lsl #16
+ 7224: 4f044527 movi v7.4s, #0x89, lsl #16
+ 7228: 4f044547 movi v7.4s, #0x8a, lsl #16
+ 722c: 4f044567 movi v7.4s, #0x8b, lsl #16
+ 7230: 4f044587 movi v7.4s, #0x8c, lsl #16
+ 7234: 4f0445a7 movi v7.4s, #0x8d, lsl #16
+ 7238: 4f0445c7 movi v7.4s, #0x8e, lsl #16
+ 723c: 4f0445e7 movi v7.4s, #0x8f, lsl #16
+ 7240: 4f044607 movi v7.4s, #0x90, lsl #16
+ 7244: 4f044627 movi v7.4s, #0x91, lsl #16
+ 7248: 4f044647 movi v7.4s, #0x92, lsl #16
+ 724c: 4f044667 movi v7.4s, #0x93, lsl #16
+ 7250: 4f044687 movi v7.4s, #0x94, lsl #16
+ 7254: 4f0446a7 movi v7.4s, #0x95, lsl #16
+ 7258: 4f0446c7 movi v7.4s, #0x96, lsl #16
+ 725c: 4f0446e7 movi v7.4s, #0x97, lsl #16
+ 7260: 4f044707 movi v7.4s, #0x98, lsl #16
+ 7264: 4f044727 movi v7.4s, #0x99, lsl #16
+ 7268: 4f044747 movi v7.4s, #0x9a, lsl #16
+ 726c: 4f044767 movi v7.4s, #0x9b, lsl #16
+ 7270: 4f044787 movi v7.4s, #0x9c, lsl #16
+ 7274: 4f0447a7 movi v7.4s, #0x9d, lsl #16
+ 7278: 4f0447c7 movi v7.4s, #0x9e, lsl #16
+ 727c: 4f0447e7 movi v7.4s, #0x9f, lsl #16
+ 7280: 4f054407 movi v7.4s, #0xa0, lsl #16
+ 7284: 4f054427 movi v7.4s, #0xa1, lsl #16
+ 7288: 4f054447 movi v7.4s, #0xa2, lsl #16
+ 728c: 4f054467 movi v7.4s, #0xa3, lsl #16
+ 7290: 4f054487 movi v7.4s, #0xa4, lsl #16
+ 7294: 4f0544a7 movi v7.4s, #0xa5, lsl #16
+ 7298: 4f0544c7 movi v7.4s, #0xa6, lsl #16
+ 729c: 4f0544e7 movi v7.4s, #0xa7, lsl #16
+ 72a0: 4f054507 movi v7.4s, #0xa8, lsl #16
+ 72a4: 4f054527 movi v7.4s, #0xa9, lsl #16
+ 72a8: 4f054547 movi v7.4s, #0xaa, lsl #16
+ 72ac: 4f054567 movi v7.4s, #0xab, lsl #16
+ 72b0: 4f054587 movi v7.4s, #0xac, lsl #16
+ 72b4: 4f0545a7 movi v7.4s, #0xad, lsl #16
+ 72b8: 4f0545c7 movi v7.4s, #0xae, lsl #16
+ 72bc: 4f0545e7 movi v7.4s, #0xaf, lsl #16
+ 72c0: 4f054607 movi v7.4s, #0xb0, lsl #16
+ 72c4: 4f054627 movi v7.4s, #0xb1, lsl #16
+ 72c8: 4f054647 movi v7.4s, #0xb2, lsl #16
+ 72cc: 4f054667 movi v7.4s, #0xb3, lsl #16
+ 72d0: 4f054687 movi v7.4s, #0xb4, lsl #16
+ 72d4: 4f0546a7 movi v7.4s, #0xb5, lsl #16
+ 72d8: 4f0546c7 movi v7.4s, #0xb6, lsl #16
+ 72dc: 4f0546e7 movi v7.4s, #0xb7, lsl #16
+ 72e0: 4f054707 movi v7.4s, #0xb8, lsl #16
+ 72e4: 4f054727 movi v7.4s, #0xb9, lsl #16
+ 72e8: 4f054747 movi v7.4s, #0xba, lsl #16
+ 72ec: 4f054767 movi v7.4s, #0xbb, lsl #16
+ 72f0: 4f054787 movi v7.4s, #0xbc, lsl #16
+ 72f4: 4f0547a7 movi v7.4s, #0xbd, lsl #16
+ 72f8: 4f0547c7 movi v7.4s, #0xbe, lsl #16
+ 72fc: 4f0547e7 movi v7.4s, #0xbf, lsl #16
+ 7300: 4f064407 movi v7.4s, #0xc0, lsl #16
+ 7304: 4f064427 movi v7.4s, #0xc1, lsl #16
+ 7308: 4f064447 movi v7.4s, #0xc2, lsl #16
+ 730c: 4f064467 movi v7.4s, #0xc3, lsl #16
+ 7310: 4f064487 movi v7.4s, #0xc4, lsl #16
+ 7314: 4f0644a7 movi v7.4s, #0xc5, lsl #16
+ 7318: 4f0644c7 movi v7.4s, #0xc6, lsl #16
+ 731c: 4f0644e7 movi v7.4s, #0xc7, lsl #16
+ 7320: 4f064507 movi v7.4s, #0xc8, lsl #16
+ 7324: 4f064527 movi v7.4s, #0xc9, lsl #16
+ 7328: 4f064547 movi v7.4s, #0xca, lsl #16
+ 732c: 4f064567 movi v7.4s, #0xcb, lsl #16
+ 7330: 4f064587 movi v7.4s, #0xcc, lsl #16
+ 7334: 4f0645a7 movi v7.4s, #0xcd, lsl #16
+ 7338: 4f0645c7 movi v7.4s, #0xce, lsl #16
+ 733c: 4f0645e7 movi v7.4s, #0xcf, lsl #16
+ 7340: 4f064607 movi v7.4s, #0xd0, lsl #16
+ 7344: 4f064627 movi v7.4s, #0xd1, lsl #16
+ 7348: 4f064647 movi v7.4s, #0xd2, lsl #16
+ 734c: 4f064667 movi v7.4s, #0xd3, lsl #16
+ 7350: 4f064687 movi v7.4s, #0xd4, lsl #16
+ 7354: 4f0646a7 movi v7.4s, #0xd5, lsl #16
+ 7358: 4f0646c7 movi v7.4s, #0xd6, lsl #16
+ 735c: 4f0646e7 movi v7.4s, #0xd7, lsl #16
+ 7360: 4f064707 movi v7.4s, #0xd8, lsl #16
+ 7364: 4f064727 movi v7.4s, #0xd9, lsl #16
+ 7368: 4f064747 movi v7.4s, #0xda, lsl #16
+ 736c: 4f064767 movi v7.4s, #0xdb, lsl #16
+ 7370: 4f064787 movi v7.4s, #0xdc, lsl #16
+ 7374: 4f0647a7 movi v7.4s, #0xdd, lsl #16
+ 7378: 4f0647c7 movi v7.4s, #0xde, lsl #16
+ 737c: 4f0647e7 movi v7.4s, #0xdf, lsl #16
+ 7380: 4f074407 movi v7.4s, #0xe0, lsl #16
+ 7384: 4f074427 movi v7.4s, #0xe1, lsl #16
+ 7388: 4f074447 movi v7.4s, #0xe2, lsl #16
+ 738c: 4f074467 movi v7.4s, #0xe3, lsl #16
+ 7390: 4f074487 movi v7.4s, #0xe4, lsl #16
+ 7394: 4f0744a7 movi v7.4s, #0xe5, lsl #16
+ 7398: 4f0744c7 movi v7.4s, #0xe6, lsl #16
+ 739c: 4f0744e7 movi v7.4s, #0xe7, lsl #16
+ 73a0: 4f074507 movi v7.4s, #0xe8, lsl #16
+ 73a4: 4f074527 movi v7.4s, #0xe9, lsl #16
+ 73a8: 4f074547 movi v7.4s, #0xea, lsl #16
+ 73ac: 4f074567 movi v7.4s, #0xeb, lsl #16
+ 73b0: 4f074587 movi v7.4s, #0xec, lsl #16
+ 73b4: 4f0745a7 movi v7.4s, #0xed, lsl #16
+ 73b8: 4f0745c7 movi v7.4s, #0xee, lsl #16
+ 73bc: 4f0745e7 movi v7.4s, #0xef, lsl #16
+ 73c0: 4f074607 movi v7.4s, #0xf0, lsl #16
+ 73c4: 4f074627 movi v7.4s, #0xf1, lsl #16
+ 73c8: 4f074647 movi v7.4s, #0xf2, lsl #16
+ 73cc: 4f074667 movi v7.4s, #0xf3, lsl #16
+ 73d0: 4f074687 movi v7.4s, #0xf4, lsl #16
+ 73d4: 4f0746a7 movi v7.4s, #0xf5, lsl #16
+ 73d8: 4f0746c7 movi v7.4s, #0xf6, lsl #16
+ 73dc: 4f0746e7 movi v7.4s, #0xf7, lsl #16
+ 73e0: 4f074707 movi v7.4s, #0xf8, lsl #16
+ 73e4: 4f074727 movi v7.4s, #0xf9, lsl #16
+ 73e8: 4f074747 movi v7.4s, #0xfa, lsl #16
+ 73ec: 4f074767 movi v7.4s, #0xfb, lsl #16
+ 73f0: 4f074787 movi v7.4s, #0xfc, lsl #16
+ 73f4: 4f0747a7 movi v7.4s, #0xfd, lsl #16
+ 73f8: 4f0747c7 movi v7.4s, #0xfe, lsl #16
+ 73fc: 4f0747e7 movi v7.4s, #0xff, lsl #16
+ 7400: 4f00040f movi v15.4s, #0x0
+ 7404: 4f00042f movi v15.4s, #0x1
+ 7408: 4f00044f movi v15.4s, #0x2
+ 740c: 4f00046f movi v15.4s, #0x3
+ 7410: 4f00048f movi v15.4s, #0x4
+ 7414: 4f0004af movi v15.4s, #0x5
+ 7418: 4f0004cf movi v15.4s, #0x6
+ 741c: 4f0004ef movi v15.4s, #0x7
+ 7420: 4f00050f movi v15.4s, #0x8
+ 7424: 4f00052f movi v15.4s, #0x9
+ 7428: 4f00054f movi v15.4s, #0xa
+ 742c: 4f00056f movi v15.4s, #0xb
+ 7430: 4f00058f movi v15.4s, #0xc
+ 7434: 4f0005af movi v15.4s, #0xd
+ 7438: 4f0005cf movi v15.4s, #0xe
+ 743c: 4f0005ef movi v15.4s, #0xf
+ 7440: 4f00060f movi v15.4s, #0x10
+ 7444: 4f00062f movi v15.4s, #0x11
+ 7448: 4f00064f movi v15.4s, #0x12
+ 744c: 4f00066f movi v15.4s, #0x13
+ 7450: 4f00068f movi v15.4s, #0x14
+ 7454: 4f0006af movi v15.4s, #0x15
+ 7458: 4f0006cf movi v15.4s, #0x16
+ 745c: 4f0006ef movi v15.4s, #0x17
+ 7460: 4f00070f movi v15.4s, #0x18
+ 7464: 4f00072f movi v15.4s, #0x19
+ 7468: 4f00074f movi v15.4s, #0x1a
+ 746c: 4f00076f movi v15.4s, #0x1b
+ 7470: 4f00078f movi v15.4s, #0x1c
+ 7474: 4f0007af movi v15.4s, #0x1d
+ 7478: 4f0007cf movi v15.4s, #0x1e
+ 747c: 4f0007ef movi v15.4s, #0x1f
+ 7480: 4f01040f movi v15.4s, #0x20
+ 7484: 4f01042f movi v15.4s, #0x21
+ 7488: 4f01044f movi v15.4s, #0x22
+ 748c: 4f01046f movi v15.4s, #0x23
+ 7490: 4f01048f movi v15.4s, #0x24
+ 7494: 4f0104af movi v15.4s, #0x25
+ 7498: 4f0104cf movi v15.4s, #0x26
+ 749c: 4f0104ef movi v15.4s, #0x27
+ 74a0: 4f01050f movi v15.4s, #0x28
+ 74a4: 4f01052f movi v15.4s, #0x29
+ 74a8: 4f01054f movi v15.4s, #0x2a
+ 74ac: 4f01056f movi v15.4s, #0x2b
+ 74b0: 4f01058f movi v15.4s, #0x2c
+ 74b4: 4f0105af movi v15.4s, #0x2d
+ 74b8: 4f0105cf movi v15.4s, #0x2e
+ 74bc: 4f0105ef movi v15.4s, #0x2f
+ 74c0: 4f01060f movi v15.4s, #0x30
+ 74c4: 4f01062f movi v15.4s, #0x31
+ 74c8: 4f01064f movi v15.4s, #0x32
+ 74cc: 4f01066f movi v15.4s, #0x33
+ 74d0: 4f01068f movi v15.4s, #0x34
+ 74d4: 4f0106af movi v15.4s, #0x35
+ 74d8: 4f0106cf movi v15.4s, #0x36
+ 74dc: 4f0106ef movi v15.4s, #0x37
+ 74e0: 4f01070f movi v15.4s, #0x38
+ 74e4: 4f01072f movi v15.4s, #0x39
+ 74e8: 4f01074f movi v15.4s, #0x3a
+ 74ec: 4f01076f movi v15.4s, #0x3b
+ 74f0: 4f01078f movi v15.4s, #0x3c
+ 74f4: 4f0107af movi v15.4s, #0x3d
+ 74f8: 4f0107cf movi v15.4s, #0x3e
+ 74fc: 4f0107ef movi v15.4s, #0x3f
+ 7500: 4f02040f movi v15.4s, #0x40
+ 7504: 4f02042f movi v15.4s, #0x41
+ 7508: 4f02044f movi v15.4s, #0x42
+ 750c: 4f02046f movi v15.4s, #0x43
+ 7510: 4f02048f movi v15.4s, #0x44
+ 7514: 4f0204af movi v15.4s, #0x45
+ 7518: 4f0204cf movi v15.4s, #0x46
+ 751c: 4f0204ef movi v15.4s, #0x47
+ 7520: 4f02050f movi v15.4s, #0x48
+ 7524: 4f02052f movi v15.4s, #0x49
+ 7528: 4f02054f movi v15.4s, #0x4a
+ 752c: 4f02056f movi v15.4s, #0x4b
+ 7530: 4f02058f movi v15.4s, #0x4c
+ 7534: 4f0205af movi v15.4s, #0x4d
+ 7538: 4f0205cf movi v15.4s, #0x4e
+ 753c: 4f0205ef movi v15.4s, #0x4f
+ 7540: 4f02060f movi v15.4s, #0x50
+ 7544: 4f02062f movi v15.4s, #0x51
+ 7548: 4f02064f movi v15.4s, #0x52
+ 754c: 4f02066f movi v15.4s, #0x53
+ 7550: 4f02068f movi v15.4s, #0x54
+ 7554: 4f0206af movi v15.4s, #0x55
+ 7558: 4f0206cf movi v15.4s, #0x56
+ 755c: 4f0206ef movi v15.4s, #0x57
+ 7560: 4f02070f movi v15.4s, #0x58
+ 7564: 4f02072f movi v15.4s, #0x59
+ 7568: 4f02074f movi v15.4s, #0x5a
+ 756c: 4f02076f movi v15.4s, #0x5b
+ 7570: 4f02078f movi v15.4s, #0x5c
+ 7574: 4f0207af movi v15.4s, #0x5d
+ 7578: 4f0207cf movi v15.4s, #0x5e
+ 757c: 4f0207ef movi v15.4s, #0x5f
+ 7580: 4f03040f movi v15.4s, #0x60
+ 7584: 4f03042f movi v15.4s, #0x61
+ 7588: 4f03044f movi v15.4s, #0x62
+ 758c: 4f03046f movi v15.4s, #0x63
+ 7590: 4f03048f movi v15.4s, #0x64
+ 7594: 4f0304af movi v15.4s, #0x65
+ 7598: 4f0304cf movi v15.4s, #0x66
+ 759c: 4f0304ef movi v15.4s, #0x67
+ 75a0: 4f03050f movi v15.4s, #0x68
+ 75a4: 4f03052f movi v15.4s, #0x69
+ 75a8: 4f03054f movi v15.4s, #0x6a
+ 75ac: 4f03056f movi v15.4s, #0x6b
+ 75b0: 4f03058f movi v15.4s, #0x6c
+ 75b4: 4f0305af movi v15.4s, #0x6d
+ 75b8: 4f0305cf movi v15.4s, #0x6e
+ 75bc: 4f0305ef movi v15.4s, #0x6f
+ 75c0: 4f03060f movi v15.4s, #0x70
+ 75c4: 4f03062f movi v15.4s, #0x71
+ 75c8: 4f03064f movi v15.4s, #0x72
+ 75cc: 4f03066f movi v15.4s, #0x73
+ 75d0: 4f03068f movi v15.4s, #0x74
+ 75d4: 4f0306af movi v15.4s, #0x75
+ 75d8: 4f0306cf movi v15.4s, #0x76
+ 75dc: 4f0306ef movi v15.4s, #0x77
+ 75e0: 4f03070f movi v15.4s, #0x78
+ 75e4: 4f03072f movi v15.4s, #0x79
+ 75e8: 4f03074f movi v15.4s, #0x7a
+ 75ec: 4f03076f movi v15.4s, #0x7b
+ 75f0: 4f03078f movi v15.4s, #0x7c
+ 75f4: 4f0307af movi v15.4s, #0x7d
+ 75f8: 4f0307cf movi v15.4s, #0x7e
+ 75fc: 4f0307ef movi v15.4s, #0x7f
+ 7600: 4f04040f movi v15.4s, #0x80
+ 7604: 4f04042f movi v15.4s, #0x81
+ 7608: 4f04044f movi v15.4s, #0x82
+ 760c: 4f04046f movi v15.4s, #0x83
+ 7610: 4f04048f movi v15.4s, #0x84
+ 7614: 4f0404af movi v15.4s, #0x85
+ 7618: 4f0404cf movi v15.4s, #0x86
+ 761c: 4f0404ef movi v15.4s, #0x87
+ 7620: 4f04050f movi v15.4s, #0x88
+ 7624: 4f04052f movi v15.4s, #0x89
+ 7628: 4f04054f movi v15.4s, #0x8a
+ 762c: 4f04056f movi v15.4s, #0x8b
+ 7630: 4f04058f movi v15.4s, #0x8c
+ 7634: 4f0405af movi v15.4s, #0x8d
+ 7638: 4f0405cf movi v15.4s, #0x8e
+ 763c: 4f0405ef movi v15.4s, #0x8f
+ 7640: 4f04060f movi v15.4s, #0x90
+ 7644: 4f04062f movi v15.4s, #0x91
+ 7648: 4f04064f movi v15.4s, #0x92
+ 764c: 4f04066f movi v15.4s, #0x93
+ 7650: 4f04068f movi v15.4s, #0x94
+ 7654: 4f0406af movi v15.4s, #0x95
+ 7658: 4f0406cf movi v15.4s, #0x96
+ 765c: 4f0406ef movi v15.4s, #0x97
+ 7660: 4f04070f movi v15.4s, #0x98
+ 7664: 4f04072f movi v15.4s, #0x99
+ 7668: 4f04074f movi v15.4s, #0x9a
+ 766c: 4f04076f movi v15.4s, #0x9b
+ 7670: 4f04078f movi v15.4s, #0x9c
+ 7674: 4f0407af movi v15.4s, #0x9d
+ 7678: 4f0407cf movi v15.4s, #0x9e
+ 767c: 4f0407ef movi v15.4s, #0x9f
+ 7680: 4f05040f movi v15.4s, #0xa0
+ 7684: 4f05042f movi v15.4s, #0xa1
+ 7688: 4f05044f movi v15.4s, #0xa2
+ 768c: 4f05046f movi v15.4s, #0xa3
+ 7690: 4f05048f movi v15.4s, #0xa4
+ 7694: 4f0504af movi v15.4s, #0xa5
+ 7698: 4f0504cf movi v15.4s, #0xa6
+ 769c: 4f0504ef movi v15.4s, #0xa7
+ 76a0: 4f05050f movi v15.4s, #0xa8
+ 76a4: 4f05052f movi v15.4s, #0xa9
+ 76a8: 4f05054f movi v15.4s, #0xaa
+ 76ac: 4f05056f movi v15.4s, #0xab
+ 76b0: 4f05058f movi v15.4s, #0xac
+ 76b4: 4f0505af movi v15.4s, #0xad
+ 76b8: 4f0505cf movi v15.4s, #0xae
+ 76bc: 4f0505ef movi v15.4s, #0xaf
+ 76c0: 4f05060f movi v15.4s, #0xb0
+ 76c4: 4f05062f movi v15.4s, #0xb1
+ 76c8: 4f05064f movi v15.4s, #0xb2
+ 76cc: 4f05066f movi v15.4s, #0xb3
+ 76d0: 4f05068f movi v15.4s, #0xb4
+ 76d4: 4f0506af movi v15.4s, #0xb5
+ 76d8: 4f0506cf movi v15.4s, #0xb6
+ 76dc: 4f0506ef movi v15.4s, #0xb7
+ 76e0: 4f05070f movi v15.4s, #0xb8
+ 76e4: 4f05072f movi v15.4s, #0xb9
+ 76e8: 4f05074f movi v15.4s, #0xba
+ 76ec: 4f05076f movi v15.4s, #0xbb
+ 76f0: 4f05078f movi v15.4s, #0xbc
+ 76f4: 4f0507af movi v15.4s, #0xbd
+ 76f8: 4f0507cf movi v15.4s, #0xbe
+ 76fc: 4f0507ef movi v15.4s, #0xbf
+ 7700: 4f06040f movi v15.4s, #0xc0
+ 7704: 4f06042f movi v15.4s, #0xc1
+ 7708: 4f06044f movi v15.4s, #0xc2
+ 770c: 4f06046f movi v15.4s, #0xc3
+ 7710: 4f06048f movi v15.4s, #0xc4
+ 7714: 4f0604af movi v15.4s, #0xc5
+ 7718: 4f0604cf movi v15.4s, #0xc6
+ 771c: 4f0604ef movi v15.4s, #0xc7
+ 7720: 4f06050f movi v15.4s, #0xc8
+ 7724: 4f06052f movi v15.4s, #0xc9
+ 7728: 4f06054f movi v15.4s, #0xca
+ 772c: 4f06056f movi v15.4s, #0xcb
+ 7730: 4f06058f movi v15.4s, #0xcc
+ 7734: 4f0605af movi v15.4s, #0xcd
+ 7738: 4f0605cf movi v15.4s, #0xce
+ 773c: 4f0605ef movi v15.4s, #0xcf
+ 7740: 4f06060f movi v15.4s, #0xd0
+ 7744: 4f06062f movi v15.4s, #0xd1
+ 7748: 4f06064f movi v15.4s, #0xd2
+ 774c: 4f06066f movi v15.4s, #0xd3
+ 7750: 4f06068f movi v15.4s, #0xd4
+ 7754: 4f0606af movi v15.4s, #0xd5
+ 7758: 4f0606cf movi v15.4s, #0xd6
+ 775c: 4f0606ef movi v15.4s, #0xd7
+ 7760: 4f06070f movi v15.4s, #0xd8
+ 7764: 4f06072f movi v15.4s, #0xd9
+ 7768: 4f06074f movi v15.4s, #0xda
+ 776c: 4f06076f movi v15.4s, #0xdb
+ 7770: 4f06078f movi v15.4s, #0xdc
+ 7774: 4f0607af movi v15.4s, #0xdd
+ 7778: 4f0607cf movi v15.4s, #0xde
+ 777c: 4f0607ef movi v15.4s, #0xdf
+ 7780: 4f07040f movi v15.4s, #0xe0
+ 7784: 4f07042f movi v15.4s, #0xe1
+ 7788: 4f07044f movi v15.4s, #0xe2
+ 778c: 4f07046f movi v15.4s, #0xe3
+ 7790: 4f07048f movi v15.4s, #0xe4
+ 7794: 4f0704af movi v15.4s, #0xe5
+ 7798: 4f0704cf movi v15.4s, #0xe6
+ 779c: 4f0704ef movi v15.4s, #0xe7
+ 77a0: 4f07050f movi v15.4s, #0xe8
+ 77a4: 4f07052f movi v15.4s, #0xe9
+ 77a8: 4f07054f movi v15.4s, #0xea
+ 77ac: 4f07056f movi v15.4s, #0xeb
+ 77b0: 4f07058f movi v15.4s, #0xec
+ 77b4: 4f0705af movi v15.4s, #0xed
+ 77b8: 4f0705cf movi v15.4s, #0xee
+ 77bc: 4f0705ef movi v15.4s, #0xef
+ 77c0: 4f07060f movi v15.4s, #0xf0
+ 77c4: 4f07062f movi v15.4s, #0xf1
+ 77c8: 4f07064f movi v15.4s, #0xf2
+ 77cc: 4f07066f movi v15.4s, #0xf3
+ 77d0: 4f07068f movi v15.4s, #0xf4
+ 77d4: 4f0706af movi v15.4s, #0xf5
+ 77d8: 4f0706cf movi v15.4s, #0xf6
+ 77dc: 4f0706ef movi v15.4s, #0xf7
+ 77e0: 4f07070f movi v15.4s, #0xf8
+ 77e4: 4f07072f movi v15.4s, #0xf9
+ 77e8: 4f07074f movi v15.4s, #0xfa
+ 77ec: 4f07076f movi v15.4s, #0xfb
+ 77f0: 4f07078f movi v15.4s, #0xfc
+ 77f4: 4f0707af movi v15.4s, #0xfd
+ 77f8: 4f0707cf movi v15.4s, #0xfe
+ 77fc: 4f0707ef movi v15.4s, #0xff
+ 7800: 4f006407 movi v7.4s, #0x0, lsl #24
+ 7804: 4f006427 movi v7.4s, #0x1, lsl #24
+ 7808: 4f006447 movi v7.4s, #0x2, lsl #24
+ 780c: 4f006467 movi v7.4s, #0x3, lsl #24
+ 7810: 4f006487 movi v7.4s, #0x4, lsl #24
+ 7814: 4f0064a7 movi v7.4s, #0x5, lsl #24
+ 7818: 4f0064c7 movi v7.4s, #0x6, lsl #24
+ 781c: 4f0064e7 movi v7.4s, #0x7, lsl #24
+ 7820: 4f006507 movi v7.4s, #0x8, lsl #24
+ 7824: 4f006527 movi v7.4s, #0x9, lsl #24
+ 7828: 4f006547 movi v7.4s, #0xa, lsl #24
+ 782c: 4f006567 movi v7.4s, #0xb, lsl #24
+ 7830: 4f006587 movi v7.4s, #0xc, lsl #24
+ 7834: 4f0065a7 movi v7.4s, #0xd, lsl #24
+ 7838: 4f0065c7 movi v7.4s, #0xe, lsl #24
+ 783c: 4f0065e7 movi v7.4s, #0xf, lsl #24
+ 7840: 4f006607 movi v7.4s, #0x10, lsl #24
+ 7844: 4f006627 movi v7.4s, #0x11, lsl #24
+ 7848: 4f006647 movi v7.4s, #0x12, lsl #24
+ 784c: 4f006667 movi v7.4s, #0x13, lsl #24
+ 7850: 4f006687 movi v7.4s, #0x14, lsl #24
+ 7854: 4f0066a7 movi v7.4s, #0x15, lsl #24
+ 7858: 4f0066c7 movi v7.4s, #0x16, lsl #24
+ 785c: 4f0066e7 movi v7.4s, #0x17, lsl #24
+ 7860: 4f006707 movi v7.4s, #0x18, lsl #24
+ 7864: 4f006727 movi v7.4s, #0x19, lsl #24
+ 7868: 4f006747 movi v7.4s, #0x1a, lsl #24
+ 786c: 4f006767 movi v7.4s, #0x1b, lsl #24
+ 7870: 4f006787 movi v7.4s, #0x1c, lsl #24
+ 7874: 4f0067a7 movi v7.4s, #0x1d, lsl #24
+ 7878: 4f0067c7 movi v7.4s, #0x1e, lsl #24
+ 787c: 4f0067e7 movi v7.4s, #0x1f, lsl #24
+ 7880: 4f016407 movi v7.4s, #0x20, lsl #24
+ 7884: 4f016427 movi v7.4s, #0x21, lsl #24
+ 7888: 4f016447 movi v7.4s, #0x22, lsl #24
+ 788c: 4f016467 movi v7.4s, #0x23, lsl #24
+ 7890: 4f016487 movi v7.4s, #0x24, lsl #24
+ 7894: 4f0164a7 movi v7.4s, #0x25, lsl #24
+ 7898: 4f0164c7 movi v7.4s, #0x26, lsl #24
+ 789c: 4f0164e7 movi v7.4s, #0x27, lsl #24
+ 78a0: 4f016507 movi v7.4s, #0x28, lsl #24
+ 78a4: 4f016527 movi v7.4s, #0x29, lsl #24
+ 78a8: 4f016547 movi v7.4s, #0x2a, lsl #24
+ 78ac: 4f016567 movi v7.4s, #0x2b, lsl #24
+ 78b0: 4f016587 movi v7.4s, #0x2c, lsl #24
+ 78b4: 4f0165a7 movi v7.4s, #0x2d, lsl #24
+ 78b8: 4f0165c7 movi v7.4s, #0x2e, lsl #24
+ 78bc: 4f0165e7 movi v7.4s, #0x2f, lsl #24
+ 78c0: 4f016607 movi v7.4s, #0x30, lsl #24
+ 78c4: 4f016627 movi v7.4s, #0x31, lsl #24
+ 78c8: 4f016647 movi v7.4s, #0x32, lsl #24
+ 78cc: 4f016667 movi v7.4s, #0x33, lsl #24
+ 78d0: 4f016687 movi v7.4s, #0x34, lsl #24
+ 78d4: 4f0166a7 movi v7.4s, #0x35, lsl #24
+ 78d8: 4f0166c7 movi v7.4s, #0x36, lsl #24
+ 78dc: 4f0166e7 movi v7.4s, #0x37, lsl #24
+ 78e0: 4f016707 movi v7.4s, #0x38, lsl #24
+ 78e4: 4f016727 movi v7.4s, #0x39, lsl #24
+ 78e8: 4f016747 movi v7.4s, #0x3a, lsl #24
+ 78ec: 4f016767 movi v7.4s, #0x3b, lsl #24
+ 78f0: 4f016787 movi v7.4s, #0x3c, lsl #24
+ 78f4: 4f0167a7 movi v7.4s, #0x3d, lsl #24
+ 78f8: 4f0167c7 movi v7.4s, #0x3e, lsl #24
+ 78fc: 4f0167e7 movi v7.4s, #0x3f, lsl #24
+ 7900: 4f026407 movi v7.4s, #0x40, lsl #24
+ 7904: 4f026427 movi v7.4s, #0x41, lsl #24
+ 7908: 4f026447 movi v7.4s, #0x42, lsl #24
+ 790c: 4f026467 movi v7.4s, #0x43, lsl #24
+ 7910: 4f026487 movi v7.4s, #0x44, lsl #24
+ 7914: 4f0264a7 movi v7.4s, #0x45, lsl #24
+ 7918: 4f0264c7 movi v7.4s, #0x46, lsl #24
+ 791c: 4f0264e7 movi v7.4s, #0x47, lsl #24
+ 7920: 4f026507 movi v7.4s, #0x48, lsl #24
+ 7924: 4f026527 movi v7.4s, #0x49, lsl #24
+ 7928: 4f026547 movi v7.4s, #0x4a, lsl #24
+ 792c: 4f026567 movi v7.4s, #0x4b, lsl #24
+ 7930: 4f026587 movi v7.4s, #0x4c, lsl #24
+ 7934: 4f0265a7 movi v7.4s, #0x4d, lsl #24
+ 7938: 4f0265c7 movi v7.4s, #0x4e, lsl #24
+ 793c: 4f0265e7 movi v7.4s, #0x4f, lsl #24
+ 7940: 4f026607 movi v7.4s, #0x50, lsl #24
+ 7944: 4f026627 movi v7.4s, #0x51, lsl #24
+ 7948: 4f026647 movi v7.4s, #0x52, lsl #24
+ 794c: 4f026667 movi v7.4s, #0x53, lsl #24
+ 7950: 4f026687 movi v7.4s, #0x54, lsl #24
+ 7954: 4f0266a7 movi v7.4s, #0x55, lsl #24
+ 7958: 4f0266c7 movi v7.4s, #0x56, lsl #24
+ 795c: 4f0266e7 movi v7.4s, #0x57, lsl #24
+ 7960: 4f026707 movi v7.4s, #0x58, lsl #24
+ 7964: 4f026727 movi v7.4s, #0x59, lsl #24
+ 7968: 4f026747 movi v7.4s, #0x5a, lsl #24
+ 796c: 4f026767 movi v7.4s, #0x5b, lsl #24
+ 7970: 4f026787 movi v7.4s, #0x5c, lsl #24
+ 7974: 4f0267a7 movi v7.4s, #0x5d, lsl #24
+ 7978: 4f0267c7 movi v7.4s, #0x5e, lsl #24
+ 797c: 4f0267e7 movi v7.4s, #0x5f, lsl #24
+ 7980: 4f036407 movi v7.4s, #0x60, lsl #24
+ 7984: 4f036427 movi v7.4s, #0x61, lsl #24
+ 7988: 4f036447 movi v7.4s, #0x62, lsl #24
+ 798c: 4f036467 movi v7.4s, #0x63, lsl #24
+ 7990: 4f036487 movi v7.4s, #0x64, lsl #24
+ 7994: 4f0364a7 movi v7.4s, #0x65, lsl #24
+ 7998: 4f0364c7 movi v7.4s, #0x66, lsl #24
+ 799c: 4f0364e7 movi v7.4s, #0x67, lsl #24
+ 79a0: 4f036507 movi v7.4s, #0x68, lsl #24
+ 79a4: 4f036527 movi v7.4s, #0x69, lsl #24
+ 79a8: 4f036547 movi v7.4s, #0x6a, lsl #24
+ 79ac: 4f036567 movi v7.4s, #0x6b, lsl #24
+ 79b0: 4f036587 movi v7.4s, #0x6c, lsl #24
+ 79b4: 4f0365a7 movi v7.4s, #0x6d, lsl #24
+ 79b8: 4f0365c7 movi v7.4s, #0x6e, lsl #24
+ 79bc: 4f0365e7 movi v7.4s, #0x6f, lsl #24
+ 79c0: 4f036607 movi v7.4s, #0x70, lsl #24
+ 79c4: 4f036627 movi v7.4s, #0x71, lsl #24
+ 79c8: 4f036647 movi v7.4s, #0x72, lsl #24
+ 79cc: 4f036667 movi v7.4s, #0x73, lsl #24
+ 79d0: 4f036687 movi v7.4s, #0x74, lsl #24
+ 79d4: 4f0366a7 movi v7.4s, #0x75, lsl #24
+ 79d8: 4f0366c7 movi v7.4s, #0x76, lsl #24
+ 79dc: 4f0366e7 movi v7.4s, #0x77, lsl #24
+ 79e0: 4f036707 movi v7.4s, #0x78, lsl #24
+ 79e4: 4f036727 movi v7.4s, #0x79, lsl #24
+ 79e8: 4f036747 movi v7.4s, #0x7a, lsl #24
+ 79ec: 4f036767 movi v7.4s, #0x7b, lsl #24
+ 79f0: 4f036787 movi v7.4s, #0x7c, lsl #24
+ 79f4: 4f0367a7 movi v7.4s, #0x7d, lsl #24
+ 79f8: 4f0367c7 movi v7.4s, #0x7e, lsl #24
+ 79fc: 4f0367e7 movi v7.4s, #0x7f, lsl #24
+ 7a00: 4f046407 movi v7.4s, #0x80, lsl #24
+ 7a04: 4f046427 movi v7.4s, #0x81, lsl #24
+ 7a08: 4f046447 movi v7.4s, #0x82, lsl #24
+ 7a0c: 4f046467 movi v7.4s, #0x83, lsl #24
+ 7a10: 4f046487 movi v7.4s, #0x84, lsl #24
+ 7a14: 4f0464a7 movi v7.4s, #0x85, lsl #24
+ 7a18: 4f0464c7 movi v7.4s, #0x86, lsl #24
+ 7a1c: 4f0464e7 movi v7.4s, #0x87, lsl #24
+ 7a20: 4f046507 movi v7.4s, #0x88, lsl #24
+ 7a24: 4f046527 movi v7.4s, #0x89, lsl #24
+ 7a28: 4f046547 movi v7.4s, #0x8a, lsl #24
+ 7a2c: 4f046567 movi v7.4s, #0x8b, lsl #24
+ 7a30: 4f046587 movi v7.4s, #0x8c, lsl #24
+ 7a34: 4f0465a7 movi v7.4s, #0x8d, lsl #24
+ 7a38: 4f0465c7 movi v7.4s, #0x8e, lsl #24
+ 7a3c: 4f0465e7 movi v7.4s, #0x8f, lsl #24
+ 7a40: 4f046607 movi v7.4s, #0x90, lsl #24
+ 7a44: 4f046627 movi v7.4s, #0x91, lsl #24
+ 7a48: 4f046647 movi v7.4s, #0x92, lsl #24
+ 7a4c: 4f046667 movi v7.4s, #0x93, lsl #24
+ 7a50: 4f046687 movi v7.4s, #0x94, lsl #24
+ 7a54: 4f0466a7 movi v7.4s, #0x95, lsl #24
+ 7a58: 4f0466c7 movi v7.4s, #0x96, lsl #24
+ 7a5c: 4f0466e7 movi v7.4s, #0x97, lsl #24
+ 7a60: 4f046707 movi v7.4s, #0x98, lsl #24
+ 7a64: 4f046727 movi v7.4s, #0x99, lsl #24
+ 7a68: 4f046747 movi v7.4s, #0x9a, lsl #24
+ 7a6c: 4f046767 movi v7.4s, #0x9b, lsl #24
+ 7a70: 4f046787 movi v7.4s, #0x9c, lsl #24
+ 7a74: 4f0467a7 movi v7.4s, #0x9d, lsl #24
+ 7a78: 4f0467c7 movi v7.4s, #0x9e, lsl #24
+ 7a7c: 4f0467e7 movi v7.4s, #0x9f, lsl #24
+ 7a80: 4f056407 movi v7.4s, #0xa0, lsl #24
+ 7a84: 4f056427 movi v7.4s, #0xa1, lsl #24
+ 7a88: 4f056447 movi v7.4s, #0xa2, lsl #24
+ 7a8c: 4f056467 movi v7.4s, #0xa3, lsl #24
+ 7a90: 4f056487 movi v7.4s, #0xa4, lsl #24
+ 7a94: 4f0564a7 movi v7.4s, #0xa5, lsl #24
+ 7a98: 4f0564c7 movi v7.4s, #0xa6, lsl #24
+ 7a9c: 4f0564e7 movi v7.4s, #0xa7, lsl #24
+ 7aa0: 4f056507 movi v7.4s, #0xa8, lsl #24
+ 7aa4: 4f056527 movi v7.4s, #0xa9, lsl #24
+ 7aa8: 4f056547 movi v7.4s, #0xaa, lsl #24
+ 7aac: 4f056567 movi v7.4s, #0xab, lsl #24
+ 7ab0: 4f056587 movi v7.4s, #0xac, lsl #24
+ 7ab4: 4f0565a7 movi v7.4s, #0xad, lsl #24
+ 7ab8: 4f0565c7 movi v7.4s, #0xae, lsl #24
+ 7abc: 4f0565e7 movi v7.4s, #0xaf, lsl #24
+ 7ac0: 4f056607 movi v7.4s, #0xb0, lsl #24
+ 7ac4: 4f056627 movi v7.4s, #0xb1, lsl #24
+ 7ac8: 4f056647 movi v7.4s, #0xb2, lsl #24
+ 7acc: 4f056667 movi v7.4s, #0xb3, lsl #24
+ 7ad0: 4f056687 movi v7.4s, #0xb4, lsl #24
+ 7ad4: 4f0566a7 movi v7.4s, #0xb5, lsl #24
+ 7ad8: 4f0566c7 movi v7.4s, #0xb6, lsl #24
+ 7adc: 4f0566e7 movi v7.4s, #0xb7, lsl #24
+ 7ae0: 4f056707 movi v7.4s, #0xb8, lsl #24
+ 7ae4: 4f056727 movi v7.4s, #0xb9, lsl #24
+ 7ae8: 4f056747 movi v7.4s, #0xba, lsl #24
+ 7aec: 4f056767 movi v7.4s, #0xbb, lsl #24
+ 7af0: 4f056787 movi v7.4s, #0xbc, lsl #24
+ 7af4: 4f0567a7 movi v7.4s, #0xbd, lsl #24
+ 7af8: 4f0567c7 movi v7.4s, #0xbe, lsl #24
+ 7afc: 4f0567e7 movi v7.4s, #0xbf, lsl #24
+ 7b00: 4f066407 movi v7.4s, #0xc0, lsl #24
+ 7b04: 4f066427 movi v7.4s, #0xc1, lsl #24
+ 7b08: 4f066447 movi v7.4s, #0xc2, lsl #24
+ 7b0c: 4f066467 movi v7.4s, #0xc3, lsl #24
+ 7b10: 4f066487 movi v7.4s, #0xc4, lsl #24
+ 7b14: 4f0664a7 movi v7.4s, #0xc5, lsl #24
+ 7b18: 4f0664c7 movi v7.4s, #0xc6, lsl #24
+ 7b1c: 4f0664e7 movi v7.4s, #0xc7, lsl #24
+ 7b20: 4f066507 movi v7.4s, #0xc8, lsl #24
+ 7b24: 4f066527 movi v7.4s, #0xc9, lsl #24
+ 7b28: 4f066547 movi v7.4s, #0xca, lsl #24
+ 7b2c: 4f066567 movi v7.4s, #0xcb, lsl #24
+ 7b30: 4f066587 movi v7.4s, #0xcc, lsl #24
+ 7b34: 4f0665a7 movi v7.4s, #0xcd, lsl #24
+ 7b38: 4f0665c7 movi v7.4s, #0xce, lsl #24
+ 7b3c: 4f0665e7 movi v7.4s, #0xcf, lsl #24
+ 7b40: 4f066607 movi v7.4s, #0xd0, lsl #24
+ 7b44: 4f066627 movi v7.4s, #0xd1, lsl #24
+ 7b48: 4f066647 movi v7.4s, #0xd2, lsl #24
+ 7b4c: 4f066667 movi v7.4s, #0xd3, lsl #24
+ 7b50: 4f066687 movi v7.4s, #0xd4, lsl #24
+ 7b54: 4f0666a7 movi v7.4s, #0xd5, lsl #24
+ 7b58: 4f0666c7 movi v7.4s, #0xd6, lsl #24
+ 7b5c: 4f0666e7 movi v7.4s, #0xd7, lsl #24
+ 7b60: 4f066707 movi v7.4s, #0xd8, lsl #24
+ 7b64: 4f066727 movi v7.4s, #0xd9, lsl #24
+ 7b68: 4f066747 movi v7.4s, #0xda, lsl #24
+ 7b6c: 4f066767 movi v7.4s, #0xdb, lsl #24
+ 7b70: 4f066787 movi v7.4s, #0xdc, lsl #24
+ 7b74: 4f0667a7 movi v7.4s, #0xdd, lsl #24
+ 7b78: 4f0667c7 movi v7.4s, #0xde, lsl #24
+ 7b7c: 4f0667e7 movi v7.4s, #0xdf, lsl #24
+ 7b80: 4f076407 movi v7.4s, #0xe0, lsl #24
+ 7b84: 4f076427 movi v7.4s, #0xe1, lsl #24
+ 7b88: 4f076447 movi v7.4s, #0xe2, lsl #24
+ 7b8c: 4f076467 movi v7.4s, #0xe3, lsl #24
+ 7b90: 4f076487 movi v7.4s, #0xe4, lsl #24
+ 7b94: 4f0764a7 movi v7.4s, #0xe5, lsl #24
+ 7b98: 4f0764c7 movi v7.4s, #0xe6, lsl #24
+ 7b9c: 4f0764e7 movi v7.4s, #0xe7, lsl #24
+ 7ba0: 4f076507 movi v7.4s, #0xe8, lsl #24
+ 7ba4: 4f076527 movi v7.4s, #0xe9, lsl #24
+ 7ba8: 4f076547 movi v7.4s, #0xea, lsl #24
+ 7bac: 4f076567 movi v7.4s, #0xeb, lsl #24
+ 7bb0: 4f076587 movi v7.4s, #0xec, lsl #24
+ 7bb4: 4f0765a7 movi v7.4s, #0xed, lsl #24
+ 7bb8: 4f0765c7 movi v7.4s, #0xee, lsl #24
+ 7bbc: 4f0765e7 movi v7.4s, #0xef, lsl #24
+ 7bc0: 4f076607 movi v7.4s, #0xf0, lsl #24
+ 7bc4: 4f076627 movi v7.4s, #0xf1, lsl #24
+ 7bc8: 4f076647 movi v7.4s, #0xf2, lsl #24
+ 7bcc: 4f076667 movi v7.4s, #0xf3, lsl #24
+ 7bd0: 4f076687 movi v7.4s, #0xf4, lsl #24
+ 7bd4: 4f0766a7 movi v7.4s, #0xf5, lsl #24
+ 7bd8: 4f0766c7 movi v7.4s, #0xf6, lsl #24
+ 7bdc: 4f0766e7 movi v7.4s, #0xf7, lsl #24
+ 7be0: 4f076707 movi v7.4s, #0xf8, lsl #24
+ 7be4: 4f076727 movi v7.4s, #0xf9, lsl #24
+ 7be8: 4f076747 movi v7.4s, #0xfa, lsl #24
+ 7bec: 4f076767 movi v7.4s, #0xfb, lsl #24
+ 7bf0: 4f076787 movi v7.4s, #0xfc, lsl #24
+ 7bf4: 4f0767a7 movi v7.4s, #0xfd, lsl #24
+ 7bf8: 4f0767c7 movi v7.4s, #0xfe, lsl #24
+ 7bfc: 4f0767e7 movi v7.4s, #0xff, lsl #24
+ 7c00: 4f00040f movi v15.4s, #0x0
+ 7c04: 4f00042f movi v15.4s, #0x1
+ 7c08: 4f00044f movi v15.4s, #0x2
+ 7c0c: 4f00046f movi v15.4s, #0x3
+ 7c10: 4f00048f movi v15.4s, #0x4
+ 7c14: 4f0004af movi v15.4s, #0x5
+ 7c18: 4f0004cf movi v15.4s, #0x6
+ 7c1c: 4f0004ef movi v15.4s, #0x7
+ 7c20: 4f00050f movi v15.4s, #0x8
+ 7c24: 4f00052f movi v15.4s, #0x9
+ 7c28: 4f00054f movi v15.4s, #0xa
+ 7c2c: 4f00056f movi v15.4s, #0xb
+ 7c30: 4f00058f movi v15.4s, #0xc
+ 7c34: 4f0005af movi v15.4s, #0xd
+ 7c38: 4f0005cf movi v15.4s, #0xe
+ 7c3c: 4f0005ef movi v15.4s, #0xf
+ 7c40: 4f00060f movi v15.4s, #0x10
+ 7c44: 4f00062f movi v15.4s, #0x11
+ 7c48: 4f00064f movi v15.4s, #0x12
+ 7c4c: 4f00066f movi v15.4s, #0x13
+ 7c50: 4f00068f movi v15.4s, #0x14
+ 7c54: 4f0006af movi v15.4s, #0x15
+ 7c58: 4f0006cf movi v15.4s, #0x16
+ 7c5c: 4f0006ef movi v15.4s, #0x17
+ 7c60: 4f00070f movi v15.4s, #0x18
+ 7c64: 4f00072f movi v15.4s, #0x19
+ 7c68: 4f00074f movi v15.4s, #0x1a
+ 7c6c: 4f00076f movi v15.4s, #0x1b
+ 7c70: 4f00078f movi v15.4s, #0x1c
+ 7c74: 4f0007af movi v15.4s, #0x1d
+ 7c78: 4f0007cf movi v15.4s, #0x1e
+ 7c7c: 4f0007ef movi v15.4s, #0x1f
+ 7c80: 4f01040f movi v15.4s, #0x20
+ 7c84: 4f01042f movi v15.4s, #0x21
+ 7c88: 4f01044f movi v15.4s, #0x22
+ 7c8c: 4f01046f movi v15.4s, #0x23
+ 7c90: 4f01048f movi v15.4s, #0x24
+ 7c94: 4f0104af movi v15.4s, #0x25
+ 7c98: 4f0104cf movi v15.4s, #0x26
+ 7c9c: 4f0104ef movi v15.4s, #0x27
+ 7ca0: 4f01050f movi v15.4s, #0x28
+ 7ca4: 4f01052f movi v15.4s, #0x29
+ 7ca8: 4f01054f movi v15.4s, #0x2a
+ 7cac: 4f01056f movi v15.4s, #0x2b
+ 7cb0: 4f01058f movi v15.4s, #0x2c
+ 7cb4: 4f0105af movi v15.4s, #0x2d
+ 7cb8: 4f0105cf movi v15.4s, #0x2e
+ 7cbc: 4f0105ef movi v15.4s, #0x2f
+ 7cc0: 4f01060f movi v15.4s, #0x30
+ 7cc4: 4f01062f movi v15.4s, #0x31
+ 7cc8: 4f01064f movi v15.4s, #0x32
+ 7ccc: 4f01066f movi v15.4s, #0x33
+ 7cd0: 4f01068f movi v15.4s, #0x34
+ 7cd4: 4f0106af movi v15.4s, #0x35
+ 7cd8: 4f0106cf movi v15.4s, #0x36
+ 7cdc: 4f0106ef movi v15.4s, #0x37
+ 7ce0: 4f01070f movi v15.4s, #0x38
+ 7ce4: 4f01072f movi v15.4s, #0x39
+ 7ce8: 4f01074f movi v15.4s, #0x3a
+ 7cec: 4f01076f movi v15.4s, #0x3b
+ 7cf0: 4f01078f movi v15.4s, #0x3c
+ 7cf4: 4f0107af movi v15.4s, #0x3d
+ 7cf8: 4f0107cf movi v15.4s, #0x3e
+ 7cfc: 4f0107ef movi v15.4s, #0x3f
+ 7d00: 4f02040f movi v15.4s, #0x40
+ 7d04: 4f02042f movi v15.4s, #0x41
+ 7d08: 4f02044f movi v15.4s, #0x42
+ 7d0c: 4f02046f movi v15.4s, #0x43
+ 7d10: 4f02048f movi v15.4s, #0x44
+ 7d14: 4f0204af movi v15.4s, #0x45
+ 7d18: 4f0204cf movi v15.4s, #0x46
+ 7d1c: 4f0204ef movi v15.4s, #0x47
+ 7d20: 4f02050f movi v15.4s, #0x48
+ 7d24: 4f02052f movi v15.4s, #0x49
+ 7d28: 4f02054f movi v15.4s, #0x4a
+ 7d2c: 4f02056f movi v15.4s, #0x4b
+ 7d30: 4f02058f movi v15.4s, #0x4c
+ 7d34: 4f0205af movi v15.4s, #0x4d
+ 7d38: 4f0205cf movi v15.4s, #0x4e
+ 7d3c: 4f0205ef movi v15.4s, #0x4f
+ 7d40: 4f02060f movi v15.4s, #0x50
+ 7d44: 4f02062f movi v15.4s, #0x51
+ 7d48: 4f02064f movi v15.4s, #0x52
+ 7d4c: 4f02066f movi v15.4s, #0x53
+ 7d50: 4f02068f movi v15.4s, #0x54
+ 7d54: 4f0206af movi v15.4s, #0x55
+ 7d58: 4f0206cf movi v15.4s, #0x56
+ 7d5c: 4f0206ef movi v15.4s, #0x57
+ 7d60: 4f02070f movi v15.4s, #0x58
+ 7d64: 4f02072f movi v15.4s, #0x59
+ 7d68: 4f02074f movi v15.4s, #0x5a
+ 7d6c: 4f02076f movi v15.4s, #0x5b
+ 7d70: 4f02078f movi v15.4s, #0x5c
+ 7d74: 4f0207af movi v15.4s, #0x5d
+ 7d78: 4f0207cf movi v15.4s, #0x5e
+ 7d7c: 4f0207ef movi v15.4s, #0x5f
+ 7d80: 4f03040f movi v15.4s, #0x60
+ 7d84: 4f03042f movi v15.4s, #0x61
+ 7d88: 4f03044f movi v15.4s, #0x62
+ 7d8c: 4f03046f movi v15.4s, #0x63
+ 7d90: 4f03048f movi v15.4s, #0x64
+ 7d94: 4f0304af movi v15.4s, #0x65
+ 7d98: 4f0304cf movi v15.4s, #0x66
+ 7d9c: 4f0304ef movi v15.4s, #0x67
+ 7da0: 4f03050f movi v15.4s, #0x68
+ 7da4: 4f03052f movi v15.4s, #0x69
+ 7da8: 4f03054f movi v15.4s, #0x6a
+ 7dac: 4f03056f movi v15.4s, #0x6b
+ 7db0: 4f03058f movi v15.4s, #0x6c
+ 7db4: 4f0305af movi v15.4s, #0x6d
+ 7db8: 4f0305cf movi v15.4s, #0x6e
+ 7dbc: 4f0305ef movi v15.4s, #0x6f
+ 7dc0: 4f03060f movi v15.4s, #0x70
+ 7dc4: 4f03062f movi v15.4s, #0x71
+ 7dc8: 4f03064f movi v15.4s, #0x72
+ 7dcc: 4f03066f movi v15.4s, #0x73
+ 7dd0: 4f03068f movi v15.4s, #0x74
+ 7dd4: 4f0306af movi v15.4s, #0x75
+ 7dd8: 4f0306cf movi v15.4s, #0x76
+ 7ddc: 4f0306ef movi v15.4s, #0x77
+ 7de0: 4f03070f movi v15.4s, #0x78
+ 7de4: 4f03072f movi v15.4s, #0x79
+ 7de8: 4f03074f movi v15.4s, #0x7a
+ 7dec: 4f03076f movi v15.4s, #0x7b
+ 7df0: 4f03078f movi v15.4s, #0x7c
+ 7df4: 4f0307af movi v15.4s, #0x7d
+ 7df8: 4f0307cf movi v15.4s, #0x7e
+ 7dfc: 4f0307ef movi v15.4s, #0x7f
+ 7e00: 4f04040f movi v15.4s, #0x80
+ 7e04: 4f04042f movi v15.4s, #0x81
+ 7e08: 4f04044f movi v15.4s, #0x82
+ 7e0c: 4f04046f movi v15.4s, #0x83
+ 7e10: 4f04048f movi v15.4s, #0x84
+ 7e14: 4f0404af movi v15.4s, #0x85
+ 7e18: 4f0404cf movi v15.4s, #0x86
+ 7e1c: 4f0404ef movi v15.4s, #0x87
+ 7e20: 4f04050f movi v15.4s, #0x88
+ 7e24: 4f04052f movi v15.4s, #0x89
+ 7e28: 4f04054f movi v15.4s, #0x8a
+ 7e2c: 4f04056f movi v15.4s, #0x8b
+ 7e30: 4f04058f movi v15.4s, #0x8c
+ 7e34: 4f0405af movi v15.4s, #0x8d
+ 7e38: 4f0405cf movi v15.4s, #0x8e
+ 7e3c: 4f0405ef movi v15.4s, #0x8f
+ 7e40: 4f04060f movi v15.4s, #0x90
+ 7e44: 4f04062f movi v15.4s, #0x91
+ 7e48: 4f04064f movi v15.4s, #0x92
+ 7e4c: 4f04066f movi v15.4s, #0x93
+ 7e50: 4f04068f movi v15.4s, #0x94
+ 7e54: 4f0406af movi v15.4s, #0x95
+ 7e58: 4f0406cf movi v15.4s, #0x96
+ 7e5c: 4f0406ef movi v15.4s, #0x97
+ 7e60: 4f04070f movi v15.4s, #0x98
+ 7e64: 4f04072f movi v15.4s, #0x99
+ 7e68: 4f04074f movi v15.4s, #0x9a
+ 7e6c: 4f04076f movi v15.4s, #0x9b
+ 7e70: 4f04078f movi v15.4s, #0x9c
+ 7e74: 4f0407af movi v15.4s, #0x9d
+ 7e78: 4f0407cf movi v15.4s, #0x9e
+ 7e7c: 4f0407ef movi v15.4s, #0x9f
+ 7e80: 4f05040f movi v15.4s, #0xa0
+ 7e84: 4f05042f movi v15.4s, #0xa1
+ 7e88: 4f05044f movi v15.4s, #0xa2
+ 7e8c: 4f05046f movi v15.4s, #0xa3
+ 7e90: 4f05048f movi v15.4s, #0xa4
+ 7e94: 4f0504af movi v15.4s, #0xa5
+ 7e98: 4f0504cf movi v15.4s, #0xa6
+ 7e9c: 4f0504ef movi v15.4s, #0xa7
+ 7ea0: 4f05050f movi v15.4s, #0xa8
+ 7ea4: 4f05052f movi v15.4s, #0xa9
+ 7ea8: 4f05054f movi v15.4s, #0xaa
+ 7eac: 4f05056f movi v15.4s, #0xab
+ 7eb0: 4f05058f movi v15.4s, #0xac
+ 7eb4: 4f0505af movi v15.4s, #0xad
+ 7eb8: 4f0505cf movi v15.4s, #0xae
+ 7ebc: 4f0505ef movi v15.4s, #0xaf
+ 7ec0: 4f05060f movi v15.4s, #0xb0
+ 7ec4: 4f05062f movi v15.4s, #0xb1
+ 7ec8: 4f05064f movi v15.4s, #0xb2
+ 7ecc: 4f05066f movi v15.4s, #0xb3
+ 7ed0: 4f05068f movi v15.4s, #0xb4
+ 7ed4: 4f0506af movi v15.4s, #0xb5
+ 7ed8: 4f0506cf movi v15.4s, #0xb6
+ 7edc: 4f0506ef movi v15.4s, #0xb7
+ 7ee0: 4f05070f movi v15.4s, #0xb8
+ 7ee4: 4f05072f movi v15.4s, #0xb9
+ 7ee8: 4f05074f movi v15.4s, #0xba
+ 7eec: 4f05076f movi v15.4s, #0xbb
+ 7ef0: 4f05078f movi v15.4s, #0xbc
+ 7ef4: 4f0507af movi v15.4s, #0xbd
+ 7ef8: 4f0507cf movi v15.4s, #0xbe
+ 7efc: 4f0507ef movi v15.4s, #0xbf
+ 7f00: 4f06040f movi v15.4s, #0xc0
+ 7f04: 4f06042f movi v15.4s, #0xc1
+ 7f08: 4f06044f movi v15.4s, #0xc2
+ 7f0c: 4f06046f movi v15.4s, #0xc3
+ 7f10: 4f06048f movi v15.4s, #0xc4
+ 7f14: 4f0604af movi v15.4s, #0xc5
+ 7f18: 4f0604cf movi v15.4s, #0xc6
+ 7f1c: 4f0604ef movi v15.4s, #0xc7
+ 7f20: 4f06050f movi v15.4s, #0xc8
+ 7f24: 4f06052f movi v15.4s, #0xc9
+ 7f28: 4f06054f movi v15.4s, #0xca
+ 7f2c: 4f06056f movi v15.4s, #0xcb
+ 7f30: 4f06058f movi v15.4s, #0xcc
+ 7f34: 4f0605af movi v15.4s, #0xcd
+ 7f38: 4f0605cf movi v15.4s, #0xce
+ 7f3c: 4f0605ef movi v15.4s, #0xcf
+ 7f40: 4f06060f movi v15.4s, #0xd0
+ 7f44: 4f06062f movi v15.4s, #0xd1
+ 7f48: 4f06064f movi v15.4s, #0xd2
+ 7f4c: 4f06066f movi v15.4s, #0xd3
+ 7f50: 4f06068f movi v15.4s, #0xd4
+ 7f54: 4f0606af movi v15.4s, #0xd5
+ 7f58: 4f0606cf movi v15.4s, #0xd6
+ 7f5c: 4f0606ef movi v15.4s, #0xd7
+ 7f60: 4f06070f movi v15.4s, #0xd8
+ 7f64: 4f06072f movi v15.4s, #0xd9
+ 7f68: 4f06074f movi v15.4s, #0xda
+ 7f6c: 4f06076f movi v15.4s, #0xdb
+ 7f70: 4f06078f movi v15.4s, #0xdc
+ 7f74: 4f0607af movi v15.4s, #0xdd
+ 7f78: 4f0607cf movi v15.4s, #0xde
+ 7f7c: 4f0607ef movi v15.4s, #0xdf
+ 7f80: 4f07040f movi v15.4s, #0xe0
+ 7f84: 4f07042f movi v15.4s, #0xe1
+ 7f88: 4f07044f movi v15.4s, #0xe2
+ 7f8c: 4f07046f movi v15.4s, #0xe3
+ 7f90: 4f07048f movi v15.4s, #0xe4
+ 7f94: 4f0704af movi v15.4s, #0xe5
+ 7f98: 4f0704cf movi v15.4s, #0xe6
+ 7f9c: 4f0704ef movi v15.4s, #0xe7
+ 7fa0: 4f07050f movi v15.4s, #0xe8
+ 7fa4: 4f07052f movi v15.4s, #0xe9
+ 7fa8: 4f07054f movi v15.4s, #0xea
+ 7fac: 4f07056f movi v15.4s, #0xeb
+ 7fb0: 4f07058f movi v15.4s, #0xec
+ 7fb4: 4f0705af movi v15.4s, #0xed
+ 7fb8: 4f0705cf movi v15.4s, #0xee
+ 7fbc: 4f0705ef movi v15.4s, #0xef
+ 7fc0: 4f07060f movi v15.4s, #0xf0
+ 7fc4: 4f07062f movi v15.4s, #0xf1
+ 7fc8: 4f07064f movi v15.4s, #0xf2
+ 7fcc: 4f07066f movi v15.4s, #0xf3
+ 7fd0: 4f07068f movi v15.4s, #0xf4
+ 7fd4: 4f0706af movi v15.4s, #0xf5
+ 7fd8: 4f0706cf movi v15.4s, #0xf6
+ 7fdc: 4f0706ef movi v15.4s, #0xf7
+ 7fe0: 4f07070f movi v15.4s, #0xf8
+ 7fe4: 4f07072f movi v15.4s, #0xf9
+ 7fe8: 4f07074f movi v15.4s, #0xfa
+ 7fec: 4f07076f movi v15.4s, #0xfb
+ 7ff0: 4f07078f movi v15.4s, #0xfc
+ 7ff4: 4f0707af movi v15.4s, #0xfd
+ 7ff8: 4f0707cf movi v15.4s, #0xfe
+ 7ffc: 4f0707ef movi v15.4s, #0xff
+ 8000: 6f07e7e0 movi v0.2d, #0xffffffffffffffff
+ 8004: 6f07e7e0 movi v0.2d, #0xffffffffffffffff
+ 8008: 6f07e7e0 movi v0.2d, #0xffffffffffffffff
+ 800c: 2f07e7ff movi d31, #0xffffffffffffffff
--- /dev/null
+// movi.s Test file for AArch64 AdvSIMD modified immediate instruction MOVI
+
+ .text
+
+ .macro all_64bit_mask_movi dst
+ .irp b7, 0, 0xff00000000000000
+ .irp b6, 0, 0xff000000000000
+ .irp b5, 0, 0xff0000000000
+ .irp b4, 0, 0xff00000000
+ .irp b3, 0, 0xff000000
+ .irp b2, 0, 0xff0000
+ .irp b1, 0, 0xff00
+ .irp b0, 0, 0xff
+ movi \dst, \b7 + \b6 + \b5 + \b4 + \b3 + \b2 + \b1 + \b0
+ .endr
+ .endr
+ .endr
+ .endr
+ .endr
+ .endr
+ .endr
+ .endr
+ .endm
+
+ // MOVI <Dd>, #<imm>
+ // MOVI <Vd>.2D, #<imm>
+ all_64bit_mask_movi d31
+ all_64bit_mask_movi v15.2d
+
+
+ .macro all_8bit_imm_movi dst, from=0, to=255
+ movi \dst, \from
+ .if \to-\from
+ all_8bit_imm_movi \dst, "(\from+1)", \to
+ .endif
+ .endm
+
+ // Per byte
+ // MOVI <Vd>.<T>, #<imm8>
+ .irp T, 8b, 16b
+ all_8bit_imm_movi v15.\T, 0, 63
+ all_8bit_imm_movi v15.\T, 64, 127
+ all_8bit_imm_movi v15.\T, 128, 191
+ all_8bit_imm_movi v15.\T, 192, 255
+ .endr
+
+
+ .macro all_8bit_imm_movi_sft dst, from=0, to=255, shift_op, amount
+ movi \dst, \from, \shift_op \amount
+ .if \to-\from
+ all_8bit_imm_movi_sft \dst, "(\from+1)", \to, \shift_op, \amount
+ .endif
+ .endm
+
+ // Shift ones, per word
+ // MOVI <Vd>.<T>, #<imm8>, MSL #<amount>
+ .irp T, 2s, 4s
+ .irp amount, 8, 16
+ // Have to break into four chunks to avoid "Fatal error: macros nested
+ // too deeply".
+ all_8bit_imm_movi_sft v7.\T, 0, 63, MSL, \amount
+ all_8bit_imm_movi_sft v7.\T, 64, 127, MSL, \amount
+ all_8bit_imm_movi_sft v7.\T, 128, 191, MSL, \amount
+ all_8bit_imm_movi_sft v7.\T, 192, 255, MSL, \amount
+ .endr
+ .endr
+
+
+ // Shift zeros, per halfword
+ // MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}
+ .irp T, 4h, 8h
+ .irp amount, 0, 8
+ all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, \amount
+ all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, \amount
+ all_8bit_imm_movi_sft v7.\T, 128, 191, LSL, \amount
+ all_8bit_imm_movi_sft v7.\T, 192, 255, LSL, \amount
+ all_8bit_imm_movi v15.\T, 0, 63
+ all_8bit_imm_movi v15.\T, 64, 127
+ all_8bit_imm_movi v15.\T, 128, 191
+ all_8bit_imm_movi v15.\T, 192, 255
+ .endr
+ .endr
+
+
+ // Shift zeros, per word
+ // MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}
+ .irp T, 2s, 4s
+ .irp amount, 0, 8, 16, 24
+ all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, \amount
+ all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, \amount
+ all_8bit_imm_movi_sft v7.\T, 128, 191, LSL, \amount
+ all_8bit_imm_movi_sft v7.\T, 192, 255, LSL, \amount
+ all_8bit_imm_movi v15.\T, 0, 63
+ all_8bit_imm_movi v15.\T, 64, 127
+ all_8bit_imm_movi v15.\T, 128, 191
+ all_8bit_imm_movi v15.\T, 192, 255
+ .endr
+ .endr
+
+ movi v0.2d, 18446744073709551615
+ movi v0.2d, -1
+ movi v0.2d, bignum
+ movi d31, 18446744073709551615
+.set bignum, 0xffffffffffffffff
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: d50340df msr daifset, #0x0
+ 4: d50341df msr daifset, #0x1
+ 8: d5034fdf msr daifset, #0xf
+ c: d50340ff msr daifclr, #0x0
+ 10: d50341ff msr daifclr, #0x1
+ 14: d5034fff msr daifclr, #0xf
+ 18: d51b4220 msr daif, x0
+ 1c: d53b4220 mrs x0, daif
--- /dev/null
+/*
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+func:
+ msr daifset, #0
+ msr daifset, #1
+ msr daifset, #15
+
+
+
+ msr daifclr, #0
+ msr daifclr, #1
+ msr daifclr, #15
+
+ msr daif, x0
+ mrs x0, daif
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 0e21a8e7 fcvtns v7.2s, v7.2s
+ 4: 2e21a8e7 fcvtnu v7.2s, v7.2s
+ 8: 0ea1a8e7 fcvtps v7.2s, v7.2s
+ c: 2ea1a8e7 fcvtpu v7.2s, v7.2s
+ 10: 0e21d8e7 scvtf v7.2s, v7.2s
+ 14: 2e21d8e7 ucvtf v7.2s, v7.2s
+ 18: 0e21b8e7 fcvtms v7.2s, v7.2s
+ 1c: 2e21b8e7 fcvtmu v7.2s, v7.2s
+ 20: 0ea1b8e7 fcvtzs v7.2s, v7.2s
+ 24: 2ea1b8e7 fcvtzu v7.2s, v7.2s
+ 28: 0e21c8e7 fcvtas v7.2s, v7.2s
+ 2c: 2e21c8e7 fcvtau v7.2s, v7.2s
+ 30: 4e21a8e7 fcvtns v7.4s, v7.4s
+ 34: 6e21a8e7 fcvtnu v7.4s, v7.4s
+ 38: 4ea1a8e7 fcvtps v7.4s, v7.4s
+ 3c: 6ea1a8e7 fcvtpu v7.4s, v7.4s
+ 40: 4e21d8e7 scvtf v7.4s, v7.4s
+ 44: 6e21d8e7 ucvtf v7.4s, v7.4s
+ 48: 4e21b8e7 fcvtms v7.4s, v7.4s
+ 4c: 6e21b8e7 fcvtmu v7.4s, v7.4s
+ 50: 4ea1b8e7 fcvtzs v7.4s, v7.4s
+ 54: 6ea1b8e7 fcvtzu v7.4s, v7.4s
+ 58: 4e21c8e7 fcvtas v7.4s, v7.4s
+ 5c: 6e21c8e7 fcvtau v7.4s, v7.4s
+ 60: 4e61a8e7 fcvtns v7.2d, v7.2d
+ 64: 6e61a8e7 fcvtnu v7.2d, v7.2d
+ 68: 4ee1a8e7 fcvtps v7.2d, v7.2d
+ 6c: 6ee1a8e7 fcvtpu v7.2d, v7.2d
+ 70: 4e61d8e7 scvtf v7.2d, v7.2d
+ 74: 6e61d8e7 ucvtf v7.2d, v7.2d
+ 78: 4e61b8e7 fcvtms v7.2d, v7.2d
+ 7c: 6e61b8e7 fcvtmu v7.2d, v7.2d
+ 80: 4ee1b8e7 fcvtzs v7.2d, v7.2d
+ 84: 6ee1b8e7 fcvtzu v7.2d, v7.2d
+ 88: 4e61c8e7 fcvtas v7.2d, v7.2d
+ 8c: 6e61c8e7 fcvtau v7.2d, v7.2d
+ 90: 5e21a8e7 fcvtns s7, s7
+ 94: 7e21a8e7 fcvtnu s7, s7
+ 98: 5ea1a8e7 fcvtps s7, s7
+ 9c: 7ea1a8e7 fcvtpu s7, s7
+ a0: 5e21d8e7 scvtf s7, s7
+ a4: 7e21d8e7 ucvtf s7, s7
+ a8: 5e21b8e7 fcvtms s7, s7
+ ac: 7e21b8e7 fcvtmu s7, s7
+ b0: 5ea1b8e7 fcvtzs s7, s7
+ b4: 7ea1b8e7 fcvtzu s7, s7
+ b8: 5e21c8e7 fcvtas s7, s7
+ bc: 7e21c8e7 fcvtau s7, s7
+ c0: 5e61a8e7 fcvtns d7, d7
+ c4: 7e61a8e7 fcvtnu d7, d7
+ c8: 5ee1a8e7 fcvtps d7, d7
+ cc: 7ee1a8e7 fcvtpu d7, d7
+ d0: 5e61d8e7 scvtf d7, d7
+ d4: 7e61d8e7 ucvtf d7, d7
+ d8: 5e61b8e7 fcvtms d7, d7
+ dc: 7e61b8e7 fcvtmu d7, d7
+ e0: 5ee1b8e7 fcvtzs d7, d7
+ e4: 7ee1b8e7 fcvtzu d7, d7
+ e8: 5e61c8e7 fcvtas d7, d7
+ ec: 7e61c8e7 fcvtau d7, d7
+ f0: 0f3fe4e7 scvtf v7.2s, v7.2s, #1
+ f4: 2f3fe4e7 ucvtf v7.2s, v7.2s, #1
+ f8: 0f3ffce7 fcvtzs v7.2s, v7.2s, #1
+ fc: 2f3ffce7 fcvtzu v7.2s, v7.2s, #1
+ 100: 4f3fe4e7 scvtf v7.4s, v7.4s, #1
+ 104: 6f3fe4e7 ucvtf v7.4s, v7.4s, #1
+ 108: 4f3ffce7 fcvtzs v7.4s, v7.4s, #1
+ 10c: 6f3ffce7 fcvtzu v7.4s, v7.4s, #1
+ 110: 4f7fe4e7 scvtf v7.2d, v7.2d, #1
+ 114: 6f7fe4e7 ucvtf v7.2d, v7.2d, #1
+ 118: 4f7ffce7 fcvtzs v7.2d, v7.2d, #1
+ 11c: 6f7ffce7 fcvtzu v7.2d, v7.2d, #1
+ 120: 5f3fe4e7 scvtf s7, s7, #1
+ 124: 7f3fe4e7 ucvtf s7, s7, #1
+ 128: 5f3ffce7 fcvtzs s7, s7, #1
+ 12c: 7f3ffce7 fcvtzu s7, s7, #1
+ 130: 5f7fe4e7 scvtf d7, d7, #1
+ 134: 7f7fe4e7 ucvtf d7, d7, #1
+ 138: 5f7ffce7 fcvtzs d7, d7, #1
+ 13c: 7f7ffce7 fcvtzu d7, d7, #1
+ 140: 0f3ee4e7 scvtf v7.2s, v7.2s, #2
+ 144: 2f3ee4e7 ucvtf v7.2s, v7.2s, #2
+ 148: 0f3efce7 fcvtzs v7.2s, v7.2s, #2
+ 14c: 2f3efce7 fcvtzu v7.2s, v7.2s, #2
+ 150: 4f3ee4e7 scvtf v7.4s, v7.4s, #2
+ 154: 6f3ee4e7 ucvtf v7.4s, v7.4s, #2
+ 158: 4f3efce7 fcvtzs v7.4s, v7.4s, #2
+ 15c: 6f3efce7 fcvtzu v7.4s, v7.4s, #2
+ 160: 4f7ee4e7 scvtf v7.2d, v7.2d, #2
+ 164: 6f7ee4e7 ucvtf v7.2d, v7.2d, #2
+ 168: 4f7efce7 fcvtzs v7.2d, v7.2d, #2
+ 16c: 6f7efce7 fcvtzu v7.2d, v7.2d, #2
+ 170: 5f3ee4e7 scvtf s7, s7, #2
+ 174: 7f3ee4e7 ucvtf s7, s7, #2
+ 178: 5f3efce7 fcvtzs s7, s7, #2
+ 17c: 7f3efce7 fcvtzu s7, s7, #2
+ 180: 5f7ee4e7 scvtf d7, d7, #2
+ 184: 7f7ee4e7 ucvtf d7, d7, #2
+ 188: 5f7efce7 fcvtzs d7, d7, #2
+ 18c: 7f7efce7 fcvtzu d7, d7, #2
+ 190: 0f3de4e7 scvtf v7.2s, v7.2s, #3
+ 194: 2f3de4e7 ucvtf v7.2s, v7.2s, #3
+ 198: 0f3dfce7 fcvtzs v7.2s, v7.2s, #3
+ 19c: 2f3dfce7 fcvtzu v7.2s, v7.2s, #3
+ 1a0: 4f3de4e7 scvtf v7.4s, v7.4s, #3
+ 1a4: 6f3de4e7 ucvtf v7.4s, v7.4s, #3
+ 1a8: 4f3dfce7 fcvtzs v7.4s, v7.4s, #3
+ 1ac: 6f3dfce7 fcvtzu v7.4s, v7.4s, #3
+ 1b0: 4f7de4e7 scvtf v7.2d, v7.2d, #3
+ 1b4: 6f7de4e7 ucvtf v7.2d, v7.2d, #3
+ 1b8: 4f7dfce7 fcvtzs v7.2d, v7.2d, #3
+ 1bc: 6f7dfce7 fcvtzu v7.2d, v7.2d, #3
+ 1c0: 5f3de4e7 scvtf s7, s7, #3
+ 1c4: 7f3de4e7 ucvtf s7, s7, #3
+ 1c8: 5f3dfce7 fcvtzs s7, s7, #3
+ 1cc: 7f3dfce7 fcvtzu s7, s7, #3
+ 1d0: 5f7de4e7 scvtf d7, d7, #3
+ 1d4: 7f7de4e7 ucvtf d7, d7, #3
+ 1d8: 5f7dfce7 fcvtzs d7, d7, #3
+ 1dc: 7f7dfce7 fcvtzu d7, d7, #3
+ 1e0: 0f3ce4e7 scvtf v7.2s, v7.2s, #4
+ 1e4: 2f3ce4e7 ucvtf v7.2s, v7.2s, #4
+ 1e8: 0f3cfce7 fcvtzs v7.2s, v7.2s, #4
+ 1ec: 2f3cfce7 fcvtzu v7.2s, v7.2s, #4
+ 1f0: 4f3ce4e7 scvtf v7.4s, v7.4s, #4
+ 1f4: 6f3ce4e7 ucvtf v7.4s, v7.4s, #4
+ 1f8: 4f3cfce7 fcvtzs v7.4s, v7.4s, #4
+ 1fc: 6f3cfce7 fcvtzu v7.4s, v7.4s, #4
+ 200: 4f7ce4e7 scvtf v7.2d, v7.2d, #4
+ 204: 6f7ce4e7 ucvtf v7.2d, v7.2d, #4
+ 208: 4f7cfce7 fcvtzs v7.2d, v7.2d, #4
+ 20c: 6f7cfce7 fcvtzu v7.2d, v7.2d, #4
+ 210: 5f3ce4e7 scvtf s7, s7, #4
+ 214: 7f3ce4e7 ucvtf s7, s7, #4
+ 218: 5f3cfce7 fcvtzs s7, s7, #4
+ 21c: 7f3cfce7 fcvtzu s7, s7, #4
+ 220: 5f7ce4e7 scvtf d7, d7, #4
+ 224: 7f7ce4e7 ucvtf d7, d7, #4
+ 228: 5f7cfce7 fcvtzs d7, d7, #4
+ 22c: 7f7cfce7 fcvtzu d7, d7, #4
+ 230: 0f3be4e7 scvtf v7.2s, v7.2s, #5
+ 234: 2f3be4e7 ucvtf v7.2s, v7.2s, #5
+ 238: 0f3bfce7 fcvtzs v7.2s, v7.2s, #5
+ 23c: 2f3bfce7 fcvtzu v7.2s, v7.2s, #5
+ 240: 4f3be4e7 scvtf v7.4s, v7.4s, #5
+ 244: 6f3be4e7 ucvtf v7.4s, v7.4s, #5
+ 248: 4f3bfce7 fcvtzs v7.4s, v7.4s, #5
+ 24c: 6f3bfce7 fcvtzu v7.4s, v7.4s, #5
+ 250: 4f7be4e7 scvtf v7.2d, v7.2d, #5
+ 254: 6f7be4e7 ucvtf v7.2d, v7.2d, #5
+ 258: 4f7bfce7 fcvtzs v7.2d, v7.2d, #5
+ 25c: 6f7bfce7 fcvtzu v7.2d, v7.2d, #5
+ 260: 5f3be4e7 scvtf s7, s7, #5
+ 264: 7f3be4e7 ucvtf s7, s7, #5
+ 268: 5f3bfce7 fcvtzs s7, s7, #5
+ 26c: 7f3bfce7 fcvtzu s7, s7, #5
+ 270: 5f7be4e7 scvtf d7, d7, #5
+ 274: 7f7be4e7 ucvtf d7, d7, #5
+ 278: 5f7bfce7 fcvtzs d7, d7, #5
+ 27c: 7f7bfce7 fcvtzu d7, d7, #5
+ 280: 0f3ae4e7 scvtf v7.2s, v7.2s, #6
+ 284: 2f3ae4e7 ucvtf v7.2s, v7.2s, #6
+ 288: 0f3afce7 fcvtzs v7.2s, v7.2s, #6
+ 28c: 2f3afce7 fcvtzu v7.2s, v7.2s, #6
+ 290: 4f3ae4e7 scvtf v7.4s, v7.4s, #6
+ 294: 6f3ae4e7 ucvtf v7.4s, v7.4s, #6
+ 298: 4f3afce7 fcvtzs v7.4s, v7.4s, #6
+ 29c: 6f3afce7 fcvtzu v7.4s, v7.4s, #6
+ 2a0: 4f7ae4e7 scvtf v7.2d, v7.2d, #6
+ 2a4: 6f7ae4e7 ucvtf v7.2d, v7.2d, #6
+ 2a8: 4f7afce7 fcvtzs v7.2d, v7.2d, #6
+ 2ac: 6f7afce7 fcvtzu v7.2d, v7.2d, #6
+ 2b0: 5f3ae4e7 scvtf s7, s7, #6
+ 2b4: 7f3ae4e7 ucvtf s7, s7, #6
+ 2b8: 5f3afce7 fcvtzs s7, s7, #6
+ 2bc: 7f3afce7 fcvtzu s7, s7, #6
+ 2c0: 5f7ae4e7 scvtf d7, d7, #6
+ 2c4: 7f7ae4e7 ucvtf d7, d7, #6
+ 2c8: 5f7afce7 fcvtzs d7, d7, #6
+ 2cc: 7f7afce7 fcvtzu d7, d7, #6
+ 2d0: 0f39e4e7 scvtf v7.2s, v7.2s, #7
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+ c00: 5f57e4e7 scvtf d7, d7, #41
+ c04: 7f57e4e7 ucvtf d7, d7, #41
+ c08: 5f57fce7 fcvtzs d7, d7, #41
+ c0c: 7f57fce7 fcvtzu d7, d7, #41
+ c10: 4f56e4e7 scvtf v7.2d, v7.2d, #42
+ c14: 6f56e4e7 ucvtf v7.2d, v7.2d, #42
+ c18: 4f56fce7 fcvtzs v7.2d, v7.2d, #42
+ c1c: 6f56fce7 fcvtzu v7.2d, v7.2d, #42
+ c20: 5f56e4e7 scvtf d7, d7, #42
+ c24: 7f56e4e7 ucvtf d7, d7, #42
+ c28: 5f56fce7 fcvtzs d7, d7, #42
+ c2c: 7f56fce7 fcvtzu d7, d7, #42
+ c30: 4f55e4e7 scvtf v7.2d, v7.2d, #43
+ c34: 6f55e4e7 ucvtf v7.2d, v7.2d, #43
+ c38: 4f55fce7 fcvtzs v7.2d, v7.2d, #43
+ c3c: 6f55fce7 fcvtzu v7.2d, v7.2d, #43
+ c40: 5f55e4e7 scvtf d7, d7, #43
+ c44: 7f55e4e7 ucvtf d7, d7, #43
+ c48: 5f55fce7 fcvtzs d7, d7, #43
+ c4c: 7f55fce7 fcvtzu d7, d7, #43
+ c50: 4f54e4e7 scvtf v7.2d, v7.2d, #44
+ c54: 6f54e4e7 ucvtf v7.2d, v7.2d, #44
+ c58: 4f54fce7 fcvtzs v7.2d, v7.2d, #44
+ c5c: 6f54fce7 fcvtzu v7.2d, v7.2d, #44
+ c60: 5f54e4e7 scvtf d7, d7, #44
+ c64: 7f54e4e7 ucvtf d7, d7, #44
+ c68: 5f54fce7 fcvtzs d7, d7, #44
+ c6c: 7f54fce7 fcvtzu d7, d7, #44
+ c70: 4f53e4e7 scvtf v7.2d, v7.2d, #45
+ c74: 6f53e4e7 ucvtf v7.2d, v7.2d, #45
+ c78: 4f53fce7 fcvtzs v7.2d, v7.2d, #45
+ c7c: 6f53fce7 fcvtzu v7.2d, v7.2d, #45
+ c80: 5f53e4e7 scvtf d7, d7, #45
+ c84: 7f53e4e7 ucvtf d7, d7, #45
+ c88: 5f53fce7 fcvtzs d7, d7, #45
+ c8c: 7f53fce7 fcvtzu d7, d7, #45
+ c90: 4f52e4e7 scvtf v7.2d, v7.2d, #46
+ c94: 6f52e4e7 ucvtf v7.2d, v7.2d, #46
+ c98: 4f52fce7 fcvtzs v7.2d, v7.2d, #46
+ c9c: 6f52fce7 fcvtzu v7.2d, v7.2d, #46
+ ca0: 5f52e4e7 scvtf d7, d7, #46
+ ca4: 7f52e4e7 ucvtf d7, d7, #46
+ ca8: 5f52fce7 fcvtzs d7, d7, #46
+ cac: 7f52fce7 fcvtzu d7, d7, #46
+ cb0: 4f51e4e7 scvtf v7.2d, v7.2d, #47
+ cb4: 6f51e4e7 ucvtf v7.2d, v7.2d, #47
+ cb8: 4f51fce7 fcvtzs v7.2d, v7.2d, #47
+ cbc: 6f51fce7 fcvtzu v7.2d, v7.2d, #47
+ cc0: 5f51e4e7 scvtf d7, d7, #47
+ cc4: 7f51e4e7 ucvtf d7, d7, #47
+ cc8: 5f51fce7 fcvtzs d7, d7, #47
+ ccc: 7f51fce7 fcvtzu d7, d7, #47
+ cd0: 4f50e4e7 scvtf v7.2d, v7.2d, #48
+ cd4: 6f50e4e7 ucvtf v7.2d, v7.2d, #48
+ cd8: 4f50fce7 fcvtzs v7.2d, v7.2d, #48
+ cdc: 6f50fce7 fcvtzu v7.2d, v7.2d, #48
+ ce0: 5f50e4e7 scvtf d7, d7, #48
+ ce4: 7f50e4e7 ucvtf d7, d7, #48
+ ce8: 5f50fce7 fcvtzs d7, d7, #48
+ cec: 7f50fce7 fcvtzu d7, d7, #48
+ cf0: 4f4fe4e7 scvtf v7.2d, v7.2d, #49
+ cf4: 6f4fe4e7 ucvtf v7.2d, v7.2d, #49
+ cf8: 4f4ffce7 fcvtzs v7.2d, v7.2d, #49
+ cfc: 6f4ffce7 fcvtzu v7.2d, v7.2d, #49
+ d00: 5f4fe4e7 scvtf d7, d7, #49
+ d04: 7f4fe4e7 ucvtf d7, d7, #49
+ d08: 5f4ffce7 fcvtzs d7, d7, #49
+ d0c: 7f4ffce7 fcvtzu d7, d7, #49
+ d10: 4f4ee4e7 scvtf v7.2d, v7.2d, #50
+ d14: 6f4ee4e7 ucvtf v7.2d, v7.2d, #50
+ d18: 4f4efce7 fcvtzs v7.2d, v7.2d, #50
+ d1c: 6f4efce7 fcvtzu v7.2d, v7.2d, #50
+ d20: 5f4ee4e7 scvtf d7, d7, #50
+ d24: 7f4ee4e7 ucvtf d7, d7, #50
+ d28: 5f4efce7 fcvtzs d7, d7, #50
+ d2c: 7f4efce7 fcvtzu d7, d7, #50
+ d30: 4f4de4e7 scvtf v7.2d, v7.2d, #51
+ d34: 6f4de4e7 ucvtf v7.2d, v7.2d, #51
+ d38: 4f4dfce7 fcvtzs v7.2d, v7.2d, #51
+ d3c: 6f4dfce7 fcvtzu v7.2d, v7.2d, #51
+ d40: 5f4de4e7 scvtf d7, d7, #51
+ d44: 7f4de4e7 ucvtf d7, d7, #51
+ d48: 5f4dfce7 fcvtzs d7, d7, #51
+ d4c: 7f4dfce7 fcvtzu d7, d7, #51
+ d50: 4f4ce4e7 scvtf v7.2d, v7.2d, #52
+ d54: 6f4ce4e7 ucvtf v7.2d, v7.2d, #52
+ d58: 4f4cfce7 fcvtzs v7.2d, v7.2d, #52
+ d5c: 6f4cfce7 fcvtzu v7.2d, v7.2d, #52
+ d60: 5f4ce4e7 scvtf d7, d7, #52
+ d64: 7f4ce4e7 ucvtf d7, d7, #52
+ d68: 5f4cfce7 fcvtzs d7, d7, #52
+ d6c: 7f4cfce7 fcvtzu d7, d7, #52
+ d70: 4f4be4e7 scvtf v7.2d, v7.2d, #53
+ d74: 6f4be4e7 ucvtf v7.2d, v7.2d, #53
+ d78: 4f4bfce7 fcvtzs v7.2d, v7.2d, #53
+ d7c: 6f4bfce7 fcvtzu v7.2d, v7.2d, #53
+ d80: 5f4be4e7 scvtf d7, d7, #53
+ d84: 7f4be4e7 ucvtf d7, d7, #53
+ d88: 5f4bfce7 fcvtzs d7, d7, #53
+ d8c: 7f4bfce7 fcvtzu d7, d7, #53
+ d90: 4f4ae4e7 scvtf v7.2d, v7.2d, #54
+ d94: 6f4ae4e7 ucvtf v7.2d, v7.2d, #54
+ d98: 4f4afce7 fcvtzs v7.2d, v7.2d, #54
+ d9c: 6f4afce7 fcvtzu v7.2d, v7.2d, #54
+ da0: 5f4ae4e7 scvtf d7, d7, #54
+ da4: 7f4ae4e7 ucvtf d7, d7, #54
+ da8: 5f4afce7 fcvtzs d7, d7, #54
+ dac: 7f4afce7 fcvtzu d7, d7, #54
+ db0: 4f49e4e7 scvtf v7.2d, v7.2d, #55
+ db4: 6f49e4e7 ucvtf v7.2d, v7.2d, #55
+ db8: 4f49fce7 fcvtzs v7.2d, v7.2d, #55
+ dbc: 6f49fce7 fcvtzu v7.2d, v7.2d, #55
+ dc0: 5f49e4e7 scvtf d7, d7, #55
+ dc4: 7f49e4e7 ucvtf d7, d7, #55
+ dc8: 5f49fce7 fcvtzs d7, d7, #55
+ dcc: 7f49fce7 fcvtzu d7, d7, #55
+ dd0: 4f48e4e7 scvtf v7.2d, v7.2d, #56
+ dd4: 6f48e4e7 ucvtf v7.2d, v7.2d, #56
+ dd8: 4f48fce7 fcvtzs v7.2d, v7.2d, #56
+ ddc: 6f48fce7 fcvtzu v7.2d, v7.2d, #56
+ de0: 5f48e4e7 scvtf d7, d7, #56
+ de4: 7f48e4e7 ucvtf d7, d7, #56
+ de8: 5f48fce7 fcvtzs d7, d7, #56
+ dec: 7f48fce7 fcvtzu d7, d7, #56
+ df0: 4f47e4e7 scvtf v7.2d, v7.2d, #57
+ df4: 6f47e4e7 ucvtf v7.2d, v7.2d, #57
+ df8: 4f47fce7 fcvtzs v7.2d, v7.2d, #57
+ dfc: 6f47fce7 fcvtzu v7.2d, v7.2d, #57
+ e00: 5f47e4e7 scvtf d7, d7, #57
+ e04: 7f47e4e7 ucvtf d7, d7, #57
+ e08: 5f47fce7 fcvtzs d7, d7, #57
+ e0c: 7f47fce7 fcvtzu d7, d7, #57
+ e10: 4f46e4e7 scvtf v7.2d, v7.2d, #58
+ e14: 6f46e4e7 ucvtf v7.2d, v7.2d, #58
+ e18: 4f46fce7 fcvtzs v7.2d, v7.2d, #58
+ e1c: 6f46fce7 fcvtzu v7.2d, v7.2d, #58
+ e20: 5f46e4e7 scvtf d7, d7, #58
+ e24: 7f46e4e7 ucvtf d7, d7, #58
+ e28: 5f46fce7 fcvtzs d7, d7, #58
+ e2c: 7f46fce7 fcvtzu d7, d7, #58
+ e30: 4f45e4e7 scvtf v7.2d, v7.2d, #59
+ e34: 6f45e4e7 ucvtf v7.2d, v7.2d, #59
+ e38: 4f45fce7 fcvtzs v7.2d, v7.2d, #59
+ e3c: 6f45fce7 fcvtzu v7.2d, v7.2d, #59
+ e40: 5f45e4e7 scvtf d7, d7, #59
+ e44: 7f45e4e7 ucvtf d7, d7, #59
+ e48: 5f45fce7 fcvtzs d7, d7, #59
+ e4c: 7f45fce7 fcvtzu d7, d7, #59
+ e50: 4f44e4e7 scvtf v7.2d, v7.2d, #60
+ e54: 6f44e4e7 ucvtf v7.2d, v7.2d, #60
+ e58: 4f44fce7 fcvtzs v7.2d, v7.2d, #60
+ e5c: 6f44fce7 fcvtzu v7.2d, v7.2d, #60
+ e60: 5f44e4e7 scvtf d7, d7, #60
+ e64: 7f44e4e7 ucvtf d7, d7, #60
+ e68: 5f44fce7 fcvtzs d7, d7, #60
+ e6c: 7f44fce7 fcvtzu d7, d7, #60
+ e70: 4f43e4e7 scvtf v7.2d, v7.2d, #61
+ e74: 6f43e4e7 ucvtf v7.2d, v7.2d, #61
+ e78: 4f43fce7 fcvtzs v7.2d, v7.2d, #61
+ e7c: 6f43fce7 fcvtzu v7.2d, v7.2d, #61
+ e80: 5f43e4e7 scvtf d7, d7, #61
+ e84: 7f43e4e7 ucvtf d7, d7, #61
+ e88: 5f43fce7 fcvtzs d7, d7, #61
+ e8c: 7f43fce7 fcvtzu d7, d7, #61
+ e90: 4f42e4e7 scvtf v7.2d, v7.2d, #62
+ e94: 6f42e4e7 ucvtf v7.2d, v7.2d, #62
+ e98: 4f42fce7 fcvtzs v7.2d, v7.2d, #62
+ e9c: 6f42fce7 fcvtzu v7.2d, v7.2d, #62
+ ea0: 5f42e4e7 scvtf d7, d7, #62
+ ea4: 7f42e4e7 ucvtf d7, d7, #62
+ ea8: 5f42fce7 fcvtzs d7, d7, #62
+ eac: 7f42fce7 fcvtzu d7, d7, #62
+ eb0: 4f41e4e7 scvtf v7.2d, v7.2d, #63
+ eb4: 6f41e4e7 ucvtf v7.2d, v7.2d, #63
+ eb8: 4f41fce7 fcvtzs v7.2d, v7.2d, #63
+ ebc: 6f41fce7 fcvtzu v7.2d, v7.2d, #63
+ ec0: 5f41e4e7 scvtf d7, d7, #63
+ ec4: 7f41e4e7 ucvtf d7, d7, #63
+ ec8: 5f41fce7 fcvtzs d7, d7, #63
+ ecc: 7f41fce7 fcvtzu d7, d7, #63
+ ed0: 4f40e4e7 scvtf v7.2d, v7.2d, #64
+ ed4: 6f40e4e7 ucvtf v7.2d, v7.2d, #64
+ ed8: 4f40fce7 fcvtzs v7.2d, v7.2d, #64
+ edc: 6f40fce7 fcvtzu v7.2d, v7.2d, #64
+ ee0: 5f40e4e7 scvtf d7, d7, #64
+ ee4: 7f40e4e7 ucvtf d7, d7, #64
+ ee8: 5f40fce7 fcvtzs d7, d7, #64
+ eec: 7f40fce7 fcvtzu d7, d7, #64
--- /dev/null
+/* neon-fp-cvt-ins.s Test file for AArch64 NEON
+ floating-point<->fixed-point conversion and
+ floating-point<->integer conversion instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro do_cvt op, fbits, reg, reg_shape
+ .ifc \fbits, 0
+ // Floating-point<->integer conversions
+ .ifc \reg, V
+ \op V7.\()\reg_shape, V7.\()\reg_shape
+ .else
+ \op \reg\()7, \reg\()7
+ .endif
+ .else
+ // Floating-point<->fixed-point conversions
+ .ifc \reg, V
+ .ifle \fbits-32
+ .ifc \reg_shape, 2S
+ \op V7.2S, V7.2S, #\fbits
+ .endif
+ .ifc \reg_shape, 4S
+ \op V7.4S, V7.4S, #\fbits
+ .endif
+ .endif
+ .ifc \reg_shape, 2D
+ \op V7.2D, V7.2D, #\fbits
+ .endif
+ .else
+ .ifc \reg, S
+ .ifle \fbits-32
+ \op S7, S7, #\fbits
+ .endif
+ .endif
+ .ifc \reg, D
+ \op D7, D7, #\fbits
+ .endif
+ .endif
+ .endif
+ .endm
+
+ .macro fcvts_with_fbits fbits
+ .ifc \fbits, 0
+ // fp <-> int
+ // AdvSIMD
+ .irp reg_shape, 2S, 4S, 2D
+ do_cvt FCVTNS, \fbits, V, \reg_shape
+ do_cvt FCVTNU, \fbits, V, \reg_shape
+ do_cvt FCVTPS, \fbits, V, \reg_shape
+ do_cvt FCVTPU, \fbits, V, \reg_shape
+ do_cvt SCVTF, \fbits, V, \reg_shape
+ do_cvt UCVTF, \fbits, V, \reg_shape
+ do_cvt FCVTMS, \fbits, V, \reg_shape
+ do_cvt FCVTMU, \fbits, V, \reg_shape
+ do_cvt FCVTZS, \fbits, V, \reg_shape
+ do_cvt FCVTZU, \fbits, V, \reg_shape
+ do_cvt FCVTAS, \fbits, V, \reg_shape
+ do_cvt FCVTAU, \fbits, V, \reg_shape
+ .endr
+ // AdvSISD
+ .irp reg, S, D
+ do_cvt FCVTNS, \fbits, \reg
+ do_cvt FCVTNU, \fbits, \reg
+ do_cvt FCVTPS, \fbits, \reg
+ do_cvt FCVTPU, \fbits, \reg
+ do_cvt SCVTF, \fbits, \reg
+ do_cvt UCVTF, \fbits, \reg
+ do_cvt FCVTMS, \fbits, \reg
+ do_cvt FCVTMU, \fbits, \reg
+ do_cvt FCVTZS, \fbits, \reg
+ do_cvt FCVTZU, \fbits, \reg
+ do_cvt FCVTAS, \fbits, \reg
+ do_cvt FCVTAU, \fbits, \reg
+ .endr
+ .else
+ // fp <-> fixed-point
+ // AdvSIMD
+ .irp reg_shape, 2S, 4S, 2D
+ do_cvt SCVTF, \fbits, V, \reg_shape
+ do_cvt UCVTF, \fbits, V, \reg_shape
+ do_cvt FCVTZS, \fbits, V, \reg_shape
+ do_cvt FCVTZU, \fbits, V, \reg_shape
+ .endr
+ // AdvSISD
+ .irp reg, S, D
+ do_cvt SCVTF, \fbits, \reg
+ do_cvt UCVTF, \fbits, \reg
+ do_cvt FCVTZS, \fbits, \reg
+ do_cvt FCVTZU, \fbits, \reg
+ .endr
+ .endif
+ .endm
+
+
+ .macro fcvts_with_fbits_wrapper from=0, to=64
+ fcvts_with_fbits \from
+ .if \to-\from
+ fcvts_with_fbits_wrapper "(\from+1)", \to
+ .endif
+ .endm
+
+func:
+ // Generate fcvt instructions without fbits and
+ // with fbits from 1 to 64, also generate [us]cvtf
+ fcvts_with_fbits_wrapper from=0, to=64
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 0e2188e7 frintn v7.2s, v7.2s
+ 4: 4e2188e7 frintn v7.4s, v7.4s
+ 8: 4e6188e7 frintn v7.2d, v7.2d
+ c: 2e2188e7 frinta v7.2s, v7.2s
+ 10: 6e2188e7 frinta v7.4s, v7.4s
+ 14: 6e6188e7 frinta v7.2d, v7.2d
+ 18: 0ea188e7 frintp v7.2s, v7.2s
+ 1c: 4ea188e7 frintp v7.4s, v7.4s
+ 20: 4ee188e7 frintp v7.2d, v7.2d
+ 24: 0e2198e7 frintm v7.2s, v7.2s
+ 28: 4e2198e7 frintm v7.4s, v7.4s
+ 2c: 4e6198e7 frintm v7.2d, v7.2d
+ 30: 2e2198e7 frintx v7.2s, v7.2s
+ 34: 6e2198e7 frintx v7.4s, v7.4s
+ 38: 6e6198e7 frintx v7.2d, v7.2d
+ 3c: 0ea198e7 frintz v7.2s, v7.2s
+ 40: 4ea198e7 frintz v7.4s, v7.4s
+ 44: 4ee198e7 frintz v7.2d, v7.2d
+ 48: 2ea198e7 frinti v7.2s, v7.2s
+ 4c: 6ea198e7 frinti v7.4s, v7.4s
+ 50: 6ee198e7 frinti v7.2d, v7.2d
--- /dev/null
+// Test file for AArch64 GAS -- Advanced SIMD floating-point round to integral
+// instructions.
+
+ .macro frint_main rd rn
+ .irp rounding_mode, N, A, P, M, X, Z, I
+ .irp reg_shape, 2S, 4S, 2D
+ frint\rounding_mode \rd\().\reg_shape, \rn\().\reg_shape
+ .endr
+ .endr
+ .endm
+
+ .text
+ frint_main v7, v7
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 4e011c21 mov v1.b\[0\], w1
+ 4: 4e011c21 mov v1.b\[0\], w1
+ 8: 4e011c42 mov v2.b\[0\], w2
+ c: 4e011c42 mov v2.b\[0\], w2
+ 10: 4e011c63 mov v3.b\[0\], w3
+ 14: 4e011c63 mov v3.b\[0\], w3
+ 18: 4e011c84 mov v4.b\[0\], w4
+ 1c: 4e011c84 mov v4.b\[0\], w4
+ 20: 4e011ca5 mov v5.b\[0\], w5
+ 24: 4e011ca5 mov v5.b\[0\], w5
+ 28: 4e011cc6 mov v6.b\[0\], w6
+ 2c: 4e011cc6 mov v6.b\[0\], w6
+ 30: 4e011ce7 mov v7.b\[0\], w7
+ 34: 4e011ce7 mov v7.b\[0\], w7
+ 38: 4e011d08 mov v8.b\[0\], w8
+ 3c: 4e011d08 mov v8.b\[0\], w8
+ 40: 4e011d29 mov v9.b\[0\], w9
+ 44: 4e011d29 mov v9.b\[0\], w9
+ 48: 4e011d4a mov v10.b\[0\], w10
+ 4c: 4e011d4a mov v10.b\[0\], w10
+ 50: 4e011d6b mov v11.b\[0\], w11
+ 54: 4e011d6b mov v11.b\[0\], w11
+ 58: 4e011d8c mov v12.b\[0\], w12
+ 5c: 4e011d8c mov v12.b\[0\], w12
+ 60: 4e011dad mov v13.b\[0\], w13
+ 64: 4e011dad mov v13.b\[0\], w13
+ 68: 4e011dce mov v14.b\[0\], w14
+ 6c: 4e011dce mov v14.b\[0\], w14
+ 70: 4e011def mov v15.b\[0\], w15
+ 74: 4e011def mov v15.b\[0\], w15
+ 78: 4e011e10 mov v16.b\[0\], w16
+ 7c: 4e011e10 mov v16.b\[0\], w16
+ 80: 4e011e31 mov v17.b\[0\], w17
+ 84: 4e011e31 mov v17.b\[0\], w17
+ 88: 4e011e52 mov v18.b\[0\], w18
+ 8c: 4e011e52 mov v18.b\[0\], w18
+ 90: 4e011e73 mov v19.b\[0\], w19
+ 94: 4e011e73 mov v19.b\[0\], w19
+ 98: 4e011e94 mov v20.b\[0\], w20
+ 9c: 4e011e94 mov v20.b\[0\], w20
+ a0: 4e011eb5 mov v21.b\[0\], w21
+ a4: 4e011eb5 mov v21.b\[0\], w21
+ a8: 4e011ed6 mov v22.b\[0\], w22
+ ac: 4e011ed6 mov v22.b\[0\], w22
+ b0: 4e011ef7 mov v23.b\[0\], w23
+ b4: 4e011ef7 mov v23.b\[0\], w23
+ b8: 4e011f18 mov v24.b\[0\], w24
+ bc: 4e011f18 mov v24.b\[0\], w24
+ c0: 4e011f39 mov v25.b\[0\], w25
+ c4: 4e011f39 mov v25.b\[0\], w25
+ c8: 4e011f5a mov v26.b\[0\], w26
+ cc: 4e011f5a mov v26.b\[0\], w26
+ d0: 4e011f7b mov v27.b\[0\], w27
+ d4: 4e011f7b mov v27.b\[0\], w27
+ d8: 4e011f9c mov v28.b\[0\], w28
+ dc: 4e011f9c mov v28.b\[0\], w28
+ e0: 4e011fbd mov v29.b\[0\], w29
+ e4: 4e011fbd mov v29.b\[0\], w29
+ e8: 4e011fde mov v30.b\[0\], w30
+ ec: 4e011fde mov v30.b\[0\], w30
+ f0: 4e031c21 mov v1.b\[1\], w1
+ f4: 4e031c21 mov v1.b\[1\], w1
+ f8: 4e031c42 mov v2.b\[1\], w2
+ fc: 4e031c42 mov v2.b\[1\], w2
+ 100: 4e031c63 mov v3.b\[1\], w3
+ 104: 4e031c63 mov v3.b\[1\], w3
+ 108: 4e031c84 mov v4.b\[1\], w4
+ 10c: 4e031c84 mov v4.b\[1\], w4
+ 110: 4e031ca5 mov v5.b\[1\], w5
+ 114: 4e031ca5 mov v5.b\[1\], w5
+ 118: 4e031cc6 mov v6.b\[1\], w6
+ 11c: 4e031cc6 mov v6.b\[1\], w6
+ 120: 4e031ce7 mov v7.b\[1\], w7
+ 124: 4e031ce7 mov v7.b\[1\], w7
+ 128: 4e031d08 mov v8.b\[1\], w8
+ 12c: 4e031d08 mov v8.b\[1\], w8
+ 130: 4e031d29 mov v9.b\[1\], w9
+ 134: 4e031d29 mov v9.b\[1\], w9
+ 138: 4e031d4a mov v10.b\[1\], w10
+ 13c: 4e031d4a mov v10.b\[1\], w10
+ 140: 4e031d6b mov v11.b\[1\], w11
+ 144: 4e031d6b mov v11.b\[1\], w11
+ 148: 4e031d8c mov v12.b\[1\], w12
+ 14c: 4e031d8c mov v12.b\[1\], w12
+ 150: 4e031dad mov v13.b\[1\], w13
+ 154: 4e031dad mov v13.b\[1\], w13
+ 158: 4e031dce mov v14.b\[1\], w14
+ 15c: 4e031dce mov v14.b\[1\], w14
+ 160: 4e031def mov v15.b\[1\], w15
+ 164: 4e031def mov v15.b\[1\], w15
+ 168: 4e031e10 mov v16.b\[1\], w16
+ 16c: 4e031e10 mov v16.b\[1\], w16
+ 170: 4e031e31 mov v17.b\[1\], w17
+ 174: 4e031e31 mov v17.b\[1\], w17
+ 178: 4e031e52 mov v18.b\[1\], w18
+ 17c: 4e031e52 mov v18.b\[1\], w18
+ 180: 4e031e73 mov v19.b\[1\], w19
+ 184: 4e031e73 mov v19.b\[1\], w19
+ 188: 4e031e94 mov v20.b\[1\], w20
+ 18c: 4e031e94 mov v20.b\[1\], w20
+ 190: 4e031eb5 mov v21.b\[1\], w21
+ 194: 4e031eb5 mov v21.b\[1\], w21
+ 198: 4e031ed6 mov v22.b\[1\], w22
+ 19c: 4e031ed6 mov v22.b\[1\], w22
+ 1a0: 4e031ef7 mov v23.b\[1\], w23
+ 1a4: 4e031ef7 mov v23.b\[1\], w23
+ 1a8: 4e031f18 mov v24.b\[1\], w24
+ 1ac: 4e031f18 mov v24.b\[1\], w24
+ 1b0: 4e031f39 mov v25.b\[1\], w25
+ 1b4: 4e031f39 mov v25.b\[1\], w25
+ 1b8: 4e031f5a mov v26.b\[1\], w26
+ 1bc: 4e031f5a mov v26.b\[1\], w26
+ 1c0: 4e031f7b mov v27.b\[1\], w27
+ 1c4: 4e031f7b mov v27.b\[1\], w27
+ 1c8: 4e031f9c mov v28.b\[1\], w28
+ 1cc: 4e031f9c mov v28.b\[1\], w28
+ 1d0: 4e031fbd mov v29.b\[1\], w29
+ 1d4: 4e031fbd mov v29.b\[1\], w29
+ 1d8: 4e031fde mov v30.b\[1\], w30
+ 1dc: 4e031fde mov v30.b\[1\], w30
+ 1e0: 4e051c21 mov v1.b\[2\], w1
+ 1e4: 4e051c21 mov v1.b\[2\], w1
+ 1e8: 4e051c42 mov v2.b\[2\], w2
+ 1ec: 4e051c42 mov v2.b\[2\], w2
+ 1f0: 4e051c63 mov v3.b\[2\], w3
+ 1f4: 4e051c63 mov v3.b\[2\], w3
+ 1f8: 4e051c84 mov v4.b\[2\], w4
+ 1fc: 4e051c84 mov v4.b\[2\], w4
+ 200: 4e051ca5 mov v5.b\[2\], w5
+ 204: 4e051ca5 mov v5.b\[2\], w5
+ 208: 4e051cc6 mov v6.b\[2\], w6
+ 20c: 4e051cc6 mov v6.b\[2\], w6
+ 210: 4e051ce7 mov v7.b\[2\], w7
+ 214: 4e051ce7 mov v7.b\[2\], w7
+ 218: 4e051d08 mov v8.b\[2\], w8
+ 21c: 4e051d08 mov v8.b\[2\], w8
+ 220: 4e051d29 mov v9.b\[2\], w9
+ 224: 4e051d29 mov v9.b\[2\], w9
+ 228: 4e051d4a mov v10.b\[2\], w10
+ 22c: 4e051d4a mov v10.b\[2\], w10
+ 230: 4e051d6b mov v11.b\[2\], w11
+ 234: 4e051d6b mov v11.b\[2\], w11
+ 238: 4e051d8c mov v12.b\[2\], w12
+ 23c: 4e051d8c mov v12.b\[2\], w12
+ 240: 4e051dad mov v13.b\[2\], w13
+ 244: 4e051dad mov v13.b\[2\], w13
+ 248: 4e051dce mov v14.b\[2\], w14
+ 24c: 4e051dce mov v14.b\[2\], w14
+ 250: 4e051def mov v15.b\[2\], w15
+ 254: 4e051def mov v15.b\[2\], w15
+ 258: 4e051e10 mov v16.b\[2\], w16
+ 25c: 4e051e10 mov v16.b\[2\], w16
+ 260: 4e051e31 mov v17.b\[2\], w17
+ 264: 4e051e31 mov v17.b\[2\], w17
+ 268: 4e051e52 mov v18.b\[2\], w18
+ 26c: 4e051e52 mov v18.b\[2\], w18
+ 270: 4e051e73 mov v19.b\[2\], w19
+ 274: 4e051e73 mov v19.b\[2\], w19
+ 278: 4e051e94 mov v20.b\[2\], w20
+ 27c: 4e051e94 mov v20.b\[2\], w20
+ 280: 4e051eb5 mov v21.b\[2\], w21
+ 284: 4e051eb5 mov v21.b\[2\], w21
+ 288: 4e051ed6 mov v22.b\[2\], w22
+ 28c: 4e051ed6 mov v22.b\[2\], w22
+ 290: 4e051ef7 mov v23.b\[2\], w23
+ 294: 4e051ef7 mov v23.b\[2\], w23
+ 298: 4e051f18 mov v24.b\[2\], w24
+ 29c: 4e051f18 mov v24.b\[2\], w24
+ 2a0: 4e051f39 mov v25.b\[2\], w25
+ 2a4: 4e051f39 mov v25.b\[2\], w25
+ 2a8: 4e051f5a mov v26.b\[2\], w26
+ 2ac: 4e051f5a mov v26.b\[2\], w26
+ 2b0: 4e051f7b mov v27.b\[2\], w27
+ 2b4: 4e051f7b mov v27.b\[2\], w27
+ 2b8: 4e051f9c mov v28.b\[2\], w28
+ 2bc: 4e051f9c mov v28.b\[2\], w28
+ 2c0: 4e051fbd mov v29.b\[2\], w29
+ 2c4: 4e051fbd mov v29.b\[2\], w29
+ 2c8: 4e051fde mov v30.b\[2\], w30
+ 2cc: 4e051fde mov v30.b\[2\], w30
+ 2d0: 4e071c21 mov v1.b\[3\], w1
+ 2d4: 4e071c21 mov v1.b\[3\], w1
+ 2d8: 4e071c42 mov v2.b\[3\], w2
+ 2dc: 4e071c42 mov v2.b\[3\], w2
+ 2e0: 4e071c63 mov v3.b\[3\], w3
+ 2e4: 4e071c63 mov v3.b\[3\], w3
+ 2e8: 4e071c84 mov v4.b\[3\], w4
+ 2ec: 4e071c84 mov v4.b\[3\], w4
+ 2f0: 4e071ca5 mov v5.b\[3\], w5
+ 2f4: 4e071ca5 mov v5.b\[3\], w5
+ 2f8: 4e071cc6 mov v6.b\[3\], w6
+ 2fc: 4e071cc6 mov v6.b\[3\], w6
+ 300: 4e071ce7 mov v7.b\[3\], w7
+ 304: 4e071ce7 mov v7.b\[3\], w7
+ 308: 4e071d08 mov v8.b\[3\], w8
+ 30c: 4e071d08 mov v8.b\[3\], w8
+ 310: 4e071d29 mov v9.b\[3\], w9
+ 314: 4e071d29 mov v9.b\[3\], w9
+ 318: 4e071d4a mov v10.b\[3\], w10
+ 31c: 4e071d4a mov v10.b\[3\], w10
+ 320: 4e071d6b mov v11.b\[3\], w11
+ 324: 4e071d6b mov v11.b\[3\], w11
+ 328: 4e071d8c mov v12.b\[3\], w12
+ 32c: 4e071d8c mov v12.b\[3\], w12
+ 330: 4e071dad mov v13.b\[3\], w13
+ 334: 4e071dad mov v13.b\[3\], w13
+ 338: 4e071dce mov v14.b\[3\], w14
+ 33c: 4e071dce mov v14.b\[3\], w14
+ 340: 4e071def mov v15.b\[3\], w15
+ 344: 4e071def mov v15.b\[3\], w15
+ 348: 4e071e10 mov v16.b\[3\], w16
+ 34c: 4e071e10 mov v16.b\[3\], w16
+ 350: 4e071e31 mov v17.b\[3\], w17
+ 354: 4e071e31 mov v17.b\[3\], w17
+ 358: 4e071e52 mov v18.b\[3\], w18
+ 35c: 4e071e52 mov v18.b\[3\], w18
+ 360: 4e071e73 mov v19.b\[3\], w19
+ 364: 4e071e73 mov v19.b\[3\], w19
+ 368: 4e071e94 mov v20.b\[3\], w20
+ 36c: 4e071e94 mov v20.b\[3\], w20
+ 370: 4e071eb5 mov v21.b\[3\], w21
+ 374: 4e071eb5 mov v21.b\[3\], w21
+ 378: 4e071ed6 mov v22.b\[3\], w22
+ 37c: 4e071ed6 mov v22.b\[3\], w22
+ 380: 4e071ef7 mov v23.b\[3\], w23
+ 384: 4e071ef7 mov v23.b\[3\], w23
+ 388: 4e071f18 mov v24.b\[3\], w24
+ 38c: 4e071f18 mov v24.b\[3\], w24
+ 390: 4e071f39 mov v25.b\[3\], w25
+ 394: 4e071f39 mov v25.b\[3\], w25
+ 398: 4e071f5a mov v26.b\[3\], w26
+ 39c: 4e071f5a mov v26.b\[3\], w26
+ 3a0: 4e071f7b mov v27.b\[3\], w27
+ 3a4: 4e071f7b mov v27.b\[3\], w27
+ 3a8: 4e071f9c mov v28.b\[3\], w28
+ 3ac: 4e071f9c mov v28.b\[3\], w28
+ 3b0: 4e071fbd mov v29.b\[3\], w29
+ 3b4: 4e071fbd mov v29.b\[3\], w29
+ 3b8: 4e071fde mov v30.b\[3\], w30
+ 3bc: 4e071fde mov v30.b\[3\], w30
+ 3c0: 4e091c21 mov v1.b\[4\], w1
+ 3c4: 4e091c21 mov v1.b\[4\], w1
+ 3c8: 4e091c42 mov v2.b\[4\], w2
+ 3cc: 4e091c42 mov v2.b\[4\], w2
+ 3d0: 4e091c63 mov v3.b\[4\], w3
+ 3d4: 4e091c63 mov v3.b\[4\], w3
+ 3d8: 4e091c84 mov v4.b\[4\], w4
+ 3dc: 4e091c84 mov v4.b\[4\], w4
+ 3e0: 4e091ca5 mov v5.b\[4\], w5
+ 3e4: 4e091ca5 mov v5.b\[4\], w5
+ 3e8: 4e091cc6 mov v6.b\[4\], w6
+ 3ec: 4e091cc6 mov v6.b\[4\], w6
+ 3f0: 4e091ce7 mov v7.b\[4\], w7
+ 3f4: 4e091ce7 mov v7.b\[4\], w7
+ 3f8: 4e091d08 mov v8.b\[4\], w8
+ 3fc: 4e091d08 mov v8.b\[4\], w8
+ 400: 4e091d29 mov v9.b\[4\], w9
+ 404: 4e091d29 mov v9.b\[4\], w9
+ 408: 4e091d4a mov v10.b\[4\], w10
+ 40c: 4e091d4a mov v10.b\[4\], w10
+ 410: 4e091d6b mov v11.b\[4\], w11
+ 414: 4e091d6b mov v11.b\[4\], w11
+ 418: 4e091d8c mov v12.b\[4\], w12
+ 41c: 4e091d8c mov v12.b\[4\], w12
+ 420: 4e091dad mov v13.b\[4\], w13
+ 424: 4e091dad mov v13.b\[4\], w13
+ 428: 4e091dce mov v14.b\[4\], w14
+ 42c: 4e091dce mov v14.b\[4\], w14
+ 430: 4e091def mov v15.b\[4\], w15
+ 434: 4e091def mov v15.b\[4\], w15
+ 438: 4e091e10 mov v16.b\[4\], w16
+ 43c: 4e091e10 mov v16.b\[4\], w16
+ 440: 4e091e31 mov v17.b\[4\], w17
+ 444: 4e091e31 mov v17.b\[4\], w17
+ 448: 4e091e52 mov v18.b\[4\], w18
+ 44c: 4e091e52 mov v18.b\[4\], w18
+ 450: 4e091e73 mov v19.b\[4\], w19
+ 454: 4e091e73 mov v19.b\[4\], w19
+ 458: 4e091e94 mov v20.b\[4\], w20
+ 45c: 4e091e94 mov v20.b\[4\], w20
+ 460: 4e091eb5 mov v21.b\[4\], w21
+ 464: 4e091eb5 mov v21.b\[4\], w21
+ 468: 4e091ed6 mov v22.b\[4\], w22
+ 46c: 4e091ed6 mov v22.b\[4\], w22
+ 470: 4e091ef7 mov v23.b\[4\], w23
+ 474: 4e091ef7 mov v23.b\[4\], w23
+ 478: 4e091f18 mov v24.b\[4\], w24
+ 47c: 4e091f18 mov v24.b\[4\], w24
+ 480: 4e091f39 mov v25.b\[4\], w25
+ 484: 4e091f39 mov v25.b\[4\], w25
+ 488: 4e091f5a mov v26.b\[4\], w26
+ 48c: 4e091f5a mov v26.b\[4\], w26
+ 490: 4e091f7b mov v27.b\[4\], w27
+ 494: 4e091f7b mov v27.b\[4\], w27
+ 498: 4e091f9c mov v28.b\[4\], w28
+ 49c: 4e091f9c mov v28.b\[4\], w28
+ 4a0: 4e091fbd mov v29.b\[4\], w29
+ 4a4: 4e091fbd mov v29.b\[4\], w29
+ 4a8: 4e091fde mov v30.b\[4\], w30
+ 4ac: 4e091fde mov v30.b\[4\], w30
+ 4b0: 4e0b1c21 mov v1.b\[5\], w1
+ 4b4: 4e0b1c21 mov v1.b\[5\], w1
+ 4b8: 4e0b1c42 mov v2.b\[5\], w2
+ 4bc: 4e0b1c42 mov v2.b\[5\], w2
+ 4c0: 4e0b1c63 mov v3.b\[5\], w3
+ 4c4: 4e0b1c63 mov v3.b\[5\], w3
+ 4c8: 4e0b1c84 mov v4.b\[5\], w4
+ 4cc: 4e0b1c84 mov v4.b\[5\], w4
+ 4d0: 4e0b1ca5 mov v5.b\[5\], w5
+ 4d4: 4e0b1ca5 mov v5.b\[5\], w5
+ 4d8: 4e0b1cc6 mov v6.b\[5\], w6
+ 4dc: 4e0b1cc6 mov v6.b\[5\], w6
+ 4e0: 4e0b1ce7 mov v7.b\[5\], w7
+ 4e4: 4e0b1ce7 mov v7.b\[5\], w7
+ 4e8: 4e0b1d08 mov v8.b\[5\], w8
+ 4ec: 4e0b1d08 mov v8.b\[5\], w8
+ 4f0: 4e0b1d29 mov v9.b\[5\], w9
+ 4f4: 4e0b1d29 mov v9.b\[5\], w9
+ 4f8: 4e0b1d4a mov v10.b\[5\], w10
+ 4fc: 4e0b1d4a mov v10.b\[5\], w10
+ 500: 4e0b1d6b mov v11.b\[5\], w11
+ 504: 4e0b1d6b mov v11.b\[5\], w11
+ 508: 4e0b1d8c mov v12.b\[5\], w12
+ 50c: 4e0b1d8c mov v12.b\[5\], w12
+ 510: 4e0b1dad mov v13.b\[5\], w13
+ 514: 4e0b1dad mov v13.b\[5\], w13
+ 518: 4e0b1dce mov v14.b\[5\], w14
+ 51c: 4e0b1dce mov v14.b\[5\], w14
+ 520: 4e0b1def mov v15.b\[5\], w15
+ 524: 4e0b1def mov v15.b\[5\], w15
+ 528: 4e0b1e10 mov v16.b\[5\], w16
+ 52c: 4e0b1e10 mov v16.b\[5\], w16
+ 530: 4e0b1e31 mov v17.b\[5\], w17
+ 534: 4e0b1e31 mov v17.b\[5\], w17
+ 538: 4e0b1e52 mov v18.b\[5\], w18
+ 53c: 4e0b1e52 mov v18.b\[5\], w18
+ 540: 4e0b1e73 mov v19.b\[5\], w19
+ 544: 4e0b1e73 mov v19.b\[5\], w19
+ 548: 4e0b1e94 mov v20.b\[5\], w20
+ 54c: 4e0b1e94 mov v20.b\[5\], w20
+ 550: 4e0b1eb5 mov v21.b\[5\], w21
+ 554: 4e0b1eb5 mov v21.b\[5\], w21
+ 558: 4e0b1ed6 mov v22.b\[5\], w22
+ 55c: 4e0b1ed6 mov v22.b\[5\], w22
+ 560: 4e0b1ef7 mov v23.b\[5\], w23
+ 564: 4e0b1ef7 mov v23.b\[5\], w23
+ 568: 4e0b1f18 mov v24.b\[5\], w24
+ 56c: 4e0b1f18 mov v24.b\[5\], w24
+ 570: 4e0b1f39 mov v25.b\[5\], w25
+ 574: 4e0b1f39 mov v25.b\[5\], w25
+ 578: 4e0b1f5a mov v26.b\[5\], w26
+ 57c: 4e0b1f5a mov v26.b\[5\], w26
+ 580: 4e0b1f7b mov v27.b\[5\], w27
+ 584: 4e0b1f7b mov v27.b\[5\], w27
+ 588: 4e0b1f9c mov v28.b\[5\], w28
+ 58c: 4e0b1f9c mov v28.b\[5\], w28
+ 590: 4e0b1fbd mov v29.b\[5\], w29
+ 594: 4e0b1fbd mov v29.b\[5\], w29
+ 598: 4e0b1fde mov v30.b\[5\], w30
+ 59c: 4e0b1fde mov v30.b\[5\], w30
+ 5a0: 4e0d1c21 mov v1.b\[6\], w1
+ 5a4: 4e0d1c21 mov v1.b\[6\], w1
+ 5a8: 4e0d1c42 mov v2.b\[6\], w2
+ 5ac: 4e0d1c42 mov v2.b\[6\], w2
+ 5b0: 4e0d1c63 mov v3.b\[6\], w3
+ 5b4: 4e0d1c63 mov v3.b\[6\], w3
+ 5b8: 4e0d1c84 mov v4.b\[6\], w4
+ 5bc: 4e0d1c84 mov v4.b\[6\], w4
+ 5c0: 4e0d1ca5 mov v5.b\[6\], w5
+ 5c4: 4e0d1ca5 mov v5.b\[6\], w5
+ 5c8: 4e0d1cc6 mov v6.b\[6\], w6
+ 5cc: 4e0d1cc6 mov v6.b\[6\], w6
+ 5d0: 4e0d1ce7 mov v7.b\[6\], w7
+ 5d4: 4e0d1ce7 mov v7.b\[6\], w7
+ 5d8: 4e0d1d08 mov v8.b\[6\], w8
+ 5dc: 4e0d1d08 mov v8.b\[6\], w8
+ 5e0: 4e0d1d29 mov v9.b\[6\], w9
+ 5e4: 4e0d1d29 mov v9.b\[6\], w9
+ 5e8: 4e0d1d4a mov v10.b\[6\], w10
+ 5ec: 4e0d1d4a mov v10.b\[6\], w10
+ 5f0: 4e0d1d6b mov v11.b\[6\], w11
+ 5f4: 4e0d1d6b mov v11.b\[6\], w11
+ 5f8: 4e0d1d8c mov v12.b\[6\], w12
+ 5fc: 4e0d1d8c mov v12.b\[6\], w12
+ 600: 4e0d1dad mov v13.b\[6\], w13
+ 604: 4e0d1dad mov v13.b\[6\], w13
+ 608: 4e0d1dce mov v14.b\[6\], w14
+ 60c: 4e0d1dce mov v14.b\[6\], w14
+ 610: 4e0d1def mov v15.b\[6\], w15
+ 614: 4e0d1def mov v15.b\[6\], w15
+ 618: 4e0d1e10 mov v16.b\[6\], w16
+ 61c: 4e0d1e10 mov v16.b\[6\], w16
+ 620: 4e0d1e31 mov v17.b\[6\], w17
+ 624: 4e0d1e31 mov v17.b\[6\], w17
+ 628: 4e0d1e52 mov v18.b\[6\], w18
+ 62c: 4e0d1e52 mov v18.b\[6\], w18
+ 630: 4e0d1e73 mov v19.b\[6\], w19
+ 634: 4e0d1e73 mov v19.b\[6\], w19
+ 638: 4e0d1e94 mov v20.b\[6\], w20
+ 63c: 4e0d1e94 mov v20.b\[6\], w20
+ 640: 4e0d1eb5 mov v21.b\[6\], w21
+ 644: 4e0d1eb5 mov v21.b\[6\], w21
+ 648: 4e0d1ed6 mov v22.b\[6\], w22
+ 64c: 4e0d1ed6 mov v22.b\[6\], w22
+ 650: 4e0d1ef7 mov v23.b\[6\], w23
+ 654: 4e0d1ef7 mov v23.b\[6\], w23
+ 658: 4e0d1f18 mov v24.b\[6\], w24
+ 65c: 4e0d1f18 mov v24.b\[6\], w24
+ 660: 4e0d1f39 mov v25.b\[6\], w25
+ 664: 4e0d1f39 mov v25.b\[6\], w25
+ 668: 4e0d1f5a mov v26.b\[6\], w26
+ 66c: 4e0d1f5a mov v26.b\[6\], w26
+ 670: 4e0d1f7b mov v27.b\[6\], w27
+ 674: 4e0d1f7b mov v27.b\[6\], w27
+ 678: 4e0d1f9c mov v28.b\[6\], w28
+ 67c: 4e0d1f9c mov v28.b\[6\], w28
+ 680: 4e0d1fbd mov v29.b\[6\], w29
+ 684: 4e0d1fbd mov v29.b\[6\], w29
+ 688: 4e0d1fde mov v30.b\[6\], w30
+ 68c: 4e0d1fde mov v30.b\[6\], w30
+ 690: 4e0f1c21 mov v1.b\[7\], w1
+ 694: 4e0f1c21 mov v1.b\[7\], w1
+ 698: 4e0f1c42 mov v2.b\[7\], w2
+ 69c: 4e0f1c42 mov v2.b\[7\], w2
+ 6a0: 4e0f1c63 mov v3.b\[7\], w3
+ 6a4: 4e0f1c63 mov v3.b\[7\], w3
+ 6a8: 4e0f1c84 mov v4.b\[7\], w4
+ 6ac: 4e0f1c84 mov v4.b\[7\], w4
+ 6b0: 4e0f1ca5 mov v5.b\[7\], w5
+ 6b4: 4e0f1ca5 mov v5.b\[7\], w5
+ 6b8: 4e0f1cc6 mov v6.b\[7\], w6
+ 6bc: 4e0f1cc6 mov v6.b\[7\], w6
+ 6c0: 4e0f1ce7 mov v7.b\[7\], w7
+ 6c4: 4e0f1ce7 mov v7.b\[7\], w7
+ 6c8: 4e0f1d08 mov v8.b\[7\], w8
+ 6cc: 4e0f1d08 mov v8.b\[7\], w8
+ 6d0: 4e0f1d29 mov v9.b\[7\], w9
+ 6d4: 4e0f1d29 mov v9.b\[7\], w9
+ 6d8: 4e0f1d4a mov v10.b\[7\], w10
+ 6dc: 4e0f1d4a mov v10.b\[7\], w10
+ 6e0: 4e0f1d6b mov v11.b\[7\], w11
+ 6e4: 4e0f1d6b mov v11.b\[7\], w11
+ 6e8: 4e0f1d8c mov v12.b\[7\], w12
+ 6ec: 4e0f1d8c mov v12.b\[7\], w12
+ 6f0: 4e0f1dad mov v13.b\[7\], w13
+ 6f4: 4e0f1dad mov v13.b\[7\], w13
+ 6f8: 4e0f1dce mov v14.b\[7\], w14
+ 6fc: 4e0f1dce mov v14.b\[7\], w14
+ 700: 4e0f1def mov v15.b\[7\], w15
+ 704: 4e0f1def mov v15.b\[7\], w15
+ 708: 4e0f1e10 mov v16.b\[7\], w16
+ 70c: 4e0f1e10 mov v16.b\[7\], w16
+ 710: 4e0f1e31 mov v17.b\[7\], w17
+ 714: 4e0f1e31 mov v17.b\[7\], w17
+ 718: 4e0f1e52 mov v18.b\[7\], w18
+ 71c: 4e0f1e52 mov v18.b\[7\], w18
+ 720: 4e0f1e73 mov v19.b\[7\], w19
+ 724: 4e0f1e73 mov v19.b\[7\], w19
+ 728: 4e0f1e94 mov v20.b\[7\], w20
+ 72c: 4e0f1e94 mov v20.b\[7\], w20
+ 730: 4e0f1eb5 mov v21.b\[7\], w21
+ 734: 4e0f1eb5 mov v21.b\[7\], w21
+ 738: 4e0f1ed6 mov v22.b\[7\], w22
+ 73c: 4e0f1ed6 mov v22.b\[7\], w22
+ 740: 4e0f1ef7 mov v23.b\[7\], w23
+ 744: 4e0f1ef7 mov v23.b\[7\], w23
+ 748: 4e0f1f18 mov v24.b\[7\], w24
+ 74c: 4e0f1f18 mov v24.b\[7\], w24
+ 750: 4e0f1f39 mov v25.b\[7\], w25
+ 754: 4e0f1f39 mov v25.b\[7\], w25
+ 758: 4e0f1f5a mov v26.b\[7\], w26
+ 75c: 4e0f1f5a mov v26.b\[7\], w26
+ 760: 4e0f1f7b mov v27.b\[7\], w27
+ 764: 4e0f1f7b mov v27.b\[7\], w27
+ 768: 4e0f1f9c mov v28.b\[7\], w28
+ 76c: 4e0f1f9c mov v28.b\[7\], w28
+ 770: 4e0f1fbd mov v29.b\[7\], w29
+ 774: 4e0f1fbd mov v29.b\[7\], w29
+ 778: 4e0f1fde mov v30.b\[7\], w30
+ 77c: 4e0f1fde mov v30.b\[7\], w30
+ 780: 4e111c21 mov v1.b\[8\], w1
+ 784: 4e111c21 mov v1.b\[8\], w1
+ 788: 4e111c42 mov v2.b\[8\], w2
+ 78c: 4e111c42 mov v2.b\[8\], w2
+ 790: 4e111c63 mov v3.b\[8\], w3
+ 794: 4e111c63 mov v3.b\[8\], w3
+ 798: 4e111c84 mov v4.b\[8\], w4
+ 79c: 4e111c84 mov v4.b\[8\], w4
+ 7a0: 4e111ca5 mov v5.b\[8\], w5
+ 7a4: 4e111ca5 mov v5.b\[8\], w5
+ 7a8: 4e111cc6 mov v6.b\[8\], w6
+ 7ac: 4e111cc6 mov v6.b\[8\], w6
+ 7b0: 4e111ce7 mov v7.b\[8\], w7
+ 7b4: 4e111ce7 mov v7.b\[8\], w7
+ 7b8: 4e111d08 mov v8.b\[8\], w8
+ 7bc: 4e111d08 mov v8.b\[8\], w8
+ 7c0: 4e111d29 mov v9.b\[8\], w9
+ 7c4: 4e111d29 mov v9.b\[8\], w9
+ 7c8: 4e111d4a mov v10.b\[8\], w10
+ 7cc: 4e111d4a mov v10.b\[8\], w10
+ 7d0: 4e111d6b mov v11.b\[8\], w11
+ 7d4: 4e111d6b mov v11.b\[8\], w11
+ 7d8: 4e111d8c mov v12.b\[8\], w12
+ 7dc: 4e111d8c mov v12.b\[8\], w12
+ 7e0: 4e111dad mov v13.b\[8\], w13
+ 7e4: 4e111dad mov v13.b\[8\], w13
+ 7e8: 4e111dce mov v14.b\[8\], w14
+ 7ec: 4e111dce mov v14.b\[8\], w14
+ 7f0: 4e111def mov v15.b\[8\], w15
+ 7f4: 4e111def mov v15.b\[8\], w15
+ 7f8: 4e111e10 mov v16.b\[8\], w16
+ 7fc: 4e111e10 mov v16.b\[8\], w16
+ 800: 4e111e31 mov v17.b\[8\], w17
+ 804: 4e111e31 mov v17.b\[8\], w17
+ 808: 4e111e52 mov v18.b\[8\], w18
+ 80c: 4e111e52 mov v18.b\[8\], w18
+ 810: 4e111e73 mov v19.b\[8\], w19
+ 814: 4e111e73 mov v19.b\[8\], w19
+ 818: 4e111e94 mov v20.b\[8\], w20
+ 81c: 4e111e94 mov v20.b\[8\], w20
+ 820: 4e111eb5 mov v21.b\[8\], w21
+ 824: 4e111eb5 mov v21.b\[8\], w21
+ 828: 4e111ed6 mov v22.b\[8\], w22
+ 82c: 4e111ed6 mov v22.b\[8\], w22
+ 830: 4e111ef7 mov v23.b\[8\], w23
+ 834: 4e111ef7 mov v23.b\[8\], w23
+ 838: 4e111f18 mov v24.b\[8\], w24
+ 83c: 4e111f18 mov v24.b\[8\], w24
+ 840: 4e111f39 mov v25.b\[8\], w25
+ 844: 4e111f39 mov v25.b\[8\], w25
+ 848: 4e111f5a mov v26.b\[8\], w26
+ 84c: 4e111f5a mov v26.b\[8\], w26
+ 850: 4e111f7b mov v27.b\[8\], w27
+ 854: 4e111f7b mov v27.b\[8\], w27
+ 858: 4e111f9c mov v28.b\[8\], w28
+ 85c: 4e111f9c mov v28.b\[8\], w28
+ 860: 4e111fbd mov v29.b\[8\], w29
+ 864: 4e111fbd mov v29.b\[8\], w29
+ 868: 4e111fde mov v30.b\[8\], w30
+ 86c: 4e111fde mov v30.b\[8\], w30
+ 870: 4e131c21 mov v1.b\[9\], w1
+ 874: 4e131c21 mov v1.b\[9\], w1
+ 878: 4e131c42 mov v2.b\[9\], w2
+ 87c: 4e131c42 mov v2.b\[9\], w2
+ 880: 4e131c63 mov v3.b\[9\], w3
+ 884: 4e131c63 mov v3.b\[9\], w3
+ 888: 4e131c84 mov v4.b\[9\], w4
+ 88c: 4e131c84 mov v4.b\[9\], w4
+ 890: 4e131ca5 mov v5.b\[9\], w5
+ 894: 4e131ca5 mov v5.b\[9\], w5
+ 898: 4e131cc6 mov v6.b\[9\], w6
+ 89c: 4e131cc6 mov v6.b\[9\], w6
+ 8a0: 4e131ce7 mov v7.b\[9\], w7
+ 8a4: 4e131ce7 mov v7.b\[9\], w7
+ 8a8: 4e131d08 mov v8.b\[9\], w8
+ 8ac: 4e131d08 mov v8.b\[9\], w8
+ 8b0: 4e131d29 mov v9.b\[9\], w9
+ 8b4: 4e131d29 mov v9.b\[9\], w9
+ 8b8: 4e131d4a mov v10.b\[9\], w10
+ 8bc: 4e131d4a mov v10.b\[9\], w10
+ 8c0: 4e131d6b mov v11.b\[9\], w11
+ 8c4: 4e131d6b mov v11.b\[9\], w11
+ 8c8: 4e131d8c mov v12.b\[9\], w12
+ 8cc: 4e131d8c mov v12.b\[9\], w12
+ 8d0: 4e131dad mov v13.b\[9\], w13
+ 8d4: 4e131dad mov v13.b\[9\], w13
+ 8d8: 4e131dce mov v14.b\[9\], w14
+ 8dc: 4e131dce mov v14.b\[9\], w14
+ 8e0: 4e131def mov v15.b\[9\], w15
+ 8e4: 4e131def mov v15.b\[9\], w15
+ 8e8: 4e131e10 mov v16.b\[9\], w16
+ 8ec: 4e131e10 mov v16.b\[9\], w16
+ 8f0: 4e131e31 mov v17.b\[9\], w17
+ 8f4: 4e131e31 mov v17.b\[9\], w17
+ 8f8: 4e131e52 mov v18.b\[9\], w18
+ 8fc: 4e131e52 mov v18.b\[9\], w18
+ 900: 4e131e73 mov v19.b\[9\], w19
+ 904: 4e131e73 mov v19.b\[9\], w19
+ 908: 4e131e94 mov v20.b\[9\], w20
+ 90c: 4e131e94 mov v20.b\[9\], w20
+ 910: 4e131eb5 mov v21.b\[9\], w21
+ 914: 4e131eb5 mov v21.b\[9\], w21
+ 918: 4e131ed6 mov v22.b\[9\], w22
+ 91c: 4e131ed6 mov v22.b\[9\], w22
+ 920: 4e131ef7 mov v23.b\[9\], w23
+ 924: 4e131ef7 mov v23.b\[9\], w23
+ 928: 4e131f18 mov v24.b\[9\], w24
+ 92c: 4e131f18 mov v24.b\[9\], w24
+ 930: 4e131f39 mov v25.b\[9\], w25
+ 934: 4e131f39 mov v25.b\[9\], w25
+ 938: 4e131f5a mov v26.b\[9\], w26
+ 93c: 4e131f5a mov v26.b\[9\], w26
+ 940: 4e131f7b mov v27.b\[9\], w27
+ 944: 4e131f7b mov v27.b\[9\], w27
+ 948: 4e131f9c mov v28.b\[9\], w28
+ 94c: 4e131f9c mov v28.b\[9\], w28
+ 950: 4e131fbd mov v29.b\[9\], w29
+ 954: 4e131fbd mov v29.b\[9\], w29
+ 958: 4e131fde mov v30.b\[9\], w30
+ 95c: 4e131fde mov v30.b\[9\], w30
+ 960: 4e151c21 mov v1.b\[10\], w1
+ 964: 4e151c21 mov v1.b\[10\], w1
+ 968: 4e151c42 mov v2.b\[10\], w2
+ 96c: 4e151c42 mov v2.b\[10\], w2
+ 970: 4e151c63 mov v3.b\[10\], w3
+ 974: 4e151c63 mov v3.b\[10\], w3
+ 978: 4e151c84 mov v4.b\[10\], w4
+ 97c: 4e151c84 mov v4.b\[10\], w4
+ 980: 4e151ca5 mov v5.b\[10\], w5
+ 984: 4e151ca5 mov v5.b\[10\], w5
+ 988: 4e151cc6 mov v6.b\[10\], w6
+ 98c: 4e151cc6 mov v6.b\[10\], w6
+ 990: 4e151ce7 mov v7.b\[10\], w7
+ 994: 4e151ce7 mov v7.b\[10\], w7
+ 998: 4e151d08 mov v8.b\[10\], w8
+ 99c: 4e151d08 mov v8.b\[10\], w8
+ 9a0: 4e151d29 mov v9.b\[10\], w9
+ 9a4: 4e151d29 mov v9.b\[10\], w9
+ 9a8: 4e151d4a mov v10.b\[10\], w10
+ 9ac: 4e151d4a mov v10.b\[10\], w10
+ 9b0: 4e151d6b mov v11.b\[10\], w11
+ 9b4: 4e151d6b mov v11.b\[10\], w11
+ 9b8: 4e151d8c mov v12.b\[10\], w12
+ 9bc: 4e151d8c mov v12.b\[10\], w12
+ 9c0: 4e151dad mov v13.b\[10\], w13
+ 9c4: 4e151dad mov v13.b\[10\], w13
+ 9c8: 4e151dce mov v14.b\[10\], w14
+ 9cc: 4e151dce mov v14.b\[10\], w14
+ 9d0: 4e151def mov v15.b\[10\], w15
+ 9d4: 4e151def mov v15.b\[10\], w15
+ 9d8: 4e151e10 mov v16.b\[10\], w16
+ 9dc: 4e151e10 mov v16.b\[10\], w16
+ 9e0: 4e151e31 mov v17.b\[10\], w17
+ 9e4: 4e151e31 mov v17.b\[10\], w17
+ 9e8: 4e151e52 mov v18.b\[10\], w18
+ 9ec: 4e151e52 mov v18.b\[10\], w18
+ 9f0: 4e151e73 mov v19.b\[10\], w19
+ 9f4: 4e151e73 mov v19.b\[10\], w19
+ 9f8: 4e151e94 mov v20.b\[10\], w20
+ 9fc: 4e151e94 mov v20.b\[10\], w20
+ a00: 4e151eb5 mov v21.b\[10\], w21
+ a04: 4e151eb5 mov v21.b\[10\], w21
+ a08: 4e151ed6 mov v22.b\[10\], w22
+ a0c: 4e151ed6 mov v22.b\[10\], w22
+ a10: 4e151ef7 mov v23.b\[10\], w23
+ a14: 4e151ef7 mov v23.b\[10\], w23
+ a18: 4e151f18 mov v24.b\[10\], w24
+ a1c: 4e151f18 mov v24.b\[10\], w24
+ a20: 4e151f39 mov v25.b\[10\], w25
+ a24: 4e151f39 mov v25.b\[10\], w25
+ a28: 4e151f5a mov v26.b\[10\], w26
+ a2c: 4e151f5a mov v26.b\[10\], w26
+ a30: 4e151f7b mov v27.b\[10\], w27
+ a34: 4e151f7b mov v27.b\[10\], w27
+ a38: 4e151f9c mov v28.b\[10\], w28
+ a3c: 4e151f9c mov v28.b\[10\], w28
+ a40: 4e151fbd mov v29.b\[10\], w29
+ a44: 4e151fbd mov v29.b\[10\], w29
+ a48: 4e151fde mov v30.b\[10\], w30
+ a4c: 4e151fde mov v30.b\[10\], w30
+ a50: 4e171c21 mov v1.b\[11\], w1
+ a54: 4e171c21 mov v1.b\[11\], w1
+ a58: 4e171c42 mov v2.b\[11\], w2
+ a5c: 4e171c42 mov v2.b\[11\], w2
+ a60: 4e171c63 mov v3.b\[11\], w3
+ a64: 4e171c63 mov v3.b\[11\], w3
+ a68: 4e171c84 mov v4.b\[11\], w4
+ a6c: 4e171c84 mov v4.b\[11\], w4
+ a70: 4e171ca5 mov v5.b\[11\], w5
+ a74: 4e171ca5 mov v5.b\[11\], w5
+ a78: 4e171cc6 mov v6.b\[11\], w6
+ a7c: 4e171cc6 mov v6.b\[11\], w6
+ a80: 4e171ce7 mov v7.b\[11\], w7
+ a84: 4e171ce7 mov v7.b\[11\], w7
+ a88: 4e171d08 mov v8.b\[11\], w8
+ a8c: 4e171d08 mov v8.b\[11\], w8
+ a90: 4e171d29 mov v9.b\[11\], w9
+ a94: 4e171d29 mov v9.b\[11\], w9
+ a98: 4e171d4a mov v10.b\[11\], w10
+ a9c: 4e171d4a mov v10.b\[11\], w10
+ aa0: 4e171d6b mov v11.b\[11\], w11
+ aa4: 4e171d6b mov v11.b\[11\], w11
+ aa8: 4e171d8c mov v12.b\[11\], w12
+ aac: 4e171d8c mov v12.b\[11\], w12
+ ab0: 4e171dad mov v13.b\[11\], w13
+ ab4: 4e171dad mov v13.b\[11\], w13
+ ab8: 4e171dce mov v14.b\[11\], w14
+ abc: 4e171dce mov v14.b\[11\], w14
+ ac0: 4e171def mov v15.b\[11\], w15
+ ac4: 4e171def mov v15.b\[11\], w15
+ ac8: 4e171e10 mov v16.b\[11\], w16
+ acc: 4e171e10 mov v16.b\[11\], w16
+ ad0: 4e171e31 mov v17.b\[11\], w17
+ ad4: 4e171e31 mov v17.b\[11\], w17
+ ad8: 4e171e52 mov v18.b\[11\], w18
+ adc: 4e171e52 mov v18.b\[11\], w18
+ ae0: 4e171e73 mov v19.b\[11\], w19
+ ae4: 4e171e73 mov v19.b\[11\], w19
+ ae8: 4e171e94 mov v20.b\[11\], w20
+ aec: 4e171e94 mov v20.b\[11\], w20
+ af0: 4e171eb5 mov v21.b\[11\], w21
+ af4: 4e171eb5 mov v21.b\[11\], w21
+ af8: 4e171ed6 mov v22.b\[11\], w22
+ afc: 4e171ed6 mov v22.b\[11\], w22
+ b00: 4e171ef7 mov v23.b\[11\], w23
+ b04: 4e171ef7 mov v23.b\[11\], w23
+ b08: 4e171f18 mov v24.b\[11\], w24
+ b0c: 4e171f18 mov v24.b\[11\], w24
+ b10: 4e171f39 mov v25.b\[11\], w25
+ b14: 4e171f39 mov v25.b\[11\], w25
+ b18: 4e171f5a mov v26.b\[11\], w26
+ b1c: 4e171f5a mov v26.b\[11\], w26
+ b20: 4e171f7b mov v27.b\[11\], w27
+ b24: 4e171f7b mov v27.b\[11\], w27
+ b28: 4e171f9c mov v28.b\[11\], w28
+ b2c: 4e171f9c mov v28.b\[11\], w28
+ b30: 4e171fbd mov v29.b\[11\], w29
+ b34: 4e171fbd mov v29.b\[11\], w29
+ b38: 4e171fde mov v30.b\[11\], w30
+ b3c: 4e171fde mov v30.b\[11\], w30
+ b40: 4e191c21 mov v1.b\[12\], w1
+ b44: 4e191c21 mov v1.b\[12\], w1
+ b48: 4e191c42 mov v2.b\[12\], w2
+ b4c: 4e191c42 mov v2.b\[12\], w2
+ b50: 4e191c63 mov v3.b\[12\], w3
+ b54: 4e191c63 mov v3.b\[12\], w3
+ b58: 4e191c84 mov v4.b\[12\], w4
+ b5c: 4e191c84 mov v4.b\[12\], w4
+ b60: 4e191ca5 mov v5.b\[12\], w5
+ b64: 4e191ca5 mov v5.b\[12\], w5
+ b68: 4e191cc6 mov v6.b\[12\], w6
+ b6c: 4e191cc6 mov v6.b\[12\], w6
+ b70: 4e191ce7 mov v7.b\[12\], w7
+ b74: 4e191ce7 mov v7.b\[12\], w7
+ b78: 4e191d08 mov v8.b\[12\], w8
+ b7c: 4e191d08 mov v8.b\[12\], w8
+ b80: 4e191d29 mov v9.b\[12\], w9
+ b84: 4e191d29 mov v9.b\[12\], w9
+ b88: 4e191d4a mov v10.b\[12\], w10
+ b8c: 4e191d4a mov v10.b\[12\], w10
+ b90: 4e191d6b mov v11.b\[12\], w11
+ b94: 4e191d6b mov v11.b\[12\], w11
+ b98: 4e191d8c mov v12.b\[12\], w12
+ b9c: 4e191d8c mov v12.b\[12\], w12
+ ba0: 4e191dad mov v13.b\[12\], w13
+ ba4: 4e191dad mov v13.b\[12\], w13
+ ba8: 4e191dce mov v14.b\[12\], w14
+ bac: 4e191dce mov v14.b\[12\], w14
+ bb0: 4e191def mov v15.b\[12\], w15
+ bb4: 4e191def mov v15.b\[12\], w15
+ bb8: 4e191e10 mov v16.b\[12\], w16
+ bbc: 4e191e10 mov v16.b\[12\], w16
+ bc0: 4e191e31 mov v17.b\[12\], w17
+ bc4: 4e191e31 mov v17.b\[12\], w17
+ bc8: 4e191e52 mov v18.b\[12\], w18
+ bcc: 4e191e52 mov v18.b\[12\], w18
+ bd0: 4e191e73 mov v19.b\[12\], w19
+ bd4: 4e191e73 mov v19.b\[12\], w19
+ bd8: 4e191e94 mov v20.b\[12\], w20
+ bdc: 4e191e94 mov v20.b\[12\], w20
+ be0: 4e191eb5 mov v21.b\[12\], w21
+ be4: 4e191eb5 mov v21.b\[12\], w21
+ be8: 4e191ed6 mov v22.b\[12\], w22
+ bec: 4e191ed6 mov v22.b\[12\], w22
+ bf0: 4e191ef7 mov v23.b\[12\], w23
+ bf4: 4e191ef7 mov v23.b\[12\], w23
+ bf8: 4e191f18 mov v24.b\[12\], w24
+ bfc: 4e191f18 mov v24.b\[12\], w24
+ c00: 4e191f39 mov v25.b\[12\], w25
+ c04: 4e191f39 mov v25.b\[12\], w25
+ c08: 4e191f5a mov v26.b\[12\], w26
+ c0c: 4e191f5a mov v26.b\[12\], w26
+ c10: 4e191f7b mov v27.b\[12\], w27
+ c14: 4e191f7b mov v27.b\[12\], w27
+ c18: 4e191f9c mov v28.b\[12\], w28
+ c1c: 4e191f9c mov v28.b\[12\], w28
+ c20: 4e191fbd mov v29.b\[12\], w29
+ c24: 4e191fbd mov v29.b\[12\], w29
+ c28: 4e191fde mov v30.b\[12\], w30
+ c2c: 4e191fde mov v30.b\[12\], w30
+ c30: 4e1b1c21 mov v1.b\[13\], w1
+ c34: 4e1b1c21 mov v1.b\[13\], w1
+ c38: 4e1b1c42 mov v2.b\[13\], w2
+ c3c: 4e1b1c42 mov v2.b\[13\], w2
+ c40: 4e1b1c63 mov v3.b\[13\], w3
+ c44: 4e1b1c63 mov v3.b\[13\], w3
+ c48: 4e1b1c84 mov v4.b\[13\], w4
+ c4c: 4e1b1c84 mov v4.b\[13\], w4
+ c50: 4e1b1ca5 mov v5.b\[13\], w5
+ c54: 4e1b1ca5 mov v5.b\[13\], w5
+ c58: 4e1b1cc6 mov v6.b\[13\], w6
+ c5c: 4e1b1cc6 mov v6.b\[13\], w6
+ c60: 4e1b1ce7 mov v7.b\[13\], w7
+ c64: 4e1b1ce7 mov v7.b\[13\], w7
+ c68: 4e1b1d08 mov v8.b\[13\], w8
+ c6c: 4e1b1d08 mov v8.b\[13\], w8
+ c70: 4e1b1d29 mov v9.b\[13\], w9
+ c74: 4e1b1d29 mov v9.b\[13\], w9
+ c78: 4e1b1d4a mov v10.b\[13\], w10
+ c7c: 4e1b1d4a mov v10.b\[13\], w10
+ c80: 4e1b1d6b mov v11.b\[13\], w11
+ c84: 4e1b1d6b mov v11.b\[13\], w11
+ c88: 4e1b1d8c mov v12.b\[13\], w12
+ c8c: 4e1b1d8c mov v12.b\[13\], w12
+ c90: 4e1b1dad mov v13.b\[13\], w13
+ c94: 4e1b1dad mov v13.b\[13\], w13
+ c98: 4e1b1dce mov v14.b\[13\], w14
+ c9c: 4e1b1dce mov v14.b\[13\], w14
+ ca0: 4e1b1def mov v15.b\[13\], w15
+ ca4: 4e1b1def mov v15.b\[13\], w15
+ ca8: 4e1b1e10 mov v16.b\[13\], w16
+ cac: 4e1b1e10 mov v16.b\[13\], w16
+ cb0: 4e1b1e31 mov v17.b\[13\], w17
+ cb4: 4e1b1e31 mov v17.b\[13\], w17
+ cb8: 4e1b1e52 mov v18.b\[13\], w18
+ cbc: 4e1b1e52 mov v18.b\[13\], w18
+ cc0: 4e1b1e73 mov v19.b\[13\], w19
+ cc4: 4e1b1e73 mov v19.b\[13\], w19
+ cc8: 4e1b1e94 mov v20.b\[13\], w20
+ ccc: 4e1b1e94 mov v20.b\[13\], w20
+ cd0: 4e1b1eb5 mov v21.b\[13\], w21
+ cd4: 4e1b1eb5 mov v21.b\[13\], w21
+ cd8: 4e1b1ed6 mov v22.b\[13\], w22
+ cdc: 4e1b1ed6 mov v22.b\[13\], w22
+ ce0: 4e1b1ef7 mov v23.b\[13\], w23
+ ce4: 4e1b1ef7 mov v23.b\[13\], w23
+ ce8: 4e1b1f18 mov v24.b\[13\], w24
+ cec: 4e1b1f18 mov v24.b\[13\], w24
+ cf0: 4e1b1f39 mov v25.b\[13\], w25
+ cf4: 4e1b1f39 mov v25.b\[13\], w25
+ cf8: 4e1b1f5a mov v26.b\[13\], w26
+ cfc: 4e1b1f5a mov v26.b\[13\], w26
+ d00: 4e1b1f7b mov v27.b\[13\], w27
+ d04: 4e1b1f7b mov v27.b\[13\], w27
+ d08: 4e1b1f9c mov v28.b\[13\], w28
+ d0c: 4e1b1f9c mov v28.b\[13\], w28
+ d10: 4e1b1fbd mov v29.b\[13\], w29
+ d14: 4e1b1fbd mov v29.b\[13\], w29
+ d18: 4e1b1fde mov v30.b\[13\], w30
+ d1c: 4e1b1fde mov v30.b\[13\], w30
+ d20: 4e1d1c21 mov v1.b\[14\], w1
+ d24: 4e1d1c21 mov v1.b\[14\], w1
+ d28: 4e1d1c42 mov v2.b\[14\], w2
+ d2c: 4e1d1c42 mov v2.b\[14\], w2
+ d30: 4e1d1c63 mov v3.b\[14\], w3
+ d34: 4e1d1c63 mov v3.b\[14\], w3
+ d38: 4e1d1c84 mov v4.b\[14\], w4
+ d3c: 4e1d1c84 mov v4.b\[14\], w4
+ d40: 4e1d1ca5 mov v5.b\[14\], w5
+ d44: 4e1d1ca5 mov v5.b\[14\], w5
+ d48: 4e1d1cc6 mov v6.b\[14\], w6
+ d4c: 4e1d1cc6 mov v6.b\[14\], w6
+ d50: 4e1d1ce7 mov v7.b\[14\], w7
+ d54: 4e1d1ce7 mov v7.b\[14\], w7
+ d58: 4e1d1d08 mov v8.b\[14\], w8
+ d5c: 4e1d1d08 mov v8.b\[14\], w8
+ d60: 4e1d1d29 mov v9.b\[14\], w9
+ d64: 4e1d1d29 mov v9.b\[14\], w9
+ d68: 4e1d1d4a mov v10.b\[14\], w10
+ d6c: 4e1d1d4a mov v10.b\[14\], w10
+ d70: 4e1d1d6b mov v11.b\[14\], w11
+ d74: 4e1d1d6b mov v11.b\[14\], w11
+ d78: 4e1d1d8c mov v12.b\[14\], w12
+ d7c: 4e1d1d8c mov v12.b\[14\], w12
+ d80: 4e1d1dad mov v13.b\[14\], w13
+ d84: 4e1d1dad mov v13.b\[14\], w13
+ d88: 4e1d1dce mov v14.b\[14\], w14
+ d8c: 4e1d1dce mov v14.b\[14\], w14
+ d90: 4e1d1def mov v15.b\[14\], w15
+ d94: 4e1d1def mov v15.b\[14\], w15
+ d98: 4e1d1e10 mov v16.b\[14\], w16
+ d9c: 4e1d1e10 mov v16.b\[14\], w16
+ da0: 4e1d1e31 mov v17.b\[14\], w17
+ da4: 4e1d1e31 mov v17.b\[14\], w17
+ da8: 4e1d1e52 mov v18.b\[14\], w18
+ dac: 4e1d1e52 mov v18.b\[14\], w18
+ db0: 4e1d1e73 mov v19.b\[14\], w19
+ db4: 4e1d1e73 mov v19.b\[14\], w19
+ db8: 4e1d1e94 mov v20.b\[14\], w20
+ dbc: 4e1d1e94 mov v20.b\[14\], w20
+ dc0: 4e1d1eb5 mov v21.b\[14\], w21
+ dc4: 4e1d1eb5 mov v21.b\[14\], w21
+ dc8: 4e1d1ed6 mov v22.b\[14\], w22
+ dcc: 4e1d1ed6 mov v22.b\[14\], w22
+ dd0: 4e1d1ef7 mov v23.b\[14\], w23
+ dd4: 4e1d1ef7 mov v23.b\[14\], w23
+ dd8: 4e1d1f18 mov v24.b\[14\], w24
+ ddc: 4e1d1f18 mov v24.b\[14\], w24
+ de0: 4e1d1f39 mov v25.b\[14\], w25
+ de4: 4e1d1f39 mov v25.b\[14\], w25
+ de8: 4e1d1f5a mov v26.b\[14\], w26
+ dec: 4e1d1f5a mov v26.b\[14\], w26
+ df0: 4e1d1f7b mov v27.b\[14\], w27
+ df4: 4e1d1f7b mov v27.b\[14\], w27
+ df8: 4e1d1f9c mov v28.b\[14\], w28
+ dfc: 4e1d1f9c mov v28.b\[14\], w28
+ e00: 4e1d1fbd mov v29.b\[14\], w29
+ e04: 4e1d1fbd mov v29.b\[14\], w29
+ e08: 4e1d1fde mov v30.b\[14\], w30
+ e0c: 4e1d1fde mov v30.b\[14\], w30
+ e10: 4e1f1c21 mov v1.b\[15\], w1
+ e14: 4e1f1c21 mov v1.b\[15\], w1
+ e18: 4e1f1c42 mov v2.b\[15\], w2
+ e1c: 4e1f1c42 mov v2.b\[15\], w2
+ e20: 4e1f1c63 mov v3.b\[15\], w3
+ e24: 4e1f1c63 mov v3.b\[15\], w3
+ e28: 4e1f1c84 mov v4.b\[15\], w4
+ e2c: 4e1f1c84 mov v4.b\[15\], w4
+ e30: 4e1f1ca5 mov v5.b\[15\], w5
+ e34: 4e1f1ca5 mov v5.b\[15\], w5
+ e38: 4e1f1cc6 mov v6.b\[15\], w6
+ e3c: 4e1f1cc6 mov v6.b\[15\], w6
+ e40: 4e1f1ce7 mov v7.b\[15\], w7
+ e44: 4e1f1ce7 mov v7.b\[15\], w7
+ e48: 4e1f1d08 mov v8.b\[15\], w8
+ e4c: 4e1f1d08 mov v8.b\[15\], w8
+ e50: 4e1f1d29 mov v9.b\[15\], w9
+ e54: 4e1f1d29 mov v9.b\[15\], w9
+ e58: 4e1f1d4a mov v10.b\[15\], w10
+ e5c: 4e1f1d4a mov v10.b\[15\], w10
+ e60: 4e1f1d6b mov v11.b\[15\], w11
+ e64: 4e1f1d6b mov v11.b\[15\], w11
+ e68: 4e1f1d8c mov v12.b\[15\], w12
+ e6c: 4e1f1d8c mov v12.b\[15\], w12
+ e70: 4e1f1dad mov v13.b\[15\], w13
+ e74: 4e1f1dad mov v13.b\[15\], w13
+ e78: 4e1f1dce mov v14.b\[15\], w14
+ e7c: 4e1f1dce mov v14.b\[15\], w14
+ e80: 4e1f1def mov v15.b\[15\], w15
+ e84: 4e1f1def mov v15.b\[15\], w15
+ e88: 4e1f1e10 mov v16.b\[15\], w16
+ e8c: 4e1f1e10 mov v16.b\[15\], w16
+ e90: 4e1f1e31 mov v17.b\[15\], w17
+ e94: 4e1f1e31 mov v17.b\[15\], w17
+ e98: 4e1f1e52 mov v18.b\[15\], w18
+ e9c: 4e1f1e52 mov v18.b\[15\], w18
+ ea0: 4e1f1e73 mov v19.b\[15\], w19
+ ea4: 4e1f1e73 mov v19.b\[15\], w19
+ ea8: 4e1f1e94 mov v20.b\[15\], w20
+ eac: 4e1f1e94 mov v20.b\[15\], w20
+ eb0: 4e1f1eb5 mov v21.b\[15\], w21
+ eb4: 4e1f1eb5 mov v21.b\[15\], w21
+ eb8: 4e1f1ed6 mov v22.b\[15\], w22
+ ebc: 4e1f1ed6 mov v22.b\[15\], w22
+ ec0: 4e1f1ef7 mov v23.b\[15\], w23
+ ec4: 4e1f1ef7 mov v23.b\[15\], w23
+ ec8: 4e1f1f18 mov v24.b\[15\], w24
+ ecc: 4e1f1f18 mov v24.b\[15\], w24
+ ed0: 4e1f1f39 mov v25.b\[15\], w25
+ ed4: 4e1f1f39 mov v25.b\[15\], w25
+ ed8: 4e1f1f5a mov v26.b\[15\], w26
+ edc: 4e1f1f5a mov v26.b\[15\], w26
+ ee0: 4e1f1f7b mov v27.b\[15\], w27
+ ee4: 4e1f1f7b mov v27.b\[15\], w27
+ ee8: 4e1f1f9c mov v28.b\[15\], w28
+ eec: 4e1f1f9c mov v28.b\[15\], w28
+ ef0: 4e1f1fbd mov v29.b\[15\], w29
+ ef4: 4e1f1fbd mov v29.b\[15\], w29
+ ef8: 4e1f1fde mov v30.b\[15\], w30
+ efc: 4e1f1fde mov v30.b\[15\], w30
+ f00: 4e021c21 mov v1.h\[0\], w1
+ f04: 4e021c21 mov v1.h\[0\], w1
+ f08: 4e021c42 mov v2.h\[0\], w2
+ f0c: 4e021c42 mov v2.h\[0\], w2
+ f10: 4e021c63 mov v3.h\[0\], w3
+ f14: 4e021c63 mov v3.h\[0\], w3
+ f18: 4e021c84 mov v4.h\[0\], w4
+ f1c: 4e021c84 mov v4.h\[0\], w4
+ f20: 4e021ca5 mov v5.h\[0\], w5
+ f24: 4e021ca5 mov v5.h\[0\], w5
+ f28: 4e021cc6 mov v6.h\[0\], w6
+ f2c: 4e021cc6 mov v6.h\[0\], w6
+ f30: 4e021ce7 mov v7.h\[0\], w7
+ f34: 4e021ce7 mov v7.h\[0\], w7
+ f38: 4e021d08 mov v8.h\[0\], w8
+ f3c: 4e021d08 mov v8.h\[0\], w8
+ f40: 4e021d29 mov v9.h\[0\], w9
+ f44: 4e021d29 mov v9.h\[0\], w9
+ f48: 4e021d4a mov v10.h\[0\], w10
+ f4c: 4e021d4a mov v10.h\[0\], w10
+ f50: 4e021d6b mov v11.h\[0\], w11
+ f54: 4e021d6b mov v11.h\[0\], w11
+ f58: 4e021d8c mov v12.h\[0\], w12
+ f5c: 4e021d8c mov v12.h\[0\], w12
+ f60: 4e021dad mov v13.h\[0\], w13
+ f64: 4e021dad mov v13.h\[0\], w13
+ f68: 4e021dce mov v14.h\[0\], w14
+ f6c: 4e021dce mov v14.h\[0\], w14
+ f70: 4e021def mov v15.h\[0\], w15
+ f74: 4e021def mov v15.h\[0\], w15
+ f78: 4e021e10 mov v16.h\[0\], w16
+ f7c: 4e021e10 mov v16.h\[0\], w16
+ f80: 4e021e31 mov v17.h\[0\], w17
+ f84: 4e021e31 mov v17.h\[0\], w17
+ f88: 4e021e52 mov v18.h\[0\], w18
+ f8c: 4e021e52 mov v18.h\[0\], w18
+ f90: 4e021e73 mov v19.h\[0\], w19
+ f94: 4e021e73 mov v19.h\[0\], w19
+ f98: 4e021e94 mov v20.h\[0\], w20
+ f9c: 4e021e94 mov v20.h\[0\], w20
+ fa0: 4e021eb5 mov v21.h\[0\], w21
+ fa4: 4e021eb5 mov v21.h\[0\], w21
+ fa8: 4e021ed6 mov v22.h\[0\], w22
+ fac: 4e021ed6 mov v22.h\[0\], w22
+ fb0: 4e021ef7 mov v23.h\[0\], w23
+ fb4: 4e021ef7 mov v23.h\[0\], w23
+ fb8: 4e021f18 mov v24.h\[0\], w24
+ fbc: 4e021f18 mov v24.h\[0\], w24
+ fc0: 4e021f39 mov v25.h\[0\], w25
+ fc4: 4e021f39 mov v25.h\[0\], w25
+ fc8: 4e021f5a mov v26.h\[0\], w26
+ fcc: 4e021f5a mov v26.h\[0\], w26
+ fd0: 4e021f7b mov v27.h\[0\], w27
+ fd4: 4e021f7b mov v27.h\[0\], w27
+ fd8: 4e021f9c mov v28.h\[0\], w28
+ fdc: 4e021f9c mov v28.h\[0\], w28
+ fe0: 4e021fbd mov v29.h\[0\], w29
+ fe4: 4e021fbd mov v29.h\[0\], w29
+ fe8: 4e021fde mov v30.h\[0\], w30
+ fec: 4e021fde mov v30.h\[0\], w30
+ ff0: 4e061c21 mov v1.h\[1\], w1
+ ff4: 4e061c21 mov v1.h\[1\], w1
+ ff8: 4e061c42 mov v2.h\[1\], w2
+ ffc: 4e061c42 mov v2.h\[1\], w2
+ 1000: 4e061c63 mov v3.h\[1\], w3
+ 1004: 4e061c63 mov v3.h\[1\], w3
+ 1008: 4e061c84 mov v4.h\[1\], w4
+ 100c: 4e061c84 mov v4.h\[1\], w4
+ 1010: 4e061ca5 mov v5.h\[1\], w5
+ 1014: 4e061ca5 mov v5.h\[1\], w5
+ 1018: 4e061cc6 mov v6.h\[1\], w6
+ 101c: 4e061cc6 mov v6.h\[1\], w6
+ 1020: 4e061ce7 mov v7.h\[1\], w7
+ 1024: 4e061ce7 mov v7.h\[1\], w7
+ 1028: 4e061d08 mov v8.h\[1\], w8
+ 102c: 4e061d08 mov v8.h\[1\], w8
+ 1030: 4e061d29 mov v9.h\[1\], w9
+ 1034: 4e061d29 mov v9.h\[1\], w9
+ 1038: 4e061d4a mov v10.h\[1\], w10
+ 103c: 4e061d4a mov v10.h\[1\], w10
+ 1040: 4e061d6b mov v11.h\[1\], w11
+ 1044: 4e061d6b mov v11.h\[1\], w11
+ 1048: 4e061d8c mov v12.h\[1\], w12
+ 104c: 4e061d8c mov v12.h\[1\], w12
+ 1050: 4e061dad mov v13.h\[1\], w13
+ 1054: 4e061dad mov v13.h\[1\], w13
+ 1058: 4e061dce mov v14.h\[1\], w14
+ 105c: 4e061dce mov v14.h\[1\], w14
+ 1060: 4e061def mov v15.h\[1\], w15
+ 1064: 4e061def mov v15.h\[1\], w15
+ 1068: 4e061e10 mov v16.h\[1\], w16
+ 106c: 4e061e10 mov v16.h\[1\], w16
+ 1070: 4e061e31 mov v17.h\[1\], w17
+ 1074: 4e061e31 mov v17.h\[1\], w17
+ 1078: 4e061e52 mov v18.h\[1\], w18
+ 107c: 4e061e52 mov v18.h\[1\], w18
+ 1080: 4e061e73 mov v19.h\[1\], w19
+ 1084: 4e061e73 mov v19.h\[1\], w19
+ 1088: 4e061e94 mov v20.h\[1\], w20
+ 108c: 4e061e94 mov v20.h\[1\], w20
+ 1090: 4e061eb5 mov v21.h\[1\], w21
+ 1094: 4e061eb5 mov v21.h\[1\], w21
+ 1098: 4e061ed6 mov v22.h\[1\], w22
+ 109c: 4e061ed6 mov v22.h\[1\], w22
+ 10a0: 4e061ef7 mov v23.h\[1\], w23
+ 10a4: 4e061ef7 mov v23.h\[1\], w23
+ 10a8: 4e061f18 mov v24.h\[1\], w24
+ 10ac: 4e061f18 mov v24.h\[1\], w24
+ 10b0: 4e061f39 mov v25.h\[1\], w25
+ 10b4: 4e061f39 mov v25.h\[1\], w25
+ 10b8: 4e061f5a mov v26.h\[1\], w26
+ 10bc: 4e061f5a mov v26.h\[1\], w26
+ 10c0: 4e061f7b mov v27.h\[1\], w27
+ 10c4: 4e061f7b mov v27.h\[1\], w27
+ 10c8: 4e061f9c mov v28.h\[1\], w28
+ 10cc: 4e061f9c mov v28.h\[1\], w28
+ 10d0: 4e061fbd mov v29.h\[1\], w29
+ 10d4: 4e061fbd mov v29.h\[1\], w29
+ 10d8: 4e061fde mov v30.h\[1\], w30
+ 10dc: 4e061fde mov v30.h\[1\], w30
+ 10e0: 4e0a1c21 mov v1.h\[2\], w1
+ 10e4: 4e0a1c21 mov v1.h\[2\], w1
+ 10e8: 4e0a1c42 mov v2.h\[2\], w2
+ 10ec: 4e0a1c42 mov v2.h\[2\], w2
+ 10f0: 4e0a1c63 mov v3.h\[2\], w3
+ 10f4: 4e0a1c63 mov v3.h\[2\], w3
+ 10f8: 4e0a1c84 mov v4.h\[2\], w4
+ 10fc: 4e0a1c84 mov v4.h\[2\], w4
+ 1100: 4e0a1ca5 mov v5.h\[2\], w5
+ 1104: 4e0a1ca5 mov v5.h\[2\], w5
+ 1108: 4e0a1cc6 mov v6.h\[2\], w6
+ 110c: 4e0a1cc6 mov v6.h\[2\], w6
+ 1110: 4e0a1ce7 mov v7.h\[2\], w7
+ 1114: 4e0a1ce7 mov v7.h\[2\], w7
+ 1118: 4e0a1d08 mov v8.h\[2\], w8
+ 111c: 4e0a1d08 mov v8.h\[2\], w8
+ 1120: 4e0a1d29 mov v9.h\[2\], w9
+ 1124: 4e0a1d29 mov v9.h\[2\], w9
+ 1128: 4e0a1d4a mov v10.h\[2\], w10
+ 112c: 4e0a1d4a mov v10.h\[2\], w10
+ 1130: 4e0a1d6b mov v11.h\[2\], w11
+ 1134: 4e0a1d6b mov v11.h\[2\], w11
+ 1138: 4e0a1d8c mov v12.h\[2\], w12
+ 113c: 4e0a1d8c mov v12.h\[2\], w12
+ 1140: 4e0a1dad mov v13.h\[2\], w13
+ 1144: 4e0a1dad mov v13.h\[2\], w13
+ 1148: 4e0a1dce mov v14.h\[2\], w14
+ 114c: 4e0a1dce mov v14.h\[2\], w14
+ 1150: 4e0a1def mov v15.h\[2\], w15
+ 1154: 4e0a1def mov v15.h\[2\], w15
+ 1158: 4e0a1e10 mov v16.h\[2\], w16
+ 115c: 4e0a1e10 mov v16.h\[2\], w16
+ 1160: 4e0a1e31 mov v17.h\[2\], w17
+ 1164: 4e0a1e31 mov v17.h\[2\], w17
+ 1168: 4e0a1e52 mov v18.h\[2\], w18
+ 116c: 4e0a1e52 mov v18.h\[2\], w18
+ 1170: 4e0a1e73 mov v19.h\[2\], w19
+ 1174: 4e0a1e73 mov v19.h\[2\], w19
+ 1178: 4e0a1e94 mov v20.h\[2\], w20
+ 117c: 4e0a1e94 mov v20.h\[2\], w20
+ 1180: 4e0a1eb5 mov v21.h\[2\], w21
+ 1184: 4e0a1eb5 mov v21.h\[2\], w21
+ 1188: 4e0a1ed6 mov v22.h\[2\], w22
+ 118c: 4e0a1ed6 mov v22.h\[2\], w22
+ 1190: 4e0a1ef7 mov v23.h\[2\], w23
+ 1194: 4e0a1ef7 mov v23.h\[2\], w23
+ 1198: 4e0a1f18 mov v24.h\[2\], w24
+ 119c: 4e0a1f18 mov v24.h\[2\], w24
+ 11a0: 4e0a1f39 mov v25.h\[2\], w25
+ 11a4: 4e0a1f39 mov v25.h\[2\], w25
+ 11a8: 4e0a1f5a mov v26.h\[2\], w26
+ 11ac: 4e0a1f5a mov v26.h\[2\], w26
+ 11b0: 4e0a1f7b mov v27.h\[2\], w27
+ 11b4: 4e0a1f7b mov v27.h\[2\], w27
+ 11b8: 4e0a1f9c mov v28.h\[2\], w28
+ 11bc: 4e0a1f9c mov v28.h\[2\], w28
+ 11c0: 4e0a1fbd mov v29.h\[2\], w29
+ 11c4: 4e0a1fbd mov v29.h\[2\], w29
+ 11c8: 4e0a1fde mov v30.h\[2\], w30
+ 11cc: 4e0a1fde mov v30.h\[2\], w30
+ 11d0: 4e0e1c21 mov v1.h\[3\], w1
+ 11d4: 4e0e1c21 mov v1.h\[3\], w1
+ 11d8: 4e0e1c42 mov v2.h\[3\], w2
+ 11dc: 4e0e1c42 mov v2.h\[3\], w2
+ 11e0: 4e0e1c63 mov v3.h\[3\], w3
+ 11e4: 4e0e1c63 mov v3.h\[3\], w3
+ 11e8: 4e0e1c84 mov v4.h\[3\], w4
+ 11ec: 4e0e1c84 mov v4.h\[3\], w4
+ 11f0: 4e0e1ca5 mov v5.h\[3\], w5
+ 11f4: 4e0e1ca5 mov v5.h\[3\], w5
+ 11f8: 4e0e1cc6 mov v6.h\[3\], w6
+ 11fc: 4e0e1cc6 mov v6.h\[3\], w6
+ 1200: 4e0e1ce7 mov v7.h\[3\], w7
+ 1204: 4e0e1ce7 mov v7.h\[3\], w7
+ 1208: 4e0e1d08 mov v8.h\[3\], w8
+ 120c: 4e0e1d08 mov v8.h\[3\], w8
+ 1210: 4e0e1d29 mov v9.h\[3\], w9
+ 1214: 4e0e1d29 mov v9.h\[3\], w9
+ 1218: 4e0e1d4a mov v10.h\[3\], w10
+ 121c: 4e0e1d4a mov v10.h\[3\], w10
+ 1220: 4e0e1d6b mov v11.h\[3\], w11
+ 1224: 4e0e1d6b mov v11.h\[3\], w11
+ 1228: 4e0e1d8c mov v12.h\[3\], w12
+ 122c: 4e0e1d8c mov v12.h\[3\], w12
+ 1230: 4e0e1dad mov v13.h\[3\], w13
+ 1234: 4e0e1dad mov v13.h\[3\], w13
+ 1238: 4e0e1dce mov v14.h\[3\], w14
+ 123c: 4e0e1dce mov v14.h\[3\], w14
+ 1240: 4e0e1def mov v15.h\[3\], w15
+ 1244: 4e0e1def mov v15.h\[3\], w15
+ 1248: 4e0e1e10 mov v16.h\[3\], w16
+ 124c: 4e0e1e10 mov v16.h\[3\], w16
+ 1250: 4e0e1e31 mov v17.h\[3\], w17
+ 1254: 4e0e1e31 mov v17.h\[3\], w17
+ 1258: 4e0e1e52 mov v18.h\[3\], w18
+ 125c: 4e0e1e52 mov v18.h\[3\], w18
+ 1260: 4e0e1e73 mov v19.h\[3\], w19
+ 1264: 4e0e1e73 mov v19.h\[3\], w19
+ 1268: 4e0e1e94 mov v20.h\[3\], w20
+ 126c: 4e0e1e94 mov v20.h\[3\], w20
+ 1270: 4e0e1eb5 mov v21.h\[3\], w21
+ 1274: 4e0e1eb5 mov v21.h\[3\], w21
+ 1278: 4e0e1ed6 mov v22.h\[3\], w22
+ 127c: 4e0e1ed6 mov v22.h\[3\], w22
+ 1280: 4e0e1ef7 mov v23.h\[3\], w23
+ 1284: 4e0e1ef7 mov v23.h\[3\], w23
+ 1288: 4e0e1f18 mov v24.h\[3\], w24
+ 128c: 4e0e1f18 mov v24.h\[3\], w24
+ 1290: 4e0e1f39 mov v25.h\[3\], w25
+ 1294: 4e0e1f39 mov v25.h\[3\], w25
+ 1298: 4e0e1f5a mov v26.h\[3\], w26
+ 129c: 4e0e1f5a mov v26.h\[3\], w26
+ 12a0: 4e0e1f7b mov v27.h\[3\], w27
+ 12a4: 4e0e1f7b mov v27.h\[3\], w27
+ 12a8: 4e0e1f9c mov v28.h\[3\], w28
+ 12ac: 4e0e1f9c mov v28.h\[3\], w28
+ 12b0: 4e0e1fbd mov v29.h\[3\], w29
+ 12b4: 4e0e1fbd mov v29.h\[3\], w29
+ 12b8: 4e0e1fde mov v30.h\[3\], w30
+ 12bc: 4e0e1fde mov v30.h\[3\], w30
+ 12c0: 4e121c21 mov v1.h\[4\], w1
+ 12c4: 4e121c21 mov v1.h\[4\], w1
+ 12c8: 4e121c42 mov v2.h\[4\], w2
+ 12cc: 4e121c42 mov v2.h\[4\], w2
+ 12d0: 4e121c63 mov v3.h\[4\], w3
+ 12d4: 4e121c63 mov v3.h\[4\], w3
+ 12d8: 4e121c84 mov v4.h\[4\], w4
+ 12dc: 4e121c84 mov v4.h\[4\], w4
+ 12e0: 4e121ca5 mov v5.h\[4\], w5
+ 12e4: 4e121ca5 mov v5.h\[4\], w5
+ 12e8: 4e121cc6 mov v6.h\[4\], w6
+ 12ec: 4e121cc6 mov v6.h\[4\], w6
+ 12f0: 4e121ce7 mov v7.h\[4\], w7
+ 12f4: 4e121ce7 mov v7.h\[4\], w7
+ 12f8: 4e121d08 mov v8.h\[4\], w8
+ 12fc: 4e121d08 mov v8.h\[4\], w8
+ 1300: 4e121d29 mov v9.h\[4\], w9
+ 1304: 4e121d29 mov v9.h\[4\], w9
+ 1308: 4e121d4a mov v10.h\[4\], w10
+ 130c: 4e121d4a mov v10.h\[4\], w10
+ 1310: 4e121d6b mov v11.h\[4\], w11
+ 1314: 4e121d6b mov v11.h\[4\], w11
+ 1318: 4e121d8c mov v12.h\[4\], w12
+ 131c: 4e121d8c mov v12.h\[4\], w12
+ 1320: 4e121dad mov v13.h\[4\], w13
+ 1324: 4e121dad mov v13.h\[4\], w13
+ 1328: 4e121dce mov v14.h\[4\], w14
+ 132c: 4e121dce mov v14.h\[4\], w14
+ 1330: 4e121def mov v15.h\[4\], w15
+ 1334: 4e121def mov v15.h\[4\], w15
+ 1338: 4e121e10 mov v16.h\[4\], w16
+ 133c: 4e121e10 mov v16.h\[4\], w16
+ 1340: 4e121e31 mov v17.h\[4\], w17
+ 1344: 4e121e31 mov v17.h\[4\], w17
+ 1348: 4e121e52 mov v18.h\[4\], w18
+ 134c: 4e121e52 mov v18.h\[4\], w18
+ 1350: 4e121e73 mov v19.h\[4\], w19
+ 1354: 4e121e73 mov v19.h\[4\], w19
+ 1358: 4e121e94 mov v20.h\[4\], w20
+ 135c: 4e121e94 mov v20.h\[4\], w20
+ 1360: 4e121eb5 mov v21.h\[4\], w21
+ 1364: 4e121eb5 mov v21.h\[4\], w21
+ 1368: 4e121ed6 mov v22.h\[4\], w22
+ 136c: 4e121ed6 mov v22.h\[4\], w22
+ 1370: 4e121ef7 mov v23.h\[4\], w23
+ 1374: 4e121ef7 mov v23.h\[4\], w23
+ 1378: 4e121f18 mov v24.h\[4\], w24
+ 137c: 4e121f18 mov v24.h\[4\], w24
+ 1380: 4e121f39 mov v25.h\[4\], w25
+ 1384: 4e121f39 mov v25.h\[4\], w25
+ 1388: 4e121f5a mov v26.h\[4\], w26
+ 138c: 4e121f5a mov v26.h\[4\], w26
+ 1390: 4e121f7b mov v27.h\[4\], w27
+ 1394: 4e121f7b mov v27.h\[4\], w27
+ 1398: 4e121f9c mov v28.h\[4\], w28
+ 139c: 4e121f9c mov v28.h\[4\], w28
+ 13a0: 4e121fbd mov v29.h\[4\], w29
+ 13a4: 4e121fbd mov v29.h\[4\], w29
+ 13a8: 4e121fde mov v30.h\[4\], w30
+ 13ac: 4e121fde mov v30.h\[4\], w30
+ 13b0: 4e161c21 mov v1.h\[5\], w1
+ 13b4: 4e161c21 mov v1.h\[5\], w1
+ 13b8: 4e161c42 mov v2.h\[5\], w2
+ 13bc: 4e161c42 mov v2.h\[5\], w2
+ 13c0: 4e161c63 mov v3.h\[5\], w3
+ 13c4: 4e161c63 mov v3.h\[5\], w3
+ 13c8: 4e161c84 mov v4.h\[5\], w4
+ 13cc: 4e161c84 mov v4.h\[5\], w4
+ 13d0: 4e161ca5 mov v5.h\[5\], w5
+ 13d4: 4e161ca5 mov v5.h\[5\], w5
+ 13d8: 4e161cc6 mov v6.h\[5\], w6
+ 13dc: 4e161cc6 mov v6.h\[5\], w6
+ 13e0: 4e161ce7 mov v7.h\[5\], w7
+ 13e4: 4e161ce7 mov v7.h\[5\], w7
+ 13e8: 4e161d08 mov v8.h\[5\], w8
+ 13ec: 4e161d08 mov v8.h\[5\], w8
+ 13f0: 4e161d29 mov v9.h\[5\], w9
+ 13f4: 4e161d29 mov v9.h\[5\], w9
+ 13f8: 4e161d4a mov v10.h\[5\], w10
+ 13fc: 4e161d4a mov v10.h\[5\], w10
+ 1400: 4e161d6b mov v11.h\[5\], w11
+ 1404: 4e161d6b mov v11.h\[5\], w11
+ 1408: 4e161d8c mov v12.h\[5\], w12
+ 140c: 4e161d8c mov v12.h\[5\], w12
+ 1410: 4e161dad mov v13.h\[5\], w13
+ 1414: 4e161dad mov v13.h\[5\], w13
+ 1418: 4e161dce mov v14.h\[5\], w14
+ 141c: 4e161dce mov v14.h\[5\], w14
+ 1420: 4e161def mov v15.h\[5\], w15
+ 1424: 4e161def mov v15.h\[5\], w15
+ 1428: 4e161e10 mov v16.h\[5\], w16
+ 142c: 4e161e10 mov v16.h\[5\], w16
+ 1430: 4e161e31 mov v17.h\[5\], w17
+ 1434: 4e161e31 mov v17.h\[5\], w17
+ 1438: 4e161e52 mov v18.h\[5\], w18
+ 143c: 4e161e52 mov v18.h\[5\], w18
+ 1440: 4e161e73 mov v19.h\[5\], w19
+ 1444: 4e161e73 mov v19.h\[5\], w19
+ 1448: 4e161e94 mov v20.h\[5\], w20
+ 144c: 4e161e94 mov v20.h\[5\], w20
+ 1450: 4e161eb5 mov v21.h\[5\], w21
+ 1454: 4e161eb5 mov v21.h\[5\], w21
+ 1458: 4e161ed6 mov v22.h\[5\], w22
+ 145c: 4e161ed6 mov v22.h\[5\], w22
+ 1460: 4e161ef7 mov v23.h\[5\], w23
+ 1464: 4e161ef7 mov v23.h\[5\], w23
+ 1468: 4e161f18 mov v24.h\[5\], w24
+ 146c: 4e161f18 mov v24.h\[5\], w24
+ 1470: 4e161f39 mov v25.h\[5\], w25
+ 1474: 4e161f39 mov v25.h\[5\], w25
+ 1478: 4e161f5a mov v26.h\[5\], w26
+ 147c: 4e161f5a mov v26.h\[5\], w26
+ 1480: 4e161f7b mov v27.h\[5\], w27
+ 1484: 4e161f7b mov v27.h\[5\], w27
+ 1488: 4e161f9c mov v28.h\[5\], w28
+ 148c: 4e161f9c mov v28.h\[5\], w28
+ 1490: 4e161fbd mov v29.h\[5\], w29
+ 1494: 4e161fbd mov v29.h\[5\], w29
+ 1498: 4e161fde mov v30.h\[5\], w30
+ 149c: 4e161fde mov v30.h\[5\], w30
+ 14a0: 4e1a1c21 mov v1.h\[6\], w1
+ 14a4: 4e1a1c21 mov v1.h\[6\], w1
+ 14a8: 4e1a1c42 mov v2.h\[6\], w2
+ 14ac: 4e1a1c42 mov v2.h\[6\], w2
+ 14b0: 4e1a1c63 mov v3.h\[6\], w3
+ 14b4: 4e1a1c63 mov v3.h\[6\], w3
+ 14b8: 4e1a1c84 mov v4.h\[6\], w4
+ 14bc: 4e1a1c84 mov v4.h\[6\], w4
+ 14c0: 4e1a1ca5 mov v5.h\[6\], w5
+ 14c4: 4e1a1ca5 mov v5.h\[6\], w5
+ 14c8: 4e1a1cc6 mov v6.h\[6\], w6
+ 14cc: 4e1a1cc6 mov v6.h\[6\], w6
+ 14d0: 4e1a1ce7 mov v7.h\[6\], w7
+ 14d4: 4e1a1ce7 mov v7.h\[6\], w7
+ 14d8: 4e1a1d08 mov v8.h\[6\], w8
+ 14dc: 4e1a1d08 mov v8.h\[6\], w8
+ 14e0: 4e1a1d29 mov v9.h\[6\], w9
+ 14e4: 4e1a1d29 mov v9.h\[6\], w9
+ 14e8: 4e1a1d4a mov v10.h\[6\], w10
+ 14ec: 4e1a1d4a mov v10.h\[6\], w10
+ 14f0: 4e1a1d6b mov v11.h\[6\], w11
+ 14f4: 4e1a1d6b mov v11.h\[6\], w11
+ 14f8: 4e1a1d8c mov v12.h\[6\], w12
+ 14fc: 4e1a1d8c mov v12.h\[6\], w12
+ 1500: 4e1a1dad mov v13.h\[6\], w13
+ 1504: 4e1a1dad mov v13.h\[6\], w13
+ 1508: 4e1a1dce mov v14.h\[6\], w14
+ 150c: 4e1a1dce mov v14.h\[6\], w14
+ 1510: 4e1a1def mov v15.h\[6\], w15
+ 1514: 4e1a1def mov v15.h\[6\], w15
+ 1518: 4e1a1e10 mov v16.h\[6\], w16
+ 151c: 4e1a1e10 mov v16.h\[6\], w16
+ 1520: 4e1a1e31 mov v17.h\[6\], w17
+ 1524: 4e1a1e31 mov v17.h\[6\], w17
+ 1528: 4e1a1e52 mov v18.h\[6\], w18
+ 152c: 4e1a1e52 mov v18.h\[6\], w18
+ 1530: 4e1a1e73 mov v19.h\[6\], w19
+ 1534: 4e1a1e73 mov v19.h\[6\], w19
+ 1538: 4e1a1e94 mov v20.h\[6\], w20
+ 153c: 4e1a1e94 mov v20.h\[6\], w20
+ 1540: 4e1a1eb5 mov v21.h\[6\], w21
+ 1544: 4e1a1eb5 mov v21.h\[6\], w21
+ 1548: 4e1a1ed6 mov v22.h\[6\], w22
+ 154c: 4e1a1ed6 mov v22.h\[6\], w22
+ 1550: 4e1a1ef7 mov v23.h\[6\], w23
+ 1554: 4e1a1ef7 mov v23.h\[6\], w23
+ 1558: 4e1a1f18 mov v24.h\[6\], w24
+ 155c: 4e1a1f18 mov v24.h\[6\], w24
+ 1560: 4e1a1f39 mov v25.h\[6\], w25
+ 1564: 4e1a1f39 mov v25.h\[6\], w25
+ 1568: 4e1a1f5a mov v26.h\[6\], w26
+ 156c: 4e1a1f5a mov v26.h\[6\], w26
+ 1570: 4e1a1f7b mov v27.h\[6\], w27
+ 1574: 4e1a1f7b mov v27.h\[6\], w27
+ 1578: 4e1a1f9c mov v28.h\[6\], w28
+ 157c: 4e1a1f9c mov v28.h\[6\], w28
+ 1580: 4e1a1fbd mov v29.h\[6\], w29
+ 1584: 4e1a1fbd mov v29.h\[6\], w29
+ 1588: 4e1a1fde mov v30.h\[6\], w30
+ 158c: 4e1a1fde mov v30.h\[6\], w30
+ 1590: 4e1e1c21 mov v1.h\[7\], w1
+ 1594: 4e1e1c21 mov v1.h\[7\], w1
+ 1598: 4e1e1c42 mov v2.h\[7\], w2
+ 159c: 4e1e1c42 mov v2.h\[7\], w2
+ 15a0: 4e1e1c63 mov v3.h\[7\], w3
+ 15a4: 4e1e1c63 mov v3.h\[7\], w3
+ 15a8: 4e1e1c84 mov v4.h\[7\], w4
+ 15ac: 4e1e1c84 mov v4.h\[7\], w4
+ 15b0: 4e1e1ca5 mov v5.h\[7\], w5
+ 15b4: 4e1e1ca5 mov v5.h\[7\], w5
+ 15b8: 4e1e1cc6 mov v6.h\[7\], w6
+ 15bc: 4e1e1cc6 mov v6.h\[7\], w6
+ 15c0: 4e1e1ce7 mov v7.h\[7\], w7
+ 15c4: 4e1e1ce7 mov v7.h\[7\], w7
+ 15c8: 4e1e1d08 mov v8.h\[7\], w8
+ 15cc: 4e1e1d08 mov v8.h\[7\], w8
+ 15d0: 4e1e1d29 mov v9.h\[7\], w9
+ 15d4: 4e1e1d29 mov v9.h\[7\], w9
+ 15d8: 4e1e1d4a mov v10.h\[7\], w10
+ 15dc: 4e1e1d4a mov v10.h\[7\], w10
+ 15e0: 4e1e1d6b mov v11.h\[7\], w11
+ 15e4: 4e1e1d6b mov v11.h\[7\], w11
+ 15e8: 4e1e1d8c mov v12.h\[7\], w12
+ 15ec: 4e1e1d8c mov v12.h\[7\], w12
+ 15f0: 4e1e1dad mov v13.h\[7\], w13
+ 15f4: 4e1e1dad mov v13.h\[7\], w13
+ 15f8: 4e1e1dce mov v14.h\[7\], w14
+ 15fc: 4e1e1dce mov v14.h\[7\], w14
+ 1600: 4e1e1def mov v15.h\[7\], w15
+ 1604: 4e1e1def mov v15.h\[7\], w15
+ 1608: 4e1e1e10 mov v16.h\[7\], w16
+ 160c: 4e1e1e10 mov v16.h\[7\], w16
+ 1610: 4e1e1e31 mov v17.h\[7\], w17
+ 1614: 4e1e1e31 mov v17.h\[7\], w17
+ 1618: 4e1e1e52 mov v18.h\[7\], w18
+ 161c: 4e1e1e52 mov v18.h\[7\], w18
+ 1620: 4e1e1e73 mov v19.h\[7\], w19
+ 1624: 4e1e1e73 mov v19.h\[7\], w19
+ 1628: 4e1e1e94 mov v20.h\[7\], w20
+ 162c: 4e1e1e94 mov v20.h\[7\], w20
+ 1630: 4e1e1eb5 mov v21.h\[7\], w21
+ 1634: 4e1e1eb5 mov v21.h\[7\], w21
+ 1638: 4e1e1ed6 mov v22.h\[7\], w22
+ 163c: 4e1e1ed6 mov v22.h\[7\], w22
+ 1640: 4e1e1ef7 mov v23.h\[7\], w23
+ 1644: 4e1e1ef7 mov v23.h\[7\], w23
+ 1648: 4e1e1f18 mov v24.h\[7\], w24
+ 164c: 4e1e1f18 mov v24.h\[7\], w24
+ 1650: 4e1e1f39 mov v25.h\[7\], w25
+ 1654: 4e1e1f39 mov v25.h\[7\], w25
+ 1658: 4e1e1f5a mov v26.h\[7\], w26
+ 165c: 4e1e1f5a mov v26.h\[7\], w26
+ 1660: 4e1e1f7b mov v27.h\[7\], w27
+ 1664: 4e1e1f7b mov v27.h\[7\], w27
+ 1668: 4e1e1f9c mov v28.h\[7\], w28
+ 166c: 4e1e1f9c mov v28.h\[7\], w28
+ 1670: 4e1e1fbd mov v29.h\[7\], w29
+ 1674: 4e1e1fbd mov v29.h\[7\], w29
+ 1678: 4e1e1fde mov v30.h\[7\], w30
+ 167c: 4e1e1fde mov v30.h\[7\], w30
+ 1680: 4e041c21 mov v1.s\[0\], w1
+ 1684: 4e041c21 mov v1.s\[0\], w1
+ 1688: 4e041c42 mov v2.s\[0\], w2
+ 168c: 4e041c42 mov v2.s\[0\], w2
+ 1690: 4e041c63 mov v3.s\[0\], w3
+ 1694: 4e041c63 mov v3.s\[0\], w3
+ 1698: 4e041c84 mov v4.s\[0\], w4
+ 169c: 4e041c84 mov v4.s\[0\], w4
+ 16a0: 4e041ca5 mov v5.s\[0\], w5
+ 16a4: 4e041ca5 mov v5.s\[0\], w5
+ 16a8: 4e041cc6 mov v6.s\[0\], w6
+ 16ac: 4e041cc6 mov v6.s\[0\], w6
+ 16b0: 4e041ce7 mov v7.s\[0\], w7
+ 16b4: 4e041ce7 mov v7.s\[0\], w7
+ 16b8: 4e041d08 mov v8.s\[0\], w8
+ 16bc: 4e041d08 mov v8.s\[0\], w8
+ 16c0: 4e041d29 mov v9.s\[0\], w9
+ 16c4: 4e041d29 mov v9.s\[0\], w9
+ 16c8: 4e041d4a mov v10.s\[0\], w10
+ 16cc: 4e041d4a mov v10.s\[0\], w10
+ 16d0: 4e041d6b mov v11.s\[0\], w11
+ 16d4: 4e041d6b mov v11.s\[0\], w11
+ 16d8: 4e041d8c mov v12.s\[0\], w12
+ 16dc: 4e041d8c mov v12.s\[0\], w12
+ 16e0: 4e041dad mov v13.s\[0\], w13
+ 16e4: 4e041dad mov v13.s\[0\], w13
+ 16e8: 4e041dce mov v14.s\[0\], w14
+ 16ec: 4e041dce mov v14.s\[0\], w14
+ 16f0: 4e041def mov v15.s\[0\], w15
+ 16f4: 4e041def mov v15.s\[0\], w15
+ 16f8: 4e041e10 mov v16.s\[0\], w16
+ 16fc: 4e041e10 mov v16.s\[0\], w16
+ 1700: 4e041e31 mov v17.s\[0\], w17
+ 1704: 4e041e31 mov v17.s\[0\], w17
+ 1708: 4e041e52 mov v18.s\[0\], w18
+ 170c: 4e041e52 mov v18.s\[0\], w18
+ 1710: 4e041e73 mov v19.s\[0\], w19
+ 1714: 4e041e73 mov v19.s\[0\], w19
+ 1718: 4e041e94 mov v20.s\[0\], w20
+ 171c: 4e041e94 mov v20.s\[0\], w20
+ 1720: 4e041eb5 mov v21.s\[0\], w21
+ 1724: 4e041eb5 mov v21.s\[0\], w21
+ 1728: 4e041ed6 mov v22.s\[0\], w22
+ 172c: 4e041ed6 mov v22.s\[0\], w22
+ 1730: 4e041ef7 mov v23.s\[0\], w23
+ 1734: 4e041ef7 mov v23.s\[0\], w23
+ 1738: 4e041f18 mov v24.s\[0\], w24
+ 173c: 4e041f18 mov v24.s\[0\], w24
+ 1740: 4e041f39 mov v25.s\[0\], w25
+ 1744: 4e041f39 mov v25.s\[0\], w25
+ 1748: 4e041f5a mov v26.s\[0\], w26
+ 174c: 4e041f5a mov v26.s\[0\], w26
+ 1750: 4e041f7b mov v27.s\[0\], w27
+ 1754: 4e041f7b mov v27.s\[0\], w27
+ 1758: 4e041f9c mov v28.s\[0\], w28
+ 175c: 4e041f9c mov v28.s\[0\], w28
+ 1760: 4e041fbd mov v29.s\[0\], w29
+ 1764: 4e041fbd mov v29.s\[0\], w29
+ 1768: 4e041fde mov v30.s\[0\], w30
+ 176c: 4e041fde mov v30.s\[0\], w30
+ 1770: 4e0c1c21 mov v1.s\[1\], w1
+ 1774: 4e0c1c21 mov v1.s\[1\], w1
+ 1778: 4e0c1c42 mov v2.s\[1\], w2
+ 177c: 4e0c1c42 mov v2.s\[1\], w2
+ 1780: 4e0c1c63 mov v3.s\[1\], w3
+ 1784: 4e0c1c63 mov v3.s\[1\], w3
+ 1788: 4e0c1c84 mov v4.s\[1\], w4
+ 178c: 4e0c1c84 mov v4.s\[1\], w4
+ 1790: 4e0c1ca5 mov v5.s\[1\], w5
+ 1794: 4e0c1ca5 mov v5.s\[1\], w5
+ 1798: 4e0c1cc6 mov v6.s\[1\], w6
+ 179c: 4e0c1cc6 mov v6.s\[1\], w6
+ 17a0: 4e0c1ce7 mov v7.s\[1\], w7
+ 17a4: 4e0c1ce7 mov v7.s\[1\], w7
+ 17a8: 4e0c1d08 mov v8.s\[1\], w8
+ 17ac: 4e0c1d08 mov v8.s\[1\], w8
+ 17b0: 4e0c1d29 mov v9.s\[1\], w9
+ 17b4: 4e0c1d29 mov v9.s\[1\], w9
+ 17b8: 4e0c1d4a mov v10.s\[1\], w10
+ 17bc: 4e0c1d4a mov v10.s\[1\], w10
+ 17c0: 4e0c1d6b mov v11.s\[1\], w11
+ 17c4: 4e0c1d6b mov v11.s\[1\], w11
+ 17c8: 4e0c1d8c mov v12.s\[1\], w12
+ 17cc: 4e0c1d8c mov v12.s\[1\], w12
+ 17d0: 4e0c1dad mov v13.s\[1\], w13
+ 17d4: 4e0c1dad mov v13.s\[1\], w13
+ 17d8: 4e0c1dce mov v14.s\[1\], w14
+ 17dc: 4e0c1dce mov v14.s\[1\], w14
+ 17e0: 4e0c1def mov v15.s\[1\], w15
+ 17e4: 4e0c1def mov v15.s\[1\], w15
+ 17e8: 4e0c1e10 mov v16.s\[1\], w16
+ 17ec: 4e0c1e10 mov v16.s\[1\], w16
+ 17f0: 4e0c1e31 mov v17.s\[1\], w17
+ 17f4: 4e0c1e31 mov v17.s\[1\], w17
+ 17f8: 4e0c1e52 mov v18.s\[1\], w18
+ 17fc: 4e0c1e52 mov v18.s\[1\], w18
+ 1800: 4e0c1e73 mov v19.s\[1\], w19
+ 1804: 4e0c1e73 mov v19.s\[1\], w19
+ 1808: 4e0c1e94 mov v20.s\[1\], w20
+ 180c: 4e0c1e94 mov v20.s\[1\], w20
+ 1810: 4e0c1eb5 mov v21.s\[1\], w21
+ 1814: 4e0c1eb5 mov v21.s\[1\], w21
+ 1818: 4e0c1ed6 mov v22.s\[1\], w22
+ 181c: 4e0c1ed6 mov v22.s\[1\], w22
+ 1820: 4e0c1ef7 mov v23.s\[1\], w23
+ 1824: 4e0c1ef7 mov v23.s\[1\], w23
+ 1828: 4e0c1f18 mov v24.s\[1\], w24
+ 182c: 4e0c1f18 mov v24.s\[1\], w24
+ 1830: 4e0c1f39 mov v25.s\[1\], w25
+ 1834: 4e0c1f39 mov v25.s\[1\], w25
+ 1838: 4e0c1f5a mov v26.s\[1\], w26
+ 183c: 4e0c1f5a mov v26.s\[1\], w26
+ 1840: 4e0c1f7b mov v27.s\[1\], w27
+ 1844: 4e0c1f7b mov v27.s\[1\], w27
+ 1848: 4e0c1f9c mov v28.s\[1\], w28
+ 184c: 4e0c1f9c mov v28.s\[1\], w28
+ 1850: 4e0c1fbd mov v29.s\[1\], w29
+ 1854: 4e0c1fbd mov v29.s\[1\], w29
+ 1858: 4e0c1fde mov v30.s\[1\], w30
+ 185c: 4e0c1fde mov v30.s\[1\], w30
+ 1860: 4e141c21 mov v1.s\[2\], w1
+ 1864: 4e141c21 mov v1.s\[2\], w1
+ 1868: 4e141c42 mov v2.s\[2\], w2
+ 186c: 4e141c42 mov v2.s\[2\], w2
+ 1870: 4e141c63 mov v3.s\[2\], w3
+ 1874: 4e141c63 mov v3.s\[2\], w3
+ 1878: 4e141c84 mov v4.s\[2\], w4
+ 187c: 4e141c84 mov v4.s\[2\], w4
+ 1880: 4e141ca5 mov v5.s\[2\], w5
+ 1884: 4e141ca5 mov v5.s\[2\], w5
+ 1888: 4e141cc6 mov v6.s\[2\], w6
+ 188c: 4e141cc6 mov v6.s\[2\], w6
+ 1890: 4e141ce7 mov v7.s\[2\], w7
+ 1894: 4e141ce7 mov v7.s\[2\], w7
+ 1898: 4e141d08 mov v8.s\[2\], w8
+ 189c: 4e141d08 mov v8.s\[2\], w8
+ 18a0: 4e141d29 mov v9.s\[2\], w9
+ 18a4: 4e141d29 mov v9.s\[2\], w9
+ 18a8: 4e141d4a mov v10.s\[2\], w10
+ 18ac: 4e141d4a mov v10.s\[2\], w10
+ 18b0: 4e141d6b mov v11.s\[2\], w11
+ 18b4: 4e141d6b mov v11.s\[2\], w11
+ 18b8: 4e141d8c mov v12.s\[2\], w12
+ 18bc: 4e141d8c mov v12.s\[2\], w12
+ 18c0: 4e141dad mov v13.s\[2\], w13
+ 18c4: 4e141dad mov v13.s\[2\], w13
+ 18c8: 4e141dce mov v14.s\[2\], w14
+ 18cc: 4e141dce mov v14.s\[2\], w14
+ 18d0: 4e141def mov v15.s\[2\], w15
+ 18d4: 4e141def mov v15.s\[2\], w15
+ 18d8: 4e141e10 mov v16.s\[2\], w16
+ 18dc: 4e141e10 mov v16.s\[2\], w16
+ 18e0: 4e141e31 mov v17.s\[2\], w17
+ 18e4: 4e141e31 mov v17.s\[2\], w17
+ 18e8: 4e141e52 mov v18.s\[2\], w18
+ 18ec: 4e141e52 mov v18.s\[2\], w18
+ 18f0: 4e141e73 mov v19.s\[2\], w19
+ 18f4: 4e141e73 mov v19.s\[2\], w19
+ 18f8: 4e141e94 mov v20.s\[2\], w20
+ 18fc: 4e141e94 mov v20.s\[2\], w20
+ 1900: 4e141eb5 mov v21.s\[2\], w21
+ 1904: 4e141eb5 mov v21.s\[2\], w21
+ 1908: 4e141ed6 mov v22.s\[2\], w22
+ 190c: 4e141ed6 mov v22.s\[2\], w22
+ 1910: 4e141ef7 mov v23.s\[2\], w23
+ 1914: 4e141ef7 mov v23.s\[2\], w23
+ 1918: 4e141f18 mov v24.s\[2\], w24
+ 191c: 4e141f18 mov v24.s\[2\], w24
+ 1920: 4e141f39 mov v25.s\[2\], w25
+ 1924: 4e141f39 mov v25.s\[2\], w25
+ 1928: 4e141f5a mov v26.s\[2\], w26
+ 192c: 4e141f5a mov v26.s\[2\], w26
+ 1930: 4e141f7b mov v27.s\[2\], w27
+ 1934: 4e141f7b mov v27.s\[2\], w27
+ 1938: 4e141f9c mov v28.s\[2\], w28
+ 193c: 4e141f9c mov v28.s\[2\], w28
+ 1940: 4e141fbd mov v29.s\[2\], w29
+ 1944: 4e141fbd mov v29.s\[2\], w29
+ 1948: 4e141fde mov v30.s\[2\], w30
+ 194c: 4e141fde mov v30.s\[2\], w30
+ 1950: 4e1c1c21 mov v1.s\[3\], w1
+ 1954: 4e1c1c21 mov v1.s\[3\], w1
+ 1958: 4e1c1c42 mov v2.s\[3\], w2
+ 195c: 4e1c1c42 mov v2.s\[3\], w2
+ 1960: 4e1c1c63 mov v3.s\[3\], w3
+ 1964: 4e1c1c63 mov v3.s\[3\], w3
+ 1968: 4e1c1c84 mov v4.s\[3\], w4
+ 196c: 4e1c1c84 mov v4.s\[3\], w4
+ 1970: 4e1c1ca5 mov v5.s\[3\], w5
+ 1974: 4e1c1ca5 mov v5.s\[3\], w5
+ 1978: 4e1c1cc6 mov v6.s\[3\], w6
+ 197c: 4e1c1cc6 mov v6.s\[3\], w6
+ 1980: 4e1c1ce7 mov v7.s\[3\], w7
+ 1984: 4e1c1ce7 mov v7.s\[3\], w7
+ 1988: 4e1c1d08 mov v8.s\[3\], w8
+ 198c: 4e1c1d08 mov v8.s\[3\], w8
+ 1990: 4e1c1d29 mov v9.s\[3\], w9
+ 1994: 4e1c1d29 mov v9.s\[3\], w9
+ 1998: 4e1c1d4a mov v10.s\[3\], w10
+ 199c: 4e1c1d4a mov v10.s\[3\], w10
+ 19a0: 4e1c1d6b mov v11.s\[3\], w11
+ 19a4: 4e1c1d6b mov v11.s\[3\], w11
+ 19a8: 4e1c1d8c mov v12.s\[3\], w12
+ 19ac: 4e1c1d8c mov v12.s\[3\], w12
+ 19b0: 4e1c1dad mov v13.s\[3\], w13
+ 19b4: 4e1c1dad mov v13.s\[3\], w13
+ 19b8: 4e1c1dce mov v14.s\[3\], w14
+ 19bc: 4e1c1dce mov v14.s\[3\], w14
+ 19c0: 4e1c1def mov v15.s\[3\], w15
+ 19c4: 4e1c1def mov v15.s\[3\], w15
+ 19c8: 4e1c1e10 mov v16.s\[3\], w16
+ 19cc: 4e1c1e10 mov v16.s\[3\], w16
+ 19d0: 4e1c1e31 mov v17.s\[3\], w17
+ 19d4: 4e1c1e31 mov v17.s\[3\], w17
+ 19d8: 4e1c1e52 mov v18.s\[3\], w18
+ 19dc: 4e1c1e52 mov v18.s\[3\], w18
+ 19e0: 4e1c1e73 mov v19.s\[3\], w19
+ 19e4: 4e1c1e73 mov v19.s\[3\], w19
+ 19e8: 4e1c1e94 mov v20.s\[3\], w20
+ 19ec: 4e1c1e94 mov v20.s\[3\], w20
+ 19f0: 4e1c1eb5 mov v21.s\[3\], w21
+ 19f4: 4e1c1eb5 mov v21.s\[3\], w21
+ 19f8: 4e1c1ed6 mov v22.s\[3\], w22
+ 19fc: 4e1c1ed6 mov v22.s\[3\], w22
+ 1a00: 4e1c1ef7 mov v23.s\[3\], w23
+ 1a04: 4e1c1ef7 mov v23.s\[3\], w23
+ 1a08: 4e1c1f18 mov v24.s\[3\], w24
+ 1a0c: 4e1c1f18 mov v24.s\[3\], w24
+ 1a10: 4e1c1f39 mov v25.s\[3\], w25
+ 1a14: 4e1c1f39 mov v25.s\[3\], w25
+ 1a18: 4e1c1f5a mov v26.s\[3\], w26
+ 1a1c: 4e1c1f5a mov v26.s\[3\], w26
+ 1a20: 4e1c1f7b mov v27.s\[3\], w27
+ 1a24: 4e1c1f7b mov v27.s\[3\], w27
+ 1a28: 4e1c1f9c mov v28.s\[3\], w28
+ 1a2c: 4e1c1f9c mov v28.s\[3\], w28
+ 1a30: 4e1c1fbd mov v29.s\[3\], w29
+ 1a34: 4e1c1fbd mov v29.s\[3\], w29
+ 1a38: 4e1c1fde mov v30.s\[3\], w30
+ 1a3c: 4e1c1fde mov v30.s\[3\], w30
+ 1a40: 6e010421 mov v1.b\[0\], v1.b\[0\]
+ 1a44: 6e010421 mov v1.b\[0\], v1.b\[0\]
+ 1a48: 6e010442 mov v2.b\[0\], v2.b\[0\]
+ 1a4c: 6e010442 mov v2.b\[0\], v2.b\[0\]
+ 1a50: 6e010463 mov v3.b\[0\], v3.b\[0\]
+ 1a54: 6e010463 mov v3.b\[0\], v3.b\[0\]
+ 1a58: 6e010484 mov v4.b\[0\], v4.b\[0\]
+ 1a5c: 6e010484 mov v4.b\[0\], v4.b\[0\]
+ 1a60: 6e0104a5 mov v5.b\[0\], v5.b\[0\]
+ 1a64: 6e0104a5 mov v5.b\[0\], v5.b\[0\]
+ 1a68: 6e0104c6 mov v6.b\[0\], v6.b\[0\]
+ 1a6c: 6e0104c6 mov v6.b\[0\], v6.b\[0\]
+ 1a70: 6e0104e7 mov v7.b\[0\], v7.b\[0\]
+ 1a74: 6e0104e7 mov v7.b\[0\], v7.b\[0\]
+ 1a78: 6e010508 mov v8.b\[0\], v8.b\[0\]
+ 1a7c: 6e010508 mov v8.b\[0\], v8.b\[0\]
+ 1a80: 6e010529 mov v9.b\[0\], v9.b\[0\]
+ 1a84: 6e010529 mov v9.b\[0\], v9.b\[0\]
+ 1a88: 6e01054a mov v10.b\[0\], v10.b\[0\]
+ 1a8c: 6e01054a mov v10.b\[0\], v10.b\[0\]
+ 1a90: 6e01056b mov v11.b\[0\], v11.b\[0\]
+ 1a94: 6e01056b mov v11.b\[0\], v11.b\[0\]
+ 1a98: 6e01058c mov v12.b\[0\], v12.b\[0\]
+ 1a9c: 6e01058c mov v12.b\[0\], v12.b\[0\]
+ 1aa0: 6e0105ad mov v13.b\[0\], v13.b\[0\]
+ 1aa4: 6e0105ad mov v13.b\[0\], v13.b\[0\]
+ 1aa8: 6e0105ce mov v14.b\[0\], v14.b\[0\]
+ 1aac: 6e0105ce mov v14.b\[0\], v14.b\[0\]
+ 1ab0: 6e0105ef mov v15.b\[0\], v15.b\[0\]
+ 1ab4: 6e0105ef mov v15.b\[0\], v15.b\[0\]
+ 1ab8: 6e010610 mov v16.b\[0\], v16.b\[0\]
+ 1abc: 6e010610 mov v16.b\[0\], v16.b\[0\]
+ 1ac0: 6e010631 mov v17.b\[0\], v17.b\[0\]
+ 1ac4: 6e010631 mov v17.b\[0\], v17.b\[0\]
+ 1ac8: 6e010652 mov v18.b\[0\], v18.b\[0\]
+ 1acc: 6e010652 mov v18.b\[0\], v18.b\[0\]
+ 1ad0: 6e010673 mov v19.b\[0\], v19.b\[0\]
+ 1ad4: 6e010673 mov v19.b\[0\], v19.b\[0\]
+ 1ad8: 6e010694 mov v20.b\[0\], v20.b\[0\]
+ 1adc: 6e010694 mov v20.b\[0\], v20.b\[0\]
+ 1ae0: 6e0106b5 mov v21.b\[0\], v21.b\[0\]
+ 1ae4: 6e0106b5 mov v21.b\[0\], v21.b\[0\]
+ 1ae8: 6e0106d6 mov v22.b\[0\], v22.b\[0\]
+ 1aec: 6e0106d6 mov v22.b\[0\], v22.b\[0\]
+ 1af0: 6e0106f7 mov v23.b\[0\], v23.b\[0\]
+ 1af4: 6e0106f7 mov v23.b\[0\], v23.b\[0\]
+ 1af8: 6e010718 mov v24.b\[0\], v24.b\[0\]
+ 1afc: 6e010718 mov v24.b\[0\], v24.b\[0\]
+ 1b00: 6e010739 mov v25.b\[0\], v25.b\[0\]
+ 1b04: 6e010739 mov v25.b\[0\], v25.b\[0\]
+ 1b08: 6e01075a mov v26.b\[0\], v26.b\[0\]
+ 1b0c: 6e01075a mov v26.b\[0\], v26.b\[0\]
+ 1b10: 6e01077b mov v27.b\[0\], v27.b\[0\]
+ 1b14: 6e01077b mov v27.b\[0\], v27.b\[0\]
+ 1b18: 6e01079c mov v28.b\[0\], v28.b\[0\]
+ 1b1c: 6e01079c mov v28.b\[0\], v28.b\[0\]
+ 1b20: 6e0107bd mov v29.b\[0\], v29.b\[0\]
+ 1b24: 6e0107bd mov v29.b\[0\], v29.b\[0\]
+ 1b28: 6e0107de mov v30.b\[0\], v30.b\[0\]
+ 1b2c: 6e0107de mov v30.b\[0\], v30.b\[0\]
+ 1b30: 6e030c21 mov v1.b\[1\], v1.b\[1\]
+ 1b34: 6e030c21 mov v1.b\[1\], v1.b\[1\]
+ 1b38: 6e030c42 mov v2.b\[1\], v2.b\[1\]
+ 1b3c: 6e030c42 mov v2.b\[1\], v2.b\[1\]
+ 1b40: 6e030c63 mov v3.b\[1\], v3.b\[1\]
+ 1b44: 6e030c63 mov v3.b\[1\], v3.b\[1\]
+ 1b48: 6e030c84 mov v4.b\[1\], v4.b\[1\]
+ 1b4c: 6e030c84 mov v4.b\[1\], v4.b\[1\]
+ 1b50: 6e030ca5 mov v5.b\[1\], v5.b\[1\]
+ 1b54: 6e030ca5 mov v5.b\[1\], v5.b\[1\]
+ 1b58: 6e030cc6 mov v6.b\[1\], v6.b\[1\]
+ 1b5c: 6e030cc6 mov v6.b\[1\], v6.b\[1\]
+ 1b60: 6e030ce7 mov v7.b\[1\], v7.b\[1\]
+ 1b64: 6e030ce7 mov v7.b\[1\], v7.b\[1\]
+ 1b68: 6e030d08 mov v8.b\[1\], v8.b\[1\]
+ 1b6c: 6e030d08 mov v8.b\[1\], v8.b\[1\]
+ 1b70: 6e030d29 mov v9.b\[1\], v9.b\[1\]
+ 1b74: 6e030d29 mov v9.b\[1\], v9.b\[1\]
+ 1b78: 6e030d4a mov v10.b\[1\], v10.b\[1\]
+ 1b7c: 6e030d4a mov v10.b\[1\], v10.b\[1\]
+ 1b80: 6e030d6b mov v11.b\[1\], v11.b\[1\]
+ 1b84: 6e030d6b mov v11.b\[1\], v11.b\[1\]
+ 1b88: 6e030d8c mov v12.b\[1\], v12.b\[1\]
+ 1b8c: 6e030d8c mov v12.b\[1\], v12.b\[1\]
+ 1b90: 6e030dad mov v13.b\[1\], v13.b\[1\]
+ 1b94: 6e030dad mov v13.b\[1\], v13.b\[1\]
+ 1b98: 6e030dce mov v14.b\[1\], v14.b\[1\]
+ 1b9c: 6e030dce mov v14.b\[1\], v14.b\[1\]
+ 1ba0: 6e030def mov v15.b\[1\], v15.b\[1\]
+ 1ba4: 6e030def mov v15.b\[1\], v15.b\[1\]
+ 1ba8: 6e030e10 mov v16.b\[1\], v16.b\[1\]
+ 1bac: 6e030e10 mov v16.b\[1\], v16.b\[1\]
+ 1bb0: 6e030e31 mov v17.b\[1\], v17.b\[1\]
+ 1bb4: 6e030e31 mov v17.b\[1\], v17.b\[1\]
+ 1bb8: 6e030e52 mov v18.b\[1\], v18.b\[1\]
+ 1bbc: 6e030e52 mov v18.b\[1\], v18.b\[1\]
+ 1bc0: 6e030e73 mov v19.b\[1\], v19.b\[1\]
+ 1bc4: 6e030e73 mov v19.b\[1\], v19.b\[1\]
+ 1bc8: 6e030e94 mov v20.b\[1\], v20.b\[1\]
+ 1bcc: 6e030e94 mov v20.b\[1\], v20.b\[1\]
+ 1bd0: 6e030eb5 mov v21.b\[1\], v21.b\[1\]
+ 1bd4: 6e030eb5 mov v21.b\[1\], v21.b\[1\]
+ 1bd8: 6e030ed6 mov v22.b\[1\], v22.b\[1\]
+ 1bdc: 6e030ed6 mov v22.b\[1\], v22.b\[1\]
+ 1be0: 6e030ef7 mov v23.b\[1\], v23.b\[1\]
+ 1be4: 6e030ef7 mov v23.b\[1\], v23.b\[1\]
+ 1be8: 6e030f18 mov v24.b\[1\], v24.b\[1\]
+ 1bec: 6e030f18 mov v24.b\[1\], v24.b\[1\]
+ 1bf0: 6e030f39 mov v25.b\[1\], v25.b\[1\]
+ 1bf4: 6e030f39 mov v25.b\[1\], v25.b\[1\]
+ 1bf8: 6e030f5a mov v26.b\[1\], v26.b\[1\]
+ 1bfc: 6e030f5a mov v26.b\[1\], v26.b\[1\]
+ 1c00: 6e030f7b mov v27.b\[1\], v27.b\[1\]
+ 1c04: 6e030f7b mov v27.b\[1\], v27.b\[1\]
+ 1c08: 6e030f9c mov v28.b\[1\], v28.b\[1\]
+ 1c0c: 6e030f9c mov v28.b\[1\], v28.b\[1\]
+ 1c10: 6e030fbd mov v29.b\[1\], v29.b\[1\]
+ 1c14: 6e030fbd mov v29.b\[1\], v29.b\[1\]
+ 1c18: 6e030fde mov v30.b\[1\], v30.b\[1\]
+ 1c1c: 6e030fde mov v30.b\[1\], v30.b\[1\]
+ 1c20: 6e051421 mov v1.b\[2\], v1.b\[2\]
+ 1c24: 6e051421 mov v1.b\[2\], v1.b\[2\]
+ 1c28: 6e051442 mov v2.b\[2\], v2.b\[2\]
+ 1c2c: 6e051442 mov v2.b\[2\], v2.b\[2\]
+ 1c30: 6e051463 mov v3.b\[2\], v3.b\[2\]
+ 1c34: 6e051463 mov v3.b\[2\], v3.b\[2\]
+ 1c38: 6e051484 mov v4.b\[2\], v4.b\[2\]
+ 1c3c: 6e051484 mov v4.b\[2\], v4.b\[2\]
+ 1c40: 6e0514a5 mov v5.b\[2\], v5.b\[2\]
+ 1c44: 6e0514a5 mov v5.b\[2\], v5.b\[2\]
+ 1c48: 6e0514c6 mov v6.b\[2\], v6.b\[2\]
+ 1c4c: 6e0514c6 mov v6.b\[2\], v6.b\[2\]
+ 1c50: 6e0514e7 mov v7.b\[2\], v7.b\[2\]
+ 1c54: 6e0514e7 mov v7.b\[2\], v7.b\[2\]
+ 1c58: 6e051508 mov v8.b\[2\], v8.b\[2\]
+ 1c5c: 6e051508 mov v8.b\[2\], v8.b\[2\]
+ 1c60: 6e051529 mov v9.b\[2\], v9.b\[2\]
+ 1c64: 6e051529 mov v9.b\[2\], v9.b\[2\]
+ 1c68: 6e05154a mov v10.b\[2\], v10.b\[2\]
+ 1c6c: 6e05154a mov v10.b\[2\], v10.b\[2\]
+ 1c70: 6e05156b mov v11.b\[2\], v11.b\[2\]
+ 1c74: 6e05156b mov v11.b\[2\], v11.b\[2\]
+ 1c78: 6e05158c mov v12.b\[2\], v12.b\[2\]
+ 1c7c: 6e05158c mov v12.b\[2\], v12.b\[2\]
+ 1c80: 6e0515ad mov v13.b\[2\], v13.b\[2\]
+ 1c84: 6e0515ad mov v13.b\[2\], v13.b\[2\]
+ 1c88: 6e0515ce mov v14.b\[2\], v14.b\[2\]
+ 1c8c: 6e0515ce mov v14.b\[2\], v14.b\[2\]
+ 1c90: 6e0515ef mov v15.b\[2\], v15.b\[2\]
+ 1c94: 6e0515ef mov v15.b\[2\], v15.b\[2\]
+ 1c98: 6e051610 mov v16.b\[2\], v16.b\[2\]
+ 1c9c: 6e051610 mov v16.b\[2\], v16.b\[2\]
+ 1ca0: 6e051631 mov v17.b\[2\], v17.b\[2\]
+ 1ca4: 6e051631 mov v17.b\[2\], v17.b\[2\]
+ 1ca8: 6e051652 mov v18.b\[2\], v18.b\[2\]
+ 1cac: 6e051652 mov v18.b\[2\], v18.b\[2\]
+ 1cb0: 6e051673 mov v19.b\[2\], v19.b\[2\]
+ 1cb4: 6e051673 mov v19.b\[2\], v19.b\[2\]
+ 1cb8: 6e051694 mov v20.b\[2\], v20.b\[2\]
+ 1cbc: 6e051694 mov v20.b\[2\], v20.b\[2\]
+ 1cc0: 6e0516b5 mov v21.b\[2\], v21.b\[2\]
+ 1cc4: 6e0516b5 mov v21.b\[2\], v21.b\[2\]
+ 1cc8: 6e0516d6 mov v22.b\[2\], v22.b\[2\]
+ 1ccc: 6e0516d6 mov v22.b\[2\], v22.b\[2\]
+ 1cd0: 6e0516f7 mov v23.b\[2\], v23.b\[2\]
+ 1cd4: 6e0516f7 mov v23.b\[2\], v23.b\[2\]
+ 1cd8: 6e051718 mov v24.b\[2\], v24.b\[2\]
+ 1cdc: 6e051718 mov v24.b\[2\], v24.b\[2\]
+ 1ce0: 6e051739 mov v25.b\[2\], v25.b\[2\]
+ 1ce4: 6e051739 mov v25.b\[2\], v25.b\[2\]
+ 1ce8: 6e05175a mov v26.b\[2\], v26.b\[2\]
+ 1cec: 6e05175a mov v26.b\[2\], v26.b\[2\]
+ 1cf0: 6e05177b mov v27.b\[2\], v27.b\[2\]
+ 1cf4: 6e05177b mov v27.b\[2\], v27.b\[2\]
+ 1cf8: 6e05179c mov v28.b\[2\], v28.b\[2\]
+ 1cfc: 6e05179c mov v28.b\[2\], v28.b\[2\]
+ 1d00: 6e0517bd mov v29.b\[2\], v29.b\[2\]
+ 1d04: 6e0517bd mov v29.b\[2\], v29.b\[2\]
+ 1d08: 6e0517de mov v30.b\[2\], v30.b\[2\]
+ 1d0c: 6e0517de mov v30.b\[2\], v30.b\[2\]
+ 1d10: 6e071c21 mov v1.b\[3\], v1.b\[3\]
+ 1d14: 6e071c21 mov v1.b\[3\], v1.b\[3\]
+ 1d18: 6e071c42 mov v2.b\[3\], v2.b\[3\]
+ 1d1c: 6e071c42 mov v2.b\[3\], v2.b\[3\]
+ 1d20: 6e071c63 mov v3.b\[3\], v3.b\[3\]
+ 1d24: 6e071c63 mov v3.b\[3\], v3.b\[3\]
+ 1d28: 6e071c84 mov v4.b\[3\], v4.b\[3\]
+ 1d2c: 6e071c84 mov v4.b\[3\], v4.b\[3\]
+ 1d30: 6e071ca5 mov v5.b\[3\], v5.b\[3\]
+ 1d34: 6e071ca5 mov v5.b\[3\], v5.b\[3\]
+ 1d38: 6e071cc6 mov v6.b\[3\], v6.b\[3\]
+ 1d3c: 6e071cc6 mov v6.b\[3\], v6.b\[3\]
+ 1d40: 6e071ce7 mov v7.b\[3\], v7.b\[3\]
+ 1d44: 6e071ce7 mov v7.b\[3\], v7.b\[3\]
+ 1d48: 6e071d08 mov v8.b\[3\], v8.b\[3\]
+ 1d4c: 6e071d08 mov v8.b\[3\], v8.b\[3\]
+ 1d50: 6e071d29 mov v9.b\[3\], v9.b\[3\]
+ 1d54: 6e071d29 mov v9.b\[3\], v9.b\[3\]
+ 1d58: 6e071d4a mov v10.b\[3\], v10.b\[3\]
+ 1d5c: 6e071d4a mov v10.b\[3\], v10.b\[3\]
+ 1d60: 6e071d6b mov v11.b\[3\], v11.b\[3\]
+ 1d64: 6e071d6b mov v11.b\[3\], v11.b\[3\]
+ 1d68: 6e071d8c mov v12.b\[3\], v12.b\[3\]
+ 1d6c: 6e071d8c mov v12.b\[3\], v12.b\[3\]
+ 1d70: 6e071dad mov v13.b\[3\], v13.b\[3\]
+ 1d74: 6e071dad mov v13.b\[3\], v13.b\[3\]
+ 1d78: 6e071dce mov v14.b\[3\], v14.b\[3\]
+ 1d7c: 6e071dce mov v14.b\[3\], v14.b\[3\]
+ 1d80: 6e071def mov v15.b\[3\], v15.b\[3\]
+ 1d84: 6e071def mov v15.b\[3\], v15.b\[3\]
+ 1d88: 6e071e10 mov v16.b\[3\], v16.b\[3\]
+ 1d8c: 6e071e10 mov v16.b\[3\], v16.b\[3\]
+ 1d90: 6e071e31 mov v17.b\[3\], v17.b\[3\]
+ 1d94: 6e071e31 mov v17.b\[3\], v17.b\[3\]
+ 1d98: 6e071e52 mov v18.b\[3\], v18.b\[3\]
+ 1d9c: 6e071e52 mov v18.b\[3\], v18.b\[3\]
+ 1da0: 6e071e73 mov v19.b\[3\], v19.b\[3\]
+ 1da4: 6e071e73 mov v19.b\[3\], v19.b\[3\]
+ 1da8: 6e071e94 mov v20.b\[3\], v20.b\[3\]
+ 1dac: 6e071e94 mov v20.b\[3\], v20.b\[3\]
+ 1db0: 6e071eb5 mov v21.b\[3\], v21.b\[3\]
+ 1db4: 6e071eb5 mov v21.b\[3\], v21.b\[3\]
+ 1db8: 6e071ed6 mov v22.b\[3\], v22.b\[3\]
+ 1dbc: 6e071ed6 mov v22.b\[3\], v22.b\[3\]
+ 1dc0: 6e071ef7 mov v23.b\[3\], v23.b\[3\]
+ 1dc4: 6e071ef7 mov v23.b\[3\], v23.b\[3\]
+ 1dc8: 6e071f18 mov v24.b\[3\], v24.b\[3\]
+ 1dcc: 6e071f18 mov v24.b\[3\], v24.b\[3\]
+ 1dd0: 6e071f39 mov v25.b\[3\], v25.b\[3\]
+ 1dd4: 6e071f39 mov v25.b\[3\], v25.b\[3\]
+ 1dd8: 6e071f5a mov v26.b\[3\], v26.b\[3\]
+ 1ddc: 6e071f5a mov v26.b\[3\], v26.b\[3\]
+ 1de0: 6e071f7b mov v27.b\[3\], v27.b\[3\]
+ 1de4: 6e071f7b mov v27.b\[3\], v27.b\[3\]
+ 1de8: 6e071f9c mov v28.b\[3\], v28.b\[3\]
+ 1dec: 6e071f9c mov v28.b\[3\], v28.b\[3\]
+ 1df0: 6e071fbd mov v29.b\[3\], v29.b\[3\]
+ 1df4: 6e071fbd mov v29.b\[3\], v29.b\[3\]
+ 1df8: 6e071fde mov v30.b\[3\], v30.b\[3\]
+ 1dfc: 6e071fde mov v30.b\[3\], v30.b\[3\]
+ 1e00: 6e092421 mov v1.b\[4\], v1.b\[4\]
+ 1e04: 6e092421 mov v1.b\[4\], v1.b\[4\]
+ 1e08: 6e092442 mov v2.b\[4\], v2.b\[4\]
+ 1e0c: 6e092442 mov v2.b\[4\], v2.b\[4\]
+ 1e10: 6e092463 mov v3.b\[4\], v3.b\[4\]
+ 1e14: 6e092463 mov v3.b\[4\], v3.b\[4\]
+ 1e18: 6e092484 mov v4.b\[4\], v4.b\[4\]
+ 1e1c: 6e092484 mov v4.b\[4\], v4.b\[4\]
+ 1e20: 6e0924a5 mov v5.b\[4\], v5.b\[4\]
+ 1e24: 6e0924a5 mov v5.b\[4\], v5.b\[4\]
+ 1e28: 6e0924c6 mov v6.b\[4\], v6.b\[4\]
+ 1e2c: 6e0924c6 mov v6.b\[4\], v6.b\[4\]
+ 1e30: 6e0924e7 mov v7.b\[4\], v7.b\[4\]
+ 1e34: 6e0924e7 mov v7.b\[4\], v7.b\[4\]
+ 1e38: 6e092508 mov v8.b\[4\], v8.b\[4\]
+ 1e3c: 6e092508 mov v8.b\[4\], v8.b\[4\]
+ 1e40: 6e092529 mov v9.b\[4\], v9.b\[4\]
+ 1e44: 6e092529 mov v9.b\[4\], v9.b\[4\]
+ 1e48: 6e09254a mov v10.b\[4\], v10.b\[4\]
+ 1e4c: 6e09254a mov v10.b\[4\], v10.b\[4\]
+ 1e50: 6e09256b mov v11.b\[4\], v11.b\[4\]
+ 1e54: 6e09256b mov v11.b\[4\], v11.b\[4\]
+ 1e58: 6e09258c mov v12.b\[4\], v12.b\[4\]
+ 1e5c: 6e09258c mov v12.b\[4\], v12.b\[4\]
+ 1e60: 6e0925ad mov v13.b\[4\], v13.b\[4\]
+ 1e64: 6e0925ad mov v13.b\[4\], v13.b\[4\]
+ 1e68: 6e0925ce mov v14.b\[4\], v14.b\[4\]
+ 1e6c: 6e0925ce mov v14.b\[4\], v14.b\[4\]
+ 1e70: 6e0925ef mov v15.b\[4\], v15.b\[4\]
+ 1e74: 6e0925ef mov v15.b\[4\], v15.b\[4\]
+ 1e78: 6e092610 mov v16.b\[4\], v16.b\[4\]
+ 1e7c: 6e092610 mov v16.b\[4\], v16.b\[4\]
+ 1e80: 6e092631 mov v17.b\[4\], v17.b\[4\]
+ 1e84: 6e092631 mov v17.b\[4\], v17.b\[4\]
+ 1e88: 6e092652 mov v18.b\[4\], v18.b\[4\]
+ 1e8c: 6e092652 mov v18.b\[4\], v18.b\[4\]
+ 1e90: 6e092673 mov v19.b\[4\], v19.b\[4\]
+ 1e94: 6e092673 mov v19.b\[4\], v19.b\[4\]
+ 1e98: 6e092694 mov v20.b\[4\], v20.b\[4\]
+ 1e9c: 6e092694 mov v20.b\[4\], v20.b\[4\]
+ 1ea0: 6e0926b5 mov v21.b\[4\], v21.b\[4\]
+ 1ea4: 6e0926b5 mov v21.b\[4\], v21.b\[4\]
+ 1ea8: 6e0926d6 mov v22.b\[4\], v22.b\[4\]
+ 1eac: 6e0926d6 mov v22.b\[4\], v22.b\[4\]
+ 1eb0: 6e0926f7 mov v23.b\[4\], v23.b\[4\]
+ 1eb4: 6e0926f7 mov v23.b\[4\], v23.b\[4\]
+ 1eb8: 6e092718 mov v24.b\[4\], v24.b\[4\]
+ 1ebc: 6e092718 mov v24.b\[4\], v24.b\[4\]
+ 1ec0: 6e092739 mov v25.b\[4\], v25.b\[4\]
+ 1ec4: 6e092739 mov v25.b\[4\], v25.b\[4\]
+ 1ec8: 6e09275a mov v26.b\[4\], v26.b\[4\]
+ 1ecc: 6e09275a mov v26.b\[4\], v26.b\[4\]
+ 1ed0: 6e09277b mov v27.b\[4\], v27.b\[4\]
+ 1ed4: 6e09277b mov v27.b\[4\], v27.b\[4\]
+ 1ed8: 6e09279c mov v28.b\[4\], v28.b\[4\]
+ 1edc: 6e09279c mov v28.b\[4\], v28.b\[4\]
+ 1ee0: 6e0927bd mov v29.b\[4\], v29.b\[4\]
+ 1ee4: 6e0927bd mov v29.b\[4\], v29.b\[4\]
+ 1ee8: 6e0927de mov v30.b\[4\], v30.b\[4\]
+ 1eec: 6e0927de mov v30.b\[4\], v30.b\[4\]
+ 1ef0: 6e0b2c21 mov v1.b\[5\], v1.b\[5\]
+ 1ef4: 6e0b2c21 mov v1.b\[5\], v1.b\[5\]
+ 1ef8: 6e0b2c42 mov v2.b\[5\], v2.b\[5\]
+ 1efc: 6e0b2c42 mov v2.b\[5\], v2.b\[5\]
+ 1f00: 6e0b2c63 mov v3.b\[5\], v3.b\[5\]
+ 1f04: 6e0b2c63 mov v3.b\[5\], v3.b\[5\]
+ 1f08: 6e0b2c84 mov v4.b\[5\], v4.b\[5\]
+ 1f0c: 6e0b2c84 mov v4.b\[5\], v4.b\[5\]
+ 1f10: 6e0b2ca5 mov v5.b\[5\], v5.b\[5\]
+ 1f14: 6e0b2ca5 mov v5.b\[5\], v5.b\[5\]
+ 1f18: 6e0b2cc6 mov v6.b\[5\], v6.b\[5\]
+ 1f1c: 6e0b2cc6 mov v6.b\[5\], v6.b\[5\]
+ 1f20: 6e0b2ce7 mov v7.b\[5\], v7.b\[5\]
+ 1f24: 6e0b2ce7 mov v7.b\[5\], v7.b\[5\]
+ 1f28: 6e0b2d08 mov v8.b\[5\], v8.b\[5\]
+ 1f2c: 6e0b2d08 mov v8.b\[5\], v8.b\[5\]
+ 1f30: 6e0b2d29 mov v9.b\[5\], v9.b\[5\]
+ 1f34: 6e0b2d29 mov v9.b\[5\], v9.b\[5\]
+ 1f38: 6e0b2d4a mov v10.b\[5\], v10.b\[5\]
+ 1f3c: 6e0b2d4a mov v10.b\[5\], v10.b\[5\]
+ 1f40: 6e0b2d6b mov v11.b\[5\], v11.b\[5\]
+ 1f44: 6e0b2d6b mov v11.b\[5\], v11.b\[5\]
+ 1f48: 6e0b2d8c mov v12.b\[5\], v12.b\[5\]
+ 1f4c: 6e0b2d8c mov v12.b\[5\], v12.b\[5\]
+ 1f50: 6e0b2dad mov v13.b\[5\], v13.b\[5\]
+ 1f54: 6e0b2dad mov v13.b\[5\], v13.b\[5\]
+ 1f58: 6e0b2dce mov v14.b\[5\], v14.b\[5\]
+ 1f5c: 6e0b2dce mov v14.b\[5\], v14.b\[5\]
+ 1f60: 6e0b2def mov v15.b\[5\], v15.b\[5\]
+ 1f64: 6e0b2def mov v15.b\[5\], v15.b\[5\]
+ 1f68: 6e0b2e10 mov v16.b\[5\], v16.b\[5\]
+ 1f6c: 6e0b2e10 mov v16.b\[5\], v16.b\[5\]
+ 1f70: 6e0b2e31 mov v17.b\[5\], v17.b\[5\]
+ 1f74: 6e0b2e31 mov v17.b\[5\], v17.b\[5\]
+ 1f78: 6e0b2e52 mov v18.b\[5\], v18.b\[5\]
+ 1f7c: 6e0b2e52 mov v18.b\[5\], v18.b\[5\]
+ 1f80: 6e0b2e73 mov v19.b\[5\], v19.b\[5\]
+ 1f84: 6e0b2e73 mov v19.b\[5\], v19.b\[5\]
+ 1f88: 6e0b2e94 mov v20.b\[5\], v20.b\[5\]
+ 1f8c: 6e0b2e94 mov v20.b\[5\], v20.b\[5\]
+ 1f90: 6e0b2eb5 mov v21.b\[5\], v21.b\[5\]
+ 1f94: 6e0b2eb5 mov v21.b\[5\], v21.b\[5\]
+ 1f98: 6e0b2ed6 mov v22.b\[5\], v22.b\[5\]
+ 1f9c: 6e0b2ed6 mov v22.b\[5\], v22.b\[5\]
+ 1fa0: 6e0b2ef7 mov v23.b\[5\], v23.b\[5\]
+ 1fa4: 6e0b2ef7 mov v23.b\[5\], v23.b\[5\]
+ 1fa8: 6e0b2f18 mov v24.b\[5\], v24.b\[5\]
+ 1fac: 6e0b2f18 mov v24.b\[5\], v24.b\[5\]
+ 1fb0: 6e0b2f39 mov v25.b\[5\], v25.b\[5\]
+ 1fb4: 6e0b2f39 mov v25.b\[5\], v25.b\[5\]
+ 1fb8: 6e0b2f5a mov v26.b\[5\], v26.b\[5\]
+ 1fbc: 6e0b2f5a mov v26.b\[5\], v26.b\[5\]
+ 1fc0: 6e0b2f7b mov v27.b\[5\], v27.b\[5\]
+ 1fc4: 6e0b2f7b mov v27.b\[5\], v27.b\[5\]
+ 1fc8: 6e0b2f9c mov v28.b\[5\], v28.b\[5\]
+ 1fcc: 6e0b2f9c mov v28.b\[5\], v28.b\[5\]
+ 1fd0: 6e0b2fbd mov v29.b\[5\], v29.b\[5\]
+ 1fd4: 6e0b2fbd mov v29.b\[5\], v29.b\[5\]
+ 1fd8: 6e0b2fde mov v30.b\[5\], v30.b\[5\]
+ 1fdc: 6e0b2fde mov v30.b\[5\], v30.b\[5\]
+ 1fe0: 6e0d3421 mov v1.b\[6\], v1.b\[6\]
+ 1fe4: 6e0d3421 mov v1.b\[6\], v1.b\[6\]
+ 1fe8: 6e0d3442 mov v2.b\[6\], v2.b\[6\]
+ 1fec: 6e0d3442 mov v2.b\[6\], v2.b\[6\]
+ 1ff0: 6e0d3463 mov v3.b\[6\], v3.b\[6\]
+ 1ff4: 6e0d3463 mov v3.b\[6\], v3.b\[6\]
+ 1ff8: 6e0d3484 mov v4.b\[6\], v4.b\[6\]
+ 1ffc: 6e0d3484 mov v4.b\[6\], v4.b\[6\]
+ 2000: 6e0d34a5 mov v5.b\[6\], v5.b\[6\]
+ 2004: 6e0d34a5 mov v5.b\[6\], v5.b\[6\]
+ 2008: 6e0d34c6 mov v6.b\[6\], v6.b\[6\]
+ 200c: 6e0d34c6 mov v6.b\[6\], v6.b\[6\]
+ 2010: 6e0d34e7 mov v7.b\[6\], v7.b\[6\]
+ 2014: 6e0d34e7 mov v7.b\[6\], v7.b\[6\]
+ 2018: 6e0d3508 mov v8.b\[6\], v8.b\[6\]
+ 201c: 6e0d3508 mov v8.b\[6\], v8.b\[6\]
+ 2020: 6e0d3529 mov v9.b\[6\], v9.b\[6\]
+ 2024: 6e0d3529 mov v9.b\[6\], v9.b\[6\]
+ 2028: 6e0d354a mov v10.b\[6\], v10.b\[6\]
+ 202c: 6e0d354a mov v10.b\[6\], v10.b\[6\]
+ 2030: 6e0d356b mov v11.b\[6\], v11.b\[6\]
+ 2034: 6e0d356b mov v11.b\[6\], v11.b\[6\]
+ 2038: 6e0d358c mov v12.b\[6\], v12.b\[6\]
+ 203c: 6e0d358c mov v12.b\[6\], v12.b\[6\]
+ 2040: 6e0d35ad mov v13.b\[6\], v13.b\[6\]
+ 2044: 6e0d35ad mov v13.b\[6\], v13.b\[6\]
+ 2048: 6e0d35ce mov v14.b\[6\], v14.b\[6\]
+ 204c: 6e0d35ce mov v14.b\[6\], v14.b\[6\]
+ 2050: 6e0d35ef mov v15.b\[6\], v15.b\[6\]
+ 2054: 6e0d35ef mov v15.b\[6\], v15.b\[6\]
+ 2058: 6e0d3610 mov v16.b\[6\], v16.b\[6\]
+ 205c: 6e0d3610 mov v16.b\[6\], v16.b\[6\]
+ 2060: 6e0d3631 mov v17.b\[6\], v17.b\[6\]
+ 2064: 6e0d3631 mov v17.b\[6\], v17.b\[6\]
+ 2068: 6e0d3652 mov v18.b\[6\], v18.b\[6\]
+ 206c: 6e0d3652 mov v18.b\[6\], v18.b\[6\]
+ 2070: 6e0d3673 mov v19.b\[6\], v19.b\[6\]
+ 2074: 6e0d3673 mov v19.b\[6\], v19.b\[6\]
+ 2078: 6e0d3694 mov v20.b\[6\], v20.b\[6\]
+ 207c: 6e0d3694 mov v20.b\[6\], v20.b\[6\]
+ 2080: 6e0d36b5 mov v21.b\[6\], v21.b\[6\]
+ 2084: 6e0d36b5 mov v21.b\[6\], v21.b\[6\]
+ 2088: 6e0d36d6 mov v22.b\[6\], v22.b\[6\]
+ 208c: 6e0d36d6 mov v22.b\[6\], v22.b\[6\]
+ 2090: 6e0d36f7 mov v23.b\[6\], v23.b\[6\]
+ 2094: 6e0d36f7 mov v23.b\[6\], v23.b\[6\]
+ 2098: 6e0d3718 mov v24.b\[6\], v24.b\[6\]
+ 209c: 6e0d3718 mov v24.b\[6\], v24.b\[6\]
+ 20a0: 6e0d3739 mov v25.b\[6\], v25.b\[6\]
+ 20a4: 6e0d3739 mov v25.b\[6\], v25.b\[6\]
+ 20a8: 6e0d375a mov v26.b\[6\], v26.b\[6\]
+ 20ac: 6e0d375a mov v26.b\[6\], v26.b\[6\]
+ 20b0: 6e0d377b mov v27.b\[6\], v27.b\[6\]
+ 20b4: 6e0d377b mov v27.b\[6\], v27.b\[6\]
+ 20b8: 6e0d379c mov v28.b\[6\], v28.b\[6\]
+ 20bc: 6e0d379c mov v28.b\[6\], v28.b\[6\]
+ 20c0: 6e0d37bd mov v29.b\[6\], v29.b\[6\]
+ 20c4: 6e0d37bd mov v29.b\[6\], v29.b\[6\]
+ 20c8: 6e0d37de mov v30.b\[6\], v30.b\[6\]
+ 20cc: 6e0d37de mov v30.b\[6\], v30.b\[6\]
+ 20d0: 6e0f3c21 mov v1.b\[7\], v1.b\[7\]
+ 20d4: 6e0f3c21 mov v1.b\[7\], v1.b\[7\]
+ 20d8: 6e0f3c42 mov v2.b\[7\], v2.b\[7\]
+ 20dc: 6e0f3c42 mov v2.b\[7\], v2.b\[7\]
+ 20e0: 6e0f3c63 mov v3.b\[7\], v3.b\[7\]
+ 20e4: 6e0f3c63 mov v3.b\[7\], v3.b\[7\]
+ 20e8: 6e0f3c84 mov v4.b\[7\], v4.b\[7\]
+ 20ec: 6e0f3c84 mov v4.b\[7\], v4.b\[7\]
+ 20f0: 6e0f3ca5 mov v5.b\[7\], v5.b\[7\]
+ 20f4: 6e0f3ca5 mov v5.b\[7\], v5.b\[7\]
+ 20f8: 6e0f3cc6 mov v6.b\[7\], v6.b\[7\]
+ 20fc: 6e0f3cc6 mov v6.b\[7\], v6.b\[7\]
+ 2100: 6e0f3ce7 mov v7.b\[7\], v7.b\[7\]
+ 2104: 6e0f3ce7 mov v7.b\[7\], v7.b\[7\]
+ 2108: 6e0f3d08 mov v8.b\[7\], v8.b\[7\]
+ 210c: 6e0f3d08 mov v8.b\[7\], v8.b\[7\]
+ 2110: 6e0f3d29 mov v9.b\[7\], v9.b\[7\]
+ 2114: 6e0f3d29 mov v9.b\[7\], v9.b\[7\]
+ 2118: 6e0f3d4a mov v10.b\[7\], v10.b\[7\]
+ 211c: 6e0f3d4a mov v10.b\[7\], v10.b\[7\]
+ 2120: 6e0f3d6b mov v11.b\[7\], v11.b\[7\]
+ 2124: 6e0f3d6b mov v11.b\[7\], v11.b\[7\]
+ 2128: 6e0f3d8c mov v12.b\[7\], v12.b\[7\]
+ 212c: 6e0f3d8c mov v12.b\[7\], v12.b\[7\]
+ 2130: 6e0f3dad mov v13.b\[7\], v13.b\[7\]
+ 2134: 6e0f3dad mov v13.b\[7\], v13.b\[7\]
+ 2138: 6e0f3dce mov v14.b\[7\], v14.b\[7\]
+ 213c: 6e0f3dce mov v14.b\[7\], v14.b\[7\]
+ 2140: 6e0f3def mov v15.b\[7\], v15.b\[7\]
+ 2144: 6e0f3def mov v15.b\[7\], v15.b\[7\]
+ 2148: 6e0f3e10 mov v16.b\[7\], v16.b\[7\]
+ 214c: 6e0f3e10 mov v16.b\[7\], v16.b\[7\]
+ 2150: 6e0f3e31 mov v17.b\[7\], v17.b\[7\]
+ 2154: 6e0f3e31 mov v17.b\[7\], v17.b\[7\]
+ 2158: 6e0f3e52 mov v18.b\[7\], v18.b\[7\]
+ 215c: 6e0f3e52 mov v18.b\[7\], v18.b\[7\]
+ 2160: 6e0f3e73 mov v19.b\[7\], v19.b\[7\]
+ 2164: 6e0f3e73 mov v19.b\[7\], v19.b\[7\]
+ 2168: 6e0f3e94 mov v20.b\[7\], v20.b\[7\]
+ 216c: 6e0f3e94 mov v20.b\[7\], v20.b\[7\]
+ 2170: 6e0f3eb5 mov v21.b\[7\], v21.b\[7\]
+ 2174: 6e0f3eb5 mov v21.b\[7\], v21.b\[7\]
+ 2178: 6e0f3ed6 mov v22.b\[7\], v22.b\[7\]
+ 217c: 6e0f3ed6 mov v22.b\[7\], v22.b\[7\]
+ 2180: 6e0f3ef7 mov v23.b\[7\], v23.b\[7\]
+ 2184: 6e0f3ef7 mov v23.b\[7\], v23.b\[7\]
+ 2188: 6e0f3f18 mov v24.b\[7\], v24.b\[7\]
+ 218c: 6e0f3f18 mov v24.b\[7\], v24.b\[7\]
+ 2190: 6e0f3f39 mov v25.b\[7\], v25.b\[7\]
+ 2194: 6e0f3f39 mov v25.b\[7\], v25.b\[7\]
+ 2198: 6e0f3f5a mov v26.b\[7\], v26.b\[7\]
+ 219c: 6e0f3f5a mov v26.b\[7\], v26.b\[7\]
+ 21a0: 6e0f3f7b mov v27.b\[7\], v27.b\[7\]
+ 21a4: 6e0f3f7b mov v27.b\[7\], v27.b\[7\]
+ 21a8: 6e0f3f9c mov v28.b\[7\], v28.b\[7\]
+ 21ac: 6e0f3f9c mov v28.b\[7\], v28.b\[7\]
+ 21b0: 6e0f3fbd mov v29.b\[7\], v29.b\[7\]
+ 21b4: 6e0f3fbd mov v29.b\[7\], v29.b\[7\]
+ 21b8: 6e0f3fde mov v30.b\[7\], v30.b\[7\]
+ 21bc: 6e0f3fde mov v30.b\[7\], v30.b\[7\]
+ 21c0: 6e114421 mov v1.b\[8\], v1.b\[8\]
+ 21c4: 6e114421 mov v1.b\[8\], v1.b\[8\]
+ 21c8: 6e114442 mov v2.b\[8\], v2.b\[8\]
+ 21cc: 6e114442 mov v2.b\[8\], v2.b\[8\]
+ 21d0: 6e114463 mov v3.b\[8\], v3.b\[8\]
+ 21d4: 6e114463 mov v3.b\[8\], v3.b\[8\]
+ 21d8: 6e114484 mov v4.b\[8\], v4.b\[8\]
+ 21dc: 6e114484 mov v4.b\[8\], v4.b\[8\]
+ 21e0: 6e1144a5 mov v5.b\[8\], v5.b\[8\]
+ 21e4: 6e1144a5 mov v5.b\[8\], v5.b\[8\]
+ 21e8: 6e1144c6 mov v6.b\[8\], v6.b\[8\]
+ 21ec: 6e1144c6 mov v6.b\[8\], v6.b\[8\]
+ 21f0: 6e1144e7 mov v7.b\[8\], v7.b\[8\]
+ 21f4: 6e1144e7 mov v7.b\[8\], v7.b\[8\]
+ 21f8: 6e114508 mov v8.b\[8\], v8.b\[8\]
+ 21fc: 6e114508 mov v8.b\[8\], v8.b\[8\]
+ 2200: 6e114529 mov v9.b\[8\], v9.b\[8\]
+ 2204: 6e114529 mov v9.b\[8\], v9.b\[8\]
+ 2208: 6e11454a mov v10.b\[8\], v10.b\[8\]
+ 220c: 6e11454a mov v10.b\[8\], v10.b\[8\]
+ 2210: 6e11456b mov v11.b\[8\], v11.b\[8\]
+ 2214: 6e11456b mov v11.b\[8\], v11.b\[8\]
+ 2218: 6e11458c mov v12.b\[8\], v12.b\[8\]
+ 221c: 6e11458c mov v12.b\[8\], v12.b\[8\]
+ 2220: 6e1145ad mov v13.b\[8\], v13.b\[8\]
+ 2224: 6e1145ad mov v13.b\[8\], v13.b\[8\]
+ 2228: 6e1145ce mov v14.b\[8\], v14.b\[8\]
+ 222c: 6e1145ce mov v14.b\[8\], v14.b\[8\]
+ 2230: 6e1145ef mov v15.b\[8\], v15.b\[8\]
+ 2234: 6e1145ef mov v15.b\[8\], v15.b\[8\]
+ 2238: 6e114610 mov v16.b\[8\], v16.b\[8\]
+ 223c: 6e114610 mov v16.b\[8\], v16.b\[8\]
+ 2240: 6e114631 mov v17.b\[8\], v17.b\[8\]
+ 2244: 6e114631 mov v17.b\[8\], v17.b\[8\]
+ 2248: 6e114652 mov v18.b\[8\], v18.b\[8\]
+ 224c: 6e114652 mov v18.b\[8\], v18.b\[8\]
+ 2250: 6e114673 mov v19.b\[8\], v19.b\[8\]
+ 2254: 6e114673 mov v19.b\[8\], v19.b\[8\]
+ 2258: 6e114694 mov v20.b\[8\], v20.b\[8\]
+ 225c: 6e114694 mov v20.b\[8\], v20.b\[8\]
+ 2260: 6e1146b5 mov v21.b\[8\], v21.b\[8\]
+ 2264: 6e1146b5 mov v21.b\[8\], v21.b\[8\]
+ 2268: 6e1146d6 mov v22.b\[8\], v22.b\[8\]
+ 226c: 6e1146d6 mov v22.b\[8\], v22.b\[8\]
+ 2270: 6e1146f7 mov v23.b\[8\], v23.b\[8\]
+ 2274: 6e1146f7 mov v23.b\[8\], v23.b\[8\]
+ 2278: 6e114718 mov v24.b\[8\], v24.b\[8\]
+ 227c: 6e114718 mov v24.b\[8\], v24.b\[8\]
+ 2280: 6e114739 mov v25.b\[8\], v25.b\[8\]
+ 2284: 6e114739 mov v25.b\[8\], v25.b\[8\]
+ 2288: 6e11475a mov v26.b\[8\], v26.b\[8\]
+ 228c: 6e11475a mov v26.b\[8\], v26.b\[8\]
+ 2290: 6e11477b mov v27.b\[8\], v27.b\[8\]
+ 2294: 6e11477b mov v27.b\[8\], v27.b\[8\]
+ 2298: 6e11479c mov v28.b\[8\], v28.b\[8\]
+ 229c: 6e11479c mov v28.b\[8\], v28.b\[8\]
+ 22a0: 6e1147bd mov v29.b\[8\], v29.b\[8\]
+ 22a4: 6e1147bd mov v29.b\[8\], v29.b\[8\]
+ 22a8: 6e1147de mov v30.b\[8\], v30.b\[8\]
+ 22ac: 6e1147de mov v30.b\[8\], v30.b\[8\]
+ 22b0: 6e134c21 mov v1.b\[9\], v1.b\[9\]
+ 22b4: 6e134c21 mov v1.b\[9\], v1.b\[9\]
+ 22b8: 6e134c42 mov v2.b\[9\], v2.b\[9\]
+ 22bc: 6e134c42 mov v2.b\[9\], v2.b\[9\]
+ 22c0: 6e134c63 mov v3.b\[9\], v3.b\[9\]
+ 22c4: 6e134c63 mov v3.b\[9\], v3.b\[9\]
+ 22c8: 6e134c84 mov v4.b\[9\], v4.b\[9\]
+ 22cc: 6e134c84 mov v4.b\[9\], v4.b\[9\]
+ 22d0: 6e134ca5 mov v5.b\[9\], v5.b\[9\]
+ 22d4: 6e134ca5 mov v5.b\[9\], v5.b\[9\]
+ 22d8: 6e134cc6 mov v6.b\[9\], v6.b\[9\]
+ 22dc: 6e134cc6 mov v6.b\[9\], v6.b\[9\]
+ 22e0: 6e134ce7 mov v7.b\[9\], v7.b\[9\]
+ 22e4: 6e134ce7 mov v7.b\[9\], v7.b\[9\]
+ 22e8: 6e134d08 mov v8.b\[9\], v8.b\[9\]
+ 22ec: 6e134d08 mov v8.b\[9\], v8.b\[9\]
+ 22f0: 6e134d29 mov v9.b\[9\], v9.b\[9\]
+ 22f4: 6e134d29 mov v9.b\[9\], v9.b\[9\]
+ 22f8: 6e134d4a mov v10.b\[9\], v10.b\[9\]
+ 22fc: 6e134d4a mov v10.b\[9\], v10.b\[9\]
+ 2300: 6e134d6b mov v11.b\[9\], v11.b\[9\]
+ 2304: 6e134d6b mov v11.b\[9\], v11.b\[9\]
+ 2308: 6e134d8c mov v12.b\[9\], v12.b\[9\]
+ 230c: 6e134d8c mov v12.b\[9\], v12.b\[9\]
+ 2310: 6e134dad mov v13.b\[9\], v13.b\[9\]
+ 2314: 6e134dad mov v13.b\[9\], v13.b\[9\]
+ 2318: 6e134dce mov v14.b\[9\], v14.b\[9\]
+ 231c: 6e134dce mov v14.b\[9\], v14.b\[9\]
+ 2320: 6e134def mov v15.b\[9\], v15.b\[9\]
+ 2324: 6e134def mov v15.b\[9\], v15.b\[9\]
+ 2328: 6e134e10 mov v16.b\[9\], v16.b\[9\]
+ 232c: 6e134e10 mov v16.b\[9\], v16.b\[9\]
+ 2330: 6e134e31 mov v17.b\[9\], v17.b\[9\]
+ 2334: 6e134e31 mov v17.b\[9\], v17.b\[9\]
+ 2338: 6e134e52 mov v18.b\[9\], v18.b\[9\]
+ 233c: 6e134e52 mov v18.b\[9\], v18.b\[9\]
+ 2340: 6e134e73 mov v19.b\[9\], v19.b\[9\]
+ 2344: 6e134e73 mov v19.b\[9\], v19.b\[9\]
+ 2348: 6e134e94 mov v20.b\[9\], v20.b\[9\]
+ 234c: 6e134e94 mov v20.b\[9\], v20.b\[9\]
+ 2350: 6e134eb5 mov v21.b\[9\], v21.b\[9\]
+ 2354: 6e134eb5 mov v21.b\[9\], v21.b\[9\]
+ 2358: 6e134ed6 mov v22.b\[9\], v22.b\[9\]
+ 235c: 6e134ed6 mov v22.b\[9\], v22.b\[9\]
+ 2360: 6e134ef7 mov v23.b\[9\], v23.b\[9\]
+ 2364: 6e134ef7 mov v23.b\[9\], v23.b\[9\]
+ 2368: 6e134f18 mov v24.b\[9\], v24.b\[9\]
+ 236c: 6e134f18 mov v24.b\[9\], v24.b\[9\]
+ 2370: 6e134f39 mov v25.b\[9\], v25.b\[9\]
+ 2374: 6e134f39 mov v25.b\[9\], v25.b\[9\]
+ 2378: 6e134f5a mov v26.b\[9\], v26.b\[9\]
+ 237c: 6e134f5a mov v26.b\[9\], v26.b\[9\]
+ 2380: 6e134f7b mov v27.b\[9\], v27.b\[9\]
+ 2384: 6e134f7b mov v27.b\[9\], v27.b\[9\]
+ 2388: 6e134f9c mov v28.b\[9\], v28.b\[9\]
+ 238c: 6e134f9c mov v28.b\[9\], v28.b\[9\]
+ 2390: 6e134fbd mov v29.b\[9\], v29.b\[9\]
+ 2394: 6e134fbd mov v29.b\[9\], v29.b\[9\]
+ 2398: 6e134fde mov v30.b\[9\], v30.b\[9\]
+ 239c: 6e134fde mov v30.b\[9\], v30.b\[9\]
+ 23a0: 6e155421 mov v1.b\[10\], v1.b\[10\]
+ 23a4: 6e155421 mov v1.b\[10\], v1.b\[10\]
+ 23a8: 6e155442 mov v2.b\[10\], v2.b\[10\]
+ 23ac: 6e155442 mov v2.b\[10\], v2.b\[10\]
+ 23b0: 6e155463 mov v3.b\[10\], v3.b\[10\]
+ 23b4: 6e155463 mov v3.b\[10\], v3.b\[10\]
+ 23b8: 6e155484 mov v4.b\[10\], v4.b\[10\]
+ 23bc: 6e155484 mov v4.b\[10\], v4.b\[10\]
+ 23c0: 6e1554a5 mov v5.b\[10\], v5.b\[10\]
+ 23c4: 6e1554a5 mov v5.b\[10\], v5.b\[10\]
+ 23c8: 6e1554c6 mov v6.b\[10\], v6.b\[10\]
+ 23cc: 6e1554c6 mov v6.b\[10\], v6.b\[10\]
+ 23d0: 6e1554e7 mov v7.b\[10\], v7.b\[10\]
+ 23d4: 6e1554e7 mov v7.b\[10\], v7.b\[10\]
+ 23d8: 6e155508 mov v8.b\[10\], v8.b\[10\]
+ 23dc: 6e155508 mov v8.b\[10\], v8.b\[10\]
+ 23e0: 6e155529 mov v9.b\[10\], v9.b\[10\]
+ 23e4: 6e155529 mov v9.b\[10\], v9.b\[10\]
+ 23e8: 6e15554a mov v10.b\[10\], v10.b\[10\]
+ 23ec: 6e15554a mov v10.b\[10\], v10.b\[10\]
+ 23f0: 6e15556b mov v11.b\[10\], v11.b\[10\]
+ 23f4: 6e15556b mov v11.b\[10\], v11.b\[10\]
+ 23f8: 6e15558c mov v12.b\[10\], v12.b\[10\]
+ 23fc: 6e15558c mov v12.b\[10\], v12.b\[10\]
+ 2400: 6e1555ad mov v13.b\[10\], v13.b\[10\]
+ 2404: 6e1555ad mov v13.b\[10\], v13.b\[10\]
+ 2408: 6e1555ce mov v14.b\[10\], v14.b\[10\]
+ 240c: 6e1555ce mov v14.b\[10\], v14.b\[10\]
+ 2410: 6e1555ef mov v15.b\[10\], v15.b\[10\]
+ 2414: 6e1555ef mov v15.b\[10\], v15.b\[10\]
+ 2418: 6e155610 mov v16.b\[10\], v16.b\[10\]
+ 241c: 6e155610 mov v16.b\[10\], v16.b\[10\]
+ 2420: 6e155631 mov v17.b\[10\], v17.b\[10\]
+ 2424: 6e155631 mov v17.b\[10\], v17.b\[10\]
+ 2428: 6e155652 mov v18.b\[10\], v18.b\[10\]
+ 242c: 6e155652 mov v18.b\[10\], v18.b\[10\]
+ 2430: 6e155673 mov v19.b\[10\], v19.b\[10\]
+ 2434: 6e155673 mov v19.b\[10\], v19.b\[10\]
+ 2438: 6e155694 mov v20.b\[10\], v20.b\[10\]
+ 243c: 6e155694 mov v20.b\[10\], v20.b\[10\]
+ 2440: 6e1556b5 mov v21.b\[10\], v21.b\[10\]
+ 2444: 6e1556b5 mov v21.b\[10\], v21.b\[10\]
+ 2448: 6e1556d6 mov v22.b\[10\], v22.b\[10\]
+ 244c: 6e1556d6 mov v22.b\[10\], v22.b\[10\]
+ 2450: 6e1556f7 mov v23.b\[10\], v23.b\[10\]
+ 2454: 6e1556f7 mov v23.b\[10\], v23.b\[10\]
+ 2458: 6e155718 mov v24.b\[10\], v24.b\[10\]
+ 245c: 6e155718 mov v24.b\[10\], v24.b\[10\]
+ 2460: 6e155739 mov v25.b\[10\], v25.b\[10\]
+ 2464: 6e155739 mov v25.b\[10\], v25.b\[10\]
+ 2468: 6e15575a mov v26.b\[10\], v26.b\[10\]
+ 246c: 6e15575a mov v26.b\[10\], v26.b\[10\]
+ 2470: 6e15577b mov v27.b\[10\], v27.b\[10\]
+ 2474: 6e15577b mov v27.b\[10\], v27.b\[10\]
+ 2478: 6e15579c mov v28.b\[10\], v28.b\[10\]
+ 247c: 6e15579c mov v28.b\[10\], v28.b\[10\]
+ 2480: 6e1557bd mov v29.b\[10\], v29.b\[10\]
+ 2484: 6e1557bd mov v29.b\[10\], v29.b\[10\]
+ 2488: 6e1557de mov v30.b\[10\], v30.b\[10\]
+ 248c: 6e1557de mov v30.b\[10\], v30.b\[10\]
+ 2490: 6e175c21 mov v1.b\[11\], v1.b\[11\]
+ 2494: 6e175c21 mov v1.b\[11\], v1.b\[11\]
+ 2498: 6e175c42 mov v2.b\[11\], v2.b\[11\]
+ 249c: 6e175c42 mov v2.b\[11\], v2.b\[11\]
+ 24a0: 6e175c63 mov v3.b\[11\], v3.b\[11\]
+ 24a4: 6e175c63 mov v3.b\[11\], v3.b\[11\]
+ 24a8: 6e175c84 mov v4.b\[11\], v4.b\[11\]
+ 24ac: 6e175c84 mov v4.b\[11\], v4.b\[11\]
+ 24b0: 6e175ca5 mov v5.b\[11\], v5.b\[11\]
+ 24b4: 6e175ca5 mov v5.b\[11\], v5.b\[11\]
+ 24b8: 6e175cc6 mov v6.b\[11\], v6.b\[11\]
+ 24bc: 6e175cc6 mov v6.b\[11\], v6.b\[11\]
+ 24c0: 6e175ce7 mov v7.b\[11\], v7.b\[11\]
+ 24c4: 6e175ce7 mov v7.b\[11\], v7.b\[11\]
+ 24c8: 6e175d08 mov v8.b\[11\], v8.b\[11\]
+ 24cc: 6e175d08 mov v8.b\[11\], v8.b\[11\]
+ 24d0: 6e175d29 mov v9.b\[11\], v9.b\[11\]
+ 24d4: 6e175d29 mov v9.b\[11\], v9.b\[11\]
+ 24d8: 6e175d4a mov v10.b\[11\], v10.b\[11\]
+ 24dc: 6e175d4a mov v10.b\[11\], v10.b\[11\]
+ 24e0: 6e175d6b mov v11.b\[11\], v11.b\[11\]
+ 24e4: 6e175d6b mov v11.b\[11\], v11.b\[11\]
+ 24e8: 6e175d8c mov v12.b\[11\], v12.b\[11\]
+ 24ec: 6e175d8c mov v12.b\[11\], v12.b\[11\]
+ 24f0: 6e175dad mov v13.b\[11\], v13.b\[11\]
+ 24f4: 6e175dad mov v13.b\[11\], v13.b\[11\]
+ 24f8: 6e175dce mov v14.b\[11\], v14.b\[11\]
+ 24fc: 6e175dce mov v14.b\[11\], v14.b\[11\]
+ 2500: 6e175def mov v15.b\[11\], v15.b\[11\]
+ 2504: 6e175def mov v15.b\[11\], v15.b\[11\]
+ 2508: 6e175e10 mov v16.b\[11\], v16.b\[11\]
+ 250c: 6e175e10 mov v16.b\[11\], v16.b\[11\]
+ 2510: 6e175e31 mov v17.b\[11\], v17.b\[11\]
+ 2514: 6e175e31 mov v17.b\[11\], v17.b\[11\]
+ 2518: 6e175e52 mov v18.b\[11\], v18.b\[11\]
+ 251c: 6e175e52 mov v18.b\[11\], v18.b\[11\]
+ 2520: 6e175e73 mov v19.b\[11\], v19.b\[11\]
+ 2524: 6e175e73 mov v19.b\[11\], v19.b\[11\]
+ 2528: 6e175e94 mov v20.b\[11\], v20.b\[11\]
+ 252c: 6e175e94 mov v20.b\[11\], v20.b\[11\]
+ 2530: 6e175eb5 mov v21.b\[11\], v21.b\[11\]
+ 2534: 6e175eb5 mov v21.b\[11\], v21.b\[11\]
+ 2538: 6e175ed6 mov v22.b\[11\], v22.b\[11\]
+ 253c: 6e175ed6 mov v22.b\[11\], v22.b\[11\]
+ 2540: 6e175ef7 mov v23.b\[11\], v23.b\[11\]
+ 2544: 6e175ef7 mov v23.b\[11\], v23.b\[11\]
+ 2548: 6e175f18 mov v24.b\[11\], v24.b\[11\]
+ 254c: 6e175f18 mov v24.b\[11\], v24.b\[11\]
+ 2550: 6e175f39 mov v25.b\[11\], v25.b\[11\]
+ 2554: 6e175f39 mov v25.b\[11\], v25.b\[11\]
+ 2558: 6e175f5a mov v26.b\[11\], v26.b\[11\]
+ 255c: 6e175f5a mov v26.b\[11\], v26.b\[11\]
+ 2560: 6e175f7b mov v27.b\[11\], v27.b\[11\]
+ 2564: 6e175f7b mov v27.b\[11\], v27.b\[11\]
+ 2568: 6e175f9c mov v28.b\[11\], v28.b\[11\]
+ 256c: 6e175f9c mov v28.b\[11\], v28.b\[11\]
+ 2570: 6e175fbd mov v29.b\[11\], v29.b\[11\]
+ 2574: 6e175fbd mov v29.b\[11\], v29.b\[11\]
+ 2578: 6e175fde mov v30.b\[11\], v30.b\[11\]
+ 257c: 6e175fde mov v30.b\[11\], v30.b\[11\]
+ 2580: 6e196421 mov v1.b\[12\], v1.b\[12\]
+ 2584: 6e196421 mov v1.b\[12\], v1.b\[12\]
+ 2588: 6e196442 mov v2.b\[12\], v2.b\[12\]
+ 258c: 6e196442 mov v2.b\[12\], v2.b\[12\]
+ 2590: 6e196463 mov v3.b\[12\], v3.b\[12\]
+ 2594: 6e196463 mov v3.b\[12\], v3.b\[12\]
+ 2598: 6e196484 mov v4.b\[12\], v4.b\[12\]
+ 259c: 6e196484 mov v4.b\[12\], v4.b\[12\]
+ 25a0: 6e1964a5 mov v5.b\[12\], v5.b\[12\]
+ 25a4: 6e1964a5 mov v5.b\[12\], v5.b\[12\]
+ 25a8: 6e1964c6 mov v6.b\[12\], v6.b\[12\]
+ 25ac: 6e1964c6 mov v6.b\[12\], v6.b\[12\]
+ 25b0: 6e1964e7 mov v7.b\[12\], v7.b\[12\]
+ 25b4: 6e1964e7 mov v7.b\[12\], v7.b\[12\]
+ 25b8: 6e196508 mov v8.b\[12\], v8.b\[12\]
+ 25bc: 6e196508 mov v8.b\[12\], v8.b\[12\]
+ 25c0: 6e196529 mov v9.b\[12\], v9.b\[12\]
+ 25c4: 6e196529 mov v9.b\[12\], v9.b\[12\]
+ 25c8: 6e19654a mov v10.b\[12\], v10.b\[12\]
+ 25cc: 6e19654a mov v10.b\[12\], v10.b\[12\]
+ 25d0: 6e19656b mov v11.b\[12\], v11.b\[12\]
+ 25d4: 6e19656b mov v11.b\[12\], v11.b\[12\]
+ 25d8: 6e19658c mov v12.b\[12\], v12.b\[12\]
+ 25dc: 6e19658c mov v12.b\[12\], v12.b\[12\]
+ 25e0: 6e1965ad mov v13.b\[12\], v13.b\[12\]
+ 25e4: 6e1965ad mov v13.b\[12\], v13.b\[12\]
+ 25e8: 6e1965ce mov v14.b\[12\], v14.b\[12\]
+ 25ec: 6e1965ce mov v14.b\[12\], v14.b\[12\]
+ 25f0: 6e1965ef mov v15.b\[12\], v15.b\[12\]
+ 25f4: 6e1965ef mov v15.b\[12\], v15.b\[12\]
+ 25f8: 6e196610 mov v16.b\[12\], v16.b\[12\]
+ 25fc: 6e196610 mov v16.b\[12\], v16.b\[12\]
+ 2600: 6e196631 mov v17.b\[12\], v17.b\[12\]
+ 2604: 6e196631 mov v17.b\[12\], v17.b\[12\]
+ 2608: 6e196652 mov v18.b\[12\], v18.b\[12\]
+ 260c: 6e196652 mov v18.b\[12\], v18.b\[12\]
+ 2610: 6e196673 mov v19.b\[12\], v19.b\[12\]
+ 2614: 6e196673 mov v19.b\[12\], v19.b\[12\]
+ 2618: 6e196694 mov v20.b\[12\], v20.b\[12\]
+ 261c: 6e196694 mov v20.b\[12\], v20.b\[12\]
+ 2620: 6e1966b5 mov v21.b\[12\], v21.b\[12\]
+ 2624: 6e1966b5 mov v21.b\[12\], v21.b\[12\]
+ 2628: 6e1966d6 mov v22.b\[12\], v22.b\[12\]
+ 262c: 6e1966d6 mov v22.b\[12\], v22.b\[12\]
+ 2630: 6e1966f7 mov v23.b\[12\], v23.b\[12\]
+ 2634: 6e1966f7 mov v23.b\[12\], v23.b\[12\]
+ 2638: 6e196718 mov v24.b\[12\], v24.b\[12\]
+ 263c: 6e196718 mov v24.b\[12\], v24.b\[12\]
+ 2640: 6e196739 mov v25.b\[12\], v25.b\[12\]
+ 2644: 6e196739 mov v25.b\[12\], v25.b\[12\]
+ 2648: 6e19675a mov v26.b\[12\], v26.b\[12\]
+ 264c: 6e19675a mov v26.b\[12\], v26.b\[12\]
+ 2650: 6e19677b mov v27.b\[12\], v27.b\[12\]
+ 2654: 6e19677b mov v27.b\[12\], v27.b\[12\]
+ 2658: 6e19679c mov v28.b\[12\], v28.b\[12\]
+ 265c: 6e19679c mov v28.b\[12\], v28.b\[12\]
+ 2660: 6e1967bd mov v29.b\[12\], v29.b\[12\]
+ 2664: 6e1967bd mov v29.b\[12\], v29.b\[12\]
+ 2668: 6e1967de mov v30.b\[12\], v30.b\[12\]
+ 266c: 6e1967de mov v30.b\[12\], v30.b\[12\]
+ 2670: 6e1b6c21 mov v1.b\[13\], v1.b\[13\]
+ 2674: 6e1b6c21 mov v1.b\[13\], v1.b\[13\]
+ 2678: 6e1b6c42 mov v2.b\[13\], v2.b\[13\]
+ 267c: 6e1b6c42 mov v2.b\[13\], v2.b\[13\]
+ 2680: 6e1b6c63 mov v3.b\[13\], v3.b\[13\]
+ 2684: 6e1b6c63 mov v3.b\[13\], v3.b\[13\]
+ 2688: 6e1b6c84 mov v4.b\[13\], v4.b\[13\]
+ 268c: 6e1b6c84 mov v4.b\[13\], v4.b\[13\]
+ 2690: 6e1b6ca5 mov v5.b\[13\], v5.b\[13\]
+ 2694: 6e1b6ca5 mov v5.b\[13\], v5.b\[13\]
+ 2698: 6e1b6cc6 mov v6.b\[13\], v6.b\[13\]
+ 269c: 6e1b6cc6 mov v6.b\[13\], v6.b\[13\]
+ 26a0: 6e1b6ce7 mov v7.b\[13\], v7.b\[13\]
+ 26a4: 6e1b6ce7 mov v7.b\[13\], v7.b\[13\]
+ 26a8: 6e1b6d08 mov v8.b\[13\], v8.b\[13\]
+ 26ac: 6e1b6d08 mov v8.b\[13\], v8.b\[13\]
+ 26b0: 6e1b6d29 mov v9.b\[13\], v9.b\[13\]
+ 26b4: 6e1b6d29 mov v9.b\[13\], v9.b\[13\]
+ 26b8: 6e1b6d4a mov v10.b\[13\], v10.b\[13\]
+ 26bc: 6e1b6d4a mov v10.b\[13\], v10.b\[13\]
+ 26c0: 6e1b6d6b mov v11.b\[13\], v11.b\[13\]
+ 26c4: 6e1b6d6b mov v11.b\[13\], v11.b\[13\]
+ 26c8: 6e1b6d8c mov v12.b\[13\], v12.b\[13\]
+ 26cc: 6e1b6d8c mov v12.b\[13\], v12.b\[13\]
+ 26d0: 6e1b6dad mov v13.b\[13\], v13.b\[13\]
+ 26d4: 6e1b6dad mov v13.b\[13\], v13.b\[13\]
+ 26d8: 6e1b6dce mov v14.b\[13\], v14.b\[13\]
+ 26dc: 6e1b6dce mov v14.b\[13\], v14.b\[13\]
+ 26e0: 6e1b6def mov v15.b\[13\], v15.b\[13\]
+ 26e4: 6e1b6def mov v15.b\[13\], v15.b\[13\]
+ 26e8: 6e1b6e10 mov v16.b\[13\], v16.b\[13\]
+ 26ec: 6e1b6e10 mov v16.b\[13\], v16.b\[13\]
+ 26f0: 6e1b6e31 mov v17.b\[13\], v17.b\[13\]
+ 26f4: 6e1b6e31 mov v17.b\[13\], v17.b\[13\]
+ 26f8: 6e1b6e52 mov v18.b\[13\], v18.b\[13\]
+ 26fc: 6e1b6e52 mov v18.b\[13\], v18.b\[13\]
+ 2700: 6e1b6e73 mov v19.b\[13\], v19.b\[13\]
+ 2704: 6e1b6e73 mov v19.b\[13\], v19.b\[13\]
+ 2708: 6e1b6e94 mov v20.b\[13\], v20.b\[13\]
+ 270c: 6e1b6e94 mov v20.b\[13\], v20.b\[13\]
+ 2710: 6e1b6eb5 mov v21.b\[13\], v21.b\[13\]
+ 2714: 6e1b6eb5 mov v21.b\[13\], v21.b\[13\]
+ 2718: 6e1b6ed6 mov v22.b\[13\], v22.b\[13\]
+ 271c: 6e1b6ed6 mov v22.b\[13\], v22.b\[13\]
+ 2720: 6e1b6ef7 mov v23.b\[13\], v23.b\[13\]
+ 2724: 6e1b6ef7 mov v23.b\[13\], v23.b\[13\]
+ 2728: 6e1b6f18 mov v24.b\[13\], v24.b\[13\]
+ 272c: 6e1b6f18 mov v24.b\[13\], v24.b\[13\]
+ 2730: 6e1b6f39 mov v25.b\[13\], v25.b\[13\]
+ 2734: 6e1b6f39 mov v25.b\[13\], v25.b\[13\]
+ 2738: 6e1b6f5a mov v26.b\[13\], v26.b\[13\]
+ 273c: 6e1b6f5a mov v26.b\[13\], v26.b\[13\]
+ 2740: 6e1b6f7b mov v27.b\[13\], v27.b\[13\]
+ 2744: 6e1b6f7b mov v27.b\[13\], v27.b\[13\]
+ 2748: 6e1b6f9c mov v28.b\[13\], v28.b\[13\]
+ 274c: 6e1b6f9c mov v28.b\[13\], v28.b\[13\]
+ 2750: 6e1b6fbd mov v29.b\[13\], v29.b\[13\]
+ 2754: 6e1b6fbd mov v29.b\[13\], v29.b\[13\]
+ 2758: 6e1b6fde mov v30.b\[13\], v30.b\[13\]
+ 275c: 6e1b6fde mov v30.b\[13\], v30.b\[13\]
+ 2760: 6e1d7421 mov v1.b\[14\], v1.b\[14\]
+ 2764: 6e1d7421 mov v1.b\[14\], v1.b\[14\]
+ 2768: 6e1d7442 mov v2.b\[14\], v2.b\[14\]
+ 276c: 6e1d7442 mov v2.b\[14\], v2.b\[14\]
+ 2770: 6e1d7463 mov v3.b\[14\], v3.b\[14\]
+ 2774: 6e1d7463 mov v3.b\[14\], v3.b\[14\]
+ 2778: 6e1d7484 mov v4.b\[14\], v4.b\[14\]
+ 277c: 6e1d7484 mov v4.b\[14\], v4.b\[14\]
+ 2780: 6e1d74a5 mov v5.b\[14\], v5.b\[14\]
+ 2784: 6e1d74a5 mov v5.b\[14\], v5.b\[14\]
+ 2788: 6e1d74c6 mov v6.b\[14\], v6.b\[14\]
+ 278c: 6e1d74c6 mov v6.b\[14\], v6.b\[14\]
+ 2790: 6e1d74e7 mov v7.b\[14\], v7.b\[14\]
+ 2794: 6e1d74e7 mov v7.b\[14\], v7.b\[14\]
+ 2798: 6e1d7508 mov v8.b\[14\], v8.b\[14\]
+ 279c: 6e1d7508 mov v8.b\[14\], v8.b\[14\]
+ 27a0: 6e1d7529 mov v9.b\[14\], v9.b\[14\]
+ 27a4: 6e1d7529 mov v9.b\[14\], v9.b\[14\]
+ 27a8: 6e1d754a mov v10.b\[14\], v10.b\[14\]
+ 27ac: 6e1d754a mov v10.b\[14\], v10.b\[14\]
+ 27b0: 6e1d756b mov v11.b\[14\], v11.b\[14\]
+ 27b4: 6e1d756b mov v11.b\[14\], v11.b\[14\]
+ 27b8: 6e1d758c mov v12.b\[14\], v12.b\[14\]
+ 27bc: 6e1d758c mov v12.b\[14\], v12.b\[14\]
+ 27c0: 6e1d75ad mov v13.b\[14\], v13.b\[14\]
+ 27c4: 6e1d75ad mov v13.b\[14\], v13.b\[14\]
+ 27c8: 6e1d75ce mov v14.b\[14\], v14.b\[14\]
+ 27cc: 6e1d75ce mov v14.b\[14\], v14.b\[14\]
+ 27d0: 6e1d75ef mov v15.b\[14\], v15.b\[14\]
+ 27d4: 6e1d75ef mov v15.b\[14\], v15.b\[14\]
+ 27d8: 6e1d7610 mov v16.b\[14\], v16.b\[14\]
+ 27dc: 6e1d7610 mov v16.b\[14\], v16.b\[14\]
+ 27e0: 6e1d7631 mov v17.b\[14\], v17.b\[14\]
+ 27e4: 6e1d7631 mov v17.b\[14\], v17.b\[14\]
+ 27e8: 6e1d7652 mov v18.b\[14\], v18.b\[14\]
+ 27ec: 6e1d7652 mov v18.b\[14\], v18.b\[14\]
+ 27f0: 6e1d7673 mov v19.b\[14\], v19.b\[14\]
+ 27f4: 6e1d7673 mov v19.b\[14\], v19.b\[14\]
+ 27f8: 6e1d7694 mov v20.b\[14\], v20.b\[14\]
+ 27fc: 6e1d7694 mov v20.b\[14\], v20.b\[14\]
+ 2800: 6e1d76b5 mov v21.b\[14\], v21.b\[14\]
+ 2804: 6e1d76b5 mov v21.b\[14\], v21.b\[14\]
+ 2808: 6e1d76d6 mov v22.b\[14\], v22.b\[14\]
+ 280c: 6e1d76d6 mov v22.b\[14\], v22.b\[14\]
+ 2810: 6e1d76f7 mov v23.b\[14\], v23.b\[14\]
+ 2814: 6e1d76f7 mov v23.b\[14\], v23.b\[14\]
+ 2818: 6e1d7718 mov v24.b\[14\], v24.b\[14\]
+ 281c: 6e1d7718 mov v24.b\[14\], v24.b\[14\]
+ 2820: 6e1d7739 mov v25.b\[14\], v25.b\[14\]
+ 2824: 6e1d7739 mov v25.b\[14\], v25.b\[14\]
+ 2828: 6e1d775a mov v26.b\[14\], v26.b\[14\]
+ 282c: 6e1d775a mov v26.b\[14\], v26.b\[14\]
+ 2830: 6e1d777b mov v27.b\[14\], v27.b\[14\]
+ 2834: 6e1d777b mov v27.b\[14\], v27.b\[14\]
+ 2838: 6e1d779c mov v28.b\[14\], v28.b\[14\]
+ 283c: 6e1d779c mov v28.b\[14\], v28.b\[14\]
+ 2840: 6e1d77bd mov v29.b\[14\], v29.b\[14\]
+ 2844: 6e1d77bd mov v29.b\[14\], v29.b\[14\]
+ 2848: 6e1d77de mov v30.b\[14\], v30.b\[14\]
+ 284c: 6e1d77de mov v30.b\[14\], v30.b\[14\]
+ 2850: 6e1f7c21 mov v1.b\[15\], v1.b\[15\]
+ 2854: 6e1f7c21 mov v1.b\[15\], v1.b\[15\]
+ 2858: 6e1f7c42 mov v2.b\[15\], v2.b\[15\]
+ 285c: 6e1f7c42 mov v2.b\[15\], v2.b\[15\]
+ 2860: 6e1f7c63 mov v3.b\[15\], v3.b\[15\]
+ 2864: 6e1f7c63 mov v3.b\[15\], v3.b\[15\]
+ 2868: 6e1f7c84 mov v4.b\[15\], v4.b\[15\]
+ 286c: 6e1f7c84 mov v4.b\[15\], v4.b\[15\]
+ 2870: 6e1f7ca5 mov v5.b\[15\], v5.b\[15\]
+ 2874: 6e1f7ca5 mov v5.b\[15\], v5.b\[15\]
+ 2878: 6e1f7cc6 mov v6.b\[15\], v6.b\[15\]
+ 287c: 6e1f7cc6 mov v6.b\[15\], v6.b\[15\]
+ 2880: 6e1f7ce7 mov v7.b\[15\], v7.b\[15\]
+ 2884: 6e1f7ce7 mov v7.b\[15\], v7.b\[15\]
+ 2888: 6e1f7d08 mov v8.b\[15\], v8.b\[15\]
+ 288c: 6e1f7d08 mov v8.b\[15\], v8.b\[15\]
+ 2890: 6e1f7d29 mov v9.b\[15\], v9.b\[15\]
+ 2894: 6e1f7d29 mov v9.b\[15\], v9.b\[15\]
+ 2898: 6e1f7d4a mov v10.b\[15\], v10.b\[15\]
+ 289c: 6e1f7d4a mov v10.b\[15\], v10.b\[15\]
+ 28a0: 6e1f7d6b mov v11.b\[15\], v11.b\[15\]
+ 28a4: 6e1f7d6b mov v11.b\[15\], v11.b\[15\]
+ 28a8: 6e1f7d8c mov v12.b\[15\], v12.b\[15\]
+ 28ac: 6e1f7d8c mov v12.b\[15\], v12.b\[15\]
+ 28b0: 6e1f7dad mov v13.b\[15\], v13.b\[15\]
+ 28b4: 6e1f7dad mov v13.b\[15\], v13.b\[15\]
+ 28b8: 6e1f7dce mov v14.b\[15\], v14.b\[15\]
+ 28bc: 6e1f7dce mov v14.b\[15\], v14.b\[15\]
+ 28c0: 6e1f7def mov v15.b\[15\], v15.b\[15\]
+ 28c4: 6e1f7def mov v15.b\[15\], v15.b\[15\]
+ 28c8: 6e1f7e10 mov v16.b\[15\], v16.b\[15\]
+ 28cc: 6e1f7e10 mov v16.b\[15\], v16.b\[15\]
+ 28d0: 6e1f7e31 mov v17.b\[15\], v17.b\[15\]
+ 28d4: 6e1f7e31 mov v17.b\[15\], v17.b\[15\]
+ 28d8: 6e1f7e52 mov v18.b\[15\], v18.b\[15\]
+ 28dc: 6e1f7e52 mov v18.b\[15\], v18.b\[15\]
+ 28e0: 6e1f7e73 mov v19.b\[15\], v19.b\[15\]
+ 28e4: 6e1f7e73 mov v19.b\[15\], v19.b\[15\]
+ 28e8: 6e1f7e94 mov v20.b\[15\], v20.b\[15\]
+ 28ec: 6e1f7e94 mov v20.b\[15\], v20.b\[15\]
+ 28f0: 6e1f7eb5 mov v21.b\[15\], v21.b\[15\]
+ 28f4: 6e1f7eb5 mov v21.b\[15\], v21.b\[15\]
+ 28f8: 6e1f7ed6 mov v22.b\[15\], v22.b\[15\]
+ 28fc: 6e1f7ed6 mov v22.b\[15\], v22.b\[15\]
+ 2900: 6e1f7ef7 mov v23.b\[15\], v23.b\[15\]
+ 2904: 6e1f7ef7 mov v23.b\[15\], v23.b\[15\]
+ 2908: 6e1f7f18 mov v24.b\[15\], v24.b\[15\]
+ 290c: 6e1f7f18 mov v24.b\[15\], v24.b\[15\]
+ 2910: 6e1f7f39 mov v25.b\[15\], v25.b\[15\]
+ 2914: 6e1f7f39 mov v25.b\[15\], v25.b\[15\]
+ 2918: 6e1f7f5a mov v26.b\[15\], v26.b\[15\]
+ 291c: 6e1f7f5a mov v26.b\[15\], v26.b\[15\]
+ 2920: 6e1f7f7b mov v27.b\[15\], v27.b\[15\]
+ 2924: 6e1f7f7b mov v27.b\[15\], v27.b\[15\]
+ 2928: 6e1f7f9c mov v28.b\[15\], v28.b\[15\]
+ 292c: 6e1f7f9c mov v28.b\[15\], v28.b\[15\]
+ 2930: 6e1f7fbd mov v29.b\[15\], v29.b\[15\]
+ 2934: 6e1f7fbd mov v29.b\[15\], v29.b\[15\]
+ 2938: 6e1f7fde mov v30.b\[15\], v30.b\[15\]
+ 293c: 6e1f7fde mov v30.b\[15\], v30.b\[15\]
+ 2940: 6e020421 mov v1.h\[0\], v1.h\[0\]
+ 2944: 6e020421 mov v1.h\[0\], v1.h\[0\]
+ 2948: 6e020442 mov v2.h\[0\], v2.h\[0\]
+ 294c: 6e020442 mov v2.h\[0\], v2.h\[0\]
+ 2950: 6e020463 mov v3.h\[0\], v3.h\[0\]
+ 2954: 6e020463 mov v3.h\[0\], v3.h\[0\]
+ 2958: 6e020484 mov v4.h\[0\], v4.h\[0\]
+ 295c: 6e020484 mov v4.h\[0\], v4.h\[0\]
+ 2960: 6e0204a5 mov v5.h\[0\], v5.h\[0\]
+ 2964: 6e0204a5 mov v5.h\[0\], v5.h\[0\]
+ 2968: 6e0204c6 mov v6.h\[0\], v6.h\[0\]
+ 296c: 6e0204c6 mov v6.h\[0\], v6.h\[0\]
+ 2970: 6e0204e7 mov v7.h\[0\], v7.h\[0\]
+ 2974: 6e0204e7 mov v7.h\[0\], v7.h\[0\]
+ 2978: 6e020508 mov v8.h\[0\], v8.h\[0\]
+ 297c: 6e020508 mov v8.h\[0\], v8.h\[0\]
+ 2980: 6e020529 mov v9.h\[0\], v9.h\[0\]
+ 2984: 6e020529 mov v9.h\[0\], v9.h\[0\]
+ 2988: 6e02054a mov v10.h\[0\], v10.h\[0\]
+ 298c: 6e02054a mov v10.h\[0\], v10.h\[0\]
+ 2990: 6e02056b mov v11.h\[0\], v11.h\[0\]
+ 2994: 6e02056b mov v11.h\[0\], v11.h\[0\]
+ 2998: 6e02058c mov v12.h\[0\], v12.h\[0\]
+ 299c: 6e02058c mov v12.h\[0\], v12.h\[0\]
+ 29a0: 6e0205ad mov v13.h\[0\], v13.h\[0\]
+ 29a4: 6e0205ad mov v13.h\[0\], v13.h\[0\]
+ 29a8: 6e0205ce mov v14.h\[0\], v14.h\[0\]
+ 29ac: 6e0205ce mov v14.h\[0\], v14.h\[0\]
+ 29b0: 6e0205ef mov v15.h\[0\], v15.h\[0\]
+ 29b4: 6e0205ef mov v15.h\[0\], v15.h\[0\]
+ 29b8: 6e020610 mov v16.h\[0\], v16.h\[0\]
+ 29bc: 6e020610 mov v16.h\[0\], v16.h\[0\]
+ 29c0: 6e020631 mov v17.h\[0\], v17.h\[0\]
+ 29c4: 6e020631 mov v17.h\[0\], v17.h\[0\]
+ 29c8: 6e020652 mov v18.h\[0\], v18.h\[0\]
+ 29cc: 6e020652 mov v18.h\[0\], v18.h\[0\]
+ 29d0: 6e020673 mov v19.h\[0\], v19.h\[0\]
+ 29d4: 6e020673 mov v19.h\[0\], v19.h\[0\]
+ 29d8: 6e020694 mov v20.h\[0\], v20.h\[0\]
+ 29dc: 6e020694 mov v20.h\[0\], v20.h\[0\]
+ 29e0: 6e0206b5 mov v21.h\[0\], v21.h\[0\]
+ 29e4: 6e0206b5 mov v21.h\[0\], v21.h\[0\]
+ 29e8: 6e0206d6 mov v22.h\[0\], v22.h\[0\]
+ 29ec: 6e0206d6 mov v22.h\[0\], v22.h\[0\]
+ 29f0: 6e0206f7 mov v23.h\[0\], v23.h\[0\]
+ 29f4: 6e0206f7 mov v23.h\[0\], v23.h\[0\]
+ 29f8: 6e020718 mov v24.h\[0\], v24.h\[0\]
+ 29fc: 6e020718 mov v24.h\[0\], v24.h\[0\]
+ 2a00: 6e020739 mov v25.h\[0\], v25.h\[0\]
+ 2a04: 6e020739 mov v25.h\[0\], v25.h\[0\]
+ 2a08: 6e02075a mov v26.h\[0\], v26.h\[0\]
+ 2a0c: 6e02075a mov v26.h\[0\], v26.h\[0\]
+ 2a10: 6e02077b mov v27.h\[0\], v27.h\[0\]
+ 2a14: 6e02077b mov v27.h\[0\], v27.h\[0\]
+ 2a18: 6e02079c mov v28.h\[0\], v28.h\[0\]
+ 2a1c: 6e02079c mov v28.h\[0\], v28.h\[0\]
+ 2a20: 6e0207bd mov v29.h\[0\], v29.h\[0\]
+ 2a24: 6e0207bd mov v29.h\[0\], v29.h\[0\]
+ 2a28: 6e0207de mov v30.h\[0\], v30.h\[0\]
+ 2a2c: 6e0207de mov v30.h\[0\], v30.h\[0\]
+ 2a30: 6e061421 mov v1.h\[1\], v1.h\[1\]
+ 2a34: 6e061421 mov v1.h\[1\], v1.h\[1\]
+ 2a38: 6e061442 mov v2.h\[1\], v2.h\[1\]
+ 2a3c: 6e061442 mov v2.h\[1\], v2.h\[1\]
+ 2a40: 6e061463 mov v3.h\[1\], v3.h\[1\]
+ 2a44: 6e061463 mov v3.h\[1\], v3.h\[1\]
+ 2a48: 6e061484 mov v4.h\[1\], v4.h\[1\]
+ 2a4c: 6e061484 mov v4.h\[1\], v4.h\[1\]
+ 2a50: 6e0614a5 mov v5.h\[1\], v5.h\[1\]
+ 2a54: 6e0614a5 mov v5.h\[1\], v5.h\[1\]
+ 2a58: 6e0614c6 mov v6.h\[1\], v6.h\[1\]
+ 2a5c: 6e0614c6 mov v6.h\[1\], v6.h\[1\]
+ 2a60: 6e0614e7 mov v7.h\[1\], v7.h\[1\]
+ 2a64: 6e0614e7 mov v7.h\[1\], v7.h\[1\]
+ 2a68: 6e061508 mov v8.h\[1\], v8.h\[1\]
+ 2a6c: 6e061508 mov v8.h\[1\], v8.h\[1\]
+ 2a70: 6e061529 mov v9.h\[1\], v9.h\[1\]
+ 2a74: 6e061529 mov v9.h\[1\], v9.h\[1\]
+ 2a78: 6e06154a mov v10.h\[1\], v10.h\[1\]
+ 2a7c: 6e06154a mov v10.h\[1\], v10.h\[1\]
+ 2a80: 6e06156b mov v11.h\[1\], v11.h\[1\]
+ 2a84: 6e06156b mov v11.h\[1\], v11.h\[1\]
+ 2a88: 6e06158c mov v12.h\[1\], v12.h\[1\]
+ 2a8c: 6e06158c mov v12.h\[1\], v12.h\[1\]
+ 2a90: 6e0615ad mov v13.h\[1\], v13.h\[1\]
+ 2a94: 6e0615ad mov v13.h\[1\], v13.h\[1\]
+ 2a98: 6e0615ce mov v14.h\[1\], v14.h\[1\]
+ 2a9c: 6e0615ce mov v14.h\[1\], v14.h\[1\]
+ 2aa0: 6e0615ef mov v15.h\[1\], v15.h\[1\]
+ 2aa4: 6e0615ef mov v15.h\[1\], v15.h\[1\]
+ 2aa8: 6e061610 mov v16.h\[1\], v16.h\[1\]
+ 2aac: 6e061610 mov v16.h\[1\], v16.h\[1\]
+ 2ab0: 6e061631 mov v17.h\[1\], v17.h\[1\]
+ 2ab4: 6e061631 mov v17.h\[1\], v17.h\[1\]
+ 2ab8: 6e061652 mov v18.h\[1\], v18.h\[1\]
+ 2abc: 6e061652 mov v18.h\[1\], v18.h\[1\]
+ 2ac0: 6e061673 mov v19.h\[1\], v19.h\[1\]
+ 2ac4: 6e061673 mov v19.h\[1\], v19.h\[1\]
+ 2ac8: 6e061694 mov v20.h\[1\], v20.h\[1\]
+ 2acc: 6e061694 mov v20.h\[1\], v20.h\[1\]
+ 2ad0: 6e0616b5 mov v21.h\[1\], v21.h\[1\]
+ 2ad4: 6e0616b5 mov v21.h\[1\], v21.h\[1\]
+ 2ad8: 6e0616d6 mov v22.h\[1\], v22.h\[1\]
+ 2adc: 6e0616d6 mov v22.h\[1\], v22.h\[1\]
+ 2ae0: 6e0616f7 mov v23.h\[1\], v23.h\[1\]
+ 2ae4: 6e0616f7 mov v23.h\[1\], v23.h\[1\]
+ 2ae8: 6e061718 mov v24.h\[1\], v24.h\[1\]
+ 2aec: 6e061718 mov v24.h\[1\], v24.h\[1\]
+ 2af0: 6e061739 mov v25.h\[1\], v25.h\[1\]
+ 2af4: 6e061739 mov v25.h\[1\], v25.h\[1\]
+ 2af8: 6e06175a mov v26.h\[1\], v26.h\[1\]
+ 2afc: 6e06175a mov v26.h\[1\], v26.h\[1\]
+ 2b00: 6e06177b mov v27.h\[1\], v27.h\[1\]
+ 2b04: 6e06177b mov v27.h\[1\], v27.h\[1\]
+ 2b08: 6e06179c mov v28.h\[1\], v28.h\[1\]
+ 2b0c: 6e06179c mov v28.h\[1\], v28.h\[1\]
+ 2b10: 6e0617bd mov v29.h\[1\], v29.h\[1\]
+ 2b14: 6e0617bd mov v29.h\[1\], v29.h\[1\]
+ 2b18: 6e0617de mov v30.h\[1\], v30.h\[1\]
+ 2b1c: 6e0617de mov v30.h\[1\], v30.h\[1\]
+ 2b20: 6e0a2421 mov v1.h\[2\], v1.h\[2\]
+ 2b24: 6e0a2421 mov v1.h\[2\], v1.h\[2\]
+ 2b28: 6e0a2442 mov v2.h\[2\], v2.h\[2\]
+ 2b2c: 6e0a2442 mov v2.h\[2\], v2.h\[2\]
+ 2b30: 6e0a2463 mov v3.h\[2\], v3.h\[2\]
+ 2b34: 6e0a2463 mov v3.h\[2\], v3.h\[2\]
+ 2b38: 6e0a2484 mov v4.h\[2\], v4.h\[2\]
+ 2b3c: 6e0a2484 mov v4.h\[2\], v4.h\[2\]
+ 2b40: 6e0a24a5 mov v5.h\[2\], v5.h\[2\]
+ 2b44: 6e0a24a5 mov v5.h\[2\], v5.h\[2\]
+ 2b48: 6e0a24c6 mov v6.h\[2\], v6.h\[2\]
+ 2b4c: 6e0a24c6 mov v6.h\[2\], v6.h\[2\]
+ 2b50: 6e0a24e7 mov v7.h\[2\], v7.h\[2\]
+ 2b54: 6e0a24e7 mov v7.h\[2\], v7.h\[2\]
+ 2b58: 6e0a2508 mov v8.h\[2\], v8.h\[2\]
+ 2b5c: 6e0a2508 mov v8.h\[2\], v8.h\[2\]
+ 2b60: 6e0a2529 mov v9.h\[2\], v9.h\[2\]
+ 2b64: 6e0a2529 mov v9.h\[2\], v9.h\[2\]
+ 2b68: 6e0a254a mov v10.h\[2\], v10.h\[2\]
+ 2b6c: 6e0a254a mov v10.h\[2\], v10.h\[2\]
+ 2b70: 6e0a256b mov v11.h\[2\], v11.h\[2\]
+ 2b74: 6e0a256b mov v11.h\[2\], v11.h\[2\]
+ 2b78: 6e0a258c mov v12.h\[2\], v12.h\[2\]
+ 2b7c: 6e0a258c mov v12.h\[2\], v12.h\[2\]
+ 2b80: 6e0a25ad mov v13.h\[2\], v13.h\[2\]
+ 2b84: 6e0a25ad mov v13.h\[2\], v13.h\[2\]
+ 2b88: 6e0a25ce mov v14.h\[2\], v14.h\[2\]
+ 2b8c: 6e0a25ce mov v14.h\[2\], v14.h\[2\]
+ 2b90: 6e0a25ef mov v15.h\[2\], v15.h\[2\]
+ 2b94: 6e0a25ef mov v15.h\[2\], v15.h\[2\]
+ 2b98: 6e0a2610 mov v16.h\[2\], v16.h\[2\]
+ 2b9c: 6e0a2610 mov v16.h\[2\], v16.h\[2\]
+ 2ba0: 6e0a2631 mov v17.h\[2\], v17.h\[2\]
+ 2ba4: 6e0a2631 mov v17.h\[2\], v17.h\[2\]
+ 2ba8: 6e0a2652 mov v18.h\[2\], v18.h\[2\]
+ 2bac: 6e0a2652 mov v18.h\[2\], v18.h\[2\]
+ 2bb0: 6e0a2673 mov v19.h\[2\], v19.h\[2\]
+ 2bb4: 6e0a2673 mov v19.h\[2\], v19.h\[2\]
+ 2bb8: 6e0a2694 mov v20.h\[2\], v20.h\[2\]
+ 2bbc: 6e0a2694 mov v20.h\[2\], v20.h\[2\]
+ 2bc0: 6e0a26b5 mov v21.h\[2\], v21.h\[2\]
+ 2bc4: 6e0a26b5 mov v21.h\[2\], v21.h\[2\]
+ 2bc8: 6e0a26d6 mov v22.h\[2\], v22.h\[2\]
+ 2bcc: 6e0a26d6 mov v22.h\[2\], v22.h\[2\]
+ 2bd0: 6e0a26f7 mov v23.h\[2\], v23.h\[2\]
+ 2bd4: 6e0a26f7 mov v23.h\[2\], v23.h\[2\]
+ 2bd8: 6e0a2718 mov v24.h\[2\], v24.h\[2\]
+ 2bdc: 6e0a2718 mov v24.h\[2\], v24.h\[2\]
+ 2be0: 6e0a2739 mov v25.h\[2\], v25.h\[2\]
+ 2be4: 6e0a2739 mov v25.h\[2\], v25.h\[2\]
+ 2be8: 6e0a275a mov v26.h\[2\], v26.h\[2\]
+ 2bec: 6e0a275a mov v26.h\[2\], v26.h\[2\]
+ 2bf0: 6e0a277b mov v27.h\[2\], v27.h\[2\]
+ 2bf4: 6e0a277b mov v27.h\[2\], v27.h\[2\]
+ 2bf8: 6e0a279c mov v28.h\[2\], v28.h\[2\]
+ 2bfc: 6e0a279c mov v28.h\[2\], v28.h\[2\]
+ 2c00: 6e0a27bd mov v29.h\[2\], v29.h\[2\]
+ 2c04: 6e0a27bd mov v29.h\[2\], v29.h\[2\]
+ 2c08: 6e0a27de mov v30.h\[2\], v30.h\[2\]
+ 2c0c: 6e0a27de mov v30.h\[2\], v30.h\[2\]
+ 2c10: 6e0e3421 mov v1.h\[3\], v1.h\[3\]
+ 2c14: 6e0e3421 mov v1.h\[3\], v1.h\[3\]
+ 2c18: 6e0e3442 mov v2.h\[3\], v2.h\[3\]
+ 2c1c: 6e0e3442 mov v2.h\[3\], v2.h\[3\]
+ 2c20: 6e0e3463 mov v3.h\[3\], v3.h\[3\]
+ 2c24: 6e0e3463 mov v3.h\[3\], v3.h\[3\]
+ 2c28: 6e0e3484 mov v4.h\[3\], v4.h\[3\]
+ 2c2c: 6e0e3484 mov v4.h\[3\], v4.h\[3\]
+ 2c30: 6e0e34a5 mov v5.h\[3\], v5.h\[3\]
+ 2c34: 6e0e34a5 mov v5.h\[3\], v5.h\[3\]
+ 2c38: 6e0e34c6 mov v6.h\[3\], v6.h\[3\]
+ 2c3c: 6e0e34c6 mov v6.h\[3\], v6.h\[3\]
+ 2c40: 6e0e34e7 mov v7.h\[3\], v7.h\[3\]
+ 2c44: 6e0e34e7 mov v7.h\[3\], v7.h\[3\]
+ 2c48: 6e0e3508 mov v8.h\[3\], v8.h\[3\]
+ 2c4c: 6e0e3508 mov v8.h\[3\], v8.h\[3\]
+ 2c50: 6e0e3529 mov v9.h\[3\], v9.h\[3\]
+ 2c54: 6e0e3529 mov v9.h\[3\], v9.h\[3\]
+ 2c58: 6e0e354a mov v10.h\[3\], v10.h\[3\]
+ 2c5c: 6e0e354a mov v10.h\[3\], v10.h\[3\]
+ 2c60: 6e0e356b mov v11.h\[3\], v11.h\[3\]
+ 2c64: 6e0e356b mov v11.h\[3\], v11.h\[3\]
+ 2c68: 6e0e358c mov v12.h\[3\], v12.h\[3\]
+ 2c6c: 6e0e358c mov v12.h\[3\], v12.h\[3\]
+ 2c70: 6e0e35ad mov v13.h\[3\], v13.h\[3\]
+ 2c74: 6e0e35ad mov v13.h\[3\], v13.h\[3\]
+ 2c78: 6e0e35ce mov v14.h\[3\], v14.h\[3\]
+ 2c7c: 6e0e35ce mov v14.h\[3\], v14.h\[3\]
+ 2c80: 6e0e35ef mov v15.h\[3\], v15.h\[3\]
+ 2c84: 6e0e35ef mov v15.h\[3\], v15.h\[3\]
+ 2c88: 6e0e3610 mov v16.h\[3\], v16.h\[3\]
+ 2c8c: 6e0e3610 mov v16.h\[3\], v16.h\[3\]
+ 2c90: 6e0e3631 mov v17.h\[3\], v17.h\[3\]
+ 2c94: 6e0e3631 mov v17.h\[3\], v17.h\[3\]
+ 2c98: 6e0e3652 mov v18.h\[3\], v18.h\[3\]
+ 2c9c: 6e0e3652 mov v18.h\[3\], v18.h\[3\]
+ 2ca0: 6e0e3673 mov v19.h\[3\], v19.h\[3\]
+ 2ca4: 6e0e3673 mov v19.h\[3\], v19.h\[3\]
+ 2ca8: 6e0e3694 mov v20.h\[3\], v20.h\[3\]
+ 2cac: 6e0e3694 mov v20.h\[3\], v20.h\[3\]
+ 2cb0: 6e0e36b5 mov v21.h\[3\], v21.h\[3\]
+ 2cb4: 6e0e36b5 mov v21.h\[3\], v21.h\[3\]
+ 2cb8: 6e0e36d6 mov v22.h\[3\], v22.h\[3\]
+ 2cbc: 6e0e36d6 mov v22.h\[3\], v22.h\[3\]
+ 2cc0: 6e0e36f7 mov v23.h\[3\], v23.h\[3\]
+ 2cc4: 6e0e36f7 mov v23.h\[3\], v23.h\[3\]
+ 2cc8: 6e0e3718 mov v24.h\[3\], v24.h\[3\]
+ 2ccc: 6e0e3718 mov v24.h\[3\], v24.h\[3\]
+ 2cd0: 6e0e3739 mov v25.h\[3\], v25.h\[3\]
+ 2cd4: 6e0e3739 mov v25.h\[3\], v25.h\[3\]
+ 2cd8: 6e0e375a mov v26.h\[3\], v26.h\[3\]
+ 2cdc: 6e0e375a mov v26.h\[3\], v26.h\[3\]
+ 2ce0: 6e0e377b mov v27.h\[3\], v27.h\[3\]
+ 2ce4: 6e0e377b mov v27.h\[3\], v27.h\[3\]
+ 2ce8: 6e0e379c mov v28.h\[3\], v28.h\[3\]
+ 2cec: 6e0e379c mov v28.h\[3\], v28.h\[3\]
+ 2cf0: 6e0e37bd mov v29.h\[3\], v29.h\[3\]
+ 2cf4: 6e0e37bd mov v29.h\[3\], v29.h\[3\]
+ 2cf8: 6e0e37de mov v30.h\[3\], v30.h\[3\]
+ 2cfc: 6e0e37de mov v30.h\[3\], v30.h\[3\]
+ 2d00: 6e124421 mov v1.h\[4\], v1.h\[4\]
+ 2d04: 6e124421 mov v1.h\[4\], v1.h\[4\]
+ 2d08: 6e124442 mov v2.h\[4\], v2.h\[4\]
+ 2d0c: 6e124442 mov v2.h\[4\], v2.h\[4\]
+ 2d10: 6e124463 mov v3.h\[4\], v3.h\[4\]
+ 2d14: 6e124463 mov v3.h\[4\], v3.h\[4\]
+ 2d18: 6e124484 mov v4.h\[4\], v4.h\[4\]
+ 2d1c: 6e124484 mov v4.h\[4\], v4.h\[4\]
+ 2d20: 6e1244a5 mov v5.h\[4\], v5.h\[4\]
+ 2d24: 6e1244a5 mov v5.h\[4\], v5.h\[4\]
+ 2d28: 6e1244c6 mov v6.h\[4\], v6.h\[4\]
+ 2d2c: 6e1244c6 mov v6.h\[4\], v6.h\[4\]
+ 2d30: 6e1244e7 mov v7.h\[4\], v7.h\[4\]
+ 2d34: 6e1244e7 mov v7.h\[4\], v7.h\[4\]
+ 2d38: 6e124508 mov v8.h\[4\], v8.h\[4\]
+ 2d3c: 6e124508 mov v8.h\[4\], v8.h\[4\]
+ 2d40: 6e124529 mov v9.h\[4\], v9.h\[4\]
+ 2d44: 6e124529 mov v9.h\[4\], v9.h\[4\]
+ 2d48: 6e12454a mov v10.h\[4\], v10.h\[4\]
+ 2d4c: 6e12454a mov v10.h\[4\], v10.h\[4\]
+ 2d50: 6e12456b mov v11.h\[4\], v11.h\[4\]
+ 2d54: 6e12456b mov v11.h\[4\], v11.h\[4\]
+ 2d58: 6e12458c mov v12.h\[4\], v12.h\[4\]
+ 2d5c: 6e12458c mov v12.h\[4\], v12.h\[4\]
+ 2d60: 6e1245ad mov v13.h\[4\], v13.h\[4\]
+ 2d64: 6e1245ad mov v13.h\[4\], v13.h\[4\]
+ 2d68: 6e1245ce mov v14.h\[4\], v14.h\[4\]
+ 2d6c: 6e1245ce mov v14.h\[4\], v14.h\[4\]
+ 2d70: 6e1245ef mov v15.h\[4\], v15.h\[4\]
+ 2d74: 6e1245ef mov v15.h\[4\], v15.h\[4\]
+ 2d78: 6e124610 mov v16.h\[4\], v16.h\[4\]
+ 2d7c: 6e124610 mov v16.h\[4\], v16.h\[4\]
+ 2d80: 6e124631 mov v17.h\[4\], v17.h\[4\]
+ 2d84: 6e124631 mov v17.h\[4\], v17.h\[4\]
+ 2d88: 6e124652 mov v18.h\[4\], v18.h\[4\]
+ 2d8c: 6e124652 mov v18.h\[4\], v18.h\[4\]
+ 2d90: 6e124673 mov v19.h\[4\], v19.h\[4\]
+ 2d94: 6e124673 mov v19.h\[4\], v19.h\[4\]
+ 2d98: 6e124694 mov v20.h\[4\], v20.h\[4\]
+ 2d9c: 6e124694 mov v20.h\[4\], v20.h\[4\]
+ 2da0: 6e1246b5 mov v21.h\[4\], v21.h\[4\]
+ 2da4: 6e1246b5 mov v21.h\[4\], v21.h\[4\]
+ 2da8: 6e1246d6 mov v22.h\[4\], v22.h\[4\]
+ 2dac: 6e1246d6 mov v22.h\[4\], v22.h\[4\]
+ 2db0: 6e1246f7 mov v23.h\[4\], v23.h\[4\]
+ 2db4: 6e1246f7 mov v23.h\[4\], v23.h\[4\]
+ 2db8: 6e124718 mov v24.h\[4\], v24.h\[4\]
+ 2dbc: 6e124718 mov v24.h\[4\], v24.h\[4\]
+ 2dc0: 6e124739 mov v25.h\[4\], v25.h\[4\]
+ 2dc4: 6e124739 mov v25.h\[4\], v25.h\[4\]
+ 2dc8: 6e12475a mov v26.h\[4\], v26.h\[4\]
+ 2dcc: 6e12475a mov v26.h\[4\], v26.h\[4\]
+ 2dd0: 6e12477b mov v27.h\[4\], v27.h\[4\]
+ 2dd4: 6e12477b mov v27.h\[4\], v27.h\[4\]
+ 2dd8: 6e12479c mov v28.h\[4\], v28.h\[4\]
+ 2ddc: 6e12479c mov v28.h\[4\], v28.h\[4\]
+ 2de0: 6e1247bd mov v29.h\[4\], v29.h\[4\]
+ 2de4: 6e1247bd mov v29.h\[4\], v29.h\[4\]
+ 2de8: 6e1247de mov v30.h\[4\], v30.h\[4\]
+ 2dec: 6e1247de mov v30.h\[4\], v30.h\[4\]
+ 2df0: 6e165421 mov v1.h\[5\], v1.h\[5\]
+ 2df4: 6e165421 mov v1.h\[5\], v1.h\[5\]
+ 2df8: 6e165442 mov v2.h\[5\], v2.h\[5\]
+ 2dfc: 6e165442 mov v2.h\[5\], v2.h\[5\]
+ 2e00: 6e165463 mov v3.h\[5\], v3.h\[5\]
+ 2e04: 6e165463 mov v3.h\[5\], v3.h\[5\]
+ 2e08: 6e165484 mov v4.h\[5\], v4.h\[5\]
+ 2e0c: 6e165484 mov v4.h\[5\], v4.h\[5\]
+ 2e10: 6e1654a5 mov v5.h\[5\], v5.h\[5\]
+ 2e14: 6e1654a5 mov v5.h\[5\], v5.h\[5\]
+ 2e18: 6e1654c6 mov v6.h\[5\], v6.h\[5\]
+ 2e1c: 6e1654c6 mov v6.h\[5\], v6.h\[5\]
+ 2e20: 6e1654e7 mov v7.h\[5\], v7.h\[5\]
+ 2e24: 6e1654e7 mov v7.h\[5\], v7.h\[5\]
+ 2e28: 6e165508 mov v8.h\[5\], v8.h\[5\]
+ 2e2c: 6e165508 mov v8.h\[5\], v8.h\[5\]
+ 2e30: 6e165529 mov v9.h\[5\], v9.h\[5\]
+ 2e34: 6e165529 mov v9.h\[5\], v9.h\[5\]
+ 2e38: 6e16554a mov v10.h\[5\], v10.h\[5\]
+ 2e3c: 6e16554a mov v10.h\[5\], v10.h\[5\]
+ 2e40: 6e16556b mov v11.h\[5\], v11.h\[5\]
+ 2e44: 6e16556b mov v11.h\[5\], v11.h\[5\]
+ 2e48: 6e16558c mov v12.h\[5\], v12.h\[5\]
+ 2e4c: 6e16558c mov v12.h\[5\], v12.h\[5\]
+ 2e50: 6e1655ad mov v13.h\[5\], v13.h\[5\]
+ 2e54: 6e1655ad mov v13.h\[5\], v13.h\[5\]
+ 2e58: 6e1655ce mov v14.h\[5\], v14.h\[5\]
+ 2e5c: 6e1655ce mov v14.h\[5\], v14.h\[5\]
+ 2e60: 6e1655ef mov v15.h\[5\], v15.h\[5\]
+ 2e64: 6e1655ef mov v15.h\[5\], v15.h\[5\]
+ 2e68: 6e165610 mov v16.h\[5\], v16.h\[5\]
+ 2e6c: 6e165610 mov v16.h\[5\], v16.h\[5\]
+ 2e70: 6e165631 mov v17.h\[5\], v17.h\[5\]
+ 2e74: 6e165631 mov v17.h\[5\], v17.h\[5\]
+ 2e78: 6e165652 mov v18.h\[5\], v18.h\[5\]
+ 2e7c: 6e165652 mov v18.h\[5\], v18.h\[5\]
+ 2e80: 6e165673 mov v19.h\[5\], v19.h\[5\]
+ 2e84: 6e165673 mov v19.h\[5\], v19.h\[5\]
+ 2e88: 6e165694 mov v20.h\[5\], v20.h\[5\]
+ 2e8c: 6e165694 mov v20.h\[5\], v20.h\[5\]
+ 2e90: 6e1656b5 mov v21.h\[5\], v21.h\[5\]
+ 2e94: 6e1656b5 mov v21.h\[5\], v21.h\[5\]
+ 2e98: 6e1656d6 mov v22.h\[5\], v22.h\[5\]
+ 2e9c: 6e1656d6 mov v22.h\[5\], v22.h\[5\]
+ 2ea0: 6e1656f7 mov v23.h\[5\], v23.h\[5\]
+ 2ea4: 6e1656f7 mov v23.h\[5\], v23.h\[5\]
+ 2ea8: 6e165718 mov v24.h\[5\], v24.h\[5\]
+ 2eac: 6e165718 mov v24.h\[5\], v24.h\[5\]
+ 2eb0: 6e165739 mov v25.h\[5\], v25.h\[5\]
+ 2eb4: 6e165739 mov v25.h\[5\], v25.h\[5\]
+ 2eb8: 6e16575a mov v26.h\[5\], v26.h\[5\]
+ 2ebc: 6e16575a mov v26.h\[5\], v26.h\[5\]
+ 2ec0: 6e16577b mov v27.h\[5\], v27.h\[5\]
+ 2ec4: 6e16577b mov v27.h\[5\], v27.h\[5\]
+ 2ec8: 6e16579c mov v28.h\[5\], v28.h\[5\]
+ 2ecc: 6e16579c mov v28.h\[5\], v28.h\[5\]
+ 2ed0: 6e1657bd mov v29.h\[5\], v29.h\[5\]
+ 2ed4: 6e1657bd mov v29.h\[5\], v29.h\[5\]
+ 2ed8: 6e1657de mov v30.h\[5\], v30.h\[5\]
+ 2edc: 6e1657de mov v30.h\[5\], v30.h\[5\]
+ 2ee0: 6e1a6421 mov v1.h\[6\], v1.h\[6\]
+ 2ee4: 6e1a6421 mov v1.h\[6\], v1.h\[6\]
+ 2ee8: 6e1a6442 mov v2.h\[6\], v2.h\[6\]
+ 2eec: 6e1a6442 mov v2.h\[6\], v2.h\[6\]
+ 2ef0: 6e1a6463 mov v3.h\[6\], v3.h\[6\]
+ 2ef4: 6e1a6463 mov v3.h\[6\], v3.h\[6\]
+ 2ef8: 6e1a6484 mov v4.h\[6\], v4.h\[6\]
+ 2efc: 6e1a6484 mov v4.h\[6\], v4.h\[6\]
+ 2f00: 6e1a64a5 mov v5.h\[6\], v5.h\[6\]
+ 2f04: 6e1a64a5 mov v5.h\[6\], v5.h\[6\]
+ 2f08: 6e1a64c6 mov v6.h\[6\], v6.h\[6\]
+ 2f0c: 6e1a64c6 mov v6.h\[6\], v6.h\[6\]
+ 2f10: 6e1a64e7 mov v7.h\[6\], v7.h\[6\]
+ 2f14: 6e1a64e7 mov v7.h\[6\], v7.h\[6\]
+ 2f18: 6e1a6508 mov v8.h\[6\], v8.h\[6\]
+ 2f1c: 6e1a6508 mov v8.h\[6\], v8.h\[6\]
+ 2f20: 6e1a6529 mov v9.h\[6\], v9.h\[6\]
+ 2f24: 6e1a6529 mov v9.h\[6\], v9.h\[6\]
+ 2f28: 6e1a654a mov v10.h\[6\], v10.h\[6\]
+ 2f2c: 6e1a654a mov v10.h\[6\], v10.h\[6\]
+ 2f30: 6e1a656b mov v11.h\[6\], v11.h\[6\]
+ 2f34: 6e1a656b mov v11.h\[6\], v11.h\[6\]
+ 2f38: 6e1a658c mov v12.h\[6\], v12.h\[6\]
+ 2f3c: 6e1a658c mov v12.h\[6\], v12.h\[6\]
+ 2f40: 6e1a65ad mov v13.h\[6\], v13.h\[6\]
+ 2f44: 6e1a65ad mov v13.h\[6\], v13.h\[6\]
+ 2f48: 6e1a65ce mov v14.h\[6\], v14.h\[6\]
+ 2f4c: 6e1a65ce mov v14.h\[6\], v14.h\[6\]
+ 2f50: 6e1a65ef mov v15.h\[6\], v15.h\[6\]
+ 2f54: 6e1a65ef mov v15.h\[6\], v15.h\[6\]
+ 2f58: 6e1a6610 mov v16.h\[6\], v16.h\[6\]
+ 2f5c: 6e1a6610 mov v16.h\[6\], v16.h\[6\]
+ 2f60: 6e1a6631 mov v17.h\[6\], v17.h\[6\]
+ 2f64: 6e1a6631 mov v17.h\[6\], v17.h\[6\]
+ 2f68: 6e1a6652 mov v18.h\[6\], v18.h\[6\]
+ 2f6c: 6e1a6652 mov v18.h\[6\], v18.h\[6\]
+ 2f70: 6e1a6673 mov v19.h\[6\], v19.h\[6\]
+ 2f74: 6e1a6673 mov v19.h\[6\], v19.h\[6\]
+ 2f78: 6e1a6694 mov v20.h\[6\], v20.h\[6\]
+ 2f7c: 6e1a6694 mov v20.h\[6\], v20.h\[6\]
+ 2f80: 6e1a66b5 mov v21.h\[6\], v21.h\[6\]
+ 2f84: 6e1a66b5 mov v21.h\[6\], v21.h\[6\]
+ 2f88: 6e1a66d6 mov v22.h\[6\], v22.h\[6\]
+ 2f8c: 6e1a66d6 mov v22.h\[6\], v22.h\[6\]
+ 2f90: 6e1a66f7 mov v23.h\[6\], v23.h\[6\]
+ 2f94: 6e1a66f7 mov v23.h\[6\], v23.h\[6\]
+ 2f98: 6e1a6718 mov v24.h\[6\], v24.h\[6\]
+ 2f9c: 6e1a6718 mov v24.h\[6\], v24.h\[6\]
+ 2fa0: 6e1a6739 mov v25.h\[6\], v25.h\[6\]
+ 2fa4: 6e1a6739 mov v25.h\[6\], v25.h\[6\]
+ 2fa8: 6e1a675a mov v26.h\[6\], v26.h\[6\]
+ 2fac: 6e1a675a mov v26.h\[6\], v26.h\[6\]
+ 2fb0: 6e1a677b mov v27.h\[6\], v27.h\[6\]
+ 2fb4: 6e1a677b mov v27.h\[6\], v27.h\[6\]
+ 2fb8: 6e1a679c mov v28.h\[6\], v28.h\[6\]
+ 2fbc: 6e1a679c mov v28.h\[6\], v28.h\[6\]
+ 2fc0: 6e1a67bd mov v29.h\[6\], v29.h\[6\]
+ 2fc4: 6e1a67bd mov v29.h\[6\], v29.h\[6\]
+ 2fc8: 6e1a67de mov v30.h\[6\], v30.h\[6\]
+ 2fcc: 6e1a67de mov v30.h\[6\], v30.h\[6\]
+ 2fd0: 6e1e7421 mov v1.h\[7\], v1.h\[7\]
+ 2fd4: 6e1e7421 mov v1.h\[7\], v1.h\[7\]
+ 2fd8: 6e1e7442 mov v2.h\[7\], v2.h\[7\]
+ 2fdc: 6e1e7442 mov v2.h\[7\], v2.h\[7\]
+ 2fe0: 6e1e7463 mov v3.h\[7\], v3.h\[7\]
+ 2fe4: 6e1e7463 mov v3.h\[7\], v3.h\[7\]
+ 2fe8: 6e1e7484 mov v4.h\[7\], v4.h\[7\]
+ 2fec: 6e1e7484 mov v4.h\[7\], v4.h\[7\]
+ 2ff0: 6e1e74a5 mov v5.h\[7\], v5.h\[7\]
+ 2ff4: 6e1e74a5 mov v5.h\[7\], v5.h\[7\]
+ 2ff8: 6e1e74c6 mov v6.h\[7\], v6.h\[7\]
+ 2ffc: 6e1e74c6 mov v6.h\[7\], v6.h\[7\]
+ 3000: 6e1e74e7 mov v7.h\[7\], v7.h\[7\]
+ 3004: 6e1e74e7 mov v7.h\[7\], v7.h\[7\]
+ 3008: 6e1e7508 mov v8.h\[7\], v8.h\[7\]
+ 300c: 6e1e7508 mov v8.h\[7\], v8.h\[7\]
+ 3010: 6e1e7529 mov v9.h\[7\], v9.h\[7\]
+ 3014: 6e1e7529 mov v9.h\[7\], v9.h\[7\]
+ 3018: 6e1e754a mov v10.h\[7\], v10.h\[7\]
+ 301c: 6e1e754a mov v10.h\[7\], v10.h\[7\]
+ 3020: 6e1e756b mov v11.h\[7\], v11.h\[7\]
+ 3024: 6e1e756b mov v11.h\[7\], v11.h\[7\]
+ 3028: 6e1e758c mov v12.h\[7\], v12.h\[7\]
+ 302c: 6e1e758c mov v12.h\[7\], v12.h\[7\]
+ 3030: 6e1e75ad mov v13.h\[7\], v13.h\[7\]
+ 3034: 6e1e75ad mov v13.h\[7\], v13.h\[7\]
+ 3038: 6e1e75ce mov v14.h\[7\], v14.h\[7\]
+ 303c: 6e1e75ce mov v14.h\[7\], v14.h\[7\]
+ 3040: 6e1e75ef mov v15.h\[7\], v15.h\[7\]
+ 3044: 6e1e75ef mov v15.h\[7\], v15.h\[7\]
+ 3048: 6e1e7610 mov v16.h\[7\], v16.h\[7\]
+ 304c: 6e1e7610 mov v16.h\[7\], v16.h\[7\]
+ 3050: 6e1e7631 mov v17.h\[7\], v17.h\[7\]
+ 3054: 6e1e7631 mov v17.h\[7\], v17.h\[7\]
+ 3058: 6e1e7652 mov v18.h\[7\], v18.h\[7\]
+ 305c: 6e1e7652 mov v18.h\[7\], v18.h\[7\]
+ 3060: 6e1e7673 mov v19.h\[7\], v19.h\[7\]
+ 3064: 6e1e7673 mov v19.h\[7\], v19.h\[7\]
+ 3068: 6e1e7694 mov v20.h\[7\], v20.h\[7\]
+ 306c: 6e1e7694 mov v20.h\[7\], v20.h\[7\]
+ 3070: 6e1e76b5 mov v21.h\[7\], v21.h\[7\]
+ 3074: 6e1e76b5 mov v21.h\[7\], v21.h\[7\]
+ 3078: 6e1e76d6 mov v22.h\[7\], v22.h\[7\]
+ 307c: 6e1e76d6 mov v22.h\[7\], v22.h\[7\]
+ 3080: 6e1e76f7 mov v23.h\[7\], v23.h\[7\]
+ 3084: 6e1e76f7 mov v23.h\[7\], v23.h\[7\]
+ 3088: 6e1e7718 mov v24.h\[7\], v24.h\[7\]
+ 308c: 6e1e7718 mov v24.h\[7\], v24.h\[7\]
+ 3090: 6e1e7739 mov v25.h\[7\], v25.h\[7\]
+ 3094: 6e1e7739 mov v25.h\[7\], v25.h\[7\]
+ 3098: 6e1e775a mov v26.h\[7\], v26.h\[7\]
+ 309c: 6e1e775a mov v26.h\[7\], v26.h\[7\]
+ 30a0: 6e1e777b mov v27.h\[7\], v27.h\[7\]
+ 30a4: 6e1e777b mov v27.h\[7\], v27.h\[7\]
+ 30a8: 6e1e779c mov v28.h\[7\], v28.h\[7\]
+ 30ac: 6e1e779c mov v28.h\[7\], v28.h\[7\]
+ 30b0: 6e1e77bd mov v29.h\[7\], v29.h\[7\]
+ 30b4: 6e1e77bd mov v29.h\[7\], v29.h\[7\]
+ 30b8: 6e1e77de mov v30.h\[7\], v30.h\[7\]
+ 30bc: 6e1e77de mov v30.h\[7\], v30.h\[7\]
+ 30c0: 6e040421 mov v1.s\[0\], v1.s\[0\]
+ 30c4: 6e040421 mov v1.s\[0\], v1.s\[0\]
+ 30c8: 6e040442 mov v2.s\[0\], v2.s\[0\]
+ 30cc: 6e040442 mov v2.s\[0\], v2.s\[0\]
+ 30d0: 6e040463 mov v3.s\[0\], v3.s\[0\]
+ 30d4: 6e040463 mov v3.s\[0\], v3.s\[0\]
+ 30d8: 6e040484 mov v4.s\[0\], v4.s\[0\]
+ 30dc: 6e040484 mov v4.s\[0\], v4.s\[0\]
+ 30e0: 6e0404a5 mov v5.s\[0\], v5.s\[0\]
+ 30e4: 6e0404a5 mov v5.s\[0\], v5.s\[0\]
+ 30e8: 6e0404c6 mov v6.s\[0\], v6.s\[0\]
+ 30ec: 6e0404c6 mov v6.s\[0\], v6.s\[0\]
+ 30f0: 6e0404e7 mov v7.s\[0\], v7.s\[0\]
+ 30f4: 6e0404e7 mov v7.s\[0\], v7.s\[0\]
+ 30f8: 6e040508 mov v8.s\[0\], v8.s\[0\]
+ 30fc: 6e040508 mov v8.s\[0\], v8.s\[0\]
+ 3100: 6e040529 mov v9.s\[0\], v9.s\[0\]
+ 3104: 6e040529 mov v9.s\[0\], v9.s\[0\]
+ 3108: 6e04054a mov v10.s\[0\], v10.s\[0\]
+ 310c: 6e04054a mov v10.s\[0\], v10.s\[0\]
+ 3110: 6e04056b mov v11.s\[0\], v11.s\[0\]
+ 3114: 6e04056b mov v11.s\[0\], v11.s\[0\]
+ 3118: 6e04058c mov v12.s\[0\], v12.s\[0\]
+ 311c: 6e04058c mov v12.s\[0\], v12.s\[0\]
+ 3120: 6e0405ad mov v13.s\[0\], v13.s\[0\]
+ 3124: 6e0405ad mov v13.s\[0\], v13.s\[0\]
+ 3128: 6e0405ce mov v14.s\[0\], v14.s\[0\]
+ 312c: 6e0405ce mov v14.s\[0\], v14.s\[0\]
+ 3130: 6e0405ef mov v15.s\[0\], v15.s\[0\]
+ 3134: 6e0405ef mov v15.s\[0\], v15.s\[0\]
+ 3138: 6e040610 mov v16.s\[0\], v16.s\[0\]
+ 313c: 6e040610 mov v16.s\[0\], v16.s\[0\]
+ 3140: 6e040631 mov v17.s\[0\], v17.s\[0\]
+ 3144: 6e040631 mov v17.s\[0\], v17.s\[0\]
+ 3148: 6e040652 mov v18.s\[0\], v18.s\[0\]
+ 314c: 6e040652 mov v18.s\[0\], v18.s\[0\]
+ 3150: 6e040673 mov v19.s\[0\], v19.s\[0\]
+ 3154: 6e040673 mov v19.s\[0\], v19.s\[0\]
+ 3158: 6e040694 mov v20.s\[0\], v20.s\[0\]
+ 315c: 6e040694 mov v20.s\[0\], v20.s\[0\]
+ 3160: 6e0406b5 mov v21.s\[0\], v21.s\[0\]
+ 3164: 6e0406b5 mov v21.s\[0\], v21.s\[0\]
+ 3168: 6e0406d6 mov v22.s\[0\], v22.s\[0\]
+ 316c: 6e0406d6 mov v22.s\[0\], v22.s\[0\]
+ 3170: 6e0406f7 mov v23.s\[0\], v23.s\[0\]
+ 3174: 6e0406f7 mov v23.s\[0\], v23.s\[0\]
+ 3178: 6e040718 mov v24.s\[0\], v24.s\[0\]
+ 317c: 6e040718 mov v24.s\[0\], v24.s\[0\]
+ 3180: 6e040739 mov v25.s\[0\], v25.s\[0\]
+ 3184: 6e040739 mov v25.s\[0\], v25.s\[0\]
+ 3188: 6e04075a mov v26.s\[0\], v26.s\[0\]
+ 318c: 6e04075a mov v26.s\[0\], v26.s\[0\]
+ 3190: 6e04077b mov v27.s\[0\], v27.s\[0\]
+ 3194: 6e04077b mov v27.s\[0\], v27.s\[0\]
+ 3198: 6e04079c mov v28.s\[0\], v28.s\[0\]
+ 319c: 6e04079c mov v28.s\[0\], v28.s\[0\]
+ 31a0: 6e0407bd mov v29.s\[0\], v29.s\[0\]
+ 31a4: 6e0407bd mov v29.s\[0\], v29.s\[0\]
+ 31a8: 6e0407de mov v30.s\[0\], v30.s\[0\]
+ 31ac: 6e0407de mov v30.s\[0\], v30.s\[0\]
+ 31b0: 6e0c2421 mov v1.s\[1\], v1.s\[1\]
+ 31b4: 6e0c2421 mov v1.s\[1\], v1.s\[1\]
+ 31b8: 6e0c2442 mov v2.s\[1\], v2.s\[1\]
+ 31bc: 6e0c2442 mov v2.s\[1\], v2.s\[1\]
+ 31c0: 6e0c2463 mov v3.s\[1\], v3.s\[1\]
+ 31c4: 6e0c2463 mov v3.s\[1\], v3.s\[1\]
+ 31c8: 6e0c2484 mov v4.s\[1\], v4.s\[1\]
+ 31cc: 6e0c2484 mov v4.s\[1\], v4.s\[1\]
+ 31d0: 6e0c24a5 mov v5.s\[1\], v5.s\[1\]
+ 31d4: 6e0c24a5 mov v5.s\[1\], v5.s\[1\]
+ 31d8: 6e0c24c6 mov v6.s\[1\], v6.s\[1\]
+ 31dc: 6e0c24c6 mov v6.s\[1\], v6.s\[1\]
+ 31e0: 6e0c24e7 mov v7.s\[1\], v7.s\[1\]
+ 31e4: 6e0c24e7 mov v7.s\[1\], v7.s\[1\]
+ 31e8: 6e0c2508 mov v8.s\[1\], v8.s\[1\]
+ 31ec: 6e0c2508 mov v8.s\[1\], v8.s\[1\]
+ 31f0: 6e0c2529 mov v9.s\[1\], v9.s\[1\]
+ 31f4: 6e0c2529 mov v9.s\[1\], v9.s\[1\]
+ 31f8: 6e0c254a mov v10.s\[1\], v10.s\[1\]
+ 31fc: 6e0c254a mov v10.s\[1\], v10.s\[1\]
+ 3200: 6e0c256b mov v11.s\[1\], v11.s\[1\]
+ 3204: 6e0c256b mov v11.s\[1\], v11.s\[1\]
+ 3208: 6e0c258c mov v12.s\[1\], v12.s\[1\]
+ 320c: 6e0c258c mov v12.s\[1\], v12.s\[1\]
+ 3210: 6e0c25ad mov v13.s\[1\], v13.s\[1\]
+ 3214: 6e0c25ad mov v13.s\[1\], v13.s\[1\]
+ 3218: 6e0c25ce mov v14.s\[1\], v14.s\[1\]
+ 321c: 6e0c25ce mov v14.s\[1\], v14.s\[1\]
+ 3220: 6e0c25ef mov v15.s\[1\], v15.s\[1\]
+ 3224: 6e0c25ef mov v15.s\[1\], v15.s\[1\]
+ 3228: 6e0c2610 mov v16.s\[1\], v16.s\[1\]
+ 322c: 6e0c2610 mov v16.s\[1\], v16.s\[1\]
+ 3230: 6e0c2631 mov v17.s\[1\], v17.s\[1\]
+ 3234: 6e0c2631 mov v17.s\[1\], v17.s\[1\]
+ 3238: 6e0c2652 mov v18.s\[1\], v18.s\[1\]
+ 323c: 6e0c2652 mov v18.s\[1\], v18.s\[1\]
+ 3240: 6e0c2673 mov v19.s\[1\], v19.s\[1\]
+ 3244: 6e0c2673 mov v19.s\[1\], v19.s\[1\]
+ 3248: 6e0c2694 mov v20.s\[1\], v20.s\[1\]
+ 324c: 6e0c2694 mov v20.s\[1\], v20.s\[1\]
+ 3250: 6e0c26b5 mov v21.s\[1\], v21.s\[1\]
+ 3254: 6e0c26b5 mov v21.s\[1\], v21.s\[1\]
+ 3258: 6e0c26d6 mov v22.s\[1\], v22.s\[1\]
+ 325c: 6e0c26d6 mov v22.s\[1\], v22.s\[1\]
+ 3260: 6e0c26f7 mov v23.s\[1\], v23.s\[1\]
+ 3264: 6e0c26f7 mov v23.s\[1\], v23.s\[1\]
+ 3268: 6e0c2718 mov v24.s\[1\], v24.s\[1\]
+ 326c: 6e0c2718 mov v24.s\[1\], v24.s\[1\]
+ 3270: 6e0c2739 mov v25.s\[1\], v25.s\[1\]
+ 3274: 6e0c2739 mov v25.s\[1\], v25.s\[1\]
+ 3278: 6e0c275a mov v26.s\[1\], v26.s\[1\]
+ 327c: 6e0c275a mov v26.s\[1\], v26.s\[1\]
+ 3280: 6e0c277b mov v27.s\[1\], v27.s\[1\]
+ 3284: 6e0c277b mov v27.s\[1\], v27.s\[1\]
+ 3288: 6e0c279c mov v28.s\[1\], v28.s\[1\]
+ 328c: 6e0c279c mov v28.s\[1\], v28.s\[1\]
+ 3290: 6e0c27bd mov v29.s\[1\], v29.s\[1\]
+ 3294: 6e0c27bd mov v29.s\[1\], v29.s\[1\]
+ 3298: 6e0c27de mov v30.s\[1\], v30.s\[1\]
+ 329c: 6e0c27de mov v30.s\[1\], v30.s\[1\]
+ 32a0: 6e144421 mov v1.s\[2\], v1.s\[2\]
+ 32a4: 6e144421 mov v1.s\[2\], v1.s\[2\]
+ 32a8: 6e144442 mov v2.s\[2\], v2.s\[2\]
+ 32ac: 6e144442 mov v2.s\[2\], v2.s\[2\]
+ 32b0: 6e144463 mov v3.s\[2\], v3.s\[2\]
+ 32b4: 6e144463 mov v3.s\[2\], v3.s\[2\]
+ 32b8: 6e144484 mov v4.s\[2\], v4.s\[2\]
+ 32bc: 6e144484 mov v4.s\[2\], v4.s\[2\]
+ 32c0: 6e1444a5 mov v5.s\[2\], v5.s\[2\]
+ 32c4: 6e1444a5 mov v5.s\[2\], v5.s\[2\]
+ 32c8: 6e1444c6 mov v6.s\[2\], v6.s\[2\]
+ 32cc: 6e1444c6 mov v6.s\[2\], v6.s\[2\]
+ 32d0: 6e1444e7 mov v7.s\[2\], v7.s\[2\]
+ 32d4: 6e1444e7 mov v7.s\[2\], v7.s\[2\]
+ 32d8: 6e144508 mov v8.s\[2\], v8.s\[2\]
+ 32dc: 6e144508 mov v8.s\[2\], v8.s\[2\]
+ 32e0: 6e144529 mov v9.s\[2\], v9.s\[2\]
+ 32e4: 6e144529 mov v9.s\[2\], v9.s\[2\]
+ 32e8: 6e14454a mov v10.s\[2\], v10.s\[2\]
+ 32ec: 6e14454a mov v10.s\[2\], v10.s\[2\]
+ 32f0: 6e14456b mov v11.s\[2\], v11.s\[2\]
+ 32f4: 6e14456b mov v11.s\[2\], v11.s\[2\]
+ 32f8: 6e14458c mov v12.s\[2\], v12.s\[2\]
+ 32fc: 6e14458c mov v12.s\[2\], v12.s\[2\]
+ 3300: 6e1445ad mov v13.s\[2\], v13.s\[2\]
+ 3304: 6e1445ad mov v13.s\[2\], v13.s\[2\]
+ 3308: 6e1445ce mov v14.s\[2\], v14.s\[2\]
+ 330c: 6e1445ce mov v14.s\[2\], v14.s\[2\]
+ 3310: 6e1445ef mov v15.s\[2\], v15.s\[2\]
+ 3314: 6e1445ef mov v15.s\[2\], v15.s\[2\]
+ 3318: 6e144610 mov v16.s\[2\], v16.s\[2\]
+ 331c: 6e144610 mov v16.s\[2\], v16.s\[2\]
+ 3320: 6e144631 mov v17.s\[2\], v17.s\[2\]
+ 3324: 6e144631 mov v17.s\[2\], v17.s\[2\]
+ 3328: 6e144652 mov v18.s\[2\], v18.s\[2\]
+ 332c: 6e144652 mov v18.s\[2\], v18.s\[2\]
+ 3330: 6e144673 mov v19.s\[2\], v19.s\[2\]
+ 3334: 6e144673 mov v19.s\[2\], v19.s\[2\]
+ 3338: 6e144694 mov v20.s\[2\], v20.s\[2\]
+ 333c: 6e144694 mov v20.s\[2\], v20.s\[2\]
+ 3340: 6e1446b5 mov v21.s\[2\], v21.s\[2\]
+ 3344: 6e1446b5 mov v21.s\[2\], v21.s\[2\]
+ 3348: 6e1446d6 mov v22.s\[2\], v22.s\[2\]
+ 334c: 6e1446d6 mov v22.s\[2\], v22.s\[2\]
+ 3350: 6e1446f7 mov v23.s\[2\], v23.s\[2\]
+ 3354: 6e1446f7 mov v23.s\[2\], v23.s\[2\]
+ 3358: 6e144718 mov v24.s\[2\], v24.s\[2\]
+ 335c: 6e144718 mov v24.s\[2\], v24.s\[2\]
+ 3360: 6e144739 mov v25.s\[2\], v25.s\[2\]
+ 3364: 6e144739 mov v25.s\[2\], v25.s\[2\]
+ 3368: 6e14475a mov v26.s\[2\], v26.s\[2\]
+ 336c: 6e14475a mov v26.s\[2\], v26.s\[2\]
+ 3370: 6e14477b mov v27.s\[2\], v27.s\[2\]
+ 3374: 6e14477b mov v27.s\[2\], v27.s\[2\]
+ 3378: 6e14479c mov v28.s\[2\], v28.s\[2\]
+ 337c: 6e14479c mov v28.s\[2\], v28.s\[2\]
+ 3380: 6e1447bd mov v29.s\[2\], v29.s\[2\]
+ 3384: 6e1447bd mov v29.s\[2\], v29.s\[2\]
+ 3388: 6e1447de mov v30.s\[2\], v30.s\[2\]
+ 338c: 6e1447de mov v30.s\[2\], v30.s\[2\]
+ 3390: 6e1c6421 mov v1.s\[3\], v1.s\[3\]
+ 3394: 6e1c6421 mov v1.s\[3\], v1.s\[3\]
+ 3398: 6e1c6442 mov v2.s\[3\], v2.s\[3\]
+ 339c: 6e1c6442 mov v2.s\[3\], v2.s\[3\]
+ 33a0: 6e1c6463 mov v3.s\[3\], v3.s\[3\]
+ 33a4: 6e1c6463 mov v3.s\[3\], v3.s\[3\]
+ 33a8: 6e1c6484 mov v4.s\[3\], v4.s\[3\]
+ 33ac: 6e1c6484 mov v4.s\[3\], v4.s\[3\]
+ 33b0: 6e1c64a5 mov v5.s\[3\], v5.s\[3\]
+ 33b4: 6e1c64a5 mov v5.s\[3\], v5.s\[3\]
+ 33b8: 6e1c64c6 mov v6.s\[3\], v6.s\[3\]
+ 33bc: 6e1c64c6 mov v6.s\[3\], v6.s\[3\]
+ 33c0: 6e1c64e7 mov v7.s\[3\], v7.s\[3\]
+ 33c4: 6e1c64e7 mov v7.s\[3\], v7.s\[3\]
+ 33c8: 6e1c6508 mov v8.s\[3\], v8.s\[3\]
+ 33cc: 6e1c6508 mov v8.s\[3\], v8.s\[3\]
+ 33d0: 6e1c6529 mov v9.s\[3\], v9.s\[3\]
+ 33d4: 6e1c6529 mov v9.s\[3\], v9.s\[3\]
+ 33d8: 6e1c654a mov v10.s\[3\], v10.s\[3\]
+ 33dc: 6e1c654a mov v10.s\[3\], v10.s\[3\]
+ 33e0: 6e1c656b mov v11.s\[3\], v11.s\[3\]
+ 33e4: 6e1c656b mov v11.s\[3\], v11.s\[3\]
+ 33e8: 6e1c658c mov v12.s\[3\], v12.s\[3\]
+ 33ec: 6e1c658c mov v12.s\[3\], v12.s\[3\]
+ 33f0: 6e1c65ad mov v13.s\[3\], v13.s\[3\]
+ 33f4: 6e1c65ad mov v13.s\[3\], v13.s\[3\]
+ 33f8: 6e1c65ce mov v14.s\[3\], v14.s\[3\]
+ 33fc: 6e1c65ce mov v14.s\[3\], v14.s\[3\]
+ 3400: 6e1c65ef mov v15.s\[3\], v15.s\[3\]
+ 3404: 6e1c65ef mov v15.s\[3\], v15.s\[3\]
+ 3408: 6e1c6610 mov v16.s\[3\], v16.s\[3\]
+ 340c: 6e1c6610 mov v16.s\[3\], v16.s\[3\]
+ 3410: 6e1c6631 mov v17.s\[3\], v17.s\[3\]
+ 3414: 6e1c6631 mov v17.s\[3\], v17.s\[3\]
+ 3418: 6e1c6652 mov v18.s\[3\], v18.s\[3\]
+ 341c: 6e1c6652 mov v18.s\[3\], v18.s\[3\]
+ 3420: 6e1c6673 mov v19.s\[3\], v19.s\[3\]
+ 3424: 6e1c6673 mov v19.s\[3\], v19.s\[3\]
+ 3428: 6e1c6694 mov v20.s\[3\], v20.s\[3\]
+ 342c: 6e1c6694 mov v20.s\[3\], v20.s\[3\]
+ 3430: 6e1c66b5 mov v21.s\[3\], v21.s\[3\]
+ 3434: 6e1c66b5 mov v21.s\[3\], v21.s\[3\]
+ 3438: 6e1c66d6 mov v22.s\[3\], v22.s\[3\]
+ 343c: 6e1c66d6 mov v22.s\[3\], v22.s\[3\]
+ 3440: 6e1c66f7 mov v23.s\[3\], v23.s\[3\]
+ 3444: 6e1c66f7 mov v23.s\[3\], v23.s\[3\]
+ 3448: 6e1c6718 mov v24.s\[3\], v24.s\[3\]
+ 344c: 6e1c6718 mov v24.s\[3\], v24.s\[3\]
+ 3450: 6e1c6739 mov v25.s\[3\], v25.s\[3\]
+ 3454: 6e1c6739 mov v25.s\[3\], v25.s\[3\]
+ 3458: 6e1c675a mov v26.s\[3\], v26.s\[3\]
+ 345c: 6e1c675a mov v26.s\[3\], v26.s\[3\]
+ 3460: 6e1c677b mov v27.s\[3\], v27.s\[3\]
+ 3464: 6e1c677b mov v27.s\[3\], v27.s\[3\]
+ 3468: 6e1c679c mov v28.s\[3\], v28.s\[3\]
+ 346c: 6e1c679c mov v28.s\[3\], v28.s\[3\]
+ 3470: 6e1c67bd mov v29.s\[3\], v29.s\[3\]
+ 3474: 6e1c67bd mov v29.s\[3\], v29.s\[3\]
+ 3478: 6e1c67de mov v30.s\[3\], v30.s\[3\]
+ 347c: 6e1c67de mov v30.s\[3\], v30.s\[3\]
+ 3480: 4e081c21 mov v1.d\[0\], x1
+ 3484: 4e081c21 mov v1.d\[0\], x1
+ 3488: 4e181c21 mov v1.d\[1\], x1
+ 348c: 4e181c21 mov v1.d\[1\], x1
+ 3490: 6e084421 mov v1.d\[0\], v1.d\[1\]
+ 3494: 6e084421 mov v1.d\[0\], v1.d\[1\]
+ 3498: 6e180421 mov v1.d\[1\], v1.d\[0\]
+ 349c: 6e180421 mov v1.d\[1\], v1.d\[0\]
+ 34a0: 4e081c42 mov v2.d\[0\], x2
+ 34a4: 4e081c42 mov v2.d\[0\], x2
+ 34a8: 4e181c42 mov v2.d\[1\], x2
+ 34ac: 4e181c42 mov v2.d\[1\], x2
+ 34b0: 6e084442 mov v2.d\[0\], v2.d\[1\]
+ 34b4: 6e084442 mov v2.d\[0\], v2.d\[1\]
+ 34b8: 6e180442 mov v2.d\[1\], v2.d\[0\]
+ 34bc: 6e180442 mov v2.d\[1\], v2.d\[0\]
+ 34c0: 4e081c63 mov v3.d\[0\], x3
+ 34c4: 4e081c63 mov v3.d\[0\], x3
+ 34c8: 4e181c63 mov v3.d\[1\], x3
+ 34cc: 4e181c63 mov v3.d\[1\], x3
+ 34d0: 6e084463 mov v3.d\[0\], v3.d\[1\]
+ 34d4: 6e084463 mov v3.d\[0\], v3.d\[1\]
+ 34d8: 6e180463 mov v3.d\[1\], v3.d\[0\]
+ 34dc: 6e180463 mov v3.d\[1\], v3.d\[0\]
+ 34e0: 4e081c84 mov v4.d\[0\], x4
+ 34e4: 4e081c84 mov v4.d\[0\], x4
+ 34e8: 4e181c84 mov v4.d\[1\], x4
+ 34ec: 4e181c84 mov v4.d\[1\], x4
+ 34f0: 6e084484 mov v4.d\[0\], v4.d\[1\]
+ 34f4: 6e084484 mov v4.d\[0\], v4.d\[1\]
+ 34f8: 6e180484 mov v4.d\[1\], v4.d\[0\]
+ 34fc: 6e180484 mov v4.d\[1\], v4.d\[0\]
+ 3500: 4e081ca5 mov v5.d\[0\], x5
+ 3504: 4e081ca5 mov v5.d\[0\], x5
+ 3508: 4e181ca5 mov v5.d\[1\], x5
+ 350c: 4e181ca5 mov v5.d\[1\], x5
+ 3510: 6e0844a5 mov v5.d\[0\], v5.d\[1\]
+ 3514: 6e0844a5 mov v5.d\[0\], v5.d\[1\]
+ 3518: 6e1804a5 mov v5.d\[1\], v5.d\[0\]
+ 351c: 6e1804a5 mov v5.d\[1\], v5.d\[0\]
+ 3520: 4e081cc6 mov v6.d\[0\], x6
+ 3524: 4e081cc6 mov v6.d\[0\], x6
+ 3528: 4e181cc6 mov v6.d\[1\], x6
+ 352c: 4e181cc6 mov v6.d\[1\], x6
+ 3530: 6e0844c6 mov v6.d\[0\], v6.d\[1\]
+ 3534: 6e0844c6 mov v6.d\[0\], v6.d\[1\]
+ 3538: 6e1804c6 mov v6.d\[1\], v6.d\[0\]
+ 353c: 6e1804c6 mov v6.d\[1\], v6.d\[0\]
+ 3540: 4e081ce7 mov v7.d\[0\], x7
+ 3544: 4e081ce7 mov v7.d\[0\], x7
+ 3548: 4e181ce7 mov v7.d\[1\], x7
+ 354c: 4e181ce7 mov v7.d\[1\], x7
+ 3550: 6e0844e7 mov v7.d\[0\], v7.d\[1\]
+ 3554: 6e0844e7 mov v7.d\[0\], v7.d\[1\]
+ 3558: 6e1804e7 mov v7.d\[1\], v7.d\[0\]
+ 355c: 6e1804e7 mov v7.d\[1\], v7.d\[0\]
+ 3560: 4e081d08 mov v8.d\[0\], x8
+ 3564: 4e081d08 mov v8.d\[0\], x8
+ 3568: 4e181d08 mov v8.d\[1\], x8
+ 356c: 4e181d08 mov v8.d\[1\], x8
+ 3570: 6e084508 mov v8.d\[0\], v8.d\[1\]
+ 3574: 6e084508 mov v8.d\[0\], v8.d\[1\]
+ 3578: 6e180508 mov v8.d\[1\], v8.d\[0\]
+ 357c: 6e180508 mov v8.d\[1\], v8.d\[0\]
+ 3580: 4e081d29 mov v9.d\[0\], x9
+ 3584: 4e081d29 mov v9.d\[0\], x9
+ 3588: 4e181d29 mov v9.d\[1\], x9
+ 358c: 4e181d29 mov v9.d\[1\], x9
+ 3590: 6e084529 mov v9.d\[0\], v9.d\[1\]
+ 3594: 6e084529 mov v9.d\[0\], v9.d\[1\]
+ 3598: 6e180529 mov v9.d\[1\], v9.d\[0\]
+ 359c: 6e180529 mov v9.d\[1\], v9.d\[0\]
+ 35a0: 4e081d4a mov v10.d\[0\], x10
+ 35a4: 4e081d4a mov v10.d\[0\], x10
+ 35a8: 4e181d4a mov v10.d\[1\], x10
+ 35ac: 4e181d4a mov v10.d\[1\], x10
+ 35b0: 6e08454a mov v10.d\[0\], v10.d\[1\]
+ 35b4: 6e08454a mov v10.d\[0\], v10.d\[1\]
+ 35b8: 6e18054a mov v10.d\[1\], v10.d\[0\]
+ 35bc: 6e18054a mov v10.d\[1\], v10.d\[0\]
+ 35c0: 4e081d6b mov v11.d\[0\], x11
+ 35c4: 4e081d6b mov v11.d\[0\], x11
+ 35c8: 4e181d6b mov v11.d\[1\], x11
+ 35cc: 4e181d6b mov v11.d\[1\], x11
+ 35d0: 6e08456b mov v11.d\[0\], v11.d\[1\]
+ 35d4: 6e08456b mov v11.d\[0\], v11.d\[1\]
+ 35d8: 6e18056b mov v11.d\[1\], v11.d\[0\]
+ 35dc: 6e18056b mov v11.d\[1\], v11.d\[0\]
+ 35e0: 4e081d8c mov v12.d\[0\], x12
+ 35e4: 4e081d8c mov v12.d\[0\], x12
+ 35e8: 4e181d8c mov v12.d\[1\], x12
+ 35ec: 4e181d8c mov v12.d\[1\], x12
+ 35f0: 6e08458c mov v12.d\[0\], v12.d\[1\]
+ 35f4: 6e08458c mov v12.d\[0\], v12.d\[1\]
+ 35f8: 6e18058c mov v12.d\[1\], v12.d\[0\]
+ 35fc: 6e18058c mov v12.d\[1\], v12.d\[0\]
+ 3600: 4e081dad mov v13.d\[0\], x13
+ 3604: 4e081dad mov v13.d\[0\], x13
+ 3608: 4e181dad mov v13.d\[1\], x13
+ 360c: 4e181dad mov v13.d\[1\], x13
+ 3610: 6e0845ad mov v13.d\[0\], v13.d\[1\]
+ 3614: 6e0845ad mov v13.d\[0\], v13.d\[1\]
+ 3618: 6e1805ad mov v13.d\[1\], v13.d\[0\]
+ 361c: 6e1805ad mov v13.d\[1\], v13.d\[0\]
+ 3620: 4e081dce mov v14.d\[0\], x14
+ 3624: 4e081dce mov v14.d\[0\], x14
+ 3628: 4e181dce mov v14.d\[1\], x14
+ 362c: 4e181dce mov v14.d\[1\], x14
+ 3630: 6e0845ce mov v14.d\[0\], v14.d\[1\]
+ 3634: 6e0845ce mov v14.d\[0\], v14.d\[1\]
+ 3638: 6e1805ce mov v14.d\[1\], v14.d\[0\]
+ 363c: 6e1805ce mov v14.d\[1\], v14.d\[0\]
+ 3640: 4e081def mov v15.d\[0\], x15
+ 3644: 4e081def mov v15.d\[0\], x15
+ 3648: 4e181def mov v15.d\[1\], x15
+ 364c: 4e181def mov v15.d\[1\], x15
+ 3650: 6e0845ef mov v15.d\[0\], v15.d\[1\]
+ 3654: 6e0845ef mov v15.d\[0\], v15.d\[1\]
+ 3658: 6e1805ef mov v15.d\[1\], v15.d\[0\]
+ 365c: 6e1805ef mov v15.d\[1\], v15.d\[0\]
+ 3660: 4e081e10 mov v16.d\[0\], x16
+ 3664: 4e081e10 mov v16.d\[0\], x16
+ 3668: 4e181e10 mov v16.d\[1\], x16
+ 366c: 4e181e10 mov v16.d\[1\], x16
+ 3670: 6e084610 mov v16.d\[0\], v16.d\[1\]
+ 3674: 6e084610 mov v16.d\[0\], v16.d\[1\]
+ 3678: 6e180610 mov v16.d\[1\], v16.d\[0\]
+ 367c: 6e180610 mov v16.d\[1\], v16.d\[0\]
+ 3680: 4e081e31 mov v17.d\[0\], x17
+ 3684: 4e081e31 mov v17.d\[0\], x17
+ 3688: 4e181e31 mov v17.d\[1\], x17
+ 368c: 4e181e31 mov v17.d\[1\], x17
+ 3690: 6e084631 mov v17.d\[0\], v17.d\[1\]
+ 3694: 6e084631 mov v17.d\[0\], v17.d\[1\]
+ 3698: 6e180631 mov v17.d\[1\], v17.d\[0\]
+ 369c: 6e180631 mov v17.d\[1\], v17.d\[0\]
+ 36a0: 4e081e52 mov v18.d\[0\], x18
+ 36a4: 4e081e52 mov v18.d\[0\], x18
+ 36a8: 4e181e52 mov v18.d\[1\], x18
+ 36ac: 4e181e52 mov v18.d\[1\], x18
+ 36b0: 6e084652 mov v18.d\[0\], v18.d\[1\]
+ 36b4: 6e084652 mov v18.d\[0\], v18.d\[1\]
+ 36b8: 6e180652 mov v18.d\[1\], v18.d\[0\]
+ 36bc: 6e180652 mov v18.d\[1\], v18.d\[0\]
+ 36c0: 4e081e73 mov v19.d\[0\], x19
+ 36c4: 4e081e73 mov v19.d\[0\], x19
+ 36c8: 4e181e73 mov v19.d\[1\], x19
+ 36cc: 4e181e73 mov v19.d\[1\], x19
+ 36d0: 6e084673 mov v19.d\[0\], v19.d\[1\]
+ 36d4: 6e084673 mov v19.d\[0\], v19.d\[1\]
+ 36d8: 6e180673 mov v19.d\[1\], v19.d\[0\]
+ 36dc: 6e180673 mov v19.d\[1\], v19.d\[0\]
+ 36e0: 4e081e94 mov v20.d\[0\], x20
+ 36e4: 4e081e94 mov v20.d\[0\], x20
+ 36e8: 4e181e94 mov v20.d\[1\], x20
+ 36ec: 4e181e94 mov v20.d\[1\], x20
+ 36f0: 6e084694 mov v20.d\[0\], v20.d\[1\]
+ 36f4: 6e084694 mov v20.d\[0\], v20.d\[1\]
+ 36f8: 6e180694 mov v20.d\[1\], v20.d\[0\]
+ 36fc: 6e180694 mov v20.d\[1\], v20.d\[0\]
+ 3700: 4e081eb5 mov v21.d\[0\], x21
+ 3704: 4e081eb5 mov v21.d\[0\], x21
+ 3708: 4e181eb5 mov v21.d\[1\], x21
+ 370c: 4e181eb5 mov v21.d\[1\], x21
+ 3710: 6e0846b5 mov v21.d\[0\], v21.d\[1\]
+ 3714: 6e0846b5 mov v21.d\[0\], v21.d\[1\]
+ 3718: 6e1806b5 mov v21.d\[1\], v21.d\[0\]
+ 371c: 6e1806b5 mov v21.d\[1\], v21.d\[0\]
+ 3720: 4e081ed6 mov v22.d\[0\], x22
+ 3724: 4e081ed6 mov v22.d\[0\], x22
+ 3728: 4e181ed6 mov v22.d\[1\], x22
+ 372c: 4e181ed6 mov v22.d\[1\], x22
+ 3730: 6e0846d6 mov v22.d\[0\], v22.d\[1\]
+ 3734: 6e0846d6 mov v22.d\[0\], v22.d\[1\]
+ 3738: 6e1806d6 mov v22.d\[1\], v22.d\[0\]
+ 373c: 6e1806d6 mov v22.d\[1\], v22.d\[0\]
+ 3740: 4e081ef7 mov v23.d\[0\], x23
+ 3744: 4e081ef7 mov v23.d\[0\], x23
+ 3748: 4e181ef7 mov v23.d\[1\], x23
+ 374c: 4e181ef7 mov v23.d\[1\], x23
+ 3750: 6e0846f7 mov v23.d\[0\], v23.d\[1\]
+ 3754: 6e0846f7 mov v23.d\[0\], v23.d\[1\]
+ 3758: 6e1806f7 mov v23.d\[1\], v23.d\[0\]
+ 375c: 6e1806f7 mov v23.d\[1\], v23.d\[0\]
+ 3760: 4e081f18 mov v24.d\[0\], x24
+ 3764: 4e081f18 mov v24.d\[0\], x24
+ 3768: 4e181f18 mov v24.d\[1\], x24
+ 376c: 4e181f18 mov v24.d\[1\], x24
+ 3770: 6e084718 mov v24.d\[0\], v24.d\[1\]
+ 3774: 6e084718 mov v24.d\[0\], v24.d\[1\]
+ 3778: 6e180718 mov v24.d\[1\], v24.d\[0\]
+ 377c: 6e180718 mov v24.d\[1\], v24.d\[0\]
+ 3780: 4e081f39 mov v25.d\[0\], x25
+ 3784: 4e081f39 mov v25.d\[0\], x25
+ 3788: 4e181f39 mov v25.d\[1\], x25
+ 378c: 4e181f39 mov v25.d\[1\], x25
+ 3790: 6e084739 mov v25.d\[0\], v25.d\[1\]
+ 3794: 6e084739 mov v25.d\[0\], v25.d\[1\]
+ 3798: 6e180739 mov v25.d\[1\], v25.d\[0\]
+ 379c: 6e180739 mov v25.d\[1\], v25.d\[0\]
+ 37a0: 4e081f5a mov v26.d\[0\], x26
+ 37a4: 4e081f5a mov v26.d\[0\], x26
+ 37a8: 4e181f5a mov v26.d\[1\], x26
+ 37ac: 4e181f5a mov v26.d\[1\], x26
+ 37b0: 6e08475a mov v26.d\[0\], v26.d\[1\]
+ 37b4: 6e08475a mov v26.d\[0\], v26.d\[1\]
+ 37b8: 6e18075a mov v26.d\[1\], v26.d\[0\]
+ 37bc: 6e18075a mov v26.d\[1\], v26.d\[0\]
+ 37c0: 4e081f7b mov v27.d\[0\], x27
+ 37c4: 4e081f7b mov v27.d\[0\], x27
+ 37c8: 4e181f7b mov v27.d\[1\], x27
+ 37cc: 4e181f7b mov v27.d\[1\], x27
+ 37d0: 6e08477b mov v27.d\[0\], v27.d\[1\]
+ 37d4: 6e08477b mov v27.d\[0\], v27.d\[1\]
+ 37d8: 6e18077b mov v27.d\[1\], v27.d\[0\]
+ 37dc: 6e18077b mov v27.d\[1\], v27.d\[0\]
+ 37e0: 4e081f9c mov v28.d\[0\], x28
+ 37e4: 4e081f9c mov v28.d\[0\], x28
+ 37e8: 4e181f9c mov v28.d\[1\], x28
+ 37ec: 4e181f9c mov v28.d\[1\], x28
+ 37f0: 6e08479c mov v28.d\[0\], v28.d\[1\]
+ 37f4: 6e08479c mov v28.d\[0\], v28.d\[1\]
+ 37f8: 6e18079c mov v28.d\[1\], v28.d\[0\]
+ 37fc: 6e18079c mov v28.d\[1\], v28.d\[0\]
+ 3800: 4e081fbd mov v29.d\[0\], x29
+ 3804: 4e081fbd mov v29.d\[0\], x29
+ 3808: 4e181fbd mov v29.d\[1\], x29
+ 380c: 4e181fbd mov v29.d\[1\], x29
+ 3810: 6e0847bd mov v29.d\[0\], v29.d\[1\]
+ 3814: 6e0847bd mov v29.d\[0\], v29.d\[1\]
+ 3818: 6e1807bd mov v29.d\[1\], v29.d\[0\]
+ 381c: 6e1807bd mov v29.d\[1\], v29.d\[0\]
+ 3820: 4e081fde mov v30.d\[0\], x30
+ 3824: 4e081fde mov v30.d\[0\], x30
+ 3828: 4e181fde mov v30.d\[1\], x30
+ 382c: 4e181fde mov v30.d\[1\], x30
+ 3830: 6e0847de mov v30.d\[0\], v30.d\[1\]
+ 3834: 6e0847de mov v30.d\[0\], v30.d\[1\]
+ 3838: 6e1807de mov v30.d\[1\], v30.d\[0\]
+ 383c: 6e1807de mov v30.d\[1\], v30.d\[0\]
--- /dev/null
+
+
+ .macro iterate_regs_types macro_name reg
+ .irp index, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+ .irp regs, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
+ \macro_name \regs b \index \reg
+ .endr
+ .endr
+
+ .irp index, 0,1,2,3,4,5,6,7
+ .irp regs, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
+ \macro_name \regs h \index \reg
+ .endr
+ .endr
+
+ .irp index, 0,1,2,3
+ .irp regs, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
+ \macro_name \regs s \index \reg
+ .endr
+ .endr
+ .endm
+
+ .macro ins_mov_main reg_num type index xw_reg
+ ins v\reg_num\().\type[\index], \xw_reg\reg_num
+ mov v\reg_num\().\type[\index], \xw_reg\reg_num
+ .endm
+
+ .macro ins_mov_element reg_num type index null
+ ins v\reg_num\().\type[\index], v\reg_num\().\type[\index]
+ mov v\reg_num\().\type[\index], v\reg_num\().\type[\index]
+ .endm
+
+ .text
+ iterate_regs_types macro_name=ins_mov_main reg=w
+ iterate_regs_types macro_name=ins_mov_element
+
+ .irp reg, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
+ ins v\reg\().d[0], x\reg
+ mov v\reg\().d[0], x\reg
+ ins v\reg\().d[1], x\reg
+ mov v\reg\().d[1], x\reg
+
+ ins v\reg\().d[0], v\reg\().d[1]
+ mov v\reg\().d[0], v\reg\().d[1]
+ ins v\reg\().d[1], v\reg\().d[0]
+ mov v\reg\().d[1], v\reg\().d[0]
+ .endr
+
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 2e205821 mvn v1.8b, v1.8b
+ 4: 2e205821 mvn v1.8b, v1.8b
+ 8: 6e205821 mvn v1.16b, v1.16b
+ c: 6e205821 mvn v1.16b, v1.16b
+ 10: 2e205842 mvn v2.8b, v2.8b
+ 14: 2e205842 mvn v2.8b, v2.8b
+ 18: 6e205842 mvn v2.16b, v2.16b
+ 1c: 6e205842 mvn v2.16b, v2.16b
+ 20: 2e205863 mvn v3.8b, v3.8b
+ 24: 2e205863 mvn v3.8b, v3.8b
+ 28: 6e205863 mvn v3.16b, v3.16b
+ 2c: 6e205863 mvn v3.16b, v3.16b
+ 30: 2e205884 mvn v4.8b, v4.8b
+ 34: 2e205884 mvn v4.8b, v4.8b
+ 38: 6e205884 mvn v4.16b, v4.16b
+ 3c: 6e205884 mvn v4.16b, v4.16b
+ 40: 2e2058a5 mvn v5.8b, v5.8b
+ 44: 2e2058a5 mvn v5.8b, v5.8b
+ 48: 6e2058a5 mvn v5.16b, v5.16b
+ 4c: 6e2058a5 mvn v5.16b, v5.16b
+ 50: 2e2058c6 mvn v6.8b, v6.8b
+ 54: 2e2058c6 mvn v6.8b, v6.8b
+ 58: 6e2058c6 mvn v6.16b, v6.16b
+ 5c: 6e2058c6 mvn v6.16b, v6.16b
+ 60: 2e2058e7 mvn v7.8b, v7.8b
+ 64: 2e2058e7 mvn v7.8b, v7.8b
+ 68: 6e2058e7 mvn v7.16b, v7.16b
+ 6c: 6e2058e7 mvn v7.16b, v7.16b
+ 70: 2e205908 mvn v8.8b, v8.8b
+ 74: 2e205908 mvn v8.8b, v8.8b
+ 78: 6e205908 mvn v8.16b, v8.16b
+ 7c: 6e205908 mvn v8.16b, v8.16b
+ 80: 2e205929 mvn v9.8b, v9.8b
+ 84: 2e205929 mvn v9.8b, v9.8b
+ 88: 6e205929 mvn v9.16b, v9.16b
+ 8c: 6e205929 mvn v9.16b, v9.16b
+ 90: 2e20594a mvn v10.8b, v10.8b
+ 94: 2e20594a mvn v10.8b, v10.8b
+ 98: 6e20594a mvn v10.16b, v10.16b
+ 9c: 6e20594a mvn v10.16b, v10.16b
+ a0: 2e20596b mvn v11.8b, v11.8b
+ a4: 2e20596b mvn v11.8b, v11.8b
+ a8: 6e20596b mvn v11.16b, v11.16b
+ ac: 6e20596b mvn v11.16b, v11.16b
+ b0: 2e20598c mvn v12.8b, v12.8b
+ b4: 2e20598c mvn v12.8b, v12.8b
+ b8: 6e20598c mvn v12.16b, v12.16b
+ bc: 6e20598c mvn v12.16b, v12.16b
+ c0: 2e2059ad mvn v13.8b, v13.8b
+ c4: 2e2059ad mvn v13.8b, v13.8b
+ c8: 6e2059ad mvn v13.16b, v13.16b
+ cc: 6e2059ad mvn v13.16b, v13.16b
+ d0: 2e2059ce mvn v14.8b, v14.8b
+ d4: 2e2059ce mvn v14.8b, v14.8b
+ d8: 6e2059ce mvn v14.16b, v14.16b
+ dc: 6e2059ce mvn v14.16b, v14.16b
+ e0: 2e2059ef mvn v15.8b, v15.8b
+ e4: 2e2059ef mvn v15.8b, v15.8b
+ e8: 6e2059ef mvn v15.16b, v15.16b
+ ec: 6e2059ef mvn v15.16b, v15.16b
+ f0: 2e205a10 mvn v16.8b, v16.8b
+ f4: 2e205a10 mvn v16.8b, v16.8b
+ f8: 6e205a10 mvn v16.16b, v16.16b
+ fc: 6e205a10 mvn v16.16b, v16.16b
+ 100: 2e205a31 mvn v17.8b, v17.8b
+ 104: 2e205a31 mvn v17.8b, v17.8b
+ 108: 6e205a31 mvn v17.16b, v17.16b
+ 10c: 6e205a31 mvn v17.16b, v17.16b
+ 110: 2e205a52 mvn v18.8b, v18.8b
+ 114: 2e205a52 mvn v18.8b, v18.8b
+ 118: 6e205a52 mvn v18.16b, v18.16b
+ 11c: 6e205a52 mvn v18.16b, v18.16b
+ 120: 2e205a73 mvn v19.8b, v19.8b
+ 124: 2e205a73 mvn v19.8b, v19.8b
+ 128: 6e205a73 mvn v19.16b, v19.16b
+ 12c: 6e205a73 mvn v19.16b, v19.16b
+ 130: 2e205a94 mvn v20.8b, v20.8b
+ 134: 2e205a94 mvn v20.8b, v20.8b
+ 138: 6e205a94 mvn v20.16b, v20.16b
+ 13c: 6e205a94 mvn v20.16b, v20.16b
+ 140: 2e205ab5 mvn v21.8b, v21.8b
+ 144: 2e205ab5 mvn v21.8b, v21.8b
+ 148: 6e205ab5 mvn v21.16b, v21.16b
+ 14c: 6e205ab5 mvn v21.16b, v21.16b
+ 150: 2e205ad6 mvn v22.8b, v22.8b
+ 154: 2e205ad6 mvn v22.8b, v22.8b
+ 158: 6e205ad6 mvn v22.16b, v22.16b
+ 15c: 6e205ad6 mvn v22.16b, v22.16b
+ 160: 2e205af7 mvn v23.8b, v23.8b
+ 164: 2e205af7 mvn v23.8b, v23.8b
+ 168: 6e205af7 mvn v23.16b, v23.16b
+ 16c: 6e205af7 mvn v23.16b, v23.16b
+ 170: 2e205b18 mvn v24.8b, v24.8b
+ 174: 2e205b18 mvn v24.8b, v24.8b
+ 178: 6e205b18 mvn v24.16b, v24.16b
+ 17c: 6e205b18 mvn v24.16b, v24.16b
+ 180: 2e205b39 mvn v25.8b, v25.8b
+ 184: 2e205b39 mvn v25.8b, v25.8b
+ 188: 6e205b39 mvn v25.16b, v25.16b
+ 18c: 6e205b39 mvn v25.16b, v25.16b
+ 190: 2e205b5a mvn v26.8b, v26.8b
+ 194: 2e205b5a mvn v26.8b, v26.8b
+ 198: 6e205b5a mvn v26.16b, v26.16b
+ 19c: 6e205b5a mvn v26.16b, v26.16b
+ 1a0: 2e205b7b mvn v27.8b, v27.8b
+ 1a4: 2e205b7b mvn v27.8b, v27.8b
+ 1a8: 6e205b7b mvn v27.16b, v27.16b
+ 1ac: 6e205b7b mvn v27.16b, v27.16b
+ 1b0: 2e205b9c mvn v28.8b, v28.8b
+ 1b4: 2e205b9c mvn v28.8b, v28.8b
+ 1b8: 6e205b9c mvn v28.16b, v28.16b
+ 1bc: 6e205b9c mvn v28.16b, v28.16b
+ 1c0: 2e205bbd mvn v29.8b, v29.8b
+ 1c4: 2e205bbd mvn v29.8b, v29.8b
+ 1c8: 6e205bbd mvn v29.16b, v29.16b
+ 1cc: 6e205bbd mvn v29.16b, v29.16b
+ 1d0: 2e205bde mvn v30.8b, v30.8b
+ 1d4: 2e205bde mvn v30.8b, v30.8b
+ 1d8: 6e205bde mvn v30.16b, v30.16b
+ 1dc: 6e205bde mvn v30.16b, v30.16b
+ 1e0: 2e205bff mvn v31.8b, v31.8b
+ 1e4: 2e205bff mvn v31.8b, v31.8b
+ 1e8: 6e205bff mvn v31.16b, v31.16b
+ 1ec: 6e205bff mvn v31.16b, v31.16b
--- /dev/null
+
+
+ .text
+ .arch armv8
+
+ .irp r, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+ not v\r\().8b, v\r\().8b
+ mvn v\r\().8b, v\r\().8b
+
+ not v\r\().16b, v\r\().16b
+ mvn v\r\().16b, v\r\().16b
+ .endr
+
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 0cdf7000 ld1 {v0.8b}, \[x0\], #8
+ 4: 0cdfa000 ld1 {v0.8b, v1.8b}, \[x0\], #16
+ 8: 0cdf6000 ld1 {v0.8b-v2.8b}, \[x0\], #24
+ c: 0cdf2000 ld1 {v0.8b-v3.8b}, \[x0\], #32
+ 10: 0cdf7400 ld1 {v0.4h}, \[x0\], #8
+ 14: 0cdfa400 ld1 {v0.4h, v1.4h}, \[x0\], #16
+ 18: 0cdf6400 ld1 {v0.4h-v2.4h}, \[x0\], #24
+ 1c: 0cdf2400 ld1 {v0.4h-v3.4h}, \[x0\], #32
+ 20: 0cdf7800 ld1 {v0.2s}, \[x0\], #8
+ 24: 0cdfa800 ld1 {v0.2s, v1.2s}, \[x0\], #16
+ 28: 0cdf6800 ld1 {v0.2s-v2.2s}, \[x0\], #24
+ 2c: 0cdf2800 ld1 {v0.2s-v3.2s}, \[x0\], #32
+ 30: 0cdf7c00 ld1 {v0.1d}, \[x0\], #8
+ 34: 0cdfac00 ld1 {v0.1d, v1.1d}, \[x0\], #16
+ 38: 0cdf6c00 ld1 {v0.1d-v2.1d}, \[x0\], #24
+ 3c: 0cdf2c00 ld1 {v0.1d-v3.1d}, \[x0\], #32
+ 40: 0c9f7000 st1 {v0.8b}, \[x0\], #8
+ 44: 0c9fa000 st1 {v0.8b, v1.8b}, \[x0\], #16
+ 48: 0c9f6000 st1 {v0.8b-v2.8b}, \[x0\], #24
+ 4c: 0c9f2000 st1 {v0.8b-v3.8b}, \[x0\], #32
+ 50: 0c9f7400 st1 {v0.4h}, \[x0\], #8
+ 54: 0c9fa400 st1 {v0.4h, v1.4h}, \[x0\], #16
+ 58: 0c9f6400 st1 {v0.4h-v2.4h}, \[x0\], #24
+ 5c: 0c9f2400 st1 {v0.4h-v3.4h}, \[x0\], #32
+ 60: 0c9f7800 st1 {v0.2s}, \[x0\], #8
+ 64: 0c9fa800 st1 {v0.2s, v1.2s}, \[x0\], #16
+ 68: 0c9f6800 st1 {v0.2s-v2.2s}, \[x0\], #24
+ 6c: 0c9f2800 st1 {v0.2s-v3.2s}, \[x0\], #32
+ 70: 0c9f7c00 st1 {v0.1d}, \[x0\], #8
+ 74: 0c9fac00 st1 {v0.1d, v1.1d}, \[x0\], #16
+ 78: 0c9f6c00 st1 {v0.1d-v2.1d}, \[x0\], #24
+ 7c: 0c9f2c00 st1 {v0.1d-v3.1d}, \[x0\], #32
+ 80: 4cdf7000 ld1 {v0.16b}, \[x0\], #16
+ 84: 4cdfa000 ld1 {v0.16b, v1.16b}, \[x0\], #32
+ 88: 4cdf6000 ld1 {v0.16b-v2.16b}, \[x0\], #48
+ 8c: 4cdf2000 ld1 {v0.16b-v3.16b}, \[x0\], #64
+ 90: 4cdf7400 ld1 {v0.8h}, \[x0\], #16
+ 94: 4cdfa400 ld1 {v0.8h, v1.8h}, \[x0\], #32
+ 98: 4cdf6400 ld1 {v0.8h-v2.8h}, \[x0\], #48
+ 9c: 4cdf2400 ld1 {v0.8h-v3.8h}, \[x0\], #64
+ a0: 4cdf7800 ld1 {v0.4s}, \[x0\], #16
+ a4: 4cdfa800 ld1 {v0.4s, v1.4s}, \[x0\], #32
+ a8: 4cdf6800 ld1 {v0.4s-v2.4s}, \[x0\], #48
+ ac: 4cdf2800 ld1 {v0.4s-v3.4s}, \[x0\], #64
+ b0: 4cdf7c00 ld1 {v0.2d}, \[x0\], #16
+ b4: 4cdfac00 ld1 {v0.2d, v1.2d}, \[x0\], #32
+ b8: 4cdf6c00 ld1 {v0.2d-v2.2d}, \[x0\], #48
+ bc: 4cdf2c00 ld1 {v0.2d-v3.2d}, \[x0\], #64
+ c0: 4c9f7000 st1 {v0.16b}, \[x0\], #16
+ c4: 4c9fa000 st1 {v0.16b, v1.16b}, \[x0\], #32
+ c8: 4c9f6000 st1 {v0.16b-v2.16b}, \[x0\], #48
+ cc: 4c9f2000 st1 {v0.16b-v3.16b}, \[x0\], #64
+ d0: 4c9f7400 st1 {v0.8h}, \[x0\], #16
+ d4: 4c9fa400 st1 {v0.8h, v1.8h}, \[x0\], #32
+ d8: 4c9f6400 st1 {v0.8h-v2.8h}, \[x0\], #48
+ dc: 4c9f2400 st1 {v0.8h-v3.8h}, \[x0\], #64
+ e0: 4c9f7800 st1 {v0.4s}, \[x0\], #16
+ e4: 4c9fa800 st1 {v0.4s, v1.4s}, \[x0\], #32
+ e8: 4c9f6800 st1 {v0.4s-v2.4s}, \[x0\], #48
+ ec: 4c9f2800 st1 {v0.4s-v3.4s}, \[x0\], #64
+ f0: 4c9f7c00 st1 {v0.2d}, \[x0\], #16
+ f4: 4c9fac00 st1 {v0.2d, v1.2d}, \[x0\], #32
+ f8: 4c9f6c00 st1 {v0.2d-v2.2d}, \[x0\], #48
+ fc: 4c9f2c00 st1 {v0.2d-v3.2d}, \[x0\], #64
+ 100: 0cc77000 ld1 {v0.8b}, \[x0\], x7
+ 104: 0cc7a000 ld1 {v0.8b, v1.8b}, \[x0\], x7
+ 108: 0cc76000 ld1 {v0.8b-v2.8b}, \[x0\], x7
+ 10c: 0cc72000 ld1 {v0.8b-v3.8b}, \[x0\], x7
+ 110: 0cc77400 ld1 {v0.4h}, \[x0\], x7
+ 114: 0cc7a400 ld1 {v0.4h, v1.4h}, \[x0\], x7
+ 118: 0cc76400 ld1 {v0.4h-v2.4h}, \[x0\], x7
+ 11c: 0cc72400 ld1 {v0.4h-v3.4h}, \[x0\], x7
+ 120: 0cc77800 ld1 {v0.2s}, \[x0\], x7
+ 124: 0cc7a800 ld1 {v0.2s, v1.2s}, \[x0\], x7
+ 128: 0cc76800 ld1 {v0.2s-v2.2s}, \[x0\], x7
+ 12c: 0cc72800 ld1 {v0.2s-v3.2s}, \[x0\], x7
+ 130: 0cc77c00 ld1 {v0.1d}, \[x0\], x7
+ 134: 0cc7ac00 ld1 {v0.1d, v1.1d}, \[x0\], x7
+ 138: 0cc76c00 ld1 {v0.1d-v2.1d}, \[x0\], x7
+ 13c: 0cc72c00 ld1 {v0.1d-v3.1d}, \[x0\], x7
+ 140: 4cc77000 ld1 {v0.16b}, \[x0\], x7
+ 144: 4cc7a000 ld1 {v0.16b, v1.16b}, \[x0\], x7
+ 148: 4cc76000 ld1 {v0.16b-v2.16b}, \[x0\], x7
+ 14c: 4cc72000 ld1 {v0.16b-v3.16b}, \[x0\], x7
+ 150: 4cc77400 ld1 {v0.8h}, \[x0\], x7
+ 154: 4cc7a400 ld1 {v0.8h, v1.8h}, \[x0\], x7
+ 158: 4cc76400 ld1 {v0.8h-v2.8h}, \[x0\], x7
+ 15c: 4cc72400 ld1 {v0.8h-v3.8h}, \[x0\], x7
+ 160: 4cc77800 ld1 {v0.4s}, \[x0\], x7
+ 164: 4cc7a800 ld1 {v0.4s, v1.4s}, \[x0\], x7
+ 168: 4cc76800 ld1 {v0.4s-v2.4s}, \[x0\], x7
+ 16c: 4cc72800 ld1 {v0.4s-v3.4s}, \[x0\], x7
+ 170: 4cc77c00 ld1 {v0.2d}, \[x0\], x7
+ 174: 4cc7ac00 ld1 {v0.2d, v1.2d}, \[x0\], x7
+ 178: 4cc76c00 ld1 {v0.2d-v2.2d}, \[x0\], x7
+ 17c: 4cc72c00 ld1 {v0.2d-v3.2d}, \[x0\], x7
+ 180: 0c877000 st1 {v0.8b}, \[x0\], x7
+ 184: 0c87a000 st1 {v0.8b, v1.8b}, \[x0\], x7
+ 188: 0c876000 st1 {v0.8b-v2.8b}, \[x0\], x7
+ 18c: 0c872000 st1 {v0.8b-v3.8b}, \[x0\], x7
+ 190: 0c877400 st1 {v0.4h}, \[x0\], x7
+ 194: 0c87a400 st1 {v0.4h, v1.4h}, \[x0\], x7
+ 198: 0c876400 st1 {v0.4h-v2.4h}, \[x0\], x7
+ 19c: 0c872400 st1 {v0.4h-v3.4h}, \[x0\], x7
+ 1a0: 0c877800 st1 {v0.2s}, \[x0\], x7
+ 1a4: 0c87a800 st1 {v0.2s, v1.2s}, \[x0\], x7
+ 1a8: 0c876800 st1 {v0.2s-v2.2s}, \[x0\], x7
+ 1ac: 0c872800 st1 {v0.2s-v3.2s}, \[x0\], x7
+ 1b0: 0c877c00 st1 {v0.1d}, \[x0\], x7
+ 1b4: 0c87ac00 st1 {v0.1d, v1.1d}, \[x0\], x7
+ 1b8: 0c876c00 st1 {v0.1d-v2.1d}, \[x0\], x7
+ 1bc: 0c872c00 st1 {v0.1d-v3.1d}, \[x0\], x7
+ 1c0: 4c877000 st1 {v0.16b}, \[x0\], x7
+ 1c4: 4c87a000 st1 {v0.16b, v1.16b}, \[x0\], x7
+ 1c8: 4c876000 st1 {v0.16b-v2.16b}, \[x0\], x7
+ 1cc: 4c872000 st1 {v0.16b-v3.16b}, \[x0\], x7
+ 1d0: 4c877400 st1 {v0.8h}, \[x0\], x7
+ 1d4: 4c87a400 st1 {v0.8h, v1.8h}, \[x0\], x7
+ 1d8: 4c876400 st1 {v0.8h-v2.8h}, \[x0\], x7
+ 1dc: 4c872400 st1 {v0.8h-v3.8h}, \[x0\], x7
+ 1e0: 4c877800 st1 {v0.4s}, \[x0\], x7
+ 1e4: 4c87a800 st1 {v0.4s, v1.4s}, \[x0\], x7
+ 1e8: 4c876800 st1 {v0.4s-v2.4s}, \[x0\], x7
+ 1ec: 4c872800 st1 {v0.4s-v3.4s}, \[x0\], x7
+ 1f0: 4c877c00 st1 {v0.2d}, \[x0\], x7
+ 1f4: 4c87ac00 st1 {v0.2d, v1.2d}, \[x0\], x7
+ 1f8: 4c876c00 st1 {v0.2d-v2.2d}, \[x0\], x7
+ 1fc: 4c872c00 st1 {v0.2d-v3.2d}, \[x0\], x7
+ 200: 0cdf8000 ld2 {v0.8b, v1.8b}, \[x0\], #16
+ 204: 0cc78000 ld2 {v0.8b, v1.8b}, \[x0\], x7
+ 208: 0cdf8400 ld2 {v0.4h, v1.4h}, \[x0\], #16
+ 20c: 0cc78400 ld2 {v0.4h, v1.4h}, \[x0\], x7
+ 210: 0cdf8800 ld2 {v0.2s, v1.2s}, \[x0\], #16
+ 214: 0cc78800 ld2 {v0.2s, v1.2s}, \[x0\], x7
+ 218: 0c9f8000 st2 {v0.8b, v1.8b}, \[x0\], #16
+ 21c: 0c878000 st2 {v0.8b, v1.8b}, \[x0\], x7
+ 220: 0c9f8400 st2 {v0.4h, v1.4h}, \[x0\], #16
+ 224: 0c878400 st2 {v0.4h, v1.4h}, \[x0\], x7
+ 228: 0c9f8800 st2 {v0.2s, v1.2s}, \[x0\], #16
+ 22c: 0c878800 st2 {v0.2s, v1.2s}, \[x0\], x7
+ 230: 4cdf8000 ld2 {v0.16b, v1.16b}, \[x0\], #32
+ 234: 4cc78000 ld2 {v0.16b, v1.16b}, \[x0\], x7
+ 238: 4cdf8400 ld2 {v0.8h, v1.8h}, \[x0\], #32
+ 23c: 4cc78400 ld2 {v0.8h, v1.8h}, \[x0\], x7
+ 240: 4cdf8800 ld2 {v0.4s, v1.4s}, \[x0\], #32
+ 244: 4cc78800 ld2 {v0.4s, v1.4s}, \[x0\], x7
+ 248: 4cdf8c00 ld2 {v0.2d, v1.2d}, \[x0\], #32
+ 24c: 4cc78c00 ld2 {v0.2d, v1.2d}, \[x0\], x7
+ 250: 4c9f8000 st2 {v0.16b, v1.16b}, \[x0\], #32
+ 254: 4c878000 st2 {v0.16b, v1.16b}, \[x0\], x7
+ 258: 4c9f8400 st2 {v0.8h, v1.8h}, \[x0\], #32
+ 25c: 4c878400 st2 {v0.8h, v1.8h}, \[x0\], x7
+ 260: 4c9f8800 st2 {v0.4s, v1.4s}, \[x0\], #32
+ 264: 4c878800 st2 {v0.4s, v1.4s}, \[x0\], x7
+ 268: 4c9f8c00 st2 {v0.2d, v1.2d}, \[x0\], #32
+ 26c: 4c878c00 st2 {v0.2d, v1.2d}, \[x0\], x7
+ 270: 0cdf4000 ld3 {v0.8b-v2.8b}, \[x0\], #24
+ 274: 0cdf0000 ld4 {v0.8b-v3.8b}, \[x0\], #32
+ 278: 0cc74000 ld3 {v0.8b-v2.8b}, \[x0\], x7
+ 27c: 0cc70000 ld4 {v0.8b-v3.8b}, \[x0\], x7
+ 280: 0cdf4400 ld3 {v0.4h-v2.4h}, \[x0\], #24
+ 284: 0cdf0400 ld4 {v0.4h-v3.4h}, \[x0\], #32
+ 288: 0cc74400 ld3 {v0.4h-v2.4h}, \[x0\], x7
+ 28c: 0cc70400 ld4 {v0.4h-v3.4h}, \[x0\], x7
+ 290: 0cdf4800 ld3 {v0.2s-v2.2s}, \[x0\], #24
+ 294: 0cdf0800 ld4 {v0.2s-v3.2s}, \[x0\], #32
+ 298: 0cc74800 ld3 {v0.2s-v2.2s}, \[x0\], x7
+ 29c: 0cc70800 ld4 {v0.2s-v3.2s}, \[x0\], x7
+ 2a0: 0c9f4000 st3 {v0.8b-v2.8b}, \[x0\], #24
+ 2a4: 0c9f0000 st4 {v0.8b-v3.8b}, \[x0\], #32
+ 2a8: 0c874000 st3 {v0.8b-v2.8b}, \[x0\], x7
+ 2ac: 0c870000 st4 {v0.8b-v3.8b}, \[x0\], x7
+ 2b0: 0c9f4400 st3 {v0.4h-v2.4h}, \[x0\], #24
+ 2b4: 0c9f0400 st4 {v0.4h-v3.4h}, \[x0\], #32
+ 2b8: 0c874400 st3 {v0.4h-v2.4h}, \[x0\], x7
+ 2bc: 0c870400 st4 {v0.4h-v3.4h}, \[x0\], x7
+ 2c0: 0c9f4800 st3 {v0.2s-v2.2s}, \[x0\], #24
+ 2c4: 0c9f0800 st4 {v0.2s-v3.2s}, \[x0\], #32
+ 2c8: 0c874800 st3 {v0.2s-v2.2s}, \[x0\], x7
+ 2cc: 0c870800 st4 {v0.2s-v3.2s}, \[x0\], x7
+ 2d0: 4cdf4000 ld3 {v0.16b-v2.16b}, \[x0\], #48
+ 2d4: 4cdf0000 ld4 {v0.16b-v3.16b}, \[x0\], #64
+ 2d8: 4cc74000 ld3 {v0.16b-v2.16b}, \[x0\], x7
+ 2dc: 4cc70000 ld4 {v0.16b-v3.16b}, \[x0\], x7
+ 2e0: 4cdf4400 ld3 {v0.8h-v2.8h}, \[x0\], #48
+ 2e4: 4cdf0400 ld4 {v0.8h-v3.8h}, \[x0\], #64
+ 2e8: 4cc74400 ld3 {v0.8h-v2.8h}, \[x0\], x7
+ 2ec: 4cc70400 ld4 {v0.8h-v3.8h}, \[x0\], x7
+ 2f0: 4cdf4800 ld3 {v0.4s-v2.4s}, \[x0\], #48
+ 2f4: 4cdf0800 ld4 {v0.4s-v3.4s}, \[x0\], #64
+ 2f8: 4cc74800 ld3 {v0.4s-v2.4s}, \[x0\], x7
+ 2fc: 4cc70800 ld4 {v0.4s-v3.4s}, \[x0\], x7
+ 300: 4cdf4c00 ld3 {v0.2d-v2.2d}, \[x0\], #48
+ 304: 4cdf0c00 ld4 {v0.2d-v3.2d}, \[x0\], #64
+ 308: 4cc74c00 ld3 {v0.2d-v2.2d}, \[x0\], x7
+ 30c: 4cc70c00 ld4 {v0.2d-v3.2d}, \[x0\], x7
+ 310: 4c9f4000 st3 {v0.16b-v2.16b}, \[x0\], #48
+ 314: 4c9f0000 st4 {v0.16b-v3.16b}, \[x0\], #64
+ 318: 4c874000 st3 {v0.16b-v2.16b}, \[x0\], x7
+ 31c: 4c870000 st4 {v0.16b-v3.16b}, \[x0\], x7
+ 320: 4c9f4400 st3 {v0.8h-v2.8h}, \[x0\], #48
+ 324: 4c9f0400 st4 {v0.8h-v3.8h}, \[x0\], #64
+ 328: 4c874400 st3 {v0.8h-v2.8h}, \[x0\], x7
+ 32c: 4c870400 st4 {v0.8h-v3.8h}, \[x0\], x7
+ 330: 4c9f4800 st3 {v0.4s-v2.4s}, \[x0\], #48
+ 334: 4c9f0800 st4 {v0.4s-v3.4s}, \[x0\], #64
+ 338: 4c874800 st3 {v0.4s-v2.4s}, \[x0\], x7
+ 33c: 4c870800 st4 {v0.4s-v3.4s}, \[x0\], x7
+ 340: 4c9f4c00 st3 {v0.2d-v2.2d}, \[x0\], #48
+ 344: 4c9f0c00 st4 {v0.2d-v3.2d}, \[x0\], #64
+ 348: 4c874c00 st3 {v0.2d-v2.2d}, \[x0\], x7
+ 34c: 4c870c00 st4 {v0.2d-v3.2d}, \[x0\], x7
+ 350: 0ddf0400 ld1 {v0.b}\[1\], \[x0\], #1
+ 354: 0dff0400 ld2 {v0.b, v1.b}\[1\], \[x0\], #2
+ 358: 0ddf2400 ld3 {v0.b-v2.b}\[1\], \[x0\], #3
+ 35c: 0dff2400 ld4 {v0.b-v3.b}\[1\], \[x0\], #4
+ 360: 0ddfc000 ld1r {v0.8b}, \[x0\], #1
+ 364: 0dffc000 ld2r {v0.8b, v1.8b}, \[x0\], #2
+ 368: 0ddfe000 ld3r {v0.8b-v2.8b}, \[x0\], #3
+ 36c: 0dffe000 ld4r {v0.8b-v3.8b}, \[x0\], #4
+ 370: 4ddfc000 ld1r {v0.16b}, \[x0\], #1
+ 374: 4dffc000 ld2r {v0.16b, v1.16b}, \[x0\], #2
+ 378: 4ddfe000 ld3r {v0.16b-v2.16b}, \[x0\], #3
+ 37c: 4dffe000 ld4r {v0.16b-v3.16b}, \[x0\], #4
+ 380: 0d9f0400 st1 {v0.b}\[1\], \[x0\], #1
+ 384: 0dbf0400 st2 {v0.b, v1.b}\[1\], \[x0\], #2
+ 388: 0d9f2400 st3 {v0.b-v2.b}\[1\], \[x0\], #3
+ 38c: 0dbf2400 st4 {v0.b-v3.b}\[1\], \[x0\], #4
+ 390: 0ddf4800 ld1 {v0.h}\[1\], \[x0\], #2
+ 394: 0dff4800 ld2 {v0.h, v1.h}\[1\], \[x0\], #4
+ 398: 0ddf6800 ld3 {v0.h-v2.h}\[1\], \[x0\], #6
+ 39c: 0dff6800 ld4 {v0.h-v3.h}\[1\], \[x0\], #8
+ 3a0: 0ddfc400 ld1r {v0.4h}, \[x0\], #2
+ 3a4: 0dffc400 ld2r {v0.4h, v1.4h}, \[x0\], #4
+ 3a8: 0ddfe400 ld3r {v0.4h-v2.4h}, \[x0\], #6
+ 3ac: 0dffe400 ld4r {v0.4h-v3.4h}, \[x0\], #8
+ 3b0: 4ddfc400 ld1r {v0.8h}, \[x0\], #2
+ 3b4: 4dffc400 ld2r {v0.8h, v1.8h}, \[x0\], #4
+ 3b8: 4ddfe400 ld3r {v0.8h-v2.8h}, \[x0\], #6
+ 3bc: 4dffe400 ld4r {v0.8h-v3.8h}, \[x0\], #8
+ 3c0: 0d9f4800 st1 {v0.h}\[1\], \[x0\], #2
+ 3c4: 0dbf4800 st2 {v0.h, v1.h}\[1\], \[x0\], #4
+ 3c8: 0d9f6800 st3 {v0.h-v2.h}\[1\], \[x0\], #6
+ 3cc: 0dbf6800 st4 {v0.h-v3.h}\[1\], \[x0\], #8
+ 3d0: 0ddf9000 ld1 {v0.s}\[1\], \[x0\], #4
+ 3d4: 0dff9000 ld2 {v0.s, v1.s}\[1\], \[x0\], #8
+ 3d8: 0ddfb000 ld3 {v0.s-v2.s}\[1\], \[x0\], #12
+ 3dc: 0dffb000 ld4 {v0.s-v3.s}\[1\], \[x0\], #16
+ 3e0: 0ddfc800 ld1r {v0.2s}, \[x0\], #4
+ 3e4: 0dffc800 ld2r {v0.2s, v1.2s}, \[x0\], #8
+ 3e8: 0ddfe800 ld3r {v0.2s-v2.2s}, \[x0\], #12
+ 3ec: 0dffe800 ld4r {v0.2s-v3.2s}, \[x0\], #16
+ 3f0: 4ddfc800 ld1r {v0.4s}, \[x0\], #4
+ 3f4: 4dffc800 ld2r {v0.4s, v1.4s}, \[x0\], #8
+ 3f8: 4ddfe800 ld3r {v0.4s-v2.4s}, \[x0\], #12
+ 3fc: 4dffe800 ld4r {v0.4s-v3.4s}, \[x0\], #16
+ 400: 0d9f9000 st1 {v0.s}\[1\], \[x0\], #4
+ 404: 0dbf9000 st2 {v0.s, v1.s}\[1\], \[x0\], #8
+ 408: 0d9fb000 st3 {v0.s-v2.s}\[1\], \[x0\], #12
+ 40c: 0dbfb000 st4 {v0.s-v3.s}\[1\], \[x0\], #16
+ 410: 4ddf8400 ld1 {v0.d}\[1\], \[x0\], #8
+ 414: 4dff8400 ld2 {v0.d, v1.d}\[1\], \[x0\], #16
+ 418: 4ddfa400 ld3 {v0.d-v2.d}\[1\], \[x0\], #24
+ 41c: 4dffa400 ld4 {v0.d-v3.d}\[1\], \[x0\], #32
+ 420: 0ddfcc00 ld1r {v0.1d}, \[x0\], #8
+ 424: 0dffcc00 ld2r {v0.1d, v1.1d}, \[x0\], #16
+ 428: 0ddfec00 ld3r {v0.1d-v2.1d}, \[x0\], #24
+ 42c: 0dffec00 ld4r {v0.1d-v3.1d}, \[x0\], #32
+ 430: 4ddfcc00 ld1r {v0.2d}, \[x0\], #8
+ 434: 4dffcc00 ld2r {v0.2d, v1.2d}, \[x0\], #16
+ 438: 4ddfec00 ld3r {v0.2d-v2.2d}, \[x0\], #24
+ 43c: 4dffec00 ld4r {v0.2d-v3.2d}, \[x0\], #32
+ 440: 4d9f8400 st1 {v0.d}\[1\], \[x0\], #8
+ 444: 4dbf8400 st2 {v0.d, v1.d}\[1\], \[x0\], #16
+ 448: 4d9fa400 st3 {v0.d-v2.d}\[1\], \[x0\], #24
+ 44c: 4dbfa400 st4 {v0.d-v3.d}\[1\], \[x0\], #32
+ 450: 0dc70400 ld1 {v0.b}\[1\], \[x0\], x7
+ 454: 0de70400 ld2 {v0.b, v1.b}\[1\], \[x0\], x7
+ 458: 0dc72400 ld3 {v0.b-v2.b}\[1\], \[x0\], x7
+ 45c: 0de72400 ld4 {v0.b-v3.b}\[1\], \[x0\], x7
+ 460: 0dc74800 ld1 {v0.h}\[1\], \[x0\], x7
+ 464: 0de74800 ld2 {v0.h, v1.h}\[1\], \[x0\], x7
+ 468: 0dc76800 ld3 {v0.h-v2.h}\[1\], \[x0\], x7
+ 46c: 0de76800 ld4 {v0.h-v3.h}\[1\], \[x0\], x7
+ 470: 0dc79000 ld1 {v0.s}\[1\], \[x0\], x7
+ 474: 0de79000 ld2 {v0.s, v1.s}\[1\], \[x0\], x7
+ 478: 0dc7b000 ld3 {v0.s-v2.s}\[1\], \[x0\], x7
+ 47c: 0de7b000 ld4 {v0.s-v3.s}\[1\], \[x0\], x7
+ 480: 4dc78400 ld1 {v0.d}\[1\], \[x0\], x7
+ 484: 4de78400 ld2 {v0.d, v1.d}\[1\], \[x0\], x7
+ 488: 4dc7a400 ld3 {v0.d-v2.d}\[1\], \[x0\], x7
+ 48c: 4de7a400 ld4 {v0.d-v3.d}\[1\], \[x0\], x7
+ 490: 0dc7c000 ld1r {v0.8b}, \[x0\], x7
+ 494: 0de7c000 ld2r {v0.8b, v1.8b}, \[x0\], x7
+ 498: 0dc7e000 ld3r {v0.8b-v2.8b}, \[x0\], x7
+ 49c: 0de7e000 ld4r {v0.8b-v3.8b}, \[x0\], x7
+ 4a0: 4dc7c000 ld1r {v0.16b}, \[x0\], x7
+ 4a4: 4de7c000 ld2r {v0.16b, v1.16b}, \[x0\], x7
+ 4a8: 4dc7e000 ld3r {v0.16b-v2.16b}, \[x0\], x7
+ 4ac: 4de7e000 ld4r {v0.16b-v3.16b}, \[x0\], x7
+ 4b0: 0dc7c400 ld1r {v0.4h}, \[x0\], x7
+ 4b4: 0de7c400 ld2r {v0.4h, v1.4h}, \[x0\], x7
+ 4b8: 0dc7e400 ld3r {v0.4h-v2.4h}, \[x0\], x7
+ 4bc: 0de7e400 ld4r {v0.4h-v3.4h}, \[x0\], x7
+ 4c0: 4dc7c400 ld1r {v0.8h}, \[x0\], x7
+ 4c4: 4de7c400 ld2r {v0.8h, v1.8h}, \[x0\], x7
+ 4c8: 4dc7e400 ld3r {v0.8h-v2.8h}, \[x0\], x7
+ 4cc: 4de7e400 ld4r {v0.8h-v3.8h}, \[x0\], x7
+ 4d0: 0dc7c800 ld1r {v0.2s}, \[x0\], x7
+ 4d4: 0de7c800 ld2r {v0.2s, v1.2s}, \[x0\], x7
+ 4d8: 0dc7e800 ld3r {v0.2s-v2.2s}, \[x0\], x7
+ 4dc: 0de7e800 ld4r {v0.2s-v3.2s}, \[x0\], x7
+ 4e0: 4dc7c800 ld1r {v0.4s}, \[x0\], x7
+ 4e4: 4de7c800 ld2r {v0.4s, v1.4s}, \[x0\], x7
+ 4e8: 4dc7e800 ld3r {v0.4s-v2.4s}, \[x0\], x7
+ 4ec: 4de7e800 ld4r {v0.4s-v3.4s}, \[x0\], x7
+ 4f0: 0dc7cc00 ld1r {v0.1d}, \[x0\], x7
+ 4f4: 0de7cc00 ld2r {v0.1d, v1.1d}, \[x0\], x7
+ 4f8: 0dc7ec00 ld3r {v0.1d-v2.1d}, \[x0\], x7
+ 4fc: 0de7ec00 ld4r {v0.1d-v3.1d}, \[x0\], x7
+ 500: 4dc7cc00 ld1r {v0.2d}, \[x0\], x7
+ 504: 4de7cc00 ld2r {v0.2d, v1.2d}, \[x0\], x7
+ 508: 4dc7ec00 ld3r {v0.2d-v2.2d}, \[x0\], x7
+ 50c: 4de7ec00 ld4r {v0.2d-v3.2d}, \[x0\], x7
+ 510: 0d870400 st1 {v0.b}\[1\], \[x0\], x7
+ 514: 0da70400 st2 {v0.b, v1.b}\[1\], \[x0\], x7
+ 518: 0d872400 st3 {v0.b-v2.b}\[1\], \[x0\], x7
+ 51c: 0da72400 st4 {v0.b-v3.b}\[1\], \[x0\], x7
+ 520: 0d874800 st1 {v0.h}\[1\], \[x0\], x7
+ 524: 0da74800 st2 {v0.h, v1.h}\[1\], \[x0\], x7
+ 528: 0d876800 st3 {v0.h-v2.h}\[1\], \[x0\], x7
+ 52c: 0da76800 st4 {v0.h-v3.h}\[1\], \[x0\], x7
+ 530: 0d879000 st1 {v0.s}\[1\], \[x0\], x7
+ 534: 0da79000 st2 {v0.s, v1.s}\[1\], \[x0\], x7
+ 538: 0d87b000 st3 {v0.s-v2.s}\[1\], \[x0\], x7
+ 53c: 0da7b000 st4 {v0.s-v3.s}\[1\], \[x0\], x7
+ 540: 4d878400 st1 {v0.d}\[1\], \[x0\], x7
+ 544: 4da78400 st2 {v0.d, v1.d}\[1\], \[x0\], x7
+ 548: 4d87a400 st3 {v0.d-v2.d}\[1\], \[x0\], x7
+ 54c: 4da7a400 st4 {v0.d-v3.d}\[1\], \[x0\], x7
--- /dev/null
+
+ # ARMv8 tests to test neon register
+ # lists syntax.
+ .text
+ .arch armv8
+
+ # Post-index multiple elements
+
+ .macro ldst1_reg_list_post_imm_64 inst type
+ \inst\()1 {v0.\type}, [x0], #8
+ \inst\()1 {v0.\type, v1.\type}, [x0], #16
+ \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #24
+ \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
+ .endm
+
+ .irp instr ld,st
+ .irp bits_64 8b, 4h, 2s, 1d
+ ldst1_reg_list_post_imm_64 \instr \bits_64
+ .endr
+ .endr
+
+ .macro ldst1_reg_list_post_imm_128 inst type
+ \inst\()1 {v0.\type}, [x0], #16
+ \inst\()1 {v0.\type, v1.\type}, [x0], #32
+ \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #48
+ \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
+ .endm
+
+ .irp instr ld,st
+ .irp bits_128 16b, 8h, 4s, 2d
+ ldst1_reg_list_post_imm_128 \instr \bits_128
+ .endr
+ .endr
+
+ .macro ldst1_reg_list_post_reg inst type postreg
+ \inst\()1 {v0.\type}, [x0], \postreg
+ \inst\()1 {v0.\type, v1.\type}, [x0], \postreg
+ \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
+ \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
+ .endm
+
+ .irp instr ld,st
+ .irp bits 8b, 4h, 2s, 1d, 16b, 8h, 4s, 2d
+ ldst1_reg_list_post_reg \instr \bits x7
+ .endr
+ .endr
+
+ .macro ldst2_reg_list_post_imm_reg_64 inst type postreg
+ \inst\()2 {v0.\type, v1.\type}, [x0], #16
+ .ifnb \postreg
+ \inst\()2 {v0.\type, v1.\type}, [x0], \postreg
+ .endif
+ .endm
+
+ .macro ldst2_reg_list_post_imm_reg_128 inst type postreg
+ \inst\()2 {v0.\type, v1.\type}, [x0], #32
+ .ifnb \postreg
+ \inst\()2 {v0.\type, v1.\type}, [x0], \postreg
+ .endif
+ .endm
+
+ .irp instr ld,st
+ .irp bits_64 8b, 4h, 2s
+ ldst2_reg_list_post_imm_reg_64 \instr \bits_64 x7
+ .endr
+ .endr
+
+ .irp instr ld,st
+ .irp bits_128 16b, 8h, 4s, 2d
+ ldst2_reg_list_post_imm_reg_128 \instr \bits_128 x7
+ .endr
+ .endr
+
+ .macro ldst34_reg_list_post_imm_reg_64 inst type postreg
+ \inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], #24
+ \inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
+ \inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
+ \inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
+ .endm
+
+ .macro ldst34_reg_list_post_imm_reg_128 inst type postreg
+ \inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], #48
+ \inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
+ \inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
+ \inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
+ .endm
+
+ .irp instr ld,st
+ .irp bits_64 8b, 4h, 2s
+ ldst34_reg_list_post_imm_reg_64 \instr \bits_64 x7
+ .endr
+ .endr
+
+ .irp instr ld,st
+ .irp bits_128 16b, 8h, 4s, 2d
+ ldst34_reg_list_post_imm_reg_128 \instr \bits_128 x7
+ .endr
+ .endr
+
+
+ # Post Index Vector-element form with replicate (Immediate offset)
+
+ # Consecutive registers in reg list
+
+ .macro ldstn_index_rep_B_imm inst index type rep
+ \inst\()1\rep {v0.\type}\index, [x0], #1
+ \inst\()2\rep {v0.\type, v1.\type}\index, [x0], #2
+ \inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #3
+ \inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #4
+ .endm
+
+ # Vector element with index
+
+ .irp instr, ld, st
+ ldstn_index_rep_B_imm \instr index="[1]" type=b rep=""
+ .ifnc \instr, st
+ .irp types 8b, 16b
+ ldstn_index_rep_B_imm \instr index="" type=\types rep="r"
+ .endr
+ .endif
+ .endr
+
+ .macro ldstn_index_rep_H_imm inst index type rep
+ \inst\()1\rep {v0.\type}\index, [x0], #2
+ \inst\()2\rep {v0.\type, v1.\type}\index, [x0], #4
+ \inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #6
+ \inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #8
+ .endm
+
+ .irp instr, ld, st
+ ldstn_index_rep_H_imm \instr index="[1]" type=h rep=""
+ .ifnc \instr, st
+ .irp types 4h, 8h
+ ldstn_index_rep_H_imm \instr index="" type=\types rep="r"
+ .endr
+ .endif
+ .endr
+
+ .macro ldstn_index_rep_S_imm inst index type rep
+ \inst\()1\rep {v0.\type}\index, [x0], #4
+ \inst\()2\rep {v0.\type, v1.\type}\index, [x0], #8
+ \inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #12
+ \inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #16
+ .endm
+
+ .irp instr, ld, st
+ ldstn_index_rep_S_imm \instr index="[1]" type=s rep=""
+ .ifnc \instr, st
+ .irp types 2s, 4s
+ ldstn_index_rep_S_imm \instr index="" type=\types rep="r"
+ .endr
+ .endif
+ .endr
+
+ .macro ldstn_index_rep_D_imm inst index type rep
+ \inst\()1\rep {v0.\type}\index, [x0], #8
+ \inst\()2\rep {v0.\type, v1.\type}\index, [x0], #16
+ \inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #24
+ \inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #32
+ .endm
+
+ .irp instr, ld, st
+ ldstn_index_rep_D_imm \instr index="[1]" type=d rep=""
+ .ifnc \instr, st
+ .irp types 1d, 2d
+ ldstn_index_rep_D_imm \instr index="" type=\types rep="r"
+ .endr
+ .endif
+ .endr
+
+ # Post Index Vector-element form with replicate (Register offset)
+ # This could have been factored into Post-index multiple
+ # element macros but this would make this already-looking-complex
+ # testcase look more complex!
+
+ # Consecutive registers in reg list
+
+ .macro ldstn_index_rep_reg inst index type rep postreg
+ \inst\()1\rep {v0.\type}\index, [x0], \postreg
+ \inst\()2\rep {v0.\type, v1.\type}\index, [x0], \postreg
+ \inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], \postreg
+ \inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], \postreg
+ .endm
+
+ .irp instr, ld, st
+ .irp itypes b,h,s,d
+ ldstn_index_rep_reg \instr index="[1]" type=\itypes rep="" postreg=x7
+ .endr
+ .ifnc \instr, st
+ .irp types 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
+ ldstn_index_rep_reg \instr index="" type=\types rep="r" postreg=x7
+ .endr
+ .endif
+ .endr
+
+ # ### End of test
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 0c407000 ld1 {v0.8b}, \[x0\]
+ 4: 0c40a000 ld1 {v0.8b, v1.8b}, \[x0\]
+ 8: 0c406000 ld1 {v0.8b-v2.8b}, \[x0\]
+ c: 0c402000 ld1 {v0.8b-v3.8b}, \[x0\]
+ 10: 0c408000 ld2 {v0.8b, v1.8b}, \[x0\]
+ 14: 0c404000 ld3 {v0.8b-v2.8b}, \[x0\]
+ 18: 0c400000 ld4 {v0.8b-v3.8b}, \[x0\]
+ 1c: 0c007000 st1 {v0.8b}, \[x0\]
+ 20: 0c00a000 st1 {v0.8b, v1.8b}, \[x0\]
+ 24: 0c006000 st1 {v0.8b-v2.8b}, \[x0\]
+ 28: 0c002000 st1 {v0.8b-v3.8b}, \[x0\]
+ 2c: 0c008000 st2 {v0.8b, v1.8b}, \[x0\]
+ 30: 0c004000 st3 {v0.8b-v2.8b}, \[x0\]
+ 34: 0c000000 st4 {v0.8b-v3.8b}, \[x0\]
+ 38: 4c407000 ld1 {v0.16b}, \[x0\]
+ 3c: 4c40a000 ld1 {v0.16b, v1.16b}, \[x0\]
+ 40: 4c406000 ld1 {v0.16b-v2.16b}, \[x0\]
+ 44: 4c402000 ld1 {v0.16b-v3.16b}, \[x0\]
+ 48: 4c408000 ld2 {v0.16b, v1.16b}, \[x0\]
+ 4c: 4c404000 ld3 {v0.16b-v2.16b}, \[x0\]
+ 50: 4c400000 ld4 {v0.16b-v3.16b}, \[x0\]
+ 54: 4c007000 st1 {v0.16b}, \[x0\]
+ 58: 4c00a000 st1 {v0.16b, v1.16b}, \[x0\]
+ 5c: 4c006000 st1 {v0.16b-v2.16b}, \[x0\]
+ 60: 4c002000 st1 {v0.16b-v3.16b}, \[x0\]
+ 64: 4c008000 st2 {v0.16b, v1.16b}, \[x0\]
+ 68: 4c004000 st3 {v0.16b-v2.16b}, \[x0\]
+ 6c: 4c000000 st4 {v0.16b-v3.16b}, \[x0\]
+ 70: 0c407400 ld1 {v0.4h}, \[x0\]
+ 74: 0c40a400 ld1 {v0.4h, v1.4h}, \[x0\]
+ 78: 0c406400 ld1 {v0.4h-v2.4h}, \[x0\]
+ 7c: 0c402400 ld1 {v0.4h-v3.4h}, \[x0\]
+ 80: 0c408400 ld2 {v0.4h, v1.4h}, \[x0\]
+ 84: 0c404400 ld3 {v0.4h-v2.4h}, \[x0\]
+ 88: 0c400400 ld4 {v0.4h-v3.4h}, \[x0\]
+ 8c: 0c007400 st1 {v0.4h}, \[x0\]
+ 90: 0c00a400 st1 {v0.4h, v1.4h}, \[x0\]
+ 94: 0c006400 st1 {v0.4h-v2.4h}, \[x0\]
+ 98: 0c002400 st1 {v0.4h-v3.4h}, \[x0\]
+ 9c: 0c008400 st2 {v0.4h, v1.4h}, \[x0\]
+ a0: 0c004400 st3 {v0.4h-v2.4h}, \[x0\]
+ a4: 0c000400 st4 {v0.4h-v3.4h}, \[x0\]
+ a8: 4c407400 ld1 {v0.8h}, \[x0\]
+ ac: 4c40a400 ld1 {v0.8h, v1.8h}, \[x0\]
+ b0: 4c406400 ld1 {v0.8h-v2.8h}, \[x0\]
+ b4: 4c402400 ld1 {v0.8h-v3.8h}, \[x0\]
+ b8: 4c408400 ld2 {v0.8h, v1.8h}, \[x0\]
+ bc: 4c404400 ld3 {v0.8h-v2.8h}, \[x0\]
+ c0: 4c400400 ld4 {v0.8h-v3.8h}, \[x0\]
+ c4: 4c007400 st1 {v0.8h}, \[x0\]
+ c8: 4c00a400 st1 {v0.8h, v1.8h}, \[x0\]
+ cc: 4c006400 st1 {v0.8h-v2.8h}, \[x0\]
+ d0: 4c002400 st1 {v0.8h-v3.8h}, \[x0\]
+ d4: 4c008400 st2 {v0.8h, v1.8h}, \[x0\]
+ d8: 4c004400 st3 {v0.8h-v2.8h}, \[x0\]
+ dc: 4c000400 st4 {v0.8h-v3.8h}, \[x0\]
+ e0: 0c407800 ld1 {v0.2s}, \[x0\]
+ e4: 0c40a800 ld1 {v0.2s, v1.2s}, \[x0\]
+ e8: 0c406800 ld1 {v0.2s-v2.2s}, \[x0\]
+ ec: 0c402800 ld1 {v0.2s-v3.2s}, \[x0\]
+ f0: 0c408800 ld2 {v0.2s, v1.2s}, \[x0\]
+ f4: 0c404800 ld3 {v0.2s-v2.2s}, \[x0\]
+ f8: 0c400800 ld4 {v0.2s-v3.2s}, \[x0\]
+ fc: 0c007800 st1 {v0.2s}, \[x0\]
+ 100: 0c00a800 st1 {v0.2s, v1.2s}, \[x0\]
+ 104: 0c006800 st1 {v0.2s-v2.2s}, \[x0\]
+ 108: 0c002800 st1 {v0.2s-v3.2s}, \[x0\]
+ 10c: 0c008800 st2 {v0.2s, v1.2s}, \[x0\]
+ 110: 0c004800 st3 {v0.2s-v2.2s}, \[x0\]
+ 114: 0c000800 st4 {v0.2s-v3.2s}, \[x0\]
+ 118: 4c407800 ld1 {v0.4s}, \[x0\]
+ 11c: 4c40a800 ld1 {v0.4s, v1.4s}, \[x0\]
+ 120: 4c406800 ld1 {v0.4s-v2.4s}, \[x0\]
+ 124: 4c402800 ld1 {v0.4s-v3.4s}, \[x0\]
+ 128: 4c408800 ld2 {v0.4s, v1.4s}, \[x0\]
+ 12c: 4c404800 ld3 {v0.4s-v2.4s}, \[x0\]
+ 130: 4c400800 ld4 {v0.4s-v3.4s}, \[x0\]
+ 134: 4c007800 st1 {v0.4s}, \[x0\]
+ 138: 4c00a800 st1 {v0.4s, v1.4s}, \[x0\]
+ 13c: 4c006800 st1 {v0.4s-v2.4s}, \[x0\]
+ 140: 4c002800 st1 {v0.4s-v3.4s}, \[x0\]
+ 144: 4c008800 st2 {v0.4s, v1.4s}, \[x0\]
+ 148: 4c004800 st3 {v0.4s-v2.4s}, \[x0\]
+ 14c: 4c000800 st4 {v0.4s-v3.4s}, \[x0\]
+ 150: 4c407c00 ld1 {v0.2d}, \[x0\]
+ 154: 4c40ac00 ld1 {v0.2d, v1.2d}, \[x0\]
+ 158: 4c406c00 ld1 {v0.2d-v2.2d}, \[x0\]
+ 15c: 4c402c00 ld1 {v0.2d-v3.2d}, \[x0\]
+ 160: 4c408c00 ld2 {v0.2d, v1.2d}, \[x0\]
+ 164: 4c404c00 ld3 {v0.2d-v2.2d}, \[x0\]
+ 168: 4c400c00 ld4 {v0.2d-v3.2d}, \[x0\]
+ 16c: 4c007c00 st1 {v0.2d}, \[x0\]
+ 170: 4c00ac00 st1 {v0.2d, v1.2d}, \[x0\]
+ 174: 4c006c00 st1 {v0.2d-v2.2d}, \[x0\]
+ 178: 4c002c00 st1 {v0.2d-v3.2d}, \[x0\]
+ 17c: 4c008c00 st2 {v0.2d, v1.2d}, \[x0\]
+ 180: 4c004c00 st3 {v0.2d-v2.2d}, \[x0\]
+ 184: 4c000c00 st4 {v0.2d-v3.2d}, \[x0\]
+ 188: 0d400400 ld1 {v0.b}\[1\], \[x0\]
+ 18c: 0d600400 ld2 {v0.b, v1.b}\[1\], \[x0\]
+ 190: 0d402400 ld3 {v0.b-v2.b}\[1\], \[x0\]
+ 194: 0d602400 ld4 {v0.b-v3.b}\[1\], \[x0\]
+ 198: 0d000400 st1 {v0.b}\[1\], \[x0\]
+ 19c: 0d200400 st2 {v0.b, v1.b}\[1\], \[x0\]
+ 1a0: 0d002400 st3 {v0.b-v2.b}\[1\], \[x0\]
+ 1a4: 0d202400 st4 {v0.b-v3.b}\[1\], \[x0\]
+ 1a8: 0d400400 ld1 {v0.b}\[1\], \[x0\]
+ 1ac: 0d600400 ld2 {v0.b, v1.b}\[1\], \[x0\]
+ 1b0: 0d402400 ld3 {v0.b-v2.b}\[1\], \[x0\]
+ 1b4: 0d602400 ld4 {v0.b-v3.b}\[1\], \[x0\]
+ 1b8: 0d000400 st1 {v0.b}\[1\], \[x0\]
+ 1bc: 0d200400 st2 {v0.b, v1.b}\[1\], \[x0\]
+ 1c0: 0d002400 st3 {v0.b-v2.b}\[1\], \[x0\]
+ 1c4: 0d202400 st4 {v0.b-v3.b}\[1\], \[x0\]
+ 1c8: 0d404800 ld1 {v0.h}\[1\], \[x0\]
+ 1cc: 0d604800 ld2 {v0.h, v1.h}\[1\], \[x0\]
+ 1d0: 0d406800 ld3 {v0.h-v2.h}\[1\], \[x0\]
+ 1d4: 0d606800 ld4 {v0.h-v3.h}\[1\], \[x0\]
+ 1d8: 0d004800 st1 {v0.h}\[1\], \[x0\]
+ 1dc: 0d204800 st2 {v0.h, v1.h}\[1\], \[x0\]
+ 1e0: 0d006800 st3 {v0.h-v2.h}\[1\], \[x0\]
+ 1e4: 0d206800 st4 {v0.h-v3.h}\[1\], \[x0\]
+ 1e8: 0d404800 ld1 {v0.h}\[1\], \[x0\]
+ 1ec: 0d604800 ld2 {v0.h, v1.h}\[1\], \[x0\]
+ 1f0: 0d406800 ld3 {v0.h-v2.h}\[1\], \[x0\]
+ 1f4: 0d606800 ld4 {v0.h-v3.h}\[1\], \[x0\]
+ 1f8: 0d004800 st1 {v0.h}\[1\], \[x0\]
+ 1fc: 0d204800 st2 {v0.h, v1.h}\[1\], \[x0\]
+ 200: 0d006800 st3 {v0.h-v2.h}\[1\], \[x0\]
+ 204: 0d206800 st4 {v0.h-v3.h}\[1\], \[x0\]
+ 208: 0d409000 ld1 {v0.s}\[1\], \[x0\]
+ 20c: 0d609000 ld2 {v0.s, v1.s}\[1\], \[x0\]
+ 210: 0d40b000 ld3 {v0.s-v2.s}\[1\], \[x0\]
+ 214: 0d60b000 ld4 {v0.s-v3.s}\[1\], \[x0\]
+ 218: 0d009000 st1 {v0.s}\[1\], \[x0\]
+ 21c: 0d209000 st2 {v0.s, v1.s}\[1\], \[x0\]
+ 220: 0d00b000 st3 {v0.s-v2.s}\[1\], \[x0\]
+ 224: 0d20b000 st4 {v0.s-v3.s}\[1\], \[x0\]
+ 228: 0d409000 ld1 {v0.s}\[1\], \[x0\]
+ 22c: 0d609000 ld2 {v0.s, v1.s}\[1\], \[x0\]
+ 230: 0d40b000 ld3 {v0.s-v2.s}\[1\], \[x0\]
+ 234: 0d60b000 ld4 {v0.s-v3.s}\[1\], \[x0\]
+ 238: 0d009000 st1 {v0.s}\[1\], \[x0\]
+ 23c: 0d209000 st2 {v0.s, v1.s}\[1\], \[x0\]
+ 240: 0d00b000 st3 {v0.s-v2.s}\[1\], \[x0\]
+ 244: 0d20b000 st4 {v0.s-v3.s}\[1\], \[x0\]
+ 248: 4d408400 ld1 {v0.d}\[1\], \[x0\]
+ 24c: 4d608400 ld2 {v0.d, v1.d}\[1\], \[x0\]
+ 250: 4d40a400 ld3 {v0.d-v2.d}\[1\], \[x0\]
+ 254: 4d60a400 ld4 {v0.d-v3.d}\[1\], \[x0\]
+ 258: 4d008400 st1 {v0.d}\[1\], \[x0\]
+ 25c: 4d208400 st2 {v0.d, v1.d}\[1\], \[x0\]
+ 260: 4d00a400 st3 {v0.d-v2.d}\[1\], \[x0\]
+ 264: 4d20a400 st4 {v0.d-v3.d}\[1\], \[x0\]
+ 268: 0d40c000 ld1r {v0.8b}, \[x0\]
+ 26c: 0d60c000 ld2r {v0.8b, v1.8b}, \[x0\]
+ 270: 0d40e000 ld3r {v0.8b-v2.8b}, \[x0\]
+ 274: 0d60e000 ld4r {v0.8b-v3.8b}, \[x0\]
+ 278: 4d40c000 ld1r {v0.16b}, \[x0\]
+ 27c: 4d60c000 ld2r {v0.16b, v1.16b}, \[x0\]
+ 280: 4d40e000 ld3r {v0.16b-v2.16b}, \[x0\]
+ 284: 4d60e000 ld4r {v0.16b-v3.16b}, \[x0\]
+ 288: 0d40c400 ld1r {v0.4h}, \[x0\]
+ 28c: 0d60c400 ld2r {v0.4h, v1.4h}, \[x0\]
+ 290: 0d40e400 ld3r {v0.4h-v2.4h}, \[x0\]
+ 294: 0d60e400 ld4r {v0.4h-v3.4h}, \[x0\]
+ 298: 4d40c400 ld1r {v0.8h}, \[x0\]
+ 29c: 4d60c400 ld2r {v0.8h, v1.8h}, \[x0\]
+ 2a0: 4d40e400 ld3r {v0.8h-v2.8h}, \[x0\]
+ 2a4: 4d60e400 ld4r {v0.8h-v3.8h}, \[x0\]
+ 2a8: 0d40c800 ld1r {v0.2s}, \[x0\]
+ 2ac: 0d60c800 ld2r {v0.2s, v1.2s}, \[x0\]
+ 2b0: 0d40e800 ld3r {v0.2s-v2.2s}, \[x0\]
+ 2b4: 0d60e800 ld4r {v0.2s-v3.2s}, \[x0\]
+ 2b8: 4d40c800 ld1r {v0.4s}, \[x0\]
+ 2bc: 4d60c800 ld2r {v0.4s, v1.4s}, \[x0\]
+ 2c0: 4d40e800 ld3r {v0.4s-v2.4s}, \[x0\]
+ 2c4: 4d60e800 ld4r {v0.4s-v3.4s}, \[x0\]
+ 2c8: 0d40cc00 ld1r {v0.1d}, \[x0\]
+ 2cc: 0d60cc00 ld2r {v0.1d, v1.1d}, \[x0\]
+ 2d0: 0d40ec00 ld3r {v0.1d-v2.1d}, \[x0\]
+ 2d4: 0d60ec00 ld4r {v0.1d-v3.1d}, \[x0\]
+ 2d8: 4d40cc00 ld1r {v0.2d}, \[x0\]
+ 2dc: 4d60cc00 ld2r {v0.2d, v1.2d}, \[x0\]
+ 2e0: 4d40ec00 ld3r {v0.2d-v2.2d}, \[x0\]
+ 2e4: 4d60ec00 ld4r {v0.2d-v3.2d}, \[x0\]
--- /dev/null
+
+ # ARMv8 tests to test neon register
+ # lists syntax.
+ .macro ldnstn_reg_list type inst index rep
+ \inst\()1\rep {v0.\type}\index, [x0]
+ .ifb \index
+ .ifb \rep
+ \inst\()1 {v0.\type, v1.\type}\index, [x0]
+ \inst\()1 {v0.\type, v1.\type, v2.\type}\index, [x0]
+ \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0]
+ .endif
+ .endif
+
+ \inst\()2\rep {v0.\type, v1.\type}\index, [x0]
+
+ \inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0]
+
+ \inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0]
+
+ .endm
+
+ .text
+ .arch armv8
+
+ ldnstn_reg_list type="8B", inst="ld" index="" rep=""
+ ldnstn_reg_list type="8B", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="16B", inst="ld" index="" rep=""
+ ldnstn_reg_list type="16B", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="4H", inst="ld" index="" rep=""
+ ldnstn_reg_list type="4H", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="8H", inst="ld" index="" rep=""
+ ldnstn_reg_list type="8H", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="2S", inst="ld" index="" rep=""
+ ldnstn_reg_list type="2S", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="4S", inst="ld" index="" rep=""
+ ldnstn_reg_list type="4S", inst="st" index="" rep=""
+
+ ldnstn_reg_list type="2D", inst="ld" index="" rep=""
+ ldnstn_reg_list type="2D", inst="st" index="" rep=""
+
+ # vector-element form
+ ldnstn_reg_list type="B", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="B", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="B", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="B", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="H", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="H", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="H", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="H", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="S", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="S", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="S", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="S", inst="st" index="[1]" rep=""
+
+ ldnstn_reg_list type="D", inst="ld" index="[1]" rep=""
+ ldnstn_reg_list type="D", inst="st" index="[1]" rep=""
+
+ # replicate form
+ ldnstn_reg_list type="8B", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="16B", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="4H", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="8H", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="2S", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="4S", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="1D", inst="ld" index="" rep="r"
+
+ ldnstn_reg_list type="2D", inst="ld" index="" rep="r"
--- /dev/null
+#source: alias.s
+#objdump: -dr -Mno-aliases
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 13823c20 extr w0, w1, w2, #15
+ 4: 93c23c20 extr x0, x1, x2, #15
+ 8: 13831c60 extr w0, w3, w3, #7
+ c: 93c51ca0 extr x0, x5, x5, #7
+ 10: 138748e6 extr w6, w7, w7, #18
+ 14: 93c7a0e6 extr x6, x7, x7, #40
+ 18: 1b020c20 madd w0, w1, w2, w3
+ 1c: 1b027c20 madd w0, w1, w2, wzr
+ 20: 1b027c20 madd w0, w1, w2, wzr
+ 24: 9b028c20 msub x0, x1, x2, x3
+ 28: 9b02fc20 msub x0, x1, x2, xzr
+ 2c: 9b02fc20 msub x0, x1, x2, xzr
+ 30: 9b220c20 smaddl x0, w1, w2, x3
+ 34: 9b227c20 smaddl x0, w1, w2, xzr
+ 38: 9b227c20 smaddl x0, w1, w2, xzr
+ 3c: 9b228c20 smsubl x0, w1, w2, x3
+ 40: 9b22fc20 smsubl x0, w1, w2, xzr
+ 44: 9b22fc20 smsubl x0, w1, w2, xzr
+ 48: 9ba20c20 umaddl x0, w1, w2, x3
+ 4c: 9ba27c20 umaddl x0, w1, w2, xzr
+ 50: 9ba27c20 umaddl x0, w1, w2, xzr
+ 54: 9ba28c20 umsubl x0, w1, w2, x3
+ 58: 9ba2fc20 umsubl x0, w1, w2, xzr
+ 5c: 9ba2fc20 umsubl x0, w1, w2, xzr
+ 60: 1a9f0420 csinc w0, w1, wzr, eq
+ 64: 1a810420 csinc w0, w1, w1, eq
+ 68: 1a810420 csinc w0, w1, w1, eq
+ 6c: 1a9f37e0 csinc w0, wzr, wzr, cc
+ 70: 1a9f37e0 csinc w0, wzr, wzr, cc
+ 74: da9f2020 csinv x0, x1, xzr, cs
+ 78: da812020 csinv x0, x1, x1, cs
+ 7c: da812020 csinv x0, x1, x1, cs
+ 80: da9f43e0 csinv x0, xzr, xzr, mi
+ 84: da9f43e0 csinv x0, xzr, xzr, mi
+ 88: da9eb7e0 csneg x0, xzr, x30, lt
+ 8c: da9eb7c0 csneg x0, x30, x30, lt
+ 90: da9eb7c0 csneg x0, x30, x30, lt
+ 94: ea020020 ands x0, x1, x2
+ 98: ea02003f ands xzr, x1, x2
+ 9c: ea02003f ands xzr, x1, x2
+ a0: 6ac27c3f ands wzr, w1, w2, ror #31
+ a4: 6ac27c3f ands wzr, w1, w2, ror #31
+ a8: aa220020 orn x0, x1, x2
+ ac: aa22003f orn xzr, x1, x2
+ b0: aa2203e0 orn x0, xzr, x2
+ b4: aa2203e0 orn x0, xzr, x2
+ b8: 2aa23c3f orn wzr, w1, w2, asr #15
+ bc: 2aa23fe0 orn w0, wzr, w2, asr #15
+ c0: 2aa23fe0 orn w0, wzr, w2, asr #15
+ c4: 0ea11c20 orr v0.8b, v1.8b, v1.8b
+ c8: 0ea21c20 orr v0.8b, v1.8b, v2.8b
+ cc: 0ea11c20 orr v0.8b, v1.8b, v1.8b
+ d0: aa1103e3 orr x3, xzr, x17
+ d4: aa110003 orr x3, x0, x17
+ d8: aa1103e3 orr x3, xzr, x17
+ dc: 92628421 and x1, x1, #0xffffffffc0000000
+ e0: 927ef800 and x0, x0, #0xfffffffffffffffd
+ e4: 121e7800 and w0, w0, #0xfffffffd
+ e8: 721d1f1f ands wzr, w24, #0x7f8
+ ec: 721d1f00 ands w0, w24, #0x7f8
+ f0: 721d1f1f ands wzr, w24, #0x7f8
+ f4: 7100807f subs wzr, w3, #0x20
+ f8: 710083e3 subs w3, wsp, #0x20
+ fc: 7100807f subs wzr, w3, #0x20
+ 100: b13ffdff adds xzr, x15, #0xfff
+ 104: f13fffef subs x15, sp, #0xfff
+ 108: b13ffdff adds xzr, x15, #0xfff
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: d4a001e1 dcps1 #0xf
+ 4: d4a00001 dcps1
+ 8: d4a00001 dcps1
+ c: d4a003e2 dcps2 #0x1f
+ 10: d4a00002 dcps2
+ 14: d4a00002 dcps2
+ 18: d4a007e3 dcps3 #0x3f
+ 1c: d4a00003 dcps3
+ 20: d4a00003 dcps3
+ 24: d65f00e0 ret x7
+ 28: d65f03c0 ret
+ 2c: d65f03c0 ret
+ 30: d503305f clrex #0x0
+ 34: d503395f clrex #0x9
+ 38: d5033f5f clrex
+ 3c: d5033f5f clrex
+ 40: d508001f sys #0, C0, C0, #0
+ 44: 10000000 adr x0, 0 <sym>
+ 44: R_AARCH64_ADR_PREL_LO21 sym
+ 48: f9400001 ldr x1, \[x0\]
+ 48: R_AARCH64_LDST64_ABS_LO12_NC sym
+ 4c: f9400001 ldr x1, \[x0\]
+ 4c: R_AARCH64_LDST64_ABS_LO12_NC sym
+ 50: f9000001 str x1, \[x0\]
+ 50: R_AARCH64_LDST64_ABS_LO12_NC sym
+ 54: f9000001 str x1, \[x0\]
+ 54: R_AARCH64_LDST64_ABS_LO12_NC sym
--- /dev/null
+// Test instructions with opertional operand or other optional element.
+
+.text
+ dcps1 #15
+ dcps1 #0
+ dcps1
+ dcps2 #31
+ dcps2 #0
+ dcps2
+ dcps3 #63
+ dcps3 #0
+ dcps3
+
+ ret x7
+ ret x30
+ ret
+
+ clrex #0
+ clrex #9
+ clrex #15
+ clrex
+
+ sys #0, c0, c0, #0
+
+ // Optional leading # for symbolic load/store offsets.
+ adr x0, sym
+ ldr x1,[x0,:lo12:sym]
+ ldr x1,[x0,#:lo12:sym]
+ str x1,[x0,:lo12:sym]
+ str x1,[x0,#:lo12:sym]
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 4f03e420 movi v0\.16b, #0x61
+ 4: 98000181 ldrsw x1, 34 <\.text\+0x34>
+ 8: 98000007 ldrsw x7, 0 <\.text>
+ 8: R_AARCH64_LD_PREL_LO19 \.data\+0x4
+ c: fa42a02a ccmp x1, x2, #0xa, ge
+ 10: 53001eaf uxtb w15, w21
+ 14: 53003f67 uxth w7, w27
+ 18: 2a1f03e8 mov w8, wzr
+ 1c: ab2013e0 adds x0, sp, w0, uxtb #4
+ 20: ab2033e0 adds x0, sp, w0, uxth #4
+ 24: ab2053e0 adds x0, sp, w0, uxtw #4
+ 28: ab2083e0 adds x0, sp, w0, sxtb
+ 2c: ab20a7e0 adds x0, sp, w0, sxth #1
+ 30: ab20cbe0 adds x0, sp, w0, sxtw #2
+ 34: deadbeef \.word 0xdeadbeef
--- /dev/null
+// programmer-friendly.s Test file for AArch64 instructions variants that are
+// not part of the architectural assembly syntax but are supported for the
+// ease of assembly level programming.
+
+.text
+ // The preferred architectural syntax does not accept the shifter
+ // LSL or any other shift operator, when the destination register
+ // has the shape of 16B or 8B.
+ movi v0.16b, 97, lsl 0
+
+ // LDR Wt, label | =value
+ // As a convenience assemblers will typically permit the notation
+ // "=value" in conjunction with the pc-relative literal load
+ // instructions to automatically place an immediate value or
+ // symbolic address in a nearby literal pool and generate a hidden
+ // label which references it.
+ ldrsw x1, =0xdeadbeef
+ ldrsw x7, u16_lable + 4
+
+ // CCMN Xn, Xm, #uimm4, cond
+ // As a convenience, GAS accepts a string representation for #uimm4,
+ // e.g. NzCv for #0xa (0b1010).
+ ccmp x1, x2, NzCv, GE
+
+.data
+u16_lable:
+ .word 0xdeadbeef
+ .word 0xcafebabe
+
+.text
+ // UXT[BHW] Wd, Wn
+ // Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
+ // for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
+ // encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
+ // A programmer-friendly assembler should accept a destination Xd in
+ // place of Wd, however that is not the preferred form for disassembly.
+ uxtb x15, w21
+ uxth x7, w27
+ uxtw x8, wzr
+
+
+ // ADDS <Xd>, <Xn|SP>, <R><m>{, UXTB {#<amount>}}
+ // In the 64-bit form, the final register operand is written as Wm
+ // for all but the (possibly omitted) UXTX/LSL and SXTX
+ // operators.
+ // As a programmer-friendly assembler, we allow e.g.
+ // ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} by changing it to
+ // ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}.
+ adds x0, sp, x0, uxtb #4
+ adds x0, sp, x0, uxth #4
+ adds x0, sp, x0, uxtw #4
+ adds x0, sp, x0, sxtb #0
+ adds x0, sp, x0, sxth #1
+ adds x0, sp, x0, sxtw #2
--- /dev/null
+#objdump: -dr
+#skip: aarch64_be-*-*
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: d65f03c0 ret
+ 4: ffff005c \.word 0xffff005c
+ 8: 0000005c \.word 0x0000005c
+ c: ffffffff \.word 0xffffffff
+ 10: 0000005c \.word 0x0000005c
+ 14: 00000000 \.word 0x00000000
+ 18: ffffffff \.word 0xffffffff
+ 1c: ffffffff \.word 0xffffffff
+ \.\.\.
+ 20: R_AARCH64_ABS64 \.text\+0x12345660
+ 28: ffffffff \.word 0xffffffff
+ 2c: ffffffff \.word 0xffffffff
+ 30: ffff0000 \.word 0xffff0000
+ 30: R_AARCH64_PREL16 global\+0x2c
+ 34: 00000000 \.word 0x00000000
+ 34: R_AARCH64_PREL32 global\+0x30
+ 38: ffffffff \.word 0xffffffff
+ 3c: d503201f nop
+ \.\.\.
+ 40: R_AARCH64_PREL64 global\+0x3c
+ 48: ffffffff \.word 0xffffffff
+ 4c: ffffffff \.word 0xffffffff
+ \.\.\.
+ 50: R_AARCH64_ABS64 global\+0x12345678
+ 58: ffffffff \.word 0xffffffff
+ 5c: ffffffff \.word 0xffffffff
--- /dev/null
+func:
+ ret
+
+.L1:
+ .balign 2
+ .hword local-.L1
+ .hword 0xffff
+ .balign 4
+ .word local-.L1
+ .word 0xffffffff
+ .balign 8
+ .xword local-.L1
+ .xword 0xffffffffffffffff
+ .xword local+0x12345600
+ .xword 0xffffffffffffffff
+
+ .balign 2
+ .hword global-.L1
+ .hword 0xffff
+ .balign 4
+ .word global-.L1
+ .word 0xffffffff
+ .balign 8
+ .xword global-.L1
+ .xword 0xffffffffffffffff
+ .xword global+0x12345678
+ .xword 0xffffffffffffffff
+
+local:
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: d281ffe0 movz x0, #0xfff
+ 4: 9280ffe0 movn x0, #0x7ff
+ 8: d2a24681 movz x1, #0x1234, lsl #16
+ c: f28acf01 movk x1, #0x5678
+ 10: 92a00001 movn x1, #0x0, lsl #16
+ 14: f29f0001 movk x1, #0xf800
+ 18: d2d55761 movz x1, #0xaabb, lsl #32
+ 1c: f2b99ba1 movk x1, #0xccdd, lsl #16
+ 20: f29ddfe1 movk x1, #0xeeff
+ 24: d2c00001 movz x1, #0x0, lsl #32
+ 24: R_AARCH64_MOVW_UABS_G2 \.data\+0x8
+ 28: f2a00001 movk x1, #0x0, lsl #16
+ 28: R_AARCH64_MOVW_UABS_G1_NC \.data\+0x8
+ 2c: f2800001 movk x1, #0x0
+ 2c: R_AARCH64_MOVW_UABS_G0_NC \.data\+0x8
+ 30: d2c00001 movz x1, #0x0, lsl #32
+ 30: R_AARCH64_MOVW_UABS_G2 xdata
+ 34: f2a00001 movk x1, #0x0, lsl #16
+ 34: R_AARCH64_MOVW_UABS_G1_NC xdata
+ 38: f2800001 movk x1, #0x0
+ 38: R_AARCH64_MOVW_UABS_G0_NC xdata
+ 3c: 92c00001 movn x1, #0x0, lsl #32
+ 40: f2bfffe1 movk x1, #0xffff, lsl #16
+ 44: f29f0001 movk x1, #0xf800
+ 48: d2ffffe1 movz x1, #0xffff, lsl #48
+ 4c: f2dfffe1 movk x1, #0xffff, lsl #32
+ 50: f2bfffe1 movk x1, #0xffff, lsl #16
+ 54: f29f0001 movk x1, #0xf800
+ 58: d2ffdb81 movz x1, #0xfedc, lsl #48
+ 5c: f2d75301 movk x1, #0xba98, lsl #32
+ 60: f2aeca81 movk x1, #0x7654, lsl #16
+ 64: f2864201 movk x1, #0x3210
+ 68: 58000920 ldr x0, 18c <llit>
+ 6c: 58000001 ldr x1, 0 <func>
+ 6c: R_AARCH64_LD_PREL_LO19 \.data\+0x8
+ 70: 58000002 ldr x2, 0 <xdata>
+ 70: R_AARCH64_LD_PREL_LO19 xdata\+0xc
+ 74: 100008c0 adr x0, 18c <llit>
+ 78: 10000001 adr x1, 0 <func>
+ 78: R_AARCH64_ADR_PREL_LO21 \.data\+0x8
+ 7c: 10000002 adr x2, 0 <func>
+ 7c: R_AARCH64_ADR_PREL_LO21 \.data\+0x1000
+ 80: 10000003 adr x3, 0 <xlit>
+ 80: R_AARCH64_ADR_PREL_LO21 xlit
+ 84: 10000004 adr x4, 0 <xdata>
+ 84: R_AARCH64_ADR_PREL_LO21 xdata\+0x10
+ 88: 10000005 adr x5, 0 <xdata>
+ 88: R_AARCH64_ADR_PREL_LO21 xdata\+0xff8
+ 8c: 90000000 adrp x0, 0 <func>
+ 8c: R_AARCH64_ADR_PREL_PG_HI21 \.text\+0x18c
+ 90: 90000001 adrp x1, 0 <func>
+ 90: R_AARCH64_ADR_PREL_PG_HI21 \.data\+0x8
+ 94: 90000002 adrp x2, 0 <func>
+ 94: R_AARCH64_ADR_PREL_PG_HI21 \.data\+0x1000
+ 98: 90000003 adrp x3, 0 <xlit>
+ 98: R_AARCH64_ADR_PREL_PG_HI21 xlit
+ 9c: 90000004 adrp x4, 0 <xdata>
+ 9c: R_AARCH64_ADR_PREL_PG_HI21 xdata\+0x10
+ a0: 90000005 adrp x5, 0 <xdata>
+ a0: R_AARCH64_ADR_PREL_PG_HI21 xdata\+0xff8
+ a4: 90000000 adrp x0, 0 <func>
+ a4: R_AARCH64_ADR_PREL_PG_HI21 \.text\+0x18c
+ a8: 90000001 adrp x1, 0 <func>
+ a8: R_AARCH64_ADR_PREL_PG_HI21 \.data\+0x8
+ ac: 90000002 adrp x2, 0 <func>
+ ac: R_AARCH64_ADR_PREL_PG_HI21 \.data\+0x1000
+ b0: 90000003 adrp x3, 0 <xlit>
+ b0: R_AARCH64_ADR_PREL_PG_HI21 xlit
+ b4: 90000004 adrp x4, 0 <xdata>
+ b4: R_AARCH64_ADR_PREL_PG_HI21 xdata\+0x10
+ b8: 90000005 adrp x5, 0 <xdata>
+ b8: R_AARCH64_ADR_PREL_PG_HI21 xdata\+0xff8
+ bc: 91000000 add x0, x0, #0x0
+ bc: R_AARCH64_ADD_ABS_LO12_NC \.text\+0x18c
+ c0: 91000021 add x1, x1, #0x0
+ c0: R_AARCH64_ADD_ABS_LO12_NC \.data\+0x8
+ c4: 91000042 add x2, x2, #0x0
+ c4: R_AARCH64_ADD_ABS_LO12_NC \.data\+0x1000
+ c8: 91000063 add x3, x3, #0x0
+ c8: R_AARCH64_ADD_ABS_LO12_NC xlit
+ cc: 91000084 add x4, x4, #0x0
+ cc: R_AARCH64_ADD_ABS_LO12_NC xdata\+0x10
+ d0: 910000a5 add x5, x5, #0x0
+ d0: R_AARCH64_ADD_ABS_LO12_NC xdata\+0xff8
+ d4: 913ffcc6 add x6, x6, #0xfff
+ d8: 39400000 ldrb w0, \[x0\]
+ d8: R_AARCH64_LDST8_ABS_LO12_NC \.text\+0x18c
+ dc: 39400021 ldrb w1, \[x1\]
+ dc: R_AARCH64_LDST8_ABS_LO12_NC \.data\+0x8
+ e0: 39400042 ldrb w2, \[x2\]
+ e0: R_AARCH64_LDST8_ABS_LO12_NC \.data\+0x1000
+ e4: 39400063 ldrb w3, \[x3\]
+ e4: R_AARCH64_LDST8_ABS_LO12_NC xlit
+ e8: 39400084 ldrb w4, \[x4\]
+ e8: R_AARCH64_LDST8_ABS_LO12_NC xdata\+0x10
+ ec: 394000a5 ldrb w5, \[x5\]
+ ec: R_AARCH64_LDST8_ABS_LO12_NC xdata\+0xff8
+ f0: 397ffcc6 ldrb w6, \[x6,#4095\]
+ f4: 360004e0 tbz w0, #0, 190 <lab>
+ f8: b6f80001 tbz x1, #63, 0 <xlab>
+ f8: R_AARCH64_TSTBR14 xlab
+ fc: 374004a2 tbnz w2, #8, 190 <lab>
+ 100: b7780002 tbnz x2, #47, 0 <xlab>
+ 100: R_AARCH64_TSTBR14 xlab
+ 104: 54000460 b\.eq 190 <lab>
+ 108: 54000000 b\.eq 0 <xlab>
+ 108: R_AARCH64_CONDBR19 xlab
+ 10c: b4000420 cbz x0, 190 <lab>
+ 110: b500001e cbnz x30, 0 <xlab>
+ 110: R_AARCH64_CONDBR19 xlab
+ 114: 1400001f b 190 <lab>
+ 118: 14000000 b 0 <xlab>
+ 118: R_AARCH64_JUMP26 xlab
+ 11c: 9400001d bl 190 <lab>
+ 120: 94000000 bl 0 <xlab>
+ 120: R_AARCH64_CALL26 xlab
+ 124: d2e24680 movz x0, #0x1234, lsl #48
+ 128: f2cacf00 movk x0, #0x5678, lsl #32
+ 12c: f2b35780 movk x0, #0x9abc, lsl #16
+ 130: f29bde00 movk x0, #0xdef0
+ 134: d2ffdb80 movz x0, #0xfedc, lsl #48
+ 138: f2d75300 movk x0, #0xba98, lsl #32
+ 13c: f2aeca80 movk x0, #0x7654, lsl #16
+ 140: f2864200 movk x0, #0x3210
+ 144: b2440c00 orr x0, x0, #0xf000000000000000
+ 148: 927cec00 and x0, x0, #0xfffffffffffffff0
+ 14c: 121c6c00 and w0, w0, #0xfffffff0
+ 150: d1200000 sub x0, x0, #0x800
+ 154: 913ffc00 add x0, x0, #0xfff
+ 158: 91200000 add x0, x0, #0x800
+ 15c: d13ffc00 sub x0, x0, #0xfff
+ 160: d41fffe1 svc #0xffff
+ 164: f8500420 ldr x0, \[x1\],#-256
+ 168: f8500c20 ldr x0, \[x1,#-256\]!
+ 16c: f8500020 ldr x0, \[x1,#-256\]
+ 170: f97ffc20 ldr x0, \[x1,#32760\]
+ 174: 79400000 ldrh w0, \[x0\]
+ 174: R_AARCH64_LDST16_ABS_LO12_NC \.text\+0x18c
+ 178: b9400021 ldr w1, \[x1\]
+ 178: R_AARCH64_LDST32_ABS_LO12_NC \.data\+0x8
+ 17c: f9400042 ldr x2, \[x2\]
+ 17c: R_AARCH64_LDST64_ABS_LO12_NC \.data\+0x1000
+ 180: 3dc00063 ldr q3, \[x3\]
+ 180: R_AARCH64_LDST128_ABS_LO12_NC xlit
+ 184: f98000f0 prfm pstl1keep, \[x7\]
+ 184: R_AARCH64_LDST64_ABS_LO12_NC \.data\+0x100c
+ 188: d65f03c0 ret
+
+000000000000018c <llit>:
+ 18c: deadf00d \.word 0xdeadf00d
--- /dev/null
+// Test file for AArch64 GAS -- instructions with relocation operators.
+
+func:
+ // BFD_RELOC_AARCH64_MOVW_G0
+ // immediate
+ movz x0,#:abs_g0:u12
+
+ // BFD_RELOC_AARCH64_MOVW_G0_S
+ // immediate
+ movz x0,#:abs_g0_s:s12
+
+ // BFD_RELOC_AARCH64_MOVW_G1
+ // immediate
+ movz x1,#:abs_g1:u32
+ movk x1,#:abs_g0_nc:u32
+
+ // BFD_RELOC_AARCH64_MOVW_G1_S
+ // immediate
+ movz x1,#:abs_g1_s:s12
+ movk x1,#:abs_g0_nc:s12
+
+ // BFD_RELOC_AARCH64_MOVW_G2
+ // immediate
+ movz x1,#:abs_g2:u48
+ movk x1,#:abs_g1_nc:u48
+ movk x1,#:abs_g0_nc:u48
+
+ // local data (section relative)
+ movz x1,#:abs_g2:ldata
+ movk x1,#:abs_g1_nc:ldata
+ movk x1,#:abs_g0_nc:ldata
+
+ // external data
+ movz x1,#:abs_g2:xdata
+ movk x1,#:abs_g1_nc:xdata
+ movk x1,#:abs_g0_nc:xdata
+
+ // BFD_RELOC_AARCH64_MOVW_G2_S
+ // immediate
+ movz x1,#:abs_g2_s:s12
+ movk x1,#:abs_g1_nc:s12
+ movk x1,#:abs_g0_nc:s12
+
+ // BFD_RELOC_AARCH64_MOVW_G3
+ // immediate
+ movz x1,#:abs_g3:s12
+ movk x1,#:abs_g2_nc:s12
+ movk x1,#:abs_g1_nc:s12
+ movk x1,#:abs_g0_nc:s12
+
+ movz x1,#:abs_g3:u64
+ movk x1,#:abs_g2_nc:u64
+ movk x1,#:abs_g1_nc:u64
+ movk x1,#:abs_g0_nc:u64
+
+ // BFD_RELOC_AARCH64_LD_LO19_PCREL
+ ldr x0,llit
+ ldr x1,ldata
+ ldr x2,xdata+12
+
+ // BFD_RELOC_AARCH64_ADR_LO21_PCREL
+ // AARCH64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
+ adr x0,llit
+ adr x1,ldata
+ adr x2,ldata+4088
+ adr x3,xlit
+ adr x4,xdata+16
+ adr x5,xdata+4088
+
+ // BFD_RELOC_AARCH64_ADR_HI21_PCREL
+ adrp x0,llit
+ adrp x1,ldata
+ adrp x2,ldata+4088
+ adrp x3,xlit
+ adrp x4,xdata+16
+ adrp x5,xdata+4088
+
+ // BFD_RELOC_AARCH64_ADR_HI21_PCREL
+ adrp x0,:pg_hi21:llit
+ adrp x1,:pg_hi21:ldata
+ adrp x2,:pg_hi21:ldata+4088
+ adrp x3,:pg_hi21:xlit
+ adrp x4,:pg_hi21:xdata+16
+ adrp x5,:pg_hi21:xdata+4088
+
+ // BFD_RELOC_AARCH64_ADD_LO12
+ add x0,x0,#:lo12:llit
+ add x1,x1,#:lo12:ldata
+ add x2,x2,#:lo12:ldata+4088
+ add x3,x3,#:lo12:xlit
+ add x4,x4,#:lo12:xdata+16
+ add x5,x5,#:lo12:xdata+4088
+ add x6,x6,u12
+
+ // BFD_RELOC_AARCH64_LDST8_LO12
+ ldrb w0, [x0, #:lo12:llit]
+ ldrb w1, [x1, #:lo12:ldata]
+ ldrb w2, [x2, #:lo12:ldata+4088]
+ ldrb w3, [x3, #:lo12:xlit]
+ ldrb w4, [x4, #:lo12:xdata+16]
+ ldrb w5, [x5, #:lo12:xdata+4088]
+ ldrb w6, [x6, u12]
+
+ // BFD_RELOC_AARCH64_TSTBR14
+ tbz x0,#0,lab
+ tbz x1,#63,xlab
+ tbnz x2,#8,lab
+ tbnz x2,#47,xlab
+
+ // BFD_RELOC_AARCH64_BRANCH19
+ b.eq lab
+ b.eq xlab
+
+ // BFD_RELOC_AARCH64_COMPARE19
+ cbz x0,lab
+ cbnz x30,xlab
+
+ // BFD_RELOC_AARCH64_JUMP26
+ b lab
+ b xlab
+
+ // BFD_RELOC_AARCH64_CALL26
+ bl lab
+ bl xlab
+
+ // BFD_RELOC_AARCH64_MOVW_IMM
+ movz x0, #0x1234, lsl #48
+ movk x0, #0x5678, lsl #32
+ movk x0, #0x9abc, lsl #16
+ movk x0, #0xdef0, lsl #0
+
+ movz x0, (u64>>48)&0xffff, lsl #48
+ movk x0, (u64>>32)&0xffff, lsl #32
+ movk x0, (u64>>16)&0xffff, lsl #16
+ movk x0, (u64>>0)&0xffff, lsl #0
+
+ // BFD_RELOC_AARCH64_BIT_IMM
+ orr x0,x0,bit1
+ and x0,x0,bit2
+ and w0,w0,bit2
+
+ // BFD_RELOC_AARCH64_ADD_U12
+ add x0,x0,s12
+ add x0,x0,u12
+ sub x0,x0,s12
+ sub x0,x0,u12
+
+ // BFD_RELOC_AARCH64_EXC_U16
+ svc u16
+
+ // BFD_RELOC_AARCH64_LDST_I9
+ // Signed 9-bit byte offset for load/store single item with writeback options.
+ // Used internally by the AARCH64 assembler and not (currently)
+ // written to any object files.
+ ldr x0,[x1],#s9
+ ldr x0,[x1,#s9]!
+
+ // No writeback, but a negative offset should cause this
+ // to be converted to a LDST_I9 relocation
+ ldr x0,[x1,#s9]
+
+ // BFD_RELOC_AARCH64_LDST_U12
+ // Unsigned 12-bit byte offset for load/store single item without options.
+ // Used internally by the AARCH64 assembler and not (currently)
+ // written to any object files.
+ ldr x0,[x1,#(u12*8)]
+
+ // BFD_RELOC_AARCH64_LDST16_LO12
+ ldrh w0, [x0, #:lo12:llit]
+ // BFD_RELOC_AARCH64_LDST32_LO12
+ ldr w1, [x1, #:lo12:ldata]
+ // BFD_RELOC_AARCH64_LDST64_LO12
+ ldr x2, [x2, #:lo12:ldata+4088]
+ // BFD_RELOC_AARCH64_LDST128_LO12
+ ldr q3, [x3, #:lo12:xlit]
+
+ // BFD_RELOC_AARCH64_LDST64_LO12
+ prfm pstl1keep, [x7, #:lo12:ldata+4100]
+
+ ret
+
+llit: .word 0xdeadf00d
+
+lab:
+
+ .data
+ .align 8
+
+dummy: .xword 0
+
+ldata: .xword 0x1122334455667788
+ .space 8184
+
+.set u8, 248
+.set s9, -256
+.set s12, -2048
+.set u12, 4095
+.set u16, 65535
+.set u32, 0x12345678
+.set u48, 0xaabbccddeeff
+.set u64, 0xfedcba9876543210
+.set bit1,0xf000000000000000
+.set bit2,~0xf
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: aa030041 orr x1, x2, x3
+ 4: aa030441 orr x1, x2, x3, lsl #1
+ 8: aa030c41 orr x1, x2, x3, lsl #3
+ c: aa031c41 orr x1, x2, x3, lsl #7
+ 10: aa033c41 orr x1, x2, x3, lsl #15
+ 14: aa037c41 orr x1, x2, x3, lsl #31
+ 18: aa03fc41 orr x1, x2, x3, lsl #63
+ 1c: aa430041 orr x1, x2, x3, lsr #0
+ 20: aa430441 orr x1, x2, x3, lsr #1
+ 24: aa430c41 orr x1, x2, x3, lsr #3
+ 28: aa431c41 orr x1, x2, x3, lsr #7
+ 2c: aa433c41 orr x1, x2, x3, lsr #15
+ 30: aa437c41 orr x1, x2, x3, lsr #31
+ 34: aa43fc41 orr x1, x2, x3, lsr #63
+ 38: aa830041 orr x1, x2, x3, asr #0
+ 3c: aa830441 orr x1, x2, x3, asr #1
+ 40: aa830c41 orr x1, x2, x3, asr #3
+ 44: aa831c41 orr x1, x2, x3, asr #7
+ 48: aa833c41 orr x1, x2, x3, asr #15
+ 4c: aa837c41 orr x1, x2, x3, asr #31
+ 50: aa83fc41 orr x1, x2, x3, asr #63
+ 54: aac30041 orr x1, x2, x3, ror #0
+ 58: aac30441 orr x1, x2, x3, ror #1
+ 5c: aac30c41 orr x1, x2, x3, ror #3
+ 60: aac31c41 orr x1, x2, x3, ror #7
+ 64: aac33c41 orr x1, x2, x3, ror #15
+ 68: aac37c41 orr x1, x2, x3, ror #31
+ 6c: aac3fc41 orr x1, x2, x3, ror #63
+ 70: 2a030041 orr w1, w2, w3
+ 74: 2a030441 orr w1, w2, w3, lsl #1
+ 78: 2a030c41 orr w1, w2, w3, lsl #3
+ 7c: 2a031c41 orr w1, w2, w3, lsl #7
+ 80: 2a033c41 orr w1, w2, w3, lsl #15
+ 84: 2a037c41 orr w1, w2, w3, lsl #31
+ 88: 2a430041 orr w1, w2, w3, lsr #0
+ 8c: 2a430441 orr w1, w2, w3, lsr #1
+ 90: 2a430c41 orr w1, w2, w3, lsr #3
+ 94: 2a431c41 orr w1, w2, w3, lsr #7
+ 98: 2a433c41 orr w1, w2, w3, lsr #15
+ 9c: 2a437c41 orr w1, w2, w3, lsr #31
+ a0: 2a830041 orr w1, w2, w3, asr #0
+ a4: 2a830441 orr w1, w2, w3, asr #1
+ a8: 2a830c41 orr w1, w2, w3, asr #3
+ ac: 2a831c41 orr w1, w2, w3, asr #7
+ b0: 2a833c41 orr w1, w2, w3, asr #15
+ b4: 2a837c41 orr w1, w2, w3, asr #31
+ b8: 2ac30041 orr w1, w2, w3, ror #0
+ bc: 2ac30441 orr w1, w2, w3, ror #1
+ c0: 2ac30c41 orr w1, w2, w3, ror #3
+ c4: 2ac31c41 orr w1, w2, w3, ror #7
+ c8: 2ac33c41 orr w1, w2, w3, ror #15
+ cc: 2ac37c41 orr w1, w2, w3, ror #31
+ d0: 8a030041 and x1, x2, x3
+ d4: 8a030441 and x1, x2, x3, lsl #1
+ d8: 8a030c41 and x1, x2, x3, lsl #3
+ dc: 8a031c41 and x1, x2, x3, lsl #7
+ e0: 8a033c41 and x1, x2, x3, lsl #15
+ e4: 8a037c41 and x1, x2, x3, lsl #31
+ e8: 8a03fc41 and x1, x2, x3, lsl #63
+ ec: 8a430041 and x1, x2, x3, lsr #0
+ f0: 8a430441 and x1, x2, x3, lsr #1
+ f4: 8a430c41 and x1, x2, x3, lsr #3
+ f8: 8a431c41 and x1, x2, x3, lsr #7
+ fc: 8a433c41 and x1, x2, x3, lsr #15
+ 100: 8a437c41 and x1, x2, x3, lsr #31
+ 104: 8a43fc41 and x1, x2, x3, lsr #63
+ 108: 8a830041 and x1, x2, x3, asr #0
+ 10c: 8a830441 and x1, x2, x3, asr #1
+ 110: 8a830c41 and x1, x2, x3, asr #3
+ 114: 8a831c41 and x1, x2, x3, asr #7
+ 118: 8a833c41 and x1, x2, x3, asr #15
+ 11c: 8a837c41 and x1, x2, x3, asr #31
+ 120: 8a83fc41 and x1, x2, x3, asr #63
+ 124: 8ac30041 and x1, x2, x3, ror #0
+ 128: 8ac30441 and x1, x2, x3, ror #1
+ 12c: 8ac30c41 and x1, x2, x3, ror #3
+ 130: 8ac31c41 and x1, x2, x3, ror #7
+ 134: 8ac33c41 and x1, x2, x3, ror #15
+ 138: 8ac37c41 and x1, x2, x3, ror #31
+ 13c: 8ac3fc41 and x1, x2, x3, ror #63
+ 140: 0a030041 and w1, w2, w3
+ 144: 0a030441 and w1, w2, w3, lsl #1
+ 148: 0a030c41 and w1, w2, w3, lsl #3
+ 14c: 0a031c41 and w1, w2, w3, lsl #7
+ 150: 0a033c41 and w1, w2, w3, lsl #15
+ 154: 0a037c41 and w1, w2, w3, lsl #31
+ 158: 0a430041 and w1, w2, w3, lsr #0
+ 15c: 0a430441 and w1, w2, w3, lsr #1
+ 160: 0a430c41 and w1, w2, w3, lsr #3
+ 164: 0a431c41 and w1, w2, w3, lsr #7
+ 168: 0a433c41 and w1, w2, w3, lsr #15
+ 16c: 0a437c41 and w1, w2, w3, lsr #31
+ 170: 0a830041 and w1, w2, w3, asr #0
+ 174: 0a830441 and w1, w2, w3, asr #1
+ 178: 0a830c41 and w1, w2, w3, asr #3
+ 17c: 0a831c41 and w1, w2, w3, asr #7
+ 180: 0a833c41 and w1, w2, w3, asr #15
+ 184: 0a837c41 and w1, w2, w3, asr #31
+ 188: 0ac30041 and w1, w2, w3, ror #0
+ 18c: 0ac30441 and w1, w2, w3, ror #1
+ 190: 0ac30c41 and w1, w2, w3, ror #3
+ 194: 0ac31c41 and w1, w2, w3, ror #7
+ 198: 0ac33c41 and w1, w2, w3, ror #15
+ 19c: 0ac37c41 and w1, w2, w3, ror #31
+ 1a0: ca030041 eor x1, x2, x3
+ 1a4: ca030441 eor x1, x2, x3, lsl #1
+ 1a8: ca030c41 eor x1, x2, x3, lsl #3
+ 1ac: ca031c41 eor x1, x2, x3, lsl #7
+ 1b0: ca033c41 eor x1, x2, x3, lsl #15
+ 1b4: ca037c41 eor x1, x2, x3, lsl #31
+ 1b8: ca03fc41 eor x1, x2, x3, lsl #63
+ 1bc: ca430041 eor x1, x2, x3, lsr #0
+ 1c0: ca430441 eor x1, x2, x3, lsr #1
+ 1c4: ca430c41 eor x1, x2, x3, lsr #3
+ 1c8: ca431c41 eor x1, x2, x3, lsr #7
+ 1cc: ca433c41 eor x1, x2, x3, lsr #15
+ 1d0: ca437c41 eor x1, x2, x3, lsr #31
+ 1d4: ca43fc41 eor x1, x2, x3, lsr #63
+ 1d8: ca830041 eor x1, x2, x3, asr #0
+ 1dc: ca830441 eor x1, x2, x3, asr #1
+ 1e0: ca830c41 eor x1, x2, x3, asr #3
+ 1e4: ca831c41 eor x1, x2, x3, asr #7
+ 1e8: ca833c41 eor x1, x2, x3, asr #15
+ 1ec: ca837c41 eor x1, x2, x3, asr #31
+ 1f0: ca83fc41 eor x1, x2, x3, asr #63
+ 1f4: cac30041 eor x1, x2, x3, ror #0
+ 1f8: cac30441 eor x1, x2, x3, ror #1
+ 1fc: cac30c41 eor x1, x2, x3, ror #3
+ 200: cac31c41 eor x1, x2, x3, ror #7
+ 204: cac33c41 eor x1, x2, x3, ror #15
+ 208: cac37c41 eor x1, x2, x3, ror #31
+ 20c: cac3fc41 eor x1, x2, x3, ror #63
+ 210: 4a030041 eor w1, w2, w3
+ 214: 4a030441 eor w1, w2, w3, lsl #1
+ 218: 4a030c41 eor w1, w2, w3, lsl #3
+ 21c: 4a031c41 eor w1, w2, w3, lsl #7
+ 220: 4a033c41 eor w1, w2, w3, lsl #15
+ 224: 4a037c41 eor w1, w2, w3, lsl #31
+ 228: 4a430041 eor w1, w2, w3, lsr #0
+ 22c: 4a430441 eor w1, w2, w3, lsr #1
+ 230: 4a430c41 eor w1, w2, w3, lsr #3
+ 234: 4a431c41 eor w1, w2, w3, lsr #7
+ 238: 4a433c41 eor w1, w2, w3, lsr #15
+ 23c: 4a437c41 eor w1, w2, w3, lsr #31
+ 240: 4a830041 eor w1, w2, w3, asr #0
+ 244: 4a830441 eor w1, w2, w3, asr #1
+ 248: 4a830c41 eor w1, w2, w3, asr #3
+ 24c: 4a831c41 eor w1, w2, w3, asr #7
+ 250: 4a833c41 eor w1, w2, w3, asr #15
+ 254: 4a837c41 eor w1, w2, w3, asr #31
+ 258: 4ac30041 eor w1, w2, w3, ror #0
+ 25c: 4ac30441 eor w1, w2, w3, ror #1
+ 260: 4ac30c41 eor w1, w2, w3, ror #3
+ 264: 4ac31c41 eor w1, w2, w3, ror #7
+ 268: 4ac33c41 eor w1, w2, w3, ror #15
+ 26c: 4ac37c41 eor w1, w2, w3, ror #31
+ 270: 8a230041 bic x1, x2, x3
+ 274: 8a230441 bic x1, x2, x3, lsl #1
+ 278: 8a230c41 bic x1, x2, x3, lsl #3
+ 27c: 8a231c41 bic x1, x2, x3, lsl #7
+ 280: 8a233c41 bic x1, x2, x3, lsl #15
+ 284: 8a237c41 bic x1, x2, x3, lsl #31
+ 288: 8a23fc41 bic x1, x2, x3, lsl #63
+ 28c: 8a630041 bic x1, x2, x3, lsr #0
+ 290: 8a630441 bic x1, x2, x3, lsr #1
+ 294: 8a630c41 bic x1, x2, x3, lsr #3
+ 298: 8a631c41 bic x1, x2, x3, lsr #7
+ 29c: 8a633c41 bic x1, x2, x3, lsr #15
+ 2a0: 8a637c41 bic x1, x2, x3, lsr #31
+ 2a4: 8a63fc41 bic x1, x2, x3, lsr #63
+ 2a8: 8aa30041 bic x1, x2, x3, asr #0
+ 2ac: 8aa30441 bic x1, x2, x3, asr #1
+ 2b0: 8aa30c41 bic x1, x2, x3, asr #3
+ 2b4: 8aa31c41 bic x1, x2, x3, asr #7
+ 2b8: 8aa33c41 bic x1, x2, x3, asr #15
+ 2bc: 8aa37c41 bic x1, x2, x3, asr #31
+ 2c0: 8aa3fc41 bic x1, x2, x3, asr #63
+ 2c4: 8ae30041 bic x1, x2, x3, ror #0
+ 2c8: 8ae30441 bic x1, x2, x3, ror #1
+ 2cc: 8ae30c41 bic x1, x2, x3, ror #3
+ 2d0: 8ae31c41 bic x1, x2, x3, ror #7
+ 2d4: 8ae33c41 bic x1, x2, x3, ror #15
+ 2d8: 8ae37c41 bic x1, x2, x3, ror #31
+ 2dc: 8ae3fc41 bic x1, x2, x3, ror #63
+ 2e0: 0a230041 bic w1, w2, w3
+ 2e4: 0a230441 bic w1, w2, w3, lsl #1
+ 2e8: 0a230c41 bic w1, w2, w3, lsl #3
+ 2ec: 0a231c41 bic w1, w2, w3, lsl #7
+ 2f0: 0a233c41 bic w1, w2, w3, lsl #15
+ 2f4: 0a237c41 bic w1, w2, w3, lsl #31
+ 2f8: 0a630041 bic w1, w2, w3, lsr #0
+ 2fc: 0a630441 bic w1, w2, w3, lsr #1
+ 300: 0a630c41 bic w1, w2, w3, lsr #3
+ 304: 0a631c41 bic w1, w2, w3, lsr #7
+ 308: 0a633c41 bic w1, w2, w3, lsr #15
+ 30c: 0a637c41 bic w1, w2, w3, lsr #31
+ 310: 0aa30041 bic w1, w2, w3, asr #0
+ 314: 0aa30441 bic w1, w2, w3, asr #1
+ 318: 0aa30c41 bic w1, w2, w3, asr #3
+ 31c: 0aa31c41 bic w1, w2, w3, asr #7
+ 320: 0aa33c41 bic w1, w2, w3, asr #15
+ 324: 0aa37c41 bic w1, w2, w3, asr #31
+ 328: 0ae30041 bic w1, w2, w3, ror #0
+ 32c: 0ae30441 bic w1, w2, w3, ror #1
+ 330: 0ae30c41 bic w1, w2, w3, ror #3
+ 334: 0ae31c41 bic w1, w2, w3, ror #7
+ 338: 0ae33c41 bic w1, w2, w3, ror #15
+ 33c: 0ae37c41 bic w1, w2, w3, ror #31
+ 340: aa230041 orn x1, x2, x3
+ 344: aa230441 orn x1, x2, x3, lsl #1
+ 348: aa230c41 orn x1, x2, x3, lsl #3
+ 34c: aa231c41 orn x1, x2, x3, lsl #7
+ 350: aa233c41 orn x1, x2, x3, lsl #15
+ 354: aa237c41 orn x1, x2, x3, lsl #31
+ 358: aa23fc41 orn x1, x2, x3, lsl #63
+ 35c: aa630041 orn x1, x2, x3, lsr #0
+ 360: aa630441 orn x1, x2, x3, lsr #1
+ 364: aa630c41 orn x1, x2, x3, lsr #3
+ 368: aa631c41 orn x1, x2, x3, lsr #7
+ 36c: aa633c41 orn x1, x2, x3, lsr #15
+ 370: aa637c41 orn x1, x2, x3, lsr #31
+ 374: aa63fc41 orn x1, x2, x3, lsr #63
+ 378: aaa30041 orn x1, x2, x3, asr #0
+ 37c: aaa30441 orn x1, x2, x3, asr #1
+ 380: aaa30c41 orn x1, x2, x3, asr #3
+ 384: aaa31c41 orn x1, x2, x3, asr #7
+ 388: aaa33c41 orn x1, x2, x3, asr #15
+ 38c: aaa37c41 orn x1, x2, x3, asr #31
+ 390: aaa3fc41 orn x1, x2, x3, asr #63
+ 394: aae30041 orn x1, x2, x3, ror #0
+ 398: aae30441 orn x1, x2, x3, ror #1
+ 39c: aae30c41 orn x1, x2, x3, ror #3
+ 3a0: aae31c41 orn x1, x2, x3, ror #7
+ 3a4: aae33c41 orn x1, x2, x3, ror #15
+ 3a8: aae37c41 orn x1, x2, x3, ror #31
+ 3ac: aae3fc41 orn x1, x2, x3, ror #63
+ 3b0: 2a230041 orn w1, w2, w3
+ 3b4: 2a230441 orn w1, w2, w3, lsl #1
+ 3b8: 2a230c41 orn w1, w2, w3, lsl #3
+ 3bc: 2a231c41 orn w1, w2, w3, lsl #7
+ 3c0: 2a233c41 orn w1, w2, w3, lsl #15
+ 3c4: 2a237c41 orn w1, w2, w3, lsl #31
+ 3c8: 2a630041 orn w1, w2, w3, lsr #0
+ 3cc: 2a630441 orn w1, w2, w3, lsr #1
+ 3d0: 2a630c41 orn w1, w2, w3, lsr #3
+ 3d4: 2a631c41 orn w1, w2, w3, lsr #7
+ 3d8: 2a633c41 orn w1, w2, w3, lsr #15
+ 3dc: 2a637c41 orn w1, w2, w3, lsr #31
+ 3e0: 2aa30041 orn w1, w2, w3, asr #0
+ 3e4: 2aa30441 orn w1, w2, w3, asr #1
+ 3e8: 2aa30c41 orn w1, w2, w3, asr #3
+ 3ec: 2aa31c41 orn w1, w2, w3, asr #7
+ 3f0: 2aa33c41 orn w1, w2, w3, asr #15
+ 3f4: 2aa37c41 orn w1, w2, w3, asr #31
+ 3f8: 2ae30041 orn w1, w2, w3, ror #0
+ 3fc: 2ae30441 orn w1, w2, w3, ror #1
+ 400: 2ae30c41 orn w1, w2, w3, ror #3
+ 404: 2ae31c41 orn w1, w2, w3, ror #7
+ 408: 2ae33c41 orn w1, w2, w3, ror #15
+ 40c: 2ae37c41 orn w1, w2, w3, ror #31
+ 410: ca230041 eon x1, x2, x3
+ 414: ca230441 eon x1, x2, x3, lsl #1
+ 418: ca230c41 eon x1, x2, x3, lsl #3
+ 41c: ca231c41 eon x1, x2, x3, lsl #7
+ 420: ca233c41 eon x1, x2, x3, lsl #15
+ 424: ca237c41 eon x1, x2, x3, lsl #31
+ 428: ca23fc41 eon x1, x2, x3, lsl #63
+ 42c: ca630041 eon x1, x2, x3, lsr #0
+ 430: ca630441 eon x1, x2, x3, lsr #1
+ 434: ca630c41 eon x1, x2, x3, lsr #3
+ 438: ca631c41 eon x1, x2, x3, lsr #7
+ 43c: ca633c41 eon x1, x2, x3, lsr #15
+ 440: ca637c41 eon x1, x2, x3, lsr #31
+ 444: ca63fc41 eon x1, x2, x3, lsr #63
+ 448: caa30041 eon x1, x2, x3, asr #0
+ 44c: caa30441 eon x1, x2, x3, asr #1
+ 450: caa30c41 eon x1, x2, x3, asr #3
+ 454: caa31c41 eon x1, x2, x3, asr #7
+ 458: caa33c41 eon x1, x2, x3, asr #15
+ 45c: caa37c41 eon x1, x2, x3, asr #31
+ 460: caa3fc41 eon x1, x2, x3, asr #63
+ 464: cae30041 eon x1, x2, x3, ror #0
+ 468: cae30441 eon x1, x2, x3, ror #1
+ 46c: cae30c41 eon x1, x2, x3, ror #3
+ 470: cae31c41 eon x1, x2, x3, ror #7
+ 474: cae33c41 eon x1, x2, x3, ror #15
+ 478: cae37c41 eon x1, x2, x3, ror #31
+ 47c: cae3fc41 eon x1, x2, x3, ror #63
+ 480: 4a230041 eon w1, w2, w3
+ 484: 4a230441 eon w1, w2, w3, lsl #1
+ 488: 4a230c41 eon w1, w2, w3, lsl #3
+ 48c: 4a231c41 eon w1, w2, w3, lsl #7
+ 490: 4a233c41 eon w1, w2, w3, lsl #15
+ 494: 4a237c41 eon w1, w2, w3, lsl #31
+ 498: 4a630041 eon w1, w2, w3, lsr #0
+ 49c: 4a630441 eon w1, w2, w3, lsr #1
+ 4a0: 4a630c41 eon w1, w2, w3, lsr #3
+ 4a4: 4a631c41 eon w1, w2, w3, lsr #7
+ 4a8: 4a633c41 eon w1, w2, w3, lsr #15
+ 4ac: 4a637c41 eon w1, w2, w3, lsr #31
+ 4b0: 4aa30041 eon w1, w2, w3, asr #0
+ 4b4: 4aa30441 eon w1, w2, w3, asr #1
+ 4b8: 4aa30c41 eon w1, w2, w3, asr #3
+ 4bc: 4aa31c41 eon w1, w2, w3, asr #7
+ 4c0: 4aa33c41 eon w1, w2, w3, asr #15
+ 4c4: 4aa37c41 eon w1, w2, w3, asr #31
+ 4c8: 4ae30041 eon w1, w2, w3, ror #0
+ 4cc: 4ae30441 eon w1, w2, w3, ror #1
+ 4d0: 4ae30c41 eon w1, w2, w3, ror #3
+ 4d4: 4ae31c41 eon w1, w2, w3, ror #7
+ 4d8: 4ae33c41 eon w1, w2, w3, ror #15
+ 4dc: 4ae37c41 eon w1, w2, w3, ror #31
+ 4e0: 8b030041 add x1, x2, x3
+ 4e4: 8b030441 add x1, x2, x3, lsl #1
+ 4e8: 8b030c41 add x1, x2, x3, lsl #3
+ 4ec: 8b031c41 add x1, x2, x3, lsl #7
+ 4f0: 8b033c41 add x1, x2, x3, lsl #15
+ 4f4: 8b037c41 add x1, x2, x3, lsl #31
+ 4f8: 8b03fc41 add x1, x2, x3, lsl #63
+ 4fc: 8b430041 add x1, x2, x3, lsr #0
+ 500: 8b430441 add x1, x2, x3, lsr #1
+ 504: 8b430c41 add x1, x2, x3, lsr #3
+ 508: 8b431c41 add x1, x2, x3, lsr #7
+ 50c: 8b433c41 add x1, x2, x3, lsr #15
+ 510: 8b437c41 add x1, x2, x3, lsr #31
+ 514: 8b43fc41 add x1, x2, x3, lsr #63
+ 518: 8b830041 add x1, x2, x3, asr #0
+ 51c: 8b830441 add x1, x2, x3, asr #1
+ 520: 8b830c41 add x1, x2, x3, asr #3
+ 524: 8b831c41 add x1, x2, x3, asr #7
+ 528: 8b833c41 add x1, x2, x3, asr #15
+ 52c: 8b837c41 add x1, x2, x3, asr #31
+ 530: 8b83fc41 add x1, x2, x3, asr #63
+ 534: 8b230041 add x1, x2, w3, uxtb
+ 538: 8b230441 add x1, x2, w3, uxtb #1
+ 53c: 8b230841 add x1, x2, w3, uxtb #2
+ 540: 8b230c41 add x1, x2, w3, uxtb #3
+ 544: 8b231041 add x1, x2, w3, uxtb #4
+ 548: 8b232041 add x1, x2, w3, uxth
+ 54c: 8b232441 add x1, x2, w3, uxth #1
+ 550: 8b232841 add x1, x2, w3, uxth #2
+ 554: 8b232c41 add x1, x2, w3, uxth #3
+ 558: 8b233041 add x1, x2, w3, uxth #4
+ 55c: 8b234041 add x1, x2, w3, uxtw
+ 560: 8b234441 add x1, x2, w3, uxtw #1
+ 564: 8b234841 add x1, x2, w3, uxtw #2
+ 568: 8b234c41 add x1, x2, w3, uxtw #3
+ 56c: 8b235041 add x1, x2, w3, uxtw #4
+ 570: 8b236041 add x1, x2, x3, uxtx
+ 574: 8b236441 add x1, x2, x3, uxtx #1
+ 578: 8b236841 add x1, x2, x3, uxtx #2
+ 57c: 8b236c41 add x1, x2, x3, uxtx #3
+ 580: 8b237041 add x1, x2, x3, uxtx #4
+ 584: 8b238041 add x1, x2, w3, sxtb
+ 588: 8b238441 add x1, x2, w3, sxtb #1
+ 58c: 8b238841 add x1, x2, w3, sxtb #2
+ 590: 8b238c41 add x1, x2, w3, sxtb #3
+ 594: 8b239041 add x1, x2, w3, sxtb #4
+ 598: 8b23a041 add x1, x2, w3, sxth
+ 59c: 8b23a441 add x1, x2, w3, sxth #1
+ 5a0: 8b23a841 add x1, x2, w3, sxth #2
+ 5a4: 8b23ac41 add x1, x2, w3, sxth #3
+ 5a8: 8b23b041 add x1, x2, w3, sxth #4
+ 5ac: 8b23c041 add x1, x2, w3, sxtw
+ 5b0: 8b23c441 add x1, x2, w3, sxtw #1
+ 5b4: 8b23c841 add x1, x2, w3, sxtw #2
+ 5b8: 8b23cc41 add x1, x2, w3, sxtw #3
+ 5bc: 8b23d041 add x1, x2, w3, sxtw #4
+ 5c0: 8b23e041 add x1, x2, x3, sxtx
+ 5c4: 8b23e441 add x1, x2, x3, sxtx #1
+ 5c8: 8b23e841 add x1, x2, x3, sxtx #2
+ 5cc: 8b23ec41 add x1, x2, x3, sxtx #3
+ 5d0: 8b23f041 add x1, x2, x3, sxtx #4
+ 5d4: 0b030041 add w1, w2, w3
+ 5d8: 0b030441 add w1, w2, w3, lsl #1
+ 5dc: 0b030c41 add w1, w2, w3, lsl #3
+ 5e0: 0b031c41 add w1, w2, w3, lsl #7
+ 5e4: 0b033c41 add w1, w2, w3, lsl #15
+ 5e8: 0b037c41 add w1, w2, w3, lsl #31
+ 5ec: 0b430041 add w1, w2, w3, lsr #0
+ 5f0: 0b430441 add w1, w2, w3, lsr #1
+ 5f4: 0b430c41 add w1, w2, w3, lsr #3
+ 5f8: 0b431c41 add w1, w2, w3, lsr #7
+ 5fc: 0b433c41 add w1, w2, w3, lsr #15
+ 600: 0b437c41 add w1, w2, w3, lsr #31
+ 604: 0b830041 add w1, w2, w3, asr #0
+ 608: 0b830441 add w1, w2, w3, asr #1
+ 60c: 0b830c41 add w1, w2, w3, asr #3
+ 610: 0b831c41 add w1, w2, w3, asr #7
+ 614: 0b833c41 add w1, w2, w3, asr #15
+ 618: 0b837c41 add w1, w2, w3, asr #31
+ 61c: 0b230041 add w1, w2, w3, uxtb
+ 620: 0b230441 add w1, w2, w3, uxtb #1
+ 624: 0b230841 add w1, w2, w3, uxtb #2
+ 628: 0b230c41 add w1, w2, w3, uxtb #3
+ 62c: 0b231041 add w1, w2, w3, uxtb #4
+ 630: 0b232041 add w1, w2, w3, uxth
+ 634: 0b232441 add w1, w2, w3, uxth #1
+ 638: 0b232841 add w1, w2, w3, uxth #2
+ 63c: 0b232c41 add w1, w2, w3, uxth #3
+ 640: 0b233041 add w1, w2, w3, uxth #4
+ 644: 0b238041 add w1, w2, w3, sxtb
+ 648: 0b238441 add w1, w2, w3, sxtb #1
+ 64c: 0b238841 add w1, w2, w3, sxtb #2
+ 650: 0b238c41 add w1, w2, w3, sxtb #3
+ 654: 0b239041 add w1, w2, w3, sxtb #4
+ 658: 0b23a041 add w1, w2, w3, sxth
+ 65c: 0b23a441 add w1, w2, w3, sxth #1
+ 660: 0b23a841 add w1, w2, w3, sxth #2
+ 664: 0b23ac41 add w1, w2, w3, sxth #3
+ 668: 0b23b041 add w1, w2, w3, sxth #4
+ 66c: cb030041 sub x1, x2, x3
+ 670: cb030441 sub x1, x2, x3, lsl #1
+ 674: cb030c41 sub x1, x2, x3, lsl #3
+ 678: cb031c41 sub x1, x2, x3, lsl #7
+ 67c: cb033c41 sub x1, x2, x3, lsl #15
+ 680: cb037c41 sub x1, x2, x3, lsl #31
+ 684: cb03fc41 sub x1, x2, x3, lsl #63
+ 688: cb430041 sub x1, x2, x3, lsr #0
+ 68c: cb430441 sub x1, x2, x3, lsr #1
+ 690: cb430c41 sub x1, x2, x3, lsr #3
+ 694: cb431c41 sub x1, x2, x3, lsr #7
+ 698: cb433c41 sub x1, x2, x3, lsr #15
+ 69c: cb437c41 sub x1, x2, x3, lsr #31
+ 6a0: cb43fc41 sub x1, x2, x3, lsr #63
+ 6a4: cb830041 sub x1, x2, x3, asr #0
+ 6a8: cb830441 sub x1, x2, x3, asr #1
+ 6ac: cb830c41 sub x1, x2, x3, asr #3
+ 6b0: cb831c41 sub x1, x2, x3, asr #7
+ 6b4: cb833c41 sub x1, x2, x3, asr #15
+ 6b8: cb837c41 sub x1, x2, x3, asr #31
+ 6bc: cb83fc41 sub x1, x2, x3, asr #63
+ 6c0: cb230041 sub x1, x2, w3, uxtb
+ 6c4: cb230441 sub x1, x2, w3, uxtb #1
+ 6c8: cb230841 sub x1, x2, w3, uxtb #2
+ 6cc: cb230c41 sub x1, x2, w3, uxtb #3
+ 6d0: cb231041 sub x1, x2, w3, uxtb #4
+ 6d4: cb232041 sub x1, x2, w3, uxth
+ 6d8: cb232441 sub x1, x2, w3, uxth #1
+ 6dc: cb232841 sub x1, x2, w3, uxth #2
+ 6e0: cb232c41 sub x1, x2, w3, uxth #3
+ 6e4: cb233041 sub x1, x2, w3, uxth #4
+ 6e8: cb234041 sub x1, x2, w3, uxtw
+ 6ec: cb234441 sub x1, x2, w3, uxtw #1
+ 6f0: cb234841 sub x1, x2, w3, uxtw #2
+ 6f4: cb234c41 sub x1, x2, w3, uxtw #3
+ 6f8: cb235041 sub x1, x2, w3, uxtw #4
+ 6fc: cb236041 sub x1, x2, x3, uxtx
+ 700: cb236441 sub x1, x2, x3, uxtx #1
+ 704: cb236841 sub x1, x2, x3, uxtx #2
+ 708: cb236c41 sub x1, x2, x3, uxtx #3
+ 70c: cb237041 sub x1, x2, x3, uxtx #4
+ 710: cb238041 sub x1, x2, w3, sxtb
+ 714: cb238441 sub x1, x2, w3, sxtb #1
+ 718: cb238841 sub x1, x2, w3, sxtb #2
+ 71c: cb238c41 sub x1, x2, w3, sxtb #3
+ 720: cb239041 sub x1, x2, w3, sxtb #4
+ 724: cb23a041 sub x1, x2, w3, sxth
+ 728: cb23a441 sub x1, x2, w3, sxth #1
+ 72c: cb23a841 sub x1, x2, w3, sxth #2
+ 730: cb23ac41 sub x1, x2, w3, sxth #3
+ 734: cb23b041 sub x1, x2, w3, sxth #4
+ 738: cb23c041 sub x1, x2, w3, sxtw
+ 73c: cb23c441 sub x1, x2, w3, sxtw #1
+ 740: cb23c841 sub x1, x2, w3, sxtw #2
+ 744: cb23cc41 sub x1, x2, w3, sxtw #3
+ 748: cb23d041 sub x1, x2, w3, sxtw #4
+ 74c: cb23e041 sub x1, x2, x3, sxtx
+ 750: cb23e441 sub x1, x2, x3, sxtx #1
+ 754: cb23e841 sub x1, x2, x3, sxtx #2
+ 758: cb23ec41 sub x1, x2, x3, sxtx #3
+ 75c: cb23f041 sub x1, x2, x3, sxtx #4
+ 760: 4b030041 sub w1, w2, w3
+ 764: 4b030441 sub w1, w2, w3, lsl #1
+ 768: 4b030c41 sub w1, w2, w3, lsl #3
+ 76c: 4b031c41 sub w1, w2, w3, lsl #7
+ 770: 4b033c41 sub w1, w2, w3, lsl #15
+ 774: 4b037c41 sub w1, w2, w3, lsl #31
+ 778: 4b430041 sub w1, w2, w3, lsr #0
+ 77c: 4b430441 sub w1, w2, w3, lsr #1
+ 780: 4b430c41 sub w1, w2, w3, lsr #3
+ 784: 4b431c41 sub w1, w2, w3, lsr #7
+ 788: 4b433c41 sub w1, w2, w3, lsr #15
+ 78c: 4b437c41 sub w1, w2, w3, lsr #31
+ 790: 4b830041 sub w1, w2, w3, asr #0
+ 794: 4b830441 sub w1, w2, w3, asr #1
+ 798: 4b830c41 sub w1, w2, w3, asr #3
+ 79c: 4b831c41 sub w1, w2, w3, asr #7
+ 7a0: 4b833c41 sub w1, w2, w3, asr #15
+ 7a4: 4b837c41 sub w1, w2, w3, asr #31
+ 7a8: 4b230041 sub w1, w2, w3, uxtb
+ 7ac: 4b230441 sub w1, w2, w3, uxtb #1
+ 7b0: 4b230841 sub w1, w2, w3, uxtb #2
+ 7b4: 4b230c41 sub w1, w2, w3, uxtb #3
+ 7b8: 4b231041 sub w1, w2, w3, uxtb #4
+ 7bc: 4b232041 sub w1, w2, w3, uxth
+ 7c0: 4b232441 sub w1, w2, w3, uxth #1
+ 7c4: 4b232841 sub w1, w2, w3, uxth #2
+ 7c8: 4b232c41 sub w1, w2, w3, uxth #3
+ 7cc: 4b233041 sub w1, w2, w3, uxth #4
+ 7d0: 4b238041 sub w1, w2, w3, sxtb
+ 7d4: 4b238441 sub w1, w2, w3, sxtb #1
+ 7d8: 4b238841 sub w1, w2, w3, sxtb #2
+ 7dc: 4b238c41 sub w1, w2, w3, sxtb #3
+ 7e0: 4b239041 sub w1, w2, w3, sxtb #4
+ 7e4: 4b23a041 sub w1, w2, w3, sxth
+ 7e8: 4b23a441 sub w1, w2, w3, sxth #1
+ 7ec: 4b23a841 sub w1, w2, w3, sxth #2
+ 7f0: 4b23ac41 sub w1, w2, w3, sxth #3
+ 7f4: 4b23b041 sub w1, w2, w3, sxth #4
+ 7f8: cb0303e2 neg x2, x3
+ 7fc: cb0307e2 neg x2, x3, lsl #1
+ 800: cb030fe2 neg x2, x3, lsl #3
+ 804: cb031fe2 neg x2, x3, lsl #7
+ 808: cb033fe2 neg x2, x3, lsl #15
+ 80c: cb037fe2 neg x2, x3, lsl #31
+ 810: cb03ffe2 neg x2, x3, lsl #63
+ 814: cb4303e2 neg x2, x3, lsr #0
+ 818: cb4307e2 neg x2, x3, lsr #1
+ 81c: cb430fe2 neg x2, x3, lsr #3
+ 820: cb431fe2 neg x2, x3, lsr #7
+ 824: cb433fe2 neg x2, x3, lsr #15
+ 828: cb437fe2 neg x2, x3, lsr #31
+ 82c: cb43ffe2 neg x2, x3, lsr #63
+ 830: cb8303e2 neg x2, x3, asr #0
+ 834: cb8307e2 neg x2, x3, asr #1
+ 838: cb830fe2 neg x2, x3, asr #3
+ 83c: cb831fe2 neg x2, x3, asr #7
+ 840: cb833fe2 neg x2, x3, asr #15
+ 844: cb837fe2 neg x2, x3, asr #31
+ 848: cb83ffe2 neg x2, x3, asr #63
+ 84c: 4b0303e2 neg w2, w3
+ 850: 4b0307e2 neg w2, w3, lsl #1
+ 854: 4b030fe2 neg w2, w3, lsl #3
+ 858: 4b031fe2 neg w2, w3, lsl #7
+ 85c: 4b033fe2 neg w2, w3, lsl #15
+ 860: 4b037fe2 neg w2, w3, lsl #31
+ 864: 4b4303e2 neg w2, w3, lsr #0
+ 868: 4b4307e2 neg w2, w3, lsr #1
+ 86c: 4b430fe2 neg w2, w3, lsr #3
+ 870: 4b431fe2 neg w2, w3, lsr #7
+ 874: 4b433fe2 neg w2, w3, lsr #15
+ 878: 4b437fe2 neg w2, w3, lsr #31
+ 87c: 4b8303e2 neg w2, w3, asr #0
+ 880: 4b8307e2 neg w2, w3, asr #1
+ 884: 4b830fe2 neg w2, w3, asr #3
+ 888: 4b831fe2 neg w2, w3, asr #7
+ 88c: 4b833fe2 neg w2, w3, asr #15
+ 890: 4b837fe2 neg w2, w3, asr #31
+ 894: eb03005f cmp x2, x3
+ 898: eb03045f cmp x2, x3, lsl #1
+ 89c: eb030c5f cmp x2, x3, lsl #3
+ 8a0: eb031c5f cmp x2, x3, lsl #7
+ 8a4: eb033c5f cmp x2, x3, lsl #15
+ 8a8: eb037c5f cmp x2, x3, lsl #31
+ 8ac: eb03fc5f cmp x2, x3, lsl #63
+ 8b0: eb43005f cmp x2, x3, lsr #0
+ 8b4: eb43045f cmp x2, x3, lsr #1
+ 8b8: eb430c5f cmp x2, x3, lsr #3
+ 8bc: eb431c5f cmp x2, x3, lsr #7
+ 8c0: eb433c5f cmp x2, x3, lsr #15
+ 8c4: eb437c5f cmp x2, x3, lsr #31
+ 8c8: eb43fc5f cmp x2, x3, lsr #63
+ 8cc: eb83005f cmp x2, x3, asr #0
+ 8d0: eb83045f cmp x2, x3, asr #1
+ 8d4: eb830c5f cmp x2, x3, asr #3
+ 8d8: eb831c5f cmp x2, x3, asr #7
+ 8dc: eb833c5f cmp x2, x3, asr #15
+ 8e0: eb837c5f cmp x2, x3, asr #31
+ 8e4: eb83fc5f cmp x2, x3, asr #63
+ 8e8: eb23005f cmp x2, w3, uxtb
+ 8ec: eb23045f cmp x2, w3, uxtb #1
+ 8f0: eb23085f cmp x2, w3, uxtb #2
+ 8f4: eb230c5f cmp x2, w3, uxtb #3
+ 8f8: eb23105f cmp x2, w3, uxtb #4
+ 8fc: eb23205f cmp x2, w3, uxth
+ 900: eb23245f cmp x2, w3, uxth #1
+ 904: eb23285f cmp x2, w3, uxth #2
+ 908: eb232c5f cmp x2, w3, uxth #3
+ 90c: eb23305f cmp x2, w3, uxth #4
+ 910: eb23405f cmp x2, w3, uxtw
+ 914: eb23445f cmp x2, w3, uxtw #1
+ 918: eb23485f cmp x2, w3, uxtw #2
+ 91c: eb234c5f cmp x2, w3, uxtw #3
+ 920: eb23505f cmp x2, w3, uxtw #4
+ 924: eb23805f cmp x2, w3, sxtb
+ 928: eb23845f cmp x2, w3, sxtb #1
+ 92c: eb23885f cmp x2, w3, sxtb #2
+ 930: eb238c5f cmp x2, w3, sxtb #3
+ 934: eb23905f cmp x2, w3, sxtb #4
+ 938: eb23a05f cmp x2, w3, sxth
+ 93c: eb23a45f cmp x2, w3, sxth #1
+ 940: eb23a85f cmp x2, w3, sxth #2
+ 944: eb23ac5f cmp x2, w3, sxth #3
+ 948: eb23b05f cmp x2, w3, sxth #4
+ 94c: eb23c05f cmp x2, w3, sxtw
+ 950: eb23c45f cmp x2, w3, sxtw #1
+ 954: eb23c85f cmp x2, w3, sxtw #2
+ 958: eb23cc5f cmp x2, w3, sxtw #3
+ 95c: eb23d05f cmp x2, w3, sxtw #4
+ 960: 6b03005f cmp w2, w3
+ 964: 6b03045f cmp w2, w3, lsl #1
+ 968: 6b030c5f cmp w2, w3, lsl #3
+ 96c: 6b031c5f cmp w2, w3, lsl #7
+ 970: 6b033c5f cmp w2, w3, lsl #15
+ 974: 6b037c5f cmp w2, w3, lsl #31
+ 978: 6b43005f cmp w2, w3, lsr #0
+ 97c: 6b43045f cmp w2, w3, lsr #1
+ 980: 6b430c5f cmp w2, w3, lsr #3
+ 984: 6b431c5f cmp w2, w3, lsr #7
+ 988: 6b433c5f cmp w2, w3, lsr #15
+ 98c: 6b437c5f cmp w2, w3, lsr #31
+ 990: 6b83005f cmp w2, w3, asr #0
+ 994: 6b83045f cmp w2, w3, asr #1
+ 998: 6b830c5f cmp w2, w3, asr #3
+ 99c: 6b831c5f cmp w2, w3, asr #7
+ 9a0: 6b833c5f cmp w2, w3, asr #15
+ 9a4: 6b837c5f cmp w2, w3, asr #31
+ 9a8: 6b23005f cmp w2, w3, uxtb
+ 9ac: 6b23045f cmp w2, w3, uxtb #1
+ 9b0: 6b23085f cmp w2, w3, uxtb #2
+ 9b4: 6b230c5f cmp w2, w3, uxtb #3
+ 9b8: 6b23105f cmp w2, w3, uxtb #4
+ 9bc: 6b23205f cmp w2, w3, uxth
+ 9c0: 6b23245f cmp w2, w3, uxth #1
+ 9c4: 6b23285f cmp w2, w3, uxth #2
+ 9c8: 6b232c5f cmp w2, w3, uxth #3
+ 9cc: 6b23305f cmp w2, w3, uxth #4
+ 9d0: 6b23805f cmp w2, w3, sxtb
+ 9d4: 6b23845f cmp w2, w3, sxtb #1
+ 9d8: 6b23885f cmp w2, w3, sxtb #2
+ 9dc: 6b238c5f cmp w2, w3, sxtb #3
+ 9e0: 6b23905f cmp w2, w3, sxtb #4
+ 9e4: 6b23a05f cmp w2, w3, sxth
+ 9e8: 6b23a45f cmp w2, w3, sxth #1
+ 9ec: 6b23a85f cmp w2, w3, sxth #2
+ 9f0: 6b23ac5f cmp w2, w3, sxth #3
+ 9f4: 6b23b05f cmp w2, w3, sxth #4
+ 9f8: ab03005f cmn x2, x3
+ 9fc: ab03045f cmn x2, x3, lsl #1
+ a00: ab030c5f cmn x2, x3, lsl #3
+ a04: ab031c5f cmn x2, x3, lsl #7
+ a08: ab033c5f cmn x2, x3, lsl #15
+ a0c: ab037c5f cmn x2, x3, lsl #31
+ a10: ab03fc5f cmn x2, x3, lsl #63
+ a14: ab43005f cmn x2, x3, lsr #0
+ a18: ab43045f cmn x2, x3, lsr #1
+ a1c: ab430c5f cmn x2, x3, lsr #3
+ a20: ab431c5f cmn x2, x3, lsr #7
+ a24: ab433c5f cmn x2, x3, lsr #15
+ a28: ab437c5f cmn x2, x3, lsr #31
+ a2c: ab43fc5f cmn x2, x3, lsr #63
+ a30: ab83005f cmn x2, x3, asr #0
+ a34: ab83045f cmn x2, x3, asr #1
+ a38: ab830c5f cmn x2, x3, asr #3
+ a3c: ab831c5f cmn x2, x3, asr #7
+ a40: ab833c5f cmn x2, x3, asr #15
+ a44: ab837c5f cmn x2, x3, asr #31
+ a48: ab83fc5f cmn x2, x3, asr #63
+ a4c: ab23005f cmn x2, w3, uxtb
+ a50: ab23045f cmn x2, w3, uxtb #1
+ a54: ab23085f cmn x2, w3, uxtb #2
+ a58: ab230c5f cmn x2, w3, uxtb #3
+ a5c: ab23105f cmn x2, w3, uxtb #4
+ a60: ab23205f cmn x2, w3, uxth
+ a64: ab23245f cmn x2, w3, uxth #1
+ a68: ab23285f cmn x2, w3, uxth #2
+ a6c: ab232c5f cmn x2, w3, uxth #3
+ a70: ab23305f cmn x2, w3, uxth #4
+ a74: ab23405f cmn x2, w3, uxtw
+ a78: ab23445f cmn x2, w3, uxtw #1
+ a7c: ab23485f cmn x2, w3, uxtw #2
+ a80: ab234c5f cmn x2, w3, uxtw #3
+ a84: ab23505f cmn x2, w3, uxtw #4
+ a88: ab23805f cmn x2, w3, sxtb
+ a8c: ab23845f cmn x2, w3, sxtb #1
+ a90: ab23885f cmn x2, w3, sxtb #2
+ a94: ab238c5f cmn x2, w3, sxtb #3
+ a98: ab23905f cmn x2, w3, sxtb #4
+ a9c: ab23a05f cmn x2, w3, sxth
+ aa0: ab23a45f cmn x2, w3, sxth #1
+ aa4: ab23a85f cmn x2, w3, sxth #2
+ aa8: ab23ac5f cmn x2, w3, sxth #3
+ aac: ab23b05f cmn x2, w3, sxth #4
+ ab0: ab23c05f cmn x2, w3, sxtw
+ ab4: ab23c45f cmn x2, w3, sxtw #1
+ ab8: ab23c85f cmn x2, w3, sxtw #2
+ abc: ab23cc5f cmn x2, w3, sxtw #3
+ ac0: ab23d05f cmn x2, w3, sxtw #4
+ ac4: 2b03005f cmn w2, w3
+ ac8: 2b03045f cmn w2, w3, lsl #1
+ acc: 2b030c5f cmn w2, w3, lsl #3
+ ad0: 2b031c5f cmn w2, w3, lsl #7
+ ad4: 2b033c5f cmn w2, w3, lsl #15
+ ad8: 2b037c5f cmn w2, w3, lsl #31
+ adc: 2b43005f cmn w2, w3, lsr #0
+ ae0: 2b43045f cmn w2, w3, lsr #1
+ ae4: 2b430c5f cmn w2, w3, lsr #3
+ ae8: 2b431c5f cmn w2, w3, lsr #7
+ aec: 2b433c5f cmn w2, w3, lsr #15
+ af0: 2b437c5f cmn w2, w3, lsr #31
+ af4: 2b83005f cmn w2, w3, asr #0
+ af8: 2b83045f cmn w2, w3, asr #1
+ afc: 2b830c5f cmn w2, w3, asr #3
+ b00: 2b831c5f cmn w2, w3, asr #7
+ b04: 2b833c5f cmn w2, w3, asr #15
+ b08: 2b837c5f cmn w2, w3, asr #31
+ b0c: 2b23005f cmn w2, w3, uxtb
+ b10: 2b23045f cmn w2, w3, uxtb #1
+ b14: 2b23085f cmn w2, w3, uxtb #2
+ b18: 2b230c5f cmn w2, w3, uxtb #3
+ b1c: 2b23105f cmn w2, w3, uxtb #4
+ b20: 2b23205f cmn w2, w3, uxth
+ b24: 2b23245f cmn w2, w3, uxth #1
+ b28: 2b23285f cmn w2, w3, uxth #2
+ b2c: 2b232c5f cmn w2, w3, uxth #3
+ b30: 2b23305f cmn w2, w3, uxth #4
+ b34: 2b23805f cmn w2, w3, sxtb
+ b38: 2b23845f cmn w2, w3, sxtb #1
+ b3c: 2b23885f cmn w2, w3, sxtb #2
+ b40: 2b238c5f cmn w2, w3, sxtb #3
+ b44: 2b23905f cmn w2, w3, sxtb #4
+ b48: 2b23a05f cmn w2, w3, sxth
+ b4c: 2b23a45f cmn w2, w3, sxth #1
+ b50: 2b23a85f cmn w2, w3, sxth #2
+ b54: 2b23ac5f cmn w2, w3, sxth #3
+ b58: 2b23b05f cmn w2, w3, sxth #4
--- /dev/null
+/* shifted.s Test file for AArch64 add-substract (extended reg.) and
+ add-substract (shifted reg.) instructions.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro op3_64 op, shift
+ \op x1, x2, x3, \shift #0
+ \op x1, x2, x3, \shift #1
+ \op x1, x2, x3, \shift #3
+ \op x1, x2, x3, \shift #7
+ \op x1, x2, x3, \shift #15
+ \op x1, x2, x3, \shift #31
+ \op x1, x2, x3, \shift #63
+ .endm
+
+ .macro op3_32 op, shift
+ \op w1, w2, w3, \shift #0
+ \op w1, w2, w3, \shift #1
+ \op w1, w2, w3, \shift #3
+ \op w1, w2, w3, \shift #7
+ \op w1, w2, w3, \shift #15
+ \op w1, w2, w3, \shift #31
+ .endm
+
+ .macro op3_64x op, shift
+ \op x1, x2, w3, \shift
+ \op x1, x2, w3, \shift #1
+ \op x1, x2, w3, \shift #2
+ \op x1, x2, w3, \shift #3
+ \op x1, x2, w3, \shift #4
+ .endm
+
+ .macro op3_64x_more op, shift
+ \op x1, x2, x3, \shift
+ \op x1, x2, x3, \shift #1
+ \op x1, x2, x3, \shift #2
+ \op x1, x2, x3, \shift #3
+ \op x1, x2, x3, \shift #4
+ .endm
+
+ .macro op3_32x op, shift
+ \op w1, w2, w3, \shift
+ \op w1, w2, w3, \shift #1
+ \op w1, w2, w3, \shift #2
+ \op w1, w2, w3, \shift #3
+ \op w1, w2, w3, \shift #4
+ .endm
+
+ .macro op2_64 op, shift
+ \op x2, x3, \shift #0
+ \op x2, x3, \shift #1
+ \op x2, x3, \shift #3
+ \op x2, x3, \shift #7
+ \op x2, x3, \shift #15
+ \op x2, x3, \shift #31
+ \op x2, x3, \shift #63
+ .endm
+
+ .macro op2_32 op, shift
+ \op w2, w3, \shift #0
+ \op w2, w3, \shift #1
+ \op w2, w3, \shift #3
+ \op w2, w3, \shift #7
+ \op w2, w3, \shift #15
+ \op w2, w3, \shift #31
+ .endm
+
+ .macro op2_64x op, shift
+ \op x2, w3, \shift
+ \op x2, w3, \shift #1
+ \op x2, w3, \shift #2
+ \op x2, w3, \shift #3
+ \op x2, w3, \shift #4
+ .endm
+
+ .macro op2_32x op, shift
+ \op w2, w3, \shift
+ \op w2, w3, \shift #1
+ \op w2, w3, \shift #2
+ \op w2, w3, \shift #3
+ \op w2, w3, \shift #4
+ .endm
+
+ .macro logical op
+ op3_64 \op, lsl
+ op3_64 \op, lsr
+ op3_64 \op, asr
+ op3_64 \op, ror
+ op3_32 \op, lsl
+ op3_32 \op, lsr
+ op3_32 \op, asr
+ op3_32 \op, ror
+ .endm
+
+ .macro arith3 op
+ op3_64 \op, lsl
+ op3_64 \op, lsr
+ op3_64 \op, asr
+ op3_64x \op, uxtb
+ op3_64x \op, uxth
+ op3_64x \op, uxtw
+ op3_64x_more \op, uxtx
+ op3_64x \op, sxtb
+ op3_64x \op, sxth
+ op3_64x \op, sxtw
+ op3_64x_more \op, sxtx
+ op3_32 \op, lsl
+ op3_32 \op, lsr
+ op3_32 \op, asr
+ op3_32x \op, uxtb
+ op3_32x \op, uxth
+ op3_32x \op, sxtb
+ op3_32x \op, sxth
+ .endm
+
+ .macro arith2 op, if_ext=1
+ op2_64 \op, lsl
+ op2_64 \op, lsr
+ op2_64 \op, asr
+ .if \if_ext
+ op2_64x \op, uxtb
+ op2_64x \op, uxth
+ op2_64x \op, uxtw
+ op2_64x \op, sxtb
+ op2_64x \op, sxth
+ op2_64x \op, sxtw
+ .endif
+ op2_32 \op, lsl
+ op2_32 \op, lsr
+ op2_32 \op, asr
+ .if \if_ext
+ op2_32x \op, uxtb
+ op2_32x \op, uxth
+ op2_32x \op, sxtb
+ op2_32x \op, sxth
+ .endif
+ .endm
+
+func:
+ logical orr
+ logical and
+ logical eor
+
+ logical bic
+ logical orn
+ logical eon
+
+ arith3 add
+ arith3 sub
+
+ arith2 neg, 0
+ arith2 cmp
+ arith2 cmn
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: b9400401 ldr w1, \[x0,#4\]
+ 4: b9400401 ldr w1, \[x0,#4\]
+ 8: b9401001 ldr w1, \[x0,#16\]
+ c: b9401001 ldr w1, \[x0,#16\]
+ 10: 8b020020 add x0, x1, x2
+ 14: 91002820 add x0, x1, #0xa
+ 18: d1002c20 sub x0, x1, #0xb
--- /dev/null
+// symbol.s Test file for the parsing of symbols
+
+ .struct 0
+$codesize:
+ .space 4
+$CPU_mode:
+ .space 4
+$entry_point:
+ .space 8
+CPU_mode:
+ .space 4
+
+.text
+ ldr w1, [x0, #$CPU_mode]
+ ldr w1, [x0, $CPU_mode]
+ ldr w1, [x0, #CPU_mode]
+ ldr w1, [x0, CPU_mode]
+
+ // Symbol that has the same name as that of a register
+ // is allowed as long as there is no ambiguity.
+.set x2, 10
+ add x0, x1, x2
+ add x0, x1, #x2
+.set s2, 11
+ sub x0, x1, s2
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: d5380587 mrs x7, id_aa64afr0_el1
+ 4: d53805a7 mrs x7, id_aa64afr1_el1
+ 8: d5380347 mrs x7, mvfr2_el1
+ c: d51b4527 msr dlr_el0, x7
+ 10: d53b4527 mrs x7, dlr_el0
+ 14: d51b4507 msr dspsr_el0, x7
+ 18: d53b4507 mrs x7, dspsr_el0
+ 1c: d51e1127 msr sder32_el3, x7
+ 20: d53e1127 mrs x7, sder32_el3
+ 24: d51e1327 msr mdcr_el3, x7
+ 28: d53e1327 mrs x7, mdcr_el3
+ 2c: d5100207 msr mdccint_el1, x7
+ 30: d5300207 mrs x7, mdccint_el1
+ 34: d5140707 msr dbgvcr32_el2, x7
+ 38: d5340707 mrs x7, dbgvcr32_el2
+ 3c: d51c5307 msr fpexc32_el2, x7
+ 40: d53c5307 mrs x7, fpexc32_el2
+ 44: d5120007 msr teecr32_el1, x7
+ 48: d5320007 mrs x7, teecr32_el1
+ 4c: d5121007 msr teehbr32_el1, x7
+ 50: d5321007 mrs x7, teehbr32_el1
+ 54: d51be207 msr cntp_tval_el0, x7
+ 58: d53be207 mrs x7, cntp_tval_el0
+ 5c: d51be227 msr cntp_ctl_el0, x7
+ 60: d53be227 mrs x7, cntp_ctl_el0
+ 64: d51be247 msr cntp_cval_el0, x7
+ 68: d53be247 mrs x7, cntp_cval_el0
+ 6c: d51fe207 msr cntps_tval_el1, x7
+ 70: d53fe207 mrs x7, cntps_tval_el1
+ 74: d51fe227 msr cntps_ctl_el1, x7
+ 78: d53fe227 mrs x7, cntps_ctl_el1
+ 7c: d51fe247 msr cntps_cval_el1, x7
+ 80: d53fe247 mrs x7, cntps_cval_el1
+ 84: d51b9d07 msr pmccntr_el0, x7
+ 88: d53b9d07 mrs x7, pmccntr_el0
+ 8c: d51be807 msr pmevcntr0_el0, x7
+ 90: d53be807 mrs x7, pmevcntr0_el0
+ 94: d51be827 msr pmevcntr1_el0, x7
+ 98: d53be827 mrs x7, pmevcntr1_el0
+ 9c: d51be847 msr pmevcntr2_el0, x7
+ a0: d53be847 mrs x7, pmevcntr2_el0
+ a4: d51be867 msr pmevcntr3_el0, x7
+ a8: d53be867 mrs x7, pmevcntr3_el0
+ ac: d51be887 msr pmevcntr4_el0, x7
+ b0: d53be887 mrs x7, pmevcntr4_el0
+ b4: d51be8a7 msr pmevcntr5_el0, x7
+ b8: d53be8a7 mrs x7, pmevcntr5_el0
+ bc: d51be8c7 msr pmevcntr6_el0, x7
+ c0: d53be8c7 mrs x7, pmevcntr6_el0
+ c4: d51be8e7 msr pmevcntr7_el0, x7
+ c8: d53be8e7 mrs x7, pmevcntr7_el0
+ cc: d51be907 msr pmevcntr8_el0, x7
+ d0: d53be907 mrs x7, pmevcntr8_el0
+ d4: d51be927 msr pmevcntr9_el0, x7
+ d8: d53be927 mrs x7, pmevcntr9_el0
+ dc: d51be947 msr pmevcntr10_el0, x7
+ e0: d53be947 mrs x7, pmevcntr10_el0
+ e4: d51be967 msr pmevcntr11_el0, x7
+ e8: d53be967 mrs x7, pmevcntr11_el0
+ ec: d51be987 msr pmevcntr12_el0, x7
+ f0: d53be987 mrs x7, pmevcntr12_el0
+ f4: d51be9a7 msr pmevcntr13_el0, x7
+ f8: d53be9a7 mrs x7, pmevcntr13_el0
+ fc: d51be9c7 msr pmevcntr14_el0, x7
+ 100: d53be9c7 mrs x7, pmevcntr14_el0
+ 104: d51be9e7 msr pmevcntr15_el0, x7
+ 108: d53be9e7 mrs x7, pmevcntr15_el0
+ 10c: d51bea07 msr pmevcntr16_el0, x7
+ 110: d53bea07 mrs x7, pmevcntr16_el0
+ 114: d51bea27 msr pmevcntr17_el0, x7
+ 118: d53bea27 mrs x7, pmevcntr17_el0
+ 11c: d51bea47 msr pmevcntr18_el0, x7
+ 120: d53bea47 mrs x7, pmevcntr18_el0
+ 124: d51bea67 msr pmevcntr19_el0, x7
+ 128: d53bea67 mrs x7, pmevcntr19_el0
+ 12c: d51bea87 msr pmevcntr20_el0, x7
+ 130: d53bea87 mrs x7, pmevcntr20_el0
+ 134: d51beaa7 msr pmevcntr21_el0, x7
+ 138: d53beaa7 mrs x7, pmevcntr21_el0
+ 13c: d51beac7 msr pmevcntr22_el0, x7
+ 140: d53beac7 mrs x7, pmevcntr22_el0
+ 144: d51beae7 msr pmevcntr23_el0, x7
+ 148: d53beae7 mrs x7, pmevcntr23_el0
+ 14c: d51beb07 msr pmevcntr24_el0, x7
+ 150: d53beb07 mrs x7, pmevcntr24_el0
+ 154: d51beb27 msr pmevcntr25_el0, x7
+ 158: d53beb27 mrs x7, pmevcntr25_el0
+ 15c: d51beb47 msr pmevcntr26_el0, x7
+ 160: d53beb47 mrs x7, pmevcntr26_el0
+ 164: d51beb67 msr pmevcntr27_el0, x7
+ 168: d53beb67 mrs x7, pmevcntr27_el0
+ 16c: d51beb87 msr pmevcntr28_el0, x7
+ 170: d53beb87 mrs x7, pmevcntr28_el0
+ 174: d51beba7 msr pmevcntr29_el0, x7
+ 178: d53beba7 mrs x7, pmevcntr29_el0
+ 17c: d51bebc7 msr pmevcntr30_el0, x7
+ 180: d53bebc7 mrs x7, pmevcntr30_el0
+ 184: d51bec07 msr pmevtyper0_el0, x7
+ 188: d53bec07 mrs x7, pmevtyper0_el0
+ 18c: d51bec27 msr pmevtyper1_el0, x7
+ 190: d53bec27 mrs x7, pmevtyper1_el0
+ 194: d51bec47 msr pmevtyper2_el0, x7
+ 198: d53bec47 mrs x7, pmevtyper2_el0
+ 19c: d51bec67 msr pmevtyper3_el0, x7
+ 1a0: d53bec67 mrs x7, pmevtyper3_el0
+ 1a4: d51bec87 msr pmevtyper4_el0, x7
+ 1a8: d53bec87 mrs x7, pmevtyper4_el0
+ 1ac: d51beca7 msr pmevtyper5_el0, x7
+ 1b0: d53beca7 mrs x7, pmevtyper5_el0
+ 1b4: d51becc7 msr pmevtyper6_el0, x7
+ 1b8: d53becc7 mrs x7, pmevtyper6_el0
+ 1bc: d51bece7 msr pmevtyper7_el0, x7
+ 1c0: d53bece7 mrs x7, pmevtyper7_el0
+ 1c4: d51bed07 msr pmevtyper8_el0, x7
+ 1c8: d53bed07 mrs x7, pmevtyper8_el0
+ 1cc: d51bed27 msr pmevtyper9_el0, x7
+ 1d0: d53bed27 mrs x7, pmevtyper9_el0
+ 1d4: d51bed47 msr pmevtyper10_el0, x7
+ 1d8: d53bed47 mrs x7, pmevtyper10_el0
+ 1dc: d51bed67 msr pmevtyper11_el0, x7
+ 1e0: d53bed67 mrs x7, pmevtyper11_el0
+ 1e4: d51bed87 msr pmevtyper12_el0, x7
+ 1e8: d53bed87 mrs x7, pmevtyper12_el0
+ 1ec: d51beda7 msr pmevtyper13_el0, x7
+ 1f0: d53beda7 mrs x7, pmevtyper13_el0
+ 1f4: d51bedc7 msr pmevtyper14_el0, x7
+ 1f8: d53bedc7 mrs x7, pmevtyper14_el0
+ 1fc: d51bede7 msr pmevtyper15_el0, x7
+ 200: d53bede7 mrs x7, pmevtyper15_el0
+ 204: d51bee07 msr pmevtyper16_el0, x7
+ 208: d53bee07 mrs x7, pmevtyper16_el0
+ 20c: d51bee27 msr pmevtyper17_el0, x7
+ 210: d53bee27 mrs x7, pmevtyper17_el0
+ 214: d51bee47 msr pmevtyper18_el0, x7
+ 218: d53bee47 mrs x7, pmevtyper18_el0
+ 21c: d51bee67 msr pmevtyper19_el0, x7
+ 220: d53bee67 mrs x7, pmevtyper19_el0
+ 224: d51bee87 msr pmevtyper20_el0, x7
+ 228: d53bee87 mrs x7, pmevtyper20_el0
+ 22c: d51beea7 msr pmevtyper21_el0, x7
+ 230: d53beea7 mrs x7, pmevtyper21_el0
+ 234: d51beec7 msr pmevtyper22_el0, x7
+ 238: d53beec7 mrs x7, pmevtyper22_el0
+ 23c: d51beee7 msr pmevtyper23_el0, x7
+ 240: d53beee7 mrs x7, pmevtyper23_el0
+ 244: d51bef07 msr pmevtyper24_el0, x7
+ 248: d53bef07 mrs x7, pmevtyper24_el0
+ 24c: d51bef27 msr pmevtyper25_el0, x7
+ 250: d53bef27 mrs x7, pmevtyper25_el0
+ 254: d51bef47 msr pmevtyper26_el0, x7
+ 258: d53bef47 mrs x7, pmevtyper26_el0
+ 25c: d51bef67 msr pmevtyper27_el0, x7
+ 260: d53bef67 mrs x7, pmevtyper27_el0
+ 264: d51bef87 msr pmevtyper28_el0, x7
+ 268: d53bef87 mrs x7, pmevtyper28_el0
+ 26c: d51befa7 msr pmevtyper29_el0, x7
+ 270: d53befa7 mrs x7, pmevtyper29_el0
+ 274: d51befc7 msr pmevtyper30_el0, x7
+ 278: d53befc7 mrs x7, pmevtyper30_el0
+ 27c: d51befe7 msr pmccfiltr_el0, x7
+ 280: d53befe7 mrs x7, pmccfiltr_el0
+ 284: d51bd067 msr tpidrro_el0, x7
+ 288: d53bd067 mrs x7, tpidrro_el0
+ 28c: d51bd047 msr tpidr_el0, x7
+ 290: d53bd047 mrs x7, tpidr_el0
+ 294: d51be007 msr cntfrq_el0, x7
+ 298: d53be007 mrs x7, cntfrq_el0
+ 29c: d518b00f msr s3_0_c11_c0_0, x15
+ 2a0: d538b00f mrs x15, s3_0_c11_c0_0
+ 2a4: d518b02f msr s3_0_c11_c0_1, x15
+ 2a8: d538b02f mrs x15, s3_0_c11_c0_1
+ 2ac: d518b04f msr s3_0_c11_c0_2, x15
+ 2b0: d538b04f mrs x15, s3_0_c11_c0_2
+ 2b4: d518b06f msr s3_0_c11_c0_3, x15
+ 2b8: d538b06f mrs x15, s3_0_c11_c0_3
+ 2bc: d518b08f msr s3_0_c11_c0_4, x15
+ 2c0: d538b08f mrs x15, s3_0_c11_c0_4
+ 2c4: d518b0af msr s3_0_c11_c0_5, x15
+ 2c8: d538b0af mrs x15, s3_0_c11_c0_5
+ 2cc: d518b0cf msr s3_0_c11_c0_6, x15
+ 2d0: d538b0cf mrs x15, s3_0_c11_c0_6
+ 2d4: d518b0ef msr s3_0_c11_c0_7, x15
+ 2d8: d538b0ef mrs x15, s3_0_c11_c0_7
+ 2dc: d518b10f msr s3_0_c11_c1_0, x15
+ 2e0: d538b10f mrs x15, s3_0_c11_c1_0
+ 2e4: d518b12f msr s3_0_c11_c1_1, x15
+ 2e8: d538b12f mrs x15, s3_0_c11_c1_1
+ 2ec: d518b14f msr s3_0_c11_c1_2, x15
+ 2f0: d538b14f mrs x15, s3_0_c11_c1_2
+ 2f4: d518b16f msr s3_0_c11_c1_3, x15
+ 2f8: d538b16f mrs x15, s3_0_c11_c1_3
+ 2fc: d518b18f msr s3_0_c11_c1_4, x15
+ 300: d538b18f mrs x15, s3_0_c11_c1_4
+ 304: d518b1af msr s3_0_c11_c1_5, x15
+ 308: d538b1af mrs x15, s3_0_c11_c1_5
+ 30c: d518b1cf msr s3_0_c11_c1_6, x15
+ 310: d538b1cf mrs x15, s3_0_c11_c1_6
+ 314: d518b1ef msr s3_0_c11_c1_7, x15
+ 318: d538b1ef mrs x15, s3_0_c11_c1_7
+ 31c: d518b20f msr s3_0_c11_c2_0, x15
+ 320: d538b20f mrs x15, s3_0_c11_c2_0
+ 324: d518b22f msr s3_0_c11_c2_1, x15
+ 328: d538b22f mrs x15, s3_0_c11_c2_1
+ 32c: d518b24f msr s3_0_c11_c2_2, x15
+ 330: d538b24f mrs x15, s3_0_c11_c2_2
+ 334: d518b26f msr s3_0_c11_c2_3, x15
+ 338: d538b26f mrs x15, s3_0_c11_c2_3
+ 33c: d518b28f msr s3_0_c11_c2_4, x15
+ 340: d538b28f mrs x15, s3_0_c11_c2_4
+ 344: d518b2af msr s3_0_c11_c2_5, x15
+ 348: d538b2af mrs x15, s3_0_c11_c2_5
+ 34c: d518b2cf msr s3_0_c11_c2_6, x15
+ 350: d538b2cf mrs x15, s3_0_c11_c2_6
+ 354: d518b2ef msr s3_0_c11_c2_7, x15
+ 358: d538b2ef mrs x15, s3_0_c11_c2_7
+ 35c: d518b30f msr s3_0_c11_c3_0, x15
+ 360: d538b30f mrs x15, s3_0_c11_c3_0
+ 364: d518b32f msr s3_0_c11_c3_1, x15
+ 368: d538b32f mrs x15, s3_0_c11_c3_1
+ 36c: d518b34f msr s3_0_c11_c3_2, x15
+ 370: d538b34f mrs x15, s3_0_c11_c3_2
+ 374: d518b36f msr s3_0_c11_c3_3, x15
+ 378: d538b36f mrs x15, s3_0_c11_c3_3
+ 37c: d518b38f msr s3_0_c11_c3_4, x15
+ 380: d538b38f mrs x15, s3_0_c11_c3_4
+ 384: d518b3af msr s3_0_c11_c3_5, x15
+ 388: d538b3af mrs x15, s3_0_c11_c3_5
+ 38c: d518b3cf msr s3_0_c11_c3_6, x15
+ 390: d538b3cf mrs x15, s3_0_c11_c3_6
+ 394: d518b3ef msr s3_0_c11_c3_7, x15
+ 398: d538b3ef mrs x15, s3_0_c11_c3_7
+ 39c: d518b40f msr s3_0_c11_c4_0, x15
+ 3a0: d538b40f mrs x15, s3_0_c11_c4_0
+ 3a4: d518b42f msr s3_0_c11_c4_1, x15
+ 3a8: d538b42f mrs x15, s3_0_c11_c4_1
+ 3ac: d518b44f msr s3_0_c11_c4_2, x15
+ 3b0: d538b44f mrs x15, s3_0_c11_c4_2
+ 3b4: d518b46f msr s3_0_c11_c4_3, x15
+ 3b8: d538b46f mrs x15, s3_0_c11_c4_3
+ 3bc: d518b48f msr s3_0_c11_c4_4, x15
+ 3c0: d538b48f mrs x15, s3_0_c11_c4_4
+ 3c4: d518b4af msr s3_0_c11_c4_5, x15
+ 3c8: d538b4af mrs x15, s3_0_c11_c4_5
+ 3cc: d518b4cf msr s3_0_c11_c4_6, x15
+ 3d0: d538b4cf mrs x15, s3_0_c11_c4_6
+ 3d4: d518b4ef msr s3_0_c11_c4_7, x15
+ 3d8: d538b4ef mrs x15, s3_0_c11_c4_7
+ 3dc: d518b50f msr s3_0_c11_c5_0, x15
+ 3e0: d538b50f mrs x15, s3_0_c11_c5_0
+ 3e4: d518b52f msr s3_0_c11_c5_1, x15
+ 3e8: d538b52f mrs x15, s3_0_c11_c5_1
+ 3ec: d518b54f msr s3_0_c11_c5_2, x15
+ 3f0: d538b54f mrs x15, s3_0_c11_c5_2
+ 3f4: d518b56f msr s3_0_c11_c5_3, x15
+ 3f8: d538b56f mrs x15, s3_0_c11_c5_3
+ 3fc: d518b58f msr s3_0_c11_c5_4, x15
+ 400: d538b58f mrs x15, s3_0_c11_c5_4
+ 404: d518b5af msr s3_0_c11_c5_5, x15
+ 408: d538b5af mrs x15, s3_0_c11_c5_5
+ 40c: d518b5cf msr s3_0_c11_c5_6, x15
+ 410: d538b5cf mrs x15, s3_0_c11_c5_6
+ 414: d518b5ef msr s3_0_c11_c5_7, x15
+ 418: d538b5ef mrs x15, s3_0_c11_c5_7
+ 41c: d518b60f msr s3_0_c11_c6_0, x15
+ 420: d538b60f mrs x15, s3_0_c11_c6_0
+ 424: d518b62f msr s3_0_c11_c6_1, x15
+ 428: d538b62f mrs x15, s3_0_c11_c6_1
+ 42c: d518b64f msr s3_0_c11_c6_2, x15
+ 430: d538b64f mrs x15, s3_0_c11_c6_2
+ 434: d518b66f msr s3_0_c11_c6_3, x15
+ 438: d538b66f mrs x15, s3_0_c11_c6_3
+ 43c: d518b68f msr s3_0_c11_c6_4, x15
+ 440: d538b68f mrs x15, s3_0_c11_c6_4
+ 444: d518b6af msr s3_0_c11_c6_5, x15
+ 448: d538b6af mrs x15, s3_0_c11_c6_5
+ 44c: d518b6cf msr s3_0_c11_c6_6, x15
+ 450: d538b6cf mrs x15, s3_0_c11_c6_6
+ 454: d518b6ef msr s3_0_c11_c6_7, x15
+ 458: d538b6ef mrs x15, s3_0_c11_c6_7
+ 45c: d518b70f msr s3_0_c11_c7_0, x15
+ 460: d538b70f mrs x15, s3_0_c11_c7_0
+ 464: d518b72f msr s3_0_c11_c7_1, x15
+ 468: d538b72f mrs x15, s3_0_c11_c7_1
+ 46c: d518b74f msr s3_0_c11_c7_2, x15
+ 470: d538b74f mrs x15, s3_0_c11_c7_2
+ 474: d518b76f msr s3_0_c11_c7_3, x15
+ 478: d538b76f mrs x15, s3_0_c11_c7_3
+ 47c: d518b78f msr s3_0_c11_c7_4, x15
+ 480: d538b78f mrs x15, s3_0_c11_c7_4
+ 484: d518b7af msr s3_0_c11_c7_5, x15
+ 488: d538b7af mrs x15, s3_0_c11_c7_5
+ 48c: d518b7cf msr s3_0_c11_c7_6, x15
+ 490: d538b7cf mrs x15, s3_0_c11_c7_6
+ 494: d518b7ef msr s3_0_c11_c7_7, x15
+ 498: d538b7ef mrs x15, s3_0_c11_c7_7
+ 49c: d518b80f msr s3_0_c11_c8_0, x15
+ 4a0: d538b80f mrs x15, s3_0_c11_c8_0
+ 4a4: d518b82f msr s3_0_c11_c8_1, x15
+ 4a8: d538b82f mrs x15, s3_0_c11_c8_1
+ 4ac: d518b84f msr s3_0_c11_c8_2, x15
+ 4b0: d538b84f mrs x15, s3_0_c11_c8_2
+ 4b4: d518b86f msr s3_0_c11_c8_3, x15
+ 4b8: d538b86f mrs x15, s3_0_c11_c8_3
+ 4bc: d518b88f msr s3_0_c11_c8_4, x15
+ 4c0: d538b88f mrs x15, s3_0_c11_c8_4
+ 4c4: d518b8af msr s3_0_c11_c8_5, x15
+ 4c8: d538b8af mrs x15, s3_0_c11_c8_5
+ 4cc: d518b8cf msr s3_0_c11_c8_6, x15
+ 4d0: d538b8cf mrs x15, s3_0_c11_c8_6
+ 4d4: d518b8ef msr s3_0_c11_c8_7, x15
+ 4d8: d538b8ef mrs x15, s3_0_c11_c8_7
+ 4dc: d518b90f msr s3_0_c11_c9_0, x15
+ 4e0: d538b90f mrs x15, s3_0_c11_c9_0
+ 4e4: d518b92f msr s3_0_c11_c9_1, x15
+ 4e8: d538b92f mrs x15, s3_0_c11_c9_1
+ 4ec: d518b94f msr s3_0_c11_c9_2, x15
+ 4f0: d538b94f mrs x15, s3_0_c11_c9_2
+ 4f4: d518b96f msr s3_0_c11_c9_3, x15
+ 4f8: d538b96f mrs x15, s3_0_c11_c9_3
+ 4fc: d518b98f msr s3_0_c11_c9_4, x15
+ 500: d538b98f mrs x15, s3_0_c11_c9_4
+ 504: d518b9af msr s3_0_c11_c9_5, x15
+ 508: d538b9af mrs x15, s3_0_c11_c9_5
+ 50c: d518b9cf msr s3_0_c11_c9_6, x15
+ 510: d538b9cf mrs x15, s3_0_c11_c9_6
+ 514: d518b9ef msr s3_0_c11_c9_7, x15
+ 518: d538b9ef mrs x15, s3_0_c11_c9_7
+ 51c: d518ba0f msr s3_0_c11_c10_0, x15
+ 520: d538ba0f mrs x15, s3_0_c11_c10_0
+ 524: d518ba2f msr s3_0_c11_c10_1, x15
+ 528: d538ba2f mrs x15, s3_0_c11_c10_1
+ 52c: d518ba4f msr s3_0_c11_c10_2, x15
+ 530: d538ba4f mrs x15, s3_0_c11_c10_2
+ 534: d518ba6f msr s3_0_c11_c10_3, x15
+ 538: d538ba6f mrs x15, s3_0_c11_c10_3
+ 53c: d518ba8f msr s3_0_c11_c10_4, x15
+ 540: d538ba8f mrs x15, s3_0_c11_c10_4
+ 544: d518baaf msr s3_0_c11_c10_5, x15
+ 548: d538baaf mrs x15, s3_0_c11_c10_5
+ 54c: d518bacf msr s3_0_c11_c10_6, x15
+ 550: d538bacf mrs x15, s3_0_c11_c10_6
+ 554: d518baef msr s3_0_c11_c10_7, x15
+ 558: d538baef mrs x15, s3_0_c11_c10_7
+ 55c: d518bb0f msr s3_0_c11_c11_0, x15
+ 560: d538bb0f mrs x15, s3_0_c11_c11_0
+ 564: d518bb2f msr s3_0_c11_c11_1, x15
+ 568: d538bb2f mrs x15, s3_0_c11_c11_1
+ 56c: d518bb4f msr s3_0_c11_c11_2, x15
+ 570: d538bb4f mrs x15, s3_0_c11_c11_2
+ 574: d518bb6f msr s3_0_c11_c11_3, x15
+ 578: d538bb6f mrs x15, s3_0_c11_c11_3
+ 57c: d518bb8f msr s3_0_c11_c11_4, x15
+ 580: d538bb8f mrs x15, s3_0_c11_c11_4
+ 584: d518bbaf msr s3_0_c11_c11_5, x15
+ 588: d538bbaf mrs x15, s3_0_c11_c11_5
+ 58c: d518bbcf msr s3_0_c11_c11_6, x15
+ 590: d538bbcf mrs x15, s3_0_c11_c11_6
+ 594: d518bbef msr s3_0_c11_c11_7, x15
+ 598: d538bbef mrs x15, s3_0_c11_c11_7
+ 59c: d518bc0f msr s3_0_c11_c12_0, x15
+ 5a0: d538bc0f mrs x15, s3_0_c11_c12_0
+ 5a4: d518bc2f msr s3_0_c11_c12_1, x15
+ 5a8: d538bc2f mrs x15, s3_0_c11_c12_1
+ 5ac: d518bc4f msr s3_0_c11_c12_2, x15
+ 5b0: d538bc4f mrs x15, s3_0_c11_c12_2
+ 5b4: d518bc6f msr s3_0_c11_c12_3, x15
+ 5b8: d538bc6f mrs x15, s3_0_c11_c12_3
+ 5bc: d518bc8f msr s3_0_c11_c12_4, x15
+ 5c0: d538bc8f mrs x15, s3_0_c11_c12_4
+ 5c4: d518bcaf msr s3_0_c11_c12_5, x15
+ 5c8: d538bcaf mrs x15, s3_0_c11_c12_5
+ 5cc: d518bccf msr s3_0_c11_c12_6, x15
+ 5d0: d538bccf mrs x15, s3_0_c11_c12_6
+ 5d4: d518bcef msr s3_0_c11_c12_7, x15
+ 5d8: d538bcef mrs x15, s3_0_c11_c12_7
+ 5dc: d518bd0f msr s3_0_c11_c13_0, x15
+ 5e0: d538bd0f mrs x15, s3_0_c11_c13_0
+ 5e4: d518bd2f msr s3_0_c11_c13_1, x15
+ 5e8: d538bd2f mrs x15, s3_0_c11_c13_1
+ 5ec: d518bd4f msr s3_0_c11_c13_2, x15
+ 5f0: d538bd4f mrs x15, s3_0_c11_c13_2
+ 5f4: d518bd6f msr s3_0_c11_c13_3, x15
+ 5f8: d538bd6f mrs x15, s3_0_c11_c13_3
+ 5fc: d518bd8f msr s3_0_c11_c13_4, x15
+ 600: d538bd8f mrs x15, s3_0_c11_c13_4
+ 604: d518bdaf msr s3_0_c11_c13_5, x15
+ 608: d538bdaf mrs x15, s3_0_c11_c13_5
+ 60c: d518bdcf msr s3_0_c11_c13_6, x15
+ 610: d538bdcf mrs x15, s3_0_c11_c13_6
+ 614: d518bdef msr s3_0_c11_c13_7, x15
+ 618: d538bdef mrs x15, s3_0_c11_c13_7
+ 61c: d518be0f msr s3_0_c11_c14_0, x15
+ 620: d538be0f mrs x15, s3_0_c11_c14_0
+ 624: d518be2f msr s3_0_c11_c14_1, x15
+ 628: d538be2f mrs x15, s3_0_c11_c14_1
+ 62c: d518be4f msr s3_0_c11_c14_2, x15
+ 630: d538be4f mrs x15, s3_0_c11_c14_2
+ 634: d518be6f msr s3_0_c11_c14_3, x15
+ 638: d538be6f mrs x15, s3_0_c11_c14_3
+ 63c: d518be8f msr s3_0_c11_c14_4, x15
+ 640: d538be8f mrs x15, s3_0_c11_c14_4
+ 644: d518beaf msr s3_0_c11_c14_5, x15
+ 648: d538beaf mrs x15, s3_0_c11_c14_5
+ 64c: d518becf msr s3_0_c11_c14_6, x15
+ 650: d538becf mrs x15, s3_0_c11_c14_6
+ 654: d518beef msr s3_0_c11_c14_7, x15
+ 658: d538beef mrs x15, s3_0_c11_c14_7
+ 65c: d518bf0f msr s3_0_c11_c15_0, x15
+ 660: d538bf0f mrs x15, s3_0_c11_c15_0
+ 664: d518bf2f msr s3_0_c11_c15_1, x15
+ 668: d538bf2f mrs x15, s3_0_c11_c15_1
+ 66c: d518bf4f msr s3_0_c11_c15_2, x15
+ 670: d538bf4f mrs x15, s3_0_c11_c15_2
+ 674: d518bf6f msr s3_0_c11_c15_3, x15
+ 678: d538bf6f mrs x15, s3_0_c11_c15_3
+ 67c: d518bf8f msr s3_0_c11_c15_4, x15
+ 680: d538bf8f mrs x15, s3_0_c11_c15_4
+ 684: d518bfaf msr s3_0_c11_c15_5, x15
+ 688: d538bfaf mrs x15, s3_0_c11_c15_5
+ 68c: d518bfcf msr s3_0_c11_c15_6, x15
+ 690: d538bfcf mrs x15, s3_0_c11_c15_6
+ 694: d518bfef msr s3_0_c11_c15_7, x15
+ 698: d538bfef mrs x15, s3_0_c11_c15_7
+ 69c: d518f00f msr s3_0_c15_c0_0, x15
+ 6a0: d538f00f mrs x15, s3_0_c15_c0_0
+ 6a4: d518f02f msr s3_0_c15_c0_1, x15
+ 6a8: d538f02f mrs x15, s3_0_c15_c0_1
+ 6ac: d518f04f msr s3_0_c15_c0_2, x15
+ 6b0: d538f04f mrs x15, s3_0_c15_c0_2
+ 6b4: d518f06f msr s3_0_c15_c0_3, x15
+ 6b8: d538f06f mrs x15, s3_0_c15_c0_3
+ 6bc: d518f08f msr s3_0_c15_c0_4, x15
+ 6c0: d538f08f mrs x15, s3_0_c15_c0_4
+ 6c4: d518f0af msr s3_0_c15_c0_5, x15
+ 6c8: d538f0af mrs x15, s3_0_c15_c0_5
+ 6cc: d518f0cf msr s3_0_c15_c0_6, x15
+ 6d0: d538f0cf mrs x15, s3_0_c15_c0_6
+ 6d4: d518f0ef msr s3_0_c15_c0_7, x15
+ 6d8: d538f0ef mrs x15, s3_0_c15_c0_7
+ 6dc: d518f10f msr s3_0_c15_c1_0, x15
+ 6e0: d538f10f mrs x15, s3_0_c15_c1_0
+ 6e4: d518f12f msr s3_0_c15_c1_1, x15
+ 6e8: d538f12f mrs x15, s3_0_c15_c1_1
+ 6ec: d518f14f msr s3_0_c15_c1_2, x15
+ 6f0: d538f14f mrs x15, s3_0_c15_c1_2
+ 6f4: d518f16f msr s3_0_c15_c1_3, x15
+ 6f8: d538f16f mrs x15, s3_0_c15_c1_3
+ 6fc: d518f18f msr s3_0_c15_c1_4, x15
+ 700: d538f18f mrs x15, s3_0_c15_c1_4
+ 704: d518f1af msr s3_0_c15_c1_5, x15
+ 708: d538f1af mrs x15, s3_0_c15_c1_5
+ 70c: d518f1cf msr s3_0_c15_c1_6, x15
+ 710: d538f1cf mrs x15, s3_0_c15_c1_6
+ 714: d518f1ef msr s3_0_c15_c1_7, x15
+ 718: d538f1ef mrs x15, s3_0_c15_c1_7
+ 71c: d518f20f msr s3_0_c15_c2_0, x15
+ 720: d538f20f mrs x15, s3_0_c15_c2_0
+ 724: d518f22f msr s3_0_c15_c2_1, x15
+ 728: d538f22f mrs x15, s3_0_c15_c2_1
+ 72c: d518f24f msr s3_0_c15_c2_2, x15
+ 730: d538f24f mrs x15, s3_0_c15_c2_2
+ 734: d518f26f msr s3_0_c15_c2_3, x15
+ 738: d538f26f mrs x15, s3_0_c15_c2_3
+ 73c: d518f28f msr s3_0_c15_c2_4, x15
+ 740: d538f28f mrs x15, s3_0_c15_c2_4
+ 744: d518f2af msr s3_0_c15_c2_5, x15
+ 748: d538f2af mrs x15, s3_0_c15_c2_5
+ 74c: d518f2cf msr s3_0_c15_c2_6, x15
+ 750: d538f2cf mrs x15, s3_0_c15_c2_6
+ 754: d518f2ef msr s3_0_c15_c2_7, x15
+ 758: d538f2ef mrs x15, s3_0_c15_c2_7
+ 75c: d518f30f msr s3_0_c15_c3_0, x15
+ 760: d538f30f mrs x15, s3_0_c15_c3_0
+ 764: d518f32f msr s3_0_c15_c3_1, x15
+ 768: d538f32f mrs x15, s3_0_c15_c3_1
+ 76c: d518f34f msr s3_0_c15_c3_2, x15
+ 770: d538f34f mrs x15, s3_0_c15_c3_2
+ 774: d518f36f msr s3_0_c15_c3_3, x15
+ 778: d538f36f mrs x15, s3_0_c15_c3_3
+ 77c: d518f38f msr s3_0_c15_c3_4, x15
+ 780: d538f38f mrs x15, s3_0_c15_c3_4
+ 784: d518f3af msr s3_0_c15_c3_5, x15
+ 788: d538f3af mrs x15, s3_0_c15_c3_5
+ 78c: d518f3cf msr s3_0_c15_c3_6, x15
+ 790: d538f3cf mrs x15, s3_0_c15_c3_6
+ 794: d518f3ef msr s3_0_c15_c3_7, x15
+ 798: d538f3ef mrs x15, s3_0_c15_c3_7
+ 79c: d518f40f msr s3_0_c15_c4_0, x15
+ 7a0: d538f40f mrs x15, s3_0_c15_c4_0
+ 7a4: d518f42f msr s3_0_c15_c4_1, x15
+ 7a8: d538f42f mrs x15, s3_0_c15_c4_1
+ 7ac: d518f44f msr s3_0_c15_c4_2, x15
+ 7b0: d538f44f mrs x15, s3_0_c15_c4_2
+ 7b4: d518f46f msr s3_0_c15_c4_3, x15
+ 7b8: d538f46f mrs x15, s3_0_c15_c4_3
+ 7bc: d518f48f msr s3_0_c15_c4_4, x15
+ 7c0: d538f48f mrs x15, s3_0_c15_c4_4
+ 7c4: d518f4af msr s3_0_c15_c4_5, x15
+ 7c8: d538f4af mrs x15, s3_0_c15_c4_5
+ 7cc: d518f4cf msr s3_0_c15_c4_6, x15
+ 7d0: d538f4cf mrs x15, s3_0_c15_c4_6
+ 7d4: d518f4ef msr s3_0_c15_c4_7, x15
+ 7d8: d538f4ef mrs x15, s3_0_c15_c4_7
+ 7dc: d518f50f msr s3_0_c15_c5_0, x15
+ 7e0: d538f50f mrs x15, s3_0_c15_c5_0
+ 7e4: d518f52f msr s3_0_c15_c5_1, x15
+ 7e8: d538f52f mrs x15, s3_0_c15_c5_1
+ 7ec: d518f54f msr s3_0_c15_c5_2, x15
+ 7f0: d538f54f mrs x15, s3_0_c15_c5_2
+ 7f4: d518f56f msr s3_0_c15_c5_3, x15
+ 7f8: d538f56f mrs x15, s3_0_c15_c5_3
+ 7fc: d518f58f msr s3_0_c15_c5_4, x15
+ 800: d538f58f mrs x15, s3_0_c15_c5_4
+ 804: d518f5af msr s3_0_c15_c5_5, x15
+ 808: d538f5af mrs x15, s3_0_c15_c5_5
+ 80c: d518f5cf msr s3_0_c15_c5_6, x15
+ 810: d538f5cf mrs x15, s3_0_c15_c5_6
+ 814: d518f5ef msr s3_0_c15_c5_7, x15
+ 818: d538f5ef mrs x15, s3_0_c15_c5_7
+ 81c: d518f60f msr s3_0_c15_c6_0, x15
+ 820: d538f60f mrs x15, s3_0_c15_c6_0
+ 824: d518f62f msr s3_0_c15_c6_1, x15
+ 828: d538f62f mrs x15, s3_0_c15_c6_1
+ 82c: d518f64f msr s3_0_c15_c6_2, x15
+ 830: d538f64f mrs x15, s3_0_c15_c6_2
+ 834: d518f66f msr s3_0_c15_c6_3, x15
+ 838: d538f66f mrs x15, s3_0_c15_c6_3
+ 83c: d518f68f msr s3_0_c15_c6_4, x15
+ 840: d538f68f mrs x15, s3_0_c15_c6_4
+ 844: d518f6af msr s3_0_c15_c6_5, x15
+ 848: d538f6af mrs x15, s3_0_c15_c6_5
+ 84c: d518f6cf msr s3_0_c15_c6_6, x15
+ 850: d538f6cf mrs x15, s3_0_c15_c6_6
+ 854: d518f6ef msr s3_0_c15_c6_7, x15
+ 858: d538f6ef mrs x15, s3_0_c15_c6_7
+ 85c: d518f70f msr s3_0_c15_c7_0, x15
+ 860: d538f70f mrs x15, s3_0_c15_c7_0
+ 864: d518f72f msr s3_0_c15_c7_1, x15
+ 868: d538f72f mrs x15, s3_0_c15_c7_1
+ 86c: d518f74f msr s3_0_c15_c7_2, x15
+ 870: d538f74f mrs x15, s3_0_c15_c7_2
+ 874: d518f76f msr s3_0_c15_c7_3, x15
+ 878: d538f76f mrs x15, s3_0_c15_c7_3
+ 87c: d518f78f msr s3_0_c15_c7_4, x15
+ 880: d538f78f mrs x15, s3_0_c15_c7_4
+ 884: d518f7af msr s3_0_c15_c7_5, x15
+ 888: d538f7af mrs x15, s3_0_c15_c7_5
+ 88c: d518f7cf msr s3_0_c15_c7_6, x15
+ 890: d538f7cf mrs x15, s3_0_c15_c7_6
+ 894: d518f7ef msr s3_0_c15_c7_7, x15
+ 898: d538f7ef mrs x15, s3_0_c15_c7_7
+ 89c: d518f80f msr s3_0_c15_c8_0, x15
+ 8a0: d538f80f mrs x15, s3_0_c15_c8_0
+ 8a4: d518f82f msr s3_0_c15_c8_1, x15
+ 8a8: d538f82f mrs x15, s3_0_c15_c8_1
+ 8ac: d518f84f msr s3_0_c15_c8_2, x15
+ 8b0: d538f84f mrs x15, s3_0_c15_c8_2
+ 8b4: d518f86f msr s3_0_c15_c8_3, x15
+ 8b8: d538f86f mrs x15, s3_0_c15_c8_3
+ 8bc: d518f88f msr s3_0_c15_c8_4, x15
+ 8c0: d538f88f mrs x15, s3_0_c15_c8_4
+ 8c4: d518f8af msr s3_0_c15_c8_5, x15
+ 8c8: d538f8af mrs x15, s3_0_c15_c8_5
+ 8cc: d518f8cf msr s3_0_c15_c8_6, x15
+ 8d0: d538f8cf mrs x15, s3_0_c15_c8_6
+ 8d4: d518f8ef msr s3_0_c15_c8_7, x15
+ 8d8: d538f8ef mrs x15, s3_0_c15_c8_7
+ 8dc: d518f90f msr s3_0_c15_c9_0, x15
+ 8e0: d538f90f mrs x15, s3_0_c15_c9_0
+ 8e4: d518f92f msr s3_0_c15_c9_1, x15
+ 8e8: d538f92f mrs x15, s3_0_c15_c9_1
+ 8ec: d518f94f msr s3_0_c15_c9_2, x15
+ 8f0: d538f94f mrs x15, s3_0_c15_c9_2
+ 8f4: d518f96f msr s3_0_c15_c9_3, x15
+ 8f8: d538f96f mrs x15, s3_0_c15_c9_3
+ 8fc: d518f98f msr s3_0_c15_c9_4, x15
+ 900: d538f98f mrs x15, s3_0_c15_c9_4
+ 904: d518f9af msr s3_0_c15_c9_5, x15
+ 908: d538f9af mrs x15, s3_0_c15_c9_5
+ 90c: d518f9cf msr s3_0_c15_c9_6, x15
+ 910: d538f9cf mrs x15, s3_0_c15_c9_6
+ 914: d518f9ef msr s3_0_c15_c9_7, x15
+ 918: d538f9ef mrs x15, s3_0_c15_c9_7
+ 91c: d518fa0f msr s3_0_c15_c10_0, x15
+ 920: d538fa0f mrs x15, s3_0_c15_c10_0
+ 924: d518fa2f msr s3_0_c15_c10_1, x15
+ 928: d538fa2f mrs x15, s3_0_c15_c10_1
+ 92c: d518fa4f msr s3_0_c15_c10_2, x15
+ 930: d538fa4f mrs x15, s3_0_c15_c10_2
+ 934: d518fa6f msr s3_0_c15_c10_3, x15
+ 938: d538fa6f mrs x15, s3_0_c15_c10_3
+ 93c: d518fa8f msr s3_0_c15_c10_4, x15
+ 940: d538fa8f mrs x15, s3_0_c15_c10_4
+ 944: d518faaf msr s3_0_c15_c10_5, x15
+ 948: d538faaf mrs x15, s3_0_c15_c10_5
+ 94c: d518facf msr s3_0_c15_c10_6, x15
+ 950: d538facf mrs x15, s3_0_c15_c10_6
+ 954: d518faef msr s3_0_c15_c10_7, x15
+ 958: d538faef mrs x15, s3_0_c15_c10_7
+ 95c: d518fb0f msr s3_0_c15_c11_0, x15
+ 960: d538fb0f mrs x15, s3_0_c15_c11_0
+ 964: d518fb2f msr s3_0_c15_c11_1, x15
+ 968: d538fb2f mrs x15, s3_0_c15_c11_1
+ 96c: d518fb4f msr s3_0_c15_c11_2, x15
+ 970: d538fb4f mrs x15, s3_0_c15_c11_2
+ 974: d518fb6f msr s3_0_c15_c11_3, x15
+ 978: d538fb6f mrs x15, s3_0_c15_c11_3
+ 97c: d518fb8f msr s3_0_c15_c11_4, x15
+ 980: d538fb8f mrs x15, s3_0_c15_c11_4
+ 984: d518fbaf msr s3_0_c15_c11_5, x15
+ 988: d538fbaf mrs x15, s3_0_c15_c11_5
+ 98c: d518fbcf msr s3_0_c15_c11_6, x15
+ 990: d538fbcf mrs x15, s3_0_c15_c11_6
+ 994: d518fbef msr s3_0_c15_c11_7, x15
+ 998: d538fbef mrs x15, s3_0_c15_c11_7
+ 99c: d518fc0f msr s3_0_c15_c12_0, x15
+ 9a0: d538fc0f mrs x15, s3_0_c15_c12_0
+ 9a4: d518fc2f msr s3_0_c15_c12_1, x15
+ 9a8: d538fc2f mrs x15, s3_0_c15_c12_1
+ 9ac: d518fc4f msr s3_0_c15_c12_2, x15
+ 9b0: d538fc4f mrs x15, s3_0_c15_c12_2
+ 9b4: d518fc6f msr s3_0_c15_c12_3, x15
+ 9b8: d538fc6f mrs x15, s3_0_c15_c12_3
+ 9bc: d518fc8f msr s3_0_c15_c12_4, x15
+ 9c0: d538fc8f mrs x15, s3_0_c15_c12_4
+ 9c4: d518fcaf msr s3_0_c15_c12_5, x15
+ 9c8: d538fcaf mrs x15, s3_0_c15_c12_5
+ 9cc: d518fccf msr s3_0_c15_c12_6, x15
+ 9d0: d538fccf mrs x15, s3_0_c15_c12_6
+ 9d4: d518fcef msr s3_0_c15_c12_7, x15
+ 9d8: d538fcef mrs x15, s3_0_c15_c12_7
+ 9dc: d518fd0f msr s3_0_c15_c13_0, x15
+ 9e0: d538fd0f mrs x15, s3_0_c15_c13_0
+ 9e4: d518fd2f msr s3_0_c15_c13_1, x15
+ 9e8: d538fd2f mrs x15, s3_0_c15_c13_1
+ 9ec: d518fd4f msr s3_0_c15_c13_2, x15
+ 9f0: d538fd4f mrs x15, s3_0_c15_c13_2
+ 9f4: d518fd6f msr s3_0_c15_c13_3, x15
+ 9f8: d538fd6f mrs x15, s3_0_c15_c13_3
+ 9fc: d518fd8f msr s3_0_c15_c13_4, x15
+ a00: d538fd8f mrs x15, s3_0_c15_c13_4
+ a04: d518fdaf msr s3_0_c15_c13_5, x15
+ a08: d538fdaf mrs x15, s3_0_c15_c13_5
+ a0c: d518fdcf msr s3_0_c15_c13_6, x15
+ a10: d538fdcf mrs x15, s3_0_c15_c13_6
+ a14: d518fdef msr s3_0_c15_c13_7, x15
+ a18: d538fdef mrs x15, s3_0_c15_c13_7
+ a1c: d518fe0f msr s3_0_c15_c14_0, x15
+ a20: d538fe0f mrs x15, s3_0_c15_c14_0
+ a24: d518fe2f msr s3_0_c15_c14_1, x15
+ a28: d538fe2f mrs x15, s3_0_c15_c14_1
+ a2c: d518fe4f msr s3_0_c15_c14_2, x15
+ a30: d538fe4f mrs x15, s3_0_c15_c14_2
+ a34: d518fe6f msr s3_0_c15_c14_3, x15
+ a38: d538fe6f mrs x15, s3_0_c15_c14_3
+ a3c: d518fe8f msr s3_0_c15_c14_4, x15
+ a40: d538fe8f mrs x15, s3_0_c15_c14_4
+ a44: d518feaf msr s3_0_c15_c14_5, x15
+ a48: d538feaf mrs x15, s3_0_c15_c14_5
+ a4c: d518fecf msr s3_0_c15_c14_6, x15
+ a50: d538fecf mrs x15, s3_0_c15_c14_6
+ a54: d518feef msr s3_0_c15_c14_7, x15
+ a58: d538feef mrs x15, s3_0_c15_c14_7
+ a5c: d518ff0f msr s3_0_c15_c15_0, x15
+ a60: d538ff0f mrs x15, s3_0_c15_c15_0
+ a64: d518ff2f msr s3_0_c15_c15_1, x15
+ a68: d538ff2f mrs x15, s3_0_c15_c15_1
+ a6c: d518ff4f msr s3_0_c15_c15_2, x15
+ a70: d538ff4f mrs x15, s3_0_c15_c15_2
+ a74: d518ff6f msr s3_0_c15_c15_3, x15
+ a78: d538ff6f mrs x15, s3_0_c15_c15_3
+ a7c: d518ff8f msr s3_0_c15_c15_4, x15
+ a80: d538ff8f mrs x15, s3_0_c15_c15_4
+ a84: d518ffaf msr s3_0_c15_c15_5, x15
+ a88: d538ffaf mrs x15, s3_0_c15_c15_5
+ a8c: d518ffcf msr s3_0_c15_c15_6, x15
+ a90: d538ffcf mrs x15, s3_0_c15_c15_6
+ a94: d518ffef msr s3_0_c15_c15_7, x15
+ a98: d538ffef mrs x15, s3_0_c15_c15_7
+ a9c: d519b00f msr s3_1_c11_c0_0, x15
+ aa0: d539b00f mrs x15, s3_1_c11_c0_0
+ aa4: d519b02f msr s3_1_c11_c0_1, x15
+ aa8: d539b02f mrs x15, s3_1_c11_c0_1
+ aac: d519b04f msr s3_1_c11_c0_2, x15
+ ab0: d539b04f mrs x15, s3_1_c11_c0_2
+ ab4: d519b06f msr s3_1_c11_c0_3, x15
+ ab8: d539b06f mrs x15, s3_1_c11_c0_3
+ abc: d519b08f msr s3_1_c11_c0_4, x15
+ ac0: d539b08f mrs x15, s3_1_c11_c0_4
+ ac4: d519b0af msr s3_1_c11_c0_5, x15
+ ac8: d539b0af mrs x15, s3_1_c11_c0_5
+ acc: d519b0cf msr s3_1_c11_c0_6, x15
+ ad0: d539b0cf mrs x15, s3_1_c11_c0_6
+ ad4: d519b0ef msr s3_1_c11_c0_7, x15
+ ad8: d539b0ef mrs x15, s3_1_c11_c0_7
+ adc: d519b10f msr s3_1_c11_c1_0, x15
+ ae0: d539b10f mrs x15, s3_1_c11_c1_0
+ ae4: d519b12f msr s3_1_c11_c1_1, x15
+ ae8: d539b12f mrs x15, s3_1_c11_c1_1
+ aec: d519b14f msr s3_1_c11_c1_2, x15
+ af0: d539b14f mrs x15, s3_1_c11_c1_2
+ af4: d519b16f msr s3_1_c11_c1_3, x15
+ af8: d539b16f mrs x15, s3_1_c11_c1_3
+ afc: d519b18f msr s3_1_c11_c1_4, x15
+ b00: d539b18f mrs x15, s3_1_c11_c1_4
+ b04: d519b1af msr s3_1_c11_c1_5, x15
+ b08: d539b1af mrs x15, s3_1_c11_c1_5
+ b0c: d519b1cf msr s3_1_c11_c1_6, x15
+ b10: d539b1cf mrs x15, s3_1_c11_c1_6
+ b14: d519b1ef msr s3_1_c11_c1_7, x15
+ b18: d539b1ef mrs x15, s3_1_c11_c1_7
+ b1c: d519b20f msr s3_1_c11_c2_0, x15
+ b20: d539b20f mrs x15, s3_1_c11_c2_0
+ b24: d519b22f msr s3_1_c11_c2_1, x15
+ b28: d539b22f mrs x15, s3_1_c11_c2_1
+ b2c: d519b24f msr s3_1_c11_c2_2, x15
+ b30: d539b24f mrs x15, s3_1_c11_c2_2
+ b34: d519b26f msr s3_1_c11_c2_3, x15
+ b38: d539b26f mrs x15, s3_1_c11_c2_3
+ b3c: d519b28f msr s3_1_c11_c2_4, x15
+ b40: d539b28f mrs x15, s3_1_c11_c2_4
+ b44: d519b2af msr s3_1_c11_c2_5, x15
+ b48: d539b2af mrs x15, s3_1_c11_c2_5
+ b4c: d519b2cf msr s3_1_c11_c2_6, x15
+ b50: d539b2cf mrs x15, s3_1_c11_c2_6
+ b54: d519b2ef msr s3_1_c11_c2_7, x15
+ b58: d539b2ef mrs x15, s3_1_c11_c2_7
+ b5c: d519b30f msr s3_1_c11_c3_0, x15
+ b60: d539b30f mrs x15, s3_1_c11_c3_0
+ b64: d519b32f msr s3_1_c11_c3_1, x15
+ b68: d539b32f mrs x15, s3_1_c11_c3_1
+ b6c: d519b34f msr s3_1_c11_c3_2, x15
+ b70: d539b34f mrs x15, s3_1_c11_c3_2
+ b74: d519b36f msr s3_1_c11_c3_3, x15
+ b78: d539b36f mrs x15, s3_1_c11_c3_3
+ b7c: d519b38f msr s3_1_c11_c3_4, x15
+ b80: d539b38f mrs x15, s3_1_c11_c3_4
+ b84: d519b3af msr s3_1_c11_c3_5, x15
+ b88: d539b3af mrs x15, s3_1_c11_c3_5
+ b8c: d519b3cf msr s3_1_c11_c3_6, x15
+ b90: d539b3cf mrs x15, s3_1_c11_c3_6
+ b94: d519b3ef msr s3_1_c11_c3_7, x15
+ b98: d539b3ef mrs x15, s3_1_c11_c3_7
+ b9c: d519b40f msr s3_1_c11_c4_0, x15
+ ba0: d539b40f mrs x15, s3_1_c11_c4_0
+ ba4: d519b42f msr s3_1_c11_c4_1, x15
+ ba8: d539b42f mrs x15, s3_1_c11_c4_1
+ bac: d519b44f msr s3_1_c11_c4_2, x15
+ bb0: d539b44f mrs x15, s3_1_c11_c4_2
+ bb4: d519b46f msr s3_1_c11_c4_3, x15
+ bb8: d539b46f mrs x15, s3_1_c11_c4_3
+ bbc: d519b48f msr s3_1_c11_c4_4, x15
+ bc0: d539b48f mrs x15, s3_1_c11_c4_4
+ bc4: d519b4af msr s3_1_c11_c4_5, x15
+ bc8: d539b4af mrs x15, s3_1_c11_c4_5
+ bcc: d519b4cf msr s3_1_c11_c4_6, x15
+ bd0: d539b4cf mrs x15, s3_1_c11_c4_6
+ bd4: d519b4ef msr s3_1_c11_c4_7, x15
+ bd8: d539b4ef mrs x15, s3_1_c11_c4_7
+ bdc: d519b50f msr s3_1_c11_c5_0, x15
+ be0: d539b50f mrs x15, s3_1_c11_c5_0
+ be4: d519b52f msr s3_1_c11_c5_1, x15
+ be8: d539b52f mrs x15, s3_1_c11_c5_1
+ bec: d519b54f msr s3_1_c11_c5_2, x15
+ bf0: d539b54f mrs x15, s3_1_c11_c5_2
+ bf4: d519b56f msr s3_1_c11_c5_3, x15
+ bf8: d539b56f mrs x15, s3_1_c11_c5_3
+ bfc: d519b58f msr s3_1_c11_c5_4, x15
+ c00: d539b58f mrs x15, s3_1_c11_c5_4
+ c04: d519b5af msr s3_1_c11_c5_5, x15
+ c08: d539b5af mrs x15, s3_1_c11_c5_5
+ c0c: d519b5cf msr s3_1_c11_c5_6, x15
+ c10: d539b5cf mrs x15, s3_1_c11_c5_6
+ c14: d519b5ef msr s3_1_c11_c5_7, x15
+ c18: d539b5ef mrs x15, s3_1_c11_c5_7
+ c1c: d519b60f msr s3_1_c11_c6_0, x15
+ c20: d539b60f mrs x15, s3_1_c11_c6_0
+ c24: d519b62f msr s3_1_c11_c6_1, x15
+ c28: d539b62f mrs x15, s3_1_c11_c6_1
+ c2c: d519b64f msr s3_1_c11_c6_2, x15
+ c30: d539b64f mrs x15, s3_1_c11_c6_2
+ c34: d519b66f msr s3_1_c11_c6_3, x15
+ c38: d539b66f mrs x15, s3_1_c11_c6_3
+ c3c: d519b68f msr s3_1_c11_c6_4, x15
+ c40: d539b68f mrs x15, s3_1_c11_c6_4
+ c44: d519b6af msr s3_1_c11_c6_5, x15
+ c48: d539b6af mrs x15, s3_1_c11_c6_5
+ c4c: d519b6cf msr s3_1_c11_c6_6, x15
+ c50: d539b6cf mrs x15, s3_1_c11_c6_6
+ c54: d519b6ef msr s3_1_c11_c6_7, x15
+ c58: d539b6ef mrs x15, s3_1_c11_c6_7
+ c5c: d519b70f msr s3_1_c11_c7_0, x15
+ c60: d539b70f mrs x15, s3_1_c11_c7_0
+ c64: d519b72f msr s3_1_c11_c7_1, x15
+ c68: d539b72f mrs x15, s3_1_c11_c7_1
+ c6c: d519b74f msr s3_1_c11_c7_2, x15
+ c70: d539b74f mrs x15, s3_1_c11_c7_2
+ c74: d519b76f msr s3_1_c11_c7_3, x15
+ c78: d539b76f mrs x15, s3_1_c11_c7_3
+ c7c: d519b78f msr s3_1_c11_c7_4, x15
+ c80: d539b78f mrs x15, s3_1_c11_c7_4
+ c84: d519b7af msr s3_1_c11_c7_5, x15
+ c88: d539b7af mrs x15, s3_1_c11_c7_5
+ c8c: d519b7cf msr s3_1_c11_c7_6, x15
+ c90: d539b7cf mrs x15, s3_1_c11_c7_6
+ c94: d519b7ef msr s3_1_c11_c7_7, x15
+ c98: d539b7ef mrs x15, s3_1_c11_c7_7
+ c9c: d519b80f msr s3_1_c11_c8_0, x15
+ ca0: d539b80f mrs x15, s3_1_c11_c8_0
+ ca4: d519b82f msr s3_1_c11_c8_1, x15
+ ca8: d539b82f mrs x15, s3_1_c11_c8_1
+ cac: d519b84f msr s3_1_c11_c8_2, x15
+ cb0: d539b84f mrs x15, s3_1_c11_c8_2
+ cb4: d519b86f msr s3_1_c11_c8_3, x15
+ cb8: d539b86f mrs x15, s3_1_c11_c8_3
+ cbc: d519b88f msr s3_1_c11_c8_4, x15
+ cc0: d539b88f mrs x15, s3_1_c11_c8_4
+ cc4: d519b8af msr s3_1_c11_c8_5, x15
+ cc8: d539b8af mrs x15, s3_1_c11_c8_5
+ ccc: d519b8cf msr s3_1_c11_c8_6, x15
+ cd0: d539b8cf mrs x15, s3_1_c11_c8_6
+ cd4: d519b8ef msr s3_1_c11_c8_7, x15
+ cd8: d539b8ef mrs x15, s3_1_c11_c8_7
+ cdc: d519b90f msr s3_1_c11_c9_0, x15
+ ce0: d539b90f mrs x15, s3_1_c11_c9_0
+ ce4: d519b92f msr s3_1_c11_c9_1, x15
+ ce8: d539b92f mrs x15, s3_1_c11_c9_1
+ cec: d519b94f msr s3_1_c11_c9_2, x15
+ cf0: d539b94f mrs x15, s3_1_c11_c9_2
+ cf4: d519b96f msr s3_1_c11_c9_3, x15
+ cf8: d539b96f mrs x15, s3_1_c11_c9_3
+ cfc: d519b98f msr s3_1_c11_c9_4, x15
+ d00: d539b98f mrs x15, s3_1_c11_c9_4
+ d04: d519b9af msr s3_1_c11_c9_5, x15
+ d08: d539b9af mrs x15, s3_1_c11_c9_5
+ d0c: d519b9cf msr s3_1_c11_c9_6, x15
+ d10: d539b9cf mrs x15, s3_1_c11_c9_6
+ d14: d519b9ef msr s3_1_c11_c9_7, x15
+ d18: d539b9ef mrs x15, s3_1_c11_c9_7
+ d1c: d519ba0f msr s3_1_c11_c10_0, x15
+ d20: d539ba0f mrs x15, s3_1_c11_c10_0
+ d24: d519ba2f msr s3_1_c11_c10_1, x15
+ d28: d539ba2f mrs x15, s3_1_c11_c10_1
+ d2c: d519ba4f msr s3_1_c11_c10_2, x15
+ d30: d539ba4f mrs x15, s3_1_c11_c10_2
+ d34: d519ba6f msr s3_1_c11_c10_3, x15
+ d38: d539ba6f mrs x15, s3_1_c11_c10_3
+ d3c: d519ba8f msr s3_1_c11_c10_4, x15
+ d40: d539ba8f mrs x15, s3_1_c11_c10_4
+ d44: d519baaf msr s3_1_c11_c10_5, x15
+ d48: d539baaf mrs x15, s3_1_c11_c10_5
+ d4c: d519bacf msr s3_1_c11_c10_6, x15
+ d50: d539bacf mrs x15, s3_1_c11_c10_6
+ d54: d519baef msr s3_1_c11_c10_7, x15
+ d58: d539baef mrs x15, s3_1_c11_c10_7
+ d5c: d519bb0f msr s3_1_c11_c11_0, x15
+ d60: d539bb0f mrs x15, s3_1_c11_c11_0
+ d64: d519bb2f msr s3_1_c11_c11_1, x15
+ d68: d539bb2f mrs x15, s3_1_c11_c11_1
+ d6c: d519bb4f msr s3_1_c11_c11_2, x15
+ d70: d539bb4f mrs x15, s3_1_c11_c11_2
+ d74: d519bb6f msr s3_1_c11_c11_3, x15
+ d78: d539bb6f mrs x15, s3_1_c11_c11_3
+ d7c: d519bb8f msr s3_1_c11_c11_4, x15
+ d80: d539bb8f mrs x15, s3_1_c11_c11_4
+ d84: d519bbaf msr s3_1_c11_c11_5, x15
+ d88: d539bbaf mrs x15, s3_1_c11_c11_5
+ d8c: d519bbcf msr s3_1_c11_c11_6, x15
+ d90: d539bbcf mrs x15, s3_1_c11_c11_6
+ d94: d519bbef msr s3_1_c11_c11_7, x15
+ d98: d539bbef mrs x15, s3_1_c11_c11_7
+ d9c: d519bc0f msr s3_1_c11_c12_0, x15
+ da0: d539bc0f mrs x15, s3_1_c11_c12_0
+ da4: d519bc2f msr s3_1_c11_c12_1, x15
+ da8: d539bc2f mrs x15, s3_1_c11_c12_1
+ dac: d519bc4f msr s3_1_c11_c12_2, x15
+ db0: d539bc4f mrs x15, s3_1_c11_c12_2
+ db4: d519bc6f msr s3_1_c11_c12_3, x15
+ db8: d539bc6f mrs x15, s3_1_c11_c12_3
+ dbc: d519bc8f msr s3_1_c11_c12_4, x15
+ dc0: d539bc8f mrs x15, s3_1_c11_c12_4
+ dc4: d519bcaf msr s3_1_c11_c12_5, x15
+ dc8: d539bcaf mrs x15, s3_1_c11_c12_5
+ dcc: d519bccf msr s3_1_c11_c12_6, x15
+ dd0: d539bccf mrs x15, s3_1_c11_c12_6
+ dd4: d519bcef msr s3_1_c11_c12_7, x15
+ dd8: d539bcef mrs x15, s3_1_c11_c12_7
+ ddc: d519bd0f msr s3_1_c11_c13_0, x15
+ de0: d539bd0f mrs x15, s3_1_c11_c13_0
+ de4: d519bd2f msr s3_1_c11_c13_1, x15
+ de8: d539bd2f mrs x15, s3_1_c11_c13_1
+ dec: d519bd4f msr s3_1_c11_c13_2, x15
+ df0: d539bd4f mrs x15, s3_1_c11_c13_2
+ df4: d519bd6f msr s3_1_c11_c13_3, x15
+ df8: d539bd6f mrs x15, s3_1_c11_c13_3
+ dfc: d519bd8f msr s3_1_c11_c13_4, x15
+ e00: d539bd8f mrs x15, s3_1_c11_c13_4
+ e04: d519bdaf msr s3_1_c11_c13_5, x15
+ e08: d539bdaf mrs x15, s3_1_c11_c13_5
+ e0c: d519bdcf msr s3_1_c11_c13_6, x15
+ e10: d539bdcf mrs x15, s3_1_c11_c13_6
+ e14: d519bdef msr s3_1_c11_c13_7, x15
+ e18: d539bdef mrs x15, s3_1_c11_c13_7
+ e1c: d519be0f msr s3_1_c11_c14_0, x15
+ e20: d539be0f mrs x15, s3_1_c11_c14_0
+ e24: d519be2f msr s3_1_c11_c14_1, x15
+ e28: d539be2f mrs x15, s3_1_c11_c14_1
+ e2c: d519be4f msr s3_1_c11_c14_2, x15
+ e30: d539be4f mrs x15, s3_1_c11_c14_2
+ e34: d519be6f msr s3_1_c11_c14_3, x15
+ e38: d539be6f mrs x15, s3_1_c11_c14_3
+ e3c: d519be8f msr s3_1_c11_c14_4, x15
+ e40: d539be8f mrs x15, s3_1_c11_c14_4
+ e44: d519beaf msr s3_1_c11_c14_5, x15
+ e48: d539beaf mrs x15, s3_1_c11_c14_5
+ e4c: d519becf msr s3_1_c11_c14_6, x15
+ e50: d539becf mrs x15, s3_1_c11_c14_6
+ e54: d519beef msr s3_1_c11_c14_7, x15
+ e58: d539beef mrs x15, s3_1_c11_c14_7
+ e5c: d519bf0f msr s3_1_c11_c15_0, x15
+ e60: d539bf0f mrs x15, s3_1_c11_c15_0
+ e64: d519bf2f msr s3_1_c11_c15_1, x15
+ e68: d539bf2f mrs x15, s3_1_c11_c15_1
+ e6c: d519bf4f msr s3_1_c11_c15_2, x15
+ e70: d539bf4f mrs x15, s3_1_c11_c15_2
+ e74: d519bf6f msr s3_1_c11_c15_3, x15
+ e78: d539bf6f mrs x15, s3_1_c11_c15_3
+ e7c: d519bf8f msr s3_1_c11_c15_4, x15
+ e80: d539bf8f mrs x15, s3_1_c11_c15_4
+ e84: d519bfaf msr s3_1_c11_c15_5, x15
+ e88: d539bfaf mrs x15, s3_1_c11_c15_5
+ e8c: d519bfcf msr s3_1_c11_c15_6, x15
+ e90: d539bfcf mrs x15, s3_1_c11_c15_6
+ e94: d519bfef msr s3_1_c11_c15_7, x15
+ e98: d539bfef mrs x15, s3_1_c11_c15_7
+ e9c: d519f00f msr s3_1_c15_c0_0, x15
+ ea0: d539f00f mrs x15, s3_1_c15_c0_0
+ ea4: d519f02f msr s3_1_c15_c0_1, x15
+ ea8: d539f02f mrs x15, s3_1_c15_c0_1
+ eac: d519f04f msr s3_1_c15_c0_2, x15
+ eb0: d539f04f mrs x15, s3_1_c15_c0_2
+ eb4: d519f06f msr s3_1_c15_c0_3, x15
+ eb8: d539f06f mrs x15, s3_1_c15_c0_3
+ ebc: d519f08f msr s3_1_c15_c0_4, x15
+ ec0: d539f08f mrs x15, s3_1_c15_c0_4
+ ec4: d519f0af msr s3_1_c15_c0_5, x15
+ ec8: d539f0af mrs x15, s3_1_c15_c0_5
+ ecc: d519f0cf msr s3_1_c15_c0_6, x15
+ ed0: d539f0cf mrs x15, s3_1_c15_c0_6
+ ed4: d519f0ef msr s3_1_c15_c0_7, x15
+ ed8: d539f0ef mrs x15, s3_1_c15_c0_7
+ edc: d519f10f msr s3_1_c15_c1_0, x15
+ ee0: d539f10f mrs x15, s3_1_c15_c1_0
+ ee4: d519f12f msr s3_1_c15_c1_1, x15
+ ee8: d539f12f mrs x15, s3_1_c15_c1_1
+ eec: d519f14f msr s3_1_c15_c1_2, x15
+ ef0: d539f14f mrs x15, s3_1_c15_c1_2
+ ef4: d519f16f msr s3_1_c15_c1_3, x15
+ ef8: d539f16f mrs x15, s3_1_c15_c1_3
+ efc: d519f18f msr s3_1_c15_c1_4, x15
+ f00: d539f18f mrs x15, s3_1_c15_c1_4
+ f04: d519f1af msr s3_1_c15_c1_5, x15
+ f08: d539f1af mrs x15, s3_1_c15_c1_5
+ f0c: d519f1cf msr s3_1_c15_c1_6, x15
+ f10: d539f1cf mrs x15, s3_1_c15_c1_6
+ f14: d519f1ef msr s3_1_c15_c1_7, x15
+ f18: d539f1ef mrs x15, s3_1_c15_c1_7
+ f1c: d519f20f msr s3_1_c15_c2_0, x15
+ f20: d539f20f mrs x15, s3_1_c15_c2_0
+ f24: d519f22f msr s3_1_c15_c2_1, x15
+ f28: d539f22f mrs x15, s3_1_c15_c2_1
+ f2c: d519f24f msr s3_1_c15_c2_2, x15
+ f30: d539f24f mrs x15, s3_1_c15_c2_2
+ f34: d519f26f msr s3_1_c15_c2_3, x15
+ f38: d539f26f mrs x15, s3_1_c15_c2_3
+ f3c: d519f28f msr s3_1_c15_c2_4, x15
+ f40: d539f28f mrs x15, s3_1_c15_c2_4
+ f44: d519f2af msr s3_1_c15_c2_5, x15
+ f48: d539f2af mrs x15, s3_1_c15_c2_5
+ f4c: d519f2cf msr s3_1_c15_c2_6, x15
+ f50: d539f2cf mrs x15, s3_1_c15_c2_6
+ f54: d519f2ef msr s3_1_c15_c2_7, x15
+ f58: d539f2ef mrs x15, s3_1_c15_c2_7
+ f5c: d519f30f msr s3_1_c15_c3_0, x15
+ f60: d539f30f mrs x15, s3_1_c15_c3_0
+ f64: d519f32f msr s3_1_c15_c3_1, x15
+ f68: d539f32f mrs x15, s3_1_c15_c3_1
+ f6c: d519f34f msr s3_1_c15_c3_2, x15
+ f70: d539f34f mrs x15, s3_1_c15_c3_2
+ f74: d519f36f msr s3_1_c15_c3_3, x15
+ f78: d539f36f mrs x15, s3_1_c15_c3_3
+ f7c: d519f38f msr s3_1_c15_c3_4, x15
+ f80: d539f38f mrs x15, s3_1_c15_c3_4
+ f84: d519f3af msr s3_1_c15_c3_5, x15
+ f88: d539f3af mrs x15, s3_1_c15_c3_5
+ f8c: d519f3cf msr s3_1_c15_c3_6, x15
+ f90: d539f3cf mrs x15, s3_1_c15_c3_6
+ f94: d519f3ef msr s3_1_c15_c3_7, x15
+ f98: d539f3ef mrs x15, s3_1_c15_c3_7
+ f9c: d519f40f msr s3_1_c15_c4_0, x15
+ fa0: d539f40f mrs x15, s3_1_c15_c4_0
+ fa4: d519f42f msr s3_1_c15_c4_1, x15
+ fa8: d539f42f mrs x15, s3_1_c15_c4_1
+ fac: d519f44f msr s3_1_c15_c4_2, x15
+ fb0: d539f44f mrs x15, s3_1_c15_c4_2
+ fb4: d519f46f msr s3_1_c15_c4_3, x15
+ fb8: d539f46f mrs x15, s3_1_c15_c4_3
+ fbc: d519f48f msr s3_1_c15_c4_4, x15
+ fc0: d539f48f mrs x15, s3_1_c15_c4_4
+ fc4: d519f4af msr s3_1_c15_c4_5, x15
+ fc8: d539f4af mrs x15, s3_1_c15_c4_5
+ fcc: d519f4cf msr s3_1_c15_c4_6, x15
+ fd0: d539f4cf mrs x15, s3_1_c15_c4_6
+ fd4: d519f4ef msr s3_1_c15_c4_7, x15
+ fd8: d539f4ef mrs x15, s3_1_c15_c4_7
+ fdc: d519f50f msr s3_1_c15_c5_0, x15
+ fe0: d539f50f mrs x15, s3_1_c15_c5_0
+ fe4: d519f52f msr s3_1_c15_c5_1, x15
+ fe8: d539f52f mrs x15, s3_1_c15_c5_1
+ fec: d519f54f msr s3_1_c15_c5_2, x15
+ ff0: d539f54f mrs x15, s3_1_c15_c5_2
+ ff4: d519f56f msr s3_1_c15_c5_3, x15
+ ff8: d539f56f mrs x15, s3_1_c15_c5_3
+ ffc: d519f58f msr s3_1_c15_c5_4, x15
+ 1000: d539f58f mrs x15, s3_1_c15_c5_4
+ 1004: d519f5af msr s3_1_c15_c5_5, x15
+ 1008: d539f5af mrs x15, s3_1_c15_c5_5
+ 100c: d519f5cf msr s3_1_c15_c5_6, x15
+ 1010: d539f5cf mrs x15, s3_1_c15_c5_6
+ 1014: d519f5ef msr s3_1_c15_c5_7, x15
+ 1018: d539f5ef mrs x15, s3_1_c15_c5_7
+ 101c: d519f60f msr s3_1_c15_c6_0, x15
+ 1020: d539f60f mrs x15, s3_1_c15_c6_0
+ 1024: d519f62f msr s3_1_c15_c6_1, x15
+ 1028: d539f62f mrs x15, s3_1_c15_c6_1
+ 102c: d519f64f msr s3_1_c15_c6_2, x15
+ 1030: d539f64f mrs x15, s3_1_c15_c6_2
+ 1034: d519f66f msr s3_1_c15_c6_3, x15
+ 1038: d539f66f mrs x15, s3_1_c15_c6_3
+ 103c: d519f68f msr s3_1_c15_c6_4, x15
+ 1040: d539f68f mrs x15, s3_1_c15_c6_4
+ 1044: d519f6af msr s3_1_c15_c6_5, x15
+ 1048: d539f6af mrs x15, s3_1_c15_c6_5
+ 104c: d519f6cf msr s3_1_c15_c6_6, x15
+ 1050: d539f6cf mrs x15, s3_1_c15_c6_6
+ 1054: d519f6ef msr s3_1_c15_c6_7, x15
+ 1058: d539f6ef mrs x15, s3_1_c15_c6_7
+ 105c: d519f70f msr s3_1_c15_c7_0, x15
+ 1060: d539f70f mrs x15, s3_1_c15_c7_0
+ 1064: d519f72f msr s3_1_c15_c7_1, x15
+ 1068: d539f72f mrs x15, s3_1_c15_c7_1
+ 106c: d519f74f msr s3_1_c15_c7_2, x15
+ 1070: d539f74f mrs x15, s3_1_c15_c7_2
+ 1074: d519f76f msr s3_1_c15_c7_3, x15
+ 1078: d539f76f mrs x15, s3_1_c15_c7_3
+ 107c: d519f78f msr s3_1_c15_c7_4, x15
+ 1080: d539f78f mrs x15, s3_1_c15_c7_4
+ 1084: d519f7af msr s3_1_c15_c7_5, x15
+ 1088: d539f7af mrs x15, s3_1_c15_c7_5
+ 108c: d519f7cf msr s3_1_c15_c7_6, x15
+ 1090: d539f7cf mrs x15, s3_1_c15_c7_6
+ 1094: d519f7ef msr s3_1_c15_c7_7, x15
+ 1098: d539f7ef mrs x15, s3_1_c15_c7_7
+ 109c: d519f80f msr s3_1_c15_c8_0, x15
+ 10a0: d539f80f mrs x15, s3_1_c15_c8_0
+ 10a4: d519f82f msr s3_1_c15_c8_1, x15
+ 10a8: d539f82f mrs x15, s3_1_c15_c8_1
+ 10ac: d519f84f msr s3_1_c15_c8_2, x15
+ 10b0: d539f84f mrs x15, s3_1_c15_c8_2
+ 10b4: d519f86f msr s3_1_c15_c8_3, x15
+ 10b8: d539f86f mrs x15, s3_1_c15_c8_3
+ 10bc: d519f88f msr s3_1_c15_c8_4, x15
+ 10c0: d539f88f mrs x15, s3_1_c15_c8_4
+ 10c4: d519f8af msr s3_1_c15_c8_5, x15
+ 10c8: d539f8af mrs x15, s3_1_c15_c8_5
+ 10cc: d519f8cf msr s3_1_c15_c8_6, x15
+ 10d0: d539f8cf mrs x15, s3_1_c15_c8_6
+ 10d4: d519f8ef msr s3_1_c15_c8_7, x15
+ 10d8: d539f8ef mrs x15, s3_1_c15_c8_7
+ 10dc: d519f90f msr s3_1_c15_c9_0, x15
+ 10e0: d539f90f mrs x15, s3_1_c15_c9_0
+ 10e4: d519f92f msr s3_1_c15_c9_1, x15
+ 10e8: d539f92f mrs x15, s3_1_c15_c9_1
+ 10ec: d519f94f msr s3_1_c15_c9_2, x15
+ 10f0: d539f94f mrs x15, s3_1_c15_c9_2
+ 10f4: d519f96f msr s3_1_c15_c9_3, x15
+ 10f8: d539f96f mrs x15, s3_1_c15_c9_3
+ 10fc: d519f98f msr s3_1_c15_c9_4, x15
+ 1100: d539f98f mrs x15, s3_1_c15_c9_4
+ 1104: d519f9af msr s3_1_c15_c9_5, x15
+ 1108: d539f9af mrs x15, s3_1_c15_c9_5
+ 110c: d519f9cf msr s3_1_c15_c9_6, x15
+ 1110: d539f9cf mrs x15, s3_1_c15_c9_6
+ 1114: d519f9ef msr s3_1_c15_c9_7, x15
+ 1118: d539f9ef mrs x15, s3_1_c15_c9_7
+ 111c: d519fa0f msr s3_1_c15_c10_0, x15
+ 1120: d539fa0f mrs x15, s3_1_c15_c10_0
+ 1124: d519fa2f msr s3_1_c15_c10_1, x15
+ 1128: d539fa2f mrs x15, s3_1_c15_c10_1
+ 112c: d519fa4f msr s3_1_c15_c10_2, x15
+ 1130: d539fa4f mrs x15, s3_1_c15_c10_2
+ 1134: d519fa6f msr s3_1_c15_c10_3, x15
+ 1138: d539fa6f mrs x15, s3_1_c15_c10_3
+ 113c: d519fa8f msr s3_1_c15_c10_4, x15
+ 1140: d539fa8f mrs x15, s3_1_c15_c10_4
+ 1144: d519faaf msr s3_1_c15_c10_5, x15
+ 1148: d539faaf mrs x15, s3_1_c15_c10_5
+ 114c: d519facf msr s3_1_c15_c10_6, x15
+ 1150: d539facf mrs x15, s3_1_c15_c10_6
+ 1154: d519faef msr s3_1_c15_c10_7, x15
+ 1158: d539faef mrs x15, s3_1_c15_c10_7
+ 115c: d519fb0f msr s3_1_c15_c11_0, x15
+ 1160: d539fb0f mrs x15, s3_1_c15_c11_0
+ 1164: d519fb2f msr s3_1_c15_c11_1, x15
+ 1168: d539fb2f mrs x15, s3_1_c15_c11_1
+ 116c: d519fb4f msr s3_1_c15_c11_2, x15
+ 1170: d539fb4f mrs x15, s3_1_c15_c11_2
+ 1174: d519fb6f msr s3_1_c15_c11_3, x15
+ 1178: d539fb6f mrs x15, s3_1_c15_c11_3
+ 117c: d519fb8f msr s3_1_c15_c11_4, x15
+ 1180: d539fb8f mrs x15, s3_1_c15_c11_4
+ 1184: d519fbaf msr s3_1_c15_c11_5, x15
+ 1188: d539fbaf mrs x15, s3_1_c15_c11_5
+ 118c: d519fbcf msr s3_1_c15_c11_6, x15
+ 1190: d539fbcf mrs x15, s3_1_c15_c11_6
+ 1194: d519fbef msr s3_1_c15_c11_7, x15
+ 1198: d539fbef mrs x15, s3_1_c15_c11_7
+ 119c: d519fc0f msr s3_1_c15_c12_0, x15
+ 11a0: d539fc0f mrs x15, s3_1_c15_c12_0
+ 11a4: d519fc2f msr s3_1_c15_c12_1, x15
+ 11a8: d539fc2f mrs x15, s3_1_c15_c12_1
+ 11ac: d519fc4f msr s3_1_c15_c12_2, x15
+ 11b0: d539fc4f mrs x15, s3_1_c15_c12_2
+ 11b4: d519fc6f msr s3_1_c15_c12_3, x15
+ 11b8: d539fc6f mrs x15, s3_1_c15_c12_3
+ 11bc: d519fc8f msr s3_1_c15_c12_4, x15
+ 11c0: d539fc8f mrs x15, s3_1_c15_c12_4
+ 11c4: d519fcaf msr s3_1_c15_c12_5, x15
+ 11c8: d539fcaf mrs x15, s3_1_c15_c12_5
+ 11cc: d519fccf msr s3_1_c15_c12_6, x15
+ 11d0: d539fccf mrs x15, s3_1_c15_c12_6
+ 11d4: d519fcef msr s3_1_c15_c12_7, x15
+ 11d8: d539fcef mrs x15, s3_1_c15_c12_7
+ 11dc: d519fd0f msr s3_1_c15_c13_0, x15
+ 11e0: d539fd0f mrs x15, s3_1_c15_c13_0
+ 11e4: d519fd2f msr s3_1_c15_c13_1, x15
+ 11e8: d539fd2f mrs x15, s3_1_c15_c13_1
+ 11ec: d519fd4f msr s3_1_c15_c13_2, x15
+ 11f0: d539fd4f mrs x15, s3_1_c15_c13_2
+ 11f4: d519fd6f msr s3_1_c15_c13_3, x15
+ 11f8: d539fd6f mrs x15, s3_1_c15_c13_3
+ 11fc: d519fd8f msr s3_1_c15_c13_4, x15
+ 1200: d539fd8f mrs x15, s3_1_c15_c13_4
+ 1204: d519fdaf msr s3_1_c15_c13_5, x15
+ 1208: d539fdaf mrs x15, s3_1_c15_c13_5
+ 120c: d519fdcf msr s3_1_c15_c13_6, x15
+ 1210: d539fdcf mrs x15, s3_1_c15_c13_6
+ 1214: d519fdef msr s3_1_c15_c13_7, x15
+ 1218: d539fdef mrs x15, s3_1_c15_c13_7
+ 121c: d519fe0f msr s3_1_c15_c14_0, x15
+ 1220: d539fe0f mrs x15, s3_1_c15_c14_0
+ 1224: d519fe2f msr s3_1_c15_c14_1, x15
+ 1228: d539fe2f mrs x15, s3_1_c15_c14_1
+ 122c: d519fe4f msr s3_1_c15_c14_2, x15
+ 1230: d539fe4f mrs x15, s3_1_c15_c14_2
+ 1234: d519fe6f msr s3_1_c15_c14_3, x15
+ 1238: d539fe6f mrs x15, s3_1_c15_c14_3
+ 123c: d519fe8f msr s3_1_c15_c14_4, x15
+ 1240: d539fe8f mrs x15, s3_1_c15_c14_4
+ 1244: d519feaf msr s3_1_c15_c14_5, x15
+ 1248: d539feaf mrs x15, s3_1_c15_c14_5
+ 124c: d519fecf msr s3_1_c15_c14_6, x15
+ 1250: d539fecf mrs x15, s3_1_c15_c14_6
+ 1254: d519feef msr s3_1_c15_c14_7, x15
+ 1258: d539feef mrs x15, s3_1_c15_c14_7
+ 125c: d519ff0f msr s3_1_c15_c15_0, x15
+ 1260: d539ff0f mrs x15, s3_1_c15_c15_0
+ 1264: d519ff2f msr s3_1_c15_c15_1, x15
+ 1268: d539ff2f mrs x15, s3_1_c15_c15_1
+ 126c: d519ff4f msr s3_1_c15_c15_2, x15
+ 1270: d539ff4f mrs x15, s3_1_c15_c15_2
+ 1274: d519ff6f msr s3_1_c15_c15_3, x15
+ 1278: d539ff6f mrs x15, s3_1_c15_c15_3
+ 127c: d519ff8f msr s3_1_c15_c15_4, x15
+ 1280: d539ff8f mrs x15, s3_1_c15_c15_4
+ 1284: d519ffaf msr s3_1_c15_c15_5, x15
+ 1288: d539ffaf mrs x15, s3_1_c15_c15_5
+ 128c: d519ffcf msr s3_1_c15_c15_6, x15
+ 1290: d539ffcf mrs x15, s3_1_c15_c15_6
+ 1294: d519ffef msr s3_1_c15_c15_7, x15
+ 1298: d539ffef mrs x15, s3_1_c15_c15_7
+ 129c: d51ab00f msr s3_2_c11_c0_0, x15
+ 12a0: d53ab00f mrs x15, s3_2_c11_c0_0
+ 12a4: d51ab02f msr s3_2_c11_c0_1, x15
+ 12a8: d53ab02f mrs x15, s3_2_c11_c0_1
+ 12ac: d51ab04f msr s3_2_c11_c0_2, x15
+ 12b0: d53ab04f mrs x15, s3_2_c11_c0_2
+ 12b4: d51ab06f msr s3_2_c11_c0_3, x15
+ 12b8: d53ab06f mrs x15, s3_2_c11_c0_3
+ 12bc: d51ab08f msr s3_2_c11_c0_4, x15
+ 12c0: d53ab08f mrs x15, s3_2_c11_c0_4
+ 12c4: d51ab0af msr s3_2_c11_c0_5, x15
+ 12c8: d53ab0af mrs x15, s3_2_c11_c0_5
+ 12cc: d51ab0cf msr s3_2_c11_c0_6, x15
+ 12d0: d53ab0cf mrs x15, s3_2_c11_c0_6
+ 12d4: d51ab0ef msr s3_2_c11_c0_7, x15
+ 12d8: d53ab0ef mrs x15, s3_2_c11_c0_7
+ 12dc: d51ab10f msr s3_2_c11_c1_0, x15
+ 12e0: d53ab10f mrs x15, s3_2_c11_c1_0
+ 12e4: d51ab12f msr s3_2_c11_c1_1, x15
+ 12e8: d53ab12f mrs x15, s3_2_c11_c1_1
+ 12ec: d51ab14f msr s3_2_c11_c1_2, x15
+ 12f0: d53ab14f mrs x15, s3_2_c11_c1_2
+ 12f4: d51ab16f msr s3_2_c11_c1_3, x15
+ 12f8: d53ab16f mrs x15, s3_2_c11_c1_3
+ 12fc: d51ab18f msr s3_2_c11_c1_4, x15
+ 1300: d53ab18f mrs x15, s3_2_c11_c1_4
+ 1304: d51ab1af msr s3_2_c11_c1_5, x15
+ 1308: d53ab1af mrs x15, s3_2_c11_c1_5
+ 130c: d51ab1cf msr s3_2_c11_c1_6, x15
+ 1310: d53ab1cf mrs x15, s3_2_c11_c1_6
+ 1314: d51ab1ef msr s3_2_c11_c1_7, x15
+ 1318: d53ab1ef mrs x15, s3_2_c11_c1_7
+ 131c: d51ab20f msr s3_2_c11_c2_0, x15
+ 1320: d53ab20f mrs x15, s3_2_c11_c2_0
+ 1324: d51ab22f msr s3_2_c11_c2_1, x15
+ 1328: d53ab22f mrs x15, s3_2_c11_c2_1
+ 132c: d51ab24f msr s3_2_c11_c2_2, x15
+ 1330: d53ab24f mrs x15, s3_2_c11_c2_2
+ 1334: d51ab26f msr s3_2_c11_c2_3, x15
+ 1338: d53ab26f mrs x15, s3_2_c11_c2_3
+ 133c: d51ab28f msr s3_2_c11_c2_4, x15
+ 1340: d53ab28f mrs x15, s3_2_c11_c2_4
+ 1344: d51ab2af msr s3_2_c11_c2_5, x15
+ 1348: d53ab2af mrs x15, s3_2_c11_c2_5
+ 134c: d51ab2cf msr s3_2_c11_c2_6, x15
+ 1350: d53ab2cf mrs x15, s3_2_c11_c2_6
+ 1354: d51ab2ef msr s3_2_c11_c2_7, x15
+ 1358: d53ab2ef mrs x15, s3_2_c11_c2_7
+ 135c: d51ab30f msr s3_2_c11_c3_0, x15
+ 1360: d53ab30f mrs x15, s3_2_c11_c3_0
+ 1364: d51ab32f msr s3_2_c11_c3_1, x15
+ 1368: d53ab32f mrs x15, s3_2_c11_c3_1
+ 136c: d51ab34f msr s3_2_c11_c3_2, x15
+ 1370: d53ab34f mrs x15, s3_2_c11_c3_2
+ 1374: d51ab36f msr s3_2_c11_c3_3, x15
+ 1378: d53ab36f mrs x15, s3_2_c11_c3_3
+ 137c: d51ab38f msr s3_2_c11_c3_4, x15
+ 1380: d53ab38f mrs x15, s3_2_c11_c3_4
+ 1384: d51ab3af msr s3_2_c11_c3_5, x15
+ 1388: d53ab3af mrs x15, s3_2_c11_c3_5
+ 138c: d51ab3cf msr s3_2_c11_c3_6, x15
+ 1390: d53ab3cf mrs x15, s3_2_c11_c3_6
+ 1394: d51ab3ef msr s3_2_c11_c3_7, x15
+ 1398: d53ab3ef mrs x15, s3_2_c11_c3_7
+ 139c: d51ab40f msr s3_2_c11_c4_0, x15
+ 13a0: d53ab40f mrs x15, s3_2_c11_c4_0
+ 13a4: d51ab42f msr s3_2_c11_c4_1, x15
+ 13a8: d53ab42f mrs x15, s3_2_c11_c4_1
+ 13ac: d51ab44f msr s3_2_c11_c4_2, x15
+ 13b0: d53ab44f mrs x15, s3_2_c11_c4_2
+ 13b4: d51ab46f msr s3_2_c11_c4_3, x15
+ 13b8: d53ab46f mrs x15, s3_2_c11_c4_3
+ 13bc: d51ab48f msr s3_2_c11_c4_4, x15
+ 13c0: d53ab48f mrs x15, s3_2_c11_c4_4
+ 13c4: d51ab4af msr s3_2_c11_c4_5, x15
+ 13c8: d53ab4af mrs x15, s3_2_c11_c4_5
+ 13cc: d51ab4cf msr s3_2_c11_c4_6, x15
+ 13d0: d53ab4cf mrs x15, s3_2_c11_c4_6
+ 13d4: d51ab4ef msr s3_2_c11_c4_7, x15
+ 13d8: d53ab4ef mrs x15, s3_2_c11_c4_7
+ 13dc: d51ab50f msr s3_2_c11_c5_0, x15
+ 13e0: d53ab50f mrs x15, s3_2_c11_c5_0
+ 13e4: d51ab52f msr s3_2_c11_c5_1, x15
+ 13e8: d53ab52f mrs x15, s3_2_c11_c5_1
+ 13ec: d51ab54f msr s3_2_c11_c5_2, x15
+ 13f0: d53ab54f mrs x15, s3_2_c11_c5_2
+ 13f4: d51ab56f msr s3_2_c11_c5_3, x15
+ 13f8: d53ab56f mrs x15, s3_2_c11_c5_3
+ 13fc: d51ab58f msr s3_2_c11_c5_4, x15
+ 1400: d53ab58f mrs x15, s3_2_c11_c5_4
+ 1404: d51ab5af msr s3_2_c11_c5_5, x15
+ 1408: d53ab5af mrs x15, s3_2_c11_c5_5
+ 140c: d51ab5cf msr s3_2_c11_c5_6, x15
+ 1410: d53ab5cf mrs x15, s3_2_c11_c5_6
+ 1414: d51ab5ef msr s3_2_c11_c5_7, x15
+ 1418: d53ab5ef mrs x15, s3_2_c11_c5_7
+ 141c: d51ab60f msr s3_2_c11_c6_0, x15
+ 1420: d53ab60f mrs x15, s3_2_c11_c6_0
+ 1424: d51ab62f msr s3_2_c11_c6_1, x15
+ 1428: d53ab62f mrs x15, s3_2_c11_c6_1
+ 142c: d51ab64f msr s3_2_c11_c6_2, x15
+ 1430: d53ab64f mrs x15, s3_2_c11_c6_2
+ 1434: d51ab66f msr s3_2_c11_c6_3, x15
+ 1438: d53ab66f mrs x15, s3_2_c11_c6_3
+ 143c: d51ab68f msr s3_2_c11_c6_4, x15
+ 1440: d53ab68f mrs x15, s3_2_c11_c6_4
+ 1444: d51ab6af msr s3_2_c11_c6_5, x15
+ 1448: d53ab6af mrs x15, s3_2_c11_c6_5
+ 144c: d51ab6cf msr s3_2_c11_c6_6, x15
+ 1450: d53ab6cf mrs x15, s3_2_c11_c6_6
+ 1454: d51ab6ef msr s3_2_c11_c6_7, x15
+ 1458: d53ab6ef mrs x15, s3_2_c11_c6_7
+ 145c: d51ab70f msr s3_2_c11_c7_0, x15
+ 1460: d53ab70f mrs x15, s3_2_c11_c7_0
+ 1464: d51ab72f msr s3_2_c11_c7_1, x15
+ 1468: d53ab72f mrs x15, s3_2_c11_c7_1
+ 146c: d51ab74f msr s3_2_c11_c7_2, x15
+ 1470: d53ab74f mrs x15, s3_2_c11_c7_2
+ 1474: d51ab76f msr s3_2_c11_c7_3, x15
+ 1478: d53ab76f mrs x15, s3_2_c11_c7_3
+ 147c: d51ab78f msr s3_2_c11_c7_4, x15
+ 1480: d53ab78f mrs x15, s3_2_c11_c7_4
+ 1484: d51ab7af msr s3_2_c11_c7_5, x15
+ 1488: d53ab7af mrs x15, s3_2_c11_c7_5
+ 148c: d51ab7cf msr s3_2_c11_c7_6, x15
+ 1490: d53ab7cf mrs x15, s3_2_c11_c7_6
+ 1494: d51ab7ef msr s3_2_c11_c7_7, x15
+ 1498: d53ab7ef mrs x15, s3_2_c11_c7_7
+ 149c: d51ab80f msr s3_2_c11_c8_0, x15
+ 14a0: d53ab80f mrs x15, s3_2_c11_c8_0
+ 14a4: d51ab82f msr s3_2_c11_c8_1, x15
+ 14a8: d53ab82f mrs x15, s3_2_c11_c8_1
+ 14ac: d51ab84f msr s3_2_c11_c8_2, x15
+ 14b0: d53ab84f mrs x15, s3_2_c11_c8_2
+ 14b4: d51ab86f msr s3_2_c11_c8_3, x15
+ 14b8: d53ab86f mrs x15, s3_2_c11_c8_3
+ 14bc: d51ab88f msr s3_2_c11_c8_4, x15
+ 14c0: d53ab88f mrs x15, s3_2_c11_c8_4
+ 14c4: d51ab8af msr s3_2_c11_c8_5, x15
+ 14c8: d53ab8af mrs x15, s3_2_c11_c8_5
+ 14cc: d51ab8cf msr s3_2_c11_c8_6, x15
+ 14d0: d53ab8cf mrs x15, s3_2_c11_c8_6
+ 14d4: d51ab8ef msr s3_2_c11_c8_7, x15
+ 14d8: d53ab8ef mrs x15, s3_2_c11_c8_7
+ 14dc: d51ab90f msr s3_2_c11_c9_0, x15
+ 14e0: d53ab90f mrs x15, s3_2_c11_c9_0
+ 14e4: d51ab92f msr s3_2_c11_c9_1, x15
+ 14e8: d53ab92f mrs x15, s3_2_c11_c9_1
+ 14ec: d51ab94f msr s3_2_c11_c9_2, x15
+ 14f0: d53ab94f mrs x15, s3_2_c11_c9_2
+ 14f4: d51ab96f msr s3_2_c11_c9_3, x15
+ 14f8: d53ab96f mrs x15, s3_2_c11_c9_3
+ 14fc: d51ab98f msr s3_2_c11_c9_4, x15
+ 1500: d53ab98f mrs x15, s3_2_c11_c9_4
+ 1504: d51ab9af msr s3_2_c11_c9_5, x15
+ 1508: d53ab9af mrs x15, s3_2_c11_c9_5
+ 150c: d51ab9cf msr s3_2_c11_c9_6, x15
+ 1510: d53ab9cf mrs x15, s3_2_c11_c9_6
+ 1514: d51ab9ef msr s3_2_c11_c9_7, x15
+ 1518: d53ab9ef mrs x15, s3_2_c11_c9_7
+ 151c: d51aba0f msr s3_2_c11_c10_0, x15
+ 1520: d53aba0f mrs x15, s3_2_c11_c10_0
+ 1524: d51aba2f msr s3_2_c11_c10_1, x15
+ 1528: d53aba2f mrs x15, s3_2_c11_c10_1
+ 152c: d51aba4f msr s3_2_c11_c10_2, x15
+ 1530: d53aba4f mrs x15, s3_2_c11_c10_2
+ 1534: d51aba6f msr s3_2_c11_c10_3, x15
+ 1538: d53aba6f mrs x15, s3_2_c11_c10_3
+ 153c: d51aba8f msr s3_2_c11_c10_4, x15
+ 1540: d53aba8f mrs x15, s3_2_c11_c10_4
+ 1544: d51abaaf msr s3_2_c11_c10_5, x15
+ 1548: d53abaaf mrs x15, s3_2_c11_c10_5
+ 154c: d51abacf msr s3_2_c11_c10_6, x15
+ 1550: d53abacf mrs x15, s3_2_c11_c10_6
+ 1554: d51abaef msr s3_2_c11_c10_7, x15
+ 1558: d53abaef mrs x15, s3_2_c11_c10_7
+ 155c: d51abb0f msr s3_2_c11_c11_0, x15
+ 1560: d53abb0f mrs x15, s3_2_c11_c11_0
+ 1564: d51abb2f msr s3_2_c11_c11_1, x15
+ 1568: d53abb2f mrs x15, s3_2_c11_c11_1
+ 156c: d51abb4f msr s3_2_c11_c11_2, x15
+ 1570: d53abb4f mrs x15, s3_2_c11_c11_2
+ 1574: d51abb6f msr s3_2_c11_c11_3, x15
+ 1578: d53abb6f mrs x15, s3_2_c11_c11_3
+ 157c: d51abb8f msr s3_2_c11_c11_4, x15
+ 1580: d53abb8f mrs x15, s3_2_c11_c11_4
+ 1584: d51abbaf msr s3_2_c11_c11_5, x15
+ 1588: d53abbaf mrs x15, s3_2_c11_c11_5
+ 158c: d51abbcf msr s3_2_c11_c11_6, x15
+ 1590: d53abbcf mrs x15, s3_2_c11_c11_6
+ 1594: d51abbef msr s3_2_c11_c11_7, x15
+ 1598: d53abbef mrs x15, s3_2_c11_c11_7
+ 159c: d51abc0f msr s3_2_c11_c12_0, x15
+ 15a0: d53abc0f mrs x15, s3_2_c11_c12_0
+ 15a4: d51abc2f msr s3_2_c11_c12_1, x15
+ 15a8: d53abc2f mrs x15, s3_2_c11_c12_1
+ 15ac: d51abc4f msr s3_2_c11_c12_2, x15
+ 15b0: d53abc4f mrs x15, s3_2_c11_c12_2
+ 15b4: d51abc6f msr s3_2_c11_c12_3, x15
+ 15b8: d53abc6f mrs x15, s3_2_c11_c12_3
+ 15bc: d51abc8f msr s3_2_c11_c12_4, x15
+ 15c0: d53abc8f mrs x15, s3_2_c11_c12_4
+ 15c4: d51abcaf msr s3_2_c11_c12_5, x15
+ 15c8: d53abcaf mrs x15, s3_2_c11_c12_5
+ 15cc: d51abccf msr s3_2_c11_c12_6, x15
+ 15d0: d53abccf mrs x15, s3_2_c11_c12_6
+ 15d4: d51abcef msr s3_2_c11_c12_7, x15
+ 15d8: d53abcef mrs x15, s3_2_c11_c12_7
+ 15dc: d51abd0f msr s3_2_c11_c13_0, x15
+ 15e0: d53abd0f mrs x15, s3_2_c11_c13_0
+ 15e4: d51abd2f msr s3_2_c11_c13_1, x15
+ 15e8: d53abd2f mrs x15, s3_2_c11_c13_1
+ 15ec: d51abd4f msr s3_2_c11_c13_2, x15
+ 15f0: d53abd4f mrs x15, s3_2_c11_c13_2
+ 15f4: d51abd6f msr s3_2_c11_c13_3, x15
+ 15f8: d53abd6f mrs x15, s3_2_c11_c13_3
+ 15fc: d51abd8f msr s3_2_c11_c13_4, x15
+ 1600: d53abd8f mrs x15, s3_2_c11_c13_4
+ 1604: d51abdaf msr s3_2_c11_c13_5, x15
+ 1608: d53abdaf mrs x15, s3_2_c11_c13_5
+ 160c: d51abdcf msr s3_2_c11_c13_6, x15
+ 1610: d53abdcf mrs x15, s3_2_c11_c13_6
+ 1614: d51abdef msr s3_2_c11_c13_7, x15
+ 1618: d53abdef mrs x15, s3_2_c11_c13_7
+ 161c: d51abe0f msr s3_2_c11_c14_0, x15
+ 1620: d53abe0f mrs x15, s3_2_c11_c14_0
+ 1624: d51abe2f msr s3_2_c11_c14_1, x15
+ 1628: d53abe2f mrs x15, s3_2_c11_c14_1
+ 162c: d51abe4f msr s3_2_c11_c14_2, x15
+ 1630: d53abe4f mrs x15, s3_2_c11_c14_2
+ 1634: d51abe6f msr s3_2_c11_c14_3, x15
+ 1638: d53abe6f mrs x15, s3_2_c11_c14_3
+ 163c: d51abe8f msr s3_2_c11_c14_4, x15
+ 1640: d53abe8f mrs x15, s3_2_c11_c14_4
+ 1644: d51abeaf msr s3_2_c11_c14_5, x15
+ 1648: d53abeaf mrs x15, s3_2_c11_c14_5
+ 164c: d51abecf msr s3_2_c11_c14_6, x15
+ 1650: d53abecf mrs x15, s3_2_c11_c14_6
+ 1654: d51abeef msr s3_2_c11_c14_7, x15
+ 1658: d53abeef mrs x15, s3_2_c11_c14_7
+ 165c: d51abf0f msr s3_2_c11_c15_0, x15
+ 1660: d53abf0f mrs x15, s3_2_c11_c15_0
+ 1664: d51abf2f msr s3_2_c11_c15_1, x15
+ 1668: d53abf2f mrs x15, s3_2_c11_c15_1
+ 166c: d51abf4f msr s3_2_c11_c15_2, x15
+ 1670: d53abf4f mrs x15, s3_2_c11_c15_2
+ 1674: d51abf6f msr s3_2_c11_c15_3, x15
+ 1678: d53abf6f mrs x15, s3_2_c11_c15_3
+ 167c: d51abf8f msr s3_2_c11_c15_4, x15
+ 1680: d53abf8f mrs x15, s3_2_c11_c15_4
+ 1684: d51abfaf msr s3_2_c11_c15_5, x15
+ 1688: d53abfaf mrs x15, s3_2_c11_c15_5
+ 168c: d51abfcf msr s3_2_c11_c15_6, x15
+ 1690: d53abfcf mrs x15, s3_2_c11_c15_6
+ 1694: d51abfef msr s3_2_c11_c15_7, x15
+ 1698: d53abfef mrs x15, s3_2_c11_c15_7
+ 169c: d51af00f msr s3_2_c15_c0_0, x15
+ 16a0: d53af00f mrs x15, s3_2_c15_c0_0
+ 16a4: d51af02f msr s3_2_c15_c0_1, x15
+ 16a8: d53af02f mrs x15, s3_2_c15_c0_1
+ 16ac: d51af04f msr s3_2_c15_c0_2, x15
+ 16b0: d53af04f mrs x15, s3_2_c15_c0_2
+ 16b4: d51af06f msr s3_2_c15_c0_3, x15
+ 16b8: d53af06f mrs x15, s3_2_c15_c0_3
+ 16bc: d51af08f msr s3_2_c15_c0_4, x15
+ 16c0: d53af08f mrs x15, s3_2_c15_c0_4
+ 16c4: d51af0af msr s3_2_c15_c0_5, x15
+ 16c8: d53af0af mrs x15, s3_2_c15_c0_5
+ 16cc: d51af0cf msr s3_2_c15_c0_6, x15
+ 16d0: d53af0cf mrs x15, s3_2_c15_c0_6
+ 16d4: d51af0ef msr s3_2_c15_c0_7, x15
+ 16d8: d53af0ef mrs x15, s3_2_c15_c0_7
+ 16dc: d51af10f msr s3_2_c15_c1_0, x15
+ 16e0: d53af10f mrs x15, s3_2_c15_c1_0
+ 16e4: d51af12f msr s3_2_c15_c1_1, x15
+ 16e8: d53af12f mrs x15, s3_2_c15_c1_1
+ 16ec: d51af14f msr s3_2_c15_c1_2, x15
+ 16f0: d53af14f mrs x15, s3_2_c15_c1_2
+ 16f4: d51af16f msr s3_2_c15_c1_3, x15
+ 16f8: d53af16f mrs x15, s3_2_c15_c1_3
+ 16fc: d51af18f msr s3_2_c15_c1_4, x15
+ 1700: d53af18f mrs x15, s3_2_c15_c1_4
+ 1704: d51af1af msr s3_2_c15_c1_5, x15
+ 1708: d53af1af mrs x15, s3_2_c15_c1_5
+ 170c: d51af1cf msr s3_2_c15_c1_6, x15
+ 1710: d53af1cf mrs x15, s3_2_c15_c1_6
+ 1714: d51af1ef msr s3_2_c15_c1_7, x15
+ 1718: d53af1ef mrs x15, s3_2_c15_c1_7
+ 171c: d51af20f msr s3_2_c15_c2_0, x15
+ 1720: d53af20f mrs x15, s3_2_c15_c2_0
+ 1724: d51af22f msr s3_2_c15_c2_1, x15
+ 1728: d53af22f mrs x15, s3_2_c15_c2_1
+ 172c: d51af24f msr s3_2_c15_c2_2, x15
+ 1730: d53af24f mrs x15, s3_2_c15_c2_2
+ 1734: d51af26f msr s3_2_c15_c2_3, x15
+ 1738: d53af26f mrs x15, s3_2_c15_c2_3
+ 173c: d51af28f msr s3_2_c15_c2_4, x15
+ 1740: d53af28f mrs x15, s3_2_c15_c2_4
+ 1744: d51af2af msr s3_2_c15_c2_5, x15
+ 1748: d53af2af mrs x15, s3_2_c15_c2_5
+ 174c: d51af2cf msr s3_2_c15_c2_6, x15
+ 1750: d53af2cf mrs x15, s3_2_c15_c2_6
+ 1754: d51af2ef msr s3_2_c15_c2_7, x15
+ 1758: d53af2ef mrs x15, s3_2_c15_c2_7
+ 175c: d51af30f msr s3_2_c15_c3_0, x15
+ 1760: d53af30f mrs x15, s3_2_c15_c3_0
+ 1764: d51af32f msr s3_2_c15_c3_1, x15
+ 1768: d53af32f mrs x15, s3_2_c15_c3_1
+ 176c: d51af34f msr s3_2_c15_c3_2, x15
+ 1770: d53af34f mrs x15, s3_2_c15_c3_2
+ 1774: d51af36f msr s3_2_c15_c3_3, x15
+ 1778: d53af36f mrs x15, s3_2_c15_c3_3
+ 177c: d51af38f msr s3_2_c15_c3_4, x15
+ 1780: d53af38f mrs x15, s3_2_c15_c3_4
+ 1784: d51af3af msr s3_2_c15_c3_5, x15
+ 1788: d53af3af mrs x15, s3_2_c15_c3_5
+ 178c: d51af3cf msr s3_2_c15_c3_6, x15
+ 1790: d53af3cf mrs x15, s3_2_c15_c3_6
+ 1794: d51af3ef msr s3_2_c15_c3_7, x15
+ 1798: d53af3ef mrs x15, s3_2_c15_c3_7
+ 179c: d51af40f msr s3_2_c15_c4_0, x15
+ 17a0: d53af40f mrs x15, s3_2_c15_c4_0
+ 17a4: d51af42f msr s3_2_c15_c4_1, x15
+ 17a8: d53af42f mrs x15, s3_2_c15_c4_1
+ 17ac: d51af44f msr s3_2_c15_c4_2, x15
+ 17b0: d53af44f mrs x15, s3_2_c15_c4_2
+ 17b4: d51af46f msr s3_2_c15_c4_3, x15
+ 17b8: d53af46f mrs x15, s3_2_c15_c4_3
+ 17bc: d51af48f msr s3_2_c15_c4_4, x15
+ 17c0: d53af48f mrs x15, s3_2_c15_c4_4
+ 17c4: d51af4af msr s3_2_c15_c4_5, x15
+ 17c8: d53af4af mrs x15, s3_2_c15_c4_5
+ 17cc: d51af4cf msr s3_2_c15_c4_6, x15
+ 17d0: d53af4cf mrs x15, s3_2_c15_c4_6
+ 17d4: d51af4ef msr s3_2_c15_c4_7, x15
+ 17d8: d53af4ef mrs x15, s3_2_c15_c4_7
+ 17dc: d51af50f msr s3_2_c15_c5_0, x15
+ 17e0: d53af50f mrs x15, s3_2_c15_c5_0
+ 17e4: d51af52f msr s3_2_c15_c5_1, x15
+ 17e8: d53af52f mrs x15, s3_2_c15_c5_1
+ 17ec: d51af54f msr s3_2_c15_c5_2, x15
+ 17f0: d53af54f mrs x15, s3_2_c15_c5_2
+ 17f4: d51af56f msr s3_2_c15_c5_3, x15
+ 17f8: d53af56f mrs x15, s3_2_c15_c5_3
+ 17fc: d51af58f msr s3_2_c15_c5_4, x15
+ 1800: d53af58f mrs x15, s3_2_c15_c5_4
+ 1804: d51af5af msr s3_2_c15_c5_5, x15
+ 1808: d53af5af mrs x15, s3_2_c15_c5_5
+ 180c: d51af5cf msr s3_2_c15_c5_6, x15
+ 1810: d53af5cf mrs x15, s3_2_c15_c5_6
+ 1814: d51af5ef msr s3_2_c15_c5_7, x15
+ 1818: d53af5ef mrs x15, s3_2_c15_c5_7
+ 181c: d51af60f msr s3_2_c15_c6_0, x15
+ 1820: d53af60f mrs x15, s3_2_c15_c6_0
+ 1824: d51af62f msr s3_2_c15_c6_1, x15
+ 1828: d53af62f mrs x15, s3_2_c15_c6_1
+ 182c: d51af64f msr s3_2_c15_c6_2, x15
+ 1830: d53af64f mrs x15, s3_2_c15_c6_2
+ 1834: d51af66f msr s3_2_c15_c6_3, x15
+ 1838: d53af66f mrs x15, s3_2_c15_c6_3
+ 183c: d51af68f msr s3_2_c15_c6_4, x15
+ 1840: d53af68f mrs x15, s3_2_c15_c6_4
+ 1844: d51af6af msr s3_2_c15_c6_5, x15
+ 1848: d53af6af mrs x15, s3_2_c15_c6_5
+ 184c: d51af6cf msr s3_2_c15_c6_6, x15
+ 1850: d53af6cf mrs x15, s3_2_c15_c6_6
+ 1854: d51af6ef msr s3_2_c15_c6_7, x15
+ 1858: d53af6ef mrs x15, s3_2_c15_c6_7
+ 185c: d51af70f msr s3_2_c15_c7_0, x15
+ 1860: d53af70f mrs x15, s3_2_c15_c7_0
+ 1864: d51af72f msr s3_2_c15_c7_1, x15
+ 1868: d53af72f mrs x15, s3_2_c15_c7_1
+ 186c: d51af74f msr s3_2_c15_c7_2, x15
+ 1870: d53af74f mrs x15, s3_2_c15_c7_2
+ 1874: d51af76f msr s3_2_c15_c7_3, x15
+ 1878: d53af76f mrs x15, s3_2_c15_c7_3
+ 187c: d51af78f msr s3_2_c15_c7_4, x15
+ 1880: d53af78f mrs x15, s3_2_c15_c7_4
+ 1884: d51af7af msr s3_2_c15_c7_5, x15
+ 1888: d53af7af mrs x15, s3_2_c15_c7_5
+ 188c: d51af7cf msr s3_2_c15_c7_6, x15
+ 1890: d53af7cf mrs x15, s3_2_c15_c7_6
+ 1894: d51af7ef msr s3_2_c15_c7_7, x15
+ 1898: d53af7ef mrs x15, s3_2_c15_c7_7
+ 189c: d51af80f msr s3_2_c15_c8_0, x15
+ 18a0: d53af80f mrs x15, s3_2_c15_c8_0
+ 18a4: d51af82f msr s3_2_c15_c8_1, x15
+ 18a8: d53af82f mrs x15, s3_2_c15_c8_1
+ 18ac: d51af84f msr s3_2_c15_c8_2, x15
+ 18b0: d53af84f mrs x15, s3_2_c15_c8_2
+ 18b4: d51af86f msr s3_2_c15_c8_3, x15
+ 18b8: d53af86f mrs x15, s3_2_c15_c8_3
+ 18bc: d51af88f msr s3_2_c15_c8_4, x15
+ 18c0: d53af88f mrs x15, s3_2_c15_c8_4
+ 18c4: d51af8af msr s3_2_c15_c8_5, x15
+ 18c8: d53af8af mrs x15, s3_2_c15_c8_5
+ 18cc: d51af8cf msr s3_2_c15_c8_6, x15
+ 18d0: d53af8cf mrs x15, s3_2_c15_c8_6
+ 18d4: d51af8ef msr s3_2_c15_c8_7, x15
+ 18d8: d53af8ef mrs x15, s3_2_c15_c8_7
+ 18dc: d51af90f msr s3_2_c15_c9_0, x15
+ 18e0: d53af90f mrs x15, s3_2_c15_c9_0
+ 18e4: d51af92f msr s3_2_c15_c9_1, x15
+ 18e8: d53af92f mrs x15, s3_2_c15_c9_1
+ 18ec: d51af94f msr s3_2_c15_c9_2, x15
+ 18f0: d53af94f mrs x15, s3_2_c15_c9_2
+ 18f4: d51af96f msr s3_2_c15_c9_3, x15
+ 18f8: d53af96f mrs x15, s3_2_c15_c9_3
+ 18fc: d51af98f msr s3_2_c15_c9_4, x15
+ 1900: d53af98f mrs x15, s3_2_c15_c9_4
+ 1904: d51af9af msr s3_2_c15_c9_5, x15
+ 1908: d53af9af mrs x15, s3_2_c15_c9_5
+ 190c: d51af9cf msr s3_2_c15_c9_6, x15
+ 1910: d53af9cf mrs x15, s3_2_c15_c9_6
+ 1914: d51af9ef msr s3_2_c15_c9_7, x15
+ 1918: d53af9ef mrs x15, s3_2_c15_c9_7
+ 191c: d51afa0f msr s3_2_c15_c10_0, x15
+ 1920: d53afa0f mrs x15, s3_2_c15_c10_0
+ 1924: d51afa2f msr s3_2_c15_c10_1, x15
+ 1928: d53afa2f mrs x15, s3_2_c15_c10_1
+ 192c: d51afa4f msr s3_2_c15_c10_2, x15
+ 1930: d53afa4f mrs x15, s3_2_c15_c10_2
+ 1934: d51afa6f msr s3_2_c15_c10_3, x15
+ 1938: d53afa6f mrs x15, s3_2_c15_c10_3
+ 193c: d51afa8f msr s3_2_c15_c10_4, x15
+ 1940: d53afa8f mrs x15, s3_2_c15_c10_4
+ 1944: d51afaaf msr s3_2_c15_c10_5, x15
+ 1948: d53afaaf mrs x15, s3_2_c15_c10_5
+ 194c: d51afacf msr s3_2_c15_c10_6, x15
+ 1950: d53afacf mrs x15, s3_2_c15_c10_6
+ 1954: d51afaef msr s3_2_c15_c10_7, x15
+ 1958: d53afaef mrs x15, s3_2_c15_c10_7
+ 195c: d51afb0f msr s3_2_c15_c11_0, x15
+ 1960: d53afb0f mrs x15, s3_2_c15_c11_0
+ 1964: d51afb2f msr s3_2_c15_c11_1, x15
+ 1968: d53afb2f mrs x15, s3_2_c15_c11_1
+ 196c: d51afb4f msr s3_2_c15_c11_2, x15
+ 1970: d53afb4f mrs x15, s3_2_c15_c11_2
+ 1974: d51afb6f msr s3_2_c15_c11_3, x15
+ 1978: d53afb6f mrs x15, s3_2_c15_c11_3
+ 197c: d51afb8f msr s3_2_c15_c11_4, x15
+ 1980: d53afb8f mrs x15, s3_2_c15_c11_4
+ 1984: d51afbaf msr s3_2_c15_c11_5, x15
+ 1988: d53afbaf mrs x15, s3_2_c15_c11_5
+ 198c: d51afbcf msr s3_2_c15_c11_6, x15
+ 1990: d53afbcf mrs x15, s3_2_c15_c11_6
+ 1994: d51afbef msr s3_2_c15_c11_7, x15
+ 1998: d53afbef mrs x15, s3_2_c15_c11_7
+ 199c: d51afc0f msr s3_2_c15_c12_0, x15
+ 19a0: d53afc0f mrs x15, s3_2_c15_c12_0
+ 19a4: d51afc2f msr s3_2_c15_c12_1, x15
+ 19a8: d53afc2f mrs x15, s3_2_c15_c12_1
+ 19ac: d51afc4f msr s3_2_c15_c12_2, x15
+ 19b0: d53afc4f mrs x15, s3_2_c15_c12_2
+ 19b4: d51afc6f msr s3_2_c15_c12_3, x15
+ 19b8: d53afc6f mrs x15, s3_2_c15_c12_3
+ 19bc: d51afc8f msr s3_2_c15_c12_4, x15
+ 19c0: d53afc8f mrs x15, s3_2_c15_c12_4
+ 19c4: d51afcaf msr s3_2_c15_c12_5, x15
+ 19c8: d53afcaf mrs x15, s3_2_c15_c12_5
+ 19cc: d51afccf msr s3_2_c15_c12_6, x15
+ 19d0: d53afccf mrs x15, s3_2_c15_c12_6
+ 19d4: d51afcef msr s3_2_c15_c12_7, x15
+ 19d8: d53afcef mrs x15, s3_2_c15_c12_7
+ 19dc: d51afd0f msr s3_2_c15_c13_0, x15
+ 19e0: d53afd0f mrs x15, s3_2_c15_c13_0
+ 19e4: d51afd2f msr s3_2_c15_c13_1, x15
+ 19e8: d53afd2f mrs x15, s3_2_c15_c13_1
+ 19ec: d51afd4f msr s3_2_c15_c13_2, x15
+ 19f0: d53afd4f mrs x15, s3_2_c15_c13_2
+ 19f4: d51afd6f msr s3_2_c15_c13_3, x15
+ 19f8: d53afd6f mrs x15, s3_2_c15_c13_3
+ 19fc: d51afd8f msr s3_2_c15_c13_4, x15
+ 1a00: d53afd8f mrs x15, s3_2_c15_c13_4
+ 1a04: d51afdaf msr s3_2_c15_c13_5, x15
+ 1a08: d53afdaf mrs x15, s3_2_c15_c13_5
+ 1a0c: d51afdcf msr s3_2_c15_c13_6, x15
+ 1a10: d53afdcf mrs x15, s3_2_c15_c13_6
+ 1a14: d51afdef msr s3_2_c15_c13_7, x15
+ 1a18: d53afdef mrs x15, s3_2_c15_c13_7
+ 1a1c: d51afe0f msr s3_2_c15_c14_0, x15
+ 1a20: d53afe0f mrs x15, s3_2_c15_c14_0
+ 1a24: d51afe2f msr s3_2_c15_c14_1, x15
+ 1a28: d53afe2f mrs x15, s3_2_c15_c14_1
+ 1a2c: d51afe4f msr s3_2_c15_c14_2, x15
+ 1a30: d53afe4f mrs x15, s3_2_c15_c14_2
+ 1a34: d51afe6f msr s3_2_c15_c14_3, x15
+ 1a38: d53afe6f mrs x15, s3_2_c15_c14_3
+ 1a3c: d51afe8f msr s3_2_c15_c14_4, x15
+ 1a40: d53afe8f mrs x15, s3_2_c15_c14_4
+ 1a44: d51afeaf msr s3_2_c15_c14_5, x15
+ 1a48: d53afeaf mrs x15, s3_2_c15_c14_5
+ 1a4c: d51afecf msr s3_2_c15_c14_6, x15
+ 1a50: d53afecf mrs x15, s3_2_c15_c14_6
+ 1a54: d51afeef msr s3_2_c15_c14_7, x15
+ 1a58: d53afeef mrs x15, s3_2_c15_c14_7
+ 1a5c: d51aff0f msr s3_2_c15_c15_0, x15
+ 1a60: d53aff0f mrs x15, s3_2_c15_c15_0
+ 1a64: d51aff2f msr s3_2_c15_c15_1, x15
+ 1a68: d53aff2f mrs x15, s3_2_c15_c15_1
+ 1a6c: d51aff4f msr s3_2_c15_c15_2, x15
+ 1a70: d53aff4f mrs x15, s3_2_c15_c15_2
+ 1a74: d51aff6f msr s3_2_c15_c15_3, x15
+ 1a78: d53aff6f mrs x15, s3_2_c15_c15_3
+ 1a7c: d51aff8f msr s3_2_c15_c15_4, x15
+ 1a80: d53aff8f mrs x15, s3_2_c15_c15_4
+ 1a84: d51affaf msr s3_2_c15_c15_5, x15
+ 1a88: d53affaf mrs x15, s3_2_c15_c15_5
+ 1a8c: d51affcf msr s3_2_c15_c15_6, x15
+ 1a90: d53affcf mrs x15, s3_2_c15_c15_6
+ 1a94: d51affef msr s3_2_c15_c15_7, x15
+ 1a98: d53affef mrs x15, s3_2_c15_c15_7
+ 1a9c: d51bb00f msr s3_3_c11_c0_0, x15
+ 1aa0: d53bb00f mrs x15, s3_3_c11_c0_0
+ 1aa4: d51bb02f msr s3_3_c11_c0_1, x15
+ 1aa8: d53bb02f mrs x15, s3_3_c11_c0_1
+ 1aac: d51bb04f msr s3_3_c11_c0_2, x15
+ 1ab0: d53bb04f mrs x15, s3_3_c11_c0_2
+ 1ab4: d51bb06f msr s3_3_c11_c0_3, x15
+ 1ab8: d53bb06f mrs x15, s3_3_c11_c0_3
+ 1abc: d51bb08f msr s3_3_c11_c0_4, x15
+ 1ac0: d53bb08f mrs x15, s3_3_c11_c0_4
+ 1ac4: d51bb0af msr s3_3_c11_c0_5, x15
+ 1ac8: d53bb0af mrs x15, s3_3_c11_c0_5
+ 1acc: d51bb0cf msr s3_3_c11_c0_6, x15
+ 1ad0: d53bb0cf mrs x15, s3_3_c11_c0_6
+ 1ad4: d51bb0ef msr s3_3_c11_c0_7, x15
+ 1ad8: d53bb0ef mrs x15, s3_3_c11_c0_7
+ 1adc: d51bb10f msr s3_3_c11_c1_0, x15
+ 1ae0: d53bb10f mrs x15, s3_3_c11_c1_0
+ 1ae4: d51bb12f msr s3_3_c11_c1_1, x15
+ 1ae8: d53bb12f mrs x15, s3_3_c11_c1_1
+ 1aec: d51bb14f msr s3_3_c11_c1_2, x15
+ 1af0: d53bb14f mrs x15, s3_3_c11_c1_2
+ 1af4: d51bb16f msr s3_3_c11_c1_3, x15
+ 1af8: d53bb16f mrs x15, s3_3_c11_c1_3
+ 1afc: d51bb18f msr s3_3_c11_c1_4, x15
+ 1b00: d53bb18f mrs x15, s3_3_c11_c1_4
+ 1b04: d51bb1af msr s3_3_c11_c1_5, x15
+ 1b08: d53bb1af mrs x15, s3_3_c11_c1_5
+ 1b0c: d51bb1cf msr s3_3_c11_c1_6, x15
+ 1b10: d53bb1cf mrs x15, s3_3_c11_c1_6
+ 1b14: d51bb1ef msr s3_3_c11_c1_7, x15
+ 1b18: d53bb1ef mrs x15, s3_3_c11_c1_7
+ 1b1c: d51bb20f msr s3_3_c11_c2_0, x15
+ 1b20: d53bb20f mrs x15, s3_3_c11_c2_0
+ 1b24: d51bb22f msr s3_3_c11_c2_1, x15
+ 1b28: d53bb22f mrs x15, s3_3_c11_c2_1
+ 1b2c: d51bb24f msr s3_3_c11_c2_2, x15
+ 1b30: d53bb24f mrs x15, s3_3_c11_c2_2
+ 1b34: d51bb26f msr s3_3_c11_c2_3, x15
+ 1b38: d53bb26f mrs x15, s3_3_c11_c2_3
+ 1b3c: d51bb28f msr s3_3_c11_c2_4, x15
+ 1b40: d53bb28f mrs x15, s3_3_c11_c2_4
+ 1b44: d51bb2af msr s3_3_c11_c2_5, x15
+ 1b48: d53bb2af mrs x15, s3_3_c11_c2_5
+ 1b4c: d51bb2cf msr s3_3_c11_c2_6, x15
+ 1b50: d53bb2cf mrs x15, s3_3_c11_c2_6
+ 1b54: d51bb2ef msr s3_3_c11_c2_7, x15
+ 1b58: d53bb2ef mrs x15, s3_3_c11_c2_7
+ 1b5c: d51bb30f msr s3_3_c11_c3_0, x15
+ 1b60: d53bb30f mrs x15, s3_3_c11_c3_0
+ 1b64: d51bb32f msr s3_3_c11_c3_1, x15
+ 1b68: d53bb32f mrs x15, s3_3_c11_c3_1
+ 1b6c: d51bb34f msr s3_3_c11_c3_2, x15
+ 1b70: d53bb34f mrs x15, s3_3_c11_c3_2
+ 1b74: d51bb36f msr s3_3_c11_c3_3, x15
+ 1b78: d53bb36f mrs x15, s3_3_c11_c3_3
+ 1b7c: d51bb38f msr s3_3_c11_c3_4, x15
+ 1b80: d53bb38f mrs x15, s3_3_c11_c3_4
+ 1b84: d51bb3af msr s3_3_c11_c3_5, x15
+ 1b88: d53bb3af mrs x15, s3_3_c11_c3_5
+ 1b8c: d51bb3cf msr s3_3_c11_c3_6, x15
+ 1b90: d53bb3cf mrs x15, s3_3_c11_c3_6
+ 1b94: d51bb3ef msr s3_3_c11_c3_7, x15
+ 1b98: d53bb3ef mrs x15, s3_3_c11_c3_7
+ 1b9c: d51bb40f msr s3_3_c11_c4_0, x15
+ 1ba0: d53bb40f mrs x15, s3_3_c11_c4_0
+ 1ba4: d51bb42f msr s3_3_c11_c4_1, x15
+ 1ba8: d53bb42f mrs x15, s3_3_c11_c4_1
+ 1bac: d51bb44f msr s3_3_c11_c4_2, x15
+ 1bb0: d53bb44f mrs x15, s3_3_c11_c4_2
+ 1bb4: d51bb46f msr s3_3_c11_c4_3, x15
+ 1bb8: d53bb46f mrs x15, s3_3_c11_c4_3
+ 1bbc: d51bb48f msr s3_3_c11_c4_4, x15
+ 1bc0: d53bb48f mrs x15, s3_3_c11_c4_4
+ 1bc4: d51bb4af msr s3_3_c11_c4_5, x15
+ 1bc8: d53bb4af mrs x15, s3_3_c11_c4_5
+ 1bcc: d51bb4cf msr s3_3_c11_c4_6, x15
+ 1bd0: d53bb4cf mrs x15, s3_3_c11_c4_6
+ 1bd4: d51bb4ef msr s3_3_c11_c4_7, x15
+ 1bd8: d53bb4ef mrs x15, s3_3_c11_c4_7
+ 1bdc: d51bb50f msr s3_3_c11_c5_0, x15
+ 1be0: d53bb50f mrs x15, s3_3_c11_c5_0
+ 1be4: d51bb52f msr s3_3_c11_c5_1, x15
+ 1be8: d53bb52f mrs x15, s3_3_c11_c5_1
+ 1bec: d51bb54f msr s3_3_c11_c5_2, x15
+ 1bf0: d53bb54f mrs x15, s3_3_c11_c5_2
+ 1bf4: d51bb56f msr s3_3_c11_c5_3, x15
+ 1bf8: d53bb56f mrs x15, s3_3_c11_c5_3
+ 1bfc: d51bb58f msr s3_3_c11_c5_4, x15
+ 1c00: d53bb58f mrs x15, s3_3_c11_c5_4
+ 1c04: d51bb5af msr s3_3_c11_c5_5, x15
+ 1c08: d53bb5af mrs x15, s3_3_c11_c5_5
+ 1c0c: d51bb5cf msr s3_3_c11_c5_6, x15
+ 1c10: d53bb5cf mrs x15, s3_3_c11_c5_6
+ 1c14: d51bb5ef msr s3_3_c11_c5_7, x15
+ 1c18: d53bb5ef mrs x15, s3_3_c11_c5_7
+ 1c1c: d51bb60f msr s3_3_c11_c6_0, x15
+ 1c20: d53bb60f mrs x15, s3_3_c11_c6_0
+ 1c24: d51bb62f msr s3_3_c11_c6_1, x15
+ 1c28: d53bb62f mrs x15, s3_3_c11_c6_1
+ 1c2c: d51bb64f msr s3_3_c11_c6_2, x15
+ 1c30: d53bb64f mrs x15, s3_3_c11_c6_2
+ 1c34: d51bb66f msr s3_3_c11_c6_3, x15
+ 1c38: d53bb66f mrs x15, s3_3_c11_c6_3
+ 1c3c: d51bb68f msr s3_3_c11_c6_4, x15
+ 1c40: d53bb68f mrs x15, s3_3_c11_c6_4
+ 1c44: d51bb6af msr s3_3_c11_c6_5, x15
+ 1c48: d53bb6af mrs x15, s3_3_c11_c6_5
+ 1c4c: d51bb6cf msr s3_3_c11_c6_6, x15
+ 1c50: d53bb6cf mrs x15, s3_3_c11_c6_6
+ 1c54: d51bb6ef msr s3_3_c11_c6_7, x15
+ 1c58: d53bb6ef mrs x15, s3_3_c11_c6_7
+ 1c5c: d51bb70f msr s3_3_c11_c7_0, x15
+ 1c60: d53bb70f mrs x15, s3_3_c11_c7_0
+ 1c64: d51bb72f msr s3_3_c11_c7_1, x15
+ 1c68: d53bb72f mrs x15, s3_3_c11_c7_1
+ 1c6c: d51bb74f msr s3_3_c11_c7_2, x15
+ 1c70: d53bb74f mrs x15, s3_3_c11_c7_2
+ 1c74: d51bb76f msr s3_3_c11_c7_3, x15
+ 1c78: d53bb76f mrs x15, s3_3_c11_c7_3
+ 1c7c: d51bb78f msr s3_3_c11_c7_4, x15
+ 1c80: d53bb78f mrs x15, s3_3_c11_c7_4
+ 1c84: d51bb7af msr s3_3_c11_c7_5, x15
+ 1c88: d53bb7af mrs x15, s3_3_c11_c7_5
+ 1c8c: d51bb7cf msr s3_3_c11_c7_6, x15
+ 1c90: d53bb7cf mrs x15, s3_3_c11_c7_6
+ 1c94: d51bb7ef msr s3_3_c11_c7_7, x15
+ 1c98: d53bb7ef mrs x15, s3_3_c11_c7_7
+ 1c9c: d51bb80f msr s3_3_c11_c8_0, x15
+ 1ca0: d53bb80f mrs x15, s3_3_c11_c8_0
+ 1ca4: d51bb82f msr s3_3_c11_c8_1, x15
+ 1ca8: d53bb82f mrs x15, s3_3_c11_c8_1
+ 1cac: d51bb84f msr s3_3_c11_c8_2, x15
+ 1cb0: d53bb84f mrs x15, s3_3_c11_c8_2
+ 1cb4: d51bb86f msr s3_3_c11_c8_3, x15
+ 1cb8: d53bb86f mrs x15, s3_3_c11_c8_3
+ 1cbc: d51bb88f msr s3_3_c11_c8_4, x15
+ 1cc0: d53bb88f mrs x15, s3_3_c11_c8_4
+ 1cc4: d51bb8af msr s3_3_c11_c8_5, x15
+ 1cc8: d53bb8af mrs x15, s3_3_c11_c8_5
+ 1ccc: d51bb8cf msr s3_3_c11_c8_6, x15
+ 1cd0: d53bb8cf mrs x15, s3_3_c11_c8_6
+ 1cd4: d51bb8ef msr s3_3_c11_c8_7, x15
+ 1cd8: d53bb8ef mrs x15, s3_3_c11_c8_7
+ 1cdc: d51bb90f msr s3_3_c11_c9_0, x15
+ 1ce0: d53bb90f mrs x15, s3_3_c11_c9_0
+ 1ce4: d51bb92f msr s3_3_c11_c9_1, x15
+ 1ce8: d53bb92f mrs x15, s3_3_c11_c9_1
+ 1cec: d51bb94f msr s3_3_c11_c9_2, x15
+ 1cf0: d53bb94f mrs x15, s3_3_c11_c9_2
+ 1cf4: d51bb96f msr s3_3_c11_c9_3, x15
+ 1cf8: d53bb96f mrs x15, s3_3_c11_c9_3
+ 1cfc: d51bb98f msr s3_3_c11_c9_4, x15
+ 1d00: d53bb98f mrs x15, s3_3_c11_c9_4
+ 1d04: d51bb9af msr s3_3_c11_c9_5, x15
+ 1d08: d53bb9af mrs x15, s3_3_c11_c9_5
+ 1d0c: d51bb9cf msr s3_3_c11_c9_6, x15
+ 1d10: d53bb9cf mrs x15, s3_3_c11_c9_6
+ 1d14: d51bb9ef msr s3_3_c11_c9_7, x15
+ 1d18: d53bb9ef mrs x15, s3_3_c11_c9_7
+ 1d1c: d51bba0f msr s3_3_c11_c10_0, x15
+ 1d20: d53bba0f mrs x15, s3_3_c11_c10_0
+ 1d24: d51bba2f msr s3_3_c11_c10_1, x15
+ 1d28: d53bba2f mrs x15, s3_3_c11_c10_1
+ 1d2c: d51bba4f msr s3_3_c11_c10_2, x15
+ 1d30: d53bba4f mrs x15, s3_3_c11_c10_2
+ 1d34: d51bba6f msr s3_3_c11_c10_3, x15
+ 1d38: d53bba6f mrs x15, s3_3_c11_c10_3
+ 1d3c: d51bba8f msr s3_3_c11_c10_4, x15
+ 1d40: d53bba8f mrs x15, s3_3_c11_c10_4
+ 1d44: d51bbaaf msr s3_3_c11_c10_5, x15
+ 1d48: d53bbaaf mrs x15, s3_3_c11_c10_5
+ 1d4c: d51bbacf msr s3_3_c11_c10_6, x15
+ 1d50: d53bbacf mrs x15, s3_3_c11_c10_6
+ 1d54: d51bbaef msr s3_3_c11_c10_7, x15
+ 1d58: d53bbaef mrs x15, s3_3_c11_c10_7
+ 1d5c: d51bbb0f msr s3_3_c11_c11_0, x15
+ 1d60: d53bbb0f mrs x15, s3_3_c11_c11_0
+ 1d64: d51bbb2f msr s3_3_c11_c11_1, x15
+ 1d68: d53bbb2f mrs x15, s3_3_c11_c11_1
+ 1d6c: d51bbb4f msr s3_3_c11_c11_2, x15
+ 1d70: d53bbb4f mrs x15, s3_3_c11_c11_2
+ 1d74: d51bbb6f msr s3_3_c11_c11_3, x15
+ 1d78: d53bbb6f mrs x15, s3_3_c11_c11_3
+ 1d7c: d51bbb8f msr s3_3_c11_c11_4, x15
+ 1d80: d53bbb8f mrs x15, s3_3_c11_c11_4
+ 1d84: d51bbbaf msr s3_3_c11_c11_5, x15
+ 1d88: d53bbbaf mrs x15, s3_3_c11_c11_5
+ 1d8c: d51bbbcf msr s3_3_c11_c11_6, x15
+ 1d90: d53bbbcf mrs x15, s3_3_c11_c11_6
+ 1d94: d51bbbef msr s3_3_c11_c11_7, x15
+ 1d98: d53bbbef mrs x15, s3_3_c11_c11_7
+ 1d9c: d51bbc0f msr s3_3_c11_c12_0, x15
+ 1da0: d53bbc0f mrs x15, s3_3_c11_c12_0
+ 1da4: d51bbc2f msr s3_3_c11_c12_1, x15
+ 1da8: d53bbc2f mrs x15, s3_3_c11_c12_1
+ 1dac: d51bbc4f msr s3_3_c11_c12_2, x15
+ 1db0: d53bbc4f mrs x15, s3_3_c11_c12_2
+ 1db4: d51bbc6f msr s3_3_c11_c12_3, x15
+ 1db8: d53bbc6f mrs x15, s3_3_c11_c12_3
+ 1dbc: d51bbc8f msr s3_3_c11_c12_4, x15
+ 1dc0: d53bbc8f mrs x15, s3_3_c11_c12_4
+ 1dc4: d51bbcaf msr s3_3_c11_c12_5, x15
+ 1dc8: d53bbcaf mrs x15, s3_3_c11_c12_5
+ 1dcc: d51bbccf msr s3_3_c11_c12_6, x15
+ 1dd0: d53bbccf mrs x15, s3_3_c11_c12_6
+ 1dd4: d51bbcef msr s3_3_c11_c12_7, x15
+ 1dd8: d53bbcef mrs x15, s3_3_c11_c12_7
+ 1ddc: d51bbd0f msr s3_3_c11_c13_0, x15
+ 1de0: d53bbd0f mrs x15, s3_3_c11_c13_0
+ 1de4: d51bbd2f msr s3_3_c11_c13_1, x15
+ 1de8: d53bbd2f mrs x15, s3_3_c11_c13_1
+ 1dec: d51bbd4f msr s3_3_c11_c13_2, x15
+ 1df0: d53bbd4f mrs x15, s3_3_c11_c13_2
+ 1df4: d51bbd6f msr s3_3_c11_c13_3, x15
+ 1df8: d53bbd6f mrs x15, s3_3_c11_c13_3
+ 1dfc: d51bbd8f msr s3_3_c11_c13_4, x15
+ 1e00: d53bbd8f mrs x15, s3_3_c11_c13_4
+ 1e04: d51bbdaf msr s3_3_c11_c13_5, x15
+ 1e08: d53bbdaf mrs x15, s3_3_c11_c13_5
+ 1e0c: d51bbdcf msr s3_3_c11_c13_6, x15
+ 1e10: d53bbdcf mrs x15, s3_3_c11_c13_6
+ 1e14: d51bbdef msr s3_3_c11_c13_7, x15
+ 1e18: d53bbdef mrs x15, s3_3_c11_c13_7
+ 1e1c: d51bbe0f msr s3_3_c11_c14_0, x15
+ 1e20: d53bbe0f mrs x15, s3_3_c11_c14_0
+ 1e24: d51bbe2f msr s3_3_c11_c14_1, x15
+ 1e28: d53bbe2f mrs x15, s3_3_c11_c14_1
+ 1e2c: d51bbe4f msr s3_3_c11_c14_2, x15
+ 1e30: d53bbe4f mrs x15, s3_3_c11_c14_2
+ 1e34: d51bbe6f msr s3_3_c11_c14_3, x15
+ 1e38: d53bbe6f mrs x15, s3_3_c11_c14_3
+ 1e3c: d51bbe8f msr s3_3_c11_c14_4, x15
+ 1e40: d53bbe8f mrs x15, s3_3_c11_c14_4
+ 1e44: d51bbeaf msr s3_3_c11_c14_5, x15
+ 1e48: d53bbeaf mrs x15, s3_3_c11_c14_5
+ 1e4c: d51bbecf msr s3_3_c11_c14_6, x15
+ 1e50: d53bbecf mrs x15, s3_3_c11_c14_6
+ 1e54: d51bbeef msr s3_3_c11_c14_7, x15
+ 1e58: d53bbeef mrs x15, s3_3_c11_c14_7
+ 1e5c: d51bbf0f msr s3_3_c11_c15_0, x15
+ 1e60: d53bbf0f mrs x15, s3_3_c11_c15_0
+ 1e64: d51bbf2f msr s3_3_c11_c15_1, x15
+ 1e68: d53bbf2f mrs x15, s3_3_c11_c15_1
+ 1e6c: d51bbf4f msr s3_3_c11_c15_2, x15
+ 1e70: d53bbf4f mrs x15, s3_3_c11_c15_2
+ 1e74: d51bbf6f msr s3_3_c11_c15_3, x15
+ 1e78: d53bbf6f mrs x15, s3_3_c11_c15_3
+ 1e7c: d51bbf8f msr s3_3_c11_c15_4, x15
+ 1e80: d53bbf8f mrs x15, s3_3_c11_c15_4
+ 1e84: d51bbfaf msr s3_3_c11_c15_5, x15
+ 1e88: d53bbfaf mrs x15, s3_3_c11_c15_5
+ 1e8c: d51bbfcf msr s3_3_c11_c15_6, x15
+ 1e90: d53bbfcf mrs x15, s3_3_c11_c15_6
+ 1e94: d51bbfef msr s3_3_c11_c15_7, x15
+ 1e98: d53bbfef mrs x15, s3_3_c11_c15_7
+ 1e9c: d51bf00f msr s3_3_c15_c0_0, x15
+ 1ea0: d53bf00f mrs x15, s3_3_c15_c0_0
+ 1ea4: d51bf02f msr s3_3_c15_c0_1, x15
+ 1ea8: d53bf02f mrs x15, s3_3_c15_c0_1
+ 1eac: d51bf04f msr s3_3_c15_c0_2, x15
+ 1eb0: d53bf04f mrs x15, s3_3_c15_c0_2
+ 1eb4: d51bf06f msr s3_3_c15_c0_3, x15
+ 1eb8: d53bf06f mrs x15, s3_3_c15_c0_3
+ 1ebc: d51bf08f msr s3_3_c15_c0_4, x15
+ 1ec0: d53bf08f mrs x15, s3_3_c15_c0_4
+ 1ec4: d51bf0af msr s3_3_c15_c0_5, x15
+ 1ec8: d53bf0af mrs x15, s3_3_c15_c0_5
+ 1ecc: d51bf0cf msr s3_3_c15_c0_6, x15
+ 1ed0: d53bf0cf mrs x15, s3_3_c15_c0_6
+ 1ed4: d51bf0ef msr s3_3_c15_c0_7, x15
+ 1ed8: d53bf0ef mrs x15, s3_3_c15_c0_7
+ 1edc: d51bf10f msr s3_3_c15_c1_0, x15
+ 1ee0: d53bf10f mrs x15, s3_3_c15_c1_0
+ 1ee4: d51bf12f msr s3_3_c15_c1_1, x15
+ 1ee8: d53bf12f mrs x15, s3_3_c15_c1_1
+ 1eec: d51bf14f msr s3_3_c15_c1_2, x15
+ 1ef0: d53bf14f mrs x15, s3_3_c15_c1_2
+ 1ef4: d51bf16f msr s3_3_c15_c1_3, x15
+ 1ef8: d53bf16f mrs x15, s3_3_c15_c1_3
+ 1efc: d51bf18f msr s3_3_c15_c1_4, x15
+ 1f00: d53bf18f mrs x15, s3_3_c15_c1_4
+ 1f04: d51bf1af msr s3_3_c15_c1_5, x15
+ 1f08: d53bf1af mrs x15, s3_3_c15_c1_5
+ 1f0c: d51bf1cf msr s3_3_c15_c1_6, x15
+ 1f10: d53bf1cf mrs x15, s3_3_c15_c1_6
+ 1f14: d51bf1ef msr s3_3_c15_c1_7, x15
+ 1f18: d53bf1ef mrs x15, s3_3_c15_c1_7
+ 1f1c: d51bf20f msr s3_3_c15_c2_0, x15
+ 1f20: d53bf20f mrs x15, s3_3_c15_c2_0
+ 1f24: d51bf22f msr s3_3_c15_c2_1, x15
+ 1f28: d53bf22f mrs x15, s3_3_c15_c2_1
+ 1f2c: d51bf24f msr s3_3_c15_c2_2, x15
+ 1f30: d53bf24f mrs x15, s3_3_c15_c2_2
+ 1f34: d51bf26f msr s3_3_c15_c2_3, x15
+ 1f38: d53bf26f mrs x15, s3_3_c15_c2_3
+ 1f3c: d51bf28f msr s3_3_c15_c2_4, x15
+ 1f40: d53bf28f mrs x15, s3_3_c15_c2_4
+ 1f44: d51bf2af msr s3_3_c15_c2_5, x15
+ 1f48: d53bf2af mrs x15, s3_3_c15_c2_5
+ 1f4c: d51bf2cf msr s3_3_c15_c2_6, x15
+ 1f50: d53bf2cf mrs x15, s3_3_c15_c2_6
+ 1f54: d51bf2ef msr s3_3_c15_c2_7, x15
+ 1f58: d53bf2ef mrs x15, s3_3_c15_c2_7
+ 1f5c: d51bf30f msr s3_3_c15_c3_0, x15
+ 1f60: d53bf30f mrs x15, s3_3_c15_c3_0
+ 1f64: d51bf32f msr s3_3_c15_c3_1, x15
+ 1f68: d53bf32f mrs x15, s3_3_c15_c3_1
+ 1f6c: d51bf34f msr s3_3_c15_c3_2, x15
+ 1f70: d53bf34f mrs x15, s3_3_c15_c3_2
+ 1f74: d51bf36f msr s3_3_c15_c3_3, x15
+ 1f78: d53bf36f mrs x15, s3_3_c15_c3_3
+ 1f7c: d51bf38f msr s3_3_c15_c3_4, x15
+ 1f80: d53bf38f mrs x15, s3_3_c15_c3_4
+ 1f84: d51bf3af msr s3_3_c15_c3_5, x15
+ 1f88: d53bf3af mrs x15, s3_3_c15_c3_5
+ 1f8c: d51bf3cf msr s3_3_c15_c3_6, x15
+ 1f90: d53bf3cf mrs x15, s3_3_c15_c3_6
+ 1f94: d51bf3ef msr s3_3_c15_c3_7, x15
+ 1f98: d53bf3ef mrs x15, s3_3_c15_c3_7
+ 1f9c: d51bf40f msr s3_3_c15_c4_0, x15
+ 1fa0: d53bf40f mrs x15, s3_3_c15_c4_0
+ 1fa4: d51bf42f msr s3_3_c15_c4_1, x15
+ 1fa8: d53bf42f mrs x15, s3_3_c15_c4_1
+ 1fac: d51bf44f msr s3_3_c15_c4_2, x15
+ 1fb0: d53bf44f mrs x15, s3_3_c15_c4_2
+ 1fb4: d51bf46f msr s3_3_c15_c4_3, x15
+ 1fb8: d53bf46f mrs x15, s3_3_c15_c4_3
+ 1fbc: d51bf48f msr s3_3_c15_c4_4, x15
+ 1fc0: d53bf48f mrs x15, s3_3_c15_c4_4
+ 1fc4: d51bf4af msr s3_3_c15_c4_5, x15
+ 1fc8: d53bf4af mrs x15, s3_3_c15_c4_5
+ 1fcc: d51bf4cf msr s3_3_c15_c4_6, x15
+ 1fd0: d53bf4cf mrs x15, s3_3_c15_c4_6
+ 1fd4: d51bf4ef msr s3_3_c15_c4_7, x15
+ 1fd8: d53bf4ef mrs x15, s3_3_c15_c4_7
+ 1fdc: d51bf50f msr s3_3_c15_c5_0, x15
+ 1fe0: d53bf50f mrs x15, s3_3_c15_c5_0
+ 1fe4: d51bf52f msr s3_3_c15_c5_1, x15
+ 1fe8: d53bf52f mrs x15, s3_3_c15_c5_1
+ 1fec: d51bf54f msr s3_3_c15_c5_2, x15
+ 1ff0: d53bf54f mrs x15, s3_3_c15_c5_2
+ 1ff4: d51bf56f msr s3_3_c15_c5_3, x15
+ 1ff8: d53bf56f mrs x15, s3_3_c15_c5_3
+ 1ffc: d51bf58f msr s3_3_c15_c5_4, x15
+ 2000: d53bf58f mrs x15, s3_3_c15_c5_4
+ 2004: d51bf5af msr s3_3_c15_c5_5, x15
+ 2008: d53bf5af mrs x15, s3_3_c15_c5_5
+ 200c: d51bf5cf msr s3_3_c15_c5_6, x15
+ 2010: d53bf5cf mrs x15, s3_3_c15_c5_6
+ 2014: d51bf5ef msr s3_3_c15_c5_7, x15
+ 2018: d53bf5ef mrs x15, s3_3_c15_c5_7
+ 201c: d51bf60f msr s3_3_c15_c6_0, x15
+ 2020: d53bf60f mrs x15, s3_3_c15_c6_0
+ 2024: d51bf62f msr s3_3_c15_c6_1, x15
+ 2028: d53bf62f mrs x15, s3_3_c15_c6_1
+ 202c: d51bf64f msr s3_3_c15_c6_2, x15
+ 2030: d53bf64f mrs x15, s3_3_c15_c6_2
+ 2034: d51bf66f msr s3_3_c15_c6_3, x15
+ 2038: d53bf66f mrs x15, s3_3_c15_c6_3
+ 203c: d51bf68f msr s3_3_c15_c6_4, x15
+ 2040: d53bf68f mrs x15, s3_3_c15_c6_4
+ 2044: d51bf6af msr s3_3_c15_c6_5, x15
+ 2048: d53bf6af mrs x15, s3_3_c15_c6_5
+ 204c: d51bf6cf msr s3_3_c15_c6_6, x15
+ 2050: d53bf6cf mrs x15, s3_3_c15_c6_6
+ 2054: d51bf6ef msr s3_3_c15_c6_7, x15
+ 2058: d53bf6ef mrs x15, s3_3_c15_c6_7
+ 205c: d51bf70f msr s3_3_c15_c7_0, x15
+ 2060: d53bf70f mrs x15, s3_3_c15_c7_0
+ 2064: d51bf72f msr s3_3_c15_c7_1, x15
+ 2068: d53bf72f mrs x15, s3_3_c15_c7_1
+ 206c: d51bf74f msr s3_3_c15_c7_2, x15
+ 2070: d53bf74f mrs x15, s3_3_c15_c7_2
+ 2074: d51bf76f msr s3_3_c15_c7_3, x15
+ 2078: d53bf76f mrs x15, s3_3_c15_c7_3
+ 207c: d51bf78f msr s3_3_c15_c7_4, x15
+ 2080: d53bf78f mrs x15, s3_3_c15_c7_4
+ 2084: d51bf7af msr s3_3_c15_c7_5, x15
+ 2088: d53bf7af mrs x15, s3_3_c15_c7_5
+ 208c: d51bf7cf msr s3_3_c15_c7_6, x15
+ 2090: d53bf7cf mrs x15, s3_3_c15_c7_6
+ 2094: d51bf7ef msr s3_3_c15_c7_7, x15
+ 2098: d53bf7ef mrs x15, s3_3_c15_c7_7
+ 209c: d51bf80f msr s3_3_c15_c8_0, x15
+ 20a0: d53bf80f mrs x15, s3_3_c15_c8_0
+ 20a4: d51bf82f msr s3_3_c15_c8_1, x15
+ 20a8: d53bf82f mrs x15, s3_3_c15_c8_1
+ 20ac: d51bf84f msr s3_3_c15_c8_2, x15
+ 20b0: d53bf84f mrs x15, s3_3_c15_c8_2
+ 20b4: d51bf86f msr s3_3_c15_c8_3, x15
+ 20b8: d53bf86f mrs x15, s3_3_c15_c8_3
+ 20bc: d51bf88f msr s3_3_c15_c8_4, x15
+ 20c0: d53bf88f mrs x15, s3_3_c15_c8_4
+ 20c4: d51bf8af msr s3_3_c15_c8_5, x15
+ 20c8: d53bf8af mrs x15, s3_3_c15_c8_5
+ 20cc: d51bf8cf msr s3_3_c15_c8_6, x15
+ 20d0: d53bf8cf mrs x15, s3_3_c15_c8_6
+ 20d4: d51bf8ef msr s3_3_c15_c8_7, x15
+ 20d8: d53bf8ef mrs x15, s3_3_c15_c8_7
+ 20dc: d51bf90f msr s3_3_c15_c9_0, x15
+ 20e0: d53bf90f mrs x15, s3_3_c15_c9_0
+ 20e4: d51bf92f msr s3_3_c15_c9_1, x15
+ 20e8: d53bf92f mrs x15, s3_3_c15_c9_1
+ 20ec: d51bf94f msr s3_3_c15_c9_2, x15
+ 20f0: d53bf94f mrs x15, s3_3_c15_c9_2
+ 20f4: d51bf96f msr s3_3_c15_c9_3, x15
+ 20f8: d53bf96f mrs x15, s3_3_c15_c9_3
+ 20fc: d51bf98f msr s3_3_c15_c9_4, x15
+ 2100: d53bf98f mrs x15, s3_3_c15_c9_4
+ 2104: d51bf9af msr s3_3_c15_c9_5, x15
+ 2108: d53bf9af mrs x15, s3_3_c15_c9_5
+ 210c: d51bf9cf msr s3_3_c15_c9_6, x15
+ 2110: d53bf9cf mrs x15, s3_3_c15_c9_6
+ 2114: d51bf9ef msr s3_3_c15_c9_7, x15
+ 2118: d53bf9ef mrs x15, s3_3_c15_c9_7
+ 211c: d51bfa0f msr s3_3_c15_c10_0, x15
+ 2120: d53bfa0f mrs x15, s3_3_c15_c10_0
+ 2124: d51bfa2f msr s3_3_c15_c10_1, x15
+ 2128: d53bfa2f mrs x15, s3_3_c15_c10_1
+ 212c: d51bfa4f msr s3_3_c15_c10_2, x15
+ 2130: d53bfa4f mrs x15, s3_3_c15_c10_2
+ 2134: d51bfa6f msr s3_3_c15_c10_3, x15
+ 2138: d53bfa6f mrs x15, s3_3_c15_c10_3
+ 213c: d51bfa8f msr s3_3_c15_c10_4, x15
+ 2140: d53bfa8f mrs x15, s3_3_c15_c10_4
+ 2144: d51bfaaf msr s3_3_c15_c10_5, x15
+ 2148: d53bfaaf mrs x15, s3_3_c15_c10_5
+ 214c: d51bfacf msr s3_3_c15_c10_6, x15
+ 2150: d53bfacf mrs x15, s3_3_c15_c10_6
+ 2154: d51bfaef msr s3_3_c15_c10_7, x15
+ 2158: d53bfaef mrs x15, s3_3_c15_c10_7
+ 215c: d51bfb0f msr s3_3_c15_c11_0, x15
+ 2160: d53bfb0f mrs x15, s3_3_c15_c11_0
+ 2164: d51bfb2f msr s3_3_c15_c11_1, x15
+ 2168: d53bfb2f mrs x15, s3_3_c15_c11_1
+ 216c: d51bfb4f msr s3_3_c15_c11_2, x15
+ 2170: d53bfb4f mrs x15, s3_3_c15_c11_2
+ 2174: d51bfb6f msr s3_3_c15_c11_3, x15
+ 2178: d53bfb6f mrs x15, s3_3_c15_c11_3
+ 217c: d51bfb8f msr s3_3_c15_c11_4, x15
+ 2180: d53bfb8f mrs x15, s3_3_c15_c11_4
+ 2184: d51bfbaf msr s3_3_c15_c11_5, x15
+ 2188: d53bfbaf mrs x15, s3_3_c15_c11_5
+ 218c: d51bfbcf msr s3_3_c15_c11_6, x15
+ 2190: d53bfbcf mrs x15, s3_3_c15_c11_6
+ 2194: d51bfbef msr s3_3_c15_c11_7, x15
+ 2198: d53bfbef mrs x15, s3_3_c15_c11_7
+ 219c: d51bfc0f msr s3_3_c15_c12_0, x15
+ 21a0: d53bfc0f mrs x15, s3_3_c15_c12_0
+ 21a4: d51bfc2f msr s3_3_c15_c12_1, x15
+ 21a8: d53bfc2f mrs x15, s3_3_c15_c12_1
+ 21ac: d51bfc4f msr s3_3_c15_c12_2, x15
+ 21b0: d53bfc4f mrs x15, s3_3_c15_c12_2
+ 21b4: d51bfc6f msr s3_3_c15_c12_3, x15
+ 21b8: d53bfc6f mrs x15, s3_3_c15_c12_3
+ 21bc: d51bfc8f msr s3_3_c15_c12_4, x15
+ 21c0: d53bfc8f mrs x15, s3_3_c15_c12_4
+ 21c4: d51bfcaf msr s3_3_c15_c12_5, x15
+ 21c8: d53bfcaf mrs x15, s3_3_c15_c12_5
+ 21cc: d51bfccf msr s3_3_c15_c12_6, x15
+ 21d0: d53bfccf mrs x15, s3_3_c15_c12_6
+ 21d4: d51bfcef msr s3_3_c15_c12_7, x15
+ 21d8: d53bfcef mrs x15, s3_3_c15_c12_7
+ 21dc: d51bfd0f msr s3_3_c15_c13_0, x15
+ 21e0: d53bfd0f mrs x15, s3_3_c15_c13_0
+ 21e4: d51bfd2f msr s3_3_c15_c13_1, x15
+ 21e8: d53bfd2f mrs x15, s3_3_c15_c13_1
+ 21ec: d51bfd4f msr s3_3_c15_c13_2, x15
+ 21f0: d53bfd4f mrs x15, s3_3_c15_c13_2
+ 21f4: d51bfd6f msr s3_3_c15_c13_3, x15
+ 21f8: d53bfd6f mrs x15, s3_3_c15_c13_3
+ 21fc: d51bfd8f msr s3_3_c15_c13_4, x15
+ 2200: d53bfd8f mrs x15, s3_3_c15_c13_4
+ 2204: d51bfdaf msr s3_3_c15_c13_5, x15
+ 2208: d53bfdaf mrs x15, s3_3_c15_c13_5
+ 220c: d51bfdcf msr s3_3_c15_c13_6, x15
+ 2210: d53bfdcf mrs x15, s3_3_c15_c13_6
+ 2214: d51bfdef msr s3_3_c15_c13_7, x15
+ 2218: d53bfdef mrs x15, s3_3_c15_c13_7
+ 221c: d51bfe0f msr s3_3_c15_c14_0, x15
+ 2220: d53bfe0f mrs x15, s3_3_c15_c14_0
+ 2224: d51bfe2f msr s3_3_c15_c14_1, x15
+ 2228: d53bfe2f mrs x15, s3_3_c15_c14_1
+ 222c: d51bfe4f msr s3_3_c15_c14_2, x15
+ 2230: d53bfe4f mrs x15, s3_3_c15_c14_2
+ 2234: d51bfe6f msr s3_3_c15_c14_3, x15
+ 2238: d53bfe6f mrs x15, s3_3_c15_c14_3
+ 223c: d51bfe8f msr s3_3_c15_c14_4, x15
+ 2240: d53bfe8f mrs x15, s3_3_c15_c14_4
+ 2244: d51bfeaf msr s3_3_c15_c14_5, x15
+ 2248: d53bfeaf mrs x15, s3_3_c15_c14_5
+ 224c: d51bfecf msr s3_3_c15_c14_6, x15
+ 2250: d53bfecf mrs x15, s3_3_c15_c14_6
+ 2254: d51bfeef msr s3_3_c15_c14_7, x15
+ 2258: d53bfeef mrs x15, s3_3_c15_c14_7
+ 225c: d51bff0f msr s3_3_c15_c15_0, x15
+ 2260: d53bff0f mrs x15, s3_3_c15_c15_0
+ 2264: d51bff2f msr s3_3_c15_c15_1, x15
+ 2268: d53bff2f mrs x15, s3_3_c15_c15_1
+ 226c: d51bff4f msr s3_3_c15_c15_2, x15
+ 2270: d53bff4f mrs x15, s3_3_c15_c15_2
+ 2274: d51bff6f msr s3_3_c15_c15_3, x15
+ 2278: d53bff6f mrs x15, s3_3_c15_c15_3
+ 227c: d51bff8f msr s3_3_c15_c15_4, x15
+ 2280: d53bff8f mrs x15, s3_3_c15_c15_4
+ 2284: d51bffaf msr s3_3_c15_c15_5, x15
+ 2288: d53bffaf mrs x15, s3_3_c15_c15_5
+ 228c: d51bffcf msr s3_3_c15_c15_6, x15
+ 2290: d53bffcf mrs x15, s3_3_c15_c15_6
+ 2294: d51bffef msr s3_3_c15_c15_7, x15
+ 2298: d53bffef mrs x15, s3_3_c15_c15_7
+ 229c: d51cb00f msr s3_4_c11_c0_0, x15
+ 22a0: d53cb00f mrs x15, s3_4_c11_c0_0
+ 22a4: d51cb02f msr s3_4_c11_c0_1, x15
+ 22a8: d53cb02f mrs x15, s3_4_c11_c0_1
+ 22ac: d51cb04f msr s3_4_c11_c0_2, x15
+ 22b0: d53cb04f mrs x15, s3_4_c11_c0_2
+ 22b4: d51cb06f msr s3_4_c11_c0_3, x15
+ 22b8: d53cb06f mrs x15, s3_4_c11_c0_3
+ 22bc: d51cb08f msr s3_4_c11_c0_4, x15
+ 22c0: d53cb08f mrs x15, s3_4_c11_c0_4
+ 22c4: d51cb0af msr s3_4_c11_c0_5, x15
+ 22c8: d53cb0af mrs x15, s3_4_c11_c0_5
+ 22cc: d51cb0cf msr s3_4_c11_c0_6, x15
+ 22d0: d53cb0cf mrs x15, s3_4_c11_c0_6
+ 22d4: d51cb0ef msr s3_4_c11_c0_7, x15
+ 22d8: d53cb0ef mrs x15, s3_4_c11_c0_7
+ 22dc: d51cb10f msr s3_4_c11_c1_0, x15
+ 22e0: d53cb10f mrs x15, s3_4_c11_c1_0
+ 22e4: d51cb12f msr s3_4_c11_c1_1, x15
+ 22e8: d53cb12f mrs x15, s3_4_c11_c1_1
+ 22ec: d51cb14f msr s3_4_c11_c1_2, x15
+ 22f0: d53cb14f mrs x15, s3_4_c11_c1_2
+ 22f4: d51cb16f msr s3_4_c11_c1_3, x15
+ 22f8: d53cb16f mrs x15, s3_4_c11_c1_3
+ 22fc: d51cb18f msr s3_4_c11_c1_4, x15
+ 2300: d53cb18f mrs x15, s3_4_c11_c1_4
+ 2304: d51cb1af msr s3_4_c11_c1_5, x15
+ 2308: d53cb1af mrs x15, s3_4_c11_c1_5
+ 230c: d51cb1cf msr s3_4_c11_c1_6, x15
+ 2310: d53cb1cf mrs x15, s3_4_c11_c1_6
+ 2314: d51cb1ef msr s3_4_c11_c1_7, x15
+ 2318: d53cb1ef mrs x15, s3_4_c11_c1_7
+ 231c: d51cb20f msr s3_4_c11_c2_0, x15
+ 2320: d53cb20f mrs x15, s3_4_c11_c2_0
+ 2324: d51cb22f msr s3_4_c11_c2_1, x15
+ 2328: d53cb22f mrs x15, s3_4_c11_c2_1
+ 232c: d51cb24f msr s3_4_c11_c2_2, x15
+ 2330: d53cb24f mrs x15, s3_4_c11_c2_2
+ 2334: d51cb26f msr s3_4_c11_c2_3, x15
+ 2338: d53cb26f mrs x15, s3_4_c11_c2_3
+ 233c: d51cb28f msr s3_4_c11_c2_4, x15
+ 2340: d53cb28f mrs x15, s3_4_c11_c2_4
+ 2344: d51cb2af msr s3_4_c11_c2_5, x15
+ 2348: d53cb2af mrs x15, s3_4_c11_c2_5
+ 234c: d51cb2cf msr s3_4_c11_c2_6, x15
+ 2350: d53cb2cf mrs x15, s3_4_c11_c2_6
+ 2354: d51cb2ef msr s3_4_c11_c2_7, x15
+ 2358: d53cb2ef mrs x15, s3_4_c11_c2_7
+ 235c: d51cb30f msr s3_4_c11_c3_0, x15
+ 2360: d53cb30f mrs x15, s3_4_c11_c3_0
+ 2364: d51cb32f msr s3_4_c11_c3_1, x15
+ 2368: d53cb32f mrs x15, s3_4_c11_c3_1
+ 236c: d51cb34f msr s3_4_c11_c3_2, x15
+ 2370: d53cb34f mrs x15, s3_4_c11_c3_2
+ 2374: d51cb36f msr s3_4_c11_c3_3, x15
+ 2378: d53cb36f mrs x15, s3_4_c11_c3_3
+ 237c: d51cb38f msr s3_4_c11_c3_4, x15
+ 2380: d53cb38f mrs x15, s3_4_c11_c3_4
+ 2384: d51cb3af msr s3_4_c11_c3_5, x15
+ 2388: d53cb3af mrs x15, s3_4_c11_c3_5
+ 238c: d51cb3cf msr s3_4_c11_c3_6, x15
+ 2390: d53cb3cf mrs x15, s3_4_c11_c3_6
+ 2394: d51cb3ef msr s3_4_c11_c3_7, x15
+ 2398: d53cb3ef mrs x15, s3_4_c11_c3_7
+ 239c: d51cb40f msr s3_4_c11_c4_0, x15
+ 23a0: d53cb40f mrs x15, s3_4_c11_c4_0
+ 23a4: d51cb42f msr s3_4_c11_c4_1, x15
+ 23a8: d53cb42f mrs x15, s3_4_c11_c4_1
+ 23ac: d51cb44f msr s3_4_c11_c4_2, x15
+ 23b0: d53cb44f mrs x15, s3_4_c11_c4_2
+ 23b4: d51cb46f msr s3_4_c11_c4_3, x15
+ 23b8: d53cb46f mrs x15, s3_4_c11_c4_3
+ 23bc: d51cb48f msr s3_4_c11_c4_4, x15
+ 23c0: d53cb48f mrs x15, s3_4_c11_c4_4
+ 23c4: d51cb4af msr s3_4_c11_c4_5, x15
+ 23c8: d53cb4af mrs x15, s3_4_c11_c4_5
+ 23cc: d51cb4cf msr s3_4_c11_c4_6, x15
+ 23d0: d53cb4cf mrs x15, s3_4_c11_c4_6
+ 23d4: d51cb4ef msr s3_4_c11_c4_7, x15
+ 23d8: d53cb4ef mrs x15, s3_4_c11_c4_7
+ 23dc: d51cb50f msr s3_4_c11_c5_0, x15
+ 23e0: d53cb50f mrs x15, s3_4_c11_c5_0
+ 23e4: d51cb52f msr s3_4_c11_c5_1, x15
+ 23e8: d53cb52f mrs x15, s3_4_c11_c5_1
+ 23ec: d51cb54f msr s3_4_c11_c5_2, x15
+ 23f0: d53cb54f mrs x15, s3_4_c11_c5_2
+ 23f4: d51cb56f msr s3_4_c11_c5_3, x15
+ 23f8: d53cb56f mrs x15, s3_4_c11_c5_3
+ 23fc: d51cb58f msr s3_4_c11_c5_4, x15
+ 2400: d53cb58f mrs x15, s3_4_c11_c5_4
+ 2404: d51cb5af msr s3_4_c11_c5_5, x15
+ 2408: d53cb5af mrs x15, s3_4_c11_c5_5
+ 240c: d51cb5cf msr s3_4_c11_c5_6, x15
+ 2410: d53cb5cf mrs x15, s3_4_c11_c5_6
+ 2414: d51cb5ef msr s3_4_c11_c5_7, x15
+ 2418: d53cb5ef mrs x15, s3_4_c11_c5_7
+ 241c: d51cb60f msr s3_4_c11_c6_0, x15
+ 2420: d53cb60f mrs x15, s3_4_c11_c6_0
+ 2424: d51cb62f msr s3_4_c11_c6_1, x15
+ 2428: d53cb62f mrs x15, s3_4_c11_c6_1
+ 242c: d51cb64f msr s3_4_c11_c6_2, x15
+ 2430: d53cb64f mrs x15, s3_4_c11_c6_2
+ 2434: d51cb66f msr s3_4_c11_c6_3, x15
+ 2438: d53cb66f mrs x15, s3_4_c11_c6_3
+ 243c: d51cb68f msr s3_4_c11_c6_4, x15
+ 2440: d53cb68f mrs x15, s3_4_c11_c6_4
+ 2444: d51cb6af msr s3_4_c11_c6_5, x15
+ 2448: d53cb6af mrs x15, s3_4_c11_c6_5
+ 244c: d51cb6cf msr s3_4_c11_c6_6, x15
+ 2450: d53cb6cf mrs x15, s3_4_c11_c6_6
+ 2454: d51cb6ef msr s3_4_c11_c6_7, x15
+ 2458: d53cb6ef mrs x15, s3_4_c11_c6_7
+ 245c: d51cb70f msr s3_4_c11_c7_0, x15
+ 2460: d53cb70f mrs x15, s3_4_c11_c7_0
+ 2464: d51cb72f msr s3_4_c11_c7_1, x15
+ 2468: d53cb72f mrs x15, s3_4_c11_c7_1
+ 246c: d51cb74f msr s3_4_c11_c7_2, x15
+ 2470: d53cb74f mrs x15, s3_4_c11_c7_2
+ 2474: d51cb76f msr s3_4_c11_c7_3, x15
+ 2478: d53cb76f mrs x15, s3_4_c11_c7_3
+ 247c: d51cb78f msr s3_4_c11_c7_4, x15
+ 2480: d53cb78f mrs x15, s3_4_c11_c7_4
+ 2484: d51cb7af msr s3_4_c11_c7_5, x15
+ 2488: d53cb7af mrs x15, s3_4_c11_c7_5
+ 248c: d51cb7cf msr s3_4_c11_c7_6, x15
+ 2490: d53cb7cf mrs x15, s3_4_c11_c7_6
+ 2494: d51cb7ef msr s3_4_c11_c7_7, x15
+ 2498: d53cb7ef mrs x15, s3_4_c11_c7_7
+ 249c: d51cb80f msr s3_4_c11_c8_0, x15
+ 24a0: d53cb80f mrs x15, s3_4_c11_c8_0
+ 24a4: d51cb82f msr s3_4_c11_c8_1, x15
+ 24a8: d53cb82f mrs x15, s3_4_c11_c8_1
+ 24ac: d51cb84f msr s3_4_c11_c8_2, x15
+ 24b0: d53cb84f mrs x15, s3_4_c11_c8_2
+ 24b4: d51cb86f msr s3_4_c11_c8_3, x15
+ 24b8: d53cb86f mrs x15, s3_4_c11_c8_3
+ 24bc: d51cb88f msr s3_4_c11_c8_4, x15
+ 24c0: d53cb88f mrs x15, s3_4_c11_c8_4
+ 24c4: d51cb8af msr s3_4_c11_c8_5, x15
+ 24c8: d53cb8af mrs x15, s3_4_c11_c8_5
+ 24cc: d51cb8cf msr s3_4_c11_c8_6, x15
+ 24d0: d53cb8cf mrs x15, s3_4_c11_c8_6
+ 24d4: d51cb8ef msr s3_4_c11_c8_7, x15
+ 24d8: d53cb8ef mrs x15, s3_4_c11_c8_7
+ 24dc: d51cb90f msr s3_4_c11_c9_0, x15
+ 24e0: d53cb90f mrs x15, s3_4_c11_c9_0
+ 24e4: d51cb92f msr s3_4_c11_c9_1, x15
+ 24e8: d53cb92f mrs x15, s3_4_c11_c9_1
+ 24ec: d51cb94f msr s3_4_c11_c9_2, x15
+ 24f0: d53cb94f mrs x15, s3_4_c11_c9_2
+ 24f4: d51cb96f msr s3_4_c11_c9_3, x15
+ 24f8: d53cb96f mrs x15, s3_4_c11_c9_3
+ 24fc: d51cb98f msr s3_4_c11_c9_4, x15
+ 2500: d53cb98f mrs x15, s3_4_c11_c9_4
+ 2504: d51cb9af msr s3_4_c11_c9_5, x15
+ 2508: d53cb9af mrs x15, s3_4_c11_c9_5
+ 250c: d51cb9cf msr s3_4_c11_c9_6, x15
+ 2510: d53cb9cf mrs x15, s3_4_c11_c9_6
+ 2514: d51cb9ef msr s3_4_c11_c9_7, x15
+ 2518: d53cb9ef mrs x15, s3_4_c11_c9_7
+ 251c: d51cba0f msr s3_4_c11_c10_0, x15
+ 2520: d53cba0f mrs x15, s3_4_c11_c10_0
+ 2524: d51cba2f msr s3_4_c11_c10_1, x15
+ 2528: d53cba2f mrs x15, s3_4_c11_c10_1
+ 252c: d51cba4f msr s3_4_c11_c10_2, x15
+ 2530: d53cba4f mrs x15, s3_4_c11_c10_2
+ 2534: d51cba6f msr s3_4_c11_c10_3, x15
+ 2538: d53cba6f mrs x15, s3_4_c11_c10_3
+ 253c: d51cba8f msr s3_4_c11_c10_4, x15
+ 2540: d53cba8f mrs x15, s3_4_c11_c10_4
+ 2544: d51cbaaf msr s3_4_c11_c10_5, x15
+ 2548: d53cbaaf mrs x15, s3_4_c11_c10_5
+ 254c: d51cbacf msr s3_4_c11_c10_6, x15
+ 2550: d53cbacf mrs x15, s3_4_c11_c10_6
+ 2554: d51cbaef msr s3_4_c11_c10_7, x15
+ 2558: d53cbaef mrs x15, s3_4_c11_c10_7
+ 255c: d51cbb0f msr s3_4_c11_c11_0, x15
+ 2560: d53cbb0f mrs x15, s3_4_c11_c11_0
+ 2564: d51cbb2f msr s3_4_c11_c11_1, x15
+ 2568: d53cbb2f mrs x15, s3_4_c11_c11_1
+ 256c: d51cbb4f msr s3_4_c11_c11_2, x15
+ 2570: d53cbb4f mrs x15, s3_4_c11_c11_2
+ 2574: d51cbb6f msr s3_4_c11_c11_3, x15
+ 2578: d53cbb6f mrs x15, s3_4_c11_c11_3
+ 257c: d51cbb8f msr s3_4_c11_c11_4, x15
+ 2580: d53cbb8f mrs x15, s3_4_c11_c11_4
+ 2584: d51cbbaf msr s3_4_c11_c11_5, x15
+ 2588: d53cbbaf mrs x15, s3_4_c11_c11_5
+ 258c: d51cbbcf msr s3_4_c11_c11_6, x15
+ 2590: d53cbbcf mrs x15, s3_4_c11_c11_6
+ 2594: d51cbbef msr s3_4_c11_c11_7, x15
+ 2598: d53cbbef mrs x15, s3_4_c11_c11_7
+ 259c: d51cbc0f msr s3_4_c11_c12_0, x15
+ 25a0: d53cbc0f mrs x15, s3_4_c11_c12_0
+ 25a4: d51cbc2f msr s3_4_c11_c12_1, x15
+ 25a8: d53cbc2f mrs x15, s3_4_c11_c12_1
+ 25ac: d51cbc4f msr s3_4_c11_c12_2, x15
+ 25b0: d53cbc4f mrs x15, s3_4_c11_c12_2
+ 25b4: d51cbc6f msr s3_4_c11_c12_3, x15
+ 25b8: d53cbc6f mrs x15, s3_4_c11_c12_3
+ 25bc: d51cbc8f msr s3_4_c11_c12_4, x15
+ 25c0: d53cbc8f mrs x15, s3_4_c11_c12_4
+ 25c4: d51cbcaf msr s3_4_c11_c12_5, x15
+ 25c8: d53cbcaf mrs x15, s3_4_c11_c12_5
+ 25cc: d51cbccf msr s3_4_c11_c12_6, x15
+ 25d0: d53cbccf mrs x15, s3_4_c11_c12_6
+ 25d4: d51cbcef msr s3_4_c11_c12_7, x15
+ 25d8: d53cbcef mrs x15, s3_4_c11_c12_7
+ 25dc: d51cbd0f msr s3_4_c11_c13_0, x15
+ 25e0: d53cbd0f mrs x15, s3_4_c11_c13_0
+ 25e4: d51cbd2f msr s3_4_c11_c13_1, x15
+ 25e8: d53cbd2f mrs x15, s3_4_c11_c13_1
+ 25ec: d51cbd4f msr s3_4_c11_c13_2, x15
+ 25f0: d53cbd4f mrs x15, s3_4_c11_c13_2
+ 25f4: d51cbd6f msr s3_4_c11_c13_3, x15
+ 25f8: d53cbd6f mrs x15, s3_4_c11_c13_3
+ 25fc: d51cbd8f msr s3_4_c11_c13_4, x15
+ 2600: d53cbd8f mrs x15, s3_4_c11_c13_4
+ 2604: d51cbdaf msr s3_4_c11_c13_5, x15
+ 2608: d53cbdaf mrs x15, s3_4_c11_c13_5
+ 260c: d51cbdcf msr s3_4_c11_c13_6, x15
+ 2610: d53cbdcf mrs x15, s3_4_c11_c13_6
+ 2614: d51cbdef msr s3_4_c11_c13_7, x15
+ 2618: d53cbdef mrs x15, s3_4_c11_c13_7
+ 261c: d51cbe0f msr s3_4_c11_c14_0, x15
+ 2620: d53cbe0f mrs x15, s3_4_c11_c14_0
+ 2624: d51cbe2f msr s3_4_c11_c14_1, x15
+ 2628: d53cbe2f mrs x15, s3_4_c11_c14_1
+ 262c: d51cbe4f msr s3_4_c11_c14_2, x15
+ 2630: d53cbe4f mrs x15, s3_4_c11_c14_2
+ 2634: d51cbe6f msr s3_4_c11_c14_3, x15
+ 2638: d53cbe6f mrs x15, s3_4_c11_c14_3
+ 263c: d51cbe8f msr s3_4_c11_c14_4, x15
+ 2640: d53cbe8f mrs x15, s3_4_c11_c14_4
+ 2644: d51cbeaf msr s3_4_c11_c14_5, x15
+ 2648: d53cbeaf mrs x15, s3_4_c11_c14_5
+ 264c: d51cbecf msr s3_4_c11_c14_6, x15
+ 2650: d53cbecf mrs x15, s3_4_c11_c14_6
+ 2654: d51cbeef msr s3_4_c11_c14_7, x15
+ 2658: d53cbeef mrs x15, s3_4_c11_c14_7
+ 265c: d51cbf0f msr s3_4_c11_c15_0, x15
+ 2660: d53cbf0f mrs x15, s3_4_c11_c15_0
+ 2664: d51cbf2f msr s3_4_c11_c15_1, x15
+ 2668: d53cbf2f mrs x15, s3_4_c11_c15_1
+ 266c: d51cbf4f msr s3_4_c11_c15_2, x15
+ 2670: d53cbf4f mrs x15, s3_4_c11_c15_2
+ 2674: d51cbf6f msr s3_4_c11_c15_3, x15
+ 2678: d53cbf6f mrs x15, s3_4_c11_c15_3
+ 267c: d51cbf8f msr s3_4_c11_c15_4, x15
+ 2680: d53cbf8f mrs x15, s3_4_c11_c15_4
+ 2684: d51cbfaf msr s3_4_c11_c15_5, x15
+ 2688: d53cbfaf mrs x15, s3_4_c11_c15_5
+ 268c: d51cbfcf msr s3_4_c11_c15_6, x15
+ 2690: d53cbfcf mrs x15, s3_4_c11_c15_6
+ 2694: d51cbfef msr s3_4_c11_c15_7, x15
+ 2698: d53cbfef mrs x15, s3_4_c11_c15_7
+ 269c: d51cf00f msr s3_4_c15_c0_0, x15
+ 26a0: d53cf00f mrs x15, s3_4_c15_c0_0
+ 26a4: d51cf02f msr s3_4_c15_c0_1, x15
+ 26a8: d53cf02f mrs x15, s3_4_c15_c0_1
+ 26ac: d51cf04f msr s3_4_c15_c0_2, x15
+ 26b0: d53cf04f mrs x15, s3_4_c15_c0_2
+ 26b4: d51cf06f msr s3_4_c15_c0_3, x15
+ 26b8: d53cf06f mrs x15, s3_4_c15_c0_3
+ 26bc: d51cf08f msr s3_4_c15_c0_4, x15
+ 26c0: d53cf08f mrs x15, s3_4_c15_c0_4
+ 26c4: d51cf0af msr s3_4_c15_c0_5, x15
+ 26c8: d53cf0af mrs x15, s3_4_c15_c0_5
+ 26cc: d51cf0cf msr s3_4_c15_c0_6, x15
+ 26d0: d53cf0cf mrs x15, s3_4_c15_c0_6
+ 26d4: d51cf0ef msr s3_4_c15_c0_7, x15
+ 26d8: d53cf0ef mrs x15, s3_4_c15_c0_7
+ 26dc: d51cf10f msr s3_4_c15_c1_0, x15
+ 26e0: d53cf10f mrs x15, s3_4_c15_c1_0
+ 26e4: d51cf12f msr s3_4_c15_c1_1, x15
+ 26e8: d53cf12f mrs x15, s3_4_c15_c1_1
+ 26ec: d51cf14f msr s3_4_c15_c1_2, x15
+ 26f0: d53cf14f mrs x15, s3_4_c15_c1_2
+ 26f4: d51cf16f msr s3_4_c15_c1_3, x15
+ 26f8: d53cf16f mrs x15, s3_4_c15_c1_3
+ 26fc: d51cf18f msr s3_4_c15_c1_4, x15
+ 2700: d53cf18f mrs x15, s3_4_c15_c1_4
+ 2704: d51cf1af msr s3_4_c15_c1_5, x15
+ 2708: d53cf1af mrs x15, s3_4_c15_c1_5
+ 270c: d51cf1cf msr s3_4_c15_c1_6, x15
+ 2710: d53cf1cf mrs x15, s3_4_c15_c1_6
+ 2714: d51cf1ef msr s3_4_c15_c1_7, x15
+ 2718: d53cf1ef mrs x15, s3_4_c15_c1_7
+ 271c: d51cf20f msr s3_4_c15_c2_0, x15
+ 2720: d53cf20f mrs x15, s3_4_c15_c2_0
+ 2724: d51cf22f msr s3_4_c15_c2_1, x15
+ 2728: d53cf22f mrs x15, s3_4_c15_c2_1
+ 272c: d51cf24f msr s3_4_c15_c2_2, x15
+ 2730: d53cf24f mrs x15, s3_4_c15_c2_2
+ 2734: d51cf26f msr s3_4_c15_c2_3, x15
+ 2738: d53cf26f mrs x15, s3_4_c15_c2_3
+ 273c: d51cf28f msr s3_4_c15_c2_4, x15
+ 2740: d53cf28f mrs x15, s3_4_c15_c2_4
+ 2744: d51cf2af msr s3_4_c15_c2_5, x15
+ 2748: d53cf2af mrs x15, s3_4_c15_c2_5
+ 274c: d51cf2cf msr s3_4_c15_c2_6, x15
+ 2750: d53cf2cf mrs x15, s3_4_c15_c2_6
+ 2754: d51cf2ef msr s3_4_c15_c2_7, x15
+ 2758: d53cf2ef mrs x15, s3_4_c15_c2_7
+ 275c: d51cf30f msr s3_4_c15_c3_0, x15
+ 2760: d53cf30f mrs x15, s3_4_c15_c3_0
+ 2764: d51cf32f msr s3_4_c15_c3_1, x15
+ 2768: d53cf32f mrs x15, s3_4_c15_c3_1
+ 276c: d51cf34f msr s3_4_c15_c3_2, x15
+ 2770: d53cf34f mrs x15, s3_4_c15_c3_2
+ 2774: d51cf36f msr s3_4_c15_c3_3, x15
+ 2778: d53cf36f mrs x15, s3_4_c15_c3_3
+ 277c: d51cf38f msr s3_4_c15_c3_4, x15
+ 2780: d53cf38f mrs x15, s3_4_c15_c3_4
+ 2784: d51cf3af msr s3_4_c15_c3_5, x15
+ 2788: d53cf3af mrs x15, s3_4_c15_c3_5
+ 278c: d51cf3cf msr s3_4_c15_c3_6, x15
+ 2790: d53cf3cf mrs x15, s3_4_c15_c3_6
+ 2794: d51cf3ef msr s3_4_c15_c3_7, x15
+ 2798: d53cf3ef mrs x15, s3_4_c15_c3_7
+ 279c: d51cf40f msr s3_4_c15_c4_0, x15
+ 27a0: d53cf40f mrs x15, s3_4_c15_c4_0
+ 27a4: d51cf42f msr s3_4_c15_c4_1, x15
+ 27a8: d53cf42f mrs x15, s3_4_c15_c4_1
+ 27ac: d51cf44f msr s3_4_c15_c4_2, x15
+ 27b0: d53cf44f mrs x15, s3_4_c15_c4_2
+ 27b4: d51cf46f msr s3_4_c15_c4_3, x15
+ 27b8: d53cf46f mrs x15, s3_4_c15_c4_3
+ 27bc: d51cf48f msr s3_4_c15_c4_4, x15
+ 27c0: d53cf48f mrs x15, s3_4_c15_c4_4
+ 27c4: d51cf4af msr s3_4_c15_c4_5, x15
+ 27c8: d53cf4af mrs x15, s3_4_c15_c4_5
+ 27cc: d51cf4cf msr s3_4_c15_c4_6, x15
+ 27d0: d53cf4cf mrs x15, s3_4_c15_c4_6
+ 27d4: d51cf4ef msr s3_4_c15_c4_7, x15
+ 27d8: d53cf4ef mrs x15, s3_4_c15_c4_7
+ 27dc: d51cf50f msr s3_4_c15_c5_0, x15
+ 27e0: d53cf50f mrs x15, s3_4_c15_c5_0
+ 27e4: d51cf52f msr s3_4_c15_c5_1, x15
+ 27e8: d53cf52f mrs x15, s3_4_c15_c5_1
+ 27ec: d51cf54f msr s3_4_c15_c5_2, x15
+ 27f0: d53cf54f mrs x15, s3_4_c15_c5_2
+ 27f4: d51cf56f msr s3_4_c15_c5_3, x15
+ 27f8: d53cf56f mrs x15, s3_4_c15_c5_3
+ 27fc: d51cf58f msr s3_4_c15_c5_4, x15
+ 2800: d53cf58f mrs x15, s3_4_c15_c5_4
+ 2804: d51cf5af msr s3_4_c15_c5_5, x15
+ 2808: d53cf5af mrs x15, s3_4_c15_c5_5
+ 280c: d51cf5cf msr s3_4_c15_c5_6, x15
+ 2810: d53cf5cf mrs x15, s3_4_c15_c5_6
+ 2814: d51cf5ef msr s3_4_c15_c5_7, x15
+ 2818: d53cf5ef mrs x15, s3_4_c15_c5_7
+ 281c: d51cf60f msr s3_4_c15_c6_0, x15
+ 2820: d53cf60f mrs x15, s3_4_c15_c6_0
+ 2824: d51cf62f msr s3_4_c15_c6_1, x15
+ 2828: d53cf62f mrs x15, s3_4_c15_c6_1
+ 282c: d51cf64f msr s3_4_c15_c6_2, x15
+ 2830: d53cf64f mrs x15, s3_4_c15_c6_2
+ 2834: d51cf66f msr s3_4_c15_c6_3, x15
+ 2838: d53cf66f mrs x15, s3_4_c15_c6_3
+ 283c: d51cf68f msr s3_4_c15_c6_4, x15
+ 2840: d53cf68f mrs x15, s3_4_c15_c6_4
+ 2844: d51cf6af msr s3_4_c15_c6_5, x15
+ 2848: d53cf6af mrs x15, s3_4_c15_c6_5
+ 284c: d51cf6cf msr s3_4_c15_c6_6, x15
+ 2850: d53cf6cf mrs x15, s3_4_c15_c6_6
+ 2854: d51cf6ef msr s3_4_c15_c6_7, x15
+ 2858: d53cf6ef mrs x15, s3_4_c15_c6_7
+ 285c: d51cf70f msr s3_4_c15_c7_0, x15
+ 2860: d53cf70f mrs x15, s3_4_c15_c7_0
+ 2864: d51cf72f msr s3_4_c15_c7_1, x15
+ 2868: d53cf72f mrs x15, s3_4_c15_c7_1
+ 286c: d51cf74f msr s3_4_c15_c7_2, x15
+ 2870: d53cf74f mrs x15, s3_4_c15_c7_2
+ 2874: d51cf76f msr s3_4_c15_c7_3, x15
+ 2878: d53cf76f mrs x15, s3_4_c15_c7_3
+ 287c: d51cf78f msr s3_4_c15_c7_4, x15
+ 2880: d53cf78f mrs x15, s3_4_c15_c7_4
+ 2884: d51cf7af msr s3_4_c15_c7_5, x15
+ 2888: d53cf7af mrs x15, s3_4_c15_c7_5
+ 288c: d51cf7cf msr s3_4_c15_c7_6, x15
+ 2890: d53cf7cf mrs x15, s3_4_c15_c7_6
+ 2894: d51cf7ef msr s3_4_c15_c7_7, x15
+ 2898: d53cf7ef mrs x15, s3_4_c15_c7_7
+ 289c: d51cf80f msr s3_4_c15_c8_0, x15
+ 28a0: d53cf80f mrs x15, s3_4_c15_c8_0
+ 28a4: d51cf82f msr s3_4_c15_c8_1, x15
+ 28a8: d53cf82f mrs x15, s3_4_c15_c8_1
+ 28ac: d51cf84f msr s3_4_c15_c8_2, x15
+ 28b0: d53cf84f mrs x15, s3_4_c15_c8_2
+ 28b4: d51cf86f msr s3_4_c15_c8_3, x15
+ 28b8: d53cf86f mrs x15, s3_4_c15_c8_3
+ 28bc: d51cf88f msr s3_4_c15_c8_4, x15
+ 28c0: d53cf88f mrs x15, s3_4_c15_c8_4
+ 28c4: d51cf8af msr s3_4_c15_c8_5, x15
+ 28c8: d53cf8af mrs x15, s3_4_c15_c8_5
+ 28cc: d51cf8cf msr s3_4_c15_c8_6, x15
+ 28d0: d53cf8cf mrs x15, s3_4_c15_c8_6
+ 28d4: d51cf8ef msr s3_4_c15_c8_7, x15
+ 28d8: d53cf8ef mrs x15, s3_4_c15_c8_7
+ 28dc: d51cf90f msr s3_4_c15_c9_0, x15
+ 28e0: d53cf90f mrs x15, s3_4_c15_c9_0
+ 28e4: d51cf92f msr s3_4_c15_c9_1, x15
+ 28e8: d53cf92f mrs x15, s3_4_c15_c9_1
+ 28ec: d51cf94f msr s3_4_c15_c9_2, x15
+ 28f0: d53cf94f mrs x15, s3_4_c15_c9_2
+ 28f4: d51cf96f msr s3_4_c15_c9_3, x15
+ 28f8: d53cf96f mrs x15, s3_4_c15_c9_3
+ 28fc: d51cf98f msr s3_4_c15_c9_4, x15
+ 2900: d53cf98f mrs x15, s3_4_c15_c9_4
+ 2904: d51cf9af msr s3_4_c15_c9_5, x15
+ 2908: d53cf9af mrs x15, s3_4_c15_c9_5
+ 290c: d51cf9cf msr s3_4_c15_c9_6, x15
+ 2910: d53cf9cf mrs x15, s3_4_c15_c9_6
+ 2914: d51cf9ef msr s3_4_c15_c9_7, x15
+ 2918: d53cf9ef mrs x15, s3_4_c15_c9_7
+ 291c: d51cfa0f msr s3_4_c15_c10_0, x15
+ 2920: d53cfa0f mrs x15, s3_4_c15_c10_0
+ 2924: d51cfa2f msr s3_4_c15_c10_1, x15
+ 2928: d53cfa2f mrs x15, s3_4_c15_c10_1
+ 292c: d51cfa4f msr s3_4_c15_c10_2, x15
+ 2930: d53cfa4f mrs x15, s3_4_c15_c10_2
+ 2934: d51cfa6f msr s3_4_c15_c10_3, x15
+ 2938: d53cfa6f mrs x15, s3_4_c15_c10_3
+ 293c: d51cfa8f msr s3_4_c15_c10_4, x15
+ 2940: d53cfa8f mrs x15, s3_4_c15_c10_4
+ 2944: d51cfaaf msr s3_4_c15_c10_5, x15
+ 2948: d53cfaaf mrs x15, s3_4_c15_c10_5
+ 294c: d51cfacf msr s3_4_c15_c10_6, x15
+ 2950: d53cfacf mrs x15, s3_4_c15_c10_6
+ 2954: d51cfaef msr s3_4_c15_c10_7, x15
+ 2958: d53cfaef mrs x15, s3_4_c15_c10_7
+ 295c: d51cfb0f msr s3_4_c15_c11_0, x15
+ 2960: d53cfb0f mrs x15, s3_4_c15_c11_0
+ 2964: d51cfb2f msr s3_4_c15_c11_1, x15
+ 2968: d53cfb2f mrs x15, s3_4_c15_c11_1
+ 296c: d51cfb4f msr s3_4_c15_c11_2, x15
+ 2970: d53cfb4f mrs x15, s3_4_c15_c11_2
+ 2974: d51cfb6f msr s3_4_c15_c11_3, x15
+ 2978: d53cfb6f mrs x15, s3_4_c15_c11_3
+ 297c: d51cfb8f msr s3_4_c15_c11_4, x15
+ 2980: d53cfb8f mrs x15, s3_4_c15_c11_4
+ 2984: d51cfbaf msr s3_4_c15_c11_5, x15
+ 2988: d53cfbaf mrs x15, s3_4_c15_c11_5
+ 298c: d51cfbcf msr s3_4_c15_c11_6, x15
+ 2990: d53cfbcf mrs x15, s3_4_c15_c11_6
+ 2994: d51cfbef msr s3_4_c15_c11_7, x15
+ 2998: d53cfbef mrs x15, s3_4_c15_c11_7
+ 299c: d51cfc0f msr s3_4_c15_c12_0, x15
+ 29a0: d53cfc0f mrs x15, s3_4_c15_c12_0
+ 29a4: d51cfc2f msr s3_4_c15_c12_1, x15
+ 29a8: d53cfc2f mrs x15, s3_4_c15_c12_1
+ 29ac: d51cfc4f msr s3_4_c15_c12_2, x15
+ 29b0: d53cfc4f mrs x15, s3_4_c15_c12_2
+ 29b4: d51cfc6f msr s3_4_c15_c12_3, x15
+ 29b8: d53cfc6f mrs x15, s3_4_c15_c12_3
+ 29bc: d51cfc8f msr s3_4_c15_c12_4, x15
+ 29c0: d53cfc8f mrs x15, s3_4_c15_c12_4
+ 29c4: d51cfcaf msr s3_4_c15_c12_5, x15
+ 29c8: d53cfcaf mrs x15, s3_4_c15_c12_5
+ 29cc: d51cfccf msr s3_4_c15_c12_6, x15
+ 29d0: d53cfccf mrs x15, s3_4_c15_c12_6
+ 29d4: d51cfcef msr s3_4_c15_c12_7, x15
+ 29d8: d53cfcef mrs x15, s3_4_c15_c12_7
+ 29dc: d51cfd0f msr s3_4_c15_c13_0, x15
+ 29e0: d53cfd0f mrs x15, s3_4_c15_c13_0
+ 29e4: d51cfd2f msr s3_4_c15_c13_1, x15
+ 29e8: d53cfd2f mrs x15, s3_4_c15_c13_1
+ 29ec: d51cfd4f msr s3_4_c15_c13_2, x15
+ 29f0: d53cfd4f mrs x15, s3_4_c15_c13_2
+ 29f4: d51cfd6f msr s3_4_c15_c13_3, x15
+ 29f8: d53cfd6f mrs x15, s3_4_c15_c13_3
+ 29fc: d51cfd8f msr s3_4_c15_c13_4, x15
+ 2a00: d53cfd8f mrs x15, s3_4_c15_c13_4
+ 2a04: d51cfdaf msr s3_4_c15_c13_5, x15
+ 2a08: d53cfdaf mrs x15, s3_4_c15_c13_5
+ 2a0c: d51cfdcf msr s3_4_c15_c13_6, x15
+ 2a10: d53cfdcf mrs x15, s3_4_c15_c13_6
+ 2a14: d51cfdef msr s3_4_c15_c13_7, x15
+ 2a18: d53cfdef mrs x15, s3_4_c15_c13_7
+ 2a1c: d51cfe0f msr s3_4_c15_c14_0, x15
+ 2a20: d53cfe0f mrs x15, s3_4_c15_c14_0
+ 2a24: d51cfe2f msr s3_4_c15_c14_1, x15
+ 2a28: d53cfe2f mrs x15, s3_4_c15_c14_1
+ 2a2c: d51cfe4f msr s3_4_c15_c14_2, x15
+ 2a30: d53cfe4f mrs x15, s3_4_c15_c14_2
+ 2a34: d51cfe6f msr s3_4_c15_c14_3, x15
+ 2a38: d53cfe6f mrs x15, s3_4_c15_c14_3
+ 2a3c: d51cfe8f msr s3_4_c15_c14_4, x15
+ 2a40: d53cfe8f mrs x15, s3_4_c15_c14_4
+ 2a44: d51cfeaf msr s3_4_c15_c14_5, x15
+ 2a48: d53cfeaf mrs x15, s3_4_c15_c14_5
+ 2a4c: d51cfecf msr s3_4_c15_c14_6, x15
+ 2a50: d53cfecf mrs x15, s3_4_c15_c14_6
+ 2a54: d51cfeef msr s3_4_c15_c14_7, x15
+ 2a58: d53cfeef mrs x15, s3_4_c15_c14_7
+ 2a5c: d51cff0f msr s3_4_c15_c15_0, x15
+ 2a60: d53cff0f mrs x15, s3_4_c15_c15_0
+ 2a64: d51cff2f msr s3_4_c15_c15_1, x15
+ 2a68: d53cff2f mrs x15, s3_4_c15_c15_1
+ 2a6c: d51cff4f msr s3_4_c15_c15_2, x15
+ 2a70: d53cff4f mrs x15, s3_4_c15_c15_2
+ 2a74: d51cff6f msr s3_4_c15_c15_3, x15
+ 2a78: d53cff6f mrs x15, s3_4_c15_c15_3
+ 2a7c: d51cff8f msr s3_4_c15_c15_4, x15
+ 2a80: d53cff8f mrs x15, s3_4_c15_c15_4
+ 2a84: d51cffaf msr s3_4_c15_c15_5, x15
+ 2a88: d53cffaf mrs x15, s3_4_c15_c15_5
+ 2a8c: d51cffcf msr s3_4_c15_c15_6, x15
+ 2a90: d53cffcf mrs x15, s3_4_c15_c15_6
+ 2a94: d51cffef msr s3_4_c15_c15_7, x15
+ 2a98: d53cffef mrs x15, s3_4_c15_c15_7
+ 2a9c: d51db00f msr s3_5_c11_c0_0, x15
+ 2aa0: d53db00f mrs x15, s3_5_c11_c0_0
+ 2aa4: d51db02f msr s3_5_c11_c0_1, x15
+ 2aa8: d53db02f mrs x15, s3_5_c11_c0_1
+ 2aac: d51db04f msr s3_5_c11_c0_2, x15
+ 2ab0: d53db04f mrs x15, s3_5_c11_c0_2
+ 2ab4: d51db06f msr s3_5_c11_c0_3, x15
+ 2ab8: d53db06f mrs x15, s3_5_c11_c0_3
+ 2abc: d51db08f msr s3_5_c11_c0_4, x15
+ 2ac0: d53db08f mrs x15, s3_5_c11_c0_4
+ 2ac4: d51db0af msr s3_5_c11_c0_5, x15
+ 2ac8: d53db0af mrs x15, s3_5_c11_c0_5
+ 2acc: d51db0cf msr s3_5_c11_c0_6, x15
+ 2ad0: d53db0cf mrs x15, s3_5_c11_c0_6
+ 2ad4: d51db0ef msr s3_5_c11_c0_7, x15
+ 2ad8: d53db0ef mrs x15, s3_5_c11_c0_7
+ 2adc: d51db10f msr s3_5_c11_c1_0, x15
+ 2ae0: d53db10f mrs x15, s3_5_c11_c1_0
+ 2ae4: d51db12f msr s3_5_c11_c1_1, x15
+ 2ae8: d53db12f mrs x15, s3_5_c11_c1_1
+ 2aec: d51db14f msr s3_5_c11_c1_2, x15
+ 2af0: d53db14f mrs x15, s3_5_c11_c1_2
+ 2af4: d51db16f msr s3_5_c11_c1_3, x15
+ 2af8: d53db16f mrs x15, s3_5_c11_c1_3
+ 2afc: d51db18f msr s3_5_c11_c1_4, x15
+ 2b00: d53db18f mrs x15, s3_5_c11_c1_4
+ 2b04: d51db1af msr s3_5_c11_c1_5, x15
+ 2b08: d53db1af mrs x15, s3_5_c11_c1_5
+ 2b0c: d51db1cf msr s3_5_c11_c1_6, x15
+ 2b10: d53db1cf mrs x15, s3_5_c11_c1_6
+ 2b14: d51db1ef msr s3_5_c11_c1_7, x15
+ 2b18: d53db1ef mrs x15, s3_5_c11_c1_7
+ 2b1c: d51db20f msr s3_5_c11_c2_0, x15
+ 2b20: d53db20f mrs x15, s3_5_c11_c2_0
+ 2b24: d51db22f msr s3_5_c11_c2_1, x15
+ 2b28: d53db22f mrs x15, s3_5_c11_c2_1
+ 2b2c: d51db24f msr s3_5_c11_c2_2, x15
+ 2b30: d53db24f mrs x15, s3_5_c11_c2_2
+ 2b34: d51db26f msr s3_5_c11_c2_3, x15
+ 2b38: d53db26f mrs x15, s3_5_c11_c2_3
+ 2b3c: d51db28f msr s3_5_c11_c2_4, x15
+ 2b40: d53db28f mrs x15, s3_5_c11_c2_4
+ 2b44: d51db2af msr s3_5_c11_c2_5, x15
+ 2b48: d53db2af mrs x15, s3_5_c11_c2_5
+ 2b4c: d51db2cf msr s3_5_c11_c2_6, x15
+ 2b50: d53db2cf mrs x15, s3_5_c11_c2_6
+ 2b54: d51db2ef msr s3_5_c11_c2_7, x15
+ 2b58: d53db2ef mrs x15, s3_5_c11_c2_7
+ 2b5c: d51db30f msr s3_5_c11_c3_0, x15
+ 2b60: d53db30f mrs x15, s3_5_c11_c3_0
+ 2b64: d51db32f msr s3_5_c11_c3_1, x15
+ 2b68: d53db32f mrs x15, s3_5_c11_c3_1
+ 2b6c: d51db34f msr s3_5_c11_c3_2, x15
+ 2b70: d53db34f mrs x15, s3_5_c11_c3_2
+ 2b74: d51db36f msr s3_5_c11_c3_3, x15
+ 2b78: d53db36f mrs x15, s3_5_c11_c3_3
+ 2b7c: d51db38f msr s3_5_c11_c3_4, x15
+ 2b80: d53db38f mrs x15, s3_5_c11_c3_4
+ 2b84: d51db3af msr s3_5_c11_c3_5, x15
+ 2b88: d53db3af mrs x15, s3_5_c11_c3_5
+ 2b8c: d51db3cf msr s3_5_c11_c3_6, x15
+ 2b90: d53db3cf mrs x15, s3_5_c11_c3_6
+ 2b94: d51db3ef msr s3_5_c11_c3_7, x15
+ 2b98: d53db3ef mrs x15, s3_5_c11_c3_7
+ 2b9c: d51db40f msr s3_5_c11_c4_0, x15
+ 2ba0: d53db40f mrs x15, s3_5_c11_c4_0
+ 2ba4: d51db42f msr s3_5_c11_c4_1, x15
+ 2ba8: d53db42f mrs x15, s3_5_c11_c4_1
+ 2bac: d51db44f msr s3_5_c11_c4_2, x15
+ 2bb0: d53db44f mrs x15, s3_5_c11_c4_2
+ 2bb4: d51db46f msr s3_5_c11_c4_3, x15
+ 2bb8: d53db46f mrs x15, s3_5_c11_c4_3
+ 2bbc: d51db48f msr s3_5_c11_c4_4, x15
+ 2bc0: d53db48f mrs x15, s3_5_c11_c4_4
+ 2bc4: d51db4af msr s3_5_c11_c4_5, x15
+ 2bc8: d53db4af mrs x15, s3_5_c11_c4_5
+ 2bcc: d51db4cf msr s3_5_c11_c4_6, x15
+ 2bd0: d53db4cf mrs x15, s3_5_c11_c4_6
+ 2bd4: d51db4ef msr s3_5_c11_c4_7, x15
+ 2bd8: d53db4ef mrs x15, s3_5_c11_c4_7
+ 2bdc: d51db50f msr s3_5_c11_c5_0, x15
+ 2be0: d53db50f mrs x15, s3_5_c11_c5_0
+ 2be4: d51db52f msr s3_5_c11_c5_1, x15
+ 2be8: d53db52f mrs x15, s3_5_c11_c5_1
+ 2bec: d51db54f msr s3_5_c11_c5_2, x15
+ 2bf0: d53db54f mrs x15, s3_5_c11_c5_2
+ 2bf4: d51db56f msr s3_5_c11_c5_3, x15
+ 2bf8: d53db56f mrs x15, s3_5_c11_c5_3
+ 2bfc: d51db58f msr s3_5_c11_c5_4, x15
+ 2c00: d53db58f mrs x15, s3_5_c11_c5_4
+ 2c04: d51db5af msr s3_5_c11_c5_5, x15
+ 2c08: d53db5af mrs x15, s3_5_c11_c5_5
+ 2c0c: d51db5cf msr s3_5_c11_c5_6, x15
+ 2c10: d53db5cf mrs x15, s3_5_c11_c5_6
+ 2c14: d51db5ef msr s3_5_c11_c5_7, x15
+ 2c18: d53db5ef mrs x15, s3_5_c11_c5_7
+ 2c1c: d51db60f msr s3_5_c11_c6_0, x15
+ 2c20: d53db60f mrs x15, s3_5_c11_c6_0
+ 2c24: d51db62f msr s3_5_c11_c6_1, x15
+ 2c28: d53db62f mrs x15, s3_5_c11_c6_1
+ 2c2c: d51db64f msr s3_5_c11_c6_2, x15
+ 2c30: d53db64f mrs x15, s3_5_c11_c6_2
+ 2c34: d51db66f msr s3_5_c11_c6_3, x15
+ 2c38: d53db66f mrs x15, s3_5_c11_c6_3
+ 2c3c: d51db68f msr s3_5_c11_c6_4, x15
+ 2c40: d53db68f mrs x15, s3_5_c11_c6_4
+ 2c44: d51db6af msr s3_5_c11_c6_5, x15
+ 2c48: d53db6af mrs x15, s3_5_c11_c6_5
+ 2c4c: d51db6cf msr s3_5_c11_c6_6, x15
+ 2c50: d53db6cf mrs x15, s3_5_c11_c6_6
+ 2c54: d51db6ef msr s3_5_c11_c6_7, x15
+ 2c58: d53db6ef mrs x15, s3_5_c11_c6_7
+ 2c5c: d51db70f msr s3_5_c11_c7_0, x15
+ 2c60: d53db70f mrs x15, s3_5_c11_c7_0
+ 2c64: d51db72f msr s3_5_c11_c7_1, x15
+ 2c68: d53db72f mrs x15, s3_5_c11_c7_1
+ 2c6c: d51db74f msr s3_5_c11_c7_2, x15
+ 2c70: d53db74f mrs x15, s3_5_c11_c7_2
+ 2c74: d51db76f msr s3_5_c11_c7_3, x15
+ 2c78: d53db76f mrs x15, s3_5_c11_c7_3
+ 2c7c: d51db78f msr s3_5_c11_c7_4, x15
+ 2c80: d53db78f mrs x15, s3_5_c11_c7_4
+ 2c84: d51db7af msr s3_5_c11_c7_5, x15
+ 2c88: d53db7af mrs x15, s3_5_c11_c7_5
+ 2c8c: d51db7cf msr s3_5_c11_c7_6, x15
+ 2c90: d53db7cf mrs x15, s3_5_c11_c7_6
+ 2c94: d51db7ef msr s3_5_c11_c7_7, x15
+ 2c98: d53db7ef mrs x15, s3_5_c11_c7_7
+ 2c9c: d51db80f msr s3_5_c11_c8_0, x15
+ 2ca0: d53db80f mrs x15, s3_5_c11_c8_0
+ 2ca4: d51db82f msr s3_5_c11_c8_1, x15
+ 2ca8: d53db82f mrs x15, s3_5_c11_c8_1
+ 2cac: d51db84f msr s3_5_c11_c8_2, x15
+ 2cb0: d53db84f mrs x15, s3_5_c11_c8_2
+ 2cb4: d51db86f msr s3_5_c11_c8_3, x15
+ 2cb8: d53db86f mrs x15, s3_5_c11_c8_3
+ 2cbc: d51db88f msr s3_5_c11_c8_4, x15
+ 2cc0: d53db88f mrs x15, s3_5_c11_c8_4
+ 2cc4: d51db8af msr s3_5_c11_c8_5, x15
+ 2cc8: d53db8af mrs x15, s3_5_c11_c8_5
+ 2ccc: d51db8cf msr s3_5_c11_c8_6, x15
+ 2cd0: d53db8cf mrs x15, s3_5_c11_c8_6
+ 2cd4: d51db8ef msr s3_5_c11_c8_7, x15
+ 2cd8: d53db8ef mrs x15, s3_5_c11_c8_7
+ 2cdc: d51db90f msr s3_5_c11_c9_0, x15
+ 2ce0: d53db90f mrs x15, s3_5_c11_c9_0
+ 2ce4: d51db92f msr s3_5_c11_c9_1, x15
+ 2ce8: d53db92f mrs x15, s3_5_c11_c9_1
+ 2cec: d51db94f msr s3_5_c11_c9_2, x15
+ 2cf0: d53db94f mrs x15, s3_5_c11_c9_2
+ 2cf4: d51db96f msr s3_5_c11_c9_3, x15
+ 2cf8: d53db96f mrs x15, s3_5_c11_c9_3
+ 2cfc: d51db98f msr s3_5_c11_c9_4, x15
+ 2d00: d53db98f mrs x15, s3_5_c11_c9_4
+ 2d04: d51db9af msr s3_5_c11_c9_5, x15
+ 2d08: d53db9af mrs x15, s3_5_c11_c9_5
+ 2d0c: d51db9cf msr s3_5_c11_c9_6, x15
+ 2d10: d53db9cf mrs x15, s3_5_c11_c9_6
+ 2d14: d51db9ef msr s3_5_c11_c9_7, x15
+ 2d18: d53db9ef mrs x15, s3_5_c11_c9_7
+ 2d1c: d51dba0f msr s3_5_c11_c10_0, x15
+ 2d20: d53dba0f mrs x15, s3_5_c11_c10_0
+ 2d24: d51dba2f msr s3_5_c11_c10_1, x15
+ 2d28: d53dba2f mrs x15, s3_5_c11_c10_1
+ 2d2c: d51dba4f msr s3_5_c11_c10_2, x15
+ 2d30: d53dba4f mrs x15, s3_5_c11_c10_2
+ 2d34: d51dba6f msr s3_5_c11_c10_3, x15
+ 2d38: d53dba6f mrs x15, s3_5_c11_c10_3
+ 2d3c: d51dba8f msr s3_5_c11_c10_4, x15
+ 2d40: d53dba8f mrs x15, s3_5_c11_c10_4
+ 2d44: d51dbaaf msr s3_5_c11_c10_5, x15
+ 2d48: d53dbaaf mrs x15, s3_5_c11_c10_5
+ 2d4c: d51dbacf msr s3_5_c11_c10_6, x15
+ 2d50: d53dbacf mrs x15, s3_5_c11_c10_6
+ 2d54: d51dbaef msr s3_5_c11_c10_7, x15
+ 2d58: d53dbaef mrs x15, s3_5_c11_c10_7
+ 2d5c: d51dbb0f msr s3_5_c11_c11_0, x15
+ 2d60: d53dbb0f mrs x15, s3_5_c11_c11_0
+ 2d64: d51dbb2f msr s3_5_c11_c11_1, x15
+ 2d68: d53dbb2f mrs x15, s3_5_c11_c11_1
+ 2d6c: d51dbb4f msr s3_5_c11_c11_2, x15
+ 2d70: d53dbb4f mrs x15, s3_5_c11_c11_2
+ 2d74: d51dbb6f msr s3_5_c11_c11_3, x15
+ 2d78: d53dbb6f mrs x15, s3_5_c11_c11_3
+ 2d7c: d51dbb8f msr s3_5_c11_c11_4, x15
+ 2d80: d53dbb8f mrs x15, s3_5_c11_c11_4
+ 2d84: d51dbbaf msr s3_5_c11_c11_5, x15
+ 2d88: d53dbbaf mrs x15, s3_5_c11_c11_5
+ 2d8c: d51dbbcf msr s3_5_c11_c11_6, x15
+ 2d90: d53dbbcf mrs x15, s3_5_c11_c11_6
+ 2d94: d51dbbef msr s3_5_c11_c11_7, x15
+ 2d98: d53dbbef mrs x15, s3_5_c11_c11_7
+ 2d9c: d51dbc0f msr s3_5_c11_c12_0, x15
+ 2da0: d53dbc0f mrs x15, s3_5_c11_c12_0
+ 2da4: d51dbc2f msr s3_5_c11_c12_1, x15
+ 2da8: d53dbc2f mrs x15, s3_5_c11_c12_1
+ 2dac: d51dbc4f msr s3_5_c11_c12_2, x15
+ 2db0: d53dbc4f mrs x15, s3_5_c11_c12_2
+ 2db4: d51dbc6f msr s3_5_c11_c12_3, x15
+ 2db8: d53dbc6f mrs x15, s3_5_c11_c12_3
+ 2dbc: d51dbc8f msr s3_5_c11_c12_4, x15
+ 2dc0: d53dbc8f mrs x15, s3_5_c11_c12_4
+ 2dc4: d51dbcaf msr s3_5_c11_c12_5, x15
+ 2dc8: d53dbcaf mrs x15, s3_5_c11_c12_5
+ 2dcc: d51dbccf msr s3_5_c11_c12_6, x15
+ 2dd0: d53dbccf mrs x15, s3_5_c11_c12_6
+ 2dd4: d51dbcef msr s3_5_c11_c12_7, x15
+ 2dd8: d53dbcef mrs x15, s3_5_c11_c12_7
+ 2ddc: d51dbd0f msr s3_5_c11_c13_0, x15
+ 2de0: d53dbd0f mrs x15, s3_5_c11_c13_0
+ 2de4: d51dbd2f msr s3_5_c11_c13_1, x15
+ 2de8: d53dbd2f mrs x15, s3_5_c11_c13_1
+ 2dec: d51dbd4f msr s3_5_c11_c13_2, x15
+ 2df0: d53dbd4f mrs x15, s3_5_c11_c13_2
+ 2df4: d51dbd6f msr s3_5_c11_c13_3, x15
+ 2df8: d53dbd6f mrs x15, s3_5_c11_c13_3
+ 2dfc: d51dbd8f msr s3_5_c11_c13_4, x15
+ 2e00: d53dbd8f mrs x15, s3_5_c11_c13_4
+ 2e04: d51dbdaf msr s3_5_c11_c13_5, x15
+ 2e08: d53dbdaf mrs x15, s3_5_c11_c13_5
+ 2e0c: d51dbdcf msr s3_5_c11_c13_6, x15
+ 2e10: d53dbdcf mrs x15, s3_5_c11_c13_6
+ 2e14: d51dbdef msr s3_5_c11_c13_7, x15
+ 2e18: d53dbdef mrs x15, s3_5_c11_c13_7
+ 2e1c: d51dbe0f msr s3_5_c11_c14_0, x15
+ 2e20: d53dbe0f mrs x15, s3_5_c11_c14_0
+ 2e24: d51dbe2f msr s3_5_c11_c14_1, x15
+ 2e28: d53dbe2f mrs x15, s3_5_c11_c14_1
+ 2e2c: d51dbe4f msr s3_5_c11_c14_2, x15
+ 2e30: d53dbe4f mrs x15, s3_5_c11_c14_2
+ 2e34: d51dbe6f msr s3_5_c11_c14_3, x15
+ 2e38: d53dbe6f mrs x15, s3_5_c11_c14_3
+ 2e3c: d51dbe8f msr s3_5_c11_c14_4, x15
+ 2e40: d53dbe8f mrs x15, s3_5_c11_c14_4
+ 2e44: d51dbeaf msr s3_5_c11_c14_5, x15
+ 2e48: d53dbeaf mrs x15, s3_5_c11_c14_5
+ 2e4c: d51dbecf msr s3_5_c11_c14_6, x15
+ 2e50: d53dbecf mrs x15, s3_5_c11_c14_6
+ 2e54: d51dbeef msr s3_5_c11_c14_7, x15
+ 2e58: d53dbeef mrs x15, s3_5_c11_c14_7
+ 2e5c: d51dbf0f msr s3_5_c11_c15_0, x15
+ 2e60: d53dbf0f mrs x15, s3_5_c11_c15_0
+ 2e64: d51dbf2f msr s3_5_c11_c15_1, x15
+ 2e68: d53dbf2f mrs x15, s3_5_c11_c15_1
+ 2e6c: d51dbf4f msr s3_5_c11_c15_2, x15
+ 2e70: d53dbf4f mrs x15, s3_5_c11_c15_2
+ 2e74: d51dbf6f msr s3_5_c11_c15_3, x15
+ 2e78: d53dbf6f mrs x15, s3_5_c11_c15_3
+ 2e7c: d51dbf8f msr s3_5_c11_c15_4, x15
+ 2e80: d53dbf8f mrs x15, s3_5_c11_c15_4
+ 2e84: d51dbfaf msr s3_5_c11_c15_5, x15
+ 2e88: d53dbfaf mrs x15, s3_5_c11_c15_5
+ 2e8c: d51dbfcf msr s3_5_c11_c15_6, x15
+ 2e90: d53dbfcf mrs x15, s3_5_c11_c15_6
+ 2e94: d51dbfef msr s3_5_c11_c15_7, x15
+ 2e98: d53dbfef mrs x15, s3_5_c11_c15_7
+ 2e9c: d51df00f msr s3_5_c15_c0_0, x15
+ 2ea0: d53df00f mrs x15, s3_5_c15_c0_0
+ 2ea4: d51df02f msr s3_5_c15_c0_1, x15
+ 2ea8: d53df02f mrs x15, s3_5_c15_c0_1
+ 2eac: d51df04f msr s3_5_c15_c0_2, x15
+ 2eb0: d53df04f mrs x15, s3_5_c15_c0_2
+ 2eb4: d51df06f msr s3_5_c15_c0_3, x15
+ 2eb8: d53df06f mrs x15, s3_5_c15_c0_3
+ 2ebc: d51df08f msr s3_5_c15_c0_4, x15
+ 2ec0: d53df08f mrs x15, s3_5_c15_c0_4
+ 2ec4: d51df0af msr s3_5_c15_c0_5, x15
+ 2ec8: d53df0af mrs x15, s3_5_c15_c0_5
+ 2ecc: d51df0cf msr s3_5_c15_c0_6, x15
+ 2ed0: d53df0cf mrs x15, s3_5_c15_c0_6
+ 2ed4: d51df0ef msr s3_5_c15_c0_7, x15
+ 2ed8: d53df0ef mrs x15, s3_5_c15_c0_7
+ 2edc: d51df10f msr s3_5_c15_c1_0, x15
+ 2ee0: d53df10f mrs x15, s3_5_c15_c1_0
+ 2ee4: d51df12f msr s3_5_c15_c1_1, x15
+ 2ee8: d53df12f mrs x15, s3_5_c15_c1_1
+ 2eec: d51df14f msr s3_5_c15_c1_2, x15
+ 2ef0: d53df14f mrs x15, s3_5_c15_c1_2
+ 2ef4: d51df16f msr s3_5_c15_c1_3, x15
+ 2ef8: d53df16f mrs x15, s3_5_c15_c1_3
+ 2efc: d51df18f msr s3_5_c15_c1_4, x15
+ 2f00: d53df18f mrs x15, s3_5_c15_c1_4
+ 2f04: d51df1af msr s3_5_c15_c1_5, x15
+ 2f08: d53df1af mrs x15, s3_5_c15_c1_5
+ 2f0c: d51df1cf msr s3_5_c15_c1_6, x15
+ 2f10: d53df1cf mrs x15, s3_5_c15_c1_6
+ 2f14: d51df1ef msr s3_5_c15_c1_7, x15
+ 2f18: d53df1ef mrs x15, s3_5_c15_c1_7
+ 2f1c: d51df20f msr s3_5_c15_c2_0, x15
+ 2f20: d53df20f mrs x15, s3_5_c15_c2_0
+ 2f24: d51df22f msr s3_5_c15_c2_1, x15
+ 2f28: d53df22f mrs x15, s3_5_c15_c2_1
+ 2f2c: d51df24f msr s3_5_c15_c2_2, x15
+ 2f30: d53df24f mrs x15, s3_5_c15_c2_2
+ 2f34: d51df26f msr s3_5_c15_c2_3, x15
+ 2f38: d53df26f mrs x15, s3_5_c15_c2_3
+ 2f3c: d51df28f msr s3_5_c15_c2_4, x15
+ 2f40: d53df28f mrs x15, s3_5_c15_c2_4
+ 2f44: d51df2af msr s3_5_c15_c2_5, x15
+ 2f48: d53df2af mrs x15, s3_5_c15_c2_5
+ 2f4c: d51df2cf msr s3_5_c15_c2_6, x15
+ 2f50: d53df2cf mrs x15, s3_5_c15_c2_6
+ 2f54: d51df2ef msr s3_5_c15_c2_7, x15
+ 2f58: d53df2ef mrs x15, s3_5_c15_c2_7
+ 2f5c: d51df30f msr s3_5_c15_c3_0, x15
+ 2f60: d53df30f mrs x15, s3_5_c15_c3_0
+ 2f64: d51df32f msr s3_5_c15_c3_1, x15
+ 2f68: d53df32f mrs x15, s3_5_c15_c3_1
+ 2f6c: d51df34f msr s3_5_c15_c3_2, x15
+ 2f70: d53df34f mrs x15, s3_5_c15_c3_2
+ 2f74: d51df36f msr s3_5_c15_c3_3, x15
+ 2f78: d53df36f mrs x15, s3_5_c15_c3_3
+ 2f7c: d51df38f msr s3_5_c15_c3_4, x15
+ 2f80: d53df38f mrs x15, s3_5_c15_c3_4
+ 2f84: d51df3af msr s3_5_c15_c3_5, x15
+ 2f88: d53df3af mrs x15, s3_5_c15_c3_5
+ 2f8c: d51df3cf msr s3_5_c15_c3_6, x15
+ 2f90: d53df3cf mrs x15, s3_5_c15_c3_6
+ 2f94: d51df3ef msr s3_5_c15_c3_7, x15
+ 2f98: d53df3ef mrs x15, s3_5_c15_c3_7
+ 2f9c: d51df40f msr s3_5_c15_c4_0, x15
+ 2fa0: d53df40f mrs x15, s3_5_c15_c4_0
+ 2fa4: d51df42f msr s3_5_c15_c4_1, x15
+ 2fa8: d53df42f mrs x15, s3_5_c15_c4_1
+ 2fac: d51df44f msr s3_5_c15_c4_2, x15
+ 2fb0: d53df44f mrs x15, s3_5_c15_c4_2
+ 2fb4: d51df46f msr s3_5_c15_c4_3, x15
+ 2fb8: d53df46f mrs x15, s3_5_c15_c4_3
+ 2fbc: d51df48f msr s3_5_c15_c4_4, x15
+ 2fc0: d53df48f mrs x15, s3_5_c15_c4_4
+ 2fc4: d51df4af msr s3_5_c15_c4_5, x15
+ 2fc8: d53df4af mrs x15, s3_5_c15_c4_5
+ 2fcc: d51df4cf msr s3_5_c15_c4_6, x15
+ 2fd0: d53df4cf mrs x15, s3_5_c15_c4_6
+ 2fd4: d51df4ef msr s3_5_c15_c4_7, x15
+ 2fd8: d53df4ef mrs x15, s3_5_c15_c4_7
+ 2fdc: d51df50f msr s3_5_c15_c5_0, x15
+ 2fe0: d53df50f mrs x15, s3_5_c15_c5_0
+ 2fe4: d51df52f msr s3_5_c15_c5_1, x15
+ 2fe8: d53df52f mrs x15, s3_5_c15_c5_1
+ 2fec: d51df54f msr s3_5_c15_c5_2, x15
+ 2ff0: d53df54f mrs x15, s3_5_c15_c5_2
+ 2ff4: d51df56f msr s3_5_c15_c5_3, x15
+ 2ff8: d53df56f mrs x15, s3_5_c15_c5_3
+ 2ffc: d51df58f msr s3_5_c15_c5_4, x15
+ 3000: d53df58f mrs x15, s3_5_c15_c5_4
+ 3004: d51df5af msr s3_5_c15_c5_5, x15
+ 3008: d53df5af mrs x15, s3_5_c15_c5_5
+ 300c: d51df5cf msr s3_5_c15_c5_6, x15
+ 3010: d53df5cf mrs x15, s3_5_c15_c5_6
+ 3014: d51df5ef msr s3_5_c15_c5_7, x15
+ 3018: d53df5ef mrs x15, s3_5_c15_c5_7
+ 301c: d51df60f msr s3_5_c15_c6_0, x15
+ 3020: d53df60f mrs x15, s3_5_c15_c6_0
+ 3024: d51df62f msr s3_5_c15_c6_1, x15
+ 3028: d53df62f mrs x15, s3_5_c15_c6_1
+ 302c: d51df64f msr s3_5_c15_c6_2, x15
+ 3030: d53df64f mrs x15, s3_5_c15_c6_2
+ 3034: d51df66f msr s3_5_c15_c6_3, x15
+ 3038: d53df66f mrs x15, s3_5_c15_c6_3
+ 303c: d51df68f msr s3_5_c15_c6_4, x15
+ 3040: d53df68f mrs x15, s3_5_c15_c6_4
+ 3044: d51df6af msr s3_5_c15_c6_5, x15
+ 3048: d53df6af mrs x15, s3_5_c15_c6_5
+ 304c: d51df6cf msr s3_5_c15_c6_6, x15
+ 3050: d53df6cf mrs x15, s3_5_c15_c6_6
+ 3054: d51df6ef msr s3_5_c15_c6_7, x15
+ 3058: d53df6ef mrs x15, s3_5_c15_c6_7
+ 305c: d51df70f msr s3_5_c15_c7_0, x15
+ 3060: d53df70f mrs x15, s3_5_c15_c7_0
+ 3064: d51df72f msr s3_5_c15_c7_1, x15
+ 3068: d53df72f mrs x15, s3_5_c15_c7_1
+ 306c: d51df74f msr s3_5_c15_c7_2, x15
+ 3070: d53df74f mrs x15, s3_5_c15_c7_2
+ 3074: d51df76f msr s3_5_c15_c7_3, x15
+ 3078: d53df76f mrs x15, s3_5_c15_c7_3
+ 307c: d51df78f msr s3_5_c15_c7_4, x15
+ 3080: d53df78f mrs x15, s3_5_c15_c7_4
+ 3084: d51df7af msr s3_5_c15_c7_5, x15
+ 3088: d53df7af mrs x15, s3_5_c15_c7_5
+ 308c: d51df7cf msr s3_5_c15_c7_6, x15
+ 3090: d53df7cf mrs x15, s3_5_c15_c7_6
+ 3094: d51df7ef msr s3_5_c15_c7_7, x15
+ 3098: d53df7ef mrs x15, s3_5_c15_c7_7
+ 309c: d51df80f msr s3_5_c15_c8_0, x15
+ 30a0: d53df80f mrs x15, s3_5_c15_c8_0
+ 30a4: d51df82f msr s3_5_c15_c8_1, x15
+ 30a8: d53df82f mrs x15, s3_5_c15_c8_1
+ 30ac: d51df84f msr s3_5_c15_c8_2, x15
+ 30b0: d53df84f mrs x15, s3_5_c15_c8_2
+ 30b4: d51df86f msr s3_5_c15_c8_3, x15
+ 30b8: d53df86f mrs x15, s3_5_c15_c8_3
+ 30bc: d51df88f msr s3_5_c15_c8_4, x15
+ 30c0: d53df88f mrs x15, s3_5_c15_c8_4
+ 30c4: d51df8af msr s3_5_c15_c8_5, x15
+ 30c8: d53df8af mrs x15, s3_5_c15_c8_5
+ 30cc: d51df8cf msr s3_5_c15_c8_6, x15
+ 30d0: d53df8cf mrs x15, s3_5_c15_c8_6
+ 30d4: d51df8ef msr s3_5_c15_c8_7, x15
+ 30d8: d53df8ef mrs x15, s3_5_c15_c8_7
+ 30dc: d51df90f msr s3_5_c15_c9_0, x15
+ 30e0: d53df90f mrs x15, s3_5_c15_c9_0
+ 30e4: d51df92f msr s3_5_c15_c9_1, x15
+ 30e8: d53df92f mrs x15, s3_5_c15_c9_1
+ 30ec: d51df94f msr s3_5_c15_c9_2, x15
+ 30f0: d53df94f mrs x15, s3_5_c15_c9_2
+ 30f4: d51df96f msr s3_5_c15_c9_3, x15
+ 30f8: d53df96f mrs x15, s3_5_c15_c9_3
+ 30fc: d51df98f msr s3_5_c15_c9_4, x15
+ 3100: d53df98f mrs x15, s3_5_c15_c9_4
+ 3104: d51df9af msr s3_5_c15_c9_5, x15
+ 3108: d53df9af mrs x15, s3_5_c15_c9_5
+ 310c: d51df9cf msr s3_5_c15_c9_6, x15
+ 3110: d53df9cf mrs x15, s3_5_c15_c9_6
+ 3114: d51df9ef msr s3_5_c15_c9_7, x15
+ 3118: d53df9ef mrs x15, s3_5_c15_c9_7
+ 311c: d51dfa0f msr s3_5_c15_c10_0, x15
+ 3120: d53dfa0f mrs x15, s3_5_c15_c10_0
+ 3124: d51dfa2f msr s3_5_c15_c10_1, x15
+ 3128: d53dfa2f mrs x15, s3_5_c15_c10_1
+ 312c: d51dfa4f msr s3_5_c15_c10_2, x15
+ 3130: d53dfa4f mrs x15, s3_5_c15_c10_2
+ 3134: d51dfa6f msr s3_5_c15_c10_3, x15
+ 3138: d53dfa6f mrs x15, s3_5_c15_c10_3
+ 313c: d51dfa8f msr s3_5_c15_c10_4, x15
+ 3140: d53dfa8f mrs x15, s3_5_c15_c10_4
+ 3144: d51dfaaf msr s3_5_c15_c10_5, x15
+ 3148: d53dfaaf mrs x15, s3_5_c15_c10_5
+ 314c: d51dfacf msr s3_5_c15_c10_6, x15
+ 3150: d53dfacf mrs x15, s3_5_c15_c10_6
+ 3154: d51dfaef msr s3_5_c15_c10_7, x15
+ 3158: d53dfaef mrs x15, s3_5_c15_c10_7
+ 315c: d51dfb0f msr s3_5_c15_c11_0, x15
+ 3160: d53dfb0f mrs x15, s3_5_c15_c11_0
+ 3164: d51dfb2f msr s3_5_c15_c11_1, x15
+ 3168: d53dfb2f mrs x15, s3_5_c15_c11_1
+ 316c: d51dfb4f msr s3_5_c15_c11_2, x15
+ 3170: d53dfb4f mrs x15, s3_5_c15_c11_2
+ 3174: d51dfb6f msr s3_5_c15_c11_3, x15
+ 3178: d53dfb6f mrs x15, s3_5_c15_c11_3
+ 317c: d51dfb8f msr s3_5_c15_c11_4, x15
+ 3180: d53dfb8f mrs x15, s3_5_c15_c11_4
+ 3184: d51dfbaf msr s3_5_c15_c11_5, x15
+ 3188: d53dfbaf mrs x15, s3_5_c15_c11_5
+ 318c: d51dfbcf msr s3_5_c15_c11_6, x15
+ 3190: d53dfbcf mrs x15, s3_5_c15_c11_6
+ 3194: d51dfbef msr s3_5_c15_c11_7, x15
+ 3198: d53dfbef mrs x15, s3_5_c15_c11_7
+ 319c: d51dfc0f msr s3_5_c15_c12_0, x15
+ 31a0: d53dfc0f mrs x15, s3_5_c15_c12_0
+ 31a4: d51dfc2f msr s3_5_c15_c12_1, x15
+ 31a8: d53dfc2f mrs x15, s3_5_c15_c12_1
+ 31ac: d51dfc4f msr s3_5_c15_c12_2, x15
+ 31b0: d53dfc4f mrs x15, s3_5_c15_c12_2
+ 31b4: d51dfc6f msr s3_5_c15_c12_3, x15
+ 31b8: d53dfc6f mrs x15, s3_5_c15_c12_3
+ 31bc: d51dfc8f msr s3_5_c15_c12_4, x15
+ 31c0: d53dfc8f mrs x15, s3_5_c15_c12_4
+ 31c4: d51dfcaf msr s3_5_c15_c12_5, x15
+ 31c8: d53dfcaf mrs x15, s3_5_c15_c12_5
+ 31cc: d51dfccf msr s3_5_c15_c12_6, x15
+ 31d0: d53dfccf mrs x15, s3_5_c15_c12_6
+ 31d4: d51dfcef msr s3_5_c15_c12_7, x15
+ 31d8: d53dfcef mrs x15, s3_5_c15_c12_7
+ 31dc: d51dfd0f msr s3_5_c15_c13_0, x15
+ 31e0: d53dfd0f mrs x15, s3_5_c15_c13_0
+ 31e4: d51dfd2f msr s3_5_c15_c13_1, x15
+ 31e8: d53dfd2f mrs x15, s3_5_c15_c13_1
+ 31ec: d51dfd4f msr s3_5_c15_c13_2, x15
+ 31f0: d53dfd4f mrs x15, s3_5_c15_c13_2
+ 31f4: d51dfd6f msr s3_5_c15_c13_3, x15
+ 31f8: d53dfd6f mrs x15, s3_5_c15_c13_3
+ 31fc: d51dfd8f msr s3_5_c15_c13_4, x15
+ 3200: d53dfd8f mrs x15, s3_5_c15_c13_4
+ 3204: d51dfdaf msr s3_5_c15_c13_5, x15
+ 3208: d53dfdaf mrs x15, s3_5_c15_c13_5
+ 320c: d51dfdcf msr s3_5_c15_c13_6, x15
+ 3210: d53dfdcf mrs x15, s3_5_c15_c13_6
+ 3214: d51dfdef msr s3_5_c15_c13_7, x15
+ 3218: d53dfdef mrs x15, s3_5_c15_c13_7
+ 321c: d51dfe0f msr s3_5_c15_c14_0, x15
+ 3220: d53dfe0f mrs x15, s3_5_c15_c14_0
+ 3224: d51dfe2f msr s3_5_c15_c14_1, x15
+ 3228: d53dfe2f mrs x15, s3_5_c15_c14_1
+ 322c: d51dfe4f msr s3_5_c15_c14_2, x15
+ 3230: d53dfe4f mrs x15, s3_5_c15_c14_2
+ 3234: d51dfe6f msr s3_5_c15_c14_3, x15
+ 3238: d53dfe6f mrs x15, s3_5_c15_c14_3
+ 323c: d51dfe8f msr s3_5_c15_c14_4, x15
+ 3240: d53dfe8f mrs x15, s3_5_c15_c14_4
+ 3244: d51dfeaf msr s3_5_c15_c14_5, x15
+ 3248: d53dfeaf mrs x15, s3_5_c15_c14_5
+ 324c: d51dfecf msr s3_5_c15_c14_6, x15
+ 3250: d53dfecf mrs x15, s3_5_c15_c14_6
+ 3254: d51dfeef msr s3_5_c15_c14_7, x15
+ 3258: d53dfeef mrs x15, s3_5_c15_c14_7
+ 325c: d51dff0f msr s3_5_c15_c15_0, x15
+ 3260: d53dff0f mrs x15, s3_5_c15_c15_0
+ 3264: d51dff2f msr s3_5_c15_c15_1, x15
+ 3268: d53dff2f mrs x15, s3_5_c15_c15_1
+ 326c: d51dff4f msr s3_5_c15_c15_2, x15
+ 3270: d53dff4f mrs x15, s3_5_c15_c15_2
+ 3274: d51dff6f msr s3_5_c15_c15_3, x15
+ 3278: d53dff6f mrs x15, s3_5_c15_c15_3
+ 327c: d51dff8f msr s3_5_c15_c15_4, x15
+ 3280: d53dff8f mrs x15, s3_5_c15_c15_4
+ 3284: d51dffaf msr s3_5_c15_c15_5, x15
+ 3288: d53dffaf mrs x15, s3_5_c15_c15_5
+ 328c: d51dffcf msr s3_5_c15_c15_6, x15
+ 3290: d53dffcf mrs x15, s3_5_c15_c15_6
+ 3294: d51dffef msr s3_5_c15_c15_7, x15
+ 3298: d53dffef mrs x15, s3_5_c15_c15_7
+ 329c: d51eb00f msr s3_6_c11_c0_0, x15
+ 32a0: d53eb00f mrs x15, s3_6_c11_c0_0
+ 32a4: d51eb02f msr s3_6_c11_c0_1, x15
+ 32a8: d53eb02f mrs x15, s3_6_c11_c0_1
+ 32ac: d51eb04f msr s3_6_c11_c0_2, x15
+ 32b0: d53eb04f mrs x15, s3_6_c11_c0_2
+ 32b4: d51eb06f msr s3_6_c11_c0_3, x15
+ 32b8: d53eb06f mrs x15, s3_6_c11_c0_3
+ 32bc: d51eb08f msr s3_6_c11_c0_4, x15
+ 32c0: d53eb08f mrs x15, s3_6_c11_c0_4
+ 32c4: d51eb0af msr s3_6_c11_c0_5, x15
+ 32c8: d53eb0af mrs x15, s3_6_c11_c0_5
+ 32cc: d51eb0cf msr s3_6_c11_c0_6, x15
+ 32d0: d53eb0cf mrs x15, s3_6_c11_c0_6
+ 32d4: d51eb0ef msr s3_6_c11_c0_7, x15
+ 32d8: d53eb0ef mrs x15, s3_6_c11_c0_7
+ 32dc: d51eb10f msr s3_6_c11_c1_0, x15
+ 32e0: d53eb10f mrs x15, s3_6_c11_c1_0
+ 32e4: d51eb12f msr s3_6_c11_c1_1, x15
+ 32e8: d53eb12f mrs x15, s3_6_c11_c1_1
+ 32ec: d51eb14f msr s3_6_c11_c1_2, x15
+ 32f0: d53eb14f mrs x15, s3_6_c11_c1_2
+ 32f4: d51eb16f msr s3_6_c11_c1_3, x15
+ 32f8: d53eb16f mrs x15, s3_6_c11_c1_3
+ 32fc: d51eb18f msr s3_6_c11_c1_4, x15
+ 3300: d53eb18f mrs x15, s3_6_c11_c1_4
+ 3304: d51eb1af msr s3_6_c11_c1_5, x15
+ 3308: d53eb1af mrs x15, s3_6_c11_c1_5
+ 330c: d51eb1cf msr s3_6_c11_c1_6, x15
+ 3310: d53eb1cf mrs x15, s3_6_c11_c1_6
+ 3314: d51eb1ef msr s3_6_c11_c1_7, x15
+ 3318: d53eb1ef mrs x15, s3_6_c11_c1_7
+ 331c: d51eb20f msr s3_6_c11_c2_0, x15
+ 3320: d53eb20f mrs x15, s3_6_c11_c2_0
+ 3324: d51eb22f msr s3_6_c11_c2_1, x15
+ 3328: d53eb22f mrs x15, s3_6_c11_c2_1
+ 332c: d51eb24f msr s3_6_c11_c2_2, x15
+ 3330: d53eb24f mrs x15, s3_6_c11_c2_2
+ 3334: d51eb26f msr s3_6_c11_c2_3, x15
+ 3338: d53eb26f mrs x15, s3_6_c11_c2_3
+ 333c: d51eb28f msr s3_6_c11_c2_4, x15
+ 3340: d53eb28f mrs x15, s3_6_c11_c2_4
+ 3344: d51eb2af msr s3_6_c11_c2_5, x15
+ 3348: d53eb2af mrs x15, s3_6_c11_c2_5
+ 334c: d51eb2cf msr s3_6_c11_c2_6, x15
+ 3350: d53eb2cf mrs x15, s3_6_c11_c2_6
+ 3354: d51eb2ef msr s3_6_c11_c2_7, x15
+ 3358: d53eb2ef mrs x15, s3_6_c11_c2_7
+ 335c: d51eb30f msr s3_6_c11_c3_0, x15
+ 3360: d53eb30f mrs x15, s3_6_c11_c3_0
+ 3364: d51eb32f msr s3_6_c11_c3_1, x15
+ 3368: d53eb32f mrs x15, s3_6_c11_c3_1
+ 336c: d51eb34f msr s3_6_c11_c3_2, x15
+ 3370: d53eb34f mrs x15, s3_6_c11_c3_2
+ 3374: d51eb36f msr s3_6_c11_c3_3, x15
+ 3378: d53eb36f mrs x15, s3_6_c11_c3_3
+ 337c: d51eb38f msr s3_6_c11_c3_4, x15
+ 3380: d53eb38f mrs x15, s3_6_c11_c3_4
+ 3384: d51eb3af msr s3_6_c11_c3_5, x15
+ 3388: d53eb3af mrs x15, s3_6_c11_c3_5
+ 338c: d51eb3cf msr s3_6_c11_c3_6, x15
+ 3390: d53eb3cf mrs x15, s3_6_c11_c3_6
+ 3394: d51eb3ef msr s3_6_c11_c3_7, x15
+ 3398: d53eb3ef mrs x15, s3_6_c11_c3_7
+ 339c: d51eb40f msr s3_6_c11_c4_0, x15
+ 33a0: d53eb40f mrs x15, s3_6_c11_c4_0
+ 33a4: d51eb42f msr s3_6_c11_c4_1, x15
+ 33a8: d53eb42f mrs x15, s3_6_c11_c4_1
+ 33ac: d51eb44f msr s3_6_c11_c4_2, x15
+ 33b0: d53eb44f mrs x15, s3_6_c11_c4_2
+ 33b4: d51eb46f msr s3_6_c11_c4_3, x15
+ 33b8: d53eb46f mrs x15, s3_6_c11_c4_3
+ 33bc: d51eb48f msr s3_6_c11_c4_4, x15
+ 33c0: d53eb48f mrs x15, s3_6_c11_c4_4
+ 33c4: d51eb4af msr s3_6_c11_c4_5, x15
+ 33c8: d53eb4af mrs x15, s3_6_c11_c4_5
+ 33cc: d51eb4cf msr s3_6_c11_c4_6, x15
+ 33d0: d53eb4cf mrs x15, s3_6_c11_c4_6
+ 33d4: d51eb4ef msr s3_6_c11_c4_7, x15
+ 33d8: d53eb4ef mrs x15, s3_6_c11_c4_7
+ 33dc: d51eb50f msr s3_6_c11_c5_0, x15
+ 33e0: d53eb50f mrs x15, s3_6_c11_c5_0
+ 33e4: d51eb52f msr s3_6_c11_c5_1, x15
+ 33e8: d53eb52f mrs x15, s3_6_c11_c5_1
+ 33ec: d51eb54f msr s3_6_c11_c5_2, x15
+ 33f0: d53eb54f mrs x15, s3_6_c11_c5_2
+ 33f4: d51eb56f msr s3_6_c11_c5_3, x15
+ 33f8: d53eb56f mrs x15, s3_6_c11_c5_3
+ 33fc: d51eb58f msr s3_6_c11_c5_4, x15
+ 3400: d53eb58f mrs x15, s3_6_c11_c5_4
+ 3404: d51eb5af msr s3_6_c11_c5_5, x15
+ 3408: d53eb5af mrs x15, s3_6_c11_c5_5
+ 340c: d51eb5cf msr s3_6_c11_c5_6, x15
+ 3410: d53eb5cf mrs x15, s3_6_c11_c5_6
+ 3414: d51eb5ef msr s3_6_c11_c5_7, x15
+ 3418: d53eb5ef mrs x15, s3_6_c11_c5_7
+ 341c: d51eb60f msr s3_6_c11_c6_0, x15
+ 3420: d53eb60f mrs x15, s3_6_c11_c6_0
+ 3424: d51eb62f msr s3_6_c11_c6_1, x15
+ 3428: d53eb62f mrs x15, s3_6_c11_c6_1
+ 342c: d51eb64f msr s3_6_c11_c6_2, x15
+ 3430: d53eb64f mrs x15, s3_6_c11_c6_2
+ 3434: d51eb66f msr s3_6_c11_c6_3, x15
+ 3438: d53eb66f mrs x15, s3_6_c11_c6_3
+ 343c: d51eb68f msr s3_6_c11_c6_4, x15
+ 3440: d53eb68f mrs x15, s3_6_c11_c6_4
+ 3444: d51eb6af msr s3_6_c11_c6_5, x15
+ 3448: d53eb6af mrs x15, s3_6_c11_c6_5
+ 344c: d51eb6cf msr s3_6_c11_c6_6, x15
+ 3450: d53eb6cf mrs x15, s3_6_c11_c6_6
+ 3454: d51eb6ef msr s3_6_c11_c6_7, x15
+ 3458: d53eb6ef mrs x15, s3_6_c11_c6_7
+ 345c: d51eb70f msr s3_6_c11_c7_0, x15
+ 3460: d53eb70f mrs x15, s3_6_c11_c7_0
+ 3464: d51eb72f msr s3_6_c11_c7_1, x15
+ 3468: d53eb72f mrs x15, s3_6_c11_c7_1
+ 346c: d51eb74f msr s3_6_c11_c7_2, x15
+ 3470: d53eb74f mrs x15, s3_6_c11_c7_2
+ 3474: d51eb76f msr s3_6_c11_c7_3, x15
+ 3478: d53eb76f mrs x15, s3_6_c11_c7_3
+ 347c: d51eb78f msr s3_6_c11_c7_4, x15
+ 3480: d53eb78f mrs x15, s3_6_c11_c7_4
+ 3484: d51eb7af msr s3_6_c11_c7_5, x15
+ 3488: d53eb7af mrs x15, s3_6_c11_c7_5
+ 348c: d51eb7cf msr s3_6_c11_c7_6, x15
+ 3490: d53eb7cf mrs x15, s3_6_c11_c7_6
+ 3494: d51eb7ef msr s3_6_c11_c7_7, x15
+ 3498: d53eb7ef mrs x15, s3_6_c11_c7_7
+ 349c: d51eb80f msr s3_6_c11_c8_0, x15
+ 34a0: d53eb80f mrs x15, s3_6_c11_c8_0
+ 34a4: d51eb82f msr s3_6_c11_c8_1, x15
+ 34a8: d53eb82f mrs x15, s3_6_c11_c8_1
+ 34ac: d51eb84f msr s3_6_c11_c8_2, x15
+ 34b0: d53eb84f mrs x15, s3_6_c11_c8_2
+ 34b4: d51eb86f msr s3_6_c11_c8_3, x15
+ 34b8: d53eb86f mrs x15, s3_6_c11_c8_3
+ 34bc: d51eb88f msr s3_6_c11_c8_4, x15
+ 34c0: d53eb88f mrs x15, s3_6_c11_c8_4
+ 34c4: d51eb8af msr s3_6_c11_c8_5, x15
+ 34c8: d53eb8af mrs x15, s3_6_c11_c8_5
+ 34cc: d51eb8cf msr s3_6_c11_c8_6, x15
+ 34d0: d53eb8cf mrs x15, s3_6_c11_c8_6
+ 34d4: d51eb8ef msr s3_6_c11_c8_7, x15
+ 34d8: d53eb8ef mrs x15, s3_6_c11_c8_7
+ 34dc: d51eb90f msr s3_6_c11_c9_0, x15
+ 34e0: d53eb90f mrs x15, s3_6_c11_c9_0
+ 34e4: d51eb92f msr s3_6_c11_c9_1, x15
+ 34e8: d53eb92f mrs x15, s3_6_c11_c9_1
+ 34ec: d51eb94f msr s3_6_c11_c9_2, x15
+ 34f0: d53eb94f mrs x15, s3_6_c11_c9_2
+ 34f4: d51eb96f msr s3_6_c11_c9_3, x15
+ 34f8: d53eb96f mrs x15, s3_6_c11_c9_3
+ 34fc: d51eb98f msr s3_6_c11_c9_4, x15
+ 3500: d53eb98f mrs x15, s3_6_c11_c9_4
+ 3504: d51eb9af msr s3_6_c11_c9_5, x15
+ 3508: d53eb9af mrs x15, s3_6_c11_c9_5
+ 350c: d51eb9cf msr s3_6_c11_c9_6, x15
+ 3510: d53eb9cf mrs x15, s3_6_c11_c9_6
+ 3514: d51eb9ef msr s3_6_c11_c9_7, x15
+ 3518: d53eb9ef mrs x15, s3_6_c11_c9_7
+ 351c: d51eba0f msr s3_6_c11_c10_0, x15
+ 3520: d53eba0f mrs x15, s3_6_c11_c10_0
+ 3524: d51eba2f msr s3_6_c11_c10_1, x15
+ 3528: d53eba2f mrs x15, s3_6_c11_c10_1
+ 352c: d51eba4f msr s3_6_c11_c10_2, x15
+ 3530: d53eba4f mrs x15, s3_6_c11_c10_2
+ 3534: d51eba6f msr s3_6_c11_c10_3, x15
+ 3538: d53eba6f mrs x15, s3_6_c11_c10_3
+ 353c: d51eba8f msr s3_6_c11_c10_4, x15
+ 3540: d53eba8f mrs x15, s3_6_c11_c10_4
+ 3544: d51ebaaf msr s3_6_c11_c10_5, x15
+ 3548: d53ebaaf mrs x15, s3_6_c11_c10_5
+ 354c: d51ebacf msr s3_6_c11_c10_6, x15
+ 3550: d53ebacf mrs x15, s3_6_c11_c10_6
+ 3554: d51ebaef msr s3_6_c11_c10_7, x15
+ 3558: d53ebaef mrs x15, s3_6_c11_c10_7
+ 355c: d51ebb0f msr s3_6_c11_c11_0, x15
+ 3560: d53ebb0f mrs x15, s3_6_c11_c11_0
+ 3564: d51ebb2f msr s3_6_c11_c11_1, x15
+ 3568: d53ebb2f mrs x15, s3_6_c11_c11_1
+ 356c: d51ebb4f msr s3_6_c11_c11_2, x15
+ 3570: d53ebb4f mrs x15, s3_6_c11_c11_2
+ 3574: d51ebb6f msr s3_6_c11_c11_3, x15
+ 3578: d53ebb6f mrs x15, s3_6_c11_c11_3
+ 357c: d51ebb8f msr s3_6_c11_c11_4, x15
+ 3580: d53ebb8f mrs x15, s3_6_c11_c11_4
+ 3584: d51ebbaf msr s3_6_c11_c11_5, x15
+ 3588: d53ebbaf mrs x15, s3_6_c11_c11_5
+ 358c: d51ebbcf msr s3_6_c11_c11_6, x15
+ 3590: d53ebbcf mrs x15, s3_6_c11_c11_6
+ 3594: d51ebbef msr s3_6_c11_c11_7, x15
+ 3598: d53ebbef mrs x15, s3_6_c11_c11_7
+ 359c: d51ebc0f msr s3_6_c11_c12_0, x15
+ 35a0: d53ebc0f mrs x15, s3_6_c11_c12_0
+ 35a4: d51ebc2f msr s3_6_c11_c12_1, x15
+ 35a8: d53ebc2f mrs x15, s3_6_c11_c12_1
+ 35ac: d51ebc4f msr s3_6_c11_c12_2, x15
+ 35b0: d53ebc4f mrs x15, s3_6_c11_c12_2
+ 35b4: d51ebc6f msr s3_6_c11_c12_3, x15
+ 35b8: d53ebc6f mrs x15, s3_6_c11_c12_3
+ 35bc: d51ebc8f msr s3_6_c11_c12_4, x15
+ 35c0: d53ebc8f mrs x15, s3_6_c11_c12_4
+ 35c4: d51ebcaf msr s3_6_c11_c12_5, x15
+ 35c8: d53ebcaf mrs x15, s3_6_c11_c12_5
+ 35cc: d51ebccf msr s3_6_c11_c12_6, x15
+ 35d0: d53ebccf mrs x15, s3_6_c11_c12_6
+ 35d4: d51ebcef msr s3_6_c11_c12_7, x15
+ 35d8: d53ebcef mrs x15, s3_6_c11_c12_7
+ 35dc: d51ebd0f msr s3_6_c11_c13_0, x15
+ 35e0: d53ebd0f mrs x15, s3_6_c11_c13_0
+ 35e4: d51ebd2f msr s3_6_c11_c13_1, x15
+ 35e8: d53ebd2f mrs x15, s3_6_c11_c13_1
+ 35ec: d51ebd4f msr s3_6_c11_c13_2, x15
+ 35f0: d53ebd4f mrs x15, s3_6_c11_c13_2
+ 35f4: d51ebd6f msr s3_6_c11_c13_3, x15
+ 35f8: d53ebd6f mrs x15, s3_6_c11_c13_3
+ 35fc: d51ebd8f msr s3_6_c11_c13_4, x15
+ 3600: d53ebd8f mrs x15, s3_6_c11_c13_4
+ 3604: d51ebdaf msr s3_6_c11_c13_5, x15
+ 3608: d53ebdaf mrs x15, s3_6_c11_c13_5
+ 360c: d51ebdcf msr s3_6_c11_c13_6, x15
+ 3610: d53ebdcf mrs x15, s3_6_c11_c13_6
+ 3614: d51ebdef msr s3_6_c11_c13_7, x15
+ 3618: d53ebdef mrs x15, s3_6_c11_c13_7
+ 361c: d51ebe0f msr s3_6_c11_c14_0, x15
+ 3620: d53ebe0f mrs x15, s3_6_c11_c14_0
+ 3624: d51ebe2f msr s3_6_c11_c14_1, x15
+ 3628: d53ebe2f mrs x15, s3_6_c11_c14_1
+ 362c: d51ebe4f msr s3_6_c11_c14_2, x15
+ 3630: d53ebe4f mrs x15, s3_6_c11_c14_2
+ 3634: d51ebe6f msr s3_6_c11_c14_3, x15
+ 3638: d53ebe6f mrs x15, s3_6_c11_c14_3
+ 363c: d51ebe8f msr s3_6_c11_c14_4, x15
+ 3640: d53ebe8f mrs x15, s3_6_c11_c14_4
+ 3644: d51ebeaf msr s3_6_c11_c14_5, x15
+ 3648: d53ebeaf mrs x15, s3_6_c11_c14_5
+ 364c: d51ebecf msr s3_6_c11_c14_6, x15
+ 3650: d53ebecf mrs x15, s3_6_c11_c14_6
+ 3654: d51ebeef msr s3_6_c11_c14_7, x15
+ 3658: d53ebeef mrs x15, s3_6_c11_c14_7
+ 365c: d51ebf0f msr s3_6_c11_c15_0, x15
+ 3660: d53ebf0f mrs x15, s3_6_c11_c15_0
+ 3664: d51ebf2f msr s3_6_c11_c15_1, x15
+ 3668: d53ebf2f mrs x15, s3_6_c11_c15_1
+ 366c: d51ebf4f msr s3_6_c11_c15_2, x15
+ 3670: d53ebf4f mrs x15, s3_6_c11_c15_2
+ 3674: d51ebf6f msr s3_6_c11_c15_3, x15
+ 3678: d53ebf6f mrs x15, s3_6_c11_c15_3
+ 367c: d51ebf8f msr s3_6_c11_c15_4, x15
+ 3680: d53ebf8f mrs x15, s3_6_c11_c15_4
+ 3684: d51ebfaf msr s3_6_c11_c15_5, x15
+ 3688: d53ebfaf mrs x15, s3_6_c11_c15_5
+ 368c: d51ebfcf msr s3_6_c11_c15_6, x15
+ 3690: d53ebfcf mrs x15, s3_6_c11_c15_6
+ 3694: d51ebfef msr s3_6_c11_c15_7, x15
+ 3698: d53ebfef mrs x15, s3_6_c11_c15_7
+ 369c: d51ef00f msr s3_6_c15_c0_0, x15
+ 36a0: d53ef00f mrs x15, s3_6_c15_c0_0
+ 36a4: d51ef02f msr s3_6_c15_c0_1, x15
+ 36a8: d53ef02f mrs x15, s3_6_c15_c0_1
+ 36ac: d51ef04f msr s3_6_c15_c0_2, x15
+ 36b0: d53ef04f mrs x15, s3_6_c15_c0_2
+ 36b4: d51ef06f msr s3_6_c15_c0_3, x15
+ 36b8: d53ef06f mrs x15, s3_6_c15_c0_3
+ 36bc: d51ef08f msr s3_6_c15_c0_4, x15
+ 36c0: d53ef08f mrs x15, s3_6_c15_c0_4
+ 36c4: d51ef0af msr s3_6_c15_c0_5, x15
+ 36c8: d53ef0af mrs x15, s3_6_c15_c0_5
+ 36cc: d51ef0cf msr s3_6_c15_c0_6, x15
+ 36d0: d53ef0cf mrs x15, s3_6_c15_c0_6
+ 36d4: d51ef0ef msr s3_6_c15_c0_7, x15
+ 36d8: d53ef0ef mrs x15, s3_6_c15_c0_7
+ 36dc: d51ef10f msr s3_6_c15_c1_0, x15
+ 36e0: d53ef10f mrs x15, s3_6_c15_c1_0
+ 36e4: d51ef12f msr s3_6_c15_c1_1, x15
+ 36e8: d53ef12f mrs x15, s3_6_c15_c1_1
+ 36ec: d51ef14f msr s3_6_c15_c1_2, x15
+ 36f0: d53ef14f mrs x15, s3_6_c15_c1_2
+ 36f4: d51ef16f msr s3_6_c15_c1_3, x15
+ 36f8: d53ef16f mrs x15, s3_6_c15_c1_3
+ 36fc: d51ef18f msr s3_6_c15_c1_4, x15
+ 3700: d53ef18f mrs x15, s3_6_c15_c1_4
+ 3704: d51ef1af msr s3_6_c15_c1_5, x15
+ 3708: d53ef1af mrs x15, s3_6_c15_c1_5
+ 370c: d51ef1cf msr s3_6_c15_c1_6, x15
+ 3710: d53ef1cf mrs x15, s3_6_c15_c1_6
+ 3714: d51ef1ef msr s3_6_c15_c1_7, x15
+ 3718: d53ef1ef mrs x15, s3_6_c15_c1_7
+ 371c: d51ef20f msr s3_6_c15_c2_0, x15
+ 3720: d53ef20f mrs x15, s3_6_c15_c2_0
+ 3724: d51ef22f msr s3_6_c15_c2_1, x15
+ 3728: d53ef22f mrs x15, s3_6_c15_c2_1
+ 372c: d51ef24f msr s3_6_c15_c2_2, x15
+ 3730: d53ef24f mrs x15, s3_6_c15_c2_2
+ 3734: d51ef26f msr s3_6_c15_c2_3, x15
+ 3738: d53ef26f mrs x15, s3_6_c15_c2_3
+ 373c: d51ef28f msr s3_6_c15_c2_4, x15
+ 3740: d53ef28f mrs x15, s3_6_c15_c2_4
+ 3744: d51ef2af msr s3_6_c15_c2_5, x15
+ 3748: d53ef2af mrs x15, s3_6_c15_c2_5
+ 374c: d51ef2cf msr s3_6_c15_c2_6, x15
+ 3750: d53ef2cf mrs x15, s3_6_c15_c2_6
+ 3754: d51ef2ef msr s3_6_c15_c2_7, x15
+ 3758: d53ef2ef mrs x15, s3_6_c15_c2_7
+ 375c: d51ef30f msr s3_6_c15_c3_0, x15
+ 3760: d53ef30f mrs x15, s3_6_c15_c3_0
+ 3764: d51ef32f msr s3_6_c15_c3_1, x15
+ 3768: d53ef32f mrs x15, s3_6_c15_c3_1
+ 376c: d51ef34f msr s3_6_c15_c3_2, x15
+ 3770: d53ef34f mrs x15, s3_6_c15_c3_2
+ 3774: d51ef36f msr s3_6_c15_c3_3, x15
+ 3778: d53ef36f mrs x15, s3_6_c15_c3_3
+ 377c: d51ef38f msr s3_6_c15_c3_4, x15
+ 3780: d53ef38f mrs x15, s3_6_c15_c3_4
+ 3784: d51ef3af msr s3_6_c15_c3_5, x15
+ 3788: d53ef3af mrs x15, s3_6_c15_c3_5
+ 378c: d51ef3cf msr s3_6_c15_c3_6, x15
+ 3790: d53ef3cf mrs x15, s3_6_c15_c3_6
+ 3794: d51ef3ef msr s3_6_c15_c3_7, x15
+ 3798: d53ef3ef mrs x15, s3_6_c15_c3_7
+ 379c: d51ef40f msr s3_6_c15_c4_0, x15
+ 37a0: d53ef40f mrs x15, s3_6_c15_c4_0
+ 37a4: d51ef42f msr s3_6_c15_c4_1, x15
+ 37a8: d53ef42f mrs x15, s3_6_c15_c4_1
+ 37ac: d51ef44f msr s3_6_c15_c4_2, x15
+ 37b0: d53ef44f mrs x15, s3_6_c15_c4_2
+ 37b4: d51ef46f msr s3_6_c15_c4_3, x15
+ 37b8: d53ef46f mrs x15, s3_6_c15_c4_3
+ 37bc: d51ef48f msr s3_6_c15_c4_4, x15
+ 37c0: d53ef48f mrs x15, s3_6_c15_c4_4
+ 37c4: d51ef4af msr s3_6_c15_c4_5, x15
+ 37c8: d53ef4af mrs x15, s3_6_c15_c4_5
+ 37cc: d51ef4cf msr s3_6_c15_c4_6, x15
+ 37d0: d53ef4cf mrs x15, s3_6_c15_c4_6
+ 37d4: d51ef4ef msr s3_6_c15_c4_7, x15
+ 37d8: d53ef4ef mrs x15, s3_6_c15_c4_7
+ 37dc: d51ef50f msr s3_6_c15_c5_0, x15
+ 37e0: d53ef50f mrs x15, s3_6_c15_c5_0
+ 37e4: d51ef52f msr s3_6_c15_c5_1, x15
+ 37e8: d53ef52f mrs x15, s3_6_c15_c5_1
+ 37ec: d51ef54f msr s3_6_c15_c5_2, x15
+ 37f0: d53ef54f mrs x15, s3_6_c15_c5_2
+ 37f4: d51ef56f msr s3_6_c15_c5_3, x15
+ 37f8: d53ef56f mrs x15, s3_6_c15_c5_3
+ 37fc: d51ef58f msr s3_6_c15_c5_4, x15
+ 3800: d53ef58f mrs x15, s3_6_c15_c5_4
+ 3804: d51ef5af msr s3_6_c15_c5_5, x15
+ 3808: d53ef5af mrs x15, s3_6_c15_c5_5
+ 380c: d51ef5cf msr s3_6_c15_c5_6, x15
+ 3810: d53ef5cf mrs x15, s3_6_c15_c5_6
+ 3814: d51ef5ef msr s3_6_c15_c5_7, x15
+ 3818: d53ef5ef mrs x15, s3_6_c15_c5_7
+ 381c: d51ef60f msr s3_6_c15_c6_0, x15
+ 3820: d53ef60f mrs x15, s3_6_c15_c6_0
+ 3824: d51ef62f msr s3_6_c15_c6_1, x15
+ 3828: d53ef62f mrs x15, s3_6_c15_c6_1
+ 382c: d51ef64f msr s3_6_c15_c6_2, x15
+ 3830: d53ef64f mrs x15, s3_6_c15_c6_2
+ 3834: d51ef66f msr s3_6_c15_c6_3, x15
+ 3838: d53ef66f mrs x15, s3_6_c15_c6_3
+ 383c: d51ef68f msr s3_6_c15_c6_4, x15
+ 3840: d53ef68f mrs x15, s3_6_c15_c6_4
+ 3844: d51ef6af msr s3_6_c15_c6_5, x15
+ 3848: d53ef6af mrs x15, s3_6_c15_c6_5
+ 384c: d51ef6cf msr s3_6_c15_c6_6, x15
+ 3850: d53ef6cf mrs x15, s3_6_c15_c6_6
+ 3854: d51ef6ef msr s3_6_c15_c6_7, x15
+ 3858: d53ef6ef mrs x15, s3_6_c15_c6_7
+ 385c: d51ef70f msr s3_6_c15_c7_0, x15
+ 3860: d53ef70f mrs x15, s3_6_c15_c7_0
+ 3864: d51ef72f msr s3_6_c15_c7_1, x15
+ 3868: d53ef72f mrs x15, s3_6_c15_c7_1
+ 386c: d51ef74f msr s3_6_c15_c7_2, x15
+ 3870: d53ef74f mrs x15, s3_6_c15_c7_2
+ 3874: d51ef76f msr s3_6_c15_c7_3, x15
+ 3878: d53ef76f mrs x15, s3_6_c15_c7_3
+ 387c: d51ef78f msr s3_6_c15_c7_4, x15
+ 3880: d53ef78f mrs x15, s3_6_c15_c7_4
+ 3884: d51ef7af msr s3_6_c15_c7_5, x15
+ 3888: d53ef7af mrs x15, s3_6_c15_c7_5
+ 388c: d51ef7cf msr s3_6_c15_c7_6, x15
+ 3890: d53ef7cf mrs x15, s3_6_c15_c7_6
+ 3894: d51ef7ef msr s3_6_c15_c7_7, x15
+ 3898: d53ef7ef mrs x15, s3_6_c15_c7_7
+ 389c: d51ef80f msr s3_6_c15_c8_0, x15
+ 38a0: d53ef80f mrs x15, s3_6_c15_c8_0
+ 38a4: d51ef82f msr s3_6_c15_c8_1, x15
+ 38a8: d53ef82f mrs x15, s3_6_c15_c8_1
+ 38ac: d51ef84f msr s3_6_c15_c8_2, x15
+ 38b0: d53ef84f mrs x15, s3_6_c15_c8_2
+ 38b4: d51ef86f msr s3_6_c15_c8_3, x15
+ 38b8: d53ef86f mrs x15, s3_6_c15_c8_3
+ 38bc: d51ef88f msr s3_6_c15_c8_4, x15
+ 38c0: d53ef88f mrs x15, s3_6_c15_c8_4
+ 38c4: d51ef8af msr s3_6_c15_c8_5, x15
+ 38c8: d53ef8af mrs x15, s3_6_c15_c8_5
+ 38cc: d51ef8cf msr s3_6_c15_c8_6, x15
+ 38d0: d53ef8cf mrs x15, s3_6_c15_c8_6
+ 38d4: d51ef8ef msr s3_6_c15_c8_7, x15
+ 38d8: d53ef8ef mrs x15, s3_6_c15_c8_7
+ 38dc: d51ef90f msr s3_6_c15_c9_0, x15
+ 38e0: d53ef90f mrs x15, s3_6_c15_c9_0
+ 38e4: d51ef92f msr s3_6_c15_c9_1, x15
+ 38e8: d53ef92f mrs x15, s3_6_c15_c9_1
+ 38ec: d51ef94f msr s3_6_c15_c9_2, x15
+ 38f0: d53ef94f mrs x15, s3_6_c15_c9_2
+ 38f4: d51ef96f msr s3_6_c15_c9_3, x15
+ 38f8: d53ef96f mrs x15, s3_6_c15_c9_3
+ 38fc: d51ef98f msr s3_6_c15_c9_4, x15
+ 3900: d53ef98f mrs x15, s3_6_c15_c9_4
+ 3904: d51ef9af msr s3_6_c15_c9_5, x15
+ 3908: d53ef9af mrs x15, s3_6_c15_c9_5
+ 390c: d51ef9cf msr s3_6_c15_c9_6, x15
+ 3910: d53ef9cf mrs x15, s3_6_c15_c9_6
+ 3914: d51ef9ef msr s3_6_c15_c9_7, x15
+ 3918: d53ef9ef mrs x15, s3_6_c15_c9_7
+ 391c: d51efa0f msr s3_6_c15_c10_0, x15
+ 3920: d53efa0f mrs x15, s3_6_c15_c10_0
+ 3924: d51efa2f msr s3_6_c15_c10_1, x15
+ 3928: d53efa2f mrs x15, s3_6_c15_c10_1
+ 392c: d51efa4f msr s3_6_c15_c10_2, x15
+ 3930: d53efa4f mrs x15, s3_6_c15_c10_2
+ 3934: d51efa6f msr s3_6_c15_c10_3, x15
+ 3938: d53efa6f mrs x15, s3_6_c15_c10_3
+ 393c: d51efa8f msr s3_6_c15_c10_4, x15
+ 3940: d53efa8f mrs x15, s3_6_c15_c10_4
+ 3944: d51efaaf msr s3_6_c15_c10_5, x15
+ 3948: d53efaaf mrs x15, s3_6_c15_c10_5
+ 394c: d51efacf msr s3_6_c15_c10_6, x15
+ 3950: d53efacf mrs x15, s3_6_c15_c10_6
+ 3954: d51efaef msr s3_6_c15_c10_7, x15
+ 3958: d53efaef mrs x15, s3_6_c15_c10_7
+ 395c: d51efb0f msr s3_6_c15_c11_0, x15
+ 3960: d53efb0f mrs x15, s3_6_c15_c11_0
+ 3964: d51efb2f msr s3_6_c15_c11_1, x15
+ 3968: d53efb2f mrs x15, s3_6_c15_c11_1
+ 396c: d51efb4f msr s3_6_c15_c11_2, x15
+ 3970: d53efb4f mrs x15, s3_6_c15_c11_2
+ 3974: d51efb6f msr s3_6_c15_c11_3, x15
+ 3978: d53efb6f mrs x15, s3_6_c15_c11_3
+ 397c: d51efb8f msr s3_6_c15_c11_4, x15
+ 3980: d53efb8f mrs x15, s3_6_c15_c11_4
+ 3984: d51efbaf msr s3_6_c15_c11_5, x15
+ 3988: d53efbaf mrs x15, s3_6_c15_c11_5
+ 398c: d51efbcf msr s3_6_c15_c11_6, x15
+ 3990: d53efbcf mrs x15, s3_6_c15_c11_6
+ 3994: d51efbef msr s3_6_c15_c11_7, x15
+ 3998: d53efbef mrs x15, s3_6_c15_c11_7
+ 399c: d51efc0f msr s3_6_c15_c12_0, x15
+ 39a0: d53efc0f mrs x15, s3_6_c15_c12_0
+ 39a4: d51efc2f msr s3_6_c15_c12_1, x15
+ 39a8: d53efc2f mrs x15, s3_6_c15_c12_1
+ 39ac: d51efc4f msr s3_6_c15_c12_2, x15
+ 39b0: d53efc4f mrs x15, s3_6_c15_c12_2
+ 39b4: d51efc6f msr s3_6_c15_c12_3, x15
+ 39b8: d53efc6f mrs x15, s3_6_c15_c12_3
+ 39bc: d51efc8f msr s3_6_c15_c12_4, x15
+ 39c0: d53efc8f mrs x15, s3_6_c15_c12_4
+ 39c4: d51efcaf msr s3_6_c15_c12_5, x15
+ 39c8: d53efcaf mrs x15, s3_6_c15_c12_5
+ 39cc: d51efccf msr s3_6_c15_c12_6, x15
+ 39d0: d53efccf mrs x15, s3_6_c15_c12_6
+ 39d4: d51efcef msr s3_6_c15_c12_7, x15
+ 39d8: d53efcef mrs x15, s3_6_c15_c12_7
+ 39dc: d51efd0f msr s3_6_c15_c13_0, x15
+ 39e0: d53efd0f mrs x15, s3_6_c15_c13_0
+ 39e4: d51efd2f msr s3_6_c15_c13_1, x15
+ 39e8: d53efd2f mrs x15, s3_6_c15_c13_1
+ 39ec: d51efd4f msr s3_6_c15_c13_2, x15
+ 39f0: d53efd4f mrs x15, s3_6_c15_c13_2
+ 39f4: d51efd6f msr s3_6_c15_c13_3, x15
+ 39f8: d53efd6f mrs x15, s3_6_c15_c13_3
+ 39fc: d51efd8f msr s3_6_c15_c13_4, x15
+ 3a00: d53efd8f mrs x15, s3_6_c15_c13_4
+ 3a04: d51efdaf msr s3_6_c15_c13_5, x15
+ 3a08: d53efdaf mrs x15, s3_6_c15_c13_5
+ 3a0c: d51efdcf msr s3_6_c15_c13_6, x15
+ 3a10: d53efdcf mrs x15, s3_6_c15_c13_6
+ 3a14: d51efdef msr s3_6_c15_c13_7, x15
+ 3a18: d53efdef mrs x15, s3_6_c15_c13_7
+ 3a1c: d51efe0f msr s3_6_c15_c14_0, x15
+ 3a20: d53efe0f mrs x15, s3_6_c15_c14_0
+ 3a24: d51efe2f msr s3_6_c15_c14_1, x15
+ 3a28: d53efe2f mrs x15, s3_6_c15_c14_1
+ 3a2c: d51efe4f msr s3_6_c15_c14_2, x15
+ 3a30: d53efe4f mrs x15, s3_6_c15_c14_2
+ 3a34: d51efe6f msr s3_6_c15_c14_3, x15
+ 3a38: d53efe6f mrs x15, s3_6_c15_c14_3
+ 3a3c: d51efe8f msr s3_6_c15_c14_4, x15
+ 3a40: d53efe8f mrs x15, s3_6_c15_c14_4
+ 3a44: d51efeaf msr s3_6_c15_c14_5, x15
+ 3a48: d53efeaf mrs x15, s3_6_c15_c14_5
+ 3a4c: d51efecf msr s3_6_c15_c14_6, x15
+ 3a50: d53efecf mrs x15, s3_6_c15_c14_6
+ 3a54: d51efeef msr s3_6_c15_c14_7, x15
+ 3a58: d53efeef mrs x15, s3_6_c15_c14_7
+ 3a5c: d51eff0f msr s3_6_c15_c15_0, x15
+ 3a60: d53eff0f mrs x15, s3_6_c15_c15_0
+ 3a64: d51eff2f msr s3_6_c15_c15_1, x15
+ 3a68: d53eff2f mrs x15, s3_6_c15_c15_1
+ 3a6c: d51eff4f msr s3_6_c15_c15_2, x15
+ 3a70: d53eff4f mrs x15, s3_6_c15_c15_2
+ 3a74: d51eff6f msr s3_6_c15_c15_3, x15
+ 3a78: d53eff6f mrs x15, s3_6_c15_c15_3
+ 3a7c: d51eff8f msr s3_6_c15_c15_4, x15
+ 3a80: d53eff8f mrs x15, s3_6_c15_c15_4
+ 3a84: d51effaf msr s3_6_c15_c15_5, x15
+ 3a88: d53effaf mrs x15, s3_6_c15_c15_5
+ 3a8c: d51effcf msr s3_6_c15_c15_6, x15
+ 3a90: d53effcf mrs x15, s3_6_c15_c15_6
+ 3a94: d51effef msr s3_6_c15_c15_7, x15
+ 3a98: d53effef mrs x15, s3_6_c15_c15_7
+ 3a9c: d51fb00f msr s3_7_c11_c0_0, x15
+ 3aa0: d53fb00f mrs x15, s3_7_c11_c0_0
+ 3aa4: d51fb02f msr s3_7_c11_c0_1, x15
+ 3aa8: d53fb02f mrs x15, s3_7_c11_c0_1
+ 3aac: d51fb04f msr s3_7_c11_c0_2, x15
+ 3ab0: d53fb04f mrs x15, s3_7_c11_c0_2
+ 3ab4: d51fb06f msr s3_7_c11_c0_3, x15
+ 3ab8: d53fb06f mrs x15, s3_7_c11_c0_3
+ 3abc: d51fb08f msr s3_7_c11_c0_4, x15
+ 3ac0: d53fb08f mrs x15, s3_7_c11_c0_4
+ 3ac4: d51fb0af msr s3_7_c11_c0_5, x15
+ 3ac8: d53fb0af mrs x15, s3_7_c11_c0_5
+ 3acc: d51fb0cf msr s3_7_c11_c0_6, x15
+ 3ad0: d53fb0cf mrs x15, s3_7_c11_c0_6
+ 3ad4: d51fb0ef msr s3_7_c11_c0_7, x15
+ 3ad8: d53fb0ef mrs x15, s3_7_c11_c0_7
+ 3adc: d51fb10f msr s3_7_c11_c1_0, x15
+ 3ae0: d53fb10f mrs x15, s3_7_c11_c1_0
+ 3ae4: d51fb12f msr s3_7_c11_c1_1, x15
+ 3ae8: d53fb12f mrs x15, s3_7_c11_c1_1
+ 3aec: d51fb14f msr s3_7_c11_c1_2, x15
+ 3af0: d53fb14f mrs x15, s3_7_c11_c1_2
+ 3af4: d51fb16f msr s3_7_c11_c1_3, x15
+ 3af8: d53fb16f mrs x15, s3_7_c11_c1_3
+ 3afc: d51fb18f msr s3_7_c11_c1_4, x15
+ 3b00: d53fb18f mrs x15, s3_7_c11_c1_4
+ 3b04: d51fb1af msr s3_7_c11_c1_5, x15
+ 3b08: d53fb1af mrs x15, s3_7_c11_c1_5
+ 3b0c: d51fb1cf msr s3_7_c11_c1_6, x15
+ 3b10: d53fb1cf mrs x15, s3_7_c11_c1_6
+ 3b14: d51fb1ef msr s3_7_c11_c1_7, x15
+ 3b18: d53fb1ef mrs x15, s3_7_c11_c1_7
+ 3b1c: d51fb20f msr s3_7_c11_c2_0, x15
+ 3b20: d53fb20f mrs x15, s3_7_c11_c2_0
+ 3b24: d51fb22f msr s3_7_c11_c2_1, x15
+ 3b28: d53fb22f mrs x15, s3_7_c11_c2_1
+ 3b2c: d51fb24f msr s3_7_c11_c2_2, x15
+ 3b30: d53fb24f mrs x15, s3_7_c11_c2_2
+ 3b34: d51fb26f msr s3_7_c11_c2_3, x15
+ 3b38: d53fb26f mrs x15, s3_7_c11_c2_3
+ 3b3c: d51fb28f msr s3_7_c11_c2_4, x15
+ 3b40: d53fb28f mrs x15, s3_7_c11_c2_4
+ 3b44: d51fb2af msr s3_7_c11_c2_5, x15
+ 3b48: d53fb2af mrs x15, s3_7_c11_c2_5
+ 3b4c: d51fb2cf msr s3_7_c11_c2_6, x15
+ 3b50: d53fb2cf mrs x15, s3_7_c11_c2_6
+ 3b54: d51fb2ef msr s3_7_c11_c2_7, x15
+ 3b58: d53fb2ef mrs x15, s3_7_c11_c2_7
+ 3b5c: d51fb30f msr s3_7_c11_c3_0, x15
+ 3b60: d53fb30f mrs x15, s3_7_c11_c3_0
+ 3b64: d51fb32f msr s3_7_c11_c3_1, x15
+ 3b68: d53fb32f mrs x15, s3_7_c11_c3_1
+ 3b6c: d51fb34f msr s3_7_c11_c3_2, x15
+ 3b70: d53fb34f mrs x15, s3_7_c11_c3_2
+ 3b74: d51fb36f msr s3_7_c11_c3_3, x15
+ 3b78: d53fb36f mrs x15, s3_7_c11_c3_3
+ 3b7c: d51fb38f msr s3_7_c11_c3_4, x15
+ 3b80: d53fb38f mrs x15, s3_7_c11_c3_4
+ 3b84: d51fb3af msr s3_7_c11_c3_5, x15
+ 3b88: d53fb3af mrs x15, s3_7_c11_c3_5
+ 3b8c: d51fb3cf msr s3_7_c11_c3_6, x15
+ 3b90: d53fb3cf mrs x15, s3_7_c11_c3_6
+ 3b94: d51fb3ef msr s3_7_c11_c3_7, x15
+ 3b98: d53fb3ef mrs x15, s3_7_c11_c3_7
+ 3b9c: d51fb40f msr s3_7_c11_c4_0, x15
+ 3ba0: d53fb40f mrs x15, s3_7_c11_c4_0
+ 3ba4: d51fb42f msr s3_7_c11_c4_1, x15
+ 3ba8: d53fb42f mrs x15, s3_7_c11_c4_1
+ 3bac: d51fb44f msr s3_7_c11_c4_2, x15
+ 3bb0: d53fb44f mrs x15, s3_7_c11_c4_2
+ 3bb4: d51fb46f msr s3_7_c11_c4_3, x15
+ 3bb8: d53fb46f mrs x15, s3_7_c11_c4_3
+ 3bbc: d51fb48f msr s3_7_c11_c4_4, x15
+ 3bc0: d53fb48f mrs x15, s3_7_c11_c4_4
+ 3bc4: d51fb4af msr s3_7_c11_c4_5, x15
+ 3bc8: d53fb4af mrs x15, s3_7_c11_c4_5
+ 3bcc: d51fb4cf msr s3_7_c11_c4_6, x15
+ 3bd0: d53fb4cf mrs x15, s3_7_c11_c4_6
+ 3bd4: d51fb4ef msr s3_7_c11_c4_7, x15
+ 3bd8: d53fb4ef mrs x15, s3_7_c11_c4_7
+ 3bdc: d51fb50f msr s3_7_c11_c5_0, x15
+ 3be0: d53fb50f mrs x15, s3_7_c11_c5_0
+ 3be4: d51fb52f msr s3_7_c11_c5_1, x15
+ 3be8: d53fb52f mrs x15, s3_7_c11_c5_1
+ 3bec: d51fb54f msr s3_7_c11_c5_2, x15
+ 3bf0: d53fb54f mrs x15, s3_7_c11_c5_2
+ 3bf4: d51fb56f msr s3_7_c11_c5_3, x15
+ 3bf8: d53fb56f mrs x15, s3_7_c11_c5_3
+ 3bfc: d51fb58f msr s3_7_c11_c5_4, x15
+ 3c00: d53fb58f mrs x15, s3_7_c11_c5_4
+ 3c04: d51fb5af msr s3_7_c11_c5_5, x15
+ 3c08: d53fb5af mrs x15, s3_7_c11_c5_5
+ 3c0c: d51fb5cf msr s3_7_c11_c5_6, x15
+ 3c10: d53fb5cf mrs x15, s3_7_c11_c5_6
+ 3c14: d51fb5ef msr s3_7_c11_c5_7, x15
+ 3c18: d53fb5ef mrs x15, s3_7_c11_c5_7
+ 3c1c: d51fb60f msr s3_7_c11_c6_0, x15
+ 3c20: d53fb60f mrs x15, s3_7_c11_c6_0
+ 3c24: d51fb62f msr s3_7_c11_c6_1, x15
+ 3c28: d53fb62f mrs x15, s3_7_c11_c6_1
+ 3c2c: d51fb64f msr s3_7_c11_c6_2, x15
+ 3c30: d53fb64f mrs x15, s3_7_c11_c6_2
+ 3c34: d51fb66f msr s3_7_c11_c6_3, x15
+ 3c38: d53fb66f mrs x15, s3_7_c11_c6_3
+ 3c3c: d51fb68f msr s3_7_c11_c6_4, x15
+ 3c40: d53fb68f mrs x15, s3_7_c11_c6_4
+ 3c44: d51fb6af msr s3_7_c11_c6_5, x15
+ 3c48: d53fb6af mrs x15, s3_7_c11_c6_5
+ 3c4c: d51fb6cf msr s3_7_c11_c6_6, x15
+ 3c50: d53fb6cf mrs x15, s3_7_c11_c6_6
+ 3c54: d51fb6ef msr s3_7_c11_c6_7, x15
+ 3c58: d53fb6ef mrs x15, s3_7_c11_c6_7
+ 3c5c: d51fb70f msr s3_7_c11_c7_0, x15
+ 3c60: d53fb70f mrs x15, s3_7_c11_c7_0
+ 3c64: d51fb72f msr s3_7_c11_c7_1, x15
+ 3c68: d53fb72f mrs x15, s3_7_c11_c7_1
+ 3c6c: d51fb74f msr s3_7_c11_c7_2, x15
+ 3c70: d53fb74f mrs x15, s3_7_c11_c7_2
+ 3c74: d51fb76f msr s3_7_c11_c7_3, x15
+ 3c78: d53fb76f mrs x15, s3_7_c11_c7_3
+ 3c7c: d51fb78f msr s3_7_c11_c7_4, x15
+ 3c80: d53fb78f mrs x15, s3_7_c11_c7_4
+ 3c84: d51fb7af msr s3_7_c11_c7_5, x15
+ 3c88: d53fb7af mrs x15, s3_7_c11_c7_5
+ 3c8c: d51fb7cf msr s3_7_c11_c7_6, x15
+ 3c90: d53fb7cf mrs x15, s3_7_c11_c7_6
+ 3c94: d51fb7ef msr s3_7_c11_c7_7, x15
+ 3c98: d53fb7ef mrs x15, s3_7_c11_c7_7
+ 3c9c: d51fb80f msr s3_7_c11_c8_0, x15
+ 3ca0: d53fb80f mrs x15, s3_7_c11_c8_0
+ 3ca4: d51fb82f msr s3_7_c11_c8_1, x15
+ 3ca8: d53fb82f mrs x15, s3_7_c11_c8_1
+ 3cac: d51fb84f msr s3_7_c11_c8_2, x15
+ 3cb0: d53fb84f mrs x15, s3_7_c11_c8_2
+ 3cb4: d51fb86f msr s3_7_c11_c8_3, x15
+ 3cb8: d53fb86f mrs x15, s3_7_c11_c8_3
+ 3cbc: d51fb88f msr s3_7_c11_c8_4, x15
+ 3cc0: d53fb88f mrs x15, s3_7_c11_c8_4
+ 3cc4: d51fb8af msr s3_7_c11_c8_5, x15
+ 3cc8: d53fb8af mrs x15, s3_7_c11_c8_5
+ 3ccc: d51fb8cf msr s3_7_c11_c8_6, x15
+ 3cd0: d53fb8cf mrs x15, s3_7_c11_c8_6
+ 3cd4: d51fb8ef msr s3_7_c11_c8_7, x15
+ 3cd8: d53fb8ef mrs x15, s3_7_c11_c8_7
+ 3cdc: d51fb90f msr s3_7_c11_c9_0, x15
+ 3ce0: d53fb90f mrs x15, s3_7_c11_c9_0
+ 3ce4: d51fb92f msr s3_7_c11_c9_1, x15
+ 3ce8: d53fb92f mrs x15, s3_7_c11_c9_1
+ 3cec: d51fb94f msr s3_7_c11_c9_2, x15
+ 3cf0: d53fb94f mrs x15, s3_7_c11_c9_2
+ 3cf4: d51fb96f msr s3_7_c11_c9_3, x15
+ 3cf8: d53fb96f mrs x15, s3_7_c11_c9_3
+ 3cfc: d51fb98f msr s3_7_c11_c9_4, x15
+ 3d00: d53fb98f mrs x15, s3_7_c11_c9_4
+ 3d04: d51fb9af msr s3_7_c11_c9_5, x15
+ 3d08: d53fb9af mrs x15, s3_7_c11_c9_5
+ 3d0c: d51fb9cf msr s3_7_c11_c9_6, x15
+ 3d10: d53fb9cf mrs x15, s3_7_c11_c9_6
+ 3d14: d51fb9ef msr s3_7_c11_c9_7, x15
+ 3d18: d53fb9ef mrs x15, s3_7_c11_c9_7
+ 3d1c: d51fba0f msr s3_7_c11_c10_0, x15
+ 3d20: d53fba0f mrs x15, s3_7_c11_c10_0
+ 3d24: d51fba2f msr s3_7_c11_c10_1, x15
+ 3d28: d53fba2f mrs x15, s3_7_c11_c10_1
+ 3d2c: d51fba4f msr s3_7_c11_c10_2, x15
+ 3d30: d53fba4f mrs x15, s3_7_c11_c10_2
+ 3d34: d51fba6f msr s3_7_c11_c10_3, x15
+ 3d38: d53fba6f mrs x15, s3_7_c11_c10_3
+ 3d3c: d51fba8f msr s3_7_c11_c10_4, x15
+ 3d40: d53fba8f mrs x15, s3_7_c11_c10_4
+ 3d44: d51fbaaf msr s3_7_c11_c10_5, x15
+ 3d48: d53fbaaf mrs x15, s3_7_c11_c10_5
+ 3d4c: d51fbacf msr s3_7_c11_c10_6, x15
+ 3d50: d53fbacf mrs x15, s3_7_c11_c10_6
+ 3d54: d51fbaef msr s3_7_c11_c10_7, x15
+ 3d58: d53fbaef mrs x15, s3_7_c11_c10_7
+ 3d5c: d51fbb0f msr s3_7_c11_c11_0, x15
+ 3d60: d53fbb0f mrs x15, s3_7_c11_c11_0
+ 3d64: d51fbb2f msr s3_7_c11_c11_1, x15
+ 3d68: d53fbb2f mrs x15, s3_7_c11_c11_1
+ 3d6c: d51fbb4f msr s3_7_c11_c11_2, x15
+ 3d70: d53fbb4f mrs x15, s3_7_c11_c11_2
+ 3d74: d51fbb6f msr s3_7_c11_c11_3, x15
+ 3d78: d53fbb6f mrs x15, s3_7_c11_c11_3
+ 3d7c: d51fbb8f msr s3_7_c11_c11_4, x15
+ 3d80: d53fbb8f mrs x15, s3_7_c11_c11_4
+ 3d84: d51fbbaf msr s3_7_c11_c11_5, x15
+ 3d88: d53fbbaf mrs x15, s3_7_c11_c11_5
+ 3d8c: d51fbbcf msr s3_7_c11_c11_6, x15
+ 3d90: d53fbbcf mrs x15, s3_7_c11_c11_6
+ 3d94: d51fbbef msr s3_7_c11_c11_7, x15
+ 3d98: d53fbbef mrs x15, s3_7_c11_c11_7
+ 3d9c: d51fbc0f msr s3_7_c11_c12_0, x15
+ 3da0: d53fbc0f mrs x15, s3_7_c11_c12_0
+ 3da4: d51fbc2f msr s3_7_c11_c12_1, x15
+ 3da8: d53fbc2f mrs x15, s3_7_c11_c12_1
+ 3dac: d51fbc4f msr s3_7_c11_c12_2, x15
+ 3db0: d53fbc4f mrs x15, s3_7_c11_c12_2
+ 3db4: d51fbc6f msr s3_7_c11_c12_3, x15
+ 3db8: d53fbc6f mrs x15, s3_7_c11_c12_3
+ 3dbc: d51fbc8f msr s3_7_c11_c12_4, x15
+ 3dc0: d53fbc8f mrs x15, s3_7_c11_c12_4
+ 3dc4: d51fbcaf msr s3_7_c11_c12_5, x15
+ 3dc8: d53fbcaf mrs x15, s3_7_c11_c12_5
+ 3dcc: d51fbccf msr s3_7_c11_c12_6, x15
+ 3dd0: d53fbccf mrs x15, s3_7_c11_c12_6
+ 3dd4: d51fbcef msr s3_7_c11_c12_7, x15
+ 3dd8: d53fbcef mrs x15, s3_7_c11_c12_7
+ 3ddc: d51fbd0f msr s3_7_c11_c13_0, x15
+ 3de0: d53fbd0f mrs x15, s3_7_c11_c13_0
+ 3de4: d51fbd2f msr s3_7_c11_c13_1, x15
+ 3de8: d53fbd2f mrs x15, s3_7_c11_c13_1
+ 3dec: d51fbd4f msr s3_7_c11_c13_2, x15
+ 3df0: d53fbd4f mrs x15, s3_7_c11_c13_2
+ 3df4: d51fbd6f msr s3_7_c11_c13_3, x15
+ 3df8: d53fbd6f mrs x15, s3_7_c11_c13_3
+ 3dfc: d51fbd8f msr s3_7_c11_c13_4, x15
+ 3e00: d53fbd8f mrs x15, s3_7_c11_c13_4
+ 3e04: d51fbdaf msr s3_7_c11_c13_5, x15
+ 3e08: d53fbdaf mrs x15, s3_7_c11_c13_5
+ 3e0c: d51fbdcf msr s3_7_c11_c13_6, x15
+ 3e10: d53fbdcf mrs x15, s3_7_c11_c13_6
+ 3e14: d51fbdef msr s3_7_c11_c13_7, x15
+ 3e18: d53fbdef mrs x15, s3_7_c11_c13_7
+ 3e1c: d51fbe0f msr s3_7_c11_c14_0, x15
+ 3e20: d53fbe0f mrs x15, s3_7_c11_c14_0
+ 3e24: d51fbe2f msr s3_7_c11_c14_1, x15
+ 3e28: d53fbe2f mrs x15, s3_7_c11_c14_1
+ 3e2c: d51fbe4f msr s3_7_c11_c14_2, x15
+ 3e30: d53fbe4f mrs x15, s3_7_c11_c14_2
+ 3e34: d51fbe6f msr s3_7_c11_c14_3, x15
+ 3e38: d53fbe6f mrs x15, s3_7_c11_c14_3
+ 3e3c: d51fbe8f msr s3_7_c11_c14_4, x15
+ 3e40: d53fbe8f mrs x15, s3_7_c11_c14_4
+ 3e44: d51fbeaf msr s3_7_c11_c14_5, x15
+ 3e48: d53fbeaf mrs x15, s3_7_c11_c14_5
+ 3e4c: d51fbecf msr s3_7_c11_c14_6, x15
+ 3e50: d53fbecf mrs x15, s3_7_c11_c14_6
+ 3e54: d51fbeef msr s3_7_c11_c14_7, x15
+ 3e58: d53fbeef mrs x15, s3_7_c11_c14_7
+ 3e5c: d51fbf0f msr s3_7_c11_c15_0, x15
+ 3e60: d53fbf0f mrs x15, s3_7_c11_c15_0
+ 3e64: d51fbf2f msr s3_7_c11_c15_1, x15
+ 3e68: d53fbf2f mrs x15, s3_7_c11_c15_1
+ 3e6c: d51fbf4f msr s3_7_c11_c15_2, x15
+ 3e70: d53fbf4f mrs x15, s3_7_c11_c15_2
+ 3e74: d51fbf6f msr s3_7_c11_c15_3, x15
+ 3e78: d53fbf6f mrs x15, s3_7_c11_c15_3
+ 3e7c: d51fbf8f msr s3_7_c11_c15_4, x15
+ 3e80: d53fbf8f mrs x15, s3_7_c11_c15_4
+ 3e84: d51fbfaf msr s3_7_c11_c15_5, x15
+ 3e88: d53fbfaf mrs x15, s3_7_c11_c15_5
+ 3e8c: d51fbfcf msr s3_7_c11_c15_6, x15
+ 3e90: d53fbfcf mrs x15, s3_7_c11_c15_6
+ 3e94: d51fbfef msr s3_7_c11_c15_7, x15
+ 3e98: d53fbfef mrs x15, s3_7_c11_c15_7
+ 3e9c: d51ff00f msr s3_7_c15_c0_0, x15
+ 3ea0: d53ff00f mrs x15, s3_7_c15_c0_0
+ 3ea4: d51ff02f msr s3_7_c15_c0_1, x15
+ 3ea8: d53ff02f mrs x15, s3_7_c15_c0_1
+ 3eac: d51ff04f msr s3_7_c15_c0_2, x15
+ 3eb0: d53ff04f mrs x15, s3_7_c15_c0_2
+ 3eb4: d51ff06f msr s3_7_c15_c0_3, x15
+ 3eb8: d53ff06f mrs x15, s3_7_c15_c0_3
+ 3ebc: d51ff08f msr s3_7_c15_c0_4, x15
+ 3ec0: d53ff08f mrs x15, s3_7_c15_c0_4
+ 3ec4: d51ff0af msr s3_7_c15_c0_5, x15
+ 3ec8: d53ff0af mrs x15, s3_7_c15_c0_5
+ 3ecc: d51ff0cf msr s3_7_c15_c0_6, x15
+ 3ed0: d53ff0cf mrs x15, s3_7_c15_c0_6
+ 3ed4: d51ff0ef msr s3_7_c15_c0_7, x15
+ 3ed8: d53ff0ef mrs x15, s3_7_c15_c0_7
+ 3edc: d51ff10f msr s3_7_c15_c1_0, x15
+ 3ee0: d53ff10f mrs x15, s3_7_c15_c1_0
+ 3ee4: d51ff12f msr s3_7_c15_c1_1, x15
+ 3ee8: d53ff12f mrs x15, s3_7_c15_c1_1
+ 3eec: d51ff14f msr s3_7_c15_c1_2, x15
+ 3ef0: d53ff14f mrs x15, s3_7_c15_c1_2
+ 3ef4: d51ff16f msr s3_7_c15_c1_3, x15
+ 3ef8: d53ff16f mrs x15, s3_7_c15_c1_3
+ 3efc: d51ff18f msr s3_7_c15_c1_4, x15
+ 3f00: d53ff18f mrs x15, s3_7_c15_c1_4
+ 3f04: d51ff1af msr s3_7_c15_c1_5, x15
+ 3f08: d53ff1af mrs x15, s3_7_c15_c1_5
+ 3f0c: d51ff1cf msr s3_7_c15_c1_6, x15
+ 3f10: d53ff1cf mrs x15, s3_7_c15_c1_6
+ 3f14: d51ff1ef msr s3_7_c15_c1_7, x15
+ 3f18: d53ff1ef mrs x15, s3_7_c15_c1_7
+ 3f1c: d51ff20f msr s3_7_c15_c2_0, x15
+ 3f20: d53ff20f mrs x15, s3_7_c15_c2_0
+ 3f24: d51ff22f msr s3_7_c15_c2_1, x15
+ 3f28: d53ff22f mrs x15, s3_7_c15_c2_1
+ 3f2c: d51ff24f msr s3_7_c15_c2_2, x15
+ 3f30: d53ff24f mrs x15, s3_7_c15_c2_2
+ 3f34: d51ff26f msr s3_7_c15_c2_3, x15
+ 3f38: d53ff26f mrs x15, s3_7_c15_c2_3
+ 3f3c: d51ff28f msr s3_7_c15_c2_4, x15
+ 3f40: d53ff28f mrs x15, s3_7_c15_c2_4
+ 3f44: d51ff2af msr s3_7_c15_c2_5, x15
+ 3f48: d53ff2af mrs x15, s3_7_c15_c2_5
+ 3f4c: d51ff2cf msr s3_7_c15_c2_6, x15
+ 3f50: d53ff2cf mrs x15, s3_7_c15_c2_6
+ 3f54: d51ff2ef msr s3_7_c15_c2_7, x15
+ 3f58: d53ff2ef mrs x15, s3_7_c15_c2_7
+ 3f5c: d51ff30f msr s3_7_c15_c3_0, x15
+ 3f60: d53ff30f mrs x15, s3_7_c15_c3_0
+ 3f64: d51ff32f msr s3_7_c15_c3_1, x15
+ 3f68: d53ff32f mrs x15, s3_7_c15_c3_1
+ 3f6c: d51ff34f msr s3_7_c15_c3_2, x15
+ 3f70: d53ff34f mrs x15, s3_7_c15_c3_2
+ 3f74: d51ff36f msr s3_7_c15_c3_3, x15
+ 3f78: d53ff36f mrs x15, s3_7_c15_c3_3
+ 3f7c: d51ff38f msr s3_7_c15_c3_4, x15
+ 3f80: d53ff38f mrs x15, s3_7_c15_c3_4
+ 3f84: d51ff3af msr s3_7_c15_c3_5, x15
+ 3f88: d53ff3af mrs x15, s3_7_c15_c3_5
+ 3f8c: d51ff3cf msr s3_7_c15_c3_6, x15
+ 3f90: d53ff3cf mrs x15, s3_7_c15_c3_6
+ 3f94: d51ff3ef msr s3_7_c15_c3_7, x15
+ 3f98: d53ff3ef mrs x15, s3_7_c15_c3_7
+ 3f9c: d51ff40f msr s3_7_c15_c4_0, x15
+ 3fa0: d53ff40f mrs x15, s3_7_c15_c4_0
+ 3fa4: d51ff42f msr s3_7_c15_c4_1, x15
+ 3fa8: d53ff42f mrs x15, s3_7_c15_c4_1
+ 3fac: d51ff44f msr s3_7_c15_c4_2, x15
+ 3fb0: d53ff44f mrs x15, s3_7_c15_c4_2
+ 3fb4: d51ff46f msr s3_7_c15_c4_3, x15
+ 3fb8: d53ff46f mrs x15, s3_7_c15_c4_3
+ 3fbc: d51ff48f msr s3_7_c15_c4_4, x15
+ 3fc0: d53ff48f mrs x15, s3_7_c15_c4_4
+ 3fc4: d51ff4af msr s3_7_c15_c4_5, x15
+ 3fc8: d53ff4af mrs x15, s3_7_c15_c4_5
+ 3fcc: d51ff4cf msr s3_7_c15_c4_6, x15
+ 3fd0: d53ff4cf mrs x15, s3_7_c15_c4_6
+ 3fd4: d51ff4ef msr s3_7_c15_c4_7, x15
+ 3fd8: d53ff4ef mrs x15, s3_7_c15_c4_7
+ 3fdc: d51ff50f msr s3_7_c15_c5_0, x15
+ 3fe0: d53ff50f mrs x15, s3_7_c15_c5_0
+ 3fe4: d51ff52f msr s3_7_c15_c5_1, x15
+ 3fe8: d53ff52f mrs x15, s3_7_c15_c5_1
+ 3fec: d51ff54f msr s3_7_c15_c5_2, x15
+ 3ff0: d53ff54f mrs x15, s3_7_c15_c5_2
+ 3ff4: d51ff56f msr s3_7_c15_c5_3, x15
+ 3ff8: d53ff56f mrs x15, s3_7_c15_c5_3
+ 3ffc: d51ff58f msr s3_7_c15_c5_4, x15
+ 4000: d53ff58f mrs x15, s3_7_c15_c5_4
+ 4004: d51ff5af msr s3_7_c15_c5_5, x15
+ 4008: d53ff5af mrs x15, s3_7_c15_c5_5
+ 400c: d51ff5cf msr s3_7_c15_c5_6, x15
+ 4010: d53ff5cf mrs x15, s3_7_c15_c5_6
+ 4014: d51ff5ef msr s3_7_c15_c5_7, x15
+ 4018: d53ff5ef mrs x15, s3_7_c15_c5_7
+ 401c: d51ff60f msr s3_7_c15_c6_0, x15
+ 4020: d53ff60f mrs x15, s3_7_c15_c6_0
+ 4024: d51ff62f msr s3_7_c15_c6_1, x15
+ 4028: d53ff62f mrs x15, s3_7_c15_c6_1
+ 402c: d51ff64f msr s3_7_c15_c6_2, x15
+ 4030: d53ff64f mrs x15, s3_7_c15_c6_2
+ 4034: d51ff66f msr s3_7_c15_c6_3, x15
+ 4038: d53ff66f mrs x15, s3_7_c15_c6_3
+ 403c: d51ff68f msr s3_7_c15_c6_4, x15
+ 4040: d53ff68f mrs x15, s3_7_c15_c6_4
+ 4044: d51ff6af msr s3_7_c15_c6_5, x15
+ 4048: d53ff6af mrs x15, s3_7_c15_c6_5
+ 404c: d51ff6cf msr s3_7_c15_c6_6, x15
+ 4050: d53ff6cf mrs x15, s3_7_c15_c6_6
+ 4054: d51ff6ef msr s3_7_c15_c6_7, x15
+ 4058: d53ff6ef mrs x15, s3_7_c15_c6_7
+ 405c: d51ff70f msr s3_7_c15_c7_0, x15
+ 4060: d53ff70f mrs x15, s3_7_c15_c7_0
+ 4064: d51ff72f msr s3_7_c15_c7_1, x15
+ 4068: d53ff72f mrs x15, s3_7_c15_c7_1
+ 406c: d51ff74f msr s3_7_c15_c7_2, x15
+ 4070: d53ff74f mrs x15, s3_7_c15_c7_2
+ 4074: d51ff76f msr s3_7_c15_c7_3, x15
+ 4078: d53ff76f mrs x15, s3_7_c15_c7_3
+ 407c: d51ff78f msr s3_7_c15_c7_4, x15
+ 4080: d53ff78f mrs x15, s3_7_c15_c7_4
+ 4084: d51ff7af msr s3_7_c15_c7_5, x15
+ 4088: d53ff7af mrs x15, s3_7_c15_c7_5
+ 408c: d51ff7cf msr s3_7_c15_c7_6, x15
+ 4090: d53ff7cf mrs x15, s3_7_c15_c7_6
+ 4094: d51ff7ef msr s3_7_c15_c7_7, x15
+ 4098: d53ff7ef mrs x15, s3_7_c15_c7_7
+ 409c: d51ff80f msr s3_7_c15_c8_0, x15
+ 40a0: d53ff80f mrs x15, s3_7_c15_c8_0
+ 40a4: d51ff82f msr s3_7_c15_c8_1, x15
+ 40a8: d53ff82f mrs x15, s3_7_c15_c8_1
+ 40ac: d51ff84f msr s3_7_c15_c8_2, x15
+ 40b0: d53ff84f mrs x15, s3_7_c15_c8_2
+ 40b4: d51ff86f msr s3_7_c15_c8_3, x15
+ 40b8: d53ff86f mrs x15, s3_7_c15_c8_3
+ 40bc: d51ff88f msr s3_7_c15_c8_4, x15
+ 40c0: d53ff88f mrs x15, s3_7_c15_c8_4
+ 40c4: d51ff8af msr s3_7_c15_c8_5, x15
+ 40c8: d53ff8af mrs x15, s3_7_c15_c8_5
+ 40cc: d51ff8cf msr s3_7_c15_c8_6, x15
+ 40d0: d53ff8cf mrs x15, s3_7_c15_c8_6
+ 40d4: d51ff8ef msr s3_7_c15_c8_7, x15
+ 40d8: d53ff8ef mrs x15, s3_7_c15_c8_7
+ 40dc: d51ff90f msr s3_7_c15_c9_0, x15
+ 40e0: d53ff90f mrs x15, s3_7_c15_c9_0
+ 40e4: d51ff92f msr s3_7_c15_c9_1, x15
+ 40e8: d53ff92f mrs x15, s3_7_c15_c9_1
+ 40ec: d51ff94f msr s3_7_c15_c9_2, x15
+ 40f0: d53ff94f mrs x15, s3_7_c15_c9_2
+ 40f4: d51ff96f msr s3_7_c15_c9_3, x15
+ 40f8: d53ff96f mrs x15, s3_7_c15_c9_3
+ 40fc: d51ff98f msr s3_7_c15_c9_4, x15
+ 4100: d53ff98f mrs x15, s3_7_c15_c9_4
+ 4104: d51ff9af msr s3_7_c15_c9_5, x15
+ 4108: d53ff9af mrs x15, s3_7_c15_c9_5
+ 410c: d51ff9cf msr s3_7_c15_c9_6, x15
+ 4110: d53ff9cf mrs x15, s3_7_c15_c9_6
+ 4114: d51ff9ef msr s3_7_c15_c9_7, x15
+ 4118: d53ff9ef mrs x15, s3_7_c15_c9_7
+ 411c: d51ffa0f msr s3_7_c15_c10_0, x15
+ 4120: d53ffa0f mrs x15, s3_7_c15_c10_0
+ 4124: d51ffa2f msr s3_7_c15_c10_1, x15
+ 4128: d53ffa2f mrs x15, s3_7_c15_c10_1
+ 412c: d51ffa4f msr s3_7_c15_c10_2, x15
+ 4130: d53ffa4f mrs x15, s3_7_c15_c10_2
+ 4134: d51ffa6f msr s3_7_c15_c10_3, x15
+ 4138: d53ffa6f mrs x15, s3_7_c15_c10_3
+ 413c: d51ffa8f msr s3_7_c15_c10_4, x15
+ 4140: d53ffa8f mrs x15, s3_7_c15_c10_4
+ 4144: d51ffaaf msr s3_7_c15_c10_5, x15
+ 4148: d53ffaaf mrs x15, s3_7_c15_c10_5
+ 414c: d51ffacf msr s3_7_c15_c10_6, x15
+ 4150: d53ffacf mrs x15, s3_7_c15_c10_6
+ 4154: d51ffaef msr s3_7_c15_c10_7, x15
+ 4158: d53ffaef mrs x15, s3_7_c15_c10_7
+ 415c: d51ffb0f msr s3_7_c15_c11_0, x15
+ 4160: d53ffb0f mrs x15, s3_7_c15_c11_0
+ 4164: d51ffb2f msr s3_7_c15_c11_1, x15
+ 4168: d53ffb2f mrs x15, s3_7_c15_c11_1
+ 416c: d51ffb4f msr s3_7_c15_c11_2, x15
+ 4170: d53ffb4f mrs x15, s3_7_c15_c11_2
+ 4174: d51ffb6f msr s3_7_c15_c11_3, x15
+ 4178: d53ffb6f mrs x15, s3_7_c15_c11_3
+ 417c: d51ffb8f msr s3_7_c15_c11_4, x15
+ 4180: d53ffb8f mrs x15, s3_7_c15_c11_4
+ 4184: d51ffbaf msr s3_7_c15_c11_5, x15
+ 4188: d53ffbaf mrs x15, s3_7_c15_c11_5
+ 418c: d51ffbcf msr s3_7_c15_c11_6, x15
+ 4190: d53ffbcf mrs x15, s3_7_c15_c11_6
+ 4194: d51ffbef msr s3_7_c15_c11_7, x15
+ 4198: d53ffbef mrs x15, s3_7_c15_c11_7
+ 419c: d51ffc0f msr s3_7_c15_c12_0, x15
+ 41a0: d53ffc0f mrs x15, s3_7_c15_c12_0
+ 41a4: d51ffc2f msr s3_7_c15_c12_1, x15
+ 41a8: d53ffc2f mrs x15, s3_7_c15_c12_1
+ 41ac: d51ffc4f msr s3_7_c15_c12_2, x15
+ 41b0: d53ffc4f mrs x15, s3_7_c15_c12_2
+ 41b4: d51ffc6f msr s3_7_c15_c12_3, x15
+ 41b8: d53ffc6f mrs x15, s3_7_c15_c12_3
+ 41bc: d51ffc8f msr s3_7_c15_c12_4, x15
+ 41c0: d53ffc8f mrs x15, s3_7_c15_c12_4
+ 41c4: d51ffcaf msr s3_7_c15_c12_5, x15
+ 41c8: d53ffcaf mrs x15, s3_7_c15_c12_5
+ 41cc: d51ffccf msr s3_7_c15_c12_6, x15
+ 41d0: d53ffccf mrs x15, s3_7_c15_c12_6
+ 41d4: d51ffcef msr s3_7_c15_c12_7, x15
+ 41d8: d53ffcef mrs x15, s3_7_c15_c12_7
+ 41dc: d51ffd0f msr s3_7_c15_c13_0, x15
+ 41e0: d53ffd0f mrs x15, s3_7_c15_c13_0
+ 41e4: d51ffd2f msr s3_7_c15_c13_1, x15
+ 41e8: d53ffd2f mrs x15, s3_7_c15_c13_1
+ 41ec: d51ffd4f msr s3_7_c15_c13_2, x15
+ 41f0: d53ffd4f mrs x15, s3_7_c15_c13_2
+ 41f4: d51ffd6f msr s3_7_c15_c13_3, x15
+ 41f8: d53ffd6f mrs x15, s3_7_c15_c13_3
+ 41fc: d51ffd8f msr s3_7_c15_c13_4, x15
+ 4200: d53ffd8f mrs x15, s3_7_c15_c13_4
+ 4204: d51ffdaf msr s3_7_c15_c13_5, x15
+ 4208: d53ffdaf mrs x15, s3_7_c15_c13_5
+ 420c: d51ffdcf msr s3_7_c15_c13_6, x15
+ 4210: d53ffdcf mrs x15, s3_7_c15_c13_6
+ 4214: d51ffdef msr s3_7_c15_c13_7, x15
+ 4218: d53ffdef mrs x15, s3_7_c15_c13_7
+ 421c: d51ffe0f msr s3_7_c15_c14_0, x15
+ 4220: d53ffe0f mrs x15, s3_7_c15_c14_0
+ 4224: d51ffe2f msr s3_7_c15_c14_1, x15
+ 4228: d53ffe2f mrs x15, s3_7_c15_c14_1
+ 422c: d51ffe4f msr s3_7_c15_c14_2, x15
+ 4230: d53ffe4f mrs x15, s3_7_c15_c14_2
+ 4234: d51ffe6f msr s3_7_c15_c14_3, x15
+ 4238: d53ffe6f mrs x15, s3_7_c15_c14_3
+ 423c: d51ffe8f msr s3_7_c15_c14_4, x15
+ 4240: d53ffe8f mrs x15, s3_7_c15_c14_4
+ 4244: d51ffeaf msr s3_7_c15_c14_5, x15
+ 4248: d53ffeaf mrs x15, s3_7_c15_c14_5
+ 424c: d51ffecf msr s3_7_c15_c14_6, x15
+ 4250: d53ffecf mrs x15, s3_7_c15_c14_6
+ 4254: d51ffeef msr s3_7_c15_c14_7, x15
+ 4258: d53ffeef mrs x15, s3_7_c15_c14_7
+ 425c: d51fff0f msr s3_7_c15_c15_0, x15
+ 4260: d53fff0f mrs x15, s3_7_c15_c15_0
+ 4264: d51fff2f msr s3_7_c15_c15_1, x15
+ 4268: d53fff2f mrs x15, s3_7_c15_c15_1
+ 426c: d51fff4f msr s3_7_c15_c15_2, x15
+ 4270: d53fff4f mrs x15, s3_7_c15_c15_2
+ 4274: d51fff6f msr s3_7_c15_c15_3, x15
+ 4278: d53fff6f mrs x15, s3_7_c15_c15_3
+ 427c: d51fff8f msr s3_7_c15_c15_4, x15
+ 4280: d53fff8f mrs x15, s3_7_c15_c15_4
+ 4284: d51fffaf msr s3_7_c15_c15_5, x15
+ 4288: d53fffaf mrs x15, s3_7_c15_c15_5
+ 428c: d51fffcf msr s3_7_c15_c15_6, x15
+ 4290: d53fffcf mrs x15, s3_7_c15_c15_6
+ 4294: d51fffef msr s3_7_c15_c15_7, x15
+ 4298: d53fffef mrs x15, s3_7_c15_c15_7
+ 429c: d513040f msr dbgdtr_el0, x15
+ 42a0: d533040f mrs x15, dbgdtr_el0
+ 42a4: d533050f mrs x15, dbgdtrrx_el0
--- /dev/null
+/* sysreg-1.s Test file for AArch64 system registers.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro rw_sys_reg sys_reg xreg r w
+ .ifc \w, 1
+ msr \sys_reg, \xreg
+ .endif
+ .ifc \r, 1
+ mrs \xreg, \sys_reg
+ .endif
+ .endm
+
+ .text
+
+ rw_sys_reg sys_reg=id_aa64afr0_el1 xreg=x7 r=1 w=0
+ rw_sys_reg sys_reg=id_aa64afr1_el1 xreg=x7 r=1 w=0
+ rw_sys_reg sys_reg=mvfr2_el1 xreg=x7 r=1 w=0
+ rw_sys_reg sys_reg=dlr_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=dspsr_el0 xreg=x7 r=1 w=1
+
+ rw_sys_reg sys_reg=sder32_el3 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=mdcr_el3 xreg=x7 r=1 w=1
+
+ rw_sys_reg sys_reg=mdccint_el1 xreg=x7 r=1 w=1
+
+ rw_sys_reg sys_reg=dbgvcr32_el2 xreg=x7 r=1 w=1
+
+ rw_sys_reg sys_reg=fpexc32_el2 xreg=x7 r=1 w=1
+
+ rw_sys_reg sys_reg=teecr32_el1 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=teehbr32_el1 xreg=x7 r=1 w=1
+
+ rw_sys_reg sys_reg=cntp_tval_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=cntp_ctl_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=cntp_cval_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=cntps_tval_el1 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=cntps_ctl_el1 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=cntps_cval_el1 xreg=x7 r=1 w=1
+
+ rw_sys_reg sys_reg=pmccntr_el0 xreg=x7 r=1 w=1
+
+ rw_sys_reg sys_reg=pmevcntr0_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr1_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr2_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr3_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr4_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr5_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr6_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr7_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr8_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr9_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr10_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr11_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr12_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr13_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr14_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr15_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr16_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr17_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr18_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr19_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr20_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr21_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr22_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr23_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr24_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr25_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr26_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr27_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr28_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr29_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevcntr30_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper0_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper1_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper2_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper3_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper4_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper5_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper6_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper7_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper8_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper9_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper10_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper11_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper12_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper13_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper14_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper15_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper16_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper17_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper18_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper19_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper20_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper21_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper22_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper23_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper24_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper25_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper26_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper27_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper28_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper29_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmevtyper30_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=pmccfiltr_el0 xreg=x7 r=1 w=1
+
+ rw_sys_reg sys_reg=tpidrro_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=tpidr_el0 xreg=x7 r=1 w=1
+ rw_sys_reg sys_reg=cntfrq_el0 xreg=x7 r=1 w=1
+
+ //
+ // Macros to generate MRS and MSR with all the implementation defined
+ // system registers in the form of S3_<op1>_<Cn>_<Cm>_<op2>.
+
+ .altmacro
+ .macro all_op2 op1, crn, crm, from=0, to=7
+ rw_sys_reg S3_\op1\()_C\crn\()_C\crm\()_\from x15 1 1
+ .if (\to-\from > 0)
+ all_op2 \op1, \crn, \crm, %(\from+1), \to
+ .endif
+ .endm
+
+ .macro all_crm op1, crn, from=0, to=15
+ all_op2 \op1, \crn, \from, 0, 7
+ .if (\to-\from > 0)
+ all_crm \op1, \crn, %(\from+1), \to
+ .endif
+ .endm
+
+ .macro all_imple_defined from=0, to=7
+ .irp crn, 11, 15
+ all_crm \from, \crn, 0, 15
+ .endr
+ .if \to-\from
+ all_imple_defined %(\from+1), \to
+ .endif
+ .endm
+
+ all_imple_defined 0, 7
+ .noaltmacro
+
+ rw_sys_reg sys_reg=dbgdtr_el0 xreg=x15 r=1 w=1
+ rw_sys_reg sys_reg=dbgdtrrx_el0 xreg=x15 r=1 w=0
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: d51b9c67 msr pmovsclr_el0, x7
+ 4: d53b9c60 mrs x0, pmovsclr_el0
+ 8: d51b9e67 msr pmovsset_el0, x7
+ c: d53b9e60 mrs x0, pmovsset_el0
+ 10: d5380140 mrs x0, id_dfr0_el1
+ 14: d5380100 mrs x0, id_pfr0_el1
+ 18: d5380120 mrs x0, id_pfr1_el1
+ 1c: d5380160 mrs x0, id_afr0_el1
+ 20: d5380180 mrs x0, id_mmfr0_el1
+ 24: d53801a0 mrs x0, id_mmfr1_el1
+ 28: d53801c0 mrs x0, id_mmfr2_el1
+ 2c: d53801e0 mrs x0, id_mmfr3_el1
+ 30: d5380200 mrs x0, id_isar0_el1
+ 34: d5380220 mrs x0, id_isar1_el1
+ 38: d5380240 mrs x0, id_isar2_el1
+ 3c: d5380260 mrs x0, id_isar3_el1
+ 40: d5380280 mrs x0, id_isar4_el1
+ 44: d53802a0 mrs x0, id_isar5_el1
--- /dev/null
+
+ # Test case for system registers
+ .text
+
+ msr pmovsclr_el0, x7
+ mrs x0, pmovsclr_el0
+
+ msr pmovsset_el0, x7
+ mrs x0, pmovsset_el0
+
+ mrs x0, id_dfr0_el1
+ mrs x0, id_pfr0_el1
+ mrs x0, id_pfr1_el1
+ mrs x0, id_afr0_el1
+ mrs x0, id_mmfr0_el1
+ mrs x0, id_mmfr1_el1
+ mrs x0, id_mmfr2_el1
+ mrs x0, id_mmfr3_el1
+ mrs x0, id_isar0_el1
+ mrs x0, id_isar1_el1
+ mrs x0, id_isar2_el1
+ mrs x0, id_isar3_el1
+ mrs x0, id_isar4_el1
+ mrs x0, id_isar5_el1
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: d6bf03e0 drps
+ 4: d503201f nop
+ 8: d503203f yield
+ c: d503205f wfe
+ 10: d503207f wfi
+ 14: d503209f sev
+ 18: d50320bf sevl
+ 1c: d503201f nop
+ 20: d503203f yield
+ 24: d503205f wfe
+ 28: d503207f wfi
+ 2c: d503209f sev
+ 30: d50320bf sevl
+ 34: d50320df hint #0x6
+ 38: d50320ff hint #0x7
+ 3c: d503211f hint #0x8
+ 40: d503213f hint #0x9
+ 44: d503215f hint #0xa
+ 48: d503217f hint #0xb
+ 4c: d503219f hint #0xc
+ 50: d50321bf hint #0xd
+ 54: d50321df hint #0xe
+ 58: d50321ff hint #0xf
+ 5c: d503221f hint #0x10
+ 60: d503223f hint #0x11
+ 64: d503225f hint #0x12
+ 68: d503227f hint #0x13
+ 6c: d503229f hint #0x14
+ 70: d50322bf hint #0x15
+ 74: d50322df hint #0x16
+ 78: d50322ff hint #0x17
+ 7c: d503231f hint #0x18
+ 80: d503233f hint #0x19
+ 84: d503235f hint #0x1a
+ 88: d503237f hint #0x1b
+ 8c: d503239f hint #0x1c
+ 90: d50323bf hint #0x1d
+ 94: d50323df hint #0x1e
+ 98: d50323ff hint #0x1f
+ 9c: d503241f hint #0x20
+ a0: d503243f hint #0x21
+ a4: d503245f hint #0x22
+ a8: d503247f hint #0x23
+ ac: d503249f hint #0x24
+ b0: d50324bf hint #0x25
+ b4: d50324df hint #0x26
+ b8: d50324ff hint #0x27
+ bc: d503251f hint #0x28
+ c0: d503253f hint #0x29
+ c4: d503255f hint #0x2a
+ c8: d503257f hint #0x2b
+ cc: d503259f hint #0x2c
+ d0: d50325bf hint #0x2d
+ d4: d50325df hint #0x2e
+ d8: d50325ff hint #0x2f
+ dc: d503261f hint #0x30
+ e0: d503263f hint #0x31
+ e4: d503265f hint #0x32
+ e8: d503267f hint #0x33
+ ec: d503269f hint #0x34
+ f0: d50326bf hint #0x35
+ f4: d50326df hint #0x36
+ f8: d50326ff hint #0x37
+ fc: d503271f hint #0x38
+ 100: d503273f hint #0x39
+ 104: d503275f hint #0x3a
+ 108: d503277f hint #0x3b
+ 10c: d503279f hint #0x3c
+ 110: d50327bf hint #0x3d
+ 114: d50327df hint #0x3e
+ 118: d50327ff hint #0x3f
+ 11c: d503281f hint #0x40
+ 120: d503283f hint #0x41
+ 124: d503285f hint #0x42
+ 128: d503287f hint #0x43
+ 12c: d503289f hint #0x44
+ 130: d50328bf hint #0x45
+ 134: d50328df hint #0x46
+ 138: d50328ff hint #0x47
+ 13c: d503291f hint #0x48
+ 140: d503293f hint #0x49
+ 144: d503295f hint #0x4a
+ 148: d503297f hint #0x4b
+ 14c: d503299f hint #0x4c
+ 150: d50329bf hint #0x4d
+ 154: d50329df hint #0x4e
+ 158: d50329ff hint #0x4f
+ 15c: d5032a1f hint #0x50
+ 160: d5032a3f hint #0x51
+ 164: d5032a5f hint #0x52
+ 168: d5032a7f hint #0x53
+ 16c: d5032a9f hint #0x54
+ 170: d5032abf hint #0x55
+ 174: d5032adf hint #0x56
+ 178: d5032aff hint #0x57
+ 17c: d5032b1f hint #0x58
+ 180: d5032b3f hint #0x59
+ 184: d5032b5f hint #0x5a
+ 188: d5032b7f hint #0x5b
+ 18c: d5032b9f hint #0x5c
+ 190: d5032bbf hint #0x5d
+ 194: d5032bdf hint #0x5e
+ 198: d5032bff hint #0x5f
+ 19c: d5032c1f hint #0x60
+ 1a0: d5032c3f hint #0x61
+ 1a4: d5032c5f hint #0x62
+ 1a8: d5032c7f hint #0x63
+ 1ac: d5032c9f hint #0x64
+ 1b0: d5032cbf hint #0x65
+ 1b4: d5032cdf hint #0x66
+ 1b8: d5032cff hint #0x67
+ 1bc: d5032d1f hint #0x68
+ 1c0: d5032d3f hint #0x69
+ 1c4: d5032d5f hint #0x6a
+ 1c8: d5032d7f hint #0x6b
+ 1cc: d5032d9f hint #0x6c
+ 1d0: d5032dbf hint #0x6d
+ 1d4: d5032ddf hint #0x6e
+ 1d8: d5032dff hint #0x6f
+ 1dc: d5032e1f hint #0x70
+ 1e0: d5032e3f hint #0x71
+ 1e4: d5032e5f hint #0x72
+ 1e8: d5032e7f hint #0x73
+ 1ec: d5032e9f hint #0x74
+ 1f0: d5032ebf hint #0x75
+ 1f4: d5032edf hint #0x76
+ 1f8: d5032eff hint #0x77
+ 1fc: d5032f1f hint #0x78
+ 200: d5032f3f hint #0x79
+ 204: d5032f5f hint #0x7a
+ 208: d5032f7f hint #0x7b
+ 20c: d5032f9f hint #0x7c
+ 210: d5032fbf hint #0x7d
+ 214: d5032fdf hint #0x7e
+ 218: d5032fff hint #0x7f
+ 21c: d52bf7e7 sysl x7, #3, C15, C7, #7
+ 220: d503309f dsb #0x00
+ 224: d503319f dsb oshld
+ 228: d503329f dsb oshst
+ 22c: d503339f dsb osh
+ 230: d503349f dsb #0x04
+ 234: d503359f dsb nshld
+ 238: d503369f dsb nshst
+ 23c: d503379f dsb nsh
+ 240: d503389f dsb #0x08
+ 244: d503399f dsb ishld
+ 248: d5033a9f dsb ishst
+ 24c: d5033b9f dsb ish
+ 250: d5033c9f dsb #0x0c
+ 254: d5033d9f dsb ld
+ 258: d5033e9f dsb st
+ 25c: d5033f9f dsb sy
+ 260: d50330bf dmb #0x00
+ 264: d50331bf dmb oshld
+ 268: d50332bf dmb oshst
+ 26c: d50333bf dmb osh
+ 270: d50334bf dmb #0x04
+ 274: d50335bf dmb nshld
+ 278: d50336bf dmb nshst
+ 27c: d50337bf dmb nsh
+ 280: d50338bf dmb #0x08
+ 284: d50339bf dmb ishld
+ 288: d5033abf dmb ishst
+ 28c: d5033bbf dmb ish
+ 290: d5033cbf dmb #0x0c
+ 294: d5033dbf dmb ld
+ 298: d5033ebf dmb st
+ 29c: d5033fbf dmb sy
+ 2a0: d50330df isb #0x0
+ 2a4: d50331df isb #0x1
+ 2a8: d50332df isb #0x2
+ 2ac: d50333df isb #0x3
+ 2b0: d50334df isb #0x4
+ 2b4: d50335df isb #0x5
+ 2b8: d50336df isb #0x6
+ 2bc: d50337df isb #0x7
+ 2c0: d50338df isb #0x8
+ 2c4: d50339df isb #0x9
+ 2c8: d5033adf isb #0xa
+ 2cc: d5033bdf isb #0xb
+ 2d0: d5033cdf isb #0xc
+ 2d4: d5033ddf isb #0xd
+ 2d8: d5033edf isb #0xe
+ 2dc: d5033fdf isb
+ 2e0: d5033fdf isb
+ 2e4: d8000000 prfm pldl1keep, 0 <LABEL1>
+ 2e4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 2e8: f8af6be0 prfm pldl1keep, \[sp,x15\]
+ 2ec: f8be58e0 prfm pldl1keep, \[x7,w30,uxtw #3\]
+ 2f0: f9800c60 prfm pldl1keep, \[x3,#24\]
+ 2f4: d8000001 prfm pldl1strm, 0 <LABEL1>
+ 2f4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 2f8: f8af6be1 prfm pldl1strm, \[sp,x15\]
+ 2fc: f8be58e1 prfm pldl1strm, \[x7,w30,uxtw #3\]
+ 300: f9800c61 prfm pldl1strm, \[x3,#24\]
+ 304: d8000002 prfm pldl2keep, 0 <LABEL1>
+ 304: R_AARCH64_LD_PREL_LO19 LABEL1
+ 308: f8af6be2 prfm pldl2keep, \[sp,x15\]
+ 30c: f8be58e2 prfm pldl2keep, \[x7,w30,uxtw #3\]
+ 310: f9800c62 prfm pldl2keep, \[x3,#24\]
+ 314: d8000003 prfm pldl2strm, 0 <LABEL1>
+ 314: R_AARCH64_LD_PREL_LO19 LABEL1
+ 318: f8af6be3 prfm pldl2strm, \[sp,x15\]
+ 31c: f8be58e3 prfm pldl2strm, \[x7,w30,uxtw #3\]
+ 320: f9800c63 prfm pldl2strm, \[x3,#24\]
+ 324: d8000004 prfm pldl3keep, 0 <LABEL1>
+ 324: R_AARCH64_LD_PREL_LO19 LABEL1
+ 328: f8af6be4 prfm pldl3keep, \[sp,x15\]
+ 32c: f8be58e4 prfm pldl3keep, \[x7,w30,uxtw #3\]
+ 330: f9800c64 prfm pldl3keep, \[x3,#24\]
+ 334: d8000005 prfm pldl3strm, 0 <LABEL1>
+ 334: R_AARCH64_LD_PREL_LO19 LABEL1
+ 338: f8af6be5 prfm pldl3strm, \[sp,x15\]
+ 33c: f8be58e5 prfm pldl3strm, \[x7,w30,uxtw #3\]
+ 340: f9800c65 prfm pldl3strm, \[x3,#24\]
+ 344: d8000006 prfm #0x06, 0 <LABEL1>
+ 344: R_AARCH64_LD_PREL_LO19 LABEL1
+ 348: f8af6be6 prfm #0x06, \[sp,x15\]
+ 34c: f8be58e6 prfm #0x06, \[x7,w30,uxtw #3\]
+ 350: f9800c66 prfm #0x06, \[x3,#24\]
+ 354: d8000007 prfm #0x07, 0 <LABEL1>
+ 354: R_AARCH64_LD_PREL_LO19 LABEL1
+ 358: f8af6be7 prfm #0x07, \[sp,x15\]
+ 35c: f8be58e7 prfm #0x07, \[x7,w30,uxtw #3\]
+ 360: f9800c67 prfm #0x07, \[x3,#24\]
+ 364: d8000008 prfm #0x08, 0 <LABEL1>
+ 364: R_AARCH64_LD_PREL_LO19 LABEL1
+ 368: f8af6be8 prfm #0x08, \[sp,x15\]
+ 36c: f8be58e8 prfm #0x08, \[x7,w30,uxtw #3\]
+ 370: f9800c68 prfm #0x08, \[x3,#24\]
+ 374: d8000009 prfm #0x09, 0 <LABEL1>
+ 374: R_AARCH64_LD_PREL_LO19 LABEL1
+ 378: f8af6be9 prfm #0x09, \[sp,x15\]
+ 37c: f8be58e9 prfm #0x09, \[x7,w30,uxtw #3\]
+ 380: f9800c69 prfm #0x09, \[x3,#24\]
+ 384: d800000a prfm #0x0a, 0 <LABEL1>
+ 384: R_AARCH64_LD_PREL_LO19 LABEL1
+ 388: f8af6bea prfm #0x0a, \[sp,x15\]
+ 38c: f8be58ea prfm #0x0a, \[x7,w30,uxtw #3\]
+ 390: f9800c6a prfm #0x0a, \[x3,#24\]
+ 394: d800000b prfm #0x0b, 0 <LABEL1>
+ 394: R_AARCH64_LD_PREL_LO19 LABEL1
+ 398: f8af6beb prfm #0x0b, \[sp,x15\]
+ 39c: f8be58eb prfm #0x0b, \[x7,w30,uxtw #3\]
+ 3a0: f9800c6b prfm #0x0b, \[x3,#24\]
+ 3a4: d800000c prfm #0x0c, 0 <LABEL1>
+ 3a4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3a8: f8af6bec prfm #0x0c, \[sp,x15\]
+ 3ac: f8be58ec prfm #0x0c, \[x7,w30,uxtw #3\]
+ 3b0: f9800c6c prfm #0x0c, \[x3,#24\]
+ 3b4: d800000d prfm #0x0d, 0 <LABEL1>
+ 3b4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3b8: f8af6bed prfm #0x0d, \[sp,x15\]
+ 3bc: f8be58ed prfm #0x0d, \[x7,w30,uxtw #3\]
+ 3c0: f9800c6d prfm #0x0d, \[x3,#24\]
+ 3c4: d800000e prfm #0x0e, 0 <LABEL1>
+ 3c4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3c8: f8af6bee prfm #0x0e, \[sp,x15\]
+ 3cc: f8be58ee prfm #0x0e, \[x7,w30,uxtw #3\]
+ 3d0: f9800c6e prfm #0x0e, \[x3,#24\]
+ 3d4: d800000f prfm #0x0f, 0 <LABEL1>
+ 3d4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3d8: f8af6bef prfm #0x0f, \[sp,x15\]
+ 3dc: f8be58ef prfm #0x0f, \[x7,w30,uxtw #3\]
+ 3e0: f9800c6f prfm #0x0f, \[x3,#24\]
+ 3e4: d8000010 prfm pstl1keep, 0 <LABEL1>
+ 3e4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3e8: f8af6bf0 prfm pstl1keep, \[sp,x15\]
+ 3ec: f8be58f0 prfm pstl1keep, \[x7,w30,uxtw #3\]
+ 3f0: f9800c70 prfm pstl1keep, \[x3,#24\]
+ 3f4: d8000011 prfm pstl1strm, 0 <LABEL1>
+ 3f4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3f8: f8af6bf1 prfm pstl1strm, \[sp,x15\]
+ 3fc: f8be58f1 prfm pstl1strm, \[x7,w30,uxtw #3\]
+ 400: f9800c71 prfm pstl1strm, \[x3,#24\]
+ 404: d8000012 prfm pstl2keep, 0 <LABEL1>
+ 404: R_AARCH64_LD_PREL_LO19 LABEL1
+ 408: f8af6bf2 prfm pstl2keep, \[sp,x15\]
+ 40c: f8be58f2 prfm pstl2keep, \[x7,w30,uxtw #3\]
+ 410: f9800c72 prfm pstl2keep, \[x3,#24\]
+ 414: d8000013 prfm pstl2strm, 0 <LABEL1>
+ 414: R_AARCH64_LD_PREL_LO19 LABEL1
+ 418: f8af6bf3 prfm pstl2strm, \[sp,x15\]
+ 41c: f8be58f3 prfm pstl2strm, \[x7,w30,uxtw #3\]
+ 420: f9800c73 prfm pstl2strm, \[x3,#24\]
+ 424: d8000014 prfm pstl3keep, 0 <LABEL1>
+ 424: R_AARCH64_LD_PREL_LO19 LABEL1
+ 428: f8af6bf4 prfm pstl3keep, \[sp,x15\]
+ 42c: f8be58f4 prfm pstl3keep, \[x7,w30,uxtw #3\]
+ 430: f9800c74 prfm pstl3keep, \[x3,#24\]
+ 434: d8000015 prfm pstl3strm, 0 <LABEL1>
+ 434: R_AARCH64_LD_PREL_LO19 LABEL1
+ 438: f8af6bf5 prfm pstl3strm, \[sp,x15\]
+ 43c: f8be58f5 prfm pstl3strm, \[x7,w30,uxtw #3\]
+ 440: f9800c75 prfm pstl3strm, \[x3,#24\]
+ 444: d8000016 prfm #0x16, 0 <LABEL1>
+ 444: R_AARCH64_LD_PREL_LO19 LABEL1
+ 448: f8af6bf6 prfm #0x16, \[sp,x15\]
+ 44c: f8be58f6 prfm #0x16, \[x7,w30,uxtw #3\]
+ 450: f9800c76 prfm #0x16, \[x3,#24\]
+ 454: d8000017 prfm #0x17, 0 <LABEL1>
+ 454: R_AARCH64_LD_PREL_LO19 LABEL1
+ 458: f8af6bf7 prfm #0x17, \[sp,x15\]
+ 45c: f8be58f7 prfm #0x17, \[x7,w30,uxtw #3\]
+ 460: f9800c77 prfm #0x17, \[x3,#24\]
+ 464: d8000018 prfm #0x18, 0 <LABEL1>
+ 464: R_AARCH64_LD_PREL_LO19 LABEL1
+ 468: f8af6bf8 prfm #0x18, \[sp,x15\]
+ 46c: f8be58f8 prfm #0x18, \[x7,w30,uxtw #3\]
+ 470: f9800c78 prfm #0x18, \[x3,#24\]
+ 474: d8000019 prfm #0x19, 0 <LABEL1>
+ 474: R_AARCH64_LD_PREL_LO19 LABEL1
+ 478: f8af6bf9 prfm #0x19, \[sp,x15\]
+ 47c: f8be58f9 prfm #0x19, \[x7,w30,uxtw #3\]
+ 480: f9800c79 prfm #0x19, \[x3,#24\]
+ 484: d800001a prfm #0x1a, 0 <LABEL1>
+ 484: R_AARCH64_LD_PREL_LO19 LABEL1
+ 488: f8af6bfa prfm #0x1a, \[sp,x15\]
+ 48c: f8be58fa prfm #0x1a, \[x7,w30,uxtw #3\]
+ 490: f9800c7a prfm #0x1a, \[x3,#24\]
+ 494: d800001b prfm #0x1b, 0 <LABEL1>
+ 494: R_AARCH64_LD_PREL_LO19 LABEL1
+ 498: f8af6bfb prfm #0x1b, \[sp,x15\]
+ 49c: f8be58fb prfm #0x1b, \[x7,w30,uxtw #3\]
+ 4a0: f9800c7b prfm #0x1b, \[x3,#24\]
+ 4a4: d800001c prfm #0x1c, 0 <LABEL1>
+ 4a4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 4a8: f8af6bfc prfm #0x1c, \[sp,x15\]
+ 4ac: f8be58fc prfm #0x1c, \[x7,w30,uxtw #3\]
+ 4b0: f9800c7c prfm #0x1c, \[x3,#24\]
+ 4b4: d800001d prfm #0x1d, 0 <LABEL1>
+ 4b4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 4b8: f8af6bfd prfm #0x1d, \[sp,x15\]
+ 4bc: f8be58fd prfm #0x1d, \[x7,w30,uxtw #3\]
+ 4c0: f9800c7d prfm #0x1d, \[x3,#24\]
+ 4c4: d800001e prfm #0x1e, 0 <LABEL1>
+ 4c4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 4c8: f8af6bfe prfm #0x1e, \[sp,x15\]
+ 4cc: f8be58fe prfm #0x1e, \[x7,w30,uxtw #3\]
+ 4d0: f9800c7e prfm #0x1e, \[x3,#24\]
+ 4d4: d800001f prfm #0x1f, 0 <LABEL1>
+ 4d4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 4d8: f8af6bff prfm #0x1f, \[sp,x15\]
+ 4dc: f8be58ff prfm #0x1f, \[x7,w30,uxtw #3\]
+ 4e0: f9800c7f prfm #0x1f, \[x3,#24\]
--- /dev/null
+ .text
+ drps
+
+ //
+ // HINTS
+ //
+
+ nop
+ yield
+ wfe
+ wfi
+ sev
+ sevl
+
+ .macro all_hints from=0, to=127
+ hint \from
+ .if \to-\from
+ all_hints "(\from+1)", \to
+ .endif
+ .endm
+
+ all_hints from=0, to=63
+ all_hints from=64, to=127
+
+ //
+ // SYSL
+ //
+
+ sysl x7, #3, C15, C7, #7
+
+ //
+ // BARRIERS
+ //
+
+ .macro all_barriers op, from=0, to=15
+ \op \from
+ .if \to-\from
+ all_barriers \op, "(\from+1)", \to
+ .endif
+ .endm
+
+ all_barriers op=dsb, from=0, to=15
+ all_barriers op=dmb, from=0, to=15
+ all_barriers op=isb, from=0, to=15
+
+ isb
+
+ //
+ // PREFETCHS
+ //
+
+ .macro all_prefetchs op, from=0, to=31
+ \op \from, LABEL1
+ \op \from, [sp, x15, lsl #0]
+ \op \from, [x7, w30, uxtw #3]
+ \op \from, [x3, #24]
+ .if \to-\from
+ all_prefetchs \op, "(\from+1)", \to
+ .endif
+ .endm
+
+ all_prefetchs op=prfm, from=0, to=31
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: d50c8027 tlbi ipas2e1is, x7
+ 4: d50c80a7 tlbi ipas2le1is, x7
+ 8: d508831f tlbi vmalle1is
+ c: d50c831f tlbi alle2is
+ 10: d50e831f tlbi alle3is
+ 14: d5088327 tlbi vae1is, x7
+ 18: d50c8327 tlbi vae2is, x7
+ 1c: d50e8327 tlbi vae3is, x7
+ 20: d5088347 tlbi aside1is, x7
+ 24: d5088367 tlbi vaae1is, x7
+ 28: d50c839f tlbi alle1is
+ 2c: d50883a7 tlbi vale1is, x7
+ 30: d50c83a7 tlbi vale2is, x7
+ 34: d50e83a7 tlbi vale3is, x7
+ 38: d50c83df tlbi vmalls12e1is
+ 3c: d50883e7 tlbi vaale1is, x7
+ 40: d50c8427 tlbi ipas2e1, x7
+ 44: d50c84a7 tlbi ipas2le1, x7
+ 48: d508871f tlbi vmalle1
+ 4c: d50c871f tlbi alle2
+ 50: d50e871f tlbi alle3
+ 54: d5088727 tlbi vae1, x7
+ 58: d50c8727 tlbi vae2, x7
+ 5c: d50e8727 tlbi vae3, x7
+ 60: d5088747 tlbi aside1, x7
+ 64: d5088767 tlbi vaae1, x7
+ 68: d50c879f tlbi alle1
+ 6c: d50887a7 tlbi vale1, x7
+ 70: d50c87a7 tlbi vale2, x7
+ 74: d50e87a7 tlbi vale3, x7
+ 78: d50c87df tlbi vmalls12e1
+ 7c: d50887e7 tlbi vaale1, x7
--- /dev/null
+// Test file for AArch64 GAS -- TLB invalidation instructions.
+
+ .macro tlbi_m op has_xt
+ .ifc \has_xt, 1
+ tlbi \op, x7
+ .else
+ tlbi \op
+ .endif
+ .endm
+
+ # Test case for tlbi operations
+ .text
+
+ tlbi_m IPAS2E1IS, 1
+ tlbi_m IPAS2LE1IS, 1
+ tlbi_m VMALLE1IS , 0
+ tlbi_m ALLE2IS, 0
+ tlbi_m ALLE3IS, 0
+ tlbi_m VAE1IS, 1
+ tlbi_m VAE2IS, 1
+ tlbi_m VAE3IS, 1
+ tlbi_m ASIDE1IS, 1
+ tlbi_m VAAE1IS, 1
+ tlbi_m ALLE1IS, 0
+ tlbi_m VALE1IS, 1
+ tlbi_m VALE2IS, 1
+ tlbi_m VALE3IS, 1
+ tlbi_m VMALLS12E1IS, 0
+ tlbi_m VAALE1IS, 1
+ tlbi_m IPAS2E1, 1
+ tlbi_m IPAS2LE1, 1
+ tlbi_m VMALLE1 , 0
+ tlbi_m ALLE2 , 0
+ tlbi_m ALLE3, 0
+ tlbi_m VAE1, 1
+ tlbi_m VAE2, 1
+ tlbi_m VAE3, 1
+ tlbi_m ASIDE1, 1
+ tlbi_m VAAE1, 1
+ tlbi_m ALLE1, 0
+ tlbi_m VALE1, 1
+ tlbi_m VALE2, 1
+ tlbi_m VALE3, 1
+ tlbi_m VMALLS12E1, 0
+ tlbi_m VAALE1, 1
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 90000000 adrp x0, 0 <var>
+ 0: R_AARCH64_TLSDESC_ADR_PAGE var
+ 4: f9400001 ldr x1, \[x0\]
+ 4: R_AARCH64_TLSDESC_LD64_LO12_NC var
+ 8: 91000000 add x0, x0, #0x0
+ 8: R_AARCH64_TLSDESC_ADD_LO12_NC var
+ c: d63f0020 blr x1
+ c: R_AARCH64_TLSDESC_CALL var
+ 10: 90000000 adrp x0, 0 <var>
+ 10: R_AARCH64_TLSGD_ADR_PAGE21 var
+ 14: 91000000 add x0, x0, #0x0
+ 14: R_AARCH64_TLSGD_ADD_LO12_NC var
+ 18: 94000000 bl 0 <__tls_get_addr>
+ 18: R_AARCH64_CALL26 __tls_get_addr
+ 1c: 90000000 adrp x0, 0 <var>
+ 1c: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 var
+ 20: f9400000 ldr x0, \[x0\]
+ 20: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC var
+ 24: 91000020 add x0, x1, #0x0
+ 24: R_AARCH64_TLSLE_ADD_TPREL_LO12 var
+ 28: 91400020 add x0, x1, #0x0, lsl #12
+ 28: R_AARCH64_TLSLE_ADD_TPREL_HI12 var
+ 2c: 91400020 add x0, x1, #0x0, lsl #12
+ 2c: R_AARCH64_TLSLE_ADD_TPREL_HI12 var
+ 30: 91000020 add x0, x1, #0x0
+ 30: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC var
--- /dev/null
+/* tls.s Test file for AArch64 TLS relocations.
+
+ Copyright 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+func:
+
+ // R_AARCH64_TLSDESC_ADR_PAGE var
+ adrp x0, :tlsdesc:var
+ // R_AARCH64_TLSDESC_LD64_LO12 var
+ ldr x1, [x0, #:tlsdesc_lo12:var]
+ // R_AARCH64_TLSDESC_ADD_LO12 var
+ add x0, x0, #:tlsdesc_lo12:var
+ // R_AARCH64_TLSDESC_CALL var
+ .tlsdesccall var
+ blr x1
+
+ // R_AARCH64_TLSGD_ADR_PAGE21 var
+ adrp x0, :tlsgd:var
+ // R_AARCH64_TLSGD_ADD_LO12_NC var
+ add x0, x0, #:tlsgd_lo12:var
+ // R_AARCH64_CALL26
+ bl __tls_get_addr
+
+ // R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 var
+ adrp x0, :gottprel:var
+ // R_AARCH64_TLSUE_GOTTPREL_LO12_NC var
+ ldr x0, [x0, #:gottprel_lo12:var]
+
+ // R_AARCH64_TLSLE_ADD_TPREL_LO12 var
+ add x0, x1, #:tprel_lo12:var
+ // R_AARCH64_TLSLE_ADD_TPREL_HI12 var
+ add x0, x1, #:tprel_hi12:var
+ // R_AARCH64_TLSLE_ADD_TPREL_HI12 var
+ add x0, x1, #:tprel_hi12:var, lsl #12
+ // R_AARCH64_TLSLE_ADD_TPREL_LO12_NC var
+ add x0, x1, #:tprel_lo12_nc:var
--- /dev/null
+#name: Verbose Error Messages
+#as: -mverbose-error
+#source: verbose-error.s
+#error-output: verbose-error.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:4: Error: missing shift amount at operand 2 -- `strb w7,\[x30,x0,lsl\]'
+[^:]*:5: Error: operand mismatch -- `ubfm w0,x1,8,31'
+[^:]*:5: Info: did you mean this\?
+[^:]*:5: Info: ubfm w0,w1,#8,#31
+[^:]*:5: Info: other valid variant\(s\):
+[^:]*:5: Info: ubfm x0,x1,#8,#31
+[^:]*:6: Error: immediate value out of range 0 to 31 at operand 4 -- `bfm w0,w1,8,43'
+[^:]*:7: Error: invalid shift amount at operand 2 -- `strb w7,\[x30,x0,lsl#1\]'
+[^:]*:8: Error: invalid addressing mode at operand 2 -- `st2 {v4.2d,v5.2d},\[x3,#3\]'
+[^:]*:9: Error: the top half of a 128-bit FP/SIMD register is expected at operand 1 -- `fmov v1.D\[0\],x0'
+[^:]*:10: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ld1r \{v1.4s,v2.4s,v3.4s\},\[x3\],x4'
+[^:]*:11: Error: missing immediate expression at operand 1 -- `svc'
+[^:]*:12: Error: operand mismatch -- `add v0.4s,v1.4s,v2.2s'
+[^:]*:12: Info: did you mean this\?
+[^:]*:12: Info: add v0.4s,v1.4s,v2.4s
+[^:]*:12: Info: other valid variant\(s\):
+[^:]*:12: Info: add v0.8b,v1.8b,v2.8b
+[^:]*:12: Info: add v0.16b,v1.16b,v2.16b
+[^:]*:12: Info: add v0.4h,v1.4h,v2.4h
+[^:]*:12: Info: add v0.8h,v1.8h,v2.8h
+[^:]*:12: Info: add v0.2s,v1.2s,v2.2s
+[^:]*:12: Info: add v0.2d,v1.2d,v2.2d
+[^:]*:13: Error: operand mismatch -- `urecpe v0.1d,v7.1d'
+[^:]*:13: Info: did you mean this\?
+[^:]*:13: Info: urecpe v0.2s,v7.2s
+[^:]*:13: Info: other valid variant\(s\):
+[^:]*:13: Info: urecpe v0.4s,v7.4s
+[^:]*:14: Error: operand mismatch -- `adds w0,wsp,x0,uxtx#1'
+[^:]*:14: Info: did you mean this\?
+[^:]*:14: Info: adds w0,wsp,w0, uxtx #1
+[^:]*:14: Info: other valid variant\(s\):
+[^:]*:14: Info: adds x0,sp,w0, uxtx #1
+[^:]*:14: Info: adds x0,sp,x0, lsl #1
+[^:]*:15: Error: operand mismatch -- `fmov d0,s0'
+[^:]*:15: Info: did you mean this\?
+[^:]*:15: Info: fmov s0,s0
+[^:]*:15: Info: other valid variant\(s\):
+[^:]*:15: Info: fmov d0,d0
+[^:]*:16: Error: operand mismatch -- `ldnp h3,h7,\[sp\],#16'
+[^:]*:16: Info: did you mean this\?
+[^:]*:16: Info: ldnp s3,s7,\[sp\],#16
+[^:]*:16: Info: other valid variant\(s\):
+[^:]*:16: Info: ldnp d3,d7,\[sp\],#16
+[^:]*:16: Info: ldnp q3,q7,\[sp\],#16
--- /dev/null
+// verbose-error.s Test file for -mverbose-error
+
+.text
+ strb w7, [x30, x0, lsl]
+ ubfm w0, x1, 8, 31
+ bfm w0, w1, 8, 43
+ strb w7, [x30, x0, lsl #1]
+ st2 {v4.2d,v5.2d},[x3,#3]
+ fmov v1.D[0],x0
+ ld1r {v1.4s, v2.4s, v3.4s}, [x3], x4
+ svc
+ add v0.4s, v1.4s, v2.2s
+ urecpe v0.1d,v7.1d
+ adds w0, wsp, x0, uxtx #1
+ fmov d0, s0
+ ldnp h3, h7, [sp], #16
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * dis-asm.h (print_insn_aarch64): New declaration.
+ (print_aarch64_disassembler_options): New declaration.
+ (aarch64_symbol_is_valid): New declaration.
+
2012-08-02 Sean Keys <skeys@ipdatasys.com>
* elf/m68hc11.h: #define E_M68HC11_NO_BANK_WARNING
target address. Return number of octets processed. */
typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
+extern int print_insn_aarch64 (bfd_vma, disassemble_info *);
extern int print_insn_alpha (bfd_vma, disassemble_info *);
extern int print_insn_avr (bfd_vma, disassemble_info *);
extern int print_insn_bfin (bfd_vma, disassemble_info *);
extern disassembler_ftype arc_get_disassembler (void *);
extern disassembler_ftype cris_get_disassembler (bfd *);
+extern void print_aarch64_disassembler_options (FILE *);
extern void print_i386_disassembler_options (FILE *);
extern void print_mips_disassembler_options (FILE *);
extern void print_ppc_disassembler_options (FILE *);
extern int get_arm_regname_num_options (void);
extern int set_arm_regname_option (int);
extern int get_arm_regnames (int, const char **, const char **, const char *const **);
+extern bfd_boolean aarch64_symbol_is_valid (asymbol *, struct disassemble_info *);
extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *);
extern void disassemble_init_powerpc (struct disassemble_info *);
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h: New file.
+ * common.h (EM_res183): Rename to EM_AARCH64.
+ (EM_res184): Rename to EM_ARM184.
+
2012-06-28 Iain Sandoe <iain@codesourcery.com>
* common.h (AT_L1I_CACHESHAPE, AT_L1D_CACHESHAPE,
--- /dev/null
+/* AArch64 ELF support for BFD.
+
+ Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GNU Binutils.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#ifndef _ELF_AARCH64_H
+#define _ELF_AARCH64_H
+
+#include "elf/reloc-macros.h"
+
+/* Processor specific program header types. */
+#define PT_AARCH64_ARCHEXT (PT_LOPROC + 0)
+
+/* Additional section types. */
+#define SHT_AARCH64_ATTRIBUTES 0x70000003 /* Section holds attributes. */
+
+/* AArch64-specific values for sh_flags. */
+#define SHF_ENTRYSECT 0x10000000 /* Section contains an
+ entry point. */
+#define SHF_COMDEF 0x80000000 /* Section may be multiply defined
+ in the input to a link step. */
+
+/* Relocation types. */
+
+START_RELOC_NUMBERS (elf_aarch64_reloc_type)
+
+/* Null relocations. */
+RELOC_NUMBER (R_AARCH64_NONE, 0) /* No reloc */
+
+FAKE_RELOC (R_AARCH64_static_min, 256)
+
+RELOC_NUMBER (R_AARCH64_NULL, 256) /* No reloc */
+
+/* Basic data relocations. */
+
+/* .xword: (S+A) */
+RELOC_NUMBER (R_AARCH64_ABS64, 257)
+
+/* .word: (S+A) */
+RELOC_NUMBER (R_AARCH64_ABS32, 258)
+
+/* .half: (S+A) */
+RELOC_NUMBER (R_AARCH64_ABS16, 259)
+
+/* .xword: (S+A-P) */
+RELOC_NUMBER (R_AARCH64_PREL64, 260)
+
+/* .word: (S+A-P) */
+RELOC_NUMBER (R_AARCH64_PREL32, 261)
+
+/* .half: (S+A-P) */
+RELOC_NUMBER (R_AARCH64_PREL16, 262)
+
+/* Group relocations to create a 16, 32, 48 or 64 bit
+ unsigned data or abs address inline. */
+
+/* MOV[ZK]: ((S+A) >> 0) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G0, 263)
+
+/* MOV[ZK]: ((S+A) >> 0) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G0_NC, 264)
+
+/* MOV[ZK]: ((S+A) >> 16) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G1, 265)
+
+/* MOV[ZK]: ((S+A) >> 16) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G1_NC, 266)
+
+/* MOV[ZK]: ((S+A) >> 32) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G2, 267)
+
+/* MOV[ZK]: ((S+A) >> 32) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G2_NC, 268)
+
+/* MOV[ZK]: ((S+A) >> 48) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G3, 269)
+
+/* Group relocations to create high part of a 16, 32, 48 or 64 bit
+ signed data or abs address inline. Will change instruction
+ to MOVN or MOVZ depending on sign of calculated value. */
+
+/* MOV[ZN]: ((S+A) >> 0) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_SABS_G0, 270)
+
+/* MOV[ZN]: ((S+A) >> 16) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_SABS_G1, 271)
+
+/* MOV[ZN]: ((S+A) >> 32) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_SABS_G2, 272)
+
+/* Relocations to generate 19, 21 and 33 bit PC-relative load/store
+ addresses: PG(x) is (x & ~0xfff). */
+
+/* LD-lit: ((S+A-P) >> 2) & 0x7ffff */
+RELOC_NUMBER (R_AARCH64_LD_PREL_LO19, 273)
+
+/* ADR: (S+A-P) & 0x1fffff */
+RELOC_NUMBER (R_AARCH64_ADR_PREL_LO21, 274)
+
+/* ADRH: ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */
+RELOC_NUMBER (R_AARCH64_ADR_PREL_PG_HI21, 275)
+
+/* ADRH: ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */
+RELOC_NUMBER (R_AARCH64_ADR_PREL_PG_HI21_NC, 276)
+
+/* ADD: (S+A) & 0xfff */
+RELOC_NUMBER (R_AARCH64_ADD_ABS_LO12_NC, 277)
+
+/* LD/ST8: (S+A) & 0xfff */
+RELOC_NUMBER (R_AARCH64_LDST8_ABS_LO12_NC, 278)
+
+/* Relocations for control-flow instructions. */
+
+/* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff. */
+RELOC_NUMBER (R_AARCH64_TSTBR14, 279)
+
+/* B.cond: ((S+A-P) >> 2) & 0x7ffff. */
+RELOC_NUMBER (R_AARCH64_CONDBR19, 280)
+
+/* 281 unused */
+
+/* B: ((S+A-P) >> 2) & 0x3ffffff. */
+RELOC_NUMBER (R_AARCH64_JUMP26, 282)
+
+/* BL: ((S+A-P) >> 2) & 0x3ffffff. */
+RELOC_NUMBER (R_AARCH64_CALL26, 283)
+
+/* LD/ST16: (S+A) & 0xffe */
+RELOC_NUMBER (R_AARCH64_LDST16_ABS_LO12_NC, 284)
+
+/* LD/ST32: (S+A) & 0xffc */
+RELOC_NUMBER (R_AARCH64_LDST32_ABS_LO12_NC, 285)
+
+/* LD/ST64: (S+A) & 0xff8 */
+RELOC_NUMBER (R_AARCH64_LDST64_ABS_LO12_NC, 286)
+
+/* LD/ST128: (S+A) & 0xff0 */
+RELOC_NUMBER (R_AARCH64_LDST128_ABS_LO12_NC, 299)
+
+RELOC_NUMBER (R_AARCH64_ADR_GOT_PAGE, 311)
+RELOC_NUMBER (R_AARCH64_LD64_GOT_LO12_NC, 312)
+
+FAKE_RELOC (R_AARCH64_static_max, 313)
+
+FAKE_RELOC (R_AARCH64_tls_min, 512)
+RELOC_NUMBER (R_AARCH64_TLSGD_ADR_PAGE21, 513)
+RELOC_NUMBER (R_AARCH64_TLSGD_ADD_LO12_NC, 514)
+RELOC_NUMBER (R_AARCH64_TLSIE_MOVW_GOTTPREL_G1, 539)
+RELOC_NUMBER (R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, 540)
+RELOC_NUMBER (R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, 541)
+RELOC_NUMBER (R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, 542)
+RELOC_NUMBER (R_AARCH64_TLSIE_LD_GOTTPREL_PREL19, 543)
+RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G2, 544)
+RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G1, 545)
+RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G1_NC, 546)
+RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G0, 547)
+RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G0_NC, 548)
+RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_HI12, 549)
+RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_LO12, 550)
+RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_LO12_NC, 551)
+FAKE_RELOC (R_AARCH64_tls_max, 552)
+
+FAKE_RELOC (R_AARCH64_tlsdesc_min, 560)
+RELOC_NUMBER (R_AARCH64_TLSDESC_LD64_PREL19, 560)
+RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PREL21, 561)
+RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PAGE, 562)
+RELOC_NUMBER (R_AARCH64_TLSDESC_LD64_LO12_NC, 563)
+RELOC_NUMBER (R_AARCH64_TLSDESC_ADD_LO12_NC, 564)
+RELOC_NUMBER (R_AARCH64_TLSDESC_OFF_G1, 565)
+RELOC_NUMBER (R_AARCH64_TLSDESC_OFF_G0_NC, 566)
+RELOC_NUMBER (R_AARCH64_TLSDESC_LDR, 567)
+RELOC_NUMBER (R_AARCH64_TLSDESC_ADD, 568)
+RELOC_NUMBER (R_AARCH64_TLSDESC_CALL, 569)
+FAKE_RELOC (R_AARCH64_tlsdesc_max, 570)
+
+/* Dynamic relocations */
+FAKE_RELOC (R_AARCH64_dyn_min, 1024)
+
+/* Copy symbol at runtime. */
+RELOC_NUMBER (R_AARCH64_COPY, 1024)
+
+/* Create GOT entry. */
+RELOC_NUMBER (R_AARCH64_GLOB_DAT, 1025)
+
+ /* Create PLT entry. */
+RELOC_NUMBER (R_AARCH64_JUMP_SLOT, 1026)
+
+/* Adjust by program base. */
+RELOC_NUMBER (R_AARCH64_RELATIVE, 1027)
+RELOC_NUMBER (R_AARCH64_TLS_DTPMOD64, 1028)
+RELOC_NUMBER (R_AARCH64_TLS_DTPREL64, 1029)
+RELOC_NUMBER (R_AARCH64_TLS_TPREL64, 1030)
+RELOC_NUMBER (R_AARCH64_TLSDESC, 1031)
+FAKE_RELOC (R_AARCH64_dyn_max, 1032)
+
+END_RELOC_NUMBERS (R_AARCH64_end)
+
+#endif /* _ELF_AARCH64_H */
#define EM_L1OM 180 /* Intel L1OM */
#define EM_K1OM 181 /* Intel K1OM */
#define EM_INTEL182 182 /* Reserved by Intel */
-#define EM_res183 183 /* Reserved by ARM */
-#define EM_res184 184 /* Reserved by ARM */
+#define EM_AARCH64 183 /* ARM 64-bit architecture */
+#define EM_ARM184 184 /* Reserved by ARM */
#define EM_AVR32 185 /* Atmel Corporation 32-bit microprocessor family */
#define EM_STM8 186 /* STMicroeletronics STM8 8-bit microcontroller */
#define EM_TILE64 187 /* Tilera TILE64 multicore architecture family */
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h: New file.
+
2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
Maciej W. Rozycki <macro@codesourcery.com>
--- /dev/null
+/* AArch64 assembler/disassembler support.
+
+ Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GNU Binutils.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#ifndef OPCODE_AARCH64_H
+#define OPCODE_AARCH64_H
+
+#include "bfd.h"
+#include "bfd_stdint.h"
+#include <assert.h>
+#include <stdlib.h>
+
+/* The offset for pc-relative addressing is currently defined to be 0. */
+#define AARCH64_PCREL_OFFSET 0
+
+typedef uint32_t aarch64_insn;
+
+/* The following bitmasks control CPU features. */
+#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
+#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
+#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
+#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
+
+/* Architectures are the sum of the base and extensions. */
+#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
+ AARCH64_FEATURE_FP \
+ | AARCH64_FEATURE_SIMD)
+#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
+#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
+
+/* CPU-specific features. */
+typedef unsigned long aarch64_feature_set;
+
+#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
+ (((CPU) & (FEAT)) != 0)
+
+#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
+ do \
+ { \
+ (TARG) = (F1) | (F2); \
+ } \
+ while (0)
+
+#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
+ do \
+ { \
+ (TARG) = (F1) &~ (F2); \
+ } \
+ while (0)
+
+#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
+
+#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
+ (((OPC) & (FEAT)) != 0)
+
+enum aarch64_operand_class
+{
+ AARCH64_OPND_CLASS_NIL,
+ AARCH64_OPND_CLASS_INT_REG,
+ AARCH64_OPND_CLASS_MODIFIED_REG,
+ AARCH64_OPND_CLASS_FP_REG,
+ AARCH64_OPND_CLASS_SIMD_REG,
+ AARCH64_OPND_CLASS_SIMD_ELEMENT,
+ AARCH64_OPND_CLASS_SISD_REG,
+ AARCH64_OPND_CLASS_SIMD_REGLIST,
+ AARCH64_OPND_CLASS_CP_REG,
+ AARCH64_OPND_CLASS_ADDRESS,
+ AARCH64_OPND_CLASS_IMMEDIATE,
+ AARCH64_OPND_CLASS_SYSTEM,
+};
+
+/* Operand code that helps both parsing and coding.
+ Keep AARCH64_OPERANDS synced. */
+
+enum aarch64_opnd
+{
+ AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
+
+ AARCH64_OPND_Rd, /* Integer register as destination. */
+ AARCH64_OPND_Rn, /* Integer register as source. */
+ AARCH64_OPND_Rm, /* Integer register as source. */
+ AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
+ AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
+ AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
+ AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
+ AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
+
+ AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
+ AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
+ AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
+ AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
+
+ AARCH64_OPND_Fd, /* Floating-point Fd. */
+ AARCH64_OPND_Fn, /* Floating-point Fn. */
+ AARCH64_OPND_Fm, /* Floating-point Fm. */
+ AARCH64_OPND_Fa, /* Floating-point Fa. */
+ AARCH64_OPND_Ft, /* Floating-point Ft. */
+ AARCH64_OPND_Ft2, /* Floating-point Ft2. */
+
+ AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
+ AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
+ AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
+
+ AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
+ AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
+ AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
+ AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
+ AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
+ AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
+ AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
+ AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
+ AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
+ AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
+ AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
+ structure to all lanes. */
+ AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
+
+ AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
+ AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
+
+ AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
+ AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
+ AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
+ AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
+ AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
+ AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
+ AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
+ (no encoding). */
+ AARCH64_OPND_IMM0, /* Immediate for #0. */
+ AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
+ AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
+ AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
+ AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
+ AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
+ AARCH64_OPND_IMM, /* Immediate. */
+ AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
+ AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
+ AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
+ AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
+ AARCH64_OPND_BIT_NUM, /* Immediate. */
+ AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
+ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
+ AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
+ each condition flag. */
+
+ AARCH64_OPND_LIMM, /* Logical Immediate. */
+ AARCH64_OPND_AIMM, /* Arithmetic immediate. */
+ AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
+ AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
+ AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
+
+ AARCH64_OPND_COND, /* Standard condition as the last operand. */
+
+ AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
+ AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
+ AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
+ AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
+ AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
+
+ AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
+ AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
+ AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
+ AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
+ AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
+ negative or unaligned and there is
+ no writeback allowed. This operand code
+ is only used to support the programmer-
+ friendly feature of using LDR/STR as the
+ the mnemonic name for LDUR/STUR instructions
+ wherever there is no ambiguity. */
+ AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
+ AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
+ AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
+
+ AARCH64_OPND_SYSREG, /* System register operand. */
+ AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
+ AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
+ AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
+ AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
+ AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
+ AARCH64_OPND_BARRIER, /* Barrier operand. */
+ AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
+ AARCH64_OPND_PRFOP, /* Prefetch operation. */
+};
+
+/* Qualifier constrains an operand. It either specifies a variant of an
+ operand type or limits values available to an operand type.
+
+ N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
+
+enum aarch64_opnd_qualifier
+{
+ /* Indicating no further qualification on an operand. */
+ AARCH64_OPND_QLF_NIL,
+
+ /* Qualifying an operand which is a general purpose (integer) register;
+ indicating the operand data size or a specific register. */
+ AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
+ AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
+ AARCH64_OPND_QLF_WSP, /* WSP. */
+ AARCH64_OPND_QLF_SP, /* SP. */
+
+ /* Qualifying an operand which is a floating-point register, a SIMD
+ vector element or a SIMD vector element list; indicating operand data
+ size or the size of each SIMD vector element in the case of a SIMD
+ vector element list.
+ These qualifiers are also used to qualify an address operand to
+ indicate the size of data element a load/store instruction is
+ accessing.
+ They are also used for the immediate shift operand in e.g. SSHR. Such
+ a use is only for the ease of operand encoding/decoding and qualifier
+ sequence matching; such a use should not be applied widely; use the value
+ constraint qualifiers for immediate operands wherever possible. */
+ AARCH64_OPND_QLF_S_B,
+ AARCH64_OPND_QLF_S_H,
+ AARCH64_OPND_QLF_S_S,
+ AARCH64_OPND_QLF_S_D,
+ AARCH64_OPND_QLF_S_Q,
+
+ /* Qualifying an operand which is a SIMD vector register or a SIMD vector
+ register list; indicating register shape.
+ They are also used for the immediate shift operand in e.g. SSHR. Such
+ a use is only for the ease of operand encoding/decoding and qualifier
+ sequence matching; such a use should not be applied widely; use the value
+ constraint qualifiers for immediate operands wherever possible. */
+ AARCH64_OPND_QLF_V_8B,
+ AARCH64_OPND_QLF_V_16B,
+ AARCH64_OPND_QLF_V_4H,
+ AARCH64_OPND_QLF_V_8H,
+ AARCH64_OPND_QLF_V_2S,
+ AARCH64_OPND_QLF_V_4S,
+ AARCH64_OPND_QLF_V_1D,
+ AARCH64_OPND_QLF_V_2D,
+ AARCH64_OPND_QLF_V_1Q,
+
+ /* Constraint on value. */
+ AARCH64_OPND_QLF_imm_0_7,
+ AARCH64_OPND_QLF_imm_0_15,
+ AARCH64_OPND_QLF_imm_0_31,
+ AARCH64_OPND_QLF_imm_0_63,
+ AARCH64_OPND_QLF_imm_1_32,
+ AARCH64_OPND_QLF_imm_1_64,
+
+ /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
+ or shift-ones. */
+ AARCH64_OPND_QLF_LSL,
+ AARCH64_OPND_QLF_MSL,
+
+ /* Special qualifier helping retrieve qualifier information during the
+ decoding time (currently not in use). */
+ AARCH64_OPND_QLF_RETRIEVE,
+};
+\f
+/* Instruction class. */
+
+enum aarch64_insn_class
+{
+ addsub_carry,
+ addsub_ext,
+ addsub_imm,
+ addsub_shift,
+ asimdall,
+ asimddiff,
+ asimdelem,
+ asimdext,
+ asimdimm,
+ asimdins,
+ asimdmisc,
+ asimdperm,
+ asimdsame,
+ asimdshf,
+ asimdtbl,
+ asisddiff,
+ asisdelem,
+ asisdlse,
+ asisdlsep,
+ asisdlso,
+ asisdlsop,
+ asisdmisc,
+ asisdone,
+ asisdpair,
+ asisdsame,
+ asisdshf,
+ bitfield,
+ branch_imm,
+ branch_reg,
+ compbranch,
+ condbranch,
+ condcmp_imm,
+ condcmp_reg,
+ condsel,
+ cryptoaes,
+ cryptosha2,
+ cryptosha3,
+ dp_1src,
+ dp_2src,
+ dp_3src,
+ exception,
+ extract,
+ float2fix,
+ float2int,
+ floatccmp,
+ floatcmp,
+ floatdp1,
+ floatdp2,
+ floatdp3,
+ floatimm,
+ floatsel,
+ ldst_immpost,
+ ldst_immpre,
+ ldst_imm9, /* immpost or immpre */
+ ldst_pos,
+ ldst_regoff,
+ ldst_unpriv,
+ ldst_unscaled,
+ ldstexcl,
+ ldstnapair_offs,
+ ldstpair_off,
+ ldstpair_indexed,
+ loadlit,
+ log_imm,
+ log_shift,
+ movewide,
+ pcreladdr,
+ ic_system,
+ testbranch,
+};
+
+/* Opcode enumerators. */
+
+enum aarch64_op
+{
+ OP_NIL,
+ OP_STRB_POS,
+ OP_LDRB_POS,
+ OP_LDRSB_POS,
+ OP_STRH_POS,
+ OP_LDRH_POS,
+ OP_LDRSH_POS,
+ OP_STR_POS,
+ OP_LDR_POS,
+ OP_STRF_POS,
+ OP_LDRF_POS,
+ OP_LDRSW_POS,
+ OP_PRFM_POS,
+
+ OP_STURB,
+ OP_LDURB,
+ OP_LDURSB,
+ OP_STURH,
+ OP_LDURH,
+ OP_LDURSH,
+ OP_STUR,
+ OP_LDUR,
+ OP_STURV,
+ OP_LDURV,
+ OP_LDURSW,
+ OP_PRFUM,
+
+ OP_LDR_LIT,
+ OP_LDRV_LIT,
+ OP_LDRSW_LIT,
+ OP_PRFM_LIT,
+
+ OP_ADD,
+ OP_B,
+ OP_BL,
+
+ OP_MOVN,
+ OP_MOVZ,
+ OP_MOVK,
+
+ OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
+ OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
+ OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
+
+ OP_MOV_V, /* MOV alias for moving vector register. */
+
+ OP_ASR_IMM,
+ OP_LSR_IMM,
+ OP_LSL_IMM,
+
+ OP_BIC,
+
+ OP_UBFX,
+ OP_BFXIL,
+ OP_SBFX,
+ OP_SBFIZ,
+ OP_BFI,
+ OP_UBFIZ,
+ OP_UXTB,
+ OP_UXTH,
+ OP_UXTW,
+
+ OP_V_MOVI_B,
+
+ OP_CINC,
+ OP_CINV,
+ OP_CNEG,
+ OP_CSET,
+ OP_CSETM,
+
+ OP_FCVT,
+ OP_FCVTN,
+ OP_FCVTN2,
+ OP_FCVTL,
+ OP_FCVTL2,
+ OP_FCVTXN_S, /* Scalar version. */
+
+ OP_ROR_IMM,
+
+ OP_TOTAL_NUM, /* Pseudo. */
+};
+
+/* Maximum number of operands an instruction can have. */
+#define AARCH64_MAX_OPND_NUM 6
+/* Maximum number of qualifier sequences an instruction can have. */
+#define AARCH64_MAX_QLF_SEQ_NUM 10
+/* Operand qualifier typedef; optimized for the size. */
+typedef unsigned char aarch64_opnd_qualifier_t;
+/* Operand qualifier sequence typedef. */
+typedef aarch64_opnd_qualifier_t \
+ aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
+
+/* FIXME: improve the efficiency. */
+static inline bfd_boolean
+empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
+{
+ int i;
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
+ return FALSE;
+ return TRUE;
+}
+
+/* This structure holds information for a particular opcode. */
+
+struct aarch64_opcode
+{
+ /* The name of the mnemonic. */
+ const char *name;
+
+ /* The opcode itself. Those bits which will be filled in with
+ operands are zeroes. */
+ aarch64_insn opcode;
+
+ /* The opcode mask. This is used by the disassembler. This is a
+ mask containing ones indicating those bits which must match the
+ opcode field, and zeroes indicating those bits which need not
+ match (and are presumably filled in by operands). */
+ aarch64_insn mask;
+
+ /* Instruction class. */
+ enum aarch64_insn_class iclass;
+
+ /* Enumerator identifier. */
+ enum aarch64_op op;
+
+ /* Which architecture variant provides this instruction. */
+ const aarch64_feature_set *avariant;
+
+ /* An array of operand codes. Each code is an index into the
+ operand table. They appear in the order which the operands must
+ appear in assembly code, and are terminated by a zero. */
+ enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
+
+ /* A list of operand qualifier code sequence. Each operand qualifier
+ code qualifies the corresponding operand code. Each operand
+ qualifier sequence specifies a valid opcode variant and related
+ constraint on operands. */
+ aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
+
+ /* Flags providing information about this instruction */
+ uint32_t flags;
+};
+
+typedef struct aarch64_opcode aarch64_opcode;
+
+/* Table describing all the AArch64 opcodes. */
+extern aarch64_opcode aarch64_opcode_table[];
+
+/* Opcode flags. */
+#define F_ALIAS (1 << 0)
+#define F_HAS_ALIAS (1 << 1)
+/* Disassembly preference priority 1-3 (the larger the higher). If nothing
+ is specified, it is the priority 0 by default, i.e. the lowest priority. */
+#define F_P1 (1 << 2)
+#define F_P2 (2 << 2)
+#define F_P3 (3 << 2)
+/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
+#define F_COND (1 << 4)
+/* Instruction has the field of 'sf'. */
+#define F_SF (1 << 5)
+/* Instruction has the field of 'size:Q'. */
+#define F_SIZEQ (1 << 6)
+/* Floating-point instruction has the field of 'type'. */
+#define F_FPTYPE (1 << 7)
+/* AdvSIMD scalar instruction has the field of 'size'. */
+#define F_SSIZE (1 << 8)
+/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
+#define F_T (1 << 9)
+/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
+#define F_GPRSIZE_IN_Q (1 << 10)
+/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
+#define F_LDS_SIZE (1 << 11)
+/* Optional operand; assume maximum of 1 operand can be optional. */
+#define F_OPD0_OPT (1 << 12)
+#define F_OPD1_OPT (2 << 12)
+#define F_OPD2_OPT (3 << 12)
+#define F_OPD3_OPT (4 << 12)
+#define F_OPD4_OPT (5 << 12)
+/* Default value for the optional operand when omitted from the assembly. */
+#define F_DEFAULT(X) (((X) & 0x1f) << 15)
+/* Instruction that is an alias of another instruction needs to be
+ encoded/decoded by converting it to/from the real form, followed by
+ the encoding/decoding according to the rules of the real opcode.
+ This compares to the direct coding using the alias's information.
+ N.B. this flag requires F_ALIAS to be used together. */
+#define F_CONV (1 << 20)
+/* Use together with F_ALIAS to indicate an alias opcode is a programmer
+ friendly pseudo instruction available only in the assembly code (thus will
+ not show up in the disassembly). */
+#define F_PSEUDO (1 << 21)
+/* Instruction has miscellaneous encoding/decoding rules. */
+#define F_MISC (1 << 22)
+/* Instruction has the field of 'N'; used in conjunction with F_SF. */
+#define F_N (1 << 23)
+/* Opcode dependent field. */
+#define F_OD(X) (((X) & 0x7) << 24)
+/* Next bit is 27. */
+
+static inline bfd_boolean
+alias_opcode_p (const aarch64_opcode *opcode)
+{
+ return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
+opcode_has_alias (const aarch64_opcode *opcode)
+{
+ return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
+}
+
+/* Priority for disassembling preference. */
+static inline int
+opcode_priority (const aarch64_opcode *opcode)
+{
+ return (opcode->flags >> 2) & 0x3;
+}
+
+static inline bfd_boolean
+pseudo_opcode_p (const aarch64_opcode *opcode)
+{
+ return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
+optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
+{
+ return (((opcode->flags >> 12) & 0x7) == idx + 1)
+ ? TRUE : FALSE;
+}
+
+static inline aarch64_insn
+get_optional_operand_default_value (const aarch64_opcode *opcode)
+{
+ return (opcode->flags >> 15) & 0x1f;
+}
+
+static inline unsigned int
+get_opcode_dependent_value (const aarch64_opcode *opcode)
+{
+ return (opcode->flags >> 24) & 0x7;
+}
+
+static inline bfd_boolean
+opcode_has_special_coder (const aarch64_opcode *opcode)
+{
+ return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
+ | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
+ : FALSE;
+}
+\f
+struct aarch64_name_value_pair
+{
+ const char * name;
+ aarch64_insn value;
+};
+
+extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
+extern const struct aarch64_name_value_pair aarch64_sys_regs [];
+extern const struct aarch64_name_value_pair aarch64_pstatefields [];
+extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
+extern const struct aarch64_name_value_pair aarch64_prfops [32];
+
+typedef struct
+{
+ const char *template;
+ uint32_t value;
+ int has_xt;
+} aarch64_sys_ins_reg;
+
+extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
+extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
+extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
+extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
+
+/* Shift/extending operator kinds.
+ N.B. order is important; keep aarch64_operand_modifiers synced. */
+enum aarch64_modifier_kind
+{
+ AARCH64_MOD_NONE,
+ AARCH64_MOD_MSL,
+ AARCH64_MOD_ROR,
+ AARCH64_MOD_ASR,
+ AARCH64_MOD_LSR,
+ AARCH64_MOD_LSL,
+ AARCH64_MOD_UXTB,
+ AARCH64_MOD_UXTH,
+ AARCH64_MOD_UXTW,
+ AARCH64_MOD_UXTX,
+ AARCH64_MOD_SXTB,
+ AARCH64_MOD_SXTH,
+ AARCH64_MOD_SXTW,
+ AARCH64_MOD_SXTX,
+};
+
+bfd_boolean
+aarch64_extend_operator_p (enum aarch64_modifier_kind);
+
+enum aarch64_modifier_kind
+aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
+/* Condition. */
+
+typedef struct
+{
+ /* A list of names with the first one as the disassembly preference;
+ terminated by NULL if fewer than 3. */
+ const char *names[3];
+ aarch64_insn value;
+} aarch64_cond;
+
+extern const aarch64_cond aarch64_conds[16];
+
+const aarch64_cond* get_cond_from_value (aarch64_insn value);
+const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
+\f
+/* Structure representing an operand. */
+
+struct aarch64_opnd_info
+{
+ enum aarch64_opnd type;
+ aarch64_opnd_qualifier_t qualifier;
+ int idx;
+
+ union
+ {
+ struct
+ {
+ unsigned regno;
+ } reg;
+ struct
+ {
+ unsigned regno : 5;
+ unsigned index : 4;
+ } reglane;
+ /* e.g. LVn. */
+ struct
+ {
+ unsigned first_regno : 5;
+ unsigned num_regs : 3;
+ /* 1 if it is a list of reg element. */
+ unsigned has_index : 1;
+ /* Lane index; valid only when has_index is 1. */
+ unsigned index : 4;
+ } reglist;
+ /* e.g. immediate or pc relative address offset. */
+ struct
+ {
+ int64_t value;
+ unsigned is_fp : 1;
+ } imm;
+ /* e.g. address in STR (register offset). */
+ struct
+ {
+ unsigned base_regno;
+ struct
+ {
+ union
+ {
+ int imm;
+ unsigned regno;
+ };
+ unsigned is_reg;
+ } offset;
+ unsigned pcrel : 1; /* PC-relative. */
+ unsigned writeback : 1;
+ unsigned preind : 1; /* Pre-indexed. */
+ unsigned postind : 1; /* Post-indexed. */
+ } addr;
+ const aarch64_cond *cond;
+ /* The encoding of the system register. */
+ aarch64_insn sysreg;
+ /* The encoding of the PSTATE field. */
+ aarch64_insn pstatefield;
+ const aarch64_sys_ins_reg *sysins_op;
+ const struct aarch64_name_value_pair *barrier;
+ const struct aarch64_name_value_pair *prfop;
+ };
+
+ /* Operand shifter; in use when the operand is a register offset address,
+ add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
+ struct
+ {
+ enum aarch64_modifier_kind kind;
+ int amount;
+ unsigned operator_present: 1; /* Only valid during encoding. */
+ /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
+ unsigned amount_present: 1;
+ } shifter;
+
+ unsigned skip:1; /* Operand is not completed if there is a fixup needed
+ to be done on it. In some (but not all) of these
+ cases, we need to tell libopcodes to skip the
+ constraint checking and the encoding for this
+ operand, so that the libopcodes can pick up the
+ right opcode before the operand is fixed-up. This
+ flag should only be used during the
+ assembling/encoding. */
+ unsigned present:1; /* Whether this operand is present in the assembly
+ line; not used during the disassembly. */
+};
+
+typedef struct aarch64_opnd_info aarch64_opnd_info;
+
+/* Structure representing an instruction.
+
+ It is used during both the assembling and disassembling. The assembler
+ fills an aarch64_inst after a successful parsing and then passes it to the
+ encoding routine to do the encoding. During the disassembling, the
+ disassembler calls the decoding routine to decode a binary instruction; on a
+ successful return, such a structure will be filled with information of the
+ instruction; then the disassembler uses the information to print out the
+ instruction. */
+
+struct aarch64_inst
+{
+ /* The value of the binary instruction. */
+ aarch64_insn value;
+
+ /* Corresponding opcode entry. */
+ const aarch64_opcode *opcode;
+
+ /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
+ const aarch64_cond *cond;
+
+ /* Operands information. */
+ aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
+};
+
+typedef struct aarch64_inst aarch64_inst;
+\f
+/* Diagnosis related declaration and interface. */
+
+/* Operand error kind enumerators.
+
+ AARCH64_OPDE_RECOVERABLE
+ Less severe error found during the parsing, very possibly because that
+ GAS has picked up a wrong instruction template for the parsing.
+
+ AARCH64_OPDE_SYNTAX_ERROR
+ General syntax error; it can be either a user error, or simply because
+ that GAS is trying a wrong instruction template.
+
+ AARCH64_OPDE_FATAL_SYNTAX_ERROR
+ Definitely a user syntax error.
+
+ AARCH64_OPDE_INVALID_VARIANT
+ No syntax error, but the operands are not a valid combination, e.g.
+ FMOV D0,S0
+
+ AARCH64_OPDE_OUT_OF_RANGE
+ Error about some immediate value out of a valid range.
+
+ AARCH64_OPDE_UNALIGNED
+ Error about some immediate value not properly aligned (i.e. not being a
+ multiple times of a certain value).
+
+ AARCH64_OPDE_REG_LIST
+ Error about the register list operand having unexpected number of
+ registers.
+
+ AARCH64_OPDE_OTHER_ERROR
+ Error of the highest severity and used for any severe issue that does not
+ fall into any of the above categories.
+
+ The enumerators are only interesting to GAS. They are declared here (in
+ libopcodes) because that some errors are detected (and then notified to GAS)
+ by libopcodes (rather than by GAS solely).
+
+ The first three errors are only deteced by GAS while the
+ AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
+ only libopcodes has the information about the valid variants of each
+ instruction.
+
+ The enumerators have an increasing severity. This is helpful when there are
+ multiple instruction templates available for a given mnemonic name (e.g.
+ FMOV); this mechanism will help choose the most suitable template from which
+ the generated diagnostics can most closely describe the issues, if any. */
+
+enum aarch64_operand_error_kind
+{
+ AARCH64_OPDE_NIL,
+ AARCH64_OPDE_RECOVERABLE,
+ AARCH64_OPDE_SYNTAX_ERROR,
+ AARCH64_OPDE_FATAL_SYNTAX_ERROR,
+ AARCH64_OPDE_INVALID_VARIANT,
+ AARCH64_OPDE_OUT_OF_RANGE,
+ AARCH64_OPDE_UNALIGNED,
+ AARCH64_OPDE_REG_LIST,
+ AARCH64_OPDE_OTHER_ERROR
+};
+
+/* N.B. GAS assumes that this structure work well with shallow copy. */
+struct aarch64_operand_error
+{
+ enum aarch64_operand_error_kind kind;
+ int index;
+ const char *error;
+ int data[3]; /* Some data for extra information. */
+};
+
+typedef struct aarch64_operand_error aarch64_operand_error;
+
+/* Encoding entrypoint. */
+
+extern int
+aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
+ aarch64_insn *, aarch64_opnd_qualifier_t *,
+ aarch64_operand_error *);
+
+extern const aarch64_opcode *
+aarch64_replace_opcode (struct aarch64_inst *,
+ const aarch64_opcode *);
+
+/* Given the opcode enumerator OP, return the pointer to the corresponding
+ opcode entry. */
+
+extern const aarch64_opcode *
+aarch64_get_opcode (enum aarch64_op);
+
+/* Generate the string representation of an operand. */
+extern void
+aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
+ const aarch64_opnd_info *, int, int *, bfd_vma *);
+
+/* Miscellaneous interface. */
+
+extern int
+aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
+
+extern aarch64_opnd_qualifier_t
+aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
+ const aarch64_opnd_qualifier_t, int);
+
+extern int
+aarch64_num_of_operands (const aarch64_opcode *);
+
+extern int
+aarch64_stack_pointer_p (const aarch64_opnd_info *);
+
+extern
+int aarch64_zero_register_p (const aarch64_opnd_info *);
+
+/* Given an operand qualifier, return the expected data element size
+ of a qualified operand. */
+extern unsigned char
+aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
+
+extern enum aarch64_operand_class
+aarch64_get_operand_class (enum aarch64_opnd);
+
+extern const char *
+aarch64_get_operand_name (enum aarch64_opnd);
+
+extern const char *
+aarch64_get_operand_desc (enum aarch64_opnd);
+
+#ifdef DEBUG_AARCH64
+extern int debug_dump;
+
+extern void
+aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
+
+#define DEBUG_TRACE(M, ...) \
+ { \
+ if (debug_dump) \
+ aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
+ }
+
+#define DEBUG_TRACE_IF(C, M, ...) \
+ { \
+ if (debug_dump && (C)) \
+ aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
+ }
+#else /* !DEBUG_AARCH64 */
+#define DEBUG_TRACE(M, ...) ;
+#define DEBUG_TRACE_IF(C, M, ...) ;
+#endif /* DEBUG_AARCH64 */
+
+#endif /* OPCODE_AARCH64_H */
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64.
+ * Makefile.in: Regenerate.
+ * configure.tgt: Add AArch64.
+ * emulparams/aarch64elf.sh: New file.
+ * emulparams/aarch64elfb.sh: New file.
+ * emulparams/aarch64linux.sh: New file.
+ * emulparams/aarch64linuxb.sh: New file.
+ * emultempl/aarch64elf.em: New file.
+ * NEWS: Mention the new feature.
+
2012-08-09 Nick Clifton <nickc@redhat.com>
* po/vi.po: Updated Vietnamese translation.
ALL_EMULATIONS = $(ALL_EMULATION_SOURCES:.c=.@OBJEXT@)
ALL_64_EMULATION_SOURCES = \
+ eaarch64elf.c \
+ eaarch64elfb.c \
+ eaarch64linux.c \
+ eaarch64linuxb.c \
eelf32_x86_64.c \
eelf32_x86_64_nacl.c \
eelf64_aix.c \
$(srcdir)/emultempl/generic.em $(srcdir)/emultempl/netbsd.em \
$(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} ns32knbsd "$(tdir_ns32knbsd)"
+eaarch64elf.c: $(srcdir)/emulparams/aarch64elf.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64elf "$(tdir_aarch64elf)"
+eaarch64elfb.c: $(srcdir)/emulparams/aarch64elfb.sh $(srcdir)/emulparams/aarch64elf.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64elfb "$(tdir_aarch64elfb)"
+eaarch64linux.c: $(srcdir)/emulparams/aarch64linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64linux "$(tdir_aarch64linux)"
+eaarch64linuxb.c: $(srcdir)/emulparams/aarch64linuxb.sh $(srcdir)/emulparams/aarch64linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64linuxb "$(tdir_aarch64linuxb)"
eor32.c: $(srcdir)/emulparams/or32.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/or32.sc ${GEN_DEPENDS}
${GENSCRIPTS} or32 "$(tdir_or32)"
ALL_EMULATIONS = $(ALL_EMULATION_SOURCES:.c=.@OBJEXT@)
ALL_64_EMULATION_SOURCES = \
+ eaarch64elf.c \
+ eaarch64elfb.c \
+ eaarch64linux.c \
+ eaarch64linuxb.c \
eelf32_x86_64.c \
eelf32_x86_64_nacl.c \
eelf64_aix.c \
-rm -f *.tab.c
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/deffilep.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64elf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64elfb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64linuxb.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaix5ppc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaix5rs6.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaixppc.Po@am__quote@
$(srcdir)/emultempl/generic.em $(srcdir)/emultempl/netbsd.em \
$(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} ns32knbsd "$(tdir_ns32knbsd)"
+eaarch64elf.c: $(srcdir)/emulparams/aarch64elf.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64elf "$(tdir_aarch64elf)"
+eaarch64elfb.c: $(srcdir)/emulparams/aarch64elfb.sh $(srcdir)/emulparams/aarch64elf.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64elfb "$(tdir_aarch64elfb)"
+eaarch64linux.c: $(srcdir)/emulparams/aarch64linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64linux "$(tdir_aarch64linux)"
+eaarch64linuxb.c: $(srcdir)/emulparams/aarch64linuxb.sh $(srcdir)/emulparams/aarch64linux.sh \
+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} aarch64linuxb "$(tdir_aarch64linuxb)"
eor32.c: $(srcdir)/emulparams/or32.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/or32.sc ${GEN_DEPENDS}
${GENSCRIPTS} or32 "$(tdir_or32)"
-*- text -*-
+* Add support for the 64-bit ARM architecture: AArch64.
+
Changes in 2.23:
* Added SORT_NONE to the linker script language to disable section sorting.
# architecture variants should be kept together even if their names
# break the alpha sorting.
case "${targ}" in
+aarch64_be-*-elf) targ_emul=aarch64elfb
+ targ_extra_emuls="aarch64elf armelfb armelf" ;;
+aarch64-*-elf) targ_emul=aarch64elf
+ targ_extra_emuls="aarch64elfb armelf armelfb" ;;
+aarch64_be-*-linux*) targ_emul=aarch64linuxb
+ targ_extra_emuls="aarch64linux aarch64elfb aarch64elf armelfb_linux_eabi armelf_linux_eabi armelfb armelf" ;;
+aarch64-*-linux*) targ_emul=aarch64linux
+ targ_extra_emuls="aarch64linuxb aarch64elf aarch64elfb armelf_linux_eabi armelfb_linux_eabi armelf armelfb" ;;
alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu)
targ_emul=elf64alpha_fbsd
targ_extra_emuls="elf64alpha alpha"
--- /dev/null
+ARCH=aarch64
+MACHINE=
+NOP=0
+
+SCRIPT_NAME=elf
+OUTPUT_FORMAT="elf64-littleaarch64"
+BIG_OUTPUT_FORMAT="elf64-bigaarch64"
+LITTLE_OUTPUT_FORMAT="elf64-littleaarch64"
+NO_REL_RELOCS=yes
+
+TEMPLATE_NAME=elf32
+EXTRA_EM_FILE=aarch64elf
+
+GENERATE_SHLIB_SCRIPT=yes
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+
+ENTRY=_start
+EMBEDDED=yes
+SEPARATE_GOTPLT=24
+TEXT_START_ADDR=0x00400000
+
+DATA_START_SYMBOLS='__data_start = . ;';
+
+# AArch64 does not support .s* sections.
+NO_SMALL_DATA=yes
+
+OTHER_BSS_SYMBOLS='__bss_start__ = .;'
+OTHER_BSS_END_SYMBOLS='_bss_end__ = . ; __bss_end__ = . ;'
+OTHER_END_SYMBOLS='__end__ = . ;'
+
+OTHER_SECTIONS='.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }'
+ATTRS_SECTIONS='.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }'
+
+# This sets the stack to the top of the simulator memory (2^19 bytes).
+STACK_ADDR=0x80000
--- /dev/null
+. ${srcdir}/emulparams/aarch64elf.sh
+OUTPUT_FORMAT="elf64-bigaarch64"
--- /dev/null
+ARCH=aarch64
+MACHINE=
+NOP=0
+
+SCRIPT_NAME=elf
+OUTPUT_FORMAT="elf64-littleaarch64"
+BIG_OUTPUT_FORMAT="elf64-bigaarch64"
+LITTLE_OUTPUT_FORMAT="elf64-littleaarch64"
+NO_REL_RELOCS=yes
+
+TEMPLATE_NAME=elf32
+EXTRA_EM_FILE=aarch64elf
+
+GENERATE_SHLIB_SCRIPT=yes
+GENERATE_PIE_SCRIPT=yes
+
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
+SEPARATE_GOTPLT=24
+IREL_IN_PLT=
+
+TEXT_START_ADDR=0x400000
+
+DATA_START_SYMBOLS='PROVIDE (__data_start = .);';
+
+# AArch64 does not support .s* sections.
+NO_SMALL_DATA=yes
+
+OTHER_BSS_SYMBOLS='__bss_start__ = .;'
+OTHER_BSS_END_SYMBOLS='_bss_end__ = . ; __bss_end__ = . ;'
+OTHER_END_SYMBOLS='__end__ = . ;'
+
+OTHER_SECTIONS='.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }'
+ATTRS_SECTIONS='.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }'
+# Ensure each PLT entry is aligned to a cache line.
+PLT=".plt ${RELOCATING-0} : ALIGN(16) { *(.plt)${IREL_IN_PLT+ *(.iplt)} }"
--- /dev/null
+. ${srcdir}/emulparams/aarch64linux.sh
+OUTPUT_FORMAT="elf64-bigaarch64"
--- /dev/null
+# This shell script emits a C file. -*- C -*-
+# Copyright 2009-2012 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the license, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING3. If not,
+# see <http://www.gnu.org/licenses/>.
+#
+
+# This file is sourced from elf32.em, and defines extra aarch64-elf
+# specific routines.
+#
+fragment <<EOF
+
+#include "ldctor.h"
+#include "elf/aarch64.h"
+
+static int no_enum_size_warning = 0;
+static int no_wchar_size_warning = 0;
+static int pic_veneer = 0;
+
+static void
+gld${EMULATION_NAME}_before_parse (void)
+{
+#ifndef TARGET_ /* I.e., if not generic. */
+ ldfile_set_output_arch ("`echo ${ARCH}`", bfd_arch_unknown);
+#endif /* not TARGET_ */
+ input_flags.dynamic = ${DYNAMIC_LINK-TRUE};
+ config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo TRUE ; else echo FALSE ; fi`;
+}
+
+static void
+aarch64_elf_before_allocation (void)
+{
+ /* We should be able to set the size of the interworking stub section. We
+ can't do it until later if we have dynamic sections, though. */
+ if (! elf_hash_table (&link_info)->dynamic_sections_created)
+ {
+ /* Here we rummage through the found bfds to collect information. */
+ LANG_FOR_EACH_INPUT_STATEMENT (is)
+ {
+ /* Initialise mapping tables for code/data. */
+ bfd_elf64_aarch64_init_maps (is->the_bfd);
+ }
+ }
+
+ /* Call the standard elf routine. */
+ gld${EMULATION_NAME}_before_allocation ();
+}
+
+/* Fake input file for stubs. */
+static lang_input_statement_type *stub_file;
+
+/* Whether we need to call gldarm_layout_sections_again. */
+static int need_laying_out = 0;
+
+/* Maximum size of a group of input sections that can be handled by
+ one stub section. A value of +/-1 indicates the bfd back-end
+ should use a suitable default size. */
+static bfd_signed_vma group_size = 1;
+
+struct hook_stub_info
+{
+ lang_statement_list_type add;
+ asection *input_section;
+};
+
+/* Traverse the linker tree to find the spot where the stub goes. */
+
+static bfd_boolean
+hook_in_stub (struct hook_stub_info *info, lang_statement_union_type **lp)
+{
+ lang_statement_union_type *l;
+ bfd_boolean ret;
+
+ for (; (l = *lp) != NULL; lp = &l->header.next)
+ {
+ switch (l->header.type)
+ {
+ case lang_constructors_statement_enum:
+ ret = hook_in_stub (info, &constructor_list.head);
+ if (ret)
+ return ret;
+ break;
+
+ case lang_output_section_statement_enum:
+ ret = hook_in_stub (info,
+ &l->output_section_statement.children.head);
+ if (ret)
+ return ret;
+ break;
+
+ case lang_wild_statement_enum:
+ ret = hook_in_stub (info, &l->wild_statement.children.head);
+ if (ret)
+ return ret;
+ break;
+
+ case lang_group_statement_enum:
+ ret = hook_in_stub (info, &l->group_statement.children.head);
+ if (ret)
+ return ret;
+ break;
+
+ case lang_input_section_enum:
+ if (l->input_section.section == info->input_section)
+ {
+ /* We've found our section. Insert the stub immediately
+ after its associated input section. */
+ *(info->add.tail) = l->header.next;
+ l->header.next = info->add.head;
+ return TRUE;
+ }
+ break;
+
+ case lang_data_statement_enum:
+ case lang_reloc_statement_enum:
+ case lang_object_symbols_statement_enum:
+ case lang_output_statement_enum:
+ case lang_target_statement_enum:
+ case lang_input_statement_enum:
+ case lang_assignment_statement_enum:
+ case lang_padding_statement_enum:
+ case lang_address_statement_enum:
+ case lang_fill_statement_enum:
+ break;
+
+ default:
+ FAIL ();
+ break;
+ }
+ }
+ return FALSE;
+}
+
+
+/* Call-back for elf64_aarch64_size_stubs. */
+
+/* Create a new stub section, and arrange for it to be linked
+ immediately after INPUT_SECTION. */
+
+static asection *
+elf64_aarch64_add_stub_section (const char *stub_sec_name,
+ asection *input_section)
+{
+ asection *stub_sec;
+ flagword flags;
+ asection *output_section;
+ const char *secname;
+ lang_output_section_statement_type *os;
+ struct hook_stub_info info;
+
+ flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
+ | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY | SEC_KEEP);
+ stub_sec = bfd_make_section_anyway_with_flags (stub_file->the_bfd,
+ stub_sec_name, flags);
+ if (stub_sec == NULL)
+ goto err_ret;
+
+ bfd_set_section_alignment (stub_file->the_bfd, stub_sec, 3);
+
+ output_section = input_section->output_section;
+ secname = bfd_get_section_name (output_section->owner, output_section);
+ os = lang_output_section_find (secname);
+
+ info.input_section = input_section;
+ lang_list_init (&info.add);
+ lang_add_section (&info.add, stub_sec, NULL, os);
+
+ if (info.add.head == NULL)
+ goto err_ret;
+
+ if (hook_in_stub (&info, &os->children.head))
+ return stub_sec;
+
+ err_ret:
+ einfo ("%X%P: can not make stub section: %E\n");
+ return NULL;
+}
+
+/* Another call-back for elf_arm_size_stubs. */
+
+static void
+gldaarch64_layout_sections_again (void)
+{
+ /* If we have changed sizes of the stub sections, then we need
+ to recalculate all the section offsets. This may mean we need to
+ add even more stubs. */
+ gld${EMULATION_NAME}_map_segments (TRUE);
+ need_laying_out = -1;
+}
+
+static void
+build_section_lists (lang_statement_union_type *statement)
+{
+ if (statement->header.type == lang_input_section_enum)
+ {
+ asection *i = statement->input_section.section;
+
+ if (!((lang_input_statement_type *) i->owner->usrdata)->flags.just_syms
+ && (i->flags & SEC_EXCLUDE) == 0
+ && i->output_section != NULL
+ && i->output_section->owner == link_info.output_bfd)
+ elf64_aarch64_next_input_section (& link_info, i);
+ }
+}
+
+static void
+gld${EMULATION_NAME}_after_allocation (void)
+{
+ /* bfd_elf32_discard_info just plays with debugging sections,
+ ie. doesn't affect any code, so we can delay resizing the
+ sections. It's likely we'll resize everything in the process of
+ adding stubs. */
+ if (bfd_elf_discard_info (link_info.output_bfd, & link_info))
+ need_laying_out = 1;
+
+ /* If generating a relocatable output file, then we don't
+ have to examine the relocs. */
+ if (stub_file != NULL && !link_info.relocatable)
+ {
+ int ret = elf64_aarch64_setup_section_lists (link_info.output_bfd,
+ & link_info);
+
+ if (ret != 0)
+ {
+ if (ret < 0)
+ {
+ einfo ("%X%P: could not compute sections lists for stub generation: %E\n");
+ return;
+ }
+
+ lang_for_each_statement (build_section_lists);
+
+ /* Call into the BFD backend to do the real work. */
+ if (! elf64_aarch64_size_stubs (link_info.output_bfd,
+ stub_file->the_bfd,
+ & link_info,
+ group_size,
+ & elf64_aarch64_add_stub_section,
+ & gldaarch64_layout_sections_again))
+ {
+ einfo ("%X%P: cannot size stub section: %E\n");
+ return;
+ }
+ }
+ }
+
+ if (need_laying_out != -1)
+ gld${EMULATION_NAME}_map_segments (need_laying_out);
+}
+
+static void
+gld${EMULATION_NAME}_finish (void)
+{
+ if (! link_info.relocatable)
+ {
+ /* Now build the linker stubs. */
+ if (stub_file->the_bfd->sections != NULL)
+ {
+ if (! elf64_aarch64_build_stubs (& link_info))
+ einfo ("%X%P: can not build stubs: %E\n");
+ }
+ }
+
+ finish_default ();
+}
+
+/* This is a convenient point to tell BFD about target specific flags.
+ After the output has been created, but before inputs are read. */
+static void
+aarch64_elf_create_output_section_statements (void)
+{
+ if (strstr (bfd_get_target (link_info.output_bfd), "aarch64") == NULL)
+ {
+ /* The arm backend needs special fields in the output hash structure.
+ These will only be created if the output format is an arm format,
+ hence we do not support linking and changing output formats at the
+ same time. Use a link followed by objcopy to change output formats. */
+ einfo ("%F%X%P: error: Cannot change output format whilst linking AArch64 binaries.\n");
+ return;
+ }
+
+ bfd_elf64_aarch64_set_options (link_info.output_bfd, &link_info,
+ no_enum_size_warning,
+ no_wchar_size_warning,
+ pic_veneer);
+
+ stub_file = lang_add_input_file ("linker stubs",
+ lang_input_file_is_fake_enum,
+ NULL);
+ stub_file->the_bfd = bfd_create ("linker stubs", link_info.output_bfd);
+ if (stub_file->the_bfd == NULL
+ || ! bfd_set_arch_mach (stub_file->the_bfd,
+ bfd_get_arch (link_info.output_bfd),
+ bfd_get_mach (link_info.output_bfd)))
+ {
+ einfo ("%X%P: can not create BFD %E\n");
+ return;
+ }
+
+ stub_file->the_bfd->flags |= BFD_LINKER_CREATED;
+ ldlang_add_file (stub_file);
+}
+
+/* Avoid processing the fake stub_file in vercheck, stat_needed and
+ check_needed routines. */
+
+static void (*real_func) (lang_input_statement_type *);
+
+static void aarch64_for_each_input_file_wrapper (lang_input_statement_type *l)
+{
+ if (l != stub_file)
+ (*real_func) (l);
+}
+
+static void
+aarch64_lang_for_each_input_file (void (*func) (lang_input_statement_type *))
+{
+ real_func = func;
+ lang_for_each_input_file (&aarch64_for_each_input_file_wrapper);
+}
+
+#define lang_for_each_input_file aarch64_lang_for_each_input_file
+
+EOF
+
+# Define some shell vars to insert bits of code into the standard elf
+# parse_args and list_options functions.
+#
+PARSE_AND_LIST_PROLOGUE='
+#define OPTION_NO_ENUM_SIZE_WARNING 309
+#define OPTION_PIC_VENEER 310
+#define OPTION_STUBGROUP_SIZE 311
+#define OPTION_NO_WCHAR_SIZE_WARNING 312
+'
+
+PARSE_AND_LIST_SHORTOPTS=p
+
+PARSE_AND_LIST_LONGOPTS='
+ { "no-pipeline-knowledge", no_argument, NULL, '\'p\''},
+ { "no-enum-size-warning", no_argument, NULL, OPTION_NO_ENUM_SIZE_WARNING},
+ { "pic-veneer", no_argument, NULL, OPTION_PIC_VENEER},
+ { "stub-group-size", required_argument, NULL, OPTION_STUBGROUP_SIZE },
+ { "no-wchar-size-warning", no_argument, NULL, OPTION_NO_WCHAR_SIZE_WARNING},
+'
+
+PARSE_AND_LIST_OPTIONS='
+ fprintf (file, _(" --no-enum-size-warning Don'\''t warn about objects with incompatible\n"
+ " enum sizes\n"));
+ fprintf (file, _(" --no-wchar-size-warning Don'\''t warn about objects with incompatible"
+ " wchar_t sizes\n"));
+ fprintf (file, _(" --pic-veneer Always generate PIC interworking veneers\n"));
+ fprintf (file, _("\
+ --stub-group-size=N Maximum size of a group of input sections that can be\n\
+ handled by one stub section. A negative value\n\
+ locates all stubs after their branches (with a\n\
+ group size of -N), while a positive value allows\n\
+ two groups of input sections, one before, and one\n\
+ after each stub section. Values of +/-1 indicate\n\
+ the linker should choose suitable defaults.\n"
+ ));
+'
+
+PARSE_AND_LIST_ARGS_CASES='
+ case '\'p\'':
+ /* Only here for backwards compatibility. */
+ break;
+
+ case OPTION_NO_ENUM_SIZE_WARNING:
+ no_enum_size_warning = 1;
+ break;
+
+ case OPTION_NO_WCHAR_SIZE_WARNING:
+ no_wchar_size_warning = 1;
+ break;
+
+ case OPTION_PIC_VENEER:
+ pic_veneer = 1;
+ break;
+
+ case OPTION_STUBGROUP_SIZE:
+ {
+ const char *end;
+
+ group_size = bfd_scan_vma (optarg, &end, 0);
+ if (*end)
+ einfo (_("%P%F: invalid number `%s'\''\n"), optarg);
+ }
+ break;
+'
+
+# We have our own before_allocation etc. functions, but they call
+# the standard routines, so give them a different name.
+LDEMUL_BEFORE_ALLOCATION=aarch64_elf_before_allocation
+LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
+LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=aarch64_elf_create_output_section_statements
+
+# Replace the elf before_parse function with our own.
+LDEMUL_BEFORE_PARSE=gld"${EMULATION_NAME}"_before_parse
+
+# Call the extra arm-elf function
+LDEMUL_FINISH=gld${EMULATION_NAME}_finish
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * ld-aarch64/aarch64-elf.exp: New file.
+ * ld-aarch64/aarch64.ld: New file.
+ * ld-aarch64/eh-frame-bar.s: New file.
+ * ld-aarch64/eh-frame-foo.s: New file.
+ * ld-aarch64/eh-frame.d: New file.
+ * ld-aarch64/emit-relocs-257-be.d: New file.
+ * ld-aarch64/emit-relocs-257.d: New file.
+ * ld-aarch64/emit-relocs-257.s: New file.
+ * ld-aarch64/emit-relocs-260-be.d: New file.
+ * ld-aarch64/emit-relocs-260.d: New file.
+ * ld-aarch64/emit-relocs-260.s: New file.
+ * ld-aarch64/emit-relocs-262.d: New file.
+ * ld-aarch64/emit-relocs-262.s: New file.
+ * ld-aarch64/emit-relocs-263.d: New file.
+ * ld-aarch64/emit-relocs-263.s: New file.
+ * ld-aarch64/emit-relocs-264.d: New file.
+ * ld-aarch64/emit-relocs-264.s: New file.
+ * ld-aarch64/emit-relocs-265.d: New file.
+ * ld-aarch64/emit-relocs-265.s: New file.
+ * ld-aarch64/emit-relocs-266.d: New file.
+ * ld-aarch64/emit-relocs-266.s: New file.
+ * ld-aarch64/emit-relocs-267.d: New file.
+ * ld-aarch64/emit-relocs-267.s: New file.
+ * ld-aarch64/emit-relocs-268.d: New file.
+ * ld-aarch64/emit-relocs-268.s: New file.
+ * ld-aarch64/emit-relocs-269.d: New file.
+ * ld-aarch64/emit-relocs-269.s: New file.
+ * ld-aarch64/emit-relocs-270-bad.d: New file.
+ * ld-aarch64/emit-relocs-270.d: New file.
+ * ld-aarch64/emit-relocs-270.s: New file.
+ * ld-aarch64/emit-relocs-271.d: New file.
+ * ld-aarch64/emit-relocs-271.s: New file.
+ * ld-aarch64/emit-relocs-272.d: New file.
+ * ld-aarch64/emit-relocs-272.s: New file.
+ * ld-aarch64/emit-relocs-273.d: New file.
+ * ld-aarch64/emit-relocs-273.s: New file.
+ * ld-aarch64/emit-relocs-274.d: New file.
+ * ld-aarch64/emit-relocs-274.s: New file.
+ * ld-aarch64/emit-relocs-275.d: New file.
+ * ld-aarch64/emit-relocs-275.s: New file.
+ * ld-aarch64/emit-relocs-276.d: New file.
+ * ld-aarch64/emit-relocs-276.s: New file.
+ * ld-aarch64/emit-relocs-277.d: New file.
+ * ld-aarch64/emit-relocs-277.s: New file.
+ * ld-aarch64/emit-relocs-278.d: New file.
+ * ld-aarch64/emit-relocs-278.s: New file.
+ * ld-aarch64/emit-relocs-279-bad.d: New file.
+ * ld-aarch64/emit-relocs-279.d: New file.
+ * ld-aarch64/emit-relocs-279.s: New file.
+ * ld-aarch64/emit-relocs-280.d: New file.
+ * ld-aarch64/emit-relocs-280.s: New file.
+ * ld-aarch64/emit-relocs-282.d: New file.
+ * ld-aarch64/emit-relocs-282.s: New file.
+ * ld-aarch64/emit-relocs-283.d: New file.
+ * ld-aarch64/emit-relocs-283.s: New file.
+ * ld-aarch64/emit-relocs-284.d: New file.
+ * ld-aarch64/emit-relocs-284.s: New file.
+ * ld-aarch64/emit-relocs-285.d: New file.
+ * ld-aarch64/emit-relocs-285.s: New file.
+ * ld-aarch64/emit-relocs-286-bad.d: New file.
+ * ld-aarch64/emit-relocs-286.d: New file.
+ * ld-aarch64/emit-relocs-286.s: New file.
+ * ld-aarch64/emit-relocs-287.d: New file.
+ * ld-aarch64/emit-relocs-287.s: New file.
+ * ld-aarch64/emit-relocs-299.d: New file.
+ * ld-aarch64/emit-relocs-299.s: New file.
+ * ld-aarch64/emit-relocs-311.d: New file.
+ * ld-aarch64/emit-relocs-311.s: New file.
+ * ld-aarch64/emit-relocs-312.d: New file.
+ * ld-aarch64/emit-relocs-312.s: New file.
+ * ld-aarch64/emit-relocs1.s: New file.
+ * ld-aarch64/farcall-b-none-function.d: New file.
+ * ld-aarch64/farcall-b-none-function.s: New file.
+ * ld-aarch64/farcall-b.d: New file.
+ * ld-aarch64/farcall-b.s: New file.
+ * ld-aarch64/farcall-back.d: New file.
+ * ld-aarch64/farcall-back.s: New file.
+ * ld-aarch64/farcall-bl-none-function.d: New file.
+ * ld-aarch64/farcall-bl-none-function.s: New file.
+ * ld-aarch64/farcall-bl.d: New file.
+ * ld-aarch64/farcall-bl.s: New file.
+ * ld-aarch64/farcall-section.d: New file.
+ * ld-aarch64/farcall-section.s: New file.
+ * ld-aarch64/limit-b.d: New file.
+ * ld-aarch64/limit-b.s: New file.
+ * ld-aarch64/limit-bl.d: New file.
+ * ld-aarch64/limit-bl.s: New file.
+ * ld-aarch64/relocs.ld: New file.
+ * ld-aarch64/tls-desc-ie.d: New file.
+ * ld-aarch64/tls-desc-ie.s: New file.
+ * ld-aarch64/tls-relax-all.d: New file.
+ * ld-aarch64/tls-relax-all.s: New file.
+ * ld-aarch64/tls-relax-gd-ie.d: New file.
+ * ld-aarch64/tls-relax-gd-ie.s: New file.
+ * ld-aarch64/tls-relax-gd-le.d: New file.
+ * ld-aarch64/tls-relax-gd-le.s: New file.
+ * ld-aarch64/tls-relax-gdesc-ie-2.d: New file.
+ * ld-aarch64/tls-relax-gdesc-ie-2.s: New file.
+ * ld-aarch64/tls-relax-gdesc-ie.d: New file.
+ * ld-aarch64/tls-relax-gdesc-ie.s: New file.
+ * ld-aarch64/tls-relax-gdesc-le-2.d: New file.
+ * ld-aarch64/tls-relax-gdesc-le-2.s: New file.
+ * ld-aarch64/tls-relax-gdesc-le.d: New file.
+ * ld-aarch64/tls-relax-gdesc-le.s: New file.
+ * ld-aarch64/tls-relax-ie-le-2.d: New file.
+ * ld-aarch64/tls-relax-ie-le-2.s: New file.
+ * ld-aarch64/tls-relax-ie-le-3.d: New file.
+ * ld-aarch64/tls-relax-ie-le-3.s: New file.
+ * ld-aarch64/tls-relax-ie-le.d: New file.
+ * ld-aarch64/tls-relax-ie-le.s: New file.
+ * ld-aarch64/weak-undefined.d: New file.
+ * ld-aarch64/weak-undefined.s: New file.
+ * ld-elf/binutils.exp (binutils_test): Add optional parameter
+ 'test_name'; change to construct 'test_name' from the 'prog_name'
+ and 'ld_options' only when "$test_name" == "".
+ * ld-elf/group8a.d (#notarget): Add AArch64.
+ * ld-elf/group8b.d (#notarget): Add AArch64.
+ * ld-elf/group9a.d (#notarget): Add AArch64.
+ * ld-elf/group9b.d (#notarget): Add AArch64.
+ * ld-elf/pr12851.d (#notarget): Add AArch64.
+ * ld-elf/pr12975.d (#notarget): Add AArch64.
+ * ld-elf/pr13177.d (#notarget): Add AArch64.
+ * ld-elf/pr13195.d (#notarget): Add AArch64.
+ * ld-elfvers/vers.exp: Add AArch64.
+ * ld-shared/shared.exp: Add AArch64.
+ * ld-srec/srec.exp: Add AArch64.
+ * lib/ld-lib.exp: Add AArch64.
+
2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
* ld-mips-elf/dyn-sec64.ld: Use HIDDEN to define _gp.
--- /dev/null
+# Expect script for various AARCH64 ELF tests.
+# Copyright 2009-2012 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# Exclude non-aarch64-ELF targets.
+if { ![is_elf_format] || ![istarget "aarch64*-*-*"] } {
+ return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result. Compare with regex (last arg).
+# nm: Apply nm options on result. Compare with regex (last arg).
+# readelf: Apply readelf options on result. Compare with regex (last arg).
+
+set aarch64elftests {
+ {"EH Frame merge" "-Ttext 0x8000" "" {eh-frame-bar.s eh-frame-foo.s}
+ {{objdump --dwarf=frames eh-frame.d}} "eh-frame"}
+}
+
+run_ld_link_tests $aarch64elftests
+
+# Relocation Tests
+run_dump_test "weak-undefined"
+run_dump_test "emit-relocs-257"
+run_dump_test "emit-relocs-257-be"
+# 258 is tested in 257
+# 259 is tested in 257
+run_dump_test "emit-relocs-260"
+run_dump_test "emit-relocs-260-be"
+# 261 is tested by 260
+run_dump_test "emit-relocs-262"
+run_dump_test "emit-relocs-263"
+run_dump_test "emit-relocs-264"
+run_dump_test "emit-relocs-265"
+run_dump_test "emit-relocs-266"
+run_dump_test "emit-relocs-267"
+run_dump_test "emit-relocs-268"
+run_dump_test "emit-relocs-269"
+run_dump_test "emit-relocs-270"
+run_dump_test "emit-relocs-270-bad"
+run_dump_test "emit-relocs-271"
+run_dump_test "emit-relocs-272"
+run_dump_test "emit-relocs-273"
+run_dump_test "emit-relocs-274"
+run_dump_test "emit-relocs-275"
+run_dump_test "emit-relocs-276"
+run_dump_test "emit-relocs-277"
+run_dump_test "emit-relocs-278"
+run_dump_test "emit-relocs-279"
+run_dump_test "emit-relocs-279-bad"
+run_dump_test "emit-relocs-280"
+# 281 is unused
+run_dump_test "emit-relocs-282"
+run_dump_test "emit-relocs-283"
+run_dump_test "emit-relocs-284"
+run_dump_test "emit-relocs-285"
+run_dump_test "emit-relocs-286"
+run_dump_test "emit-relocs-286-bad"
+# 287-298 are not done yet
+run_dump_test "emit-relocs-299"
+# 300-310 are not done yet
+run_dump_test "emit-relocs-311"
+run_dump_test "emit-relocs-312"
+
+
+run_dump_test "limit-b"
+run_dump_test "limit-bl"
+run_dump_test "farcall-section"
+run_dump_test "farcall-back"
+run_dump_test "farcall-bl"
+run_dump_test "farcall-b"
+run_dump_test "farcall-b-none-function"
+run_dump_test "farcall-bl-none-function"
+
+run_dump_test "tls-relax-all"
+run_dump_test "tls-relax-gd-le"
+run_dump_test "tls-relax-gdesc-le"
+run_dump_test "tls-relax-gd-ie"
+run_dump_test "tls-relax-gdesc-ie"
+run_dump_test "tls-relax-ie-le"
+run_dump_test "tls-desc-ie"
+run_dump_test "tls-relax-gdesc-ie-2"
+run_dump_test "tls-relax-gdesc-le-2"
+run_dump_test "tls-relax-ie-le-2"
+run_dump_test "tls-relax-ie-le-3"
--- /dev/null
+/* Script for ld testsuite */
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x8000); . = 0x8000;
+ .text :
+ {
+ *(.before)
+ *(.text)
+ *(.after)
+ } =0
+ . = 0x9000;
+ .got : { *(.got) *(.got.plt)}
+ . = 0x12340000;
+ .far : { *(.far) }
+ .ARM.attributes 0 : { *(.ARM.atttributes) }
+}
--- /dev/null
+__longjmp:
+ .cfi_startproc
+ .cfi_def_cfa x0, 0
+ .cfi_offset x19, 16
+ .cfi_offset x20, 16
+ .cfi_offset x21, 16
+ .cfi_offset x22, 16
+ .cfi_offset x23, 24
+ .cfi_offset x24, 24
+ .cfi_offset x25, 24
+ .cfi_offset x26, 24
+ .cfi_offset x27, 24
+ .cfi_offset x28, 32
+ .cfi_offset x29, 32
+ .cfi_offset x30, 36
+ .cfi_offset d9, 8
+# This eh frame data differs from eh-frame-bar.s here, see the comment
+# in eh-frame-foo.s
+ .cfi_offset d11, 8
+
+ ldp x19, x20, [x0, #16]
+ ldp x21, x22, [x0, #16]
+ ldp x23, x24, [x0, #24]
+ ldp x25, x26, [x0, #24]
+ ldp x27, x28, [x0, #24]
+ ldp x29, x30, [x0, #32]
+
+ ldp d8, d9, [x0, #8]
+ ldp d10, d11, [x0, #8]
+ ldp d12, d13, [x0, #8]
+ ldp d14, d15, [x0, #8]
+ ldr x5, [x0, #48]
+ mov sp, x5
+ cmp x1, #0
+ mov x0, #1
+ csel x0, x1, x0, ne
+ br x30
+ .cfi_endproc
--- /dev/null
+__longjmp:
+ .cfi_startproc
+ .cfi_def_cfa x0, 0
+ .cfi_offset x19, 16
+ .cfi_offset x20, 16
+ .cfi_offset x21, 16
+ .cfi_offset x22, 16
+ .cfi_offset x23, 24
+ .cfi_offset x24, 24
+ .cfi_offset x25, 24
+ .cfi_offset x26, 24
+ .cfi_offset x27, 24
+ .cfi_offset x28, 32
+ .cfi_offset x29, 32
+ .cfi_offset x30, 36
+ .cfi_offset d9, 8
+
+/* This eh frame data differs from eh-frame-bar.s here. The eh
+ frame information is identical but changes at the end. The
+ initial identical section is long enough to overflow the
+ initial instruction buffer used in eh frame merging. This
+ checks that merging does something sane once the initial
+ instruction buffer overflows. */
+
+.cfi_offset d10, 8
+
+
+
+
+
+
+
+ ldp x19, x20, [x0, #16]
+ ldp x21, x22, [x0, #16]
+ ldp x23, x24, [x0, #24]
+ ldp x25, x26, [x0, #24]
+ ldp x27, x28, [x0, #24]
+ ldp x29, x30, [x0, #32]
+
+ ldp d8, d9, [x0, #8]
+ ldp d10, d11, [x0, #8]
+ ldp d12, d13, [x0, #8]
+ ldp d14, d15, [x0, #8]
+ ldr x5, [x0, #48]
+ mov sp, x5
+ cmp x1, #0
+ mov x0, #1
+ csel x0, x1, x0, ne
+
+ br x30
+ .cfi_endproc
+
+ .global _start
+_start:
+
--- /dev/null
+.*: file format elf64-(little|big)aarch64
+
+Contents of the .eh_frame section:
+
+00000000 00000044 00000000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 2
+ Data alignment factor: -4
+ Return address column: 30
+ Augmentation data: 1b
+
+ DW_CFA_def_cfa: r31 ofs 0
+ DW_CFA_def_cfa: r0 ofs 0
+ DW_CFA_offset_extended_sf: r19 at cfa\+16
+ DW_CFA_offset_extended_sf: r20 at cfa\+16
+ DW_CFA_offset_extended_sf: r21 at cfa\+16
+ DW_CFA_offset_extended_sf: r22 at cfa\+16
+ DW_CFA_offset_extended_sf: r23 at cfa\+24
+ DW_CFA_offset_extended_sf: r24 at cfa\+24
+ DW_CFA_offset_extended_sf: r25 at cfa\+24
+ DW_CFA_offset_extended_sf: r26 at cfa\+24
+ DW_CFA_offset_extended_sf: r27 at cfa\+24
+ DW_CFA_offset_extended_sf: r28 at cfa\+32
+ DW_CFA_offset_extended_sf: r29 at cfa\+32
+ DW_CFA_offset_extended_sf: r30 at cfa\+36
+ DW_CFA_offset_extended_sf: r9 at cfa\+8
+ DW_CFA_offset_extended_sf: r11 at cfa\+8
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+
+00000048 00000014 0000004c FDE cie=00000000 pc=f*ffffff80..f*ffffffc0
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+
+00000060 00000044 00000000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 2
+ Data alignment factor: -4
+ Return address column: 30
+ Augmentation data: 1b
+
+ DW_CFA_def_cfa: r31 ofs 0
+ DW_CFA_def_cfa: r0 ofs 0
+ DW_CFA_offset_extended_sf: r19 at cfa\+16
+ DW_CFA_offset_extended_sf: r20 at cfa\+16
+ DW_CFA_offset_extended_sf: r21 at cfa\+16
+ DW_CFA_offset_extended_sf: r22 at cfa\+16
+ DW_CFA_offset_extended_sf: r23 at cfa\+24
+ DW_CFA_offset_extended_sf: r24 at cfa\+24
+ DW_CFA_offset_extended_sf: r25 at cfa\+24
+ DW_CFA_offset_extended_sf: r26 at cfa\+24
+ DW_CFA_offset_extended_sf: r27 at cfa\+24
+ DW_CFA_offset_extended_sf: r28 at cfa\+32
+ DW_CFA_offset_extended_sf: r29 at cfa\+32
+ DW_CFA_offset_extended_sf: r30 at cfa\+36
+ DW_CFA_offset_extended_sf: r9 at cfa\+8
+ DW_CFA_offset_extended_sf: r10 at cfa\+8
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+
+000000a8 00000014 0000004c FDE cie=00000060 pc=f*ffffffc0..00000000
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+
--- /dev/null
+#source: emit-relocs-257.s
+#ld: -T relocs.ld --defsym tempy=0x11012 --defsym tempy2=0x45034 --defsym tempy3=0x1234 -e0 --emit-relocs
+#notarget: aarch64-*-*
+#objdump: -dr
+#...
+ +10000: 00011012 \.word 0x00011012
+ +10000: R_AARCH64_ABS32 tempy
+ +10004: 00000000 \.word 0x00000000
+ +10004: R_AARCH64_ABS64 tempy2
+ +10008: 00045034 \.word 0x00045034
+ +1000c: 1234123c \.word 0x1234123c
+ +1000c: R_AARCH64_ABS16 tempy3
+ +1000e: R_AARCH64_ABS16 tempy3\+0x8
+ +10010: 8a000000 and x0, x0, x0
+ +10014: 92400000 and x0, x0, #0x1
+
--- /dev/null
+#source: emit-relocs-257.s
+#ld: -T relocs.ld --defsym tempy=0x11012 --defsym tempy2=0x45034 --defsym tempy3=0x1234 -e0 --emit-relocs
+#notarget: aarch64_be-*-*
+#objdump: -dr
+#...
+ +10000: 00011012 \.word 0x00011012
+ +10000: R_AARCH64_ABS32 tempy
+ +10004: 00045034 \.word 0x00045034
+ +10004: R_AARCH64_ABS64 tempy2
+ +10008: 00000000 \.word 0x00000000
+ +1000c: 123c1234 \.word 0x123c1234
+ +1000c: R_AARCH64_ABS16 tempy3
+ +1000e: R_AARCH64_ABS16 tempy3\+0x8
+ +10010: 8a000000 and x0, x0, x0
+ +10014: 92400000 and x0, x0, #0x1
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+.word tempy
+.xword tempy2
+.hword tempy3
+.hword tempy3+8
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+
+
--- /dev/null
+#source: emit-relocs-260.s
+#ld: -T relocs.ld --defsym tempy=0x11012 --defsym tempy2=0x45034 --defsym tempy3=0x1234 --defsym _GOT_=0x10000 -e0 --emit-relocs
+#notarget: aarch64-*-*
+#objdump: -dr
+#...
+ +10000: R_AARCH64_PREL32 _GOT_
+ +10004: R_AARCH64_PREL64 _GOT_\+0x12
+ +10008: 0000000e \.word 0x0000000e
+ +1000c: fff404f2 \.word 0xfff404f2
+ +1000c: R_AARCH64_PREL16 _GOT_
+ +1000e: R_AARCH64_PREL16 _GOT_\+0x500
+ +10010: 8a000000 and x0, x0, x0
+ +10014: 92400000 and x0, x0, #0x1
+
--- /dev/null
+#source: emit-relocs-260.s
+#ld: -T relocs.ld --defsym tempy=0x11012 --defsym tempy2=0x45034 --defsym tempy3=0x1234 --defsym _GOT_=0x10000 -e0 --emit-relocs
+#notarget: aarch64_be-*-*
+#objdump: -dr
+#...
+ +10000: 00000000 \.word 0x00000000
+ +10000: R_AARCH64_PREL32 _GOT_
+ +10004: 0000000e \.word 0x0000000e
+ +10004: R_AARCH64_PREL64 _GOT_\+0x12
+ +10008: 00000000 \.word 0x00000000
+ +1000c: 04f2fff4 \.word 0x04f2fff4
+ +1000c: R_AARCH64_PREL16 _GOT_
+ +1000e: R_AARCH64_PREL16 _GOT_\+0x500
+ +10010: 8a000000 and x0, x0, x0
+ +10014: 92400000 and x0, x0, #0x1
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+.word _GOT_ - .
+.xword _GOT_ - . + 0x12
+.hword _GOT_ - .
+.hword _GOT_ - . + 0x500
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+
+
+
--- /dev/null
+#source: emit-relocs-262.s
+#ld: -T relocs.ld --defsym tempy=0x11012 --defsym tempy2=0x45034 --defsym tempy3=0x1234 --defsym _GOT_=0x20000 -e0 --emit-relocs
+#error: .*truncated.*
+#objdump: -dr
+#...
+ +10000: 00011012 \.word 0x00011012
+ +10000: R_AARCH64_PREL32 tempy
+ +10004: 00045034 \.word 0x00045034
+ +10004: R_AARCH64_PREL64 tempy2
+ +10008: 00000000 \.word 0x00000000
+ +1000c: 123c1234 \.word 0x123c1234
+ +1000c: R_AARCH64_PREL16 tempy3
+ +1000e: R_AARCH64_PREL16 tempy3\+0x8
+ +10010: 8a000000 and x0, x0, x0
+ +10014: 92400000 and x0, x0, #0x1
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+.word _GOT_ - .
+.xword _GOT_ - . + 0x12
+.hword _GOT_ - .
+.hword _GOT_ - .
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+
+
+
--- /dev/null
+#source: emit-relocs-263.s
+#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
+#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_MOVW_UABS_G0 against symbol `tempy.*
+#objdump: -dr
+
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2820004 movz x4, #0x1000
+ +10008: R_AARCH64_MOVW_UABS_G0 tempy
+ +1000c: d28a0007 movz x7, #0x5000
+ +1000c: R_AARCH64_MOVW_UABS_G0 tempy2
+ +10010: d2824691 movz x17, #0x1234
+ +10010: R_AARCH64_MOVW_UABS_G0 tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :abs_g0:tempy
+ movz x7, :abs_g0:tempy2
+ movz x17, :abs_g0:tempy3
+
--- /dev/null
+#source: emit-relocs-264.s
+#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2820004 movz x4, #0x1000
+ +10008: R_AARCH64_MOVW_UABS_G0_NC tempy
+ +1000c: d28a0007 movz x7, #0x5000
+ +1000c: R_AARCH64_MOVW_UABS_G0_NC tempy2
+ +10010: d2824691 movz x17, #0x1234
+ +10010: R_AARCH64_MOVW_UABS_G0_NC tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :abs_g0_nc:tempy
+ movz x7, :abs_g0_nc:tempy2
+ movz x17, :abs_g0_nc:tempy3
+
--- /dev/null
+#source: emit-relocs-265.s
+#ld: -T relocs.ld --defsym tempy=0x100011000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
+#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_MOVW_UABS_G1 against symbol `tempy.*
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2a00024 movz x4, #0x1, lsl #16
+ +10008: R_AARCH64_MOVW_UABS_G1 tempy
+ +1000c: d2a00087 movz x7, #0x4, lsl #16
+ +1000c: R_AARCH64_MOVW_UABS_G1 tempy2
+ +10010: d2a00011 movz x17, #0x0, lsl #16
+ +10010: R_AARCH64_MOVW_UABS_G1 tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :abs_g1:tempy
+ movz x7, :abs_g1:tempy2
+ movz x17, :abs_g1:tempy3
+
--- /dev/null
+#source: emit-relocs-266.s
+#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2a00024 movz x4, #0x1, lsl #16
+ +10008: R_AARCH64_MOVW_UABS_G1_NC tempy
+ +1000c: d2a00087 movz x7, #0x4, lsl #16
+ +1000c: R_AARCH64_MOVW_UABS_G1_NC tempy2
+ +10010: d2a00011 movz x17, #0x0, lsl #16
+ +10010: R_AARCH64_MOVW_UABS_G1_NC tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :abs_g1_nc:tempy
+ movz x7, :abs_g1_nc:tempy2
+ movz x17, :abs_g1_nc:tempy3
+
--- /dev/null
+#source: emit-relocs-267.s
+#ld: -T relocs.ld --defsym tempy=0x63001000 --defsym tempy2=0x4500000000 --defsym tempy3=0x1234567812345 -e0 --emit-relocs
+#error: .*truncated.*tempy3.*
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2c00004 movz x4, #0x0, lsl #32
+ +10008: R_AARCH64_MOVW_UABS_G2 tempy
+ +1000c: d2c008a7 movz x7, #0x45, lsl #32
+ +1000c: R_AARCH64_MOVW_UABS_G2 tempy2
+ +10010: d2c468b1 movz x17, #0x2345, lsl #32
+ +10010: R_AARCH64_MOVW_UABS_G2 tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :abs_g2:tempy
+ movz x7, :abs_g2:tempy2
+ movz x17, :abs_g2:tempy3
+
--- /dev/null
+#source: emit-relocs-268.s
+#ld: -T relocs.ld --defsym tempy=0x63001000 --defsym tempy2=0x4500000000 --defsym tempy3=0x1234567812345 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2c00004 movz x4, #0x0, lsl #32
+ +10008: R_AARCH64_MOVW_UABS_G2_NC tempy
+ +1000c: d2c008a7 movz x7, #0x45, lsl #32
+ +1000c: R_AARCH64_MOVW_UABS_G2_NC tempy2
+ +10010: d2c468b1 movz x17, #0x2345, lsl #32
+ +10010: R_AARCH64_MOVW_UABS_G2_NC tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :abs_g2_nc:tempy
+ movz x7, :abs_g2_nc:tempy2
+ movz x17, :abs_g2_nc:tempy3
+
--- /dev/null
+#source: emit-relocs-269.s
+#ld: -T relocs.ld --defsym tempy=0x6300100100100100 --defsym tempy2=0xf00df00df00df00d --defsym tempy3=0x1234567812345 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2ec6004 movz x4, #0x6300, lsl #48
+ +10008: R_AARCH64_MOVW_UABS_G3 tempy
+ +1000c: d2fe01a7 movz x7, #0xf00d, lsl #48
+ +1000c: R_AARCH64_MOVW_UABS_G3 tempy2
+ +10010: d2e00031 movz x17, #0x1, lsl #48
+ +10010: R_AARCH64_MOVW_UABS_G3 tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :abs_g3:tempy
+ movz x7, :abs_g3:tempy2
+ movz x17, :abs_g3:tempy3
+
--- /dev/null
+#source: emit-relocs-270.s
+#ld: -T relocs.ld --defsym tempy=0x10012 --defsym tempy2=0x45000 --defsym tempy3=-292 -e0 --emit-relocs
+#error: .*truncated.*tempy[12].*
+#objdump: -dr
+
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2820244 movz x4, #0x1012
+ +10008: R_AARCH64_MOVW_SABS_G0 tempy
+ +1000c: d288a007 movz x7, #0x4500
+ +1000c: R_AARCH64_MOVW_SABS_G0 tempy2
+ +10010: 92802471 movn x17, #0x123
+ +10010: R_AARCH64_MOVW_SABS_G0 tempy3
+
--- /dev/null
+#source: emit-relocs-270.s
+#ld: -T relocs.ld --defsym tempy=0x1012 --defsym tempy2=0x4500 --defsym tempy3=-292 -e0 --emit-relocs
+#objdump: -dr
+
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2820244 movz x4, #0x1012
+ +10008: R_AARCH64_MOVW_SABS_G0 tempy
+ +1000c: d288a007 movz x7, #0x4500
+ +1000c: R_AARCH64_MOVW_SABS_G0 tempy2
+ +10010: 92802471 movn x17, #0x123
+ +10010: R_AARCH64_MOVW_SABS_G0 tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :abs_g0_s:tempy
+ movz x7, :abs_g0_s:tempy2
+ movz x17, :abs_g0_s:tempy3
+
--- /dev/null
+#source: emit-relocs-271.s
+#ld: -T relocs.ld --defsym tempy=0x1012 --defsym tempy2=0x674500 --defsym tempy3=-292 -e0 --emit-relocs
+#objdump: -dr
+
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2a00004 movz x4, #0x0, lsl #16
+ +10008: R_AARCH64_MOVW_SABS_G1 tempy
+ +1000c: d2a00ce7 movz x7, #0x67, lsl #16
+ +1000c: R_AARCH64_MOVW_SABS_G1 tempy2
+ +10010: 92a00011 movn x17, #0x0, lsl #16
+ +10010: R_AARCH64_MOVW_SABS_G1 tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :abs_g1_s:tempy
+ movz x7, :abs_g1_s:tempy2
+ movz x17, :abs_g1_s:tempy3
+
--- /dev/null
+#source: emit-relocs-272.s
+#ld: -T relocs.ld --defsym tempy=0x1012 --defsym tempy2=-12345678912345 --defsym tempy3=-292 -e0 --emit-relocs
+#objdump: -dr
+
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2c00004 movz x4, #0x0, lsl #32
+ +10008: R_AARCH64_MOVW_SABS_G2 tempy
+ +1000c: 92c16747 movn x7, #0xb3a, lsl #32
+ +1000c: R_AARCH64_MOVW_SABS_G2 tempy2
+ +10010: 92c00011 movn x17, #0x0, lsl #32
+ +10010: R_AARCH64_MOVW_SABS_G2 tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :abs_g2_s:tempy
+ movz x7, :abs_g2_s:tempy2
+ movz x17, :abs_g2_s:tempy3
+
--- /dev/null
+#source: emit-relocs-273.s
+#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: 58007fc4 ldr x4, 11000 <tempy>
+ +10008: R_AARCH64_LD_PREL_LO19 tempy
+ +1000c: 581a7fa7 ldr x7, 45000 <tempy2>
+ +1000c: R_AARCH64_LD_PREL_LO19 tempy2
+ +10010: 58f89131 ldr x17, 1234 <tempy3>
+ +10010: R_AARCH64_LD_PREL_LO19 tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ ldr x4,tempy
+ ldr x7,tempy2
+ ldr x17,tempy3
+
--- /dev/null
+#source: emit-relocs-274.s
+#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: 10007fc2 adr x2, .*
+ +10008: R_AARCH64_ADR_PREL_LO21 tempy
+ +1000c: 101a7fa7 adr x7, 45000 .*
+ +1000c: R_AARCH64_ADR_PREL_LO21 tempy2
+ +10010: 10f89131 adr x17, .*
+ +10010: R_AARCH64_ADR_PREL_LO21 tempy3
--- /dev/null
+ and x0,x0,x0
+ and x0,x0,#1
+ adr x2,tempy
+ adr x7,tempy2
+ adr x17,tempy3
--- /dev/null
+#source: emit-relocs-275.s
+#ld: -T relocs.ld --defsym tempy=0x200011000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
+#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_ADR_PREL_PG_HI21 against symbol `tempy'
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: b0000002 adrp x2, .*
+ +10008: R_AARCH64_ADR_PREL_PG_HI21 tempy
+ +1000c: b00001a7 adrp x7, .*
+ +1000c: R_AARCH64_ADR_PREL_PG_HI21 tempy2
+ +10010: b0ffff91 adrp x17, .*
+ +10010: R_AARCH64_ADR_PREL_PG_HI21 tempy3
+
+
--- /dev/null
+.comm gempy,4,4
+.text
+ and x0,x0,x0
+ and x0,x0,#1
+ adrp x2,tempy
+ adrp x7,tempy2
+ adrp x17,tempy3
+
--- /dev/null
+#source: emit-relocs-275.s
+#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: b0000002 adrp x2, 11000 <tempy>
+ +10008: R_AARCH64_ADR_PREL_PG_HI21 tempy
+ +1000c: b00001a7 adrp x7, 45000 <tempy2>
+ +1000c: R_AARCH64_ADR_PREL_PG_HI21 tempy2
+ +10010: b0ffff91 adrp x17, 1000 <tempy3-0x234>
+ +10010: R_AARCH64_ADR_PREL_PG_HI21 tempy3
+
+
--- /dev/null
+.comm gempy,4,4
+.text
+ and x0,x0,x0
+ and x0,x0,#1
+ adrp x2,tempy
+ adrp x7,tempy2
+ adrp x17,tempy3
+
--- /dev/null
+#source: emit-relocs-277.s
+#ld: -T relocs.ld --defsym tempy=0x11018 --defsym tempy2=0x45038 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: 91006064 add x4, x3,.*
+ +10008: R_AARCH64_ADD_ABS_LO12_NC tempy
+ +1000c: 9100e067 add x7, x3,.*
+ +1000c: R_AARCH64_ADD_ABS_LO12_NC tempy2
+ +10010: 9108d071 add x17, x3,.*
+ +10010: R_AARCH64_ADD_ABS_LO12_NC tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ add x4, x3, #:lo12:tempy
+ add x7, x3, #:lo12:tempy2
+ add x17, x3, #:lo12:tempy3
--- /dev/null
+#source: emit-relocs-278.s
+#ld: -T relocs.ld --defsym tempy=0x11018 --defsym tempy2=0x45038 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: 3d406064 ldr b4, \[x3,.*
+ +10008: R_AARCH64_LDST8_ABS_LO12_NC tempy
+ +1000c: 3d40e067 ldr b7, \[x3,.*
+ +1000c: R_AARCH64_LDST8_ABS_LO12_NC tempy2
+ +10010: 3d48d071 ldr b17, \[x3,.*
+ +10010: R_AARCH64_LDST8_ABS_LO12_NC tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ ldr b4, [x3, #:lo12:tempy]
+ ldr b7, [x3, #:lo12:tempy2]
+ ldr b17, [x3, #:lo12:tempy3]
--- /dev/null
+#source: emit-relocs-279.s
+#ld: -T relocs.ld --defsym target=0xc000 --defsym target2=0x45678 -e0 --emit-relocs
+#error: .*truncated.*target2.*
+#objdump: -dr
+#...
+ +10000: 8a000000 and .*
+ +10004: 8a000000 and .*
+ +10008: 8a000000 and .*
+ +1000c: 8a000000 and .*
+ +10010: 17ffeffc b c000 <target>
+ +10010: R_AARCH64_TSTBR14 target
+ +10014: 17ffefff b c010 <target\+0x10>
+ +10014: R_AARCH64_TSTBR14 target\+0x10
--- /dev/null
+#source: emit-relocs-279.s
+#ld: -T relocs.ld --defsym target=0xc000 --defsym target2=0x12340 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and .*
+ +10004: 8a000000 and .*
+ +10008: 8a000000 and .*
+ +1000c: 8a000000 and .*
+ +10010: 363dff84 tbz w4, #7, c000 <target>
+ +10010: R_AARCH64_TSTBR14 target
+ +10014: b745ffe7 tbnz x7, #40, c010 <target\+0x10>
+ +10014: R_AARCH64_TSTBR14 target\+0x10
+ +10018: 3619194c tbz w12, #3, 12340 <target2>
+ +10018: R_AARCH64_TSTBR14 target2
+ +1001c: b7c118d1 tbnz x17, #56, 12334 <target.*
+ +1001c: R_AARCH64_TSTBR14 target.*
+
--- /dev/null
+ and x0,x0,x0
+ and x0,x0,x0
+ and x0,x0,x0
+ and x0,x0,x0
+ tbz x4, 7, target
+ tbnz x7, 40, target+16
+ tbz x12, 3, target2
+ tbnz x17, 56, target2-12
--- /dev/null
+#source: emit-relocs-280.s
+#ld: -T relocs.ld --defsym target=0xc000 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and .*
+ +10004: 8a000000 and .*
+ +10008: 8a000000 and .*
+ +1000c: 8a000000 and .*
+ +10010: 54fdff80 b.eq c000 <target>
+ +10010: R_AARCH64_CONDBR19 target
+ +10014: 54fdffe0 b.eq c010 <target\+0x10>
+ +10014: R_AARCH64_CONDBR19 target\+0x10
--- /dev/null
+ and x0,x0,x0
+ and x0,x0,x0
+ and x0,x0,x0
+ and x0,x0,x0
+ beq target
+ beq target+16
--- /dev/null
+#source: emit-relocs-282.s
+#ld: -T relocs.ld --defsym target=0xc000 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and .*
+ +10004: 8a000000 and .*
+ +10008: 8a000000 and .*
+ +1000c: 8a000000 and .*
+ +10010: 17ffeffc b c000 <target>
+ +10010: R_AARCH64_JUMP26 target
+ +10014: 17ffefff b c010 <target\+0x10>
+ +10014: R_AARCH64_JUMP26 target\+0x10
--- /dev/null
+ and x0,x0,x0
+ and x0,x0,x0
+ and x0,x0,x0
+ and x0,x0,x0
+ b target
+ b target+16
--- /dev/null
+#source: emit-relocs-283.s
+#ld: -T relocs.ld --defsym target=0xc000 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and .*
+ +10004: 8a000000 and .*
+ +10008: 8a000000 and .*
+ +1000c: 8a000000 and .*
+ +10010: 97ffeffc bl c000 <target>
+ +10010: R_AARCH64_CALL26 target
+ +10014: 97ffefff bl c010 <target\+0x10>
+ +10014: R_AARCH64_CALL26 target\+0x10
--- /dev/null
+ and x0,x0,x0
+ and x0,x0,x0
+ and x0,x0,x0
+ and x0,x0,x0
+ bl target
+ bl target+16
--- /dev/null
+#source: emit-relocs-284.s
+#ld: -T relocs.ld --defsym tempy=0x11018 --defsym tempy2=0x45038 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: 7d403064 ldr h4, \[x3,.*
+ +10008: R_AARCH64_LDST16_ABS_LO12_NC tempy
+ +1000c: 7d407067 ldr h7, \[x3,.*
+ +1000c: R_AARCH64_LDST16_ABS_LO12_NC tempy2
+ +10010: 7d446871 ldr h17, \[x3,.*
+ +10010: R_AARCH64_LDST16_ABS_LO12_NC tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ ldr h4, [x3, #:lo12:tempy]
+ ldr h7, [x3, #:lo12:tempy2]
+ ldr h17, [x3, #:lo12:tempy3]
--- /dev/null
+#source: emit-relocs-285.s
+#ld: -T relocs.ld --defsym tempy=0x11018 --defsym tempy2=0x45038 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: b9401864 ldr w4, \[x3,.*
+ +10008: R_AARCH64_LDST32_ABS_LO12_NC tempy
+ +1000c: b9403867 ldr w7, \[x3,.*
+ +1000c: R_AARCH64_LDST32_ABS_LO12_NC tempy2
+ +10010: b9423471 ldr w17, \[x3,.*
+ +10010: R_AARCH64_LDST32_ABS_LO12_NC tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ ldr w4, [x3, #:lo12:tempy]
+ ldr w7, [x3, #:lo12:tempy2]
+ ldr w17, [x3, #:lo12:tempy3]
--- /dev/null
+#source: emit-relocs-286.s
+#ld: -T relocs.ld --defsym tempy=0x11018 --defsym tempy2=0x45038 --defsym tempy3=0x1234 -e0 --emit-relocs
+#error: .*truncated.*tempy3.*
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: f9400c64 ldr x4, \[x3,.*
+ +10008: R_AARCH64_LDST64_ABS_LO12_NC tempy
+ +1000c: f9401c67 ldr x7, \[x3,.*
+ +1000c: R_AARCH64_LDST64_ABS_LO12_NC tempy2
+ +10010: f9411871 ldr x17, \[x3,.*
+ +10010: R_AARCH64_LDST64_ABS_LO12_NC tempy3
+
--- /dev/null
+#source: emit-relocs-286.s
+#ld: -T relocs.ld --defsym tempy=0x11018 --defsym tempy2=0x45038 --defsym tempy3=0x1230 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: f9400c64 ldr x4, \[x3,.*
+ +10008: R_AARCH64_LDST64_ABS_LO12_NC tempy
+ +1000c: f9401c67 ldr x7, \[x3,.*
+ +1000c: R_AARCH64_LDST64_ABS_LO12_NC tempy2
+ +10010: f9411871 ldr x17, \[x3,.*
+ +10010: R_AARCH64_LDST64_ABS_LO12_NC tempy3
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ ldr x4, [x3, #:lo12:tempy]
+ ldr x7, [x3, #:lo12:tempy2]
+ ldr x17, [x3, #:lo12:tempy3]
--- /dev/null
+#source: emit-relocs-287.s
+#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 --defsym _GOT_=0x10000 -e0 --emit-relocs
+#objdump: -dr
+
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: d2820004 movz x4, #0x1000
+ +10008: R_AARCH64_MOVW_PREL_G0 _GOT_
+ +1000c: d28a0007 movz x7, #0x5000
+ +1000c: R_AARCH64_MOVW_PREL_G0 _GOT_
+ +10010: d2824691 movz x17, #0x1234
+ +10010: R_AARCH64_MOVW_PREL_G0 _GOT_
+
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :prel_g0:tempy
+ movz x7, :prel_g0:tempy2
+ movz x17, :prel_g0:tempy3
+
--- /dev/null
+#source: emit-relocs-299.s
+#ld: -T relocs.ld --defsym tempy=0x11030 --defsym tempy2=0x45fa0 --defsym tempy3=0x1230 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: 3dc00c64 ldr q4, \[x3,.*
+ +10008: R_AARCH64_LDST128_ABS_LO12_NC tempy
+ +1000c: 3dc3e867 ldr q7, \[x3,.*
+ +1000c: R_AARCH64_LDST128_ABS_LO12_NC tempy2
+ +10010: 3dc08c71 ldr q17, \[x3,.*
+ +10010: R_AARCH64_LDST128_ABS_LO12_NC tempy3
--- /dev/null
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ ldr q4, [x3, #:lo12:tempy]
+ ldr q7, [x3, #:lo12:tempy2]
+ ldr q17, [x3, #:lo12:tempy3]
--- /dev/null
+#source: emit-relocs-311.s
+#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: b0000002 adrp x2, 11000 <tempy>
+ +10008: R_AARCH64_ADR_PREL_PG_HI21 tempy
+ +1000c: b00001a7 adrp x7, 45000 <tempy2>
+ +1000c: R_AARCH64_ADR_PREL_PG_HI21 tempy2
+ +10010: b0ffff91 adrp x17, 1000 <tempy3-0x234>
+ +10010: R_AARCH64_ADR_PREL_PG_HI21 tempy3
+ +10014: 90000083 adrp x3, 20000 <tempy[+]0xf000>
+ +10014: R_AARCH64_ADR_GOT_PAGE gempy
--- /dev/null
+.comm gempy,4,4
+.text
+ and x0,x0,x0
+ and x0,x0,#1
+ adrp x2,tempy
+ adrp x7,tempy2
+ adrp x17,tempy3
+ adrp x3,:got:gempy
--- /dev/null
+#source: emit-relocs-312.s
+#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000: 8a000000 and x0, x0, x0
+ +10004: 92400000 and x0, x0, #0x1
+ +10008: 58007fc4 ldr x4, 11000 <tempy>
+ +10008: R_AARCH64_LD_PREL_LO19 tempy
+ +1000c: 581a7fa7 ldr x7, 45000 <tempy2>
+ +1000c: R_AARCH64_LD_PREL_LO19 tempy2
+ +10010: 58f89131 ldr x17, 1234 <tempy3>
+ +10010: R_AARCH64_LD_PREL_LO19 tempy3
+ +10014: f9400843 ldr x3, \[x2.*
+ +10014: R_AARCH64_LD64_GOT_LO12_NC jempy
+ +10018: f9400444 ldr x4, \[x2.*
+ +10018: R_AARCH64_LD64_GOT_LO12_NC gempy
+ +1001c: f9400045 ldr x5, \[x2.*
+ +1001c: R_AARCH64_LD64_GOT_LO12_NC lempy
+
--- /dev/null
+.comm gempy,4
+.comm jempy,4
+.comm lempy,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ ldr x4,tempy
+ ldr x7,tempy2
+ ldr x17,tempy3
+ ldr x3, [x2, #:got_lo12:jempy]
+ ldr x4, [x2, #:got_lo12:gempy]
+ ldr x5, [x2, #:got_lo12:lempy]
--- /dev/null
+ and x0,x0,x0
+ and x0,x0,x0
+ and x0,x0,x0
+ and x0,x0,x0
+ b target
+ b target+16
--- /dev/null
+#name: aarch64-farcall-b-none-function
+#source: farcall-b-none-function.s
+#as:
+#ld: -Ttext 0x1000 --section-start .foo=0x8001000
+#error: .*\(.text\+0x0\): relocation truncated to fit: R_AARCH64_JUMP26 against symbol `bar'.*
--- /dev/null
+ .global _start
+ .global bar
+
+# We will place the section .text at 0x1000.
+
+ .text
+
+_start:
+ b bar
+ ret
+
+# We will place the section .foo at 0x8001000.
+
+ .section .foo, "xa"
+bar:
+ ret
--- /dev/null
+#name: aarch64-farcall-b
+#source: farcall-b.s
+#as:
+#ld: -Ttext 0x1000 --section-start .foo=0x8001000
+#objdump: -dr
+#...
+
+Disassembly of section .text:
+
+0000000000001000 <_start>:
+ +1000: 14000002 b 1008 <__bar_veneer>
+ +1004: d65f03c0 ret
+0000000000001008 <__bar_veneer>:
+ 1008: 90040010 adrp x16, 8001000 <bar>
+ 100c: 91000210 add x16, x16, #0x0
+ 1010: d61f0200 br x16
+ ...
+
+Disassembly of section .foo:
+
+0000000008001000 <bar>:
+ 8001000: d65f03c0 ret
--- /dev/null
+ .global _start
+ .global bar
+
+# We will place the section .text at 0x1000.
+
+ .text
+
+_start:
+ b bar
+ ret
+
+# We will place the section .foo at 0x8001000.
+
+ .section .foo, "xa"
+ .type bar, @function
+bar:
+ ret
--- /dev/null
+#name: aarch64-farcall-back
+#source: farcall-back.s
+#as:
+#ld: -Ttext 0x1000 --section-start .foo=0x100000000
+#notarget: aarch64_be-*-*
+#objdump: -dr
+#...
+
+Disassembly of section .text:
+
+0000000000001000 <_start>:
+ 1000: 14000412 b 2048 <__bar1_veneer>
+ 1004: 94000411 bl 2048 <__bar1_veneer>
+ 1008: 14000406 b 2020 <__bar2_veneer>
+ 100c: 94000405 bl 2020 <__bar2_veneer>
+ 1010: 14000408 b 2030 <__bar3_veneer>
+ 1014: 94000407 bl 2030 <__bar3_veneer>
+ 1018: d65f03c0 ret
+ ...
+
+000000000000201c <_back>:
+ 201c: d65f03c0 ret
+
+0000000000002020 <__bar2_veneer>:
+ 2020: f07ffff0 adrp x16, 100001000 <bar1\+0x1000>
+ 2024: 91002210 add x16, x16, #0x8
+ 2028: d61f0200 br x16
+ 202c: 00000000 .inst 0x00000000 ; undefined
+
+0000000000002030 <__bar3_veneer>:
+ 2030: 58000090 ldr x16, 2040 <__bar3_veneer\+0x10>
+ 2034: 10000011 adr x17, 2034 <__bar3_veneer\+0x4>
+ 2038: 8b110210 add x16, x16, x17
+ 203c: d61f0200 br x16
+ 2040: ffffffdc .word 0xffffffdc
+ 2044: 00000000 .word 0x00000000
+
+0000000000002048 <__bar1_veneer>:
+ 2048: d07ffff0 adrp x16, 100000000 <bar1>
+ 204c: 91000210 add x16, x16, #0x0
+ 2050: d61f0200 br x16
+ ...
+
+Disassembly of section .foo:
+
+0000000100000000 <bar1>:
+ 100000000: d65f03c0 ret
+ 100000004: 14000805 b 100002018 <___start_veneer>
+ ...
+
+0000000100001008 <bar2>:
+ 100001008: d65f03c0 ret
+ 10000100c: 14000403 b 100002018 <___start_veneer>
+ ...
+
+0000000100002010 <bar3>:
+ 100002010: d65f03c0 ret
+ 100002014: 14000007 b 100002030 <___back_veneer>
+
+0000000100002018 <___start_veneer>:
+ 100002018: 58000090 ldr x16, 100002028 <___start_veneer\+0x10>
+ 10000201c: 10000011 adr x17, 10000201c <___start_veneer\+0x4>
+ 100002020: 8b110210 add x16, x16, x17
+ 100002024: d61f0200 br x16
+ 100002028: ffffefe4 .word 0xffffefe4
+ 10000202c: fffffffe .word 0xfffffffe
+
+0000000100002030 <___back_veneer>:
+ 100002030: 90800010 adrp x16, 2000 <_start\+0x1000>
+ 100002034: 91007210 add x16, x16, #0x1c
+ 100002038: d61f0200 br x16
+ ...
--- /dev/null
+ .global _start
+ .global _back
+ .global bar1
+ .global bar2
+ .global bar3
+
+# We will place the section .text at 0x1000.
+
+ .text
+
+ .type _start, @function
+_start:
+ b bar1
+ bl bar1
+ b bar2
+ bl bar2
+ b bar3
+ bl bar3
+ ret
+ .space 0x1000
+ .type _back, @function
+_back: ret
+
+# We will place the section .foo at 0x8001000.
+
+ .section .foo, "xa"
+ .type bar1, @function
+bar1:
+ ret
+ b _start
+
+ .space 0x1000
+ .type bar2, @function
+bar2:
+ ret
+ b _start
+
+ .space 0x1000
+ .type bar3, @function
+bar3:
+ ret
+ b _back
--- /dev/null
+#name: aarch64-farcall-bl-none-function
+#source: farcall-bl-none-function.s
+#as:
+#ld: -Ttext 0x1000 --section-start .foo=0x8001000
+#error: .*\(.text\+0x0\): relocation truncated to fit: R_AARCH64_CALL26 against symbol `bar'.*
--- /dev/null
+ .global _start
+ .global bar
+
+# We will place the section .text at 0x1000.
+
+ .text
+
+_start:
+ bl bar
+ ret
+
+# We will place the section .foo at 0x8001000.
+
+ .section .foo, "xa"
+bar:
+ ret
--- /dev/null
+#name: aarch64-farcall-bl
+#source: farcall-bl.s
+#as:
+#ld: -Ttext 0x1000 --section-start .foo=0x8001000
+#objdump: -dr
+#...
+
+Disassembly of section .text:
+
+0000000000001000 <_start>:
+ +1000: 94000002 bl 1008 <__bar_veneer>
+ +1004: d65f03c0 ret
+
+0000000000001008 <__bar_veneer>:
+ 1008: 90040010 adrp x16, 8001000 <bar>
+ 100c: 91000210 add x16, x16, #0x0
+ 1010: d61f0200 br x16
+ ...
+
+Disassembly of section .foo:
+
+0000000008001000 <bar>:
+ 8001000: d65f03c0 ret
--- /dev/null
+ .global _start
+ .global bar
+
+# We will place the section .text at 0x1000.
+
+ .text
+
+_start:
+ bl bar
+ ret
+
+# We will place the section .foo at 0x8001000.
+
+ .section .foo, "xa"
+ .type bar, @function
+bar:
+ ret
--- /dev/null
+#name: Aarch64 farcall to symbol of type STT_SECTION
+#source: farcall-section.s
+#as:
+#ld: -Ttext 0x1000 --section-start .foo=0x8001014
+#error: .*\(.text\+0x0\): relocation truncated to fit: R_AARCH64_CALL26 against `.foo'
--- /dev/null
+# Test to ensure that an Aarch64 call exceeding 128MB generates an error
+# if the destination is of type STT_SECTION (eg non-global symbol)
+
+ .global _start
+
+# We will place the section .text at 0x1000.
+
+ .text
+
+_start:
+ bl bar
+
+# We will place the section .foo at 0x8001020.
+
+ .section .foo, "xa"
+
+bar:
+ ret
+
--- /dev/null
+#name: aarch64-limit-b
+#source: limit-b.s
+#as:
+#ld: -Ttext 0x1000 --section-start .foo=0x8000ffc
+#objdump: -dr
+#...
+
+Disassembly of section .text:
+
+0000000000001000 <_start>:
+ 1000: 15ffffff b 8000ffc <bar>
+ 1004: d65f03c0 ret
+
+Disassembly of section .foo:
+
+0000000008000ffc <bar>:
+ 8000ffc: d65f03c0 ret
--- /dev/null
+# Test maximum encoding range of b
+
+ .global _start
+ .global bar
+
+# We will place the section .text at 0x1000.
+
+ .text
+
+_start:
+ b bar
+ ret
+
+# We will place the section .foo at 0x8000ffc
+
+ .section .foo, "xa"
+ .type bar, @function
+bar:
+ ret
--- /dev/null
+#name: aarch64-limit-bl
+#source: limit-bl.s
+#as:
+#ld: -Ttext 0x1000 --section-start .foo=0x8000ffc
+#objdump: -dr
+#...
+
+Disassembly of section .text:
+
+0000000000001000 <_start>:
+ 1000: 95ffffff bl 8000ffc <bar>
+ 1004: d65f03c0 ret
+
+Disassembly of section .foo:
+
+0000000008000ffc <bar>:
+ 8000ffc: d65f03c0 ret
--- /dev/null
+# Test maximum encoding range of bl
+
+ .global _start
+ .global bar
+
+# We will place the section .text at 0x1000.
+
+ .text
+
+_start:
+ bl bar
+ ret
+
+# We will place the section .foo at 0x8000ffc
+
+ .section .foo, "xa"
+ .type bar, @function
+bar:
+ ret
--- /dev/null
+/* Script for ld testsuite */
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x8000); . = 0x10000;
+ .text :
+ {
+ *(.before)
+ *(.text)
+ *(.after)
+ } =0
+ . = 0x20000;
+ .got : { *(.got) *(.got.plt)}
+ . = 0x12340000;
+ .far : { *(.far) }
+ .ARM.attributes 0 : { *(.ARM.atttributes) }
+}
--- /dev/null
+#source: tls-desc-ie.s
+#ld: -shared -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_>
+ +10004: 91002000 add x0, x0, #0x8
+ +10008: 94000016 bl 10060 <v1\+0x10060>
+ +1000c: d503201f nop
+ +10010: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_>
+ +10014: f9400000 ldr x0, \[x0\]
+ +10018: d503201f nop
+ +1001c: d503201f nop
+ +10020: d53bd041 mrs x1, tpidr_el0
+ +10024: 8b000020 add x0, x1, x0
+ +10028: d53bd042 mrs x2, tpidr_el0
+ +1002c: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_>
+ +10030: f9400000 ldr x0, \[x0\]
+ +10034: 8b000040 add x0, x2, x0
+ +10038: b9400000 ldr w0, \[x0\]
+ +1003c: 0b000020 add w0, w1, w0
+
+Disassembly of section .plt:
+
+0000000000010040 <.plt>:
+ +10040: a9bf7bf0 stp x16, x30, \[sp,#-16\]!
+ +10044: 90000090 adrp x16, 20000 <_GLOBAL_OFFSET_TABLE_>
+ +10048: f9401611 ldr x17, \[x16,#40\]
+ +1004c: 9100a210 add x16, x16, #0x28
+ +10050: d61f0220 br x17
+ +10054: d503201f nop
+ +10058: d503201f nop
+ +1005c: d503201f nop
+ +10060: 90000090 adrp x16, 20000 <_GLOBAL_OFFSET_TABLE_>
+ +10064: f9401a11 ldr x17, \[x16,#48\]
+ +10068: 9100c210 add x16, x16, #0x30
+ +1006c: d61f0220 br x17
--- /dev/null
+ .global v1
+ .global v2
+ .section .tdata,"awT",%progbits
+v1:
+ .word 1
+
+ .text
+
+# This GD access does not relax. It consumes a double GOT slot.
+
+ adrp x0, :tlsgd:v2
+ add x0, x0, :tlsgd_lo12:v2
+ bl __tls_get_addr
+ nop
+
+# Test the combination of a TLSDESC-GD and IE access to the same
+# symbol. We expect the TLSDESC-GD to relax to IE.
+
+ adrp x0, :tlsdesc:v1
+ ldr x1, [x0, #:tlsdesc_lo12:v1]
+ add x0, x0, :tlsdesc_lo12:v1
+ .tlsdesccall v1
+ blr x1
+ mrs x1, tpidr_el0
+ add x0, x1, x0
+
+ mrs x2, tpidr_el0
+ adrp x0, :gottprel:v1
+ ldr x0, [x0, #:gottprel_lo12:v1]
+ add x0, x2, x0
+ ldr w0, [x0]
+ add w0, w1, w0
--- /dev/null
+#source: tls-relax-all.s
+#ld: -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: a9bf7bfd stp x29, x30, \[sp,#-16\]!
+ +10004: 910003fd mov x29, sp
+ +10008: 90000080 adrp x0, 20000 <ie_var\+0x1fff0>
+ +1000c: f9400000 ldr x0, \[x0\]
+ +10010: d503201f nop
+ +10014: d503201f nop
+ +10018: d53bd041 mrs x1, tpidr_el0
+ +1001c: 8b000020 add x0, x1, x0
+ +10020: b9400001 ldr w1, \[x0\]
+ +10024: d2a00000 movz x0, #0x0, lsl #16
+ +10028: f2800280 movk x0, #0x14
+ +1002c: d503201f nop
+ +10030: d503201f nop
+ +10034: d53bd042 mrs x2, tpidr_el0
+ +10038: 8b000040 add x0, x2, x0
+ +1003c: b9400000 ldr w0, \[x0\]
+ +10040: 0b000021 add w1, w1, w0
+ +10044: 90000080 adrp x0, 20000 <ie_var\+0x1fff0>
+ +10048: f9400400 ldr x0, \[x0,#8\]
+ +1004c: d53bd041 mrs x1, tpidr_el0
+ +10050: 8b000020 add x0, x1, x0
+ +10054: b9400000 ldr w0, \[x0\]
+ +10058: 0b000021 add w1, w1, w0
+ +1005c: d2a00000 movz x0, #0x0, lsl #16
+ +10060: f2800380 movk x0, #0x1c
+ +10064: d53bd041 mrs x1, tpidr_el0
+ +10068: 8b000020 add x0, x1, x0
+ +1006c: b9400000 ldr w0, \[x0\]
+ +10070: 0b000021 add w1, w1, w0
+ +10074: d53bd042 mrs x2, tpidr_el0
+ +10078: d2a00000 movz x0, #0x0, lsl #16
+ +1007c: f2800400 movk x0, #0x20
+ +10080: 8b000040 add x0, x2, x0
+ +10084: b9400000 ldr w0, \[x0\]
+ +10088: 0b000020 add w0, w1, w0
--- /dev/null
+ .global gdesc_var_1
+ .global gd_var_1
+ .section .tdata,"awT",%progbits
+gdesc_var_1:
+ .word 1
+gdesc_var_2:
+ .word 2
+gd_var_1:
+ .word 3
+gd_var_2:
+ .word 4
+ie_var:
+ .word 5
+ .text
+ stp x29, x30, [sp, -16]!
+ add x29, sp, 0
+ adrp x0, :tlsdesc:gdesc_var_1
+ ldr x1, [x0, #:tlsdesc_lo12:gdesc_var_1]
+ add x0, x0, :tlsdesc_lo12:gdesc_var_1
+ .tlsdesccall gdesc_var_1
+ blr x1
+ mrs x1, tpidr_el0
+ add x0, x1, x0
+ ldr w1, [x0]
+ adrp x0, :tlsdesc:gdesc_var_2
+ ldr x2, [x0, #:tlsdesc_lo12:gdesc_var_2]
+ add x0, x0, :tlsdesc_lo12:gdesc_var_2
+ .tlsdesccall gdesc_var_2
+ blr x2
+ mrs x2, tpidr_el0
+ add x0, x2, x0
+ ldr w0, [x0]
+ add w1, w1, w0
+ adrp x0, :tlsgd:gd_var_1
+ add x0, x0, :tlsgd_lo12:gd_var_1
+ bl __tls_get_addr
+ nop
+ ldr w0, [x0]
+ add w1, w1, w0
+ adrp x0, :tlsgd:gd_var_2
+ add x0, x0, :tlsgd_lo12:gd_var_2
+ bl __tls_get_addr
+ nop
+ ldr w0, [x0]
+ add w1, w1, w0
+ mrs x2, tpidr_el0
+ adrp x0, :gottprel:ie_var
+ ldr x0, [x0, #:gottprel_lo12:ie_var]
+ add x0, x2, x0
+ ldr w0, [x0]
+ add w0, w1, w0
--- /dev/null
+#source: tls-relax-gd-ie.s
+#ld: -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: 90000080 adrp x0, 20000 <var\+0x20000>
+ +10004: f9400000 ldr x0, \[x0\]
+ +10008: d53bd041 mrs x1, tpidr_el0
+ +1000c: 8b000020 add x0, x1, x0
+ +10010: b9400000 ldr w0, \[x0\]
--- /dev/null
+ .global var
+ .section .tdata,"awT",%progbits
+var:
+ .word 2
+ .text
+ adrp x0, :tlsgd:var
+ add x0, x0, :tlsgd_lo12:var
+ bl __tls_get_addr
+ nop
+ ldr w0, [x0]
--- /dev/null
+#source: tls-relax-gd-le.s
+#ld: -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: d2a00000 movz x0, #0x0, lsl #16
+ +10004: f2800200 movk x0, #0x10
+ +10008: d53bd041 mrs x1, tpidr_el0
+ +1000c: 8b000020 add x0, x1, x0
+ +10010: b9400000 ldr w0, \[x0\]
--- /dev/null
+ .section .tdata
+var:
+ .word 2
+ .text
+ adrp x0, :tlsgd:var
+ add x0, x0, :tlsgd_lo12:var
+ bl __tls_get_addr
+ nop
+ ldr w0, [x0]
--- /dev/null
+#source: tls-relax-gdesc-ie-2.s
+#ld: -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: 90000080 adrp x0, 20000 <var\+0x20000>
+ +10004: d503201f nop
+ +10008: f9400000 ldr x0, \[x0\]
+ +1000c: d503201f nop
+ +10010: d503201f nop
+ +10014: d503201f nop
+ +10018: d503201f nop
+ +1001c: d503201f nop
+ +10020: d503201f nop
+ +10024: d503201f nop
+ +10028: d503201f nop
+ +1002c: d53bd041 mrs x1, tpidr_el0
+ +10030: 8b000020 add x0, x1, x0
+ +10034: b9400000 ldr w0, \[x0\]
--- /dev/null
+// Test TLS Desc to TLS IE relaxation when instructions are not consecutive.
+
+ .global var
+ .section .tdata
+var:
+ .word 2
+ .text
+ adrp x0, :tlsdesc:var
+ nop
+ ldr x1, [x0, #:tlsdesc_lo12:var]
+ nop
+ nop
+ nop
+ add x0, x0, :tlsdesc_lo12:var
+ nop
+ nop
+ .tlsdesccall var
+ blr x1
+ nop
+ mrs x1, tpidr_el0
+ add x0, x1, x0
+ ldr w0, [x0]
+ .global var
+ .section .tdata
--- /dev/null
+#source: tls-relax-gdesc-ie.s
+#ld: -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: 90000080 adrp x0, 20000 <var\+0x20000>
+ +10004: f9400000 ldr x0, \[x0\]
+ +10008: d503201f nop
+ +1000c: d503201f nop
+ +10010: d53bd041 mrs x1, tpidr_el0
+ +10014: 8b000020 add x0, x1, x0
+ +10018: b9400000 ldr w0, \[x0\]
--- /dev/null
+ .global var
+ .section .tdata
+var:
+ .word 2
+ .text
+ adrp x0, :tlsdesc:var
+ ldr x1, [x0, #:tlsdesc_lo12:var]
+ add x0, x0, :tlsdesc_lo12:var
+ .tlsdesccall var
+ blr x1
+ mrs x1, tpidr_el0
+ add x0, x1, x0
+ ldr w0, [x0]
--- /dev/null
+#source: tls-relax-gdesc-le-2.s
+#ld: -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: d2a00000 movz x0, #0x0, lsl #16
+ +10004: d503201f nop
+ +10008: d503201f nop
+ +1000c: f2800200 movk x0, #0x10
+ +10010: d503201f nop
+ +10014: d503201f nop
+ +10018: d503201f nop
+ +1001c: d503201f nop
+ +10020: d503201f nop
+ +10024: d503201f nop
+ +10028: d503201f nop
+ +1002c: d53bd041 mrs x1, tpidr_el0
+ +10030: 8b000020 add x0, x1, x0
+ +10034: b9400000 ldr w0, \[x0\]
--- /dev/null
+# Test TLS Desc to TLS LE relaxation when instructions are not consecutive.
+
+ .section .tdata
+var:
+ .word 2
+ .text
+ adrp x0, :tlsdesc:var
+ nop
+ nop
+ ldr x1, [x0, #:tlsdesc_lo12:var]
+ nop
+ add x0, x0, :tlsdesc_lo12:var
+ nop
+ nop
+ nop
+ .tlsdesccall var
+ blr x1
+ nop
+ mrs x1, tpidr_el0
+ add x0, x1, x0
+ ldr w0, [x0]
+ .section .tdata
--- /dev/null
+#source: tls-relax-gdesc-le.s
+#ld: -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: d2a00000 movz x0, #0x0, lsl #16
+ +10004: f2800200 movk x0, #0x10
+ +10008: d503201f nop
+ +1000c: d503201f nop
+ +10010: d53bd041 mrs x1, tpidr_el0
+ +10014: 8b000020 add x0, x1, x0
+ +10018: b9400000 ldr w0, \[x0\]
--- /dev/null
+ .section .tdata
+var:
+ .word 2
+ .text
+ adrp x0, :tlsdesc:var
+ ldr x1, [x0, #:tlsdesc_lo12:var]
+ add x0, x0, :tlsdesc_lo12:var
+ .tlsdesccall var
+ blr x1
+ mrs x1, tpidr_el0
+ add x0, x1, x0
+ ldr w0, [x0]
--- /dev/null
+#source: tls-relax-ie-le-2.s
+#ld: -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: d53bd041 mrs x1, tpidr_el0
+ +10004: d503201f nop
+ +10008: d503201f nop
+ +1000c: d2a00000 movz x0, #0x0, lsl #16
+ +10010: d503201f nop
+ +10014: d503201f nop
+ +10018: d503201f nop
+ +1001c: f2800200 movk x0, #0x10
+ +10020: d503201f nop
+ +10024: 8b000020 add x0, x1, x0
+ +10028: d503201f nop
+ +1002c: d503201f nop
+ +10030: b9400000 ldr w0, \[x0\]
--- /dev/null
+# Test TLS IE to TLS LE relaxation when instructions are not consecutive.
+
+ .section .tdata
+var:
+ .word 2
+ .text
+ mrs x1, tpidr_el0
+ nop
+ nop
+ adrp x0, :gottprel:var
+ nop
+ nop
+ nop
+ ldr x0, [x0, #:gottprel_lo12:var]
+ nop
+ add x0, x1, x0
+ nop
+ nop
+ ldr w0, [x0]
+ .section .tdata
--- /dev/null
+#source: tls-relax-ie-le-3.s
+#ld: -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: d53bd042 mrs x2, tpidr_el0
+ +10004: d2a0000f movz x15, #0x0, lsl #16
+ +10008: f280020f movk x15, #0x10
+ +1000c: 8b0f004f add x15, x2, x15
+ +10010: b94001e0 ldr w0, \[x15\]
--- /dev/null
+# Test TLS IE to TLS LE relaxation when using arbitrary registers.
+
+ .section .tdata
+var:
+ .word 2
+ .text
+ mrs x2, tpidr_el0
+ adrp x15, :gottprel:var
+ ldr x15, [x15, #:gottprel_lo12:var]
+ add x15, x2, x15
+ ldr w0, [x15]
+ .section .tdata
--- /dev/null
+#source: tls-relax-ie-le.s
+#ld: -T relocs.ld -e0
+#objdump: -dr
+#...
+ +10000: d53bd041 mrs x1, tpidr_el0
+ +10004: d2a00000 movz x0, #0x0, lsl #16
+ +10008: f2800200 movk x0, #0x10
+ +1000c: 8b000020 add x0, x1, x0
+ +10010: b9400000 ldr w0, \[x0\]
--- /dev/null
+ .section .tdata
+var:
+ .word 2
+ .text
+ mrs x1, tpidr_el0
+ adrp x0, :gottprel:var
+ ldr x0, [x0, #:gottprel_lo12:var]
+ add x0, x1, x0
+ ldr w0, [x0]
--- /dev/null
+#source: weak-undefined.s
+#ld: -Ttext 0xF0000000 -T relocs.ld -e0 --emit-relocs
+#objdump: -d
+#...
+ +f0000000: 54000001 b\.ne f0000000 <main>
+ +f0000004: 54000000 b\.eq f0000004 <main\+0x4>
+ +f0000008: 54000002 b\.cs f0000008 <main\+0x8>
+ +f000000c: 54000003 b\.cc f000000c <main\+0xc>
+ +f0000010: 5400000c b\.gt f0000010 <main\+0x10>
+ +f0000014: 5400000a b\.ge f0000014 <main\+0x14>
+ +f0000018: 5400000b b\.lt f0000018 <main\+0x18>
+ +f000001c: 5400000d b\.le f000001c <main\+0x1c>
+ +f0000020: d503201f nop
+ +f0000024: d503201f nop
+ +f0000028: 58000000 ldr x0, f0000028 <main\+0x28>
+ +f000002c: 10000000 adr x0, f000002c <main\+0x2c>
+ +f0000030: 90000000 adrp x0, f0000000 <main>
+ +f0000034: 91000000 add x0, x0, #0x0
--- /dev/null
+.text
+ .weak foo
+ .global main
+main:
+ b.ne foo
+ b.eq foo
+ b.cs foo
+ b.cc foo
+ b.gt foo
+ b.ge foo
+ b.lt foo
+ b.le foo
+ b foo
+ bl foo
+ ldr x0, foo
+ adr x0, foo
+ adrp x0, foo
+ add x0, x0, :lo12:foo
return
}
-proc binutils_test { prog_name ld_options test } {
+# The optional test_name argument provides a mechanism for the caller
+# to hardwire the test name. This is important if ld_options contains
+# absolute path names because the default test name is constructed
+# from the prog_name and ld_options and we do not want absolute paths
+# to appear in the test_name.
+proc binutils_test { prog_name ld_options test {test_name ""}} {
global as
global ld
global READELF
global link_output
eval set prog \$$prog_name
- set test_name "$prog_name $ld_options ($test)"
+
+ if { "$test_name" == "" } {
+ set test_name "$prog_name $ld_options ($test)"
+ }
if { ![ld_assemble $as $srcdir/$subdir/$test.s tmpdir/$test.o ] } {
unresolved "$test_name"
binutils_test objcopy "-z relro -shared" relro2
}
-binutils_test strip "-T ${srcdir}/${subdir}/lma.lnk" lma
+binutils_test strip "-T ${srcdir}/${subdir}/lma.lnk" lma "strip -T lma.lnk"
set tls_tests { "tdata1" "tdata2" }
# hppa64 has its own .tbss section, with different flags.
#source: group8.s
#ld: -r --gc-sections --entry foo
#readelf: -g --wide
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#source: group8.s
#ld: -r --gc-sections --entry bar
#readelf: -g --wide
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#source: group9.s
#ld: -r --gc-sections --entry foo
#readelf: -g --wide
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: alpha-*-* hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#source: group9.s
#ld: -r --gc-sections --entry bar
#readelf: -g --wide
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: alpha-*-* hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#source: start.s
#ld: --gc-sections
#readelf: -s --wide
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#ld: --gc-sections -shared -version-script pr12975.t
#readelf: -s --wide
#target: *-*-linux* *-*-gnu*
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#ld: --gc-sections -shared
#readelf: -s -D --wide
#target: *-*-linux* *-*-gnu*
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#ld: --gc-sections -shared -version-script pr13195.t
#readelf: -s --wide -D
#target: *-*-linux* *-*-gnu*
-#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
+#notarget: aarch64*-*-* arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
&& ![istarget sparc*-*-elf]
&& ![istarget sparc*-*-solaris2*]
&& ![istarget sparc*-*-linux*]
+ && ![istarget aarch64*-*-linux*]
&& ![istarget arm*-*-linux*]
&& ![istarget mips*-*-linux*]
&& ![istarget alpha*-*-linux*]
ld_compile "$CC $CFLAGS $cflags" $srcdir/$subdir/pr13683.c tmpdir/pr13683.o
run_dump_test "pr13683"
}
+
+if { [is_remote host] || [which $CC] != 0 } {
+ ld_compile "$CC $CFLAGS $cflags" $srcdir/$subdir/pr14265.c tmpdir/pr14265.o
+ run_dump_test "pr14265"
+}
+
&& ![istarget rs6000*-*-aix*] \
&& ![istarget powerpc*-*-aix*] \
&& ![istarget s390*-*-linux*] \
+ && ![istarget aarch64*-*-linux*] \
&& ![istarget x86_64-*-linux*] } {
return
}
setup_xfail "sh64*-*-*"
}
- if {[istarget arm*-*-*]} {
- # ARM targets cannot convert format in the linker
+ if {[istarget aarch64*-*-*] || \
+ [istarget arm*-*-*]} {
+ # ARM targets cannot convert format in the linker
# using the --oformat command line switch
+ setup_xfail "aarch64-*-*"
+ setup_xfail "aarch64_be-*-*"
setup_xfail "arm*-*-*"
}
if {![info exists gc_sections_available_saved]} {
# Some targets don't support gc-sections despite whatever's
# advertised by ld's options.
- if {[istarget arc-*-*]
+ if {[istarget aarch64*-*-*]
+ || [istarget arc-*-*]
|| [istarget d30v-*-*]
|| [istarget dlx-*-*]
|| [istarget i960-*-*]
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64.
+ * Makefile.in: Regenerate.
+ * aarch64-asm.c: New file.
+ * aarch64-asm.h: New file.
+ * aarch64-dis.c: New file.
+ * aarch64-dis.h: New file.
+ * aarch64-gen.c: New file.
+ * aarch64-opc.c: New file.
+ * aarch64-opc.h: New file.
+ * aarch64-tbl.h: New file.
+ * configure.in: Add AArch64.
+ * configure: Regenerate.
+ * disassemble.c: Add AArch64.
+ * aarch64-asm-2.c: New file (automatically generated).
+ * aarch64-dis-2.c: New file (automatically generated).
+ * aarch64-opc-2.c: New file (automatically generated).
+ * po/POTFILES.in: Regenerate.
+
2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c (micromips_opcodes): Update comment.
# Header files.
HFILES = \
+ aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
# C source files that correspond to .o's ending up in libopcodes
# for all machines.
TARGET_LIBOPCODES_CFILES = \
+ aarch64-asm.c \
+ aarch64-asm-2.c \
+ aarch64-dis.c \
+ aarch64-dis-2.c \
+ aarch64-opc.c \
+ aarch64-opc-2.c \
alpha-dis.c \
alpha-opc.c \
arc-dis.c \
# C source files that correspond to .o's.
CFILES = \
$(LIBOPCODES_CFILES) \
+ aarch64-gen.c \
i386-gen.c \
ia64-asmtab.c \
ia64-gen.c \
$(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \
archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles=
-MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_BUILD) ia64-gen$(EXEEXT_FOR_BUILD) \
- s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab z8kgen$(EXEEXT_FOR_BUILD) \
- opc2c$(EXEEXT_FOR_BUILD)
+MOSTLYCLEANFILES = aarch64-gen$(EXEEXT_FOR_BUILD) i386-gen$(EXEEXT_FOR_BUILD) \
+ ia64-gen$(EXEEXT_FOR_BUILD) s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab \
+ z8kgen$(EXEEXT_FOR_BUILD) opc2c$(EXEEXT_FOR_BUILD)
-MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
+MAINTAINERCLEANFILES = $(srcdir)/aarch64-asm-2.c $(srcdir)/aarch64-dis-2.c \
+ $(srcdir)/aarch64-opc-2.c $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
$(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \
$(srcdir)/rl78-decode.c \
$(srcdir)/rx-decode.c
+aarch64-gen$(EXEEXT_FOR_BUILD): aarch64-gen.o $(BUILD_LIB_DEPS)
+ $(LINK_FOR_BUILD) aarch64-gen.o $(BUILD_LIBS)
+
+aarch64-gen.o: aarch64-gen.c $(BFD_H) $(INCDIR)/getopt.h $(INCDIR)/libiberty.h\
+ $(INCDIR)/opcode/aarch64.h config.h aarch64-opc.h aarch64-tbl.h
+ $(COMPILE_FOR_BUILD) -c $(srcdir)/aarch64-gen.c
+
+$(srcdir)/aarch64-asm-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-asm > $@
+$(srcdir)/aarch64-dis-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-dis > $@
+$(srcdir)/aarch64-opc-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-opc > $@
+
i386-gen$(EXEEXT_FOR_BUILD): i386-gen.o $(BUILD_LIB_DEPS)
$(LINK_FOR_BUILD) i386-gen.o $(BUILD_LIBS)
# Header files.
HFILES = \
+ aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
# C source files that correspond to .o's ending up in libopcodes
# for all machines.
TARGET_LIBOPCODES_CFILES = \
+ aarch64-asm.c \
+ aarch64-asm-2.c \
+ aarch64-dis.c \
+ aarch64-dis-2.c \
+ aarch64-opc.c \
+ aarch64-opc-2.c \
alpha-dis.c \
alpha-opc.c \
arc-dis.c \
# C source files that correspond to .o's.
CFILES = \
$(LIBOPCODES_CFILES) \
+ aarch64-gen.c \
i386-gen.c \
ia64-asmtab.c \
ia64-gen.c \
@CGEN_MAINT_TRUE@XC16X_DEPS = stamp-xc16x
@CGEN_MAINT_FALSE@XSTORMY16_DEPS =
@CGEN_MAINT_TRUE@XSTORMY16_DEPS = stamp-xstormy16
-MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_BUILD) ia64-gen$(EXEEXT_FOR_BUILD) \
- s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab z8kgen$(EXEEXT_FOR_BUILD) \
- opc2c$(EXEEXT_FOR_BUILD)
+MOSTLYCLEANFILES = aarch64-gen$(EXEEXT_FOR_BUILD) i386-gen$(EXEEXT_FOR_BUILD) \
+ ia64-gen$(EXEEXT_FOR_BUILD) s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab \
+ z8kgen$(EXEEXT_FOR_BUILD) opc2c$(EXEEXT_FOR_BUILD)
-MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
+MAINTAINERCLEANFILES = $(srcdir)/aarch64-asm-2.c $(srcdir)/aarch64-dis-2.c \
+ $(srcdir)/aarch64-opc-2.c $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
$(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \
$(srcdir)/rl78-decode.c \
$(srcdir)/rx-decode.c
distclean-compile:
-rm -f *.tab.c
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-asm-2.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-asm.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-dis-2.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-opc-2.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/alpha-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/alpha-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-dis.Plo@am__quote@
$(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \
archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles=
+aarch64-gen$(EXEEXT_FOR_BUILD): aarch64-gen.o $(BUILD_LIB_DEPS)
+ $(LINK_FOR_BUILD) aarch64-gen.o $(BUILD_LIBS)
+
+aarch64-gen.o: aarch64-gen.c $(BFD_H) $(INCDIR)/getopt.h $(INCDIR)/libiberty.h\
+ $(INCDIR)/opcode/aarch64.h config.h aarch64-opc.h aarch64-tbl.h
+ $(COMPILE_FOR_BUILD) -c $(srcdir)/aarch64-gen.c
+
+$(srcdir)/aarch64-asm-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-asm > $@
+$(srcdir)/aarch64-dis-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-dis > $@
+$(srcdir)/aarch64-opc-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+ ./aarch64-gen$(exeext_for_build) --gen-opc > $@
+
i386-gen$(EXEEXT_FOR_BUILD): i386-gen.o $(BUILD_LIB_DEPS)
$(LINK_FOR_BUILD) i386-gen.o $(BUILD_LIBS)
--- /dev/null
+/* This file is automatically generated by aarch64-gen. Do not edit! */
+/* Copyright 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include "aarch64-asm.h"
+
+
+const aarch64_opcode *
+aarch64_find_real_opcode (const aarch64_opcode *opcode)
+{
+ /* Use the index as the key to locate the real opcode. */
+ int key = opcode - aarch64_opcode_table;
+ int value;
+ switch (key)
+ {
+ case 3: /* ngc */
+ value = 2; /* --> sbc. */
+ break;
+ case 5: /* ngcs */
+ value = 4; /* --> sbcs. */
+ break;
+ case 8: /* cmn */
+ value = 7; /* --> adds. */
+ break;
+ case 11: /* cmp */
+ value = 10; /* --> subs. */
+ break;
+ case 13: /* mov */
+ value = 12; /* --> add. */
+ break;
+ case 15: /* cmn */
+ value = 14; /* --> adds. */
+ break;
+ case 18: /* cmp */
+ value = 17; /* --> subs. */
+ break;
+ case 21: /* cmn */
+ value = 20; /* --> adds. */
+ break;
+ case 23: /* neg */
+ value = 22; /* --> sub. */
+ break;
+ case 26: /* negs */
+ case 25: /* cmp */
+ value = 24; /* --> subs. */
+ break;
+ case 139: /* mov */
+ value = 138; /* --> umov. */
+ break;
+ case 141: /* mov */
+ value = 140; /* --> ins. */
+ break;
+ case 143: /* mov */
+ value = 142; /* --> ins. */
+ break;
+ case 204: /* mvn */
+ value = 203; /* --> not. */
+ break;
+ case 259: /* mov */
+ value = 258; /* --> orr. */
+ break;
+ case 427: /* mov */
+ value = 426; /* --> dup. */
+ break;
+ case 494: /* sxtw */
+ case 493: /* sxth */
+ case 492: /* sxtb */
+ case 495: /* asr */
+ case 491: /* sbfx */
+ case 490: /* sbfiz */
+ value = 489; /* --> sbfm. */
+ break;
+ case 498: /* bfxil */
+ case 497: /* bfi */
+ value = 496; /* --> bfm. */
+ break;
+ case 503: /* uxth */
+ case 502: /* uxtb */
+ case 505: /* lsr */
+ case 504: /* lsl */
+ case 501: /* ubfx */
+ case 500: /* ubfiz */
+ value = 499; /* --> ubfm. */
+ break;
+ case 523: /* cset */
+ case 522: /* cinc */
+ value = 521; /* --> csinc. */
+ break;
+ case 526: /* csetm */
+ case 525: /* cinv */
+ value = 524; /* --> csinv. */
+ break;
+ case 528: /* cneg */
+ value = 527; /* --> csneg. */
+ break;
+ case 553: /* lsl */
+ value = 552; /* --> lslv. */
+ break;
+ case 555: /* lsr */
+ value = 554; /* --> lsrv. */
+ break;
+ case 557: /* asr */
+ value = 556; /* --> asrv. */
+ break;
+ case 559: /* ror */
+ value = 558; /* --> rorv. */
+ break;
+ case 561: /* mul */
+ value = 560; /* --> madd. */
+ break;
+ case 563: /* mneg */
+ value = 562; /* --> msub. */
+ break;
+ case 565: /* smull */
+ value = 564; /* --> smaddl. */
+ break;
+ case 567: /* smnegl */
+ value = 566; /* --> smsubl. */
+ break;
+ case 570: /* umull */
+ value = 569; /* --> umaddl. */
+ break;
+ case 572: /* umnegl */
+ value = 571; /* --> umsubl. */
+ break;
+ case 583: /* ror */
+ value = 582; /* --> extr. */
+ break;
+ case 683: /* strb */
+ value = 681; /* --> sturb. */
+ break;
+ case 684: /* ldrb */
+ value = 682; /* --> ldurb. */
+ break;
+ case 686: /* ldrsb */
+ value = 685; /* --> ldursb. */
+ break;
+ case 689: /* str */
+ value = 687; /* --> stur. */
+ break;
+ case 690: /* ldr */
+ value = 688; /* --> ldur. */
+ break;
+ case 693: /* strh */
+ value = 691; /* --> sturh. */
+ break;
+ case 694: /* ldrh */
+ value = 692; /* --> ldurh. */
+ break;
+ case 696: /* ldrsh */
+ value = 695; /* --> ldursh. */
+ break;
+ case 699: /* str */
+ value = 697; /* --> stur. */
+ break;
+ case 700: /* ldr */
+ value = 698; /* --> ldur. */
+ break;
+ case 702: /* ldrsw */
+ value = 701; /* --> ldursw. */
+ break;
+ case 704: /* prfm */
+ value = 703; /* --> prfum. */
+ break;
+ case 746: /* bic */
+ value = 745; /* --> and. */
+ break;
+ case 748: /* mov */
+ value = 747; /* --> orr. */
+ break;
+ case 751: /* tst */
+ value = 750; /* --> ands. */
+ break;
+ case 756: /* uxtw */
+ case 755: /* mov */
+ value = 754; /* --> orr. */
+ break;
+ case 758: /* mvn */
+ value = 757; /* --> orn. */
+ break;
+ case 762: /* tst */
+ value = 761; /* --> ands. */
+ break;
+ case 765: /* mov */
+ value = 764; /* --> movn. */
+ break;
+ case 767: /* mov */
+ value = 766; /* --> movz. */
+ break;
+ case 778: /* sevl */
+ case 777: /* sev */
+ case 776: /* wfi */
+ case 775: /* wfe */
+ case 774: /* yield */
+ case 773: /* nop */
+ value = 772; /* --> hint. */
+ break;
+ case 787: /* tlbi */
+ case 786: /* ic */
+ case 785: /* dc */
+ case 784: /* at */
+ value = 783; /* --> sys. */
+ break;
+ default: return NULL;
+ }
+
+ return aarch64_opcode_table + value;
+}
+
+const char*
+aarch64_insert_operand (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code, const aarch64_inst *inst)
+{
+ /* Use the index as the key. */
+ int key = self - aarch64_operands;
+ switch (key)
+ {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 18:
+ case 19:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 24:
+ case 25:
+ case 26:
+ case 34:
+ case 35:
+ return aarch64_ins_regno (self, info, code, inst);
+ case 11:
+ return aarch64_ins_reg_extended (self, info, code, inst);
+ case 12:
+ return aarch64_ins_reg_shifted (self, info, code, inst);
+ case 17:
+ return aarch64_ins_ft (self, info, code, inst);
+ case 27:
+ case 28:
+ case 29:
+ return aarch64_ins_reglane (self, info, code, inst);
+ case 30:
+ return aarch64_ins_reglist (self, info, code, inst);
+ case 31:
+ return aarch64_ins_ldst_reglist (self, info, code, inst);
+ case 32:
+ return aarch64_ins_ldst_reglist_r (self, info, code, inst);
+ case 33:
+ return aarch64_ins_ldst_elemlist (self, info, code, inst);
+ case 36:
+ case 45:
+ case 46:
+ case 47:
+ case 48:
+ case 49:
+ case 50:
+ case 51:
+ case 52:
+ case 53:
+ case 54:
+ case 55:
+ case 56:
+ case 57:
+ case 65:
+ case 66:
+ case 67:
+ case 68:
+ return aarch64_ins_imm (self, info, code, inst);
+ case 37:
+ case 38:
+ return aarch64_ins_advsimd_imm_shift (self, info, code, inst);
+ case 39:
+ case 40:
+ case 41:
+ return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
+ case 58:
+ return aarch64_ins_limm (self, info, code, inst);
+ case 59:
+ return aarch64_ins_aimm (self, info, code, inst);
+ case 60:
+ return aarch64_ins_imm_half (self, info, code, inst);
+ case 61:
+ return aarch64_ins_fbits (self, info, code, inst);
+ case 63:
+ return aarch64_ins_cond (self, info, code, inst);
+ case 69:
+ case 75:
+ return aarch64_ins_addr_simple (self, info, code, inst);
+ case 70:
+ return aarch64_ins_addr_regoff (self, info, code, inst);
+ case 71:
+ case 72:
+ case 73:
+ return aarch64_ins_addr_simm (self, info, code, inst);
+ case 74:
+ return aarch64_ins_addr_uimm12 (self, info, code, inst);
+ case 76:
+ return aarch64_ins_simd_addr_post (self, info, code, inst);
+ case 77:
+ return aarch64_ins_sysreg (self, info, code, inst);
+ case 78:
+ return aarch64_ins_pstatefield (self, info, code, inst);
+ case 79:
+ case 80:
+ case 81:
+ case 82:
+ return aarch64_ins_sysins_op (self, info, code, inst);
+ case 83:
+ case 84:
+ return aarch64_ins_barrier (self, info, code, inst);
+ case 85:
+ return aarch64_ins_prfop (self, info, code, inst);
+ default: assert (0); abort ();
+ }
+}
--- /dev/null
+/* aarch64-asm.c -- AArch64 assembler support.
+ Copyright 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include <stdarg.h>
+#include "aarch64-asm.h"
+
+/* Utilities. */
+
+/* The unnamed arguments consist of the number of fields and information about
+ these fields where the VALUE will be inserted into CODE. MASK can be zero or
+ the base mask of the opcode.
+
+ N.B. the fields are required to be in such an order than the least signficant
+ field for VALUE comes the first, e.g. the <index> in
+ SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
+ is encoded in H:L:M in some cases, the the fields H:L:M should be passed in
+ the order of M, L, H. */
+
+static inline void
+insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...)
+{
+ uint32_t num;
+ const aarch64_field *field;
+ enum aarch64_field_kind kind;
+ va_list va;
+
+ va_start (va, mask);
+ num = va_arg (va, uint32_t);
+ assert (num <= 5);
+ while (num--)
+ {
+ kind = va_arg (va, enum aarch64_field_kind);
+ field = &fields[kind];
+ insert_field (kind, code, value, mask);
+ value >>= field->width;
+ }
+ va_end (va);
+}
+
+/* Operand inserters. */
+
+/* Insert register number. */
+const char *
+aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ insert_field (self->fields[0], code, info->reg.regno, 0);
+ return NULL;
+}
+
+/* Insert register number, index and/or other data for SIMD register element
+ operand, e.g. the last source operand in
+ SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
+const char *
+aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
+ aarch64_insn *code, const aarch64_inst *inst)
+{
+ /* regno */
+ insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask);
+ /* index and/or type */
+ if (inst->opcode->iclass == asisdone || inst->opcode->iclass == asimdins)
+ {
+ int pos = info->qualifier - AARCH64_OPND_QLF_S_B;
+ if (info->type == AARCH64_OPND_En
+ && inst->opcode->operands[0] == AARCH64_OPND_Ed)
+ {
+ /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
+ assert (info->idx == 1); /* Vn */
+ aarch64_insn value = info->reglane.index << pos;
+ insert_field (FLD_imm4, code, value, 0);
+ }
+ else
+ {
+ /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
+ imm5<3:0> <V>
+ 0000 RESERVED
+ xxx1 B
+ xx10 H
+ x100 S
+ 1000 D */
+ aarch64_insn value = ((info->reglane.index << 1) | 1) << pos;
+ insert_field (FLD_imm5, code, value, 0);
+ }
+ }
+ else
+ {
+ /* index for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
+ or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
+ switch (info->qualifier)
+ {
+ case AARCH64_OPND_QLF_S_H:
+ /* H:L:M */
+ insert_fields (code, info->reglane.index, 0, 3, FLD_M, FLD_L, FLD_H);
+ break;
+ case AARCH64_OPND_QLF_S_S:
+ /* H:L */
+ insert_fields (code, info->reglane.index, 0, 2, FLD_L, FLD_H);
+ break;
+ case AARCH64_OPND_QLF_S_D:
+ /* H */
+ insert_field (FLD_H, code, info->reglane.index, 0);
+ break;
+ default:
+ assert (0);
+ }
+ }
+ return NULL;
+}
+
+/* Insert regno and len field of a register list operand, e.g. Vn in TBL. */
+const char *
+aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* R */
+ insert_field (self->fields[0], code, info->reglist.first_regno, 0);
+ /* len */
+ insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);
+ return NULL;
+}
+
+/* Insert Rt and opcode fields for a register list operand, e.g. Vt
+ in AdvSIMD load/store instructions. */
+const char *
+aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst)
+{
+ aarch64_insn value;
+ /* Number of elements in each structure to be loaded/stored. */
+ unsigned num = get_opcode_dependent_value (inst->opcode);
+
+ /* Rt */
+ insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
+ /* opcode */
+ switch (num)
+ {
+ case 1:
+ switch (info->reglist.num_regs)
+ {
+ case 1: value = 0x7; break;
+ case 2: value = 0xa; break;
+ case 3: value = 0x6; break;
+ case 4: value = 0x2; break;
+ default: assert (0);
+ }
+ break;
+ case 2:
+ value = info->reglist.num_regs == 4 ? 0x3 : 0x8;
+ break;
+ case 3:
+ value = 0x4;
+ break;
+ case 4:
+ value = 0x0;
+ break;
+ default:
+ assert (0);
+ }
+ insert_field (FLD_opcode, code, value, 0);
+
+ return NULL;
+}
+
+/* Insert Rt and S fields for a register list operand, e.g. Vt in AdvSIMD load
+ single structure to all lanes instructions. */
+const char *
+aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst)
+{
+ aarch64_insn value;
+ /* The opcode dependent area stores the number of elements in
+ each structure to be loaded/stored. */
+ int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1;
+
+ /* Rt */
+ insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
+ /* S */
+ value = (aarch64_insn) 0;
+ if (is_ld1r && info->reglist.num_regs == 2)
+ /* OP_LD1R does not have alternating variant, but have "two consecutive"
+ instead. */
+ value = (aarch64_insn) 1;
+ insert_field (FLD_S, code, value, 0);
+
+ return NULL;
+}
+
+/* Insert Q, opcode<2:1>, S, size and Rt fields for a register element list
+ operand e.g. Vt in AdvSIMD load/store single element instructions. */
+const char *
+aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ aarch64_field field = {0, 0};
+ aarch64_insn QSsize; /* fields Q:S:size. */
+ aarch64_insn opcodeh2; /* opcode<2:1> */
+
+ assert (info->reglist.has_index);
+
+ /* Rt */
+ insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
+ /* Encode the index, opcode<2:1> and size. */
+ switch (info->qualifier)
+ {
+ case AARCH64_OPND_QLF_S_B:
+ /* Index encoded in "Q:S:size". */
+ QSsize = info->reglist.index;
+ opcodeh2 = 0x0;
+ break;
+ case AARCH64_OPND_QLF_S_H:
+ /* Index encoded in "Q:S:size<1>". */
+ QSsize = info->reglist.index << 1;
+ opcodeh2 = 0x1;
+ break;
+ case AARCH64_OPND_QLF_S_S:
+ /* Index encoded in "Q:S". */
+ QSsize = info->reglist.index << 2;
+ opcodeh2 = 0x2;
+ break;
+ case AARCH64_OPND_QLF_S_D:
+ /* Index encoded in "Q". */
+ QSsize = info->reglist.index << 3 | 0x1;
+ opcodeh2 = 0x2;
+ break;
+ default:
+ assert (0);
+ }
+ insert_fields (code, QSsize, 0, 3, FLD_vldst_size, FLD_S, FLD_Q);
+ gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
+ insert_field_2 (&field, code, opcodeh2, 0);
+
+ return NULL;
+}
+
+/* Insert fields immh:immb and/or Q for e.g. the shift immediate in
+ SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
+ or SSHR <V><d>, <V><n>, #<shift>. */
+const char *
+aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code, const aarch64_inst *inst)
+{
+ unsigned val = aarch64_get_qualifier_standard_value (info->qualifier);
+ aarch64_insn Q, imm;
+
+ if (inst->opcode->iclass == asimdshf)
+ {
+ /* Q
+ immh Q <T>
+ 0000 x SEE AdvSIMD modified immediate
+ 0001 0 8B
+ 0001 1 16B
+ 001x 0 4H
+ 001x 1 8H
+ 01xx 0 2S
+ 01xx 1 4S
+ 1xxx 0 RESERVED
+ 1xxx 1 2D */
+ Q = (val & 0x1) ? 1 : 0;
+ insert_field (FLD_Q, code, Q, inst->opcode->mask);
+ val >>= 1;
+ }
+
+ assert (info->type == AARCH64_OPND_IMM_VLSR
+ || info->type == AARCH64_OPND_IMM_VLSL);
+
+ if (info->type == AARCH64_OPND_IMM_VLSR)
+ /* immh:immb
+ immh <shift>
+ 0000 SEE AdvSIMD modified immediate
+ 0001 (16-UInt(immh:immb))
+ 001x (32-UInt(immh:immb))
+ 01xx (64-UInt(immh:immb))
+ 1xxx (128-UInt(immh:immb)) */
+ imm = (16 << (unsigned)val) - info->imm.value;
+ else
+ /* immh:immb
+ immh <shift>
+ 0000 SEE AdvSIMD modified immediate
+ 0001 (UInt(immh:immb)-8)
+ 001x (UInt(immh:immb)-16)
+ 01xx (UInt(immh:immb)-32)
+ 1xxx (UInt(immh:immb)-64) */
+ imm = info->imm.value + (8 << (unsigned)val);
+ insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh);
+
+ return NULL;
+}
+
+/* Insert fields for e.g. the immediate operands in
+ BFM <Wd>, <Wn>, #<immr>, #<imms>. */
+const char *
+aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ int64_t imm;
+ /* Maximum of two fields to insert. */
+ assert (self->fields[2] == FLD_NIL);
+
+ imm = info->imm.value;
+ if (operand_need_shift_by_two (self))
+ imm >>= 2;
+ if (self->fields[1] == FLD_NIL)
+ insert_field (self->fields[0], code, imm, 0);
+ else
+ /* e.g. TBZ b5:b40. */
+ insert_fields (code, imm, 0, 2, self->fields[1], self->fields[0]);
+ return NULL;
+}
+
+/* Insert immediate and its shift amount for e.g. the last operand in
+ MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
+const char *
+aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* imm16 */
+ aarch64_ins_imm (self, info, code, inst);
+ /* hw */
+ insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);
+ return NULL;
+}
+
+/* Insert cmode and "a:b:c:d:e:f:g:h" fields for e.g. the last operand in
+ MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
+const char *
+aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
+ uint64_t imm = info->imm.value;
+ enum aarch64_modifier_kind kind = info->shifter.kind;
+ int amount = info->shifter.amount;
+ aarch64_field field = {0, 0};
+
+ /* a:b:c:d:e:f:g:h */
+ if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8)
+ {
+ /* Either MOVI <Dd>, #<imm>
+ or MOVI <Vd>.2D, #<imm>.
+ <imm> is a 64-bit immediate
+ "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
+ encoded in "a:b:c:d:e:f:g:h". */
+ imm = aarch64_shrink_expanded_imm8 (imm);
+ assert ((int)imm >= 0);
+ }
+ assert (imm <= 255);
+ insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc);
+
+ if (kind == AARCH64_MOD_NONE)
+ return NULL;
+
+ /* shift amount partially in cmode */
+ assert (kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSL);
+ if (kind == AARCH64_MOD_LSL)
+ {
+ /* AARCH64_MOD_LSL: shift zeros. */
+ int esize = aarch64_get_qualifier_esize (opnd0_qualifier);
+ assert (esize == 4 || esize == 2);
+ amount >>= 3;
+ if (esize == 4)
+ gen_sub_field (FLD_cmode, 1, 2, &field); /* per word */
+ else
+ gen_sub_field (FLD_cmode, 1, 1, &field); /* per halfword */
+ }
+ else
+ {
+ /* AARCH64_MOD_MSL: shift ones. */
+ amount >>= 4;
+ gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */
+ }
+ insert_field_2 (&field, code, amount, 0);
+
+ return NULL;
+}
+
+/* Insert #<fbits> for the immediate operand in fp fix-point instructions,
+ e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
+const char *
+aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ insert_field (self->fields[0], code, 64 - info->imm.value, 0);
+ return NULL;
+}
+
+/* Insert arithmetic immediate for e.g. the last operand in
+ SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
+const char *
+aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
+ aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* shift */
+ aarch64_insn value = info->shifter.amount ? 1 : 0;
+ insert_field (self->fields[0], code, value, 0);
+ /* imm12 (unsigned) */
+ insert_field (self->fields[1], code, info->imm.value, 0);
+ return NULL;
+}
+
+/* Insert logical/bitmask immediate for e.g. the last operand in
+ ORR <Wd|WSP>, <Wn>, #<imm>. */
+const char *
+aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
+ aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ aarch64_insn value;
+ uint64_t imm = info->imm.value;
+ int is32 = aarch64_get_qualifier_esize (inst->operands[0].qualifier) == 4;
+
+ if (inst->opcode->op == OP_BIC)
+ imm = ~imm;
+ if (aarch64_logical_immediate_p (imm, is32, &value) == FALSE)
+ /* The constraint check should have guaranteed this wouldn't happen. */
+ assert (0);
+
+ insert_fields (code, value, 0, 3, self->fields[2], self->fields[1],
+ self->fields[0]);
+ return NULL;
+}
+
+/* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
+ or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
+const char *
+aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
+ aarch64_insn *code, const aarch64_inst *inst)
+{
+ aarch64_insn value;
+
+ assert (info->idx == 0);
+
+ /* Rt */
+ aarch64_ins_regno (self, info, code, inst);
+ if (inst->opcode->iclass == ldstpair_indexed
+ || inst->opcode->iclass == ldstnapair_offs
+ || inst->opcode->iclass == ldstpair_off
+ || inst->opcode->iclass == loadlit)
+ {
+ /* size */
+ switch (info->qualifier)
+ {
+ case AARCH64_OPND_QLF_S_S: value = 0; break;
+ case AARCH64_OPND_QLF_S_D: value = 1; break;
+ case AARCH64_OPND_QLF_S_Q: value = 2; break;
+ default: assert (0);
+ }
+ insert_field (FLD_ldst_size, code, value, 0);
+ }
+ else
+ {
+ /* opc[1]:size */
+ value = aarch64_get_qualifier_standard_value (info->qualifier);
+ insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1);
+ }
+
+ return NULL;
+}
+
+/* Encode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
+const char *
+aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* Rn */
+ insert_field (FLD_Rn, code, info->addr.base_regno, 0);
+ return NULL;
+}
+
+/* Encode the address operand for e.g.
+ STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+const char *
+aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ aarch64_insn S;
+ enum aarch64_modifier_kind kind = info->shifter.kind;
+
+ /* Rn */
+ insert_field (FLD_Rn, code, info->addr.base_regno, 0);
+ /* Rm */
+ insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
+ /* option */
+ if (kind == AARCH64_MOD_LSL)
+ kind = AARCH64_MOD_UXTX; /* Trick to enable the table-driven. */
+ insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);
+ /* S */
+ if (info->qualifier != AARCH64_OPND_QLF_S_B)
+ S = info->shifter.amount != 0;
+ else
+ /* For STR <Bt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}},
+ S <amount>
+ 0 [absent]
+ 1 #0
+ Must be #0 if <extend> is explicitly LSL. */
+ S = info->shifter.operator_present && info->shifter.amount_present;
+ insert_field (FLD_S, code, S, 0);
+
+ return NULL;
+}
+
+/* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
+const char *
+aarch64_ins_addr_simm (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code, const aarch64_inst *inst)
+{
+ int imm;
+
+ /* Rn */
+ insert_field (FLD_Rn, code, info->addr.base_regno, 0);
+ /* simm (imm9 or imm7) */
+ imm = info->addr.offset.imm;
+ if (self->fields[0] == FLD_imm7)
+ /* scaled immediate in ld/st pair instructions.. */
+ imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier));
+ insert_field (self->fields[0], code, imm, 0);
+ /* pre/post- index */
+ if (info->addr.writeback)
+ {
+ assert (inst->opcode->iclass != ldst_unscaled
+ && inst->opcode->iclass != ldstnapair_offs
+ && inst->opcode->iclass != ldstpair_off
+ && inst->opcode->iclass != ldst_unpriv);
+ assert (info->addr.preind != info->addr.postind);
+ if (info->addr.preind)
+ insert_field (self->fields[1], code, 1, 0);
+ }
+
+ return NULL;
+}
+
+/* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]. */
+const char *
+aarch64_ins_addr_uimm12 (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ int shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
+
+ /* Rn */
+ insert_field (self->fields[0], code, info->addr.base_regno, 0);
+ /* uimm12 */
+ insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);
+ return NULL;
+}
+
+/* Encode the address operand for e.g.
+ LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
+const char *
+aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* Rn */
+ insert_field (FLD_Rn, code, info->addr.base_regno, 0);
+ /* Rm | #<amount> */
+ if (info->addr.offset.is_reg)
+ insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
+ else
+ insert_field (FLD_Rm, code, 0x1f, 0);
+ return NULL;
+}
+
+/* Encode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
+const char *
+aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* cond */
+ insert_field (FLD_cond, code, info->cond->value, 0);
+ return NULL;
+}
+
+/* Encode the system register operand for e.g. MRS <Xt>, <systemreg>. */
+const char *
+aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* op0:op1:CRn:CRm:op2 */
+ insert_fields (code, info->sysreg, inst->opcode->mask, 5,
+ FLD_op2, FLD_CRm, FLD_CRn, FLD_op1, FLD_op0);
+ return NULL;
+}
+
+/* Encode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
+const char *
+aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* op1:op2 */
+ insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
+ FLD_op2, FLD_op1);
+ return NULL;
+}
+
+/* Encode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
+const char *
+aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* op1:CRn:CRm:op2 */
+ insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4,
+ FLD_op2, FLD_CRm, FLD_CRn, FLD_op1);
+ return NULL;
+}
+
+/* Encode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
+
+const char *
+aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* CRm */
+ insert_field (FLD_CRm, code, info->barrier->value, 0);
+ return NULL;
+}
+
+/* Encode the prefetch operation option operand for e.g.
+ PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
+
+const char *
+aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* prfop in Rt */
+ insert_field (FLD_Rt, code, info->prfop->value, 0);
+ return NULL;
+}
+
+/* Encode the extended register operand for e.g.
+ STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+const char *
+aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ enum aarch64_modifier_kind kind;
+
+ /* Rm */
+ insert_field (FLD_Rm, code, info->reg.regno, 0);
+ /* option */
+ kind = info->shifter.kind;
+ if (kind == AARCH64_MOD_LSL)
+ kind = info->qualifier == AARCH64_OPND_QLF_W
+ ? AARCH64_MOD_UXTW : AARCH64_MOD_UXTX;
+ insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);
+ /* imm3 */
+ insert_field (FLD_imm3, code, info->shifter.amount, 0);
+
+ return NULL;
+}
+
+/* Encode the shifted register operand for e.g.
+ SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
+const char *
+aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* Rm */
+ insert_field (FLD_Rm, code, info->reg.regno, 0);
+ /* shift */
+ insert_field (FLD_shift, code,
+ aarch64_get_operand_modifier_value (info->shifter.kind), 0);
+ /* imm6 */
+ insert_field (FLD_imm6, code, info->shifter.amount, 0);
+
+ return NULL;
+}
+
+/* Miscellaneous encoding functions. */
+
+/* Encode size[0], i.e. bit 22, for
+ e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
+
+static void
+encode_asimd_fcvt (aarch64_inst *inst)
+{
+ aarch64_insn value;
+ aarch64_field field = {0, 0};
+ enum aarch64_opnd_qualifier qualifier;
+
+ switch (inst->opcode->op)
+ {
+ case OP_FCVTN:
+ case OP_FCVTN2:
+ /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
+ qualifier = inst->operands[1].qualifier;
+ break;
+ case OP_FCVTL:
+ case OP_FCVTL2:
+ /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
+ qualifier = inst->operands[0].qualifier;
+ break;
+ default:
+ assert (0);
+ }
+ assert (qualifier == AARCH64_OPND_QLF_V_4S
+ || qualifier == AARCH64_OPND_QLF_V_2D);
+ value = (qualifier == AARCH64_OPND_QLF_V_4S) ? 0 : 1;
+ gen_sub_field (FLD_size, 0, 1, &field);
+ insert_field_2 (&field, &inst->value, value, 0);
+}
+
+/* Encode size[0], i.e. bit 22, for
+ e.g. FCVTXN <Vb><d>, <Va><n>. */
+
+static void
+encode_asisd_fcvtxn (aarch64_inst *inst)
+{
+ aarch64_insn val = 1;
+ aarch64_field field = {0, 0};
+ assert (inst->operands[0].qualifier == AARCH64_OPND_QLF_S_S);
+ gen_sub_field (FLD_size, 0, 1, &field);
+ insert_field_2 (&field, &inst->value, val, 0);
+}
+
+/* Encode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
+static void
+encode_fcvt (aarch64_inst *inst)
+{
+ aarch64_insn val;
+ const aarch64_field field = {15, 2};
+
+ /* opc dstsize */
+ switch (inst->operands[0].qualifier)
+ {
+ case AARCH64_OPND_QLF_S_S: val = 0; break;
+ case AARCH64_OPND_QLF_S_D: val = 1; break;
+ case AARCH64_OPND_QLF_S_H: val = 3; break;
+ default: abort ();
+ }
+ insert_field_2 (&field, &inst->value, val, 0);
+
+ return;
+}
+
+/* Do miscellaneous encodings that are not common enough to be driven by
+ flags. */
+
+static void
+do_misc_encoding (aarch64_inst *inst)
+{
+ switch (inst->opcode->op)
+ {
+ case OP_FCVT:
+ encode_fcvt (inst);
+ break;
+ case OP_FCVTN:
+ case OP_FCVTN2:
+ case OP_FCVTL:
+ case OP_FCVTL2:
+ encode_asimd_fcvt (inst);
+ break;
+ case OP_FCVTXN_S:
+ encode_asisd_fcvtxn (inst);
+ break;
+ default: break;
+ }
+}
+
+/* Encode the 'size' and 'Q' field for e.g. SHADD. */
+static void
+encode_sizeq (aarch64_inst *inst)
+{
+ aarch64_insn sizeq;
+ enum aarch64_field_kind kind;
+ int idx;
+
+ /* Get the index of the operand whose information we are going to use
+ to encode the size and Q fields.
+ This is deduced from the possible valid qualifier lists. */
+ idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode);
+ DEBUG_TRACE ("idx: %d; qualifier: %s", idx,
+ aarch64_get_qualifier_name (inst->operands[idx].qualifier));
+ sizeq = aarch64_get_qualifier_standard_value (inst->operands[idx].qualifier);
+ /* Q */
+ insert_field (FLD_Q, &inst->value, sizeq & 0x1, inst->opcode->mask);
+ /* size */
+ if (inst->opcode->iclass == asisdlse
+ || inst->opcode->iclass == asisdlsep
+ || inst->opcode->iclass == asisdlso
+ || inst->opcode->iclass == asisdlsop)
+ kind = FLD_vldst_size;
+ else
+ kind = FLD_size;
+ insert_field (kind, &inst->value, (sizeq >> 1) & 0x3, inst->opcode->mask);
+}
+
+/* Opcodes that have fields shared by multiple operands are usually flagged
+ with flags. In this function, we detect such flags and use the
+ information in one of the related operands to do the encoding. The 'one'
+ operand is not any operand but one of the operands that has the enough
+ information for such an encoding. */
+
+static void
+do_special_encoding (struct aarch64_inst *inst)
+{
+ int idx;
+ aarch64_insn value;
+
+ DEBUG_TRACE ("enter with coding 0x%x", (uint32_t) inst->value);
+
+ /* Condition for truly conditional executed instructions, e.g. b.cond. */
+ if (inst->opcode->flags & F_COND)
+ {
+ insert_field (FLD_cond2, &inst->value, inst->cond->value, 0);
+ }
+ if (inst->opcode->flags & F_SF)
+ {
+ idx = select_operand_for_sf_field_coding (inst->opcode);
+ value = (inst->operands[idx].qualifier == AARCH64_OPND_QLF_X
+ || inst->operands[idx].qualifier == AARCH64_OPND_QLF_SP)
+ ? 1 : 0;
+ insert_field (FLD_sf, &inst->value, value, 0);
+ if (inst->opcode->flags & F_N)
+ insert_field (FLD_N, &inst->value, value, inst->opcode->mask);
+ }
+ if (inst->opcode->flags & F_SIZEQ)
+ encode_sizeq (inst);
+ if (inst->opcode->flags & F_FPTYPE)
+ {
+ idx = select_operand_for_fptype_field_coding (inst->opcode);
+ switch (inst->operands[idx].qualifier)
+ {
+ case AARCH64_OPND_QLF_S_S: value = 0; break;
+ case AARCH64_OPND_QLF_S_D: value = 1; break;
+ case AARCH64_OPND_QLF_S_H: value = 3; break;
+ default: assert (0);
+ }
+ insert_field (FLD_type, &inst->value, value, 0);
+ }
+ if (inst->opcode->flags & F_SSIZE)
+ {
+ enum aarch64_opnd_qualifier qualifier;
+ idx = select_operand_for_scalar_size_field_coding (inst->opcode);
+ qualifier = inst->operands[idx].qualifier;
+ assert (qualifier >= AARCH64_OPND_QLF_S_B
+ && qualifier <= AARCH64_OPND_QLF_S_Q);
+ value = aarch64_get_qualifier_standard_value (qualifier);
+ insert_field (FLD_size, &inst->value, value, inst->opcode->mask);
+ }
+ if (inst->opcode->flags & F_T)
+ {
+ int num; /* num of consecutive '0's on the right side of imm5<3:0>. */
+ aarch64_field field = {0, 0};
+ enum aarch64_opnd_qualifier qualifier;
+
+ idx = 0;
+ qualifier = inst->operands[idx].qualifier;
+ assert (aarch64_get_operand_class (inst->opcode->operands[0])
+ == AARCH64_OPND_CLASS_SIMD_REG
+ && qualifier >= AARCH64_OPND_QLF_V_8B
+ && qualifier <= AARCH64_OPND_QLF_V_2D);
+ /* imm5<3:0> q <t>
+ 0000 x reserved
+ xxx1 0 8b
+ xxx1 1 16b
+ xx10 0 4h
+ xx10 1 8h
+ x100 0 2s
+ x100 1 4s
+ 1000 0 reserved
+ 1000 1 2d */
+ value = aarch64_get_qualifier_standard_value (qualifier);
+ insert_field (FLD_Q, &inst->value, value & 0x1, inst->opcode->mask);
+ num = (int) value >> 1;
+ assert (num >= 0 && num <= 3);
+ gen_sub_field (FLD_imm5, 0, num + 1, &field);
+ insert_field_2 (&field, &inst->value, 1 << num, inst->opcode->mask);
+ }
+ if (inst->opcode->flags & F_GPRSIZE_IN_Q)
+ {
+ /* Use Rt to encode in the case of e.g.
+ STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
+ enum aarch64_opnd_qualifier qualifier;
+ idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt);
+ if (idx == -1)
+ /* Otherwise use the result operand, which has to be a integer
+ register. */
+ idx = 0;
+ assert (idx == 0 || idx == 1);
+ assert (aarch64_get_operand_class (inst->opcode->operands[idx])
+ == AARCH64_OPND_CLASS_INT_REG);
+ qualifier = inst->operands[idx].qualifier;
+ insert_field (FLD_Q, &inst->value,
+ aarch64_get_qualifier_standard_value (qualifier), 0);
+ }
+ if (inst->opcode->flags & F_LDS_SIZE)
+ {
+ /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+ enum aarch64_opnd_qualifier qualifier;
+ aarch64_field field = {0, 0};
+ assert (aarch64_get_operand_class (inst->opcode->operands[0])
+ == AARCH64_OPND_CLASS_INT_REG);
+ gen_sub_field (FLD_opc, 0, 1, &field);
+ qualifier = inst->operands[0].qualifier;
+ insert_field_2 (&field, &inst->value,
+ 1 - aarch64_get_qualifier_standard_value (qualifier), 0);
+ }
+ /* Miscellaneous encoding as the last step. */
+ if (inst->opcode->flags & F_MISC)
+ do_misc_encoding (inst);
+
+ DEBUG_TRACE ("exit with coding 0x%x", (uint32_t) inst->value);
+}
+
+/* Converters converting an alias opcode instruction to its real form. */
+
+/* ROR <Wd>, <Ws>, #<shift>
+ is equivalent to:
+ EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
+static void
+convert_ror_to_extr (aarch64_inst *inst)
+{
+ copy_operand_info (inst, 3, 2);
+ copy_operand_info (inst, 2, 1);
+}
+
+/* Convert
+ LSR <Xd>, <Xn>, #<shift>
+ to
+ UBFM <Xd>, <Xn>, #<shift>, #63. */
+static void
+convert_sr_to_bfm (aarch64_inst *inst)
+{
+ inst->operands[3].imm.value =
+ inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
+}
+
+/* Convert MOV to ORR. */
+static void
+convert_mov_to_orr (aarch64_inst *inst)
+{
+ /* MOV <Vd>.<T>, <Vn>.<T>
+ is equivalent to:
+ ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
+ copy_operand_info (inst, 2, 1);
+}
+
+/* When <imms> >= <immr>, the instruction written:
+ SBFX <Xd>, <Xn>, #<lsb>, #<width>
+ is equivalent to:
+ SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
+
+static void
+convert_bfx_to_bfm (aarch64_inst *inst)
+{
+ int64_t lsb, width;
+
+ /* Convert the operand. */
+ lsb = inst->operands[2].imm.value;
+ width = inst->operands[3].imm.value;
+ inst->operands[2].imm.value = lsb;
+ inst->operands[3].imm.value = lsb + width - 1;
+}
+
+/* When <imms> < <immr>, the instruction written:
+ SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
+ is equivalent to:
+ SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
+
+static void
+convert_bfi_to_bfm (aarch64_inst *inst)
+{
+ int64_t lsb, width;
+
+ /* Convert the operand. */
+ lsb = inst->operands[2].imm.value;
+ width = inst->operands[3].imm.value;
+ if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
+ {
+ inst->operands[2].imm.value = (32 - lsb) & 0x1f;
+ inst->operands[3].imm.value = width - 1;
+ }
+ else
+ {
+ inst->operands[2].imm.value = (64 - lsb) & 0x3f;
+ inst->operands[3].imm.value = width - 1;
+ }
+}
+
+/* The instruction written:
+ LSL <Xd>, <Xn>, #<shift>
+ is equivalent to:
+ UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
+
+static void
+convert_lsl_to_ubfm (aarch64_inst *inst)
+{
+ int64_t shift = inst->operands[2].imm.value;
+
+ if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
+ {
+ inst->operands[2].imm.value = (32 - shift) & 0x1f;
+ inst->operands[3].imm.value = 31 - shift;
+ }
+ else
+ {
+ inst->operands[2].imm.value = (64 - shift) & 0x3f;
+ inst->operands[3].imm.value = 63 - shift;
+ }
+}
+
+/* CINC <Wd>, <Wn>, <cond>
+ is equivalent to:
+ CSINC <Wd>, <Wn>, <Wn>, invert(<cond>). */
+
+static void
+convert_to_csel (aarch64_inst *inst)
+{
+ copy_operand_info (inst, 3, 2);
+ copy_operand_info (inst, 2, 1);
+ inst->operands[3].cond = get_inverted_cond (inst->operands[3].cond);
+}
+
+/* CSET <Wd>, <cond>
+ is equivalent to:
+ CSINC <Wd>, WZR, WZR, invert(<cond>). */
+
+static void
+convert_cset_to_csinc (aarch64_inst *inst)
+{
+ copy_operand_info (inst, 3, 1);
+ copy_operand_info (inst, 2, 0);
+ copy_operand_info (inst, 1, 0);
+ inst->operands[1].reg.regno = 0x1f;
+ inst->operands[2].reg.regno = 0x1f;
+ inst->operands[3].cond = get_inverted_cond (inst->operands[3].cond);
+}
+
+/* MOV <Wd>, #<imm>
+ is equivalent to:
+ MOVZ <Wd>, #<imm16>, LSL #<shift>. */
+
+static void
+convert_mov_to_movewide (aarch64_inst *inst)
+{
+ int is32;
+ uint32_t shift_amount;
+ uint64_t value;
+
+ switch (inst->opcode->op)
+ {
+ case OP_MOV_IMM_WIDE:
+ value = inst->operands[1].imm.value;
+ break;
+ case OP_MOV_IMM_WIDEN:
+ value = ~inst->operands[1].imm.value;
+ break;
+ default:
+ assert (0);
+ }
+ inst->operands[1].type = AARCH64_OPND_HALF;
+ is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
+ /* This should have been guaranteed by the constraint check. */
+ assert (aarch64_wide_constant_p (value, is32, &shift_amount) == TRUE);
+ value >>= shift_amount;
+ value &= 0xffff;
+ inst->operands[1].imm.value = value;
+ inst->operands[1].shifter.kind = AARCH64_MOD_LSL;
+ inst->operands[1].shifter.amount = shift_amount;
+}
+
+/* MOV <Wd>, #<imm>
+ is equivalent to:
+ ORR <Wd>, WZR, #<imm>. */
+
+static void
+convert_mov_to_movebitmask (aarch64_inst *inst)
+{
+ copy_operand_info (inst, 2, 1);
+ inst->operands[1].reg.regno = 0x1f;
+ inst->operands[1].skip = 0;
+}
+
+/* Some alias opcodes are assembled by being converted to their real-form. */
+
+static void
+convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
+{
+ const aarch64_opcode *alias = inst->opcode;
+
+ if ((alias->flags & F_CONV) == 0)
+ goto convert_to_real_return;
+
+ switch (alias->op)
+ {
+ case OP_ASR_IMM:
+ case OP_LSR_IMM:
+ convert_sr_to_bfm (inst);
+ break;
+ case OP_LSL_IMM:
+ convert_lsl_to_ubfm (inst);
+ break;
+ case OP_CINC:
+ case OP_CINV:
+ case OP_CNEG:
+ convert_to_csel (inst);
+ break;
+ case OP_CSET:
+ case OP_CSETM:
+ convert_cset_to_csinc (inst);
+ break;
+ case OP_UBFX:
+ case OP_BFXIL:
+ case OP_SBFX:
+ convert_bfx_to_bfm (inst);
+ break;
+ case OP_SBFIZ:
+ case OP_BFI:
+ case OP_UBFIZ:
+ convert_bfi_to_bfm (inst);
+ break;
+ case OP_MOV_V:
+ convert_mov_to_orr (inst);
+ break;
+ case OP_MOV_IMM_WIDE:
+ case OP_MOV_IMM_WIDEN:
+ convert_mov_to_movewide (inst);
+ break;
+ case OP_MOV_IMM_LOG:
+ convert_mov_to_movebitmask (inst);
+ break;
+ case OP_ROR_IMM:
+ convert_ror_to_extr (inst);
+ break;
+ default:
+ break;
+ }
+
+convert_to_real_return:
+ aarch64_replace_opcode (inst, real);
+}
+
+/* Encode *INST_ORI of the opcode code OPCODE.
+ Return the encoded result in *CODE and if QLF_SEQ is not NULL, return the
+ matched operand qualifier sequence in *QLF_SEQ. */
+
+int
+aarch64_opcode_encode (const aarch64_opcode *opcode,
+ const aarch64_inst *inst_ori, aarch64_insn *code,
+ aarch64_opnd_qualifier_t *qlf_seq,
+ aarch64_operand_error *mismatch_detail)
+{
+ int i;
+ const aarch64_opcode *aliased;
+ aarch64_inst copy, *inst;
+
+ DEBUG_TRACE ("enter with %s", opcode->name);
+
+ /* Create a copy of *INST_ORI, so that we can do any change we want. */
+ copy = *inst_ori;
+ inst = ©
+
+ assert (inst->opcode == NULL || inst->opcode == opcode);
+ if (inst->opcode == NULL)
+ inst->opcode = opcode;
+
+ /* Constrain the operands.
+ After passing this, the encoding is guaranteed to succeed. */
+ if (aarch64_match_operands_constraint (inst, mismatch_detail) == 0)
+ {
+ DEBUG_TRACE ("FAIL since operand constraint not met");
+ return 0;
+ }
+
+ /* Get the base value.
+ Note: this has to be before the aliasing handling below in order to
+ get the base value from the alias opcode before we move on to the
+ aliased opcode for encoding. */
+ inst->value = opcode->opcode;
+
+ /* No need to do anything else if the opcode does not have any operand. */
+ if (aarch64_num_of_operands (opcode) == 0)
+ goto encoding_exit;
+
+ /* Assign operand indexes and check types. Also put the matched
+ operand qualifiers in *QLF_SEQ to return. */
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ {
+ assert (opcode->operands[i] == inst->operands[i].type);
+ inst->operands[i].idx = i;
+ if (qlf_seq != NULL)
+ *qlf_seq = inst->operands[i].qualifier;
+ }
+
+ aliased = aarch64_find_real_opcode (opcode);
+ /* If the opcode is an alias and it does not ask for direct encoding by
+ itself, the instruction will be transformed to the form of real opcode
+ and the encoding will be carried out using the rules for the aliased
+ opcode. */
+ if (aliased != NULL && (opcode->flags & F_CONV))
+ {
+ DEBUG_TRACE ("real opcode '%s' has been found for the alias %s",
+ aliased->name, opcode->name);
+ /* Convert the operands to the form of the real opcode. */
+ convert_to_real (inst, aliased);
+ opcode = aliased;
+ }
+
+ aarch64_opnd_info *info = inst->operands;
+
+ /* Call the inserter of each operand. */
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++info)
+ {
+ const aarch64_operand *opnd;
+ enum aarch64_opnd type = opcode->operands[i];
+ if (type == AARCH64_OPND_NIL)
+ break;
+ if (info->skip)
+ {
+ DEBUG_TRACE ("skip the incomplete operand %d", i);
+ continue;
+ }
+ opnd = &aarch64_operands[type];
+ if (operand_has_inserter (opnd))
+ aarch64_insert_operand (opnd, info, &inst->value, inst);
+ }
+
+ /* Call opcode encoders indicated by flags. */
+ if (opcode_has_special_coder (opcode))
+ do_special_encoding (inst);
+
+encoding_exit:
+ DEBUG_TRACE ("exit with %s", opcode->name);
+
+ *code = inst->value;
+
+ return 1;
+}
--- /dev/null
+/* aarch64-asm.h -- Header file for aarch64-asm.c and aarch64-asm-2.c.
+ Copyright 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#ifndef OPCODES_AARCH64_ASM_H
+#define OPCODES_AARCH64_ASM_H
+
+#include "aarch64-opc.h"
+
+/* Given OPCODE, return the opcode entry that OPCODE aliases to, e.g.
+ given LSL, return UBFM. */
+
+const aarch64_opcode* aarch64_find_real_opcode (const aarch64_opcode *);
+
+/* Switch-table-based high-level operand inserter. */
+
+const char* aarch64_insert_operand (const aarch64_operand *,
+ const aarch64_opnd_info *, aarch64_insn *,
+ const aarch64_inst *);
+
+/* Operand inserters. */
+
+#define AARCH64_DECL_OPD_INSERTER(x) \
+ const char* aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
+ aarch64_insn *, const aarch64_inst *)
+
+AARCH64_DECL_OPD_INSERTER (ins_regno);
+AARCH64_DECL_OPD_INSERTER (ins_reglane);
+AARCH64_DECL_OPD_INSERTER (ins_reglist);
+AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist);
+AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist_r);
+AARCH64_DECL_OPD_INSERTER (ins_ldst_elemlist);
+AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_shift);
+AARCH64_DECL_OPD_INSERTER (ins_imm);
+AARCH64_DECL_OPD_INSERTER (ins_imm_half);
+AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_modified);
+AARCH64_DECL_OPD_INSERTER (ins_fbits);
+AARCH64_DECL_OPD_INSERTER (ins_aimm);
+AARCH64_DECL_OPD_INSERTER (ins_limm);
+AARCH64_DECL_OPD_INSERTER (ins_ft);
+AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
+AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
+AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
+AARCH64_DECL_OPD_INSERTER (ins_addr_uimm12);
+AARCH64_DECL_OPD_INSERTER (ins_simd_addr_post);
+AARCH64_DECL_OPD_INSERTER (ins_cond);
+AARCH64_DECL_OPD_INSERTER (ins_sysreg);
+AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
+AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
+AARCH64_DECL_OPD_INSERTER (ins_barrier);
+AARCH64_DECL_OPD_INSERTER (ins_prfop);
+AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
+AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
+
+#undef AARCH64_DECL_OPD_INSERTER
+
+#endif /* OPCODES_AARCH64_ASM_H */
--- /dev/null
+/* This file is automatically generated by aarch64-gen. Do not edit! */
+/* Copyright 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include "aarch64-dis.h"
+
+/* Called by aarch64_opcode_lookup. */
+
+static int
+aarch64_opcode_lookup_1 (uint32_t word)
+{
+ if (((word >> 26) & 0x1) == 0)
+ {
+ if (((word >> 25) & 0x1) == 0)
+ {
+ if (((word >> 27) & 0x1) == 0)
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx0000xxx0
+ adr. */
+ return 769;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx0000xxx1
+ adrp. */
+ return 770;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx1000x00x
+ add. */
+ return 12;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx1000x01x
+ sub. */
+ return 16;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx1000x10x
+ adds. */
+ return 14;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx1000x11x
+ subs. */
+ return 17;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx000x0010000
+ stxrb. */
+ return 705;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx000x0010010
+ stxrh. */
+ return 711;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx000x00100x1
+ stxr. */
+ return 717;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx100x00100xx
+ stxp. */
+ return 719;
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx000x0010000
+ stlxrb. */
+ return 706;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx000x0010010
+ stlxrh. */
+ return 712;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx000x00100x1
+ stlxr. */
+ return 718;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx100x00100xx
+ stlxp. */
+ return 720;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx00x00101xx
+ stnp. */
+ return 727;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx01x0010000
+ stlrb. */
+ return 709;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx01x0010010
+ stlrh. */
+ return 715;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx01x00100x1
+ stlr. */
+ return 725;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx01x00101xx
+ stp. */
+ return 736;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx010x0010000
+ ldxrb. */
+ return 707;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx010x0010010
+ ldxrh. */
+ return 713;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx010x00100x1
+ ldxr. */
+ return 721;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx110x00100xx
+ ldxp. */
+ return 723;
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx010x0010000
+ ldaxrb. */
+ return 708;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx010x0010010
+ ldaxrh. */
+ return 714;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx010x00100x1
+ ldaxr. */
+ return 722;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx110x00100xx
+ ldaxp. */
+ return 724;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx10x001010x
+ ldnp. */
+ return 728;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx10x001011x
+ ldpsw. */
+ return 735;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx11x0010000
+ ldarb. */
+ return 710;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx11x0010010
+ ldarh. */
+ return 716;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx11x00100x1
+ ldar. */
+ return 726;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx11x001010x
+ ldp. */
+ return 737;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx11x001011x
+ ldpsw. */
+ return 740;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx000110x0
+ ldr. */
+ return 741;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx00011001
+ ldrsw. */
+ return 743;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx00011011
+ prfm. */
+ return 744;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxx0000011100
+ sturb. */
+ return 681;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxx0000011110
+ sturh. */
+ return 691;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxx00000111x1
+ stur. */
+ return 697;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxx1000011100
+ ldurb. */
+ return 682;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxx1000011110
+ ldurh. */
+ return 692;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxx10000111x1
+ ldur. */
+ return 698;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxxx100011100
+ ldursb. */
+ return 685;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxxx100011101
+ ldursw. */
+ return 701;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxxx100011110
+ ldursh. */
+ return 695;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxxx100011111
+ prfum. */
+ return 703;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx00000011100
+ sttrb. */
+ return 672;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx00000011110
+ sttrh. */
+ return 675;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx000000111x1
+ sttr. */
+ return 678;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx01000011100
+ ldtrb. */
+ return 673;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx01000011110
+ ldtrh. */
+ return 676;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx010000111x1
+ ldtr. */
+ return 679;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx0x100011100
+ ldtrsb. */
+ return 674;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx0x100011101
+ ldtrsw. */
+ return 680;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx0x10001111x
+ ldtrsh. */
+ return 677;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx10000011100
+ strb. */
+ return 660;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx10000011110
+ strh. */
+ return 665;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx100000111x1
+ str. */
+ return 668;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx11000011100
+ ldrb. */
+ return 661;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx11000011110
+ ldrh. */
+ return 666;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx110000111x1
+ ldr. */
+ return 669;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx1x100011100
+ ldrsb. */
+ return 662;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx1x100011101
+ ldrsw. */
+ return 670;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx1x100011110
+ ldrsh. */
+ return 667;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx1x100011111
+ prfm. */
+ return 671;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxx0000011100
+ strb. */
+ return 637;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxx0000011110
+ strh. */
+ return 642;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxx00000111x1
+ str. */
+ return 645;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxx1000011100
+ ldrb. */
+ return 638;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxx1000011110
+ ldrh. */
+ return 643;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxx10000111x1
+ ldr. */
+ return 646;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxxx100011100
+ ldrsb. */
+ return 639;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxxx100011101
+ ldrsw. */
+ return 647;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxxx10001111x
+ ldrsh. */
+ return 644;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx0010011x00
+ strb. */
+ return 648;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx0010011x10
+ strh. */
+ return 653;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx0010011xx1
+ str. */
+ return 656;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx1010011x00
+ ldrb. */
+ return 649;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx1010011x10
+ ldrh. */
+ return 654;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx1010011xx1
+ ldr. */
+ return 657;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx110011x00
+ ldrsb. */
+ return 650;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx110011x01
+ ldrsw. */
+ return 658;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx110011x10
+ ldrsh. */
+ return 655;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx110011x11
+ prfm. */
+ return 659;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ if (((word >> 27) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx00100x00x
+ and. */
+ return 745;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx00100x01x
+ eor. */
+ return 749;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx00100x10x
+ orr. */
+ return 747;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx00100x11x
+ ands. */
+ return 750;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx10100x00x
+ movn. */
+ return 764;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx10100x01x
+ movz. */
+ return 766;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx10100x1xx
+ movk. */
+ return 768;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0xx0101000x
+ and. */
+ return 752;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0xx0101001x
+ eor. */
+ return 759;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0xx0101010x
+ orr. */
+ return 754;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0xx0101011x
+ ands. */
+ return 761;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx0000101100x
+ adc. */
+ return 0;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx0000101101x
+ sbc. */
+ return 2;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx0000101110x
+ adcs. */
+ return 1;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx0000101111x
+ sbcs. */
+ return 4;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx00101011x0x
+ csel. */
+ return 520;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx00101011x1x
+ csinv. */
+ return 524;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx01001011x0x
+ ccmn. */
+ return 518;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx01001011x1x
+ ccmp. */
+ return 519;
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0000xxxxxxx01101011xxx
+ rbit. */
+ return 543;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0001xxxxxxx01101011xxx
+ lslv. */
+ return 552;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001xxxxxxxx01101011xxx
+ clz. */
+ return 547;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx0x001011x0x
+ ccmn. */
+ return 516;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxx0x001011x1x
+ ccmp. */
+ return 517;
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01x0xxxxxxx0x101011x0x
+ udiv. */
+ return 550;
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01x0xxxxxxx0x101011x10
+ rev. */
+ return 545;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01x0xxxxxxx0x101011x11
+ rev32. */
+ return 549;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01x1xxxxxxx0x101011xxx
+ asrv. */
+ return 556;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx10xxxxxxxxx00x01011x0x
+ csinc. */
+ return 521;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx10xxxxxxxxx00x01011x1x
+ csneg. */
+ return 527;
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1000xxxxxxx01x01011xxx
+ rev16. */
+ return 544;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1001xxxxxxx01x01011xxx
+ lsrv. */
+ return 554;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101xxxxxxxx01x01011xxx
+ cls. */
+ return 548;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11x0xxxxxxx0xx01011x0x
+ sdiv. */
+ return 551;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11x0xxxxxxx0xx01011x1x
+ rev. */
+ return 546;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11x1xxxxxxx0xx01011xxx
+ rorv. */
+ return 558;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1xx0101x00x
+ bic. */
+ return 753;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1xx0101x01x
+ eon. */
+ return 760;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1xx0101x10x
+ orn. */
+ return 757;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1xx0101x11x
+ bics. */
+ return 763;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 27) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx01100x00x
+ sbfm. */
+ return 489;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx01100x01x
+ ubfm. */
+ return 499;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx01100x1xx
+ bfm. */
+ return 496;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxx11100xxxx
+ extr. */
+ return 582;
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0xx1101000x
+ add. */
+ return 19;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0xx1101001x
+ sub. */
+ return 22;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0xx1101010x
+ adds. */
+ return 20;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0xx1101011x
+ subs. */
+ return 24;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx00x11011xxx
+ madd. */
+ return 560;
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx01011011xxx
+ smulh. */
+ return 568;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx01111011xxx
+ umulh. */
+ return 573;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx0xx11011xxx
+ msub. */
+ return 562;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1x01101000x
+ add. */
+ return 6;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1x01101001x
+ sub. */
+ return 9;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1x01101010x
+ adds. */
+ return 7;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1x01101011x
+ subs. */
+ return 10;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx1x011011xxx
+ smaddl. */
+ return 564;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx1x011011xxx
+ smsubl. */
+ return 566;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx1x11101xxxx
+ umaddl. */
+ return 569;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx1x11101xxxx
+ umsubl. */
+ return 571;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 27) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxxxx10x000
+ b. */
+ return 506;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxxxx10x001
+ bl. */
+ return 507;
+ }
+ }
+ else
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ if (((word >> 25) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx0010x010
+ b.c. */
+ return 515;
+ }
+ else
+ {
+ if (((word >> 0) & 0x1) == 0)
+ {
+ if (((word >> 1) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 00xxxxxxxxxxxxxxxxxxx0xx0010x011
+ hlt. */
+ return 578;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 00xxxxxxxxxxxxxxxxxxx1xx0010x011
+ brk. */
+ return 577;
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 01xxxxxxxxxxxxxxxxxxx0xx0010x011
+ hvc. */
+ return 575;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 01xxxxxxxxxxxxxxxxxxx1xx0010x011
+ dcps2. */
+ return 580;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 1) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 10xxxxxxxxxxxxxxxxxxx0xx0010x011
+ svc. */
+ return 574;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 10xxxxxxxxxxxxxxxxxxx1xx0010x011
+ dcps1. */
+ return 579;
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 11xxxxxxxxxxxxxxxxxxx0xx0010x011
+ smc. */
+ return 576;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 11xxxxxxxxxxxxxxxxxxx1xx0010x011
+ dcps3. */
+ return 581;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0000110x01x
+ br. */
+ return 508;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0010110x01x
+ eret. */
+ return 511;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx01x0110x01x
+ ret. */
+ return 510;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1x00110x01x
+ blr. */
+ return 509;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1x10110x01x
+ drps. */
+ return 512;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx00xxxxx00xxx1x10x01x
+ msr. */
+ return 771;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx01xxxxx00xxx1x10x01x
+ hint. */
+ return 772;
+ }
+ }
+ else
+ {
+ if (((word >> 5) & 0x1) == 0)
+ {
+ if (((word >> 6) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxx00xxxxx1xxxxxx00xxx1x10x01x
+ dsb. */
+ return 780;
+ }
+ else
+ {
+ if (((word >> 7) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxx010xxxx1xxxxxx00xxx1x10x01x
+ clrex. */
+ return 779;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxx011xxxx1xxxxxx00xxx1x10x01x
+ isb. */
+ return 782;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxx1xxxxxx1xxxxxx00xxx1x10x01x
+ dmb. */
+ return 781;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxx100xx1x10x01x
+ sys. */
+ return 783;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxx101xx1x10x01x
+ sysl. */
+ return 789;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxx10xx1x10x01x
+ msr. */
+ return 788;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxx11xx1x10x01x
+ mrs. */
+ return 790;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ if (((word >> 25) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx0010x1xx
+ cbz. */
+ return 513;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx0110x1xx
+ tbz. */
+ return 791;
+ }
+ }
+ else
+ {
+ if (((word >> 25) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx1010x1xx
+ cbnz. */
+ return 514;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx1110x1xx
+ tbnz. */
+ return 792;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 25) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx00001100xx
+ st4. */
+ return 351;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx00001101xx
+ stnp. */
+ return 729;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx0xxxxxxx000101100xx
+ st1. */
+ return 367;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx0xxxxxxx100101100xx
+ st2. */
+ return 369;
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx1xxxxxxx000101100xx
+ st3. */
+ return 368;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx1xxxxxxx100101100xx
+ st4. */
+ return 370;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx00101101xx
+ stp. */
+ return 733;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx001001100xx
+ st4. */
+ return 359;
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx0xxxxxxx001101100xx
+ st1. */
+ return 379;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx1xxxxxxx001101100xx
+ st3. */
+ return 380;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx0xxxxxxx101x01100xx
+ st2. */
+ return 381;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx1xxxxxxx101x01100xx
+ st4. */
+ return 382;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx01x01101xx
+ stp. */
+ return 738;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx10001100xx
+ ld4. */
+ return 355;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx10001101xx
+ ldnp. */
+ return 730;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx0xxxxxxx010101100xx
+ ld1. */
+ return 371;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx0xxxxxxx110101100xx
+ ld2. */
+ return 375;
+ }
+ }
+ else
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx1xxxxxxx010101100xx
+ ld3. */
+ return 372;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx1xxxxxxx110101100xx
+ ld4. */
+ return 376;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx10101101xx
+ ldp. */
+ return 734;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx011001100xx
+ ld4. */
+ return 363;
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx0xxxxxxx011101100xx
+ ld1. */
+ return 383;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx1xxxxxxx011101100xx
+ ld3. */
+ return 384;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx0xxxxxxx111x01100xx
+ ld2. */
+ return 387;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxx1xxxxxxx111x01100xx
+ ld4. */
+ return 388;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx11x01101xx
+ ldp. */
+ return 739;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxxxx001110xx
+ ldr. */
+ return 742;
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxx0x001111xx
+ stur. */
+ return 687;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxxx1x001111xx
+ ldur. */
+ return 688;
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxxx0x001111xx
+ str. */
+ return 663;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01xxxxxxxxxx1x001111xx
+ ldr. */
+ return 664;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxx0x001111xx
+ str. */
+ return 640;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxxx1x001111xx
+ ldr. */
+ return 641;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx0x10111xxx
+ str. */
+ return 651;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxxx1x10111xxx
+ ldr. */
+ return 652;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 24) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000xxxxxxxx0xx011100xx
+ tbl. */
+ return 337;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001xxxxxxxx0xx011100xx
+ tbx. */
+ return 338;
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010x0xxxxxx0xx011100xx
+ trn1. */
+ return 216;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010x1xxxxxx0xx011100xx
+ trn2. */
+ return 219;
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01100xxxxxx0xx011100xx
+ uzp1. */
+ return 215;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01101xxxxxx0xx011100xx
+ uzp2. */
+ return 218;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01110xxxxxx0xx011100xx
+ zip1. */
+ return 217;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx01111xxxxxx0xx011100xx
+ zip2. */
+ return 220;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0xxxxxxxxxx0xx011101xx
+ ext. */
+ return 119;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx10xxxxxxxxx0xx011100xx
+ dup. */
+ return 135;
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1100xxxxxxx0xx011100xx
+ dup. */
+ return 136;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1101xxxxxxx0xx011100xx
+ smov. */
+ return 137;
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1110xxxxxxx0xx011100xx
+ ins. */
+ return 140;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1111xxxxxxx0xx011100xx
+ umov. */
+ return 138;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxx0xx011101xx
+ ins. */
+ return 142;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxx00xxx0xx01111x0x
+ fcvtzs. */
+ return 586;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxx01xxx0xx01111x0x
+ scvtf. */
+ return 584;
+ }
+ }
+ else
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxx10xxx0xx01111x0x
+ fcvtzu. */
+ return 587;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxx11xxx0xx01111x0x
+ ucvtf. */
+ return 585;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x000xxxxxx0xx01111x1x
+ sha1c. */
+ return 536;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x001xxxxxx0xx01111x1x
+ sha256h. */
+ return 540;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x010xxxxxx0xx01111x1x
+ sha1m. */
+ return 538;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x011xxxxxx0xx01111x1x
+ sha256su1. */
+ return 542;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x100xxxxxx0xx01111x1x
+ sha1p. */
+ return 537;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x101xxxxxx0xx01111x1x
+ sha256h2. */
+ return 541;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x11xxxxxxx0xx01111x1x
+ sha1su0. */
+ return 539;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xxxxxxxxxx0xx01111x1x
+ dup. */
+ return 426;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx1xx0111000x
+ saddl. */
+ return 38;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx1xx0111001x
+ saddl2. */
+ return 39;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx1xx0111010x
+ uaddl. */
+ return 70;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx1xx0111011x
+ uaddl2. */
+ return 71;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000000001xx01111xxx
+ fcvtns. */
+ return 588;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000000011xx01111xxx
+ fcvtms. */
+ return 598;
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000000101xx01111xxx
+ fcvtps. */
+ return 596;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000000111xx01111xxx
+ fcvtzs. */
+ return 600;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000001xx1xx01111xxx
+ fcvtas. */
+ return 592;
+ }
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000010xx1xx01111xxx
+ scvtf. */
+ return 590;
+ }
+ else
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0000000110x1xx01111xxx
+ fmov. */
+ return 594;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0000000111x1xx01111xxx
+ fmov. */
+ return 602;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000100001xx01111xxx
+ fcvtnu. */
+ return 589;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000100011xx01111xxx
+ fcvtmu. */
+ return 599;
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000100101xx01111xxx
+ fcvtpu. */
+ return 597;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000100111xx01111xxx
+ fcvtzu. */
+ return 601;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000101xx1xx01111xxx
+ fcvtau. */
+ return 593;
+ }
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000110xx1xx01111xxx
+ ucvtf. */
+ return 591;
+ }
+ else
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0000001110x1xx01111xxx
+ fmov. */
+ return 595;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0000001111x1xx01111xxx
+ fmov. */
+ return 603;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx1xx0111x00x
+ smlal. */
+ return 54;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx1xx0111x01x
+ smlal2. */
+ return 55;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx1xx0111x10x
+ umlal. */
+ return 86;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx1xx0111x11x
+ umlal2. */
+ return 87;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000010xxxxx1xx0111000x
+ addhn. */
+ return 46;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000010xxxxx1xx0111001x
+ addhn2. */
+ return 47;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000010xxxxx1xx0111010x
+ raddhn. */
+ return 78;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000010xxxxx1xx0111011x
+ raddhn2. */
+ return 79;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000011xxxxx1xx0111000x
+ smull. */
+ return 62;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000011xxxxx1xx0111001x
+ smull2. */
+ return 63;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000011xxxxx1xx0111010x
+ umull. */
+ return 90;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000011xxxxx1xx0111011x
+ umull2. */
+ return 91;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000010000xx1xx01111xxx
+ fmov. */
+ return 610;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000010001xx1xx01111xxx
+ frintn. */
+ return 615;
+ }
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000010100xx1xx01111xxx
+ fneg. */
+ return 612;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000010101xx1xx01111xxx
+ frintm. */
+ return 617;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000011000xx1xx01111xxx
+ fabs. */
+ return 611;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000011001xx1xx01111xxx
+ frintp. */
+ return 616;
+ }
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000011100xx1xx01111xxx
+ fsqrt. */
+ return 613;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000011101xx1xx01111xxx
+ frintz. */
+ return 618;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xx10xx1xx01111xxx
+ fcvt. */
+ return 614;
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000010011xx1xx01111xxx
+ frinta. */
+ return 619;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000010111xx1xx01111xxx
+ frintx. */
+ return 620;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000011x11xx1xx01111xxx
+ frinti. */
+ return 621;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000100xxxxx1xx0111000x
+ ssubl. */
+ return 42;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000100xxxxx1xx0111001x
+ ssubl2. */
+ return 43;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000100xxxxx1xx0111010x
+ usubl. */
+ return 74;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000100xxxxx1xx0111011x
+ usubl2. */
+ return 75;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00xxxxx000100xxxxx1xx01111xxx
+ fcmp. */
+ return 606;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx01xxxxx000100xxxxx1xx01111xxx
+ fcmpe. */
+ return 607;
+ }
+ }
+ else
+ {
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx10xxxxx000100xxxxx1xx01111xxx
+ fcmp. */
+ return 608;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx11xxxxx000100xxxxx1xx01111xxx
+ fcmpe. */
+ return 609;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000101xxxxx1xx0111x00x
+ smlsl. */
+ return 58;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000101xxxxx1xx0111x01x
+ smlsl2. */
+ return 59;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000101xxxxx1xx0111x10x
+ umlsl. */
+ return 88;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000101xxxxx1xx0111x11x
+ umlsl2. */
+ return 89;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000110xxxxx1xx0111x00x
+ subhn. */
+ return 50;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000110xxxxx1xx0111x01x
+ subhn2. */
+ return 51;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000110xxxxx1xx0111x10x
+ rsubhn. */
+ return 82;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000110xxxxx1xx0111x11x
+ rsubhn2. */
+ return 83;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000111xxxxx10x0111xx0x
+ pmull. */
+ return 66;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000111xxxxx10x0111xx1x
+ pmull2. */
+ return 68;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000111xxxxx11x0111xx0x
+ pmull. */
+ return 67;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000111xxxxx11x0111xx1x
+ pmull2. */
+ return 69;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001000xxxxx1xx0111000x
+ saddw. */
+ return 40;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001000xxxxx1xx0111001x
+ saddw2. */
+ return 41;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001000xxxxx1xx0111010x
+ uaddw. */
+ return 72;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001000xxxxx1xx0111011x
+ uaddw2. */
+ return 73;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001001xxxxx1xx01110x0x
+ sqdmlal. */
+ return 56;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001001xxxxx1xx01110x1x
+ sqdmlal2. */
+ return 57;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001010xxxxx1xx0111000x
+ sabal. */
+ return 48;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001010xxxxx1xx0111001x
+ sabal2. */
+ return 49;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001010xxxxx1xx0111010x
+ uabal. */
+ return 80;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001010xxxxx1xx0111011x
+ uabal2. */
+ return 81;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001011xxxxx1xx01110x0x
+ sqdmull. */
+ return 64;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001011xxxxx1xx01110x1x
+ sqdmull2. */
+ return 65;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001100xxxxx1xx0111000x
+ ssubw. */
+ return 44;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001100xxxxx1xx0111001x
+ ssubw2. */
+ return 45;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001100xxxxx1xx0111010x
+ usubw. */
+ return 76;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001100xxxxx1xx0111011x
+ usubw2. */
+ return 77;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001101xxxxx1xx01110x0x
+ sqdmlsl. */
+ return 60;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001101xxxxx1xx01110x1x
+ sqdmlsl2. */
+ return 61;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx1xx0111000x
+ sabdl. */
+ return 52;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx1xx0111001x
+ sabdl2. */
+ return 53;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx1xx0111010x
+ uabdl. */
+ return 84;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx1xx0111011x
+ uabdl2. */
+ return 85;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx001xxxxxxxx1xx01111x0x
+ fmov. */
+ return 635;
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx1xx01111x1x
+ sqdmlal. */
+ return 339;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx1xx01111x1x
+ sqdmull. */
+ return 341;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0011xxxxxxx1xx01111x1x
+ sqdmlsl. */
+ return 340;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010000xxxxx1xx011100xx
+ rev64. */
+ return 144;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010000xxxxx1xx011101xx
+ rev32. */
+ return 180;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010000xxxxx1xx01111x0x
+ fmul. */
+ return 622;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010000xxxxx1xx01111x1x
+ sha1h. */
+ return 533;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100010xxxx1xx011100xx
+ cmgt. */
+ return 152;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100010xxxx1xx011101xx
+ cmge. */
+ return 186;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100011xxxx1x0011100xx
+ frintn. */
+ return 164;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100011xxxx1x0011101xx
+ frinta. */
+ return 197;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100011xxxx1x101110xxx
+ frintp. */
+ return 174;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010001xxxxx1xx0111100x
+ fnmul. */
+ return 630;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010001xxxxx1xx0111101x
+ cmgt. */
+ return 393;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010001xxxxx1xx011111xx
+ cmge. */
+ return 411;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100100xx0x1xx011100xx
+ cls. */
+ return 148;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100100xx0x1xx011101xx
+ clz. */
+ return 183;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100100xx1x1xx01110xxx
+ aese. */
+ return 529;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100101xxxx1xx0111000x
+ sqxtn. */
+ return 158;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100101xxxx1xx0111001x
+ sqxtn2. */
+ return 159;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100101xxxx1xx0111010x
+ uqxtn. */
+ return 193;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100101xxxx1xx0111011x
+ uqxtn2. */
+ return 194;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010010xxxxx1xx0111100x
+ fmax. */
+ return 626;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010010xxxxx1xx0111101x
+ sqxtn. */
+ return 397;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010010xxxxx1xx011111xx
+ uqxtn. */
+ return 415;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100110xxx01xx011100xx
+ fcmgt. */
+ return 170;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100110xxx01xx011101xx
+ fcmge. */
+ return 206;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100110xxx01xx011110xx
+ fcmgt. */
+ return 402;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100110xxx01xx011111xx
+ fcmge. */
+ return 421;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100110xxx11x001110xxx
+ fmaxnmv. */
+ return 34;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100110xxx11x001111xxx
+ fmaxnmp. */
+ return 429;
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100110xxx11x101110xxx
+ fminnmv. */
+ return 36;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100110xxx11x101111xxx
+ fminnmp. */
+ return 432;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100111xxxx1x0011100xx
+ fcvtas. */
+ return 168;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100111xxxx1x0011101xx
+ fcvtau. */
+ return 201;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100111xxxx1x0011110xx
+ fcvtas. */
+ return 400;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100111xxxx1x0011111xx
+ fcvtau. */
+ return 419;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100111xxxx1x10111x0xx
+ urecpe. */
+ return 178;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0100111xxxx1x10111x1xx
+ ursqrte. */
+ return 212;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101000xxxx1xx011100xx
+ saddlp. */
+ return 146;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101000xxxx1xx011101xx
+ uaddlp. */
+ return 181;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101001xxxx1xx0111000x
+ xtn. */
+ return 156;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101001xxxx1xx0111001x
+ xtn2. */
+ return 157;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101001xxxx1xx0111010x
+ sqxtun. */
+ return 189;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101001xxxx1xx0111011x
+ sqxtun2. */
+ return 190;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010100xxxxx1xx0111100x
+ fadd. */
+ return 624;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010100xxxxx1xx0111101x
+ sha256su0. */
+ return 535;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010100xxxxx1xx011111xx
+ sqxtun. */
+ return 414;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101010xxx01xx01110xxx
+ cmlt. */
+ return 154;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101010xxx01xx01111xxx
+ cmlt. */
+ return 395;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101010xxx11xx0111x0xx
+ smaxv. */
+ return 28;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101010xxx11xx0111x1xx
+ umaxv. */
+ return 32;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101011xxx01x0011100xx
+ fcvtns. */
+ return 166;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101011xxx01x0011101xx
+ fcvtnu. */
+ return 199;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101011xxx01x0011110xx
+ fcvtns. */
+ return 398;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101011xxx01x0011111xx
+ fcvtnu. */
+ return 417;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101011xxx01x1011100xx
+ fcvtps. */
+ return 176;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101011xxx01x1011101xx
+ fcvtpu. */
+ return 210;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101011xxx01x1011110xx
+ fcvtps. */
+ return 405;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101011xxx01x1011111xx
+ fcvtpu. */
+ return 423;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101011xxx11xx0111x0xx
+ sminv. */
+ return 29;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101011xxx11xx0111x1xx
+ uminv. */
+ return 33;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101100xx0x1xx011100xx
+ sadalp. */
+ return 150;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101100xx0x1xx011101xx
+ uadalp. */
+ return 184;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101100xx1x1xx01110xxx
+ aesmc. */
+ return 531;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101101xxxx1xx0111000x
+ fcvtn. */
+ return 160;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101101xxxx1xx0111001x
+ fcvtn2. */
+ return 161;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101101xxxx1xx0111010x
+ fcvtxn. */
+ return 195;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0101101xxxx1xx0111011x
+ fcvtxn2. */
+ return 196;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010110xxxxx1xx011110xx
+ fmaxnm. */
+ return 628;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010110xxxxx1xx011111xx
+ fcvtxn. */
+ return 416;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010111xxxxx1xx01110xxx
+ fcmlt. */
+ return 172;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx010111xxxxx1xx01111xxx
+ fcmlt. */
+ return 404;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011000xxxxx1xx01110xxx
+ rev16. */
+ return 145;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011000xxxxx1xx01111x0x
+ fdiv. */
+ return 623;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011000xxxxx1xx01111x1x
+ sha1su1. */
+ return 534;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110010xxxx1xx011100xx
+ cmeq. */
+ return 153;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110010xxxx1xx011101xx
+ cmle. */
+ return 187;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110010xxxx1xx011110xx
+ cmeq. */
+ return 394;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110010xxxx1xx011111xx
+ cmle. */
+ return 412;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110011xxxx1x00111x0xx
+ frintm. */
+ return 165;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110011xxxx1x00111x1xx
+ frintx. */
+ return 198;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110011xxxx1x10111x0xx
+ frintz. */
+ return 175;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110011xxxx1x10111x1xx
+ frinti. */
+ return 209;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011010xxx0x1xx011100xx
+ cnt. */
+ return 149;
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011010xxx0x10x011101xx
+ not. */
+ return 203;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011010xxx0x11x011101xx
+ rbit. */
+ return 205;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011010xxx1x1xx01110xxx
+ aesd. */
+ return 530;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011010xxxxx1xx01111xxx
+ fmin. */
+ return 627;
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110110xxx01xx011100xx
+ fcmeq. */
+ return 171;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110110xxx01xx011101xx
+ fcmle. */
+ return 207;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110110xxx01xx011110xx
+ fcmeq. */
+ return 403;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110110xxx01xx011111xx
+ fcmle. */
+ return 422;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110110xxx11xx0111xxxx
+ faddp. */
+ return 430;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110111xxxx1x0011100xx
+ scvtf. */
+ return 169;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110111xxxx1x0011101xx
+ ucvtf. */
+ return 202;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110111xxxx1x0011110xx
+ scvtf. */
+ return 401;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110111xxxx1x0011111xx
+ ucvtf. */
+ return 420;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110111xxxx1x1011100xx
+ frecpe. */
+ return 179;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110111xxxx1x1011101xx
+ frsqrte. */
+ return 213;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110111xxxx1x1011110xx
+ frecpe. */
+ return 407;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0110111xxxx1x1011111xx
+ frsqrte. */
+ return 425;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111000xxx01xx011100xx
+ suqadd. */
+ return 147;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111000xxx01xx011101xx
+ usqadd. */
+ return 182;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111000xxx11xx011100xx
+ saddlv. */
+ return 27;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111000xxx11xx011101xx
+ uaddlv. */
+ return 31;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111001xxxx1xx01110x0x
+ shll. */
+ return 191;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111001xxxx1xx01110x1x
+ shll2. */
+ return 192;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011100xxxxx1xx0111100x
+ fsub. */
+ return 625;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011100xxxxx1xx0111101x
+ suqadd. */
+ return 391;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011100xxxxx1xx011111xx
+ usqadd. */
+ return 409;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111010xxxx1xx011100xx
+ abs. */
+ return 155;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111010xxxx1xx011101xx
+ neg. */
+ return 188;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111010xxxx1xx011110xx
+ abs. */
+ return 396;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111010xxxx1xx011111xx
+ neg. */
+ return 413;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111011xxx01x0011100xx
+ fcvtms. */
+ return 167;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111011xxx01x0011101xx
+ fcvtmu. */
+ return 200;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111011xxx01x0011110xx
+ fcvtms. */
+ return 399;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111011xxx01x0011111xx
+ fcvtmu. */
+ return 418;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111011xxx01x1011100xx
+ fcvtzs. */
+ return 177;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111011xxx01x1011101xx
+ fcvtzu. */
+ return 211;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111011xxx01x1011110xx
+ fcvtzs. */
+ return 406;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111011xxx01x1011111xx
+ fcvtzu. */
+ return 424;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111011xxx11xx01110xxx
+ addv. */
+ return 30;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111011xxx11xx01111xxx
+ addp. */
+ return 428;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111100xx0x1xx011100xx
+ sqabs. */
+ return 151;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111100xx0x1xx011101xx
+ sqneg. */
+ return 185;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111100xx1x1xx01110xxx
+ aesimc. */
+ return 532;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111101xxxx1xx01110x0x
+ fcvtl. */
+ return 162;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111101xxxx1xx01110x1x
+ fcvtl2. */
+ return 163;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011110xxxxx1xx0111100x
+ fminnm. */
+ return 629;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011110xxxxx1xx0111101x
+ sqabs. */
+ return 392;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx011110xxxxx1xx011111xx
+ sqneg. */
+ return 410;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111110xxx01xx0111x0xx
+ fabs. */
+ return 173;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111110xxx01xx0111x1xx
+ fneg. */
+ return 208;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111110xxx11x001110xxx
+ fmaxv. */
+ return 35;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111110xxx11x001111xxx
+ fmaxp. */
+ return 431;
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111110xxx11x101110xxx
+ fminv. */
+ return 37;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111110xxx11x101111xxx
+ fminp. */
+ return 433;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111111xxxx1xx01110xxx
+ fsqrt. */
+ return 214;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0111111xxxx1xx01111xxx
+ frecpx. */
+ return 408;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100000xxxxx1xx011100xx
+ shadd. */
+ return 221;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100000xxxxx1xx011101xx
+ uhadd. */
+ return 261;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100001xxxxx1xx011100xx
+ add. */
+ return 236;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100001xxxxx1xx011101xx
+ sub. */
+ return 276;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100010xxxxx1xx011100xx
+ sshl. */
+ return 228;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100010xxxxx1xx011101xx
+ ushl. */
+ return 268;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100011xxxxx1x0011100xx
+ fmaxnm. */
+ return 244;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100011xxxxx1x0011101xx
+ fmaxnmp. */
+ return 283;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100011xxxxx1x1011100xx
+ fminnm. */
+ return 253;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100011xxxxx1x1011101xx
+ fminnmp. */
+ return 292;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100100xxxxx1xx011100xx
+ shsub. */
+ return 224;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100100xxxxx1xx011101xx
+ uhsub. */
+ return 264;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100101xxxxx1xx011100xx
+ smaxp. */
+ return 240;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100101xxxxx1xx011101xx
+ umaxp. */
+ return 280;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100110xxxxx1xx011100xx
+ smax. */
+ return 232;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100110xxxxx1xx011101xx
+ umax. */
+ return 272;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100111xxxxx1x0011100xx
+ fcmeq. */
+ return 248;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100111xxxxx1x0011101xx
+ fcmge. */
+ return 286;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100111xxxxx1x101110xxx
+ fcmgt. */
+ return 294;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101000xxxxx1xx011100xx
+ srhadd. */
+ return 223;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101000xxxxx1xx011101xx
+ urhadd. */
+ return 263;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101001xxxxx1xx011100xx
+ mla. */
+ return 238;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101001xxxxx1xx011101xx
+ mls. */
+ return 278;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101010xxxxx1xx011100xx
+ srshl. */
+ return 230;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101010xxxxx1xx011101xx
+ urshl. */
+ return 270;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101011xxxxx1x0011100xx
+ fadd. */
+ return 246;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101011xxxxx1x0011101xx
+ faddp. */
+ return 284;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101011xxxxx1x1011100xx
+ fsub. */
+ return 255;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101011xxxxx1x1011101xx
+ fabd. */
+ return 293;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101100xxxxx1xx011100xx
+ cmgt. */
+ return 226;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101100xxxxx1xx011101xx
+ cmhi. */
+ return 266;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101101xxxxx1xx011100xx
+ sqdmulh. */
+ return 242;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101101xxxxx1xx011101xx
+ sqrdmulh. */
+ return 282;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101110xxxxx1xx011100xx
+ sabd. */
+ return 234;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101110xxxxx1xx011101xx
+ uabd. */
+ return 274;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101111xxxxx1x0011100xx
+ fmax. */
+ return 249;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101111xxxxx1x0011101xx
+ fmaxp. */
+ return 288;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101111xxxxx1x1011100xx
+ fmin. */
+ return 256;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101111xxxxx1x1011101xx
+ fminp. */
+ return 296;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxx0xxxxx10xxxxxxxxx1xx0111100x
+ fccmp. */
+ return 604;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxx1xxxxx10xxxxxxxxx1xx0111100x
+ fccmpe. */
+ return 605;
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx10000xxxxxx1xx0111101x
+ add. */
+ return 447;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx10001xxxxxx1xx0111101x
+ sshl. */
+ return 445;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1001xxxxxxx1xx0111101x
+ fcmeq. */
+ return 440;
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1010xxxxxxx1xx0111101x
+ srshl. */
+ return 446;
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1011x0xxxxx1xx0111101x
+ cmgt. */
+ return 443;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1011x1xxxxx1xx0111101x
+ sqdmulh. */
+ return 438;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx10000xxxxxx1xx011111xx
+ sub. */
+ return 463;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx10001xxxxxx1xx011111xx
+ ushl. */
+ return 461;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1001xxxxxxx1x0011111xx
+ fcmge. */
+ return 454;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1001xxxxxxx1x1011111xx
+ fcmgt. */
+ return 457;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1010x0xxxxx1xx011111xx
+ urshl. */
+ return 462;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1010x1xxxxx1xx011111xx
+ fabd. */
+ return 456;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1011x0xxxxx1xx011111xx
+ cmhi. */
+ return 459;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1011x1xxxxx1xx011111xx
+ sqrdmulh. */
+ return 453;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110000xxxxx1xx011100xx
+ sqadd. */
+ return 222;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110000xxxxx1xx011101xx
+ uqadd. */
+ return 262;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110001xxxxx1xx011100xx
+ cmtst. */
+ return 237;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110001xxxxx1xx011101xx
+ cmeq. */
+ return 277;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110010xxxxx1xx011100xx
+ sqshl. */
+ return 229;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110010xxxxx1xx011101xx
+ uqshl. */
+ return 269;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110011xxxxx1x001110xxx
+ fmla. */
+ return 245;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110011xxxxx1x101110xxx
+ fmls. */
+ return 254;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110100xxxxx1xx011100xx
+ sqsub. */
+ return 225;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110100xxxxx1xx011101xx
+ uqsub. */
+ return 265;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110101xxxxx1xx011100xx
+ sminp. */
+ return 241;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110101xxxxx1xx011101xx
+ uminp. */
+ return 281;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110110xxxxx1xx011100xx
+ smin. */
+ return 233;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110110xxxxx1xx011101xx
+ umin. */
+ return 273;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110111xxxxx1x001110xxx
+ facge. */
+ return 287;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110111xxxxx1x101110xxx
+ facgt. */
+ return 295;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111000xxxxx100011100xx
+ and. */
+ return 251;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111000xxxxx100011101xx
+ eor. */
+ return 290;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111000xxxxx101011100xx
+ orr. */
+ return 258;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111000xxxxx101011101xx
+ bit. */
+ return 297;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111000xxxxx110011100xx
+ bic. */
+ return 252;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111000xxxxx110011101xx
+ bsl. */
+ return 291;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111000xxxxx111011100xx
+ orn. */
+ return 260;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111000xxxxx111011101xx
+ bif. */
+ return 298;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111001xxxxx1xx011100xx
+ mul. */
+ return 239;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111001xxxxx1xx011101xx
+ pmul. */
+ return 279;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111010xxxxx1xx011100xx
+ sqrshl. */
+ return 231;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111010xxxxx1xx011101xx
+ uqrshl. */
+ return 271;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111011xxxxx1xx011100xx
+ fmulx. */
+ return 247;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111011xxxxx1xx011101xx
+ fmul. */
+ return 285;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111100xxxxx1xx011100xx
+ cmge. */
+ return 227;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111100xxxxx1xx011101xx
+ cmhs. */
+ return 267;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111101xxxxx1xx01110xxx
+ addp. */
+ return 243;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111110xxxxx1xx011100xx
+ saba. */
+ return 235;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111110xxxxx1xx011101xx
+ uaba. */
+ return 275;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111111xxxxx1x0011100xx
+ frecps. */
+ return 250;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111111xxxxx1x0011101xx
+ fdiv. */
+ return 289;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx111111xxxxx1x101110xxx
+ frsqrts. */
+ return 257;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11xxxxxxxxx1xx0111100x
+ fcsel. */
+ return 636;
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110000xxxxx1xx0111101x
+ sqadd. */
+ return 434;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110001xxxxx1xx0111101x
+ cmtst. */
+ return 448;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11001xxxxxx1xx0111101x
+ sqshl. */
+ return 436;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1101xxxxxxx1xx0111101x
+ sqsub. */
+ return 435;
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1110x0xxxxx1xx0111101x
+ sqrshl. */
+ return 437;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1110x1xxxxx1xx0111101x
+ fmulx. */
+ return 439;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11110xxxxxx1xx0111101x
+ cmge. */
+ return 444;
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11111xxxxxx1x00111101x
+ frecps. */
+ return 441;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11111xxxxxx1x10111101x
+ frsqrts. */
+ return 442;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110000xxxxx1xx011111xx
+ uqadd. */
+ return 449;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110001xxxxx1xx011111xx
+ cmeq. */
+ return 464;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11001xxxxxx1xx011111xx
+ uqshl. */
+ return 451;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11010xxxxxx1xx011111xx
+ uqsub. */
+ return 450;
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11011xxxxxx1x0011111xx
+ facge. */
+ return 455;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11011xxxxxx1x1011111xx
+ facgt. */
+ return 458;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1110xxxxxxx1xx011111xx
+ uqrshl. */
+ return 452;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1111xxxxxxx1xx011111xx
+ cmhs. */
+ return 460;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0000xxxxxxxx11110xxx
+ mla. */
+ return 110;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0010xxxxxxxx11110xxx
+ mls. */
+ return 113;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0100xxxxxxxx1111000x
+ smlal. */
+ return 92;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0100xxxxxxxx1111001x
+ smlal2. */
+ return 93;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0100xxxxxxxx1111010x
+ umlal. */
+ return 111;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0100xxxxxxxx1111011x
+ umlal2. */
+ return 112;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0110xxxxxxxx1111000x
+ smlsl. */
+ return 96;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0110xxxxxxxx1111001x
+ smlsl2. */
+ return 97;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0110xxxxxxxx1111010x
+ umlsl. */
+ return 114;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0110xxxxxxxx1111011x
+ umlsl2. */
+ return 115;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1000xxxxxxxx11110xxx
+ fmla. */
+ return 107;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1010xxxxxxxx11110xxx
+ fmls. */
+ return 108;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1100xxxxxxxx11110x0x
+ sqdmlal. */
+ return 94;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1100xxxxxxxx11110x1x
+ sqdmlal2. */
+ return 95;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1110xxxxxxxx11110x0x
+ sqdmlsl. */
+ return 98;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1110xxxxxxxx11110x1x
+ sqdmlsl2. */
+ return 99;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1x0xx0xxxxxxxx111100xx
+ movi. */
+ return 120;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1x0xx0xxxxxxxx111101xx
+ mvni. */
+ return 127;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1x1xx0xxxxxxxx111100xx
+ orr. */
+ return 121;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1x1xx0xxxxxxxx111101xx
+ bic. */
+ return 128;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx0xx1111100x
+ fmadd. */
+ return 631;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx1xx1111100x
+ fnmadd. */
+ return 633;
+ }
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0xx000xxxxxxxx1111101x
+ fmla. */
+ return 347;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0xx010xxxxxxxx1111101x
+ fmls. */
+ return 348;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0xx100xxxxxxxx1111101x
+ sqdmlal. */
+ return 342;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0xx110xxxxxxxx1111101x
+ sqdmlsl. */
+ return 343;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1x00x0xxxxxxxx1111101x
+ sshr. */
+ return 465;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1x01x0xxxxxxxx1111101x
+ srshr. */
+ return 467;
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1x1000xxxxxxxx1111101x
+ ssra. */
+ return 466;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1x1010xxxxxxxx1111101x
+ shl. */
+ return 469;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1x1100xxxxxxxx1111101x
+ srsra. */
+ return 468;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1x1110xxxxxxxx1111101x
+ sqshl. */
+ return 470;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx0000xxxxxxxx111111xx
+ ushr. */
+ return 475;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx0010xxxxxxxx111111xx
+ sri. */
+ return 479;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx0100xxxxxxxx111111xx
+ urshr. */
+ return 477;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx0110xxxxxxxx111111xx
+ sqshlu. */
+ return 481;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx1000xxxxxxxx111111xx
+ usra. */
+ return 476;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx1010xxxxxxxx111111xx
+ sli. */
+ return 480;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx1100xxxxxxxx111111xx
+ ursra. */
+ return 478;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx1110xxxxxxxx111111xx
+ uqshl. */
+ return 482;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0001xxxxxxxx11110xxx
+ mul. */
+ return 100;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0011xxxxxxxx11110xxx
+ sqdmulh. */
+ return 105;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x01x1xxxxxxxx1111000x
+ smull. */
+ return 101;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x01x1xxxxxxxx1111001x
+ smull2. */
+ return 102;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x01x1xxxxxxxx1111010x
+ umull. */
+ return 116;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x01x1xxxxxxxx1111011x
+ umull2. */
+ return 117;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1001xxxxxxxx111100xx
+ fmul. */
+ return 109;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1001xxxxxxxx111101xx
+ fmulx. */
+ return 118;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1011xxxxxxxx11110xxx
+ sqrdmulh. */
+ return 106;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x11x1xxxxxxxx11110x0x
+ sqdmull. */
+ return 103;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x11x1xxxxxxxx11110x1x
+ sqdmull2. */
+ return 104;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100x01xxxxxxxx111100xx
+ movi. */
+ return 122;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100x01xxxxxxxx111101xx
+ mvni. */
+ return 129;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101x01xxxxxxxx111100xx
+ orr. */
+ return 123;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101x01xxxxxxxx111101xx
+ bic. */
+ return 130;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx10x011xxxxxxxx111100xx
+ movi. */
+ return 124;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx10x011xxxxxxxx111101xx
+ mvni. */
+ return 131;
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100111xxxxxxxx111100xx
+ movi. */
+ return 125;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100111xxxxxxxx111101xx
+ movi. */
+ return 132;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101111xxxxxxxx111100xx
+ fmov. */
+ return 126;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101111xxxxxxxx111101xx
+ fmov. */
+ return 134;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110xx1xxxxxxxx1111000x
+ rshrn. */
+ return 307;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110xx1xxxxxxxx1111001x
+ rshrn2. */
+ return 308;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110xx1xxxxxxxx1111010x
+ sqrshrun. */
+ return 327;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110xx1xxxxxxxx1111011x
+ sqrshrun2. */
+ return 328;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1110x1xxxxxxxx1111000x
+ sqrshrn. */
+ return 311;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1110x1xxxxxxxx1111001x
+ sqrshrn2. */
+ return 312;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1110x1xxxxxxxx1111010x
+ uqrshrn. */
+ return 331;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1110x1xxxxxxxx1111011x
+ uqrshrn2. */
+ return 332;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1111x1xxxxxxxx111100xx
+ fcvtzs. */
+ return 316;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1111x1xxxxxxxx111101xx
+ fcvtzu. */
+ return 336;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx0xx1111100x
+ fmsub. */
+ return 632;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx1xx1111100x
+ fnmsub. */
+ return 634;
+ }
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0xx1xxxxxxxx1111101x
+ sqdmulh. */
+ return 345;
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1001xxxxxxxx1111101x
+ fmul. */
+ return 349;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1011xxxxxxxx1111101x
+ sqrdmulh. */
+ return 346;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x11x1xxxxxxxx1111101x
+ sqdmull. */
+ return 344;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100xx1xxxxxxxx1111101x
+ scvtf. */
+ return 473;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101xx1xxxxxxxx1111101x
+ sqshrn. */
+ return 471;
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11x0x1xxxxxxxx1111101x
+ sqrshrn. */
+ return 472;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx11x1x1xxxxxxxx1111101x
+ fcvtzs. */
+ return 474;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0xxxx1xxxxxxxx111111xx
+ fmulx. */
+ return 350;
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1000x1xxxxxxxx111111xx
+ sqshrun. */
+ return 483;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1001x1xxxxxxxx111111xx
+ ucvtf. */
+ return 487;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101xx1xxxxxxxx111111xx
+ uqshrn. */
+ return 485;
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110xx1xxxxxxxx111111xx
+ sqrshrun. */
+ return 484;
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1110x1xxxxxxxx111111xx
+ uqrshrn. */
+ return 486;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1111x1xxxxxxxx111111xx
+ fcvtzu. */
+ return 488;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+}
+
+/* Lookup opcode WORD in the opcode table. N.B. all alias
+ opcodes are ignored here. */
+
+const aarch64_opcode *
+aarch64_opcode_lookup (uint32_t word)
+{
+ return aarch64_opcode_table + aarch64_opcode_lookup_1 (word);
+}
+
+const aarch64_opcode *
+aarch64_find_next_opcode (const aarch64_opcode *opcode)
+{
+ /* Use the index as the key to locate the next opcode. */
+ int key = opcode - aarch64_opcode_table;
+ int value;
+ switch (key)
+ {
+ case 727: value = 731; break; /* stnp --> stp. */
+ case 731: return NULL; /* stp --> NULL. */
+ case 728: value = 732; break; /* ldnp --> ldp. */
+ case 732: return NULL; /* ldp --> NULL. */
+ case 351: value = 352; break; /* st4 --> st1. */
+ case 352: value = 353; break; /* st1 --> st2. */
+ case 353: value = 354; break; /* st2 --> st3. */
+ case 354: return NULL; /* st3 --> NULL. */
+ case 359: value = 360; break; /* st4 --> st1. */
+ case 360: value = 361; break; /* st1 --> st2. */
+ case 361: value = 362; break; /* st2 --> st3. */
+ case 362: return NULL; /* st3 --> NULL. */
+ case 355: value = 356; break; /* ld4 --> ld1. */
+ case 356: value = 357; break; /* ld1 --> ld2. */
+ case 357: value = 358; break; /* ld2 --> ld3. */
+ case 358: return NULL; /* ld3 --> NULL. */
+ case 371: value = 373; break; /* ld1 --> ld1r. */
+ case 373: return NULL; /* ld1r --> NULL. */
+ case 375: value = 377; break; /* ld2 --> ld2r. */
+ case 377: return NULL; /* ld2r --> NULL. */
+ case 372: value = 374; break; /* ld3 --> ld3r. */
+ case 374: return NULL; /* ld3r --> NULL. */
+ case 376: value = 378; break; /* ld4 --> ld4r. */
+ case 378: return NULL; /* ld4r --> NULL. */
+ case 363: value = 364; break; /* ld4 --> ld1. */
+ case 364: value = 365; break; /* ld1 --> ld2. */
+ case 365: value = 366; break; /* ld2 --> ld3. */
+ case 366: return NULL; /* ld3 --> NULL. */
+ case 383: value = 385; break; /* ld1 --> ld1r. */
+ case 385: return NULL; /* ld1r --> NULL. */
+ case 384: value = 386; break; /* ld3 --> ld3r. */
+ case 386: return NULL; /* ld3r --> NULL. */
+ case 387: value = 389; break; /* ld2 --> ld2r. */
+ case 389: return NULL; /* ld2r --> NULL. */
+ case 388: value = 390; break; /* ld4 --> ld4r. */
+ case 390: return NULL; /* ld4r --> NULL. */
+ case 120: value = 299; break; /* movi --> sshr. */
+ case 299: value = 301; break; /* sshr --> srshr. */
+ case 301: return NULL; /* srshr --> NULL. */
+ case 127: value = 317; break; /* mvni --> ushr. */
+ case 317: value = 319; break; /* ushr --> urshr. */
+ case 319: value = 321; break; /* urshr --> sri. */
+ case 321: value = 323; break; /* sri --> sqshlu. */
+ case 323: return NULL; /* sqshlu --> NULL. */
+ case 121: value = 300; break; /* orr --> ssra. */
+ case 300: value = 302; break; /* ssra --> srsra. */
+ case 302: value = 303; break; /* srsra --> shl. */
+ case 303: value = 304; break; /* shl --> sqshl. */
+ case 304: return NULL; /* sqshl --> NULL. */
+ case 128: value = 318; break; /* bic --> usra. */
+ case 318: value = 320; break; /* usra --> ursra. */
+ case 320: value = 322; break; /* ursra --> sli. */
+ case 322: value = 324; break; /* sli --> uqshl. */
+ case 324: return NULL; /* uqshl --> NULL. */
+ case 122: value = 305; break; /* movi --> shrn. */
+ case 305: value = 306; break; /* shrn --> shrn2. */
+ case 306: value = 313; break; /* shrn2 --> sshll. */
+ case 313: value = 314; break; /* sshll --> sshll2. */
+ case 314: return NULL; /* sshll2 --> NULL. */
+ case 129: value = 325; break; /* mvni --> sqshrun. */
+ case 325: value = 326; break; /* sqshrun --> sqshrun2. */
+ case 326: value = 333; break; /* sqshrun2 --> ushll. */
+ case 333: value = 334; break; /* ushll --> ushll2. */
+ case 334: return NULL; /* ushll2 --> NULL. */
+ case 123: value = 309; break; /* orr --> sqshrn. */
+ case 309: value = 310; break; /* sqshrn --> sqshrn2. */
+ case 310: return NULL; /* sqshrn2 --> NULL. */
+ case 130: value = 329; break; /* bic --> uqshrn. */
+ case 329: value = 330; break; /* uqshrn --> uqshrn2. */
+ case 330: return NULL; /* uqshrn2 --> NULL. */
+ case 125: value = 315; break; /* movi --> scvtf. */
+ case 315: return NULL; /* scvtf --> NULL. */
+ case 132: value = 133; break; /* movi --> movi. */
+ case 133: value = 335; break; /* movi --> ucvtf. */
+ case 335: return NULL; /* ucvtf --> NULL. */
+ default: return NULL;
+ }
+
+ return aarch64_opcode_table + value;
+}
+
+const aarch64_opcode *
+aarch64_find_alias_opcode (const aarch64_opcode *opcode)
+{
+ /* Use the index as the key to locate the alias opcode. */
+ int key = opcode - aarch64_opcode_table;
+ int value;
+ switch (key)
+ {
+ case 2: value = 3; break; /* sbc --> ngc. */
+ case 4: value = 5; break; /* sbcs --> ngcs. */
+ case 7: value = 8; break; /* adds --> cmn. */
+ case 10: value = 11; break; /* subs --> cmp. */
+ case 12: value = 13; break; /* add --> mov. */
+ case 14: value = 15; break; /* adds --> cmn. */
+ case 17: value = 18; break; /* subs --> cmp. */
+ case 20: value = 21; break; /* adds --> cmn. */
+ case 22: value = 23; break; /* sub --> neg. */
+ case 24: value = 26; break; /* subs --> negs. */
+ case 138: value = 139; break; /* umov --> mov. */
+ case 140: value = 141; break; /* ins --> mov. */
+ case 142: value = 143; break; /* ins --> mov. */
+ case 203: value = 204; break; /* not --> mvn. */
+ case 258: value = 259; break; /* orr --> mov. */
+ case 426: value = 427; break; /* dup --> mov. */
+ case 489: value = 494; break; /* sbfm --> sxtw. */
+ case 496: value = 498; break; /* bfm --> bfxil. */
+ case 499: value = 503; break; /* ubfm --> uxth. */
+ case 521: value = 523; break; /* csinc --> cset. */
+ case 524: value = 526; break; /* csinv --> csetm. */
+ case 527: value = 528; break; /* csneg --> cneg. */
+ case 552: value = 553; break; /* lslv --> lsl. */
+ case 554: value = 555; break; /* lsrv --> lsr. */
+ case 556: value = 557; break; /* asrv --> asr. */
+ case 558: value = 559; break; /* rorv --> ror. */
+ case 560: value = 561; break; /* madd --> mul. */
+ case 562: value = 563; break; /* msub --> mneg. */
+ case 564: value = 565; break; /* smaddl --> smull. */
+ case 566: value = 567; break; /* smsubl --> smnegl. */
+ case 569: value = 570; break; /* umaddl --> umull. */
+ case 571: value = 572; break; /* umsubl --> umnegl. */
+ case 582: value = 583; break; /* extr --> ror. */
+ case 681: value = 683; break; /* sturb --> strb. */
+ case 682: value = 684; break; /* ldurb --> ldrb. */
+ case 685: value = 686; break; /* ldursb --> ldrsb. */
+ case 687: value = 689; break; /* stur --> str. */
+ case 688: value = 690; break; /* ldur --> ldr. */
+ case 691: value = 693; break; /* sturh --> strh. */
+ case 692: value = 694; break; /* ldurh --> ldrh. */
+ case 695: value = 696; break; /* ldursh --> ldrsh. */
+ case 697: value = 699; break; /* stur --> str. */
+ case 698: value = 700; break; /* ldur --> ldr. */
+ case 701: value = 702; break; /* ldursw --> ldrsw. */
+ case 703: value = 704; break; /* prfum --> prfm. */
+ case 745: value = 746; break; /* and --> bic. */
+ case 747: value = 748; break; /* orr --> mov. */
+ case 750: value = 751; break; /* ands --> tst. */
+ case 754: value = 756; break; /* orr --> uxtw. */
+ case 757: value = 758; break; /* orn --> mvn. */
+ case 761: value = 762; break; /* ands --> tst. */
+ case 764: value = 765; break; /* movn --> mov. */
+ case 766: value = 767; break; /* movz --> mov. */
+ case 772: value = 778; break; /* hint --> sevl. */
+ case 783: value = 787; break; /* sys --> tlbi. */
+ default: return NULL;
+ }
+
+ return aarch64_opcode_table + value;
+}
+
+const aarch64_opcode *
+aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)
+{
+ /* Use the index as the key to locate the next opcode. */
+ int key = opcode - aarch64_opcode_table;
+ int value;
+ switch (key)
+ {
+ case 26: value = 25; break; /* negs --> cmp. */
+ case 494: value = 493; break; /* sxtw --> sxth. */
+ case 493: value = 492; break; /* sxth --> sxtb. */
+ case 492: value = 495; break; /* sxtb --> asr. */
+ case 495: value = 491; break; /* asr --> sbfx. */
+ case 491: value = 490; break; /* sbfx --> sbfiz. */
+ case 498: value = 497; break; /* bfxil --> bfi. */
+ case 503: value = 502; break; /* uxth --> uxtb. */
+ case 502: value = 505; break; /* uxtb --> lsr. */
+ case 505: value = 504; break; /* lsr --> lsl. */
+ case 504: value = 501; break; /* lsl --> ubfx. */
+ case 501: value = 500; break; /* ubfx --> ubfiz. */
+ case 523: value = 522; break; /* cset --> cinc. */
+ case 526: value = 525; break; /* csetm --> cinv. */
+ case 756: value = 755; break; /* uxtw --> mov. */
+ case 778: value = 777; break; /* sevl --> sev. */
+ case 777: value = 776; break; /* sev --> wfi. */
+ case 776: value = 775; break; /* wfi --> wfe. */
+ case 775: value = 774; break; /* wfe --> yield. */
+ case 774: value = 773; break; /* yield --> nop. */
+ case 787: value = 786; break; /* tlbi --> ic. */
+ case 786: value = 785; break; /* ic --> dc. */
+ case 785: value = 784; break; /* dc --> at. */
+ default: return NULL;
+ }
+
+ return aarch64_opcode_table + value;
+}
+
+int
+aarch64_extract_operand (const aarch64_operand *self,
+ aarch64_opnd_info *info,
+ aarch64_insn code, const aarch64_inst *inst)
+{
+ /* Use the index as the key. */
+ int key = self - aarch64_operands;
+ switch (key)
+ {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 9:
+ case 10:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 18:
+ case 19:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 24:
+ case 25:
+ case 26:
+ case 34:
+ case 35:
+ return aarch64_ext_regno (self, info, code, inst);
+ case 8:
+ return aarch64_ext_regrt_sysins (self, info, code, inst);
+ case 11:
+ return aarch64_ext_reg_extended (self, info, code, inst);
+ case 12:
+ return aarch64_ext_reg_shifted (self, info, code, inst);
+ case 17:
+ return aarch64_ext_ft (self, info, code, inst);
+ case 27:
+ case 28:
+ case 29:
+ return aarch64_ext_reglane (self, info, code, inst);
+ case 30:
+ return aarch64_ext_reglist (self, info, code, inst);
+ case 31:
+ return aarch64_ext_ldst_reglist (self, info, code, inst);
+ case 32:
+ return aarch64_ext_ldst_reglist_r (self, info, code, inst);
+ case 33:
+ return aarch64_ext_ldst_elemlist (self, info, code, inst);
+ case 36:
+ case 45:
+ case 46:
+ case 47:
+ case 48:
+ case 49:
+ case 50:
+ case 51:
+ case 52:
+ case 53:
+ case 54:
+ case 55:
+ case 56:
+ case 57:
+ case 64:
+ case 65:
+ case 66:
+ case 67:
+ case 68:
+ return aarch64_ext_imm (self, info, code, inst);
+ case 37:
+ case 38:
+ return aarch64_ext_advsimd_imm_shift (self, info, code, inst);
+ case 39:
+ case 40:
+ case 41:
+ return aarch64_ext_advsimd_imm_modified (self, info, code, inst);
+ case 42:
+ return aarch64_ext_shll_imm (self, info, code, inst);
+ case 58:
+ return aarch64_ext_limm (self, info, code, inst);
+ case 59:
+ return aarch64_ext_aimm (self, info, code, inst);
+ case 60:
+ return aarch64_ext_imm_half (self, info, code, inst);
+ case 61:
+ return aarch64_ext_fbits (self, info, code, inst);
+ case 63:
+ return aarch64_ext_cond (self, info, code, inst);
+ case 69:
+ case 75:
+ return aarch64_ext_addr_simple (self, info, code, inst);
+ case 70:
+ return aarch64_ext_addr_regoff (self, info, code, inst);
+ case 71:
+ case 72:
+ case 73:
+ return aarch64_ext_addr_simm (self, info, code, inst);
+ case 74:
+ return aarch64_ext_addr_uimm12 (self, info, code, inst);
+ case 76:
+ return aarch64_ext_simd_addr_post (self, info, code, inst);
+ case 77:
+ return aarch64_ext_sysreg (self, info, code, inst);
+ case 78:
+ return aarch64_ext_pstatefield (self, info, code, inst);
+ case 79:
+ case 80:
+ case 81:
+ case 82:
+ return aarch64_ext_sysins_op (self, info, code, inst);
+ case 83:
+ case 84:
+ return aarch64_ext_barrier (self, info, code, inst);
+ case 85:
+ return aarch64_ext_prfop (self, info, code, inst);
+ default: assert (0); abort ();
+ }
+}
--- /dev/null
+/* aarch64-dis.c -- AArch64 disassembler.
+ Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include "bfd_stdint.h"
+#include "dis-asm.h"
+#include "libiberty.h"
+#include "opintl.h"
+#include "aarch64-dis.h"
+
+#if !defined(EMBEDDED_ENV)
+#define SYMTAB_AVAILABLE 1
+#include "elf-bfd.h"
+#include "elf/aarch64.h"
+#endif
+
+#define ERR_OK 0
+#define ERR_UND -1
+#define ERR_UNP -3
+#define ERR_NYI -5
+
+#define INSNLEN 4
+
+/* Cached mapping symbol state. */
+enum map_type
+{
+ MAP_INSN,
+ MAP_DATA
+};
+
+static enum map_type last_type;
+static int last_mapping_sym = -1;
+static bfd_vma last_mapping_addr = 0;
+
+/* Other options */
+static int no_aliases = 0; /* If set disassemble as most general inst. */
+\f
+
+static void
+set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED)
+{
+}
+
+static void
+parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED)
+{
+ /* Try to match options that are simple flags */
+ if (CONST_STRNEQ (option, "no-aliases"))
+ {
+ no_aliases = 1;
+ return;
+ }
+
+ if (CONST_STRNEQ (option, "aliases"))
+ {
+ no_aliases = 0;
+ return;
+ }
+
+#ifdef DEBUG_AARCH64
+ if (CONST_STRNEQ (option, "debug_dump"))
+ {
+ debug_dump = 1;
+ return;
+ }
+#endif /* DEBUG_AARCH64 */
+
+ /* Invalid option. */
+ fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
+}
+
+static void
+parse_aarch64_dis_options (const char *options)
+{
+ const char *option_end;
+
+ if (options == NULL)
+ return;
+
+ while (*options != '\0')
+ {
+ /* Skip empty options. */
+ if (*options == ',')
+ {
+ options++;
+ continue;
+ }
+
+ /* We know that *options is neither NUL or a comma. */
+ option_end = options + 1;
+ while (*option_end != ',' && *option_end != '\0')
+ option_end++;
+
+ parse_aarch64_dis_option (options, option_end - options);
+
+ /* Go on to the next one. If option_end points to a comma, it
+ will be skipped above. */
+ options = option_end;
+ }
+}
+\f
+/* Functions doing the instruction disassembling. */
+
+/* The unnamed arguments consist of the number of fields and information about
+ these fields where the VALUE will be extracted from CODE and returned.
+ MASK can be zero or the base mask of the opcode.
+
+ N.B. the fields are required to be in such an order than the most signficant
+ field for VALUE comes the first, e.g. the <index> in
+ SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
+ is encoded in H:L:M in some cases, the the fields H:L:M should be passed in
+ the order of H, L, M. */
+
+static inline aarch64_insn
+extract_fields (aarch64_insn code, aarch64_insn mask, ...)
+{
+ uint32_t num;
+ const aarch64_field *field;
+ enum aarch64_field_kind kind;
+ va_list va;
+
+ va_start (va, mask);
+ num = va_arg (va, uint32_t);
+ assert (num <= 5);
+ aarch64_insn value = 0x0;
+ while (num--)
+ {
+ kind = va_arg (va, enum aarch64_field_kind);
+ field = &fields[kind];
+ value <<= field->width;
+ value |= extract_field (kind, code, mask);
+ }
+ return value;
+}
+
+/* Sign-extend bit I of VALUE. */
+static inline int32_t
+sign_extend (aarch64_insn value, unsigned i)
+{
+ uint32_t ret = value;
+
+ assert (i < 32);
+ if ((value >> i) & 0x1)
+ {
+ uint32_t val = (uint32_t)(-1) << i;
+ ret = ret | val;
+ }
+ return (int32_t) ret;
+}
+
+/* N.B. the following inline helpfer functions create a dependency on the
+ order of operand qualifier enumerators. */
+
+/* Given VALUE, return qualifier for a general purpose register. */
+static inline enum aarch64_opnd_qualifier
+get_greg_qualifier_from_value (aarch64_insn value)
+{
+ enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_W + value;
+ assert (value <= 0x1
+ && aarch64_get_qualifier_standard_value (qualifier) == value);
+ return qualifier;
+}
+
+/* Given VALUE, return qualifier for a vector register. */
+static inline enum aarch64_opnd_qualifier
+get_vreg_qualifier_from_value (aarch64_insn value)
+{
+ enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value;
+
+ assert (value <= 0x8
+ && aarch64_get_qualifier_standard_value (qualifier) == value);
+ return qualifier;
+}
+
+/* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */
+static inline enum aarch64_opnd_qualifier
+get_sreg_qualifier_from_value (aarch64_insn value)
+{
+ enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value;
+
+ assert (value <= 0x4
+ && aarch64_get_qualifier_standard_value (qualifier) == value);
+ return qualifier;
+}
+
+/* Given the instruction in *INST which is probably half way through the
+ decoding and our caller wants to know the expected qualifier for operand
+ I. Return such a qualifier if we can establish it; otherwise return
+ AARCH64_OPND_QLF_NIL. */
+
+static aarch64_opnd_qualifier_t
+get_expected_qualifier (const aarch64_inst *inst, int i)
+{
+ aarch64_opnd_qualifier_seq_t qualifiers;
+ /* Should not be called if the qualifier is known. */
+ assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL);
+ if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list,
+ i, qualifiers))
+ return qualifiers[i];
+ else
+ return AARCH64_OPND_QLF_NIL;
+}
+
+/* Operand extractors. */
+
+int
+aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
+ const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ info->reg.regno = extract_field (self->fields[0], code, 0);
+ return 1;
+}
+
+/* e.g. IC <ic_op>{, <Xt>}. */
+int
+aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
+ const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ info->reg.regno = extract_field (self->fields[0], code, 0);
+ assert (info->idx == 1
+ && (aarch64_get_operand_class (inst->operands[0].type)
+ == AARCH64_OPND_CLASS_SYSTEM));
+ /* This will make the constraint checking happy and more importantly will
+ help the disassembler determine whether this operand is optional or
+ not. */
+ info->present = inst->operands[0].sysins_op->has_xt;
+
+ return 1;
+}
+
+/* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
+int
+aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
+ const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* regno */
+ info->reglane.regno = extract_field (self->fields[0], code,
+ inst->opcode->mask);
+
+ /* Index and/or type. */
+ if (inst->opcode->iclass == asisdone
+ || inst->opcode->iclass == asimdins)
+ {
+ if (info->type == AARCH64_OPND_En
+ && inst->opcode->operands[0] == AARCH64_OPND_Ed)
+ {
+ unsigned shift;
+ /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
+ assert (info->idx == 1); /* Vn */
+ aarch64_insn value = extract_field (FLD_imm4, code, 0);
+ /* Depend on AARCH64_OPND_Ed to determine the qualifier. */
+ info->qualifier = get_expected_qualifier (inst, info->idx);
+ shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
+ info->reglane.index = value >> shift;
+ }
+ else
+ {
+ /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
+ imm5<3:0> <V>
+ 0000 RESERVED
+ xxx1 B
+ xx10 H
+ x100 S
+ 1000 D */
+ int pos = -1;
+ aarch64_insn value = extract_field (FLD_imm5, code, 0);
+ while (++pos <= 3 && (value & 0x1) == 0)
+ value >>= 1;
+ if (pos > 3)
+ return 0;
+ info->qualifier = get_sreg_qualifier_from_value (pos);
+ info->reglane.index = (unsigned) (value >> 1);
+ }
+ }
+ else
+ {
+ /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
+ or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
+
+ /* Need information in other operand(s) to help decoding. */
+ info->qualifier = get_expected_qualifier (inst, info->idx);
+ switch (info->qualifier)
+ {
+ case AARCH64_OPND_QLF_S_H:
+ /* h:l:m */
+ info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
+ FLD_M);
+ info->reglane.regno &= 0xf;
+ break;
+ case AARCH64_OPND_QLF_S_S:
+ /* h:l */
+ info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
+ break;
+ case AARCH64_OPND_QLF_S_D:
+ /* H */
+ info->reglane.index = extract_field (FLD_H, code, 0);
+ break;
+ default:
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+int
+aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info,
+ const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* R */
+ info->reglist.first_regno = extract_field (self->fields[0], code, 0);
+ /* len */
+ info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1;
+ return 1;
+}
+
+/* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
+int
+aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info, const aarch64_insn code,
+ const aarch64_inst *inst)
+{
+ aarch64_insn value;
+ /* Number of elements in each structure to be loaded/stored. */
+ unsigned expected_num = get_opcode_dependent_value (inst->opcode);
+
+ struct
+ {
+ unsigned is_reserved;
+ unsigned num_regs;
+ unsigned num_elements;
+ } data [] =
+ { {0, 4, 4},
+ {1, 4, 4},
+ {0, 4, 1},
+ {0, 4, 2},
+ {0, 3, 3},
+ {1, 3, 3},
+ {0, 3, 1},
+ {0, 1, 1},
+ {0, 2, 2},
+ {1, 2, 2},
+ {0, 2, 1},
+ };
+
+ /* Rt */
+ info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
+ /* opcode */
+ value = extract_field (FLD_opcode, code, 0);
+ if (expected_num != data[value].num_elements || data[value].is_reserved)
+ return 0;
+ info->reglist.num_regs = data[value].num_regs;
+
+ return 1;
+}
+
+/* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
+ lanes instructions. */
+int
+aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info, const aarch64_insn code,
+ const aarch64_inst *inst)
+{
+ aarch64_insn value;
+
+ /* Rt */
+ info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
+ /* S */
+ value = extract_field (FLD_S, code, 0);
+
+ /* Number of registers is equal to the number of elements in
+ each structure to be loaded/stored. */
+ info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
+ assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
+
+ /* Except when it is LD1R. */
+ if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1)
+ info->reglist.num_regs = 2;
+
+ return 1;
+}
+
+/* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
+ load/store single element instructions. */
+int
+aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info, const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ aarch64_field field = {0, 0};
+ aarch64_insn QSsize; /* fields Q:S:size. */
+ aarch64_insn opcodeh2; /* opcode<2:1> */
+
+ /* Rt */
+ info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
+
+ /* Decode the index, opcode<2:1> and size. */
+ gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
+ opcodeh2 = extract_field_2 (&field, code, 0);
+ QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size);
+ switch (opcodeh2)
+ {
+ case 0x0:
+ info->qualifier = AARCH64_OPND_QLF_S_B;
+ /* Index encoded in "Q:S:size". */
+ info->reglist.index = QSsize;
+ break;
+ case 0x1:
+ info->qualifier = AARCH64_OPND_QLF_S_H;
+ /* Index encoded in "Q:S:size<1>". */
+ info->reglist.index = QSsize >> 1;
+ break;
+ case 0x2:
+ if ((QSsize & 0x1) == 0)
+ {
+ info->qualifier = AARCH64_OPND_QLF_S_S;
+ /* Index encoded in "Q:S". */
+ info->reglist.index = QSsize >> 2;
+ }
+ else
+ {
+ info->qualifier = AARCH64_OPND_QLF_S_D;
+ /* Index encoded in "Q". */
+ info->reglist.index = QSsize >> 3;
+ if (extract_field (FLD_S, code, 0))
+ /* UND */
+ return 0;
+ }
+ break;
+ default:
+ return 0;
+ }
+
+ info->reglist.has_index = 1;
+ info->reglist.num_regs = 0;
+ /* Number of registers is equal to the number of elements in
+ each structure to be loaded/stored. */
+ info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
+ assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
+
+ return 1;
+}
+
+/* Decode fields immh:immb and/or Q for e.g.
+ SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
+ or SSHR <V><d>, <V><n>, #<shift>. */
+
+int
+aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info, const aarch64_insn code,
+ const aarch64_inst *inst)
+{
+ int pos;
+ aarch64_insn Q, imm, immh;
+ enum aarch64_insn_class iclass = inst->opcode->iclass;
+
+ immh = extract_field (FLD_immh, code, 0);
+ if (immh == 0)
+ return 0;
+ imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb);
+ pos = 4;
+ /* Get highest set bit in immh. */
+ while (--pos >= 0 && (immh & 0x8) == 0)
+ immh <<= 1;
+
+ assert ((iclass == asimdshf || iclass == asisdshf)
+ && (info->type == AARCH64_OPND_IMM_VLSR
+ || info->type == AARCH64_OPND_IMM_VLSL));
+
+ if (iclass == asimdshf)
+ {
+ Q = extract_field (FLD_Q, code, 0);
+ /* immh Q <T>
+ 0000 x SEE AdvSIMD modified immediate
+ 0001 0 8B
+ 0001 1 16B
+ 001x 0 4H
+ 001x 1 8H
+ 01xx 0 2S
+ 01xx 1 4S
+ 1xxx 0 RESERVED
+ 1xxx 1 2D */
+ info->qualifier =
+ get_vreg_qualifier_from_value ((pos << 1) | (int) Q);
+ }
+ else
+ info->qualifier = get_sreg_qualifier_from_value (pos);
+
+ if (info->type == AARCH64_OPND_IMM_VLSR)
+ /* immh <shift>
+ 0000 SEE AdvSIMD modified immediate
+ 0001 (16-UInt(immh:immb))
+ 001x (32-UInt(immh:immb))
+ 01xx (64-UInt(immh:immb))
+ 1xxx (128-UInt(immh:immb)) */
+ info->imm.value = (16 << pos) - imm;
+ else
+ /* immh:immb
+ immh <shift>
+ 0000 SEE AdvSIMD modified immediate
+ 0001 (UInt(immh:immb)-8)
+ 001x (UInt(immh:immb)-16)
+ 01xx (UInt(immh:immb)-32)
+ 1xxx (UInt(immh:immb)-64) */
+ info->imm.value = imm - (8 << pos);
+
+ return 1;
+}
+
+/* Decode shift immediate for e.g. sshr (imm). */
+int
+aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info, const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ int64_t imm;
+ aarch64_insn val;
+ val = extract_field (FLD_size, code, 0);
+ switch (val)
+ {
+ case 0: imm = 8; break;
+ case 1: imm = 16; break;
+ case 2: imm = 32; break;
+ default: return 0;
+ }
+ info->imm.value = imm;
+ return 1;
+}
+
+/* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
+ value in the field(s) will be extracted as unsigned immediate value. */
+int
+aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
+ const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ int64_t imm;
+ /* Maximum of two fields to extract. */
+ assert (self->fields[2] == FLD_NIL);
+
+ if (self->fields[1] == FLD_NIL)
+ imm = extract_field (self->fields[0], code, 0);
+ else
+ /* e.g. TBZ b5:b40. */
+ imm = extract_fields (code, 0, 2, self->fields[0], self->fields[1]);
+
+ if (info->type == AARCH64_OPND_FPIMM)
+ info->imm.is_fp = 1;
+
+ if (operand_need_sign_extension (self))
+ imm = sign_extend (imm, get_operand_fields_width (self) - 1);
+
+ if (operand_need_shift_by_two (self))
+ imm <<= 2;
+
+ if (info->type == AARCH64_OPND_ADDR_ADRP)
+ imm <<= 12;
+
+ info->imm.value = imm;
+ return 1;
+}
+
+/* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
+int
+aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info,
+ const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ aarch64_ext_imm (self, info, code, inst);
+ info->shifter.kind = AARCH64_MOD_LSL;
+ info->shifter.amount = extract_field (FLD_hw, code, 0) << 4;
+ return 1;
+}
+
+/* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
+ MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
+int
+aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ uint64_t imm;
+ enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
+ aarch64_field field = {0, 0};
+
+ assert (info->idx == 1);
+
+ if (info->type == AARCH64_OPND_SIMD_FPIMM)
+ info->imm.is_fp = 1;
+
+ /* a:b:c:d:e:f:g:h */
+ imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh);
+ if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8)
+ {
+ /* Either MOVI <Dd>, #<imm>
+ or MOVI <Vd>.2D, #<imm>.
+ <imm> is a 64-bit immediate
+ 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
+ encoded in "a:b:c:d:e:f:g:h". */
+ int i;
+ unsigned abcdefgh = imm;
+ for (imm = 0ull, i = 0; i < 8; i++)
+ if (((abcdefgh >> i) & 0x1) != 0)
+ imm |= 0xffull << (8 * i);
+ }
+ info->imm.value = imm;
+
+ /* cmode */
+ info->qualifier = get_expected_qualifier (inst, info->idx);
+ switch (info->qualifier)
+ {
+ case AARCH64_OPND_QLF_NIL:
+ /* no shift */
+ info->shifter.kind = AARCH64_MOD_NONE;
+ return 1;
+ case AARCH64_OPND_QLF_LSL:
+ /* shift zeros */
+ info->shifter.kind = AARCH64_MOD_LSL;
+ switch (aarch64_get_qualifier_esize (opnd0_qualifier))
+ {
+ case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */
+ case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */
+ default: assert (0); return 0;
+ }
+ /* 00: 0; 01: 8; 10:16; 11:24. */
+ info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
+ break;
+ case AARCH64_OPND_QLF_MSL:
+ /* shift ones */
+ info->shifter.kind = AARCH64_MOD_MSL;
+ gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */
+ info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8;
+ break;
+ default:
+ assert (0);
+ return 0;
+ }
+
+ return 1;
+}
+
+/* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
+int
+aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info, const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ info->imm.value = 64- extract_field (FLD_scale, code, 0);
+ return 1;
+}
+
+/* Decode arithmetic immediate for e.g.
+ SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
+int
+aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info, const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ aarch64_insn value;
+
+ info->shifter.kind = AARCH64_MOD_LSL;
+ /* shift */
+ value = extract_field (FLD_shift, code, 0);
+ if (value >= 2)
+ return 0;
+ info->shifter.amount = value ? 12 : 0;
+ /* imm12 (unsigned) */
+ info->imm.value = extract_field (FLD_imm12, code, 0);
+
+ return 1;
+}
+
+/* Decode logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
+
+int
+aarch64_ext_limm (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info, const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ uint64_t imm, mask;
+ uint32_t sf;
+ uint32_t N, R, S;
+ unsigned simd_size;
+ aarch64_insn value;
+
+ value = extract_fields (code, 0, 3, FLD_N, FLD_immr, FLD_imms);
+ assert (inst->operands[0].qualifier == AARCH64_OPND_QLF_W
+ || inst->operands[0].qualifier == AARCH64_OPND_QLF_X);
+ sf = aarch64_get_qualifier_esize (inst->operands[0].qualifier) != 4;
+
+ /* value is N:immr:imms. */
+ S = value & 0x3f;
+ R = (value >> 6) & 0x3f;
+ N = (value >> 12) & 0x1;
+
+ if (sf == 0 && N == 1)
+ return 0;
+
+ /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
+ (in other words, right rotated by R), then replicated. */
+ if (N != 0)
+ {
+ simd_size = 64;
+ mask = 0xffffffffffffffffull;
+ }
+ else
+ {
+ switch (S)
+ {
+ case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32; break;
+ case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break;
+ case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break;
+ case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break;
+ case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break;
+ default: return 0;
+ }
+ mask = (1ull << simd_size) - 1;
+ /* Top bits are IGNORED. */
+ R &= simd_size - 1;
+ }
+ /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
+ if (S == simd_size - 1)
+ return 0;
+ /* S+1 consecutive bits to 1. */
+ /* NOTE: S can't be 63 due to detection above. */
+ imm = (1ull << (S + 1)) - 1;
+ /* Rotate to the left by simd_size - R. */
+ if (R != 0)
+ imm = ((imm << (simd_size - R)) & mask) | (imm >> R);
+ /* Replicate the value according to SIMD size. */
+ switch (simd_size)
+ {
+ case 2: imm = (imm << 2) | imm;
+ case 4: imm = (imm << 4) | imm;
+ case 8: imm = (imm << 8) | imm;
+ case 16: imm = (imm << 16) | imm;
+ case 32: imm = (imm << 32) | imm;
+ case 64: break;
+ default: assert (0); return 0;
+ }
+
+ info->imm.value = sf ? imm : imm & 0xffffffff;
+
+ return 1;
+}
+
+/* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
+ or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
+int
+aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ const aarch64_insn code, const aarch64_inst *inst)
+{
+ aarch64_insn value;
+
+ /* Rt */
+ info->reg.regno = extract_field (FLD_Rt, code, 0);
+
+ /* size */
+ value = extract_field (FLD_ldst_size, code, 0);
+ if (inst->opcode->iclass == ldstpair_indexed
+ || inst->opcode->iclass == ldstnapair_offs
+ || inst->opcode->iclass == ldstpair_off
+ || inst->opcode->iclass == loadlit)
+ {
+ enum aarch64_opnd_qualifier qualifier;
+ switch (value)
+ {
+ case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
+ case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
+ case 2: qualifier = AARCH64_OPND_QLF_S_Q; break;
+ default: return 0;
+ }
+ info->qualifier = qualifier;
+ }
+ else
+ {
+ /* opc1:size */
+ value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size);
+ if (value > 0x4)
+ return 0;
+ info->qualifier = get_sreg_qualifier_from_value (value);
+ }
+
+ return 1;
+}
+
+/* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
+int
+aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* Rn */
+ info->addr.base_regno = extract_field (FLD_Rn, code, 0);
+ return 1;
+}
+
+/* Decode the address operand for e.g.
+ STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+int
+aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code, const aarch64_inst *inst)
+{
+ aarch64_insn S, value;
+
+ /* Rn */
+ info->addr.base_regno = extract_field (FLD_Rn, code, 0);
+ /* Rm */
+ info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
+ /* option */
+ value = extract_field (FLD_option, code, 0);
+ info->shifter.kind =
+ aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
+ /* Fix-up the shifter kind; although the table-driven approach is
+ efficient, it is slightly inflexible, thus needing this fix-up. */
+ if (info->shifter.kind == AARCH64_MOD_UXTX)
+ info->shifter.kind = AARCH64_MOD_LSL;
+ /* S */
+ S = extract_field (FLD_S, code, 0);
+ if (S == 0)
+ {
+ info->shifter.amount = 0;
+ info->shifter.amount_present = 0;
+ }
+ else
+ {
+ int size;
+ /* Need information in other operand(s) to help achieve the decoding
+ from 'S' field. */
+ info->qualifier = get_expected_qualifier (inst, info->idx);
+ /* Get the size of the data element that is accessed, which may be
+ different from that of the source register size, e.g. in strb/ldrb. */
+ size = aarch64_get_qualifier_esize (info->qualifier);
+ info->shifter.amount = get_logsz (size);
+ info->shifter.amount_present = 1;
+ }
+
+ return 1;
+}
+
+/* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
+int
+aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
+ aarch64_insn code, const aarch64_inst *inst)
+{
+ aarch64_insn imm;
+ info->qualifier = get_expected_qualifier (inst, info->idx);
+
+ /* Rn */
+ info->addr.base_regno = extract_field (FLD_Rn, code, 0);
+ /* simm (imm9 or imm7) */
+ imm = extract_field (self->fields[0], code, 0);
+ info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1);
+ if (self->fields[0] == FLD_imm7)
+ /* scaled immediate in ld/st pair instructions. */
+ info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
+ /* qualifier */
+ if (inst->opcode->iclass == ldst_unscaled
+ || inst->opcode->iclass == ldstnapair_offs
+ || inst->opcode->iclass == ldstpair_off
+ || inst->opcode->iclass == ldst_unpriv)
+ info->addr.writeback = 0;
+ else
+ {
+ /* pre/post- index */
+ info->addr.writeback = 1;
+ if (extract_field (self->fields[1], code, 0) == 1)
+ info->addr.preind = 1;
+ else
+ info->addr.postind = 1;
+ }
+
+ return 1;
+}
+
+/* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
+int
+aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ int shift;
+ info->qualifier = get_expected_qualifier (inst, info->idx);
+ shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
+ /* Rn */
+ info->addr.base_regno = extract_field (self->fields[0], code, 0);
+ /* uimm12 */
+ info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift;
+ return 1;
+}
+
+/* Decode the address operand for e.g.
+ LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
+int
+aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code, const aarch64_inst *inst)
+{
+ /* The opcode dependent area stores the number of elements in
+ each structure to be loaded/stored. */
+ int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1;
+
+ /* Rn */
+ info->addr.base_regno = extract_field (FLD_Rn, code, 0);
+ /* Rm | #<amount> */
+ info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
+ if (info->addr.offset.regno == 31)
+ {
+ if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL)
+ /* Special handling of loading single structure to all lane. */
+ info->addr.offset.imm = (is_ld1r ? 1
+ : inst->operands[0].reglist.num_regs)
+ * aarch64_get_qualifier_esize (inst->operands[0].qualifier);
+ else
+ info->addr.offset.imm = inst->operands[0].reglist.num_regs
+ * aarch64_get_qualifier_esize (inst->operands[0].qualifier)
+ * aarch64_get_qualifier_nelem (inst->operands[0].qualifier);
+ }
+ else
+ info->addr.offset.is_reg = 1;
+ info->addr.writeback = 1;
+
+ return 1;
+}
+
+/* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
+int
+aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ aarch64_insn value;
+ /* cond */
+ value = extract_field (FLD_cond, code, 0);
+ info->cond = get_cond_from_value (value);
+ return 1;
+}
+
+/* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
+int
+aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* op0:op1:CRn:CRm:op2 */
+ info->sysreg = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn,
+ FLD_CRm, FLD_op2);
+ return 1;
+}
+
+/* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
+int
+aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ int i;
+ /* op1:op2 */
+ info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
+ for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
+ if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
+ return 1;
+ /* Reserved value in <pstatefield>. */
+ return 0;
+}
+
+/* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
+int
+aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ int i;
+ aarch64_insn value;
+ const aarch64_sys_ins_reg *sysins_ops;
+ /* op0:op1:CRn:CRm:op2 */
+ value = extract_fields (code, 0, 5,
+ FLD_op0, FLD_op1, FLD_CRn,
+ FLD_CRm, FLD_op2);
+
+ switch (info->type)
+ {
+ case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break;
+ case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break;
+ case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break;
+ case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break;
+ default: assert (0); return 0;
+ }
+
+ for (i = 0; sysins_ops[i].template != NULL; ++i)
+ if (sysins_ops[i].value == value)
+ {
+ info->sysins_op = sysins_ops + i;
+ DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
+ info->sysins_op->template,
+ (unsigned)info->sysins_op->value,
+ info->sysins_op->has_xt, i);
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
+
+int
+aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* CRm */
+ info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0);
+ return 1;
+}
+
+/* Decode the prefetch operation option operand for e.g.
+ PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
+
+int
+aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* prfop in Rt */
+ info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0);
+ return 1;
+}
+
+/* Decode the extended register operand for e.g.
+ STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+int
+aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ aarch64_insn value;
+
+ /* Rm */
+ info->reg.regno = extract_field (FLD_Rm, code, 0);
+ /* option */
+ value = extract_field (FLD_option, code, 0);
+ info->shifter.kind =
+ aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
+ /* imm3 */
+ info->shifter.amount = extract_field (FLD_imm3, code, 0);
+
+ /* This makes the constraint checking happy. */
+ info->shifter.operator_present = 1;
+
+ /* Assume inst->operands[0].qualifier has been resolved. */
+ assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL);
+ info->qualifier = AARCH64_OPND_QLF_W;
+ if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X
+ && (info->shifter.kind == AARCH64_MOD_UXTX
+ || info->shifter.kind == AARCH64_MOD_SXTX))
+ info->qualifier = AARCH64_OPND_QLF_X;
+
+ return 1;
+}
+
+/* Decode the shifted register operand for e.g.
+ SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
+int
+aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ aarch64_insn value;
+
+ /* Rm */
+ info->reg.regno = extract_field (FLD_Rm, code, 0);
+ /* shift */
+ value = extract_field (FLD_shift, code, 0);
+ info->shifter.kind =
+ aarch64_get_operand_modifier_from_value (value, FALSE /* extend_p */);
+ if (info->shifter.kind == AARCH64_MOD_ROR
+ && inst->opcode->iclass != log_shift)
+ /* ROR is not available for the shifted register operand in arithmetic
+ instructions. */
+ return 0;
+ /* imm6 */
+ info->shifter.amount = extract_field (FLD_imm6, code, 0);
+
+ /* This makes the constraint checking happy. */
+ info->shifter.operator_present = 1;
+
+ return 1;
+}
+\f
+/* Bitfields that are commonly used to encode certain operands' information
+ may be partially used as part of the base opcode in some instructions.
+ For example, the bit 1 of the field 'size' in
+ FCVTXN <Vb><d>, <Va><n>
+ is actually part of the base opcode, while only size<0> is available
+ for encoding the register type. Another example is the AdvSIMD
+ instruction ORR (register), in which the field 'size' is also used for
+ the base opcode, leaving only the field 'Q' available to encode the
+ vector register arrangement specifier '8B' or '16B'.
+
+ This function tries to deduce the qualifier from the value of partially
+ constrained field(s). Given the VALUE of such a field or fields, the
+ qualifiers CANDIDATES and the MASK (indicating which bits are valid for
+ operand encoding), the function returns the matching qualifier or
+ AARCH64_OPND_QLF_NIL if nothing matches.
+
+ N.B. CANDIDATES is a group of possible qualifiers that are valid for
+ one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
+ may end with AARCH64_OPND_QLF_NIL. */
+
+static enum aarch64_opnd_qualifier
+get_qualifier_from_partial_encoding (aarch64_insn value,
+ const enum aarch64_opnd_qualifier* \
+ candidates,
+ aarch64_insn mask)
+{
+ int i;
+ DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value, (int)mask);
+ for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
+ {
+ aarch64_insn standard_value;
+ if (candidates[i] == AARCH64_OPND_QLF_NIL)
+ break;
+ standard_value = aarch64_get_qualifier_standard_value (candidates[i]);
+ if ((standard_value & mask) == (value & mask))
+ return candidates[i];
+ }
+ return AARCH64_OPND_QLF_NIL;
+}
+
+/* Given a list of qualifier sequences, return all possible valid qualifiers
+ for operand IDX in QUALIFIERS.
+ Assume QUALIFIERS is an array whose length is large enough. */
+
+static void
+get_operand_possible_qualifiers (int idx,
+ const aarch64_opnd_qualifier_seq_t *list,
+ enum aarch64_opnd_qualifier *qualifiers)
+{
+ int i;
+ for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
+ if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL)
+ break;
+}
+
+/* Decode the size Q field for e.g. SHADD.
+ We tag one operand with the qualifer according to the code;
+ whether the qualifier is valid for this opcode or not, it is the
+ duty of the semantic checking. */
+
+static int
+decode_sizeq (aarch64_inst *inst)
+{
+ int idx;
+ enum aarch64_opnd_qualifier qualifier;
+ aarch64_insn code;
+ aarch64_insn value, mask;
+ enum aarch64_field_kind fld_sz;
+ enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
+
+ if (inst->opcode->iclass == asisdlse
+ || inst->opcode->iclass == asisdlsep
+ || inst->opcode->iclass == asisdlso
+ || inst->opcode->iclass == asisdlsop)
+ fld_sz = FLD_vldst_size;
+ else
+ fld_sz = FLD_size;
+
+ code = inst->value;
+ value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q);
+ /* Obtain the info that which bits of fields Q and size are actually
+ available for operand encoding. Opcodes like FMAXNM and FMLA have
+ size[1] unavailable. */
+ mask = extract_fields (~inst->opcode->mask, 0, 2, fld_sz, FLD_Q);
+
+ /* The index of the operand we are going to tag a qualifier and the qualifer
+ itself are reasoned from the value of the size and Q fields and the
+ possible valid qualifier lists. */
+ idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode);
+ DEBUG_TRACE ("key idx: %d", idx);
+
+ /* For most related instruciton, size:Q are fully available for operand
+ encoding. */
+ if (mask == 0x7)
+ {
+ inst->operands[idx].qualifier = get_vreg_qualifier_from_value (value);
+ return 1;
+ }
+
+ get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
+ candidates);
+#ifdef DEBUG_AARCH64
+ if (debug_dump)
+ {
+ int i;
+ for (i = 0; candidates[i] != AARCH64_OPND_QLF_NIL
+ && i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
+ DEBUG_TRACE ("qualifier %d: %s", i,
+ aarch64_get_qualifier_name(candidates[i]));
+ DEBUG_TRACE ("%d, %d", (int)value, (int)mask);
+ }
+#endif /* DEBUG_AARCH64 */
+
+ qualifier = get_qualifier_from_partial_encoding (value, candidates, mask);
+
+ if (qualifier == AARCH64_OPND_QLF_NIL)
+ return 0;
+
+ inst->operands[idx].qualifier = qualifier;
+ return 1;
+}
+
+/* Decode size[0]:Q, i.e. bit 22 and bit 30, for
+ e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
+
+static int
+decode_asimd_fcvt (aarch64_inst *inst)
+{
+ aarch64_field field = {0, 0};
+ aarch64_insn value;
+ enum aarch64_opnd_qualifier qualifier;
+
+ gen_sub_field (FLD_size, 0, 1, &field);
+ value = extract_field_2 (&field, inst->value, 0);
+ qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S
+ : AARCH64_OPND_QLF_V_2D;
+ switch (inst->opcode->op)
+ {
+ case OP_FCVTN:
+ case OP_FCVTN2:
+ /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
+ inst->operands[1].qualifier = qualifier;
+ break;
+ case OP_FCVTL:
+ case OP_FCVTL2:
+ /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
+ inst->operands[0].qualifier = qualifier;
+ break;
+ default:
+ assert (0);
+ return 0;
+ }
+
+ return 1;
+}
+
+/* Decode size[0], i.e. bit 22, for
+ e.g. FCVTXN <Vb><d>, <Va><n>. */
+
+static int
+decode_asisd_fcvtxn (aarch64_inst *inst)
+{
+ aarch64_field field = {0, 0};
+ gen_sub_field (FLD_size, 0, 1, &field);
+ if (!extract_field_2 (&field, inst->value, 0))
+ return 0;
+ inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S;
+ return 1;
+}
+
+/* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
+static int
+decode_fcvt (aarch64_inst *inst)
+{
+ enum aarch64_opnd_qualifier qualifier;
+ aarch64_insn value;
+ const aarch64_field field = {15, 2};
+
+ /* opc dstsize */
+ value = extract_field_2 (&field, inst->value, 0);
+ switch (value)
+ {
+ case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
+ case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
+ case 3: qualifier = AARCH64_OPND_QLF_S_H; break;
+ default: return 0;
+ }
+ inst->operands[0].qualifier = qualifier;
+
+ return 1;
+}
+
+/* Do miscellaneous decodings that are not common enough to be driven by
+ flags. */
+
+static int
+do_misc_decoding (aarch64_inst *inst)
+{
+ switch (inst->opcode->op)
+ {
+ case OP_FCVT:
+ return decode_fcvt (inst);
+ case OP_FCVTN:
+ case OP_FCVTN2:
+ case OP_FCVTL:
+ case OP_FCVTL2:
+ return decode_asimd_fcvt (inst);
+ case OP_FCVTXN_S:
+ return decode_asisd_fcvtxn (inst);
+ default:
+ return 0;
+ }
+}
+
+/* Opcodes that have fields shared by multiple operands are usually flagged
+ with flags. In this function, we detect such flags, decode the related
+ field(s) and store the information in one of the related operands. The
+ 'one' operand is not any operand but one of the operands that can
+ accommadate all the information that has been decoded. */
+
+static int
+do_special_decoding (aarch64_inst *inst)
+{
+ int idx;
+ aarch64_insn value;
+ /* Condition for truly conditional executed instructions, e.g. b.cond. */
+ if (inst->opcode->flags & F_COND)
+ {
+ value = extract_field (FLD_cond2, inst->value, 0);
+ inst->cond = get_cond_from_value (value);
+ }
+ /* 'sf' field. */
+ if (inst->opcode->flags & F_SF)
+ {
+ idx = select_operand_for_sf_field_coding (inst->opcode);
+ value = extract_field (FLD_sf, inst->value, 0);
+ inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
+ if ((inst->opcode->flags & F_N)
+ && extract_field (FLD_N, inst->value, 0) != value)
+ return 0;
+ }
+ /* size:Q fields. */
+ if (inst->opcode->flags & F_SIZEQ)
+ return decode_sizeq (inst);
+
+ if (inst->opcode->flags & F_FPTYPE)
+ {
+ idx = select_operand_for_fptype_field_coding (inst->opcode);
+ value = extract_field (FLD_type, inst->value, 0);
+ switch (value)
+ {
+ case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break;
+ case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break;
+ case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break;
+ default: return 0;
+ }
+ }
+
+ if (inst->opcode->flags & F_SSIZE)
+ {
+ /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
+ of the base opcode. */
+ aarch64_insn mask;
+ enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
+ idx = select_operand_for_scalar_size_field_coding (inst->opcode);
+ value = extract_field (FLD_size, inst->value, inst->opcode->mask);
+ mask = extract_field (FLD_size, ~inst->opcode->mask, 0);
+ /* For most related instruciton, the 'size' field is fully available for
+ operand encoding. */
+ if (mask == 0x3)
+ inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value);
+ else
+ {
+ get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
+ candidates);
+ inst->operands[idx].qualifier
+ = get_qualifier_from_partial_encoding (value, candidates, mask);
+ }
+ }
+
+ if (inst->opcode->flags & F_T)
+ {
+ /* Num of consecutive '0's on the right side of imm5<3:0>. */
+ int num = 0;
+ unsigned val, Q;
+ assert (aarch64_get_operand_class (inst->opcode->operands[0])
+ == AARCH64_OPND_CLASS_SIMD_REG);
+ /* imm5<3:0> q <t>
+ 0000 x reserved
+ xxx1 0 8b
+ xxx1 1 16b
+ xx10 0 4h
+ xx10 1 8h
+ x100 0 2s
+ x100 1 4s
+ 1000 0 reserved
+ 1000 1 2d */
+ val = extract_field (FLD_imm5, inst->value, 0);
+ while ((val & 0x1) == 0 && ++num <= 3)
+ val >>= 1;
+ if (num > 3)
+ return 0;
+ Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask);
+ inst->operands[0].qualifier =
+ get_vreg_qualifier_from_value ((num << 1) | Q);
+ }
+
+ if (inst->opcode->flags & F_GPRSIZE_IN_Q)
+ {
+ /* Use Rt to encode in the case of e.g.
+ STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
+ idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt);
+ if (idx == -1)
+ {
+ /* Otherwise use the result operand, which has to be a integer
+ register. */
+ assert (aarch64_get_operand_class (inst->opcode->operands[0])
+ == AARCH64_OPND_CLASS_INT_REG);
+ idx = 0;
+ }
+ assert (idx == 0 || idx == 1);
+ value = extract_field (FLD_Q, inst->value, 0);
+ inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
+ }
+
+ if (inst->opcode->flags & F_LDS_SIZE)
+ {
+ aarch64_field field = {0, 0};
+ assert (aarch64_get_operand_class (inst->opcode->operands[0])
+ == AARCH64_OPND_CLASS_INT_REG);
+ gen_sub_field (FLD_opc, 0, 1, &field);
+ value = extract_field_2 (&field, inst->value, 0);
+ inst->operands[0].qualifier
+ = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
+ }
+
+ /* Miscellaneous decoding; done as the last step. */
+ if (inst->opcode->flags & F_MISC)
+ return do_misc_decoding (inst);
+
+ return 1;
+}
+
+/* Converters converting a real opcode instruction to its alias form. */
+
+/* ROR <Wd>, <Ws>, #<shift>
+ is equivalent to:
+ EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
+static int
+convert_extr_to_ror (aarch64_inst *inst)
+{
+ if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
+ {
+ copy_operand_info (inst, 2, 3);
+ inst->operands[3].type = AARCH64_OPND_NIL;
+ return 1;
+ }
+ return 0;
+}
+
+/* Convert
+ UBFM <Xd>, <Xn>, #<shift>, #63.
+ to
+ LSR <Xd>, <Xn>, #<shift>. */
+static int
+convert_bfm_to_sr (aarch64_inst *inst)
+{
+ int64_t imms, val;
+
+ imms = inst->operands[3].imm.value;
+ val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
+ if (imms == val)
+ {
+ inst->operands[3].type = AARCH64_OPND_NIL;
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Convert MOV to ORR. */
+static int
+convert_orr_to_mov (aarch64_inst *inst)
+{
+ /* MOV <Vd>.<T>, <Vn>.<T>
+ is equivalent to:
+ ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
+ if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
+ {
+ inst->operands[2].type = AARCH64_OPND_NIL;
+ return 1;
+ }
+ return 0;
+}
+
+/* When <imms> >= <immr>, the instruction written:
+ SBFX <Xd>, <Xn>, #<lsb>, #<width>
+ is equivalent to:
+ SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
+
+static int
+convert_bfm_to_bfx (aarch64_inst *inst)
+{
+ int64_t immr, imms;
+
+ immr = inst->operands[2].imm.value;
+ imms = inst->operands[3].imm.value;
+ if (imms >= immr)
+ {
+ int64_t lsb = immr;
+ inst->operands[2].imm.value = lsb;
+ inst->operands[3].imm.value = imms + 1 - lsb;
+ /* The two opcodes have different qualifiers for
+ the immediate operands; reset to help the checking. */
+ reset_operand_qualifier (inst, 2);
+ reset_operand_qualifier (inst, 3);
+ return 1;
+ }
+
+ return 0;
+}
+
+/* When <imms> < <immr>, the instruction written:
+ SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
+ is equivalent to:
+ SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
+
+static int
+convert_bfm_to_bfi (aarch64_inst *inst)
+{
+ int64_t immr, imms, val;
+
+ immr = inst->operands[2].imm.value;
+ imms = inst->operands[3].imm.value;
+ val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
+ if (imms < immr)
+ {
+ inst->operands[2].imm.value = (val - immr) & (val - 1);
+ inst->operands[3].imm.value = imms + 1;
+ /* The two opcodes have different qualifiers for
+ the immediate operands; reset to help the checking. */
+ reset_operand_qualifier (inst, 2);
+ reset_operand_qualifier (inst, 3);
+ return 1;
+ }
+
+ return 0;
+}
+
+/* The instruction written:
+ LSL <Xd>, <Xn>, #<shift>
+ is equivalent to:
+ UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
+
+static int
+convert_ubfm_to_lsl (aarch64_inst *inst)
+{
+ int64_t immr = inst->operands[2].imm.value;
+ int64_t imms = inst->operands[3].imm.value;
+ int64_t val
+ = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
+
+ if ((immr == 0 && imms == val) || immr == imms + 1)
+ {
+ inst->operands[3].type = AARCH64_OPND_NIL;
+ inst->operands[2].imm.value = val - imms;
+ return 1;
+ }
+
+ return 0;
+}
+
+/* CINC <Wd>, <Wn>, <cond>
+ is equivalent to:
+ CSINC <Wd>, <Wn>, <Wn>, invert(<cond>). */
+
+static int
+convert_from_csel (aarch64_inst *inst)
+{
+ if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
+ {
+ copy_operand_info (inst, 2, 3);
+ inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
+ inst->operands[3].type = AARCH64_OPND_NIL;
+ return 1;
+ }
+ return 0;
+}
+
+/* CSET <Wd>, <cond>
+ is equivalent to:
+ CSINC <Wd>, WZR, WZR, invert(<cond>). */
+
+static int
+convert_csinc_to_cset (aarch64_inst *inst)
+{
+ if (inst->operands[1].reg.regno == 0x1f
+ && inst->operands[2].reg.regno == 0x1f)
+ {
+ copy_operand_info (inst, 1, 3);
+ inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);
+ inst->operands[3].type = AARCH64_OPND_NIL;
+ inst->operands[2].type = AARCH64_OPND_NIL;
+ return 1;
+ }
+ return 0;
+}
+
+/* MOV <Wd>, #<imm>
+ is equivalent to:
+ MOVZ <Wd>, #<imm16>, LSL #<shift>.
+
+ A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
+ ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
+ or where a MOVN has an immediate that could be encoded by MOVZ, or where
+ MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
+ machine-instruction mnemonic must be used. */
+
+static int
+convert_movewide_to_mov (aarch64_inst *inst)
+{
+ uint64_t value = inst->operands[1].imm.value;
+ /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
+ if (value == 0 && inst->operands[1].shifter.amount != 0)
+ return 0;
+ inst->operands[1].type = AARCH64_OPND_IMM_MOV;
+ inst->operands[1].shifter.kind = AARCH64_MOD_NONE;
+ value <<= inst->operands[1].shifter.amount;
+ /* As an alias convertor, it has to be clear that the INST->OPCODE
+ is the opcode of the real instruction. */
+ if (inst->opcode->op == OP_MOVN)
+ {
+ int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
+ value = ~value;
+ /* A MOVN has an immediate that could be encoded by MOVZ. */
+ if (aarch64_wide_constant_p (value, is32, NULL) == TRUE)
+ return 0;
+ }
+ inst->operands[1].imm.value = value;
+ inst->operands[1].shifter.amount = 0;
+ return 1;
+}
+
+/* MOV <Wd>, #<imm>
+ is equivalent to:
+ ORR <Wd>, WZR, #<imm>.
+
+ A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
+ ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
+ or where a MOVN has an immediate that could be encoded by MOVZ, or where
+ MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
+ machine-instruction mnemonic must be used. */
+
+static int
+convert_movebitmask_to_mov (aarch64_inst *inst)
+{
+ int is32;
+ uint64_t value;
+
+ /* Should have been assured by the base opcode value. */
+ assert (inst->operands[1].reg.regno == 0x1f);
+ copy_operand_info (inst, 1, 2);
+ is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
+ inst->operands[1].type = AARCH64_OPND_IMM_MOV;
+ value = inst->operands[1].imm.value;
+ /* ORR has an immediate that could be generated by a MOVZ or MOVN
+ instruction. */
+ if (inst->operands[0].reg.regno != 0x1f
+ && (aarch64_wide_constant_p (value, is32, NULL) == TRUE
+ || aarch64_wide_constant_p (~value, is32, NULL) == TRUE))
+ return 0;
+
+ inst->operands[2].type = AARCH64_OPND_NIL;
+ return 1;
+}
+
+/* Some alias opcodes are disassembled by being converted from their real-form.
+ N.B. INST->OPCODE is the real opcode rather than the alias. */
+
+static int
+convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
+{
+ switch (alias->op)
+ {
+ case OP_ASR_IMM:
+ case OP_LSR_IMM:
+ return convert_bfm_to_sr (inst);
+ case OP_LSL_IMM:
+ return convert_ubfm_to_lsl (inst);
+ case OP_CINC:
+ case OP_CINV:
+ case OP_CNEG:
+ return convert_from_csel (inst);
+ case OP_CSET:
+ case OP_CSETM:
+ return convert_csinc_to_cset (inst);
+ case OP_UBFX:
+ case OP_BFXIL:
+ case OP_SBFX:
+ return convert_bfm_to_bfx (inst);
+ case OP_SBFIZ:
+ case OP_BFI:
+ case OP_UBFIZ:
+ return convert_bfm_to_bfi (inst);
+ case OP_MOV_V:
+ return convert_orr_to_mov (inst);
+ case OP_MOV_IMM_WIDE:
+ case OP_MOV_IMM_WIDEN:
+ return convert_movewide_to_mov (inst);
+ case OP_MOV_IMM_LOG:
+ return convert_movebitmask_to_mov (inst);
+ case OP_ROR_IMM:
+ return convert_extr_to_ror (inst);
+ default:
+ return 0;
+ }
+}
+
+static int aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn,
+ aarch64_inst *, int);
+
+/* Given the instruction information in *INST, check if the instruction has
+ any alias form that can be used to represent *INST. If the answer is yes,
+ update *INST to be in the form of the determined alias. */
+
+/* In the opcode description table, the following flags are used in opcode
+ entries to help establish the relations between the real and alias opcodes:
+
+ F_ALIAS: opcode is an alias
+ F_HAS_ALIAS: opcode has alias(es)
+ F_P1
+ F_P2
+ F_P3: Disassembly preference priority 1-3 (the larger the
+ higher). If nothing is specified, it is the priority
+ 0 by default, i.e. the lowest priority.
+
+ Although the relation between the machine and the alias instructions are not
+ explicitly described, it can be easily determined from the base opcode
+ values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
+ description entries:
+
+ The mask of an alias opcode must be equal to or a super-set (i.e. more
+ constrained) of that of the aliased opcode; so is the base opcode value.
+
+ if (opcode_has_alias (real) && alias_opcode_p (opcode)
+ && (opcode->mask & real->mask) == real->mask
+ && (real->mask & opcode->opcode) == (real->mask & real->opcode))
+ then OPCODE is an alias of, and only of, the REAL instruction
+
+ The alias relationship is forced flat-structured to keep related algorithm
+ simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
+
+ During the disassembling, the decoding decision tree (in
+ opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
+ if the decoding of such a machine instruction succeeds (and -Mno-aliases is
+ not specified), the disassembler will check whether there is any alias
+ instruction exists for this real instruction. If there is, the disassembler
+ will try to disassemble the 32-bit binary again using the alias's rule, or
+ try to convert the IR to the form of the alias. In the case of the multiple
+ aliases, the aliases are tried one by one from the highest priority
+ (currently the flag F_P3) to the lowest priority (no priority flag), and the
+ first succeeds first adopted.
+
+ You may ask why there is a need for the conversion of IR from one form to
+ another in handling certain aliases. This is because on one hand it avoids
+ adding more operand code to handle unusual encoding/decoding; on other
+ hand, during the disassembling, the conversion is an effective approach to
+ check the condition of an alias (as an alias may be adopted only if certain
+ conditions are met).
+
+ In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
+ aarch64_opcode_table and generated aarch64_find_alias_opcode and
+ aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
+
+static void
+determine_disassembling_preference (struct aarch64_inst *inst)
+{
+ const aarch64_opcode *opcode;
+ const aarch64_opcode *alias;
+
+ opcode = inst->opcode;
+
+ /* This opcode does not have an alias, so use itself. */
+ if (opcode_has_alias (opcode) == FALSE)
+ return;
+
+ alias = aarch64_find_alias_opcode (opcode);
+ assert (alias);
+
+#ifdef DEBUG_AARCH64
+ if (debug_dump)
+ {
+ const aarch64_opcode *tmp = alias;
+ printf ("#### LIST orderd: ");
+ while (tmp)
+ {
+ printf ("%s, ", tmp->name);
+ tmp = aarch64_find_next_alias_opcode (tmp);
+ }
+ printf ("\n");
+ }
+#endif /* DEBUG_AARCH64 */
+
+ for (; alias; alias = aarch64_find_next_alias_opcode (alias))
+ {
+ DEBUG_TRACE ("try %s", alias->name);
+ assert (alias_opcode_p (alias));
+
+ /* An alias can be a pseudo opcode which will never be used in the
+ disassembly, e.g. BIC logical immediate is such a pseudo opcode
+ aliasing AND. */
+ if (pseudo_opcode_p (alias))
+ {
+ DEBUG_TRACE ("skip pseudo %s", alias->name);
+ continue;
+ }
+
+ if ((inst->value & alias->mask) != alias->opcode)
+ {
+ DEBUG_TRACE ("skip %s as base opcode not match", alias->name);
+ continue;
+ }
+ /* No need to do any complicated transformation on operands, if the alias
+ opcode does not have any operand. */
+ if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value)
+ {
+ DEBUG_TRACE ("succeed with 0-operand opcode %s", alias->name);
+ aarch64_replace_opcode (inst, alias);
+ return;
+ }
+ if (alias->flags & F_CONV)
+ {
+ aarch64_inst copy;
+ memcpy (©, inst, sizeof (aarch64_inst));
+ /* ALIAS is the preference as long as the instruction can be
+ successfully converted to the form of ALIAS. */
+ if (convert_to_alias (©, alias) == 1)
+ {
+ aarch64_replace_opcode (©, alias);
+ assert (aarch64_match_operands_constraint (©, NULL));
+ DEBUG_TRACE ("succeed with %s via conversion", alias->name);
+ memcpy (inst, ©, sizeof (aarch64_inst));
+ return;
+ }
+ }
+ else
+ {
+ /* Directly decode the alias opcode. */
+ aarch64_inst temp;
+ memset (&temp, '\0', sizeof (aarch64_inst));
+ if (aarch64_opcode_decode (alias, inst->value, &temp, 1) == 1)
+ {
+ DEBUG_TRACE ("succeed with %s via direct decoding", alias->name);
+ memcpy (inst, &temp, sizeof (aarch64_inst));
+ return;
+ }
+ }
+ }
+}
+
+/* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
+ fails, which meanes that CODE is not an instruction of OPCODE; otherwise
+ return 1.
+
+ If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
+ determined and used to disassemble CODE; this is done just before the
+ return. */
+
+static int
+aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
+ aarch64_inst *inst, int noaliases_p)
+{
+ int i;
+
+ DEBUG_TRACE ("enter with %s", opcode->name);
+
+ assert (opcode && inst);
+
+ /* Check the base opcode. */
+ if ((code & opcode->mask) != (opcode->opcode & opcode->mask))
+ {
+ DEBUG_TRACE ("base opcode match FAIL");
+ goto decode_fail;
+ }
+
+ /* Clear inst. */
+ memset (inst, '\0', sizeof (aarch64_inst));
+
+ inst->opcode = opcode;
+ inst->value = code;
+
+ /* Assign operand codes and indexes. */
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ {
+ if (opcode->operands[i] == AARCH64_OPND_NIL)
+ break;
+ inst->operands[i].type = opcode->operands[i];
+ inst->operands[i].idx = i;
+ }
+
+ /* Call the opcode decoder indicated by flags. */
+ if (opcode_has_special_coder (opcode) && do_special_decoding (inst) == 0)
+ {
+ DEBUG_TRACE ("opcode flag-based decoder FAIL");
+ goto decode_fail;
+ }
+
+ /* Call operand decoders. */
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ {
+ const aarch64_operand *opnd;
+ enum aarch64_opnd type;
+ type = opcode->operands[i];
+ if (type == AARCH64_OPND_NIL)
+ break;
+ opnd = &aarch64_operands[type];
+ if (operand_has_extractor (opnd)
+ && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst)))
+ {
+ DEBUG_TRACE ("operand decoder FAIL at operand %d", i);
+ goto decode_fail;
+ }
+ }
+
+ /* Match the qualifiers. */
+ if (aarch64_match_operands_constraint (inst, NULL) == 1)
+ {
+ /* Arriving here, the CODE has been determined as a valid instruction
+ of OPCODE and *INST has been filled with information of this OPCODE
+ instruction. Before the return, check if the instruction has any
+ alias and should be disassembled in the form of its alias instead.
+ If the answer is yes, *INST will be updated. */
+ if (!noaliases_p)
+ determine_disassembling_preference (inst);
+ DEBUG_TRACE ("SUCCESS");
+ return 1;
+ }
+ else
+ {
+ DEBUG_TRACE ("constraint matching FAIL");
+ }
+
+decode_fail:
+ return 0;
+}
+\f
+/* This does some user-friendly fix-up to *INST. It is currently focus on
+ the adjustment of qualifiers to help the printed instruction
+ recognized/understood more easily. */
+
+static void
+user_friendly_fixup (aarch64_inst *inst)
+{
+ switch (inst->opcode->iclass)
+ {
+ case testbranch:
+ /* TBNZ Xn|Wn, #uimm6, label
+ Test and Branch Not Zero: conditionally jumps to label if bit number
+ uimm6 in register Xn is not zero. The bit number implies the width of
+ the register, which may be written and should be disassembled as Wn if
+ uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
+ */
+ if (inst->operands[1].imm.value < 32)
+ inst->operands[0].qualifier = AARCH64_OPND_QLF_W;
+ break;
+ default: break;
+ }
+}
+
+/* Decode INSN and fill in *INST the instruction information. */
+
+static int
+disas_aarch64_insn (uint64_t pc ATTRIBUTE_UNUSED, uint32_t insn,
+ aarch64_inst *inst)
+{
+ const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
+
+#ifdef DEBUG_AARCH64
+ if (debug_dump)
+ {
+ const aarch64_opcode *tmp = opcode;
+ printf ("\n");
+ DEBUG_TRACE ("opcode lookup:");
+ while (tmp != NULL)
+ {
+ aarch64_verbose (" %s", tmp->name);
+ tmp = aarch64_find_next_opcode (tmp);
+ }
+ }
+#endif /* DEBUG_AARCH64 */
+
+ /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
+ distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
+ opcode field and value, apart from the difference that one of them has an
+ extra field as part of the opcode, but such a field is used for operand
+ encoding in other opcode(s) ('immh' in the case of the example). */
+ while (opcode != NULL)
+ {
+ /* But only one opcode can be decoded successfully for, as the
+ decoding routine will check the constraint carefully. */
+ if (aarch64_opcode_decode (opcode, insn, inst, no_aliases) == 1)
+ return ERR_OK;
+ opcode = aarch64_find_next_opcode (opcode);
+ }
+
+ return ERR_UND;
+}
+
+/* Print operands. */
+
+static void
+print_operands (bfd_vma pc, const aarch64_opcode *opcode,
+ const aarch64_opnd_info *opnds, struct disassemble_info *info)
+{
+ int i, pcrel_p, num_printed;
+ for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ {
+ const size_t size = 128;
+ char str[size];
+ /* We regard the opcode operand info more, however we also look into
+ the inst->operands to support the disassembling of the optional
+ operand.
+ The two operand code should be the same in all cases, apart from
+ when the operand can be optional. */
+ if (opcode->operands[i] == AARCH64_OPND_NIL
+ || opnds[i].type == AARCH64_OPND_NIL)
+ break;
+
+ /* Generate the operand string in STR. */
+ aarch64_print_operand (str, size, pc, opcode, opnds, i, &pcrel_p,
+ &info->target);
+
+ /* Print the delimiter (taking account of omitted operand(s)). */
+ if (str[0] != '\0')
+ (*info->fprintf_func) (info->stream, "%s",
+ num_printed++ == 0 ? "\t" : ", ");
+
+ /* Print the operand. */
+ if (pcrel_p)
+ (*info->print_address_func) (info->target, info);
+ else
+ (*info->fprintf_func) (info->stream, "%s", str);
+ }
+}
+
+/* Print the instruction mnemonic name. */
+
+static void
+print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info)
+{
+ if (inst->opcode->flags & F_COND)
+ {
+ /* For instructions that are truly conditionally executed, e.g. b.cond,
+ prepare the full mnemonic name with the corresponding condition
+ suffix. */
+ char name[8], *ptr;
+ size_t len;
+
+ ptr = strchr (inst->opcode->name, '.');
+ assert (ptr && inst->cond);
+ len = ptr - inst->opcode->name;
+ assert (len < 8);
+ strncpy (name, inst->opcode->name, len);
+ name [len] = '\0';
+ (*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]);
+ }
+ else
+ (*info->fprintf_func) (info->stream, "%s", inst->opcode->name);
+}
+
+/* Print the instruction according to *INST. */
+
+static void
+print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst,
+ struct disassemble_info *info)
+{
+ print_mnemonic_name (inst, info);
+ print_operands (pc, inst->opcode, inst->operands, info);
+}
+
+/* Entry-point of the instruction disassembler and printer. */
+
+static void
+print_insn_aarch64_word (bfd_vma pc,
+ uint32_t word,
+ struct disassemble_info *info)
+{
+ static const char *err_msg[6] =
+ {
+ [ERR_OK] = "_",
+ [-ERR_UND] = "undefined",
+ [-ERR_UNP] = "unpredictable",
+ [-ERR_NYI] = "NYI"
+ };
+
+ int ret;
+ aarch64_inst inst;
+
+ info->insn_info_valid = 1;
+ info->branch_delay_insns = 0;
+ info->data_size = 0;
+ info->target = 0;
+ info->target2 = 0;
+
+ if (info->flags & INSN_HAS_RELOC)
+ /* If the instruction has a reloc associated with it, then
+ the offset field in the instruction will actually be the
+ addend for the reloc. (If we are using REL type relocs).
+ In such cases, we can ignore the pc when computing
+ addresses, since the addend is not currently pc-relative. */
+ pc = 0;
+
+ ret = disas_aarch64_insn (pc, word, &inst);
+
+ if (((word >> 21) & 0x3ff) == 1)
+ {
+ /* RESERVED for ALES. */
+ assert (ret != ERR_OK);
+ ret = ERR_NYI;
+ }
+
+ switch (ret)
+ {
+ case ERR_UND:
+ case ERR_UNP:
+ case ERR_NYI:
+ /* Handle undefined instructions. */
+ info->insn_type = dis_noninsn;
+ (*info->fprintf_func) (info->stream,".inst\t0x%08x ; %s",
+ word, err_msg[-ret]);
+ break;
+ case ERR_OK:
+ user_friendly_fixup (&inst);
+ print_aarch64_insn (pc, &inst, info);
+ break;
+ default:
+ abort ();
+ }
+}
+
+/* Disallow mapping symbols ($x, $d etc) from
+ being displayed in symbol relative addresses. */
+
+bfd_boolean
+aarch64_symbol_is_valid (asymbol * sym,
+ struct disassemble_info * info ATTRIBUTE_UNUSED)
+{
+ const char * name;
+
+ if (sym == NULL)
+ return FALSE;
+
+ name = bfd_asymbol_name (sym);
+
+ return name
+ && (name[0] != '$'
+ || (name[1] != 'x' && name[1] != 'd')
+ || (name[2] != '\0' && name[2] != '.'));
+}
+
+/* Print data bytes on INFO->STREAM. */
+
+static void
+print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
+ uint32_t word,
+ struct disassemble_info *info)
+{
+ switch (info->bytes_per_chunk)
+ {
+ case 1:
+ info->fprintf_func (info->stream, ".byte\t0x%02x", word);
+ break;
+ case 2:
+ info->fprintf_func (info->stream, ".short\t0x%04x", word);
+ break;
+ case 4:
+ info->fprintf_func (info->stream, ".word\t0x%08x", word);
+ break;
+ default:
+ abort ();
+ }
+}
+
+/* Try to infer the code or data type from a symbol.
+ Returns nonzero if *MAP_TYPE was set. */
+
+static int
+get_sym_code_type (struct disassemble_info *info, int n,
+ enum map_type *map_type)
+{
+ elf_symbol_type *es;
+ unsigned int type;
+ const char *name;
+
+ es = *(elf_symbol_type **)(info->symtab + n);
+ type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
+
+ /* If the symbol has function type then use that. */
+ if (type == STT_FUNC)
+ {
+ *map_type = MAP_INSN;
+ return TRUE;
+ }
+
+ /* Check for mapping symbols. */
+ name = bfd_asymbol_name(info->symtab[n]);
+ if (name[0] == '$'
+ && (name[1] == 'x' || name[1] == 'd')
+ && (name[2] == '\0' || name[2] == '.'))
+ {
+ *map_type = (name[1] == 'x' ? MAP_INSN : MAP_DATA);
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/* Entry-point of the AArch64 disassembler. */
+
+int
+print_insn_aarch64 (bfd_vma pc,
+ struct disassemble_info *info)
+{
+ bfd_byte buffer[INSNLEN];
+ int status;
+ void (*printer) (bfd_vma, uint32_t, struct disassemble_info *);
+ bfd_boolean found = FALSE;
+ unsigned int size = 4;
+ unsigned long data;
+
+ if (info->disassembler_options)
+ {
+ set_default_aarch64_dis_options (info);
+
+ parse_aarch64_dis_options (info->disassembler_options);
+
+ /* To avoid repeated parsing of these options, we remove them here. */
+ info->disassembler_options = NULL;
+ }
+
+ /* Aarch64 instructions are always little-endian */
+ info->endian_code = BFD_ENDIAN_LITTLE;
+
+ /* First check the full symtab for a mapping symbol, even if there
+ are no usable non-mapping symbols for this address. */
+ if (info->symtab_size != 0
+ && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
+ {
+ enum map_type type = MAP_INSN;
+ int last_sym = -1;
+ bfd_vma addr;
+ int n;
+
+ if (pc <= last_mapping_addr)
+ last_mapping_sym = -1;
+
+ /* Start scanning at the start of the function, or wherever
+ we finished last time. */
+ n = info->symtab_pos + 1;
+ if (n < last_mapping_sym)
+ n = last_mapping_sym;
+
+ /* Scan up to the location being disassembled. */
+ for (; n < info->symtab_size; n++)
+ {
+ addr = bfd_asymbol_value (info->symtab[n]);
+ if (addr > pc)
+ break;
+ if ((info->section == NULL
+ || info->section == info->symtab[n]->section)
+ && get_sym_code_type (info, n, &type))
+ {
+ last_sym = n;
+ found = TRUE;
+ }
+ }
+
+ if (!found)
+ {
+ n = info->symtab_pos;
+ if (n < last_mapping_sym)
+ n = last_mapping_sym;
+
+ /* No mapping symbol found at this address. Look backwards
+ for a preceeding one. */
+ for (; n >= 0; n--)
+ {
+ if (get_sym_code_type (info, n, &type))
+ {
+ last_sym = n;
+ found = TRUE;
+ break;
+ }
+ }
+ }
+
+ last_mapping_sym = last_sym;
+ last_type = type;
+
+ /* Look a little bit ahead to see if we should print out
+ less than four bytes of data. If there's a symbol,
+ mapping or otherwise, after two bytes then don't
+ print more. */
+ if (last_type == MAP_DATA)
+ {
+ size = 4 - (pc & 3);
+ for (n = last_sym + 1; n < info->symtab_size; n++)
+ {
+ addr = bfd_asymbol_value (info->symtab[n]);
+ if (addr > pc)
+ {
+ if (addr - pc < size)
+ size = addr - pc;
+ break;
+ }
+ }
+ /* If the next symbol is after three bytes, we need to
+ print only part of the data, so that we can use either
+ .byte or .short. */
+ if (size == 3)
+ size = (pc & 1) ? 1 : 2;
+ }
+ }
+
+ if (last_type == MAP_DATA)
+ {
+ /* size was set above. */
+ info->bytes_per_chunk = size;
+ info->display_endian = info->endian;
+ printer = print_insn_data;
+ }
+ else
+ {
+ info->bytes_per_chunk = size = INSNLEN;
+ info->display_endian = info->endian_code;
+ printer = print_insn_aarch64_word;
+ }
+
+ status = (*info->read_memory_func) (pc, buffer, size, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ data = bfd_get_bits (buffer, size * 8,
+ info->display_endian == BFD_ENDIAN_BIG);
+
+ (*printer) (pc, data, info);
+
+ return size;
+}
+\f
+void
+print_aarch64_disassembler_options (FILE *stream)
+{
+ fprintf (stream, _("\n\
+The following AARCH64 specific disassembler options are supported for use\n\
+with the -M switch (multiple options should be separated by commas):\n"));
+
+ fprintf (stream, _("\n\
+ no-aliases Don't print instruction aliases.\n"));
+
+ fprintf (stream, _("\n\
+ aliases Do print instruction aliases.\n"));
+
+#ifdef DEBUG_AARCH64
+ fprintf (stream, _("\n\
+ debug_dump Temp switch for debug trace.\n"));
+#endif /* DEBUG_AARCH64 */
+
+ fprintf (stream, _("\n"));
+}
--- /dev/null
+/* aarch64-dis.h -- Header file for aarch64-dis.c and aarch64-dis-2.c.
+ Copyright 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#ifndef OPCODES_AARCH64_DIS_H
+#define OPCODES_AARCH64_DIS_H
+#include "bfd_stdint.h"
+#include "aarch64-opc.h"
+
+/* Lookup opcode WORD in the opcode table.
+
+ In the case of multiple aarch64_opcode candidates, one of them will be
+ returned; for other candidate(s), call aarch64_find_next_opcode to
+ obtain. Note that aarch64_find_next_opcode finds the next
+ aarch64_opcode candidate in a way as if all related aarch64_opcode
+ entries were in a single-link list.
+
+ N.B. all alias opcodes are ignored here. */
+
+const aarch64_opcode* aarch64_opcode_lookup (uint32_t);
+const aarch64_opcode* aarch64_find_next_opcode (const aarch64_opcode *);
+
+/* Given OPCODE, return its alias, e.g. given UBFM, return LSL.
+
+ In the case of multiple alias candidates, the one of the highest priority
+ (or one of several aliases of the same highest priority) will be
+ returned; for the other candidate(s), call aarch64_find_next_alias_opcode
+ to obtain. Note that aarch64_find_next_alias_opcode finds the next
+ alias candidate in a way as if all related aliases were in a single-link
+ list with priority from the highest to the least. */
+
+const aarch64_opcode* aarch64_find_alias_opcode (const aarch64_opcode *);
+const aarch64_opcode* aarch64_find_next_alias_opcode (const aarch64_opcode *);
+
+/* Switch-table-based high-level operand extractor. */
+
+int aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *,
+ const aarch64_insn, const aarch64_inst *);
+
+/* Operand extractors. */
+
+#define AARCH64_DECL_OPD_EXTRACTOR(x) \
+ int aarch64_##x (const aarch64_operand *, aarch64_opnd_info *, \
+ const aarch64_insn, const aarch64_inst *)
+
+AARCH64_DECL_OPD_EXTRACTOR (ext_regno);
+AARCH64_DECL_OPD_EXTRACTOR (ext_regrt_sysins);
+AARCH64_DECL_OPD_EXTRACTOR (ext_reglane);
+AARCH64_DECL_OPD_EXTRACTOR (ext_reglist);
+AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_reglist);
+AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_reglist_r);
+AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_elemlist);
+AARCH64_DECL_OPD_EXTRACTOR (ext_advsimd_imm_shift);
+AARCH64_DECL_OPD_EXTRACTOR (ext_shll_imm);
+AARCH64_DECL_OPD_EXTRACTOR (ext_imm);
+AARCH64_DECL_OPD_EXTRACTOR (ext_imm_half);
+AARCH64_DECL_OPD_EXTRACTOR (ext_advsimd_imm_modified);
+AARCH64_DECL_OPD_EXTRACTOR (ext_fbits);
+AARCH64_DECL_OPD_EXTRACTOR (ext_aimm);
+AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
+AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
+AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
+AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
+AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);
+AARCH64_DECL_OPD_EXTRACTOR (ext_addr_uimm12);
+AARCH64_DECL_OPD_EXTRACTOR (ext_simd_addr_post);
+AARCH64_DECL_OPD_EXTRACTOR (ext_cond);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sysreg);
+AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op);
+AARCH64_DECL_OPD_EXTRACTOR (ext_barrier);
+AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
+AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
+AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);
+
+#undef AARCH64_DECL_OPD_EXTRACTOR
+
+#endif /* OPCODES_AARCH64_DIS_H */
--- /dev/null
+/* aarch64-gen.c -- Generate tables and routines for opcode lookup and
+ instruction encoding and decoding.
+ Copyright 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+
+#include "libiberty.h"
+#include "getopt.h"
+#include "opcode/aarch64.h"
+
+#include "aarch64-tbl.h"
+
+static int debug = 0;
+
+/* Structure used in the decoding tree to group a list of aarch64_opcode
+ entries. */
+
+struct opcode_node
+{
+ aarch64_insn opcode;
+ aarch64_insn mask;
+ /* Index of the entry in the original table; the top 2 bits help
+ determine the table. */
+ unsigned int index;
+ struct opcode_node *next;
+};
+
+typedef struct opcode_node opcode_node;
+
+/* Head of the list of the opcode_node after read_table. */
+static opcode_node opcode_nodes_head;
+
+/* Node in the decoding tree. */
+
+struct bittree
+{
+ unsigned int bitno;
+ /* 0, 1, and X (don't care). */
+ struct bittree *bits[2];
+ /* List of opcodes; only valid for the leaf node. */
+ opcode_node *list;
+};
+
+/* Allocate and initialize an opcode_node. */
+static opcode_node*
+new_opcode_node (void)
+{
+ opcode_node* ent = malloc (sizeof (opcode_node));
+
+ if (!ent)
+ abort ();
+
+ ent->opcode = 0;
+ ent->mask = 0;
+ ent->index = -1;
+ ent->next = NULL;
+
+ return ent;
+}
+
+/* Multiple tables are supported, although currently only one table is
+ in use. N.B. there are still some functions have the table name
+ 'aarch64_opcode_table' hard-coded in, e.g. print_find_next_opcode;
+ therefore some amount of work needs to be done if the full support
+ for multiple tables needs to be enabled. */
+static const struct aarch64_opcode *aarch64_opcode_tables[] =
+{aarch64_opcode_table};
+
+/* Use top 2 bits to indiate which table. */
+static unsigned int
+initialize_index (const struct aarch64_opcode* table)
+{
+ int i;
+ const int num_of_tables = sizeof (aarch64_opcode_tables)
+ / sizeof (struct aarch64_opcode *);
+ for (i = 0; i < num_of_tables; ++i)
+ if (table == aarch64_opcode_tables [i])
+ break;
+ if (i == num_of_tables)
+ abort ();
+ return (unsigned int)i << 30;
+}
+
+static inline const struct aarch64_opcode *
+index2table (unsigned int index)
+{
+ return aarch64_opcode_tables[(index >> 30) & 0x3];
+}
+
+static inline unsigned int
+real_index (unsigned int index)
+{
+ return index & ((1 << 30) - 1);
+}
+
+/* Given OPCODE_NODE, return the corresponding aarch64_opcode*. */
+static const aarch64_opcode*
+get_aarch64_opcode (const opcode_node *opcode_node)
+{
+ if (opcode_node == NULL)
+ return NULL;
+ return &index2table (opcode_node->index)[real_index (opcode_node->index)];
+}
+
+static void
+read_table (const struct aarch64_opcode* table)
+{
+ const struct aarch64_opcode *ent = table;
+ opcode_node **new_ent;
+ unsigned int index = initialize_index (table);
+
+ if (!ent->name)
+ return;
+
+ new_ent = &opcode_nodes_head.next;
+
+ while (*new_ent)
+ new_ent = &(*new_ent)->next;
+
+ do
+ {
+ /* F_PSEUDO needs to be used together with F_ALIAS to indicate an alias
+ opcode is a programmer friendly pseudo instruction available only in
+ the assembly code (thus will not show up in the disassembly). */
+ assert (pseudo_opcode_p (ent) == FALSE || alias_opcode_p (ent) == TRUE);
+ /* Skip alias (inc. pseudo) opcode. */
+ if (alias_opcode_p (ent) == TRUE)
+ {
+ index++;
+ continue;
+ }
+ *new_ent = new_opcode_node ();
+ (*new_ent)->opcode = ent->opcode;
+ (*new_ent)->mask = ent->mask;
+ (*new_ent)->index = index++;
+ new_ent = &((*new_ent)->next);
+ } while ((++ent)->name);
+}
+
+static inline void
+print_one_opcode_node (opcode_node* ent)
+{
+ printf ("%s\t%08x\t%08x\t%d\n", get_aarch64_opcode (ent)->name,
+ get_aarch64_opcode (ent)->opcode, get_aarch64_opcode (ent)->mask,
+ (int)real_index (ent->index));
+}
+
+/* As an internal debugging utility, print out the list of nodes pointed
+ by opcode_nodes_head. */
+static void
+print_opcode_nodes (void)
+{
+ opcode_node* ent = opcode_nodes_head.next;
+ printf ("print_opcode_nodes table:\n");
+ while (ent)
+ {
+ print_one_opcode_node (ent);
+ ent = ent->next;
+ }
+}
+
+static struct bittree*
+new_bittree_node (void)
+{
+ struct bittree* node;
+ node = malloc (sizeof (struct bittree));
+ if (!node)
+ abort ();
+ node->bitno = -1;
+ node->bits[0] = NULL;
+ node->bits[1] = NULL;
+ return node;
+}
+
+/* The largest number of opcode entries that exist at a leaf node of the
+ decoding decision tree. The reason that there can be more than one
+ opcode entry is because some opcodes have shared field that is partially
+ constrained and thus cannot be fully isolated using the algorithm
+ here. */
+static int max_num_opcodes_at_leaf_node = 0;
+
+/* Given a list of opcodes headed by *OPCODE, try to establish one bit that
+ is shared by all the opcodes in the list as one of base opcode bits. If
+ such a bit is found, divide the list of the opcodes into two based on the
+ value of the bit.
+
+ Store the bit number in BITTREE->BITNO if the division succeeds. If unable
+ to determine such a bit or there is only one opcode in the list, the list
+ is decided to be undividable and OPCODE will be assigned to BITTREE->LIST.
+
+ The function recursively call itself until OPCODE is undividable.
+
+ N.B. the nature of this algrithm determines that given any value in the
+ 32-bit space, the computed decision tree will always be able to find one or
+ more opcodes entries for it, regardless whether there is a valid instruction
+ defined for this value or not. In order to detect the undefined values,
+ when the caller obtains the opcode entry/entries, it should at least compare
+ the bit-wise AND result of the value and the mask with the base opcode
+ value; if the two are different, it means that the value is undefined
+ (although the value may be still undefined when the comparison is the same,
+ in which case call aarch64_opcode_decode to carry out further checks). */
+
+static void
+divide_table_1 (struct bittree *bittree, opcode_node *opcode)
+{
+ aarch64_insn mask_and;
+ opcode_node *ent;
+ unsigned int bitno;
+ aarch64_insn bitmask;
+ opcode_node list0, list1, **ptr0, **ptr1;
+ static int depth = 0;
+
+ ++depth;
+
+ if (debug)
+ printf ("Enter into depth %d\n", depth);
+
+ assert (opcode != NULL);
+
+ /* Succeed when there is only one opcode left. */
+ if (!opcode->next)
+ {
+ if (debug)
+ {
+ printf ("opcode isolated:\n");
+ print_one_opcode_node (opcode);
+ }
+ goto divide_table_1_finish;
+ }
+
+divide_table_1_try_again:
+ mask_and = -1;
+ ent = opcode;
+ while (ent)
+ {
+ mask_and &= ent->mask;
+ ent = ent->next;
+ }
+
+ if (debug)
+ printf ("mask and result: %08x\n", (unsigned int)mask_and);
+
+ /* If no more bit to look into, we have to accept the reality then. */
+ if (!mask_and)
+ {
+ int i;
+ opcode_node *ptr;
+ if (debug)
+ {
+ ptr = opcode;
+ printf ("Isolated opcode group:\n");
+ do {
+ print_one_opcode_node (ptr);
+ ptr = ptr->next;
+ } while (ptr);
+ }
+ /* Count the number of opcodes. */
+ for (i = 0, ptr = opcode; ptr; ++i)
+ ptr = ptr->next;
+ if (i > max_num_opcodes_at_leaf_node)
+ max_num_opcodes_at_leaf_node = i;
+ goto divide_table_1_finish;
+ }
+
+ /* Pick up the right most bit that is 1. */
+ bitno = 0;
+ while (!(mask_and & (1 << bitno)))
+ ++bitno;
+ bitmask = (1 << bitno);
+
+ if (debug)
+ printf ("use bit %d\n", bitno);
+
+ /* Record in the bittree. */
+ bittree->bitno = bitno;
+
+ /* Get two new opcode lists; adjust their masks. */
+ list0.next = NULL;
+ list1.next = NULL;
+ ptr0 = &list0.next;
+ ptr1 = &list1.next;
+ ent = opcode;
+ while (ent)
+ {
+ if (ent->opcode & bitmask)
+ {
+ ent->mask &= (~bitmask);
+ *ptr1 = ent;
+ ent = ent->next;
+ (*ptr1)->next = NULL;
+ ptr1 = &(*ptr1)->next;
+ }
+ else
+ {
+ ent->mask &= (~bitmask);
+ *ptr0 = ent;
+ ent = ent->next;
+ (*ptr0)->next = NULL;
+ ptr0 = &(*ptr0)->next;
+ }
+ }
+
+ /* If BITNO can NOT divide the opcode group, try next bit. */
+ if (list0.next == NULL)
+ {
+ opcode = list1.next;
+ goto divide_table_1_try_again;
+ }
+ else if (list1.next == NULL)
+ {
+ opcode = list0.next;
+ goto divide_table_1_try_again;
+ }
+
+ /* Further divide. */
+ bittree->bits[0] = new_bittree_node ();
+ bittree->bits[1] = new_bittree_node ();
+ divide_table_1 (bittree->bits[0], list0.next);
+ divide_table_1 (bittree->bits[1], list1.next);
+
+divide_table_1_finish:
+ if (debug)
+ printf ("Leave from depth %d\n", depth);
+ --depth;
+
+ /* Record the opcode entries on this leaf node. */
+ bittree->list = opcode;
+
+ return;
+}
+
+/* Call divide_table_1 to divide the all the opcodes and thus create the
+ decoding decision tree. */
+static struct bittree *
+divide_table (void)
+{
+ struct bittree *bittree = new_bittree_node ();
+ divide_table_1 (bittree, opcode_nodes_head.next);
+ return bittree;
+}
+
+/* Read in all of the tables, create the decoding decision tree and return
+ the tree root. */
+static struct bittree *
+initialize_decoder_tree (void)
+{
+ int i;
+ const int num_of_tables = (sizeof (aarch64_opcode_tables)
+ / sizeof (struct aarch64_opcode *));
+ for (i = 0; i < num_of_tables; ++i)
+ read_table (aarch64_opcode_tables [i]);
+ if (debug)
+ print_opcode_nodes ();
+ return divide_table ();
+}
+
+static void __attribute__ ((format (printf, 2, 3)))
+indented_print (unsigned int indent, const char *format, ...)
+{
+ /* 80 number of spaces pluc a NULL terminator. */
+ static const char spaces[81] =
+ " ";
+ va_list ap;
+ va_start (ap, format);
+ assert (indent <= 80);
+ printf ("%s", &spaces[80 - indent]);
+ vprintf (format, ap);
+ va_end (ap);
+}
+
+/* N.B. read the comment above divide_table_1 for the reason why the generated
+ decision tree function never returns NULL. */
+
+static void
+print_decision_tree_1 (unsigned int indent, struct bittree* bittree)
+{
+ /* PATTERN is only used to generate comment in the code. */
+ static char pattern[33] = "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx";
+ assert (bittree != NULL);
+
+ /* Leaf node located. */
+ if (bittree->bits[0] == NULL && bittree->bits[1] == NULL)
+ {
+ assert (bittree->list != NULL);
+ indented_print (indent, "/* 33222222222211111111110000000000\n");
+ indented_print (indent, " 10987654321098765432109876543210\n");
+ indented_print (indent, " %s\n", pattern);
+ indented_print (indent, " %s. */\n",
+ get_aarch64_opcode (bittree->list)->name);
+ indented_print (indent, "return %u;\n",
+ real_index (bittree->list->index));
+ return;
+ }
+
+ /* Walk down the decoder tree. */
+ indented_print (indent, "if (((word >> %d) & 0x1) == 0)\n", bittree->bitno);
+ indented_print (indent, " {\n");
+ pattern[bittree->bitno] = '0';
+ print_decision_tree_1 (indent + 4, bittree->bits[0]);
+ indented_print (indent, " }\n");
+ indented_print (indent, "else\n");
+ indented_print (indent, " {\n");
+ pattern[bittree->bitno] = '1';
+ print_decision_tree_1 (indent + 4, bittree->bits[1]);
+ indented_print (indent, " }\n");
+ pattern[bittree->bitno] = 'x';
+}
+
+/* Generate aarch64_opcode_lookup in C code to the standard output. */
+
+static void
+print_decision_tree (struct bittree* bittree)
+{
+ if (debug)
+ printf ("Enter print_decision_tree\n");
+
+ printf ("/* Called by aarch64_opcode_lookup. */\n\n");
+
+ printf ("static int\n");
+ printf ("aarch64_opcode_lookup_1 (uint32_t word)\n");
+ printf ("{\n");
+
+ print_decision_tree_1 (2, bittree);
+
+ printf ("}\n\n");
+
+
+ printf ("/* Lookup opcode WORD in the opcode table. N.B. all alias\n");
+ printf (" opcodes are ignored here. */\n\n");
+
+ printf ("const aarch64_opcode *\n");
+ printf ("aarch64_opcode_lookup (uint32_t word)\n");
+ printf ("{\n");
+ printf (" return aarch64_opcode_table + aarch64_opcode_lookup_1 (word);\n");
+ printf ("}\n");
+}
+
+static void
+print_find_next_opcode_1 (struct bittree* bittree)
+{
+ assert (bittree != NULL);
+
+ /* Leaf node located. */
+ if (bittree->bits[0] == NULL && bittree->bits[1] == NULL)
+ {
+ assert (bittree->list != NULL);
+ /* Find multiple opcode entries in one leaf node. */
+ if (bittree->list->next != NULL)
+ {
+ opcode_node *list = bittree->list;
+ while (list != NULL)
+ {
+ const aarch64_opcode *curr = get_aarch64_opcode (list);
+ const aarch64_opcode *next = get_aarch64_opcode (list->next);
+
+ printf (" case %u: ",
+ (unsigned int)(curr - aarch64_opcode_table));
+ if (list->next != NULL)
+ {
+ printf ("value = %u; break;\t", real_index (list->next->index));
+ printf ("/* %s --> %s. */\n", curr->name, next->name);
+ }
+ else
+ {
+ printf ("return NULL;\t\t");
+ printf ("/* %s --> NULL. */\n", curr->name);
+ }
+
+ list = list->next;
+ }
+ }
+ return;
+ }
+
+ /* Walk down the decoder tree. */
+ print_find_next_opcode_1 (bittree->bits[0]);
+ print_find_next_opcode_1 (bittree->bits[1]);
+}
+
+/* Generate aarch64_find_next_opcode in C code to the standard output. */
+
+static void
+print_find_next_opcode (struct bittree* bittree)
+{
+ if (debug)
+ printf ("Enter print_find_next_opcode\n");
+
+ printf ("\n");
+ printf ("const aarch64_opcode *\n");
+ printf ("aarch64_find_next_opcode (const aarch64_opcode *opcode)\n");
+ printf ("{\n");
+ printf (" /* Use the index as the key to locate the next opcode. */\n");
+ printf (" int key = opcode - aarch64_opcode_table;\n");
+ printf (" int value;\n");
+ printf (" switch (key)\n");
+ printf (" {\n");
+
+ print_find_next_opcode_1 (bittree);
+
+ printf (" default: return NULL;\n");
+ printf (" }\n\n");
+
+ printf (" return aarch64_opcode_table + value;\n");
+ printf ("}\n");
+}
+
+/* Release the dynamic memory resource allocated for the generation of the
+ decoder tree. */
+
+static void
+release_resource_decoder_tree (struct bittree* bittree)
+{
+ assert (bittree != NULL);
+
+ /* Leaf node located. */
+ if (bittree->bits[0] == NULL && bittree->bits[1] == NULL)
+ {
+ assert (bittree->list != NULL);
+ /* Free opcode_nodes. */
+ opcode_node *list = bittree->list;
+ while (list != NULL)
+ {
+ opcode_node *next = list->next;
+ free (list);
+ list = next;
+ }
+ /* Free the tree node. */
+ free (bittree);
+ return;
+ }
+
+ /* Walk down the decoder tree. */
+ release_resource_decoder_tree (bittree->bits[0]);
+ release_resource_decoder_tree (bittree->bits[1]);
+
+ /* Free the tree node. */
+ free (bittree);
+}
+
+/* Generate aarch64_find_real_opcode in C code to the standard output.
+ TABLE points to the alias info table, while NUM indicates the number of
+ entries in the table. */
+
+static void
+print_find_real_opcode (const opcode_node *table, int num)
+{
+ int i;
+
+ if (debug)
+ printf ("Enter print_find_real_opcode\n");
+
+ printf ("\n");
+ printf ("const aarch64_opcode *\n");
+ printf ("aarch64_find_real_opcode (const aarch64_opcode *opcode)\n");
+ printf ("{\n");
+ printf (" /* Use the index as the key to locate the real opcode. */\n");
+ printf (" int key = opcode - aarch64_opcode_table;\n");
+ printf (" int value;\n");
+ printf (" switch (key)\n");
+ printf (" {\n");
+
+ for (i = 0; i < num; ++i)
+ {
+ const opcode_node *real = table + i;
+ const opcode_node *alias = real->next;
+ for (; alias; alias = alias->next)
+ printf (" case %u:\t/* %s */\n", real_index (alias->index),
+ get_aarch64_opcode (alias)->name);
+ printf (" value = %u;\t/* --> %s. */\n", real_index (real->index),
+ get_aarch64_opcode (real)->name);
+ printf (" break;\n");
+ }
+
+ printf (" default: return NULL;\n");
+ printf (" }\n\n");
+
+ printf (" return aarch64_opcode_table + value;\n");
+ printf ("}\n");
+}
+
+/* Generate aarch64_find_alias_opcode in C code to the standard output.
+ TABLE points to the alias info table, while NUM indicates the number of
+ entries in the table. */
+
+static void
+print_find_alias_opcode (const opcode_node *table, int num)
+{
+ int i;
+
+ if (debug)
+ printf ("Enter print_find_alias_opcode\n");
+
+ printf ("\n");
+ printf ("const aarch64_opcode *\n");
+ printf ("aarch64_find_alias_opcode (const aarch64_opcode *opcode)\n");
+ printf ("{\n");
+ printf (" /* Use the index as the key to locate the alias opcode. */\n");
+ printf (" int key = opcode - aarch64_opcode_table;\n");
+ printf (" int value;\n");
+ printf (" switch (key)\n");
+ printf (" {\n");
+
+ for (i = 0; i < num; ++i)
+ {
+ const opcode_node *node = table + i;
+ assert (node->next);
+ printf (" case %u: value = %u; break;", real_index (node->index),
+ real_index (node->next->index));
+ printf ("\t/* %s --> %s. */\n", get_aarch64_opcode (node)->name,
+ get_aarch64_opcode (node->next)->name);
+ }
+
+ printf (" default: return NULL;\n");
+ printf (" }\n\n");
+
+ printf (" return aarch64_opcode_table + value;\n");
+ printf ("}\n");
+}
+
+/* Generate aarch64_find_next_alias_opcode in C code to the standard output.
+ TABLE points to the alias info table, while NUM indicates the number of
+ entries in the table. */
+
+static void
+print_find_next_alias_opcode (const opcode_node *table, int num)
+{
+ int i;
+
+ if (debug)
+ printf ("Enter print_find_next_alias_opcode\n");
+
+ printf ("\n");
+ printf ("const aarch64_opcode *\n");
+ printf ("aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)\n");
+ printf ("{\n");
+ printf (" /* Use the index as the key to locate the next opcode. */\n");
+ printf (" int key = opcode - aarch64_opcode_table;\n");
+ printf (" int value;\n");
+ printf (" switch (key)\n");
+ printf (" {\n");
+
+ for (i = 0; i < num; ++i)
+ {
+ const opcode_node *node = table + i;
+ assert (node->next);
+ if (node->next->next == NULL)
+ continue;
+ while (node->next->next)
+ {
+ printf (" case %u: value = %u; break;", real_index (node->next->index),
+ real_index (node->next->next->index));
+ printf ("\t/* %s --> %s. */\n",
+ get_aarch64_opcode (node->next)->name,
+ get_aarch64_opcode (node->next->next)->name);
+ node = node->next;
+ }
+ }
+
+ printf (" default: return NULL;\n");
+ printf (" }\n\n");
+
+ printf (" return aarch64_opcode_table + value;\n");
+ printf ("}\n");
+}
+
+/* Given OPCODE, establish and return a link list of alias nodes in the
+ preferred order. */
+
+opcode_node *
+find_alias_opcode (const aarch64_opcode *opcode)
+{
+ int i;
+ /* Assume maximum of 8 disassemble preference candidates. */
+ const int max_num_aliases = 8;
+ const aarch64_opcode *ent;
+ const aarch64_opcode *preferred[max_num_aliases];
+ opcode_node head, **next;
+
+ assert (opcode_has_alias (opcode));
+
+ i = 0;
+ ent = aarch64_opcode_table;
+ while (ent->name != NULL)
+ {
+ /* The mask of an alias opcode must be equal to or a super-set (i.e.
+ more constrained) of that of the aliased opcode; so is the base
+ opcode value. */
+ if (alias_opcode_p (ent) == TRUE
+ && (ent->mask & opcode->mask) == opcode->mask
+ && (opcode->mask & ent->opcode) == (opcode->mask & opcode->opcode))
+ {
+ assert (i < max_num_aliases);
+ preferred[i++] = ent;
+ if (debug)
+ printf ("found %s for %s.", ent->name, opcode->name);
+ }
+ ++ent;
+ }
+
+ if (debug)
+ {
+ int m;
+ printf ("un-orderd list: ");
+ for (m = 0; m < i; ++m)
+ printf ("%s, ", preferred[m]->name);
+ printf ("\n");
+ }
+
+ /* There must be at least one alias. */
+ assert (i >= 1);
+
+ /* Sort preferred array according to the priority (from the lowest to the
+ highest. */
+ if (i > 1)
+ {
+ int j, k;
+ for (j = 0; j < i - 1; ++j)
+ {
+ for (k = 0; k < i - 1 - j; ++k)
+ {
+ const aarch64_opcode *t;
+ t = preferred [k+1];
+ if (opcode_priority (t) < opcode_priority (preferred [k]))
+ {
+ preferred [k+1] = preferred [k];
+ preferred [k] = t;
+ }
+ }
+ }
+ }
+
+ if (debug)
+ {
+ int m;
+ printf ("orderd list: ");
+ for (m = 0; m < i; ++m)
+ printf ("%s, ", preferred[m]->name);
+ printf ("\n");
+ }
+
+ /* Create a link-list of opcode_node with disassemble preference from
+ higher to lower. */
+ next = &head.next;
+ --i;
+ while (i >= 0)
+ {
+ const aarch64_opcode *alias = preferred [i];
+ opcode_node *node = new_opcode_node ();
+
+ if (debug)
+ printf ("add %s.\n", alias->name);
+
+ node->index = alias - aarch64_opcode_table;
+ *next = node;
+ next = &node->next;
+
+ --i;
+ }
+ *next = NULL;
+
+ return head.next;
+}
+
+/* Create and return alias information.
+ Return the address of the created alias info table; return the number
+ of table entries in *NUM_PTR. */
+
+opcode_node *
+create_alias_info (int *num_ptr)
+{
+ int i, num;
+ opcode_node *ret;
+ const aarch64_opcode *ent;
+
+ /* Calculate the total number of opcodes that have alias. */
+ num = 0;
+ ent = aarch64_opcode_table;
+ while (ent->name != NULL)
+ {
+ if (opcode_has_alias (ent))
+ {
+ /* Assert the alias relationship be flat-structured to keep
+ algorithms simple; not allow F_ALIAS and F_HAS_ALIAS both
+ specified. */
+ assert (!alias_opcode_p (ent));
+ ++num;
+ }
+ ++ent;
+ }
+ assert (num_ptr);
+ *num_ptr = num;
+
+ /* The array of real opcodes that have alias(es). */
+ ret = malloc (sizeof (opcode_node) * num);
+
+ /* For each opcode, establish a list of alias nodes in a preferred
+ order. */
+ for (i = 0, ent = aarch64_opcode_table; i < num; ++i, ++ent)
+ {
+ opcode_node *node = ret + i;
+ while (ent->name != NULL && !opcode_has_alias (ent))
+ ++ent;
+ assert (ent->name != NULL);
+ node->index = ent - aarch64_opcode_table;
+ node->next = find_alias_opcode (ent);
+ assert (node->next);
+ }
+ assert (i == num);
+
+ return ret;
+}
+
+/* Release the dynamic memory resource allocated for the generation of the
+ alias information. */
+
+void
+release_resource_alias_info (opcode_node *alias_info, int num)
+{
+ int i = 0;
+ opcode_node *node = alias_info;
+
+ /* Free opcode_node list. */
+ for (; i < num; ++i, ++node)
+ {
+ opcode_node *list = node->next;
+ do
+ {
+ opcode_node *next = list->next;
+ free (list);
+ list = next;
+ } while (list != NULL);
+ }
+
+ /* Free opcode_node array. */
+ free (alias_info);
+}
+
+/* As a debugging utility, print out the result of the table division, although
+ it is not doing much this moment. */
+static void
+print_divide_result (const struct bittree *bittree ATTRIBUTE_UNUSED)
+{
+ printf ("max_num_opcodes_at_leaf_node: %d\n", max_num_opcodes_at_leaf_node);
+ return;
+}
+\f
+/* Structure to help generate the operand table. */
+struct operand
+{
+ const char *class;
+ const char *inserter;
+ const char *extractor;
+ const char *str;
+ const char *flags;
+ const char *fields;
+ const char *desc;
+ unsigned processed : 1;
+ unsigned has_inserter : 1;
+ unsigned has_extractor : 1;
+};
+
+typedef struct operand operand;
+
+#ifdef X
+#undef X
+#endif
+
+#ifdef Y
+#undef Y
+#endif
+
+#ifdef F
+#undef F
+#endif
+
+/* Get the operand information in strings. */
+
+static operand operands[] =
+{
+ {"NIL", "0", "0", "", "0", "{0}", "<none>", 0, 0, 0},
+#define F(...) #__VA_ARGS__
+#define X(a,b,c,d,e,f,g) \
+ {#a, #b, #c, d, #e, "{"f"}", g, 0, 0, 0},
+#define Y(a,b,d,e,f,g) \
+ {#a, "ins_"#b, "ext_"#b, d, #e, "{"f"}", g, 0, 0, 0},
+ AARCH64_OPERANDS
+ {"NIL", "0", "0", "", "0", "{0}", "DUMMY", 0, 0, 0},
+};
+
+#undef F
+#undef X
+
+static void
+process_operand_table (void)
+{
+ int i;
+ operand *opnd;
+ const int num = sizeof (operands) / sizeof (operand);
+
+ for (i = 0, opnd = operands; i < num; ++i, ++opnd)
+ {
+ opnd->has_inserter = opnd->inserter[0] != '0';
+ opnd->has_extractor = opnd->extractor[0] != '0';
+ }
+}
+
+/* Generate aarch64_operands in C to the standard output. */
+
+static void
+print_operand_table (void)
+{
+ int i;
+ operand *opnd;
+ const int num = sizeof (operands) / sizeof (operand);
+
+ if (debug)
+ printf ("Enter print_operand_table\n");
+
+ printf ("\n");
+ printf ("const struct aarch64_operand aarch64_operands[] =\n");
+ printf ("{\n");
+
+ for (i = 0, opnd = operands; i < num; ++i, ++opnd)
+ {
+ char flags[256];
+ flags[0] = '\0';
+ if (opnd->flags[0] != '0')
+ sprintf (flags, "%s", opnd->flags);
+ if (opnd->has_inserter)
+ {
+ if (flags[0] != '\0')
+ strcat (flags, " | ");
+ strcat (flags, "OPD_F_HAS_INSERTER");
+ }
+ if (opnd->has_extractor)
+ {
+ if (flags[0] != '\0')
+ strcat (flags, " | ");
+ strcat (flags, "OPD_F_HAS_EXTRACTOR");
+ }
+ if (flags[0] == '\0')
+ {
+ flags[0] = '0';
+ flags[1] = '\0';
+ }
+ printf (" {AARCH64_OPND_CLASS_%s, \"%s\", %s, %s, \"%s\"},\n",
+ opnd->class, opnd->str, flags, opnd->fields, opnd->desc);
+ }
+ printf ("};\n");
+}
+
+/* Generate aarch64_insert_operand in C to the standard output. */
+
+static void
+print_operand_inserter (void)
+{
+ int i;
+ operand *opnd;
+ const int num = sizeof (operands) / sizeof (operand);
+
+ if (debug)
+ printf ("Enter print_operand_inserter\n");
+
+ printf ("\n");
+ printf ("const char*\n");
+ printf ("aarch64_insert_operand (const aarch64_operand *self,\n\
+ const aarch64_opnd_info *info,\n\
+ aarch64_insn *code, const aarch64_inst *inst)\n");
+ printf ("{\n");
+ printf (" /* Use the index as the key. */\n");
+ printf (" int key = self - aarch64_operands;\n");
+ printf (" switch (key)\n");
+ printf (" {\n");
+
+ for (i = 0, opnd = operands; i < num; ++i, ++opnd)
+ opnd->processed = 0;
+
+ for (i = 0, opnd = operands; i < num; ++i, ++opnd)
+ {
+ if (!opnd->processed && opnd->has_inserter)
+ {
+ int j = i + 1;
+ const int len = strlen (opnd->inserter);
+ operand *opnd2 = opnd + 1;
+ printf (" case %u:\n", (unsigned int)(opnd - operands));
+ opnd->processed = 1;
+ for (; j < num; ++j, ++opnd2)
+ {
+ if (!opnd2->processed
+ && opnd2->has_inserter
+ && len == strlen (opnd2->inserter)
+ && strncmp (opnd->inserter, opnd2->inserter, len) == 0)
+ {
+ printf (" case %u:\n", (unsigned int)(opnd2 - operands));
+ opnd2->processed = 1;
+ }
+ }
+ printf (" return aarch64_%s (self, info, code, inst);\n",
+ opnd->inserter);
+ }
+ }
+
+ printf (" default: assert (0); abort ();\n");
+ printf (" }\n");
+ printf ("}\n");
+}
+
+/* Generate aarch64_extract_operand in C to the standard output. */
+
+static void
+print_operand_extractor (void)
+{
+ int i;
+ operand *opnd;
+ const int num = sizeof (operands) / sizeof (operand);
+
+ if (debug)
+ printf ("Enter print_operand_extractor\n");
+
+ printf ("\n");
+ printf ("int\n");
+ printf ("aarch64_extract_operand (const aarch64_operand *self,\n\
+ aarch64_opnd_info *info,\n\
+ aarch64_insn code, const aarch64_inst *inst)\n");
+ printf ("{\n");
+ printf (" /* Use the index as the key. */\n");
+ printf (" int key = self - aarch64_operands;\n");
+ printf (" switch (key)\n");
+ printf (" {\n");
+
+ for (i = 0, opnd = operands; i < num; ++i, ++opnd)
+ opnd->processed = 0;
+
+ for (i = 0, opnd = operands; i < num; ++i, ++opnd)
+ {
+ if (!opnd->processed && opnd->has_extractor)
+ {
+ int j = i + 1;
+ const int len = strlen (opnd->extractor);
+ operand *opnd2 = opnd + 1;
+ printf (" case %u:\n", (unsigned int)(opnd - operands));
+ opnd->processed = 1;
+ for (; j < num; ++j, ++opnd2)
+ {
+ if (!opnd2->processed
+ && opnd2->has_extractor
+ && len == strlen (opnd2->extractor)
+ && strncmp (opnd->extractor, opnd2->extractor, len) == 0)
+ {
+ printf (" case %u:\n", (unsigned int)(opnd2 - operands));
+ opnd2->processed = 1;
+ }
+ }
+ printf (" return aarch64_%s (self, info, code, inst);\n",
+ opnd->extractor);
+ }
+ }
+
+ printf (" default: assert (0); abort ();\n");
+ printf (" }\n");
+ printf ("}\n");
+}
+\f
+/* Table indexed by opcode enumerator stores the index of the corresponding
+ opcode entry in aarch64_opcode_table. */
+static unsigned op_enum_table [OP_TOTAL_NUM];
+
+/* Print out the routine which, given the opcode enumerator, returns the
+ corresponding opcode entry pointer. */
+
+static void
+print_get_opcode (void)
+{
+ int i;
+ const int num = OP_TOTAL_NUM;
+ const aarch64_opcode *opcode;
+
+ if (debug)
+ printf ("Enter print_get_opcode\n");
+
+ /* Fill in the internal table. */
+ opcode = aarch64_opcode_table;
+ while (opcode->name != NULL)
+ {
+ if (opcode->op != OP_NIL)
+ {
+ /* Assert opcode enumerator be unique, in other words, no shared by
+ different opcodes. */
+ if (op_enum_table[opcode->op] != 0)
+ {
+ fprintf (stderr, "Opcode %u is shared by different %s and %s.\n",
+ opcode->op,
+ aarch64_opcode_table[op_enum_table[opcode->op]].name,
+ opcode->name);
+ assert (0);
+ abort ();
+ }
+ assert (opcode->op < OP_TOTAL_NUM);
+ op_enum_table[opcode->op] = opcode - aarch64_opcode_table;
+ }
+ ++opcode;
+ }
+
+ /* Print the table. */
+ printf ("\n");
+ printf ("/* Indexed by an enum aarch64_op enumerator, the value is the offset of\n\
+ the corresponding aarch64_opcode entry in the aarch64_opcode_table. */\n\n");
+ printf ("static const unsigned op_enum_table [] =\n");
+ printf ("{\n");
+ for (i = 0; i < num; ++i)
+ printf (" %u,\n", op_enum_table[i]);
+ printf ("};\n");
+
+ /* Print the function. */
+ printf ("\n");
+ printf ("/* Given the opcode enumerator OP, return the pointer to the corresponding\n");
+ printf (" opcode entry. */\n");
+ printf ("\n");
+ printf ("const aarch64_opcode *\n");
+ printf ("aarch64_get_opcode (enum aarch64_op op)\n");
+ printf ("{\n");
+ printf (" return aarch64_opcode_table + op_enum_table[op];\n");
+ printf ("}\n");
+}
+
+/* Print out the content of an opcode table (not in use). */
+static void ATTRIBUTE_UNUSED
+print_table (struct aarch64_opcode* table)
+{
+ struct aarch64_opcode *ent = table;
+ do
+ {
+ printf ("%s\t%08x\t%08x\n", ent->name, (unsigned int)ent->opcode,
+ (unsigned int)ent->mask);
+ } while ((++ent)->name);
+}
+\f
+static const char * program_name = NULL;
+
+/* Program options. */
+struct option long_options[] =
+{
+ {"debug", no_argument, NULL, 'd'},
+ {"version", no_argument, NULL, 'V'},
+ {"help", no_argument, NULL, 'h'},
+ {"gen-opc", no_argument, NULL, 'c'},
+ {"gen-asm", no_argument, NULL, 'a'},
+ {"gen-dis", no_argument, NULL, 's'},
+ {0, no_argument, NULL, 0}
+};
+
+static void
+print_version (void)
+{
+ printf ("%s: version 1.0\n", program_name);
+ xexit (0);
+}
+
+static void
+usage (FILE * stream, int status)
+{
+ fprintf (stream, "Usage: %s [-V | --version] [-d | --debug] [--help]\n",
+ program_name);
+ fprintf (stream, "\t[ [-c | --gen-opc] | [-a | --gen-asm] | [-s | --gen-dis] ]\n");
+ xexit (status);
+}
+
+int
+main (int argc, char **argv)
+{
+ extern int chdir (char *);
+ int c;
+ int gen_opcode_p = 0;
+ int gen_assembler_p = 0;
+ int gen_disassembler_p = 0;
+
+ program_name = *argv;
+ xmalloc_set_program_name (program_name);
+
+ while ((c = getopt_long (argc, argv, "vVdhacs", long_options, 0)) != EOF)
+ switch (c)
+ {
+ case 'V':
+ case 'v':
+ print_version ();
+ break;
+ case 'd':
+ debug = 1;
+ break;
+ case 'h':
+ case '?':
+ usage (stderr, 0);
+ break;
+ case 'c':
+ gen_opcode_p = 1;
+ break;
+ case 'a':
+ gen_assembler_p = 1;
+ break;
+ case 's':
+ gen_disassembler_p = 1;
+ break;
+ default:
+ case 0:
+ break;
+ }
+
+ if (argc == 1 || optind != argc)
+ usage (stdout, 1);
+
+ if (gen_opcode_p + gen_assembler_p + gen_disassembler_p > 1)
+ {
+ printf ("Please specify only one of the following options\n\
+ [-c | --gen-opc] [-a | --gen-asm] [-s | --gen-dis]\n");
+ xexit (2);
+ }
+
+ struct bittree *decoder_tree;
+
+ decoder_tree = initialize_decoder_tree ();
+ if (debug)
+ print_divide_result (decoder_tree);
+
+ printf ("/* This file is automatically generated by aarch64-gen. Do not edit! */\n");
+ printf ("/* Copyright 2012 Free Software Foundation, Inc.\n\
+ Contributed by ARM Ltd.\n\
+\n\
+ This file is part of the GNU opcodes library.\n\
+\n\
+ This library is free software; you can redistribute it and/or modify\n\
+ it under the terms of the GNU General Public License as published by\n\
+ the Free Software Foundation; either version 3, or (at your option)\n\
+ any later version.\n\
+\n\
+ It is distributed in the hope that it will be useful, but WITHOUT\n\
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n\
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n\
+ License for more details.\n\
+\n\
+ You should have received a copy of the GNU General Public License\n\
+ along with this program; see the file COPYING3. If not,\n\
+ see <http://www.gnu.org/licenses/>. */\n");
+
+ printf ("\n");
+ printf ("#include \"sysdep.h\"\n");
+ if (gen_opcode_p)
+ printf ("#include \"aarch64-opc.h\"\n");
+ if (gen_assembler_p)
+ printf ("#include \"aarch64-asm.h\"\n");
+ if (gen_disassembler_p)
+ printf ("#include \"aarch64-dis.h\"\n");
+ printf ("\n");
+
+ /* Generate opcode entry lookup for the disassembler. */
+ if (gen_disassembler_p)
+ {
+ print_decision_tree (decoder_tree);
+ print_find_next_opcode (decoder_tree);
+ release_resource_decoder_tree (decoder_tree);
+ }
+
+ /* Generate alias opcode handling for the assembler or the disassembler. */
+ if (gen_assembler_p || gen_disassembler_p)
+ {
+ int num;
+ opcode_node *alias_info = create_alias_info (&num);
+
+ if (gen_assembler_p)
+ print_find_real_opcode (alias_info, num);
+
+ if (gen_disassembler_p)
+ {
+ print_find_alias_opcode (alias_info, num);
+ print_find_next_alias_opcode (alias_info, num);
+ }
+
+ release_resource_alias_info (alias_info, num);
+ }
+
+ /* Generate operand table. */
+ process_operand_table ();
+
+ if (gen_assembler_p)
+ print_operand_inserter ();
+
+ if (gen_disassembler_p)
+ print_operand_extractor ();
+
+ if (gen_opcode_p)
+ print_operand_table ();
+
+ /* Generate utility to return aarch64_opcode entry given an enumerator. */
+ if (gen_opcode_p)
+ print_get_opcode ();
+
+ exit (0);
+}
--- /dev/null
+/* This file is automatically generated by aarch64-gen. Do not edit! */
+/* Copyright 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include "aarch64-opc.h"
+
+
+const struct aarch64_operand aarch64_operands[] =
+{
+ {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "<none>"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
+ {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"},
+ {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"},
+ {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register"},
+ {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register"},
+ {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register"},
+ {AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "the top half of a 128-bit FP/SIMD register"},
+ {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "the top half of a 128-bit FP/SIMD register"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"},
+ {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"},
+ {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
+ {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
+ {AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"},
+ {AARCH64_OPND_CLASS_CP_REG, "Cn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
+ {AARCH64_OPND_CLASS_CP_REG, "Cm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an 8-bit unsigned immediate with optional shift"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an 8-bit floating-point constant"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {}, "an immediate shift amount of 8, 16 or 32"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {}, "0"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {}, "0.0"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"},
+ {AARCH64_OPND_CLASS_NIL, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"},
+ {AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a system register"},
+ {AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a PSTATE field name"},
+ {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address translation operation specifier"},
+ {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a data cache maintenance operation specifier"},
+ {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instructin cache maintenance operation specifier"},
+ {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
+ {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
+ {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an prefetch operation specifier"},
+ {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
+};
+
+/* Indexed by an enum aarch64_op enumerator, the value is the offset of
+ the corresponding aarch64_opcode entry in the aarch64_opcode_table. */
+
+static const unsigned op_enum_table [] =
+{
+ 0,
+ 648,
+ 649,
+ 650,
+ 653,
+ 654,
+ 655,
+ 656,
+ 657,
+ 651,
+ 652,
+ 658,
+ 659,
+ 681,
+ 682,
+ 685,
+ 691,
+ 692,
+ 695,
+ 697,
+ 698,
+ 687,
+ 688,
+ 701,
+ 703,
+ 741,
+ 742,
+ 743,
+ 744,
+ 12,
+ 506,
+ 507,
+ 764,
+ 766,
+ 768,
+ 748,
+ 767,
+ 765,
+ 259,
+ 495,
+ 505,
+ 504,
+ 746,
+ 501,
+ 498,
+ 491,
+ 490,
+ 497,
+ 500,
+ 502,
+ 503,
+ 756,
+ 125,
+ 522,
+ 525,
+ 528,
+ 523,
+ 526,
+ 614,
+ 160,
+ 161,
+ 162,
+ 163,
+ 416,
+ 583,
+};
+
+/* Given the opcode enumerator OP, return the pointer to the corresponding
+ opcode entry. */
+
+const aarch64_opcode *
+aarch64_get_opcode (enum aarch64_op op)
+{
+ return aarch64_opcode_table + op_enum_table[op];
+}
--- /dev/null
+/* aarch64-opc.c -- AArch64 opcode support.
+ Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include <assert.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <stdarg.h>
+#include <inttypes.h>
+
+#include "opintl.h"
+
+#include "aarch64-opc.h"
+
+#ifdef DEBUG_AARCH64
+int debug_dump = FALSE;
+#endif /* DEBUG_AARCH64 */
+
+/* Helper functions to determine which operand to be used to encode/decode
+ the size:Q fields for AdvSIMD instructions. */
+
+static inline bfd_boolean
+vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
+{
+ return ((qualifier >= AARCH64_OPND_QLF_V_8B
+ && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
+ : FALSE);
+}
+
+static inline bfd_boolean
+fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
+{
+ return ((qualifier >= AARCH64_OPND_QLF_S_B
+ && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
+ : FALSE);
+}
+
+enum data_pattern
+{
+ DP_UNKNOWN,
+ DP_VECTOR_3SAME,
+ DP_VECTOR_LONG,
+ DP_VECTOR_WIDE,
+ DP_VECTOR_ACROSS_LANES,
+};
+
+static const char significant_operand_index [] =
+{
+ 0, /* DP_UNKNOWN, by default using operand 0. */
+ 0, /* DP_VECTOR_3SAME */
+ 1, /* DP_VECTOR_LONG */
+ 2, /* DP_VECTOR_WIDE */
+ 1, /* DP_VECTOR_ACROSS_LANES */
+};
+
+/* Given a sequence of qualifiers in QUALIFIERS, determine and return
+ the data pattern.
+ N.B. QUALIFIERS is a possible sequence of qualifiers each of which
+ corresponds to one of a sequence of operands. */
+
+static enum data_pattern
+get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
+{
+ if (vector_qualifier_p (qualifiers[0]) == TRUE)
+ {
+ /* e.g. v.4s, v.4s, v.4s
+ or v.4h, v.4h, v.h[3]. */
+ if (qualifiers[0] == qualifiers[1]
+ && vector_qualifier_p (qualifiers[2]) == TRUE
+ && (aarch64_get_qualifier_esize (qualifiers[0])
+ == aarch64_get_qualifier_esize (qualifiers[1]))
+ && (aarch64_get_qualifier_esize (qualifiers[0])
+ == aarch64_get_qualifier_esize (qualifiers[2])))
+ return DP_VECTOR_3SAME;
+ /* e.g. v.8h, v.8b, v.8b.
+ or v.4s, v.4h, v.h[2].
+ or v.8h, v.16b. */
+ if (vector_qualifier_p (qualifiers[1]) == TRUE
+ && aarch64_get_qualifier_esize (qualifiers[0]) != 0
+ && (aarch64_get_qualifier_esize (qualifiers[0])
+ == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
+ return DP_VECTOR_LONG;
+ /* e.g. v.8h, v.8h, v.8b. */
+ if (qualifiers[0] == qualifiers[1]
+ && vector_qualifier_p (qualifiers[2]) == TRUE
+ && aarch64_get_qualifier_esize (qualifiers[0]) != 0
+ && (aarch64_get_qualifier_esize (qualifiers[0])
+ == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
+ && (aarch64_get_qualifier_esize (qualifiers[0])
+ == aarch64_get_qualifier_esize (qualifiers[1])))
+ return DP_VECTOR_WIDE;
+ }
+ else if (fp_qualifier_p (qualifiers[0]) == TRUE)
+ {
+ /* e.g. SADDLV <V><d>, <Vn>.<T>. */
+ if (vector_qualifier_p (qualifiers[1]) == TRUE
+ && qualifiers[2] == AARCH64_OPND_QLF_NIL)
+ return DP_VECTOR_ACROSS_LANES;
+ }
+
+ return DP_UNKNOWN;
+}
+
+/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
+ the AdvSIMD instructions. */
+/* N.B. it is possible to do some optimization that doesn't call
+ get_data_pattern each time when we need to select an operand. We can
+ either buffer the caculated the result or statically generate the data,
+ however, it is not obvious that the optimization will bring significant
+ benefit. */
+
+int
+aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
+{
+ return
+ significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
+}
+\f
+const aarch64_field fields[] =
+{
+ { 0, 0 }, /* NIL. */
+ { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
+ { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
+ { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
+ { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
+ { 5, 19 }, /* imm19: e.g. in CBZ. */
+ { 5, 19 }, /* immhi: e.g. in ADRP. */
+ { 29, 2 }, /* immlo: e.g. in ADRP. */
+ { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
+ { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
+ { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
+ { 30, 1 }, /* Q: in most AdvSIMD instructions. */
+ { 0, 5 }, /* Rt: in load/store instructions. */
+ { 0, 5 }, /* Rd: in many integer instructions. */
+ { 5, 5 }, /* Rn: in many integer instructions. */
+ { 10, 5 }, /* Rt2: in load/store pair instructions. */
+ { 10, 5 }, /* Ra: in fp instructions. */
+ { 5, 3 }, /* op2: in the system instructions. */
+ { 8, 4 }, /* CRm: in the system instructions. */
+ { 12, 4 }, /* CRn: in the system instructions. */
+ { 16, 3 }, /* op1: in the system instructions. */
+ { 19, 2 }, /* op0: in the system instructions. */
+ { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
+ { 12, 4 }, /* cond: condition flags as a source operand. */
+ { 12, 4 }, /* opcode: in advsimd load/store instructions. */
+ { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
+ { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
+ { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
+ { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
+ { 16, 5 }, /* Rs: in load/store exclusive instructions. */
+ { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
+ { 12, 1 }, /* S: in load/store reg offset instructions. */
+ { 21, 2 }, /* hw: in move wide constant instructions. */
+ { 22, 2 }, /* opc: in load/store reg offset instructions. */
+ { 23, 1 }, /* opc1: in load/store reg offset instructions. */
+ { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
+ { 22, 2 }, /* type: floating point type field in fp data inst. */
+ { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
+ { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
+ { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
+ { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
+ { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
+ { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
+ { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
+ { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
+ { 5, 14 }, /* imm14: in test bit and branch instructions. */
+ { 5, 16 }, /* imm16: in exception instructions. */
+ { 0, 26 }, /* imm26: in unconditional branch instructions. */
+ { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
+ { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
+ { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
+ { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
+ { 22, 1 }, /* N: in logical (immediate) instructions. */
+ { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
+ { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
+ { 31, 1 }, /* sf: in integer data processing instructions. */
+ { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
+ { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
+ { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
+ { 31, 1 }, /* b5: in the test bit and branch instructions. */
+ { 19, 5 }, /* b40: in the test bit and branch instructions. */
+ { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
+};
+
+enum aarch64_operand_class
+aarch64_get_operand_class (enum aarch64_opnd type)
+{
+ return aarch64_operands[type].op_class;
+}
+
+const char *
+aarch64_get_operand_name (enum aarch64_opnd type)
+{
+ return aarch64_operands[type].name;
+}
+
+/* Get operand description string.
+ This is usually for the diagnosis purpose. */
+const char *
+aarch64_get_operand_desc (enum aarch64_opnd type)
+{
+ return aarch64_operands[type].desc;
+}
+
+/* Table of all conditional affixes. */
+const aarch64_cond aarch64_conds[16] =
+{
+ {{"eq"}, 0x0},
+ {{"ne"}, 0x1},
+ {{"cs", "hs"}, 0x2},
+ {{"cc", "lo", "ul"}, 0x3},
+ {{"mi"}, 0x4},
+ {{"pl"}, 0x5},
+ {{"vs"}, 0x6},
+ {{"vc"}, 0x7},
+ {{"hi"}, 0x8},
+ {{"ls"}, 0x9},
+ {{"ge"}, 0xa},
+ {{"lt"}, 0xb},
+ {{"gt"}, 0xc},
+ {{"le"}, 0xd},
+ {{"al"}, 0xe},
+ {{"nv"}, 0xf},
+};
+
+const aarch64_cond *
+get_cond_from_value (aarch64_insn value)
+{
+ assert (value < 16);
+ return &aarch64_conds[(unsigned int) value];
+}
+
+const aarch64_cond *
+get_inverted_cond (const aarch64_cond *cond)
+{
+ return &aarch64_conds[cond->value ^ 0x1];
+}
+
+/* Table describing the operand extension/shifting operators; indexed by
+ enum aarch64_modifier_kind.
+
+ The value column provides the most common values for encoding modifiers,
+ which enables table-driven encoding/decoding for the modifiers. */
+const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
+{
+ {"none", 0x0},
+ {"msl", 0x0},
+ {"ror", 0x3},
+ {"asr", 0x2},
+ {"lsr", 0x1},
+ {"lsl", 0x0},
+ {"uxtb", 0x0},
+ {"uxth", 0x1},
+ {"uxtw", 0x2},
+ {"uxtx", 0x3},
+ {"sxtb", 0x4},
+ {"sxth", 0x5},
+ {"sxtw", 0x6},
+ {"sxtx", 0x7},
+ {NULL, 0},
+};
+
+enum aarch64_modifier_kind
+aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
+{
+ return desc - aarch64_operand_modifiers;
+}
+
+aarch64_insn
+aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
+{
+ return aarch64_operand_modifiers[kind].value;
+}
+
+enum aarch64_modifier_kind
+aarch64_get_operand_modifier_from_value (aarch64_insn value,
+ bfd_boolean extend_p)
+{
+ if (extend_p == TRUE)
+ return AARCH64_MOD_UXTB + value;
+ else
+ return AARCH64_MOD_LSL - value;
+}
+
+bfd_boolean
+aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
+{
+ return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
+ ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
+aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
+{
+ return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
+ ? TRUE : FALSE;
+}
+
+const struct aarch64_name_value_pair aarch64_barrier_options[16] =
+{
+ { "#0x00", 0x0 },
+ { "oshld", 0x1 },
+ { "oshst", 0x2 },
+ { "osh", 0x3 },
+ { "#0x04", 0x4 },
+ { "nshld", 0x5 },
+ { "nshst", 0x6 },
+ { "nsh", 0x7 },
+ { "#0x08", 0x8 },
+ { "ishld", 0x9 },
+ { "ishst", 0xa },
+ { "ish", 0xb },
+ { "#0x0c", 0xc },
+ { "ld", 0xd },
+ { "st", 0xe },
+ { "sy", 0xf },
+};
+
+/* op -> op: load = 0 store = 1
+ l -> level: 1-3
+ t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
+#define B(op,l,t) ((((op) * 2) << 3) | (((l) - 1) << 1) | (t))
+const struct aarch64_name_value_pair aarch64_prfops[32] =
+{
+ { "pldl1keep", B(0, 1, 0) },
+ { "pldl1strm", B(0, 1, 1) },
+ { "pldl2keep", B(0, 2, 0) },
+ { "pldl2strm", B(0, 2, 1) },
+ { "pldl3keep", B(0, 3, 0) },
+ { "pldl3strm", B(0, 3, 1) },
+ { "#0x06", 0x06 },
+ { "#0x07", 0x07 },
+ { "#0x08", 0x08 },
+ { "#0x09", 0x09 },
+ { "#0x0a", 0x0a },
+ { "#0x0b", 0x0b },
+ { "#0x0c", 0x0c },
+ { "#0x0d", 0x0d },
+ { "#0x0e", 0x0e },
+ { "#0x0f", 0x0f },
+ { "pstl1keep", B(1, 1, 0) },
+ { "pstl1strm", B(1, 1, 1) },
+ { "pstl2keep", B(1, 2, 0) },
+ { "pstl2strm", B(1, 2, 1) },
+ { "pstl3keep", B(1, 3, 0) },
+ { "pstl3strm", B(1, 3, 1) },
+ { "#0x16", 0x16 },
+ { "#0x17", 0x17 },
+ { "#0x18", 0x18 },
+ { "#0x19", 0x19 },
+ { "#0x1a", 0x1a },
+ { "#0x1b", 0x1b },
+ { "#0x1c", 0x1c },
+ { "#0x1d", 0x1d },
+ { "#0x1e", 0x1e },
+ { "#0x1f", 0x1f },
+};
+#undef B
+\f
+/* Utilities on value constraint. */
+
+static inline int
+value_in_range_p (int64_t value, int low, int high)
+{
+ return (value >= low && value <= high) ? 1 : 0;
+}
+
+static inline int
+value_aligned_p (int64_t value, int align)
+{
+ return ((value & (align - 1)) == 0) ? 1 : 0;
+}
+
+/* A signed value fits in a field. */
+static inline int
+value_fit_signed_field_p (int64_t value, unsigned width)
+{
+ assert (width < 32);
+ if (width < sizeof (value) * 8)
+ {
+ int64_t lim = (int64_t)1 << (width - 1);
+ if (value >= -lim && value < lim)
+ return 1;
+ }
+ return 0;
+}
+
+/* An unsigned value fits in a field. */
+static inline int
+value_fit_unsigned_field_p (int64_t value, unsigned width)
+{
+ assert (width < 32);
+ if (width < sizeof (value) * 8)
+ {
+ int64_t lim = (int64_t)1 << width;
+ if (value >= 0 && value < lim)
+ return 1;
+ }
+ return 0;
+}
+
+/* Return 1 if OPERAND is SP or WSP. */
+int
+aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
+{
+ return ((aarch64_get_operand_class (operand->type)
+ == AARCH64_OPND_CLASS_INT_REG)
+ && operand_maybe_stack_pointer (aarch64_operands + operand->type)
+ && operand->reg.regno == 31);
+}
+
+/* Return 1 if OPERAND is XZR or WZP. */
+int
+aarch64_zero_register_p (const aarch64_opnd_info *operand)
+{
+ return ((aarch64_get_operand_class (operand->type)
+ == AARCH64_OPND_CLASS_INT_REG)
+ && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
+ && operand->reg.regno == 31);
+}
+
+/* Return true if the operand *OPERAND that has the operand code
+ OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
+ qualified by the qualifier TARGET. */
+
+static inline int
+operand_also_qualified_p (const struct aarch64_opnd_info *operand,
+ aarch64_opnd_qualifier_t target)
+{
+ switch (operand->qualifier)
+ {
+ case AARCH64_OPND_QLF_W:
+ if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
+ return 1;
+ break;
+ case AARCH64_OPND_QLF_X:
+ if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
+ return 1;
+ break;
+ case AARCH64_OPND_QLF_WSP:
+ if (target == AARCH64_OPND_QLF_W
+ && operand_maybe_stack_pointer (aarch64_operands + operand->type))
+ return 1;
+ break;
+ case AARCH64_OPND_QLF_SP:
+ if (target == AARCH64_OPND_QLF_X
+ && operand_maybe_stack_pointer (aarch64_operands + operand->type))
+ return 1;
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+/* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
+ for operand KNOWN_IDX, return the expected qualifier for operand IDX.
+
+ Return NIL if more than one expected qualifiers are found. */
+
+aarch64_opnd_qualifier_t
+aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
+ int idx,
+ const aarch64_opnd_qualifier_t known_qlf,
+ int known_idx)
+{
+ int i, saved_i;
+
+ /* Special case.
+
+ When the known qualifier is NIL, we have to assume that there is only
+ one qualifier sequence in the *QSEQ_LIST and return the corresponding
+ qualifier directly. One scenario is that for instruction
+ PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
+ which has only one possible valid qualifier sequence
+ NIL, S_D
+ the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
+ determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
+
+ Because the qualifier NIL has dual roles in the qualifier sequence:
+ it can mean no qualifier for the operand, or the qualifer sequence is
+ not in use (when all qualifiers in the sequence are NILs), we have to
+ handle this special case here. */
+ if (known_qlf == AARCH64_OPND_NIL)
+ {
+ assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
+ return qseq_list[0][idx];
+ }
+
+ for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
+ {
+ if (qseq_list[i][known_idx] == known_qlf)
+ {
+ if (saved_i != -1)
+ /* More than one sequences are found to have KNOWN_QLF at
+ KNOWN_IDX. */
+ return AARCH64_OPND_NIL;
+ saved_i = i;
+ }
+ }
+
+ return qseq_list[saved_i][idx];
+}
+
+enum operand_qualifier_kind
+{
+ OQK_NIL,
+ OQK_OPD_VARIANT,
+ OQK_VALUE_IN_RANGE,
+ OQK_MISC,
+};
+
+/* Operand qualifier description. */
+struct operand_qualifier_data
+{
+ /* The usage of the three data fields depends on the qualifier kind. */
+ int data0;
+ int data1;
+ int data2;
+ /* Description. */
+ const char *desc;
+ /* Kind. */
+ enum operand_qualifier_kind kind;
+};
+
+/* Indexed by the operand qualifier enumerators. */
+struct operand_qualifier_data aarch64_opnd_qualifiers[] =
+{
+ {0, 0, 0, "NIL", OQK_NIL},
+
+ /* Operand variant qualifiers.
+ First 3 fields:
+ element size, number of elements and common value for encoding. */
+
+ {4, 1, 0x0, "w", OQK_OPD_VARIANT},
+ {8, 1, 0x1, "x", OQK_OPD_VARIANT},
+ {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
+ {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
+
+ {1, 1, 0x0, "b", OQK_OPD_VARIANT},
+ {2, 1, 0x1, "h", OQK_OPD_VARIANT},
+ {4, 1, 0x2, "s", OQK_OPD_VARIANT},
+ {8, 1, 0x3, "d", OQK_OPD_VARIANT},
+ {16, 1, 0x4, "q", OQK_OPD_VARIANT},
+
+ {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
+ {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
+ {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
+ {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
+ {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
+ {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
+ {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
+ {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
+ {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
+
+ /* Qualifiers constraining the value range.
+ First 3 fields:
+ Lower bound, higher bound, unused. */
+
+ {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
+ {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
+ {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
+ {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
+ {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
+ {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
+
+ /* Qualifiers for miscellaneous purpose.
+ First 3 fields:
+ unused, unused and unused. */
+
+ {0, 0, 0, "lsl", 0},
+ {0, 0, 0, "msl", 0},
+
+ {0, 0, 0, "retrieving", 0},
+};
+
+static inline bfd_boolean
+operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
+{
+ return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
+ ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
+qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
+{
+ return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
+ ? TRUE : FALSE;
+}
+
+const char*
+aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
+{
+ return aarch64_opnd_qualifiers[qualifier].desc;
+}
+
+/* Given an operand qualifier, return the expected data element size
+ of a qualified operand. */
+unsigned char
+aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
+{
+ assert (operand_variant_qualifier_p (qualifier) == TRUE);
+ return aarch64_opnd_qualifiers[qualifier].data0;
+}
+
+unsigned char
+aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
+{
+ assert (operand_variant_qualifier_p (qualifier) == TRUE);
+ return aarch64_opnd_qualifiers[qualifier].data1;
+}
+
+aarch64_insn
+aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
+{
+ assert (operand_variant_qualifier_p (qualifier) == TRUE);
+ return aarch64_opnd_qualifiers[qualifier].data2;
+}
+
+static int
+get_lower_bound (aarch64_opnd_qualifier_t qualifier)
+{
+ assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
+ return aarch64_opnd_qualifiers[qualifier].data0;
+}
+
+static int
+get_upper_bound (aarch64_opnd_qualifier_t qualifier)
+{
+ assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
+ return aarch64_opnd_qualifiers[qualifier].data1;
+}
+
+#ifdef DEBUG_AARCH64
+void
+aarch64_verbose (const char *str, ...)
+{
+ va_list ap;
+ va_start (ap, str);
+ printf ("#### ");
+ vprintf (str, ap);
+ printf ("\n");
+ va_end (ap);
+}
+
+static inline void
+dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
+{
+ int i;
+ printf ("#### \t");
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
+ printf ("%s,", aarch64_get_qualifier_name (*qualifier));
+ printf ("\n");
+}
+
+static void
+dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
+ const aarch64_opnd_qualifier_t *qualifier)
+{
+ int i;
+ aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
+
+ aarch64_verbose ("dump_match_qualifiers:");
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ curr[i] = opnd[i].qualifier;
+ dump_qualifier_sequence (curr);
+ aarch64_verbose ("against");
+ dump_qualifier_sequence (qualifier);
+}
+#endif /* DEBUG_AARCH64 */
+
+/* TODO improve this, we can have an extra field at the runtime to
+ store the number of operands rather than calculating it every time. */
+
+int
+aarch64_num_of_operands (const aarch64_opcode *opcode)
+{
+ int i = 0;
+ const enum aarch64_opnd *opnds = opcode->operands;
+ while (opnds[i++] != AARCH64_OPND_NIL)
+ ;
+ --i;
+ assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
+ return i;
+}
+
+/* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
+ If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
+
+ N.B. on the entry, it is very likely that only some operands in *INST
+ have had their qualifiers been established.
+
+ If STOP_AT is not -1, the function will only try to match
+ the qualifier sequence for operands before and including the operand
+ of index STOP_AT; and on success *RET will only be filled with the first
+ (STOP_AT+1) qualifiers.
+
+ A couple examples of the matching algorithm:
+
+ X,W,NIL should match
+ X,W,NIL
+
+ NIL,NIL should match
+ X ,NIL
+
+ Apart from serving the main encoding routine, this can also be called
+ during or after the operand decoding. */
+
+int
+aarch64_find_best_match (const aarch64_inst *inst,
+ const aarch64_opnd_qualifier_seq_t *qualifiers_list,
+ int stop_at, aarch64_opnd_qualifier_t *ret)
+{
+ int found = 0;
+ int i, num_opnds;
+ const aarch64_opnd_qualifier_t *qualifiers;
+
+ num_opnds = aarch64_num_of_operands (inst->opcode);
+ if (num_opnds == 0)
+ {
+ DEBUG_TRACE ("SUCCEED: no operand");
+ return 1;
+ }
+
+ if (stop_at < 0 || stop_at >= num_opnds)
+ stop_at = num_opnds - 1;
+
+ /* For each pattern. */
+ for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
+ {
+ int j;
+ qualifiers = *qualifiers_list;
+
+ /* Start as positive. */
+ found = 1;
+
+ DEBUG_TRACE ("%d", i);
+#ifdef DEBUG_AARCH64
+ if (debug_dump)
+ dump_match_qualifiers (inst->operands, qualifiers);
+#endif
+
+ /* Most opcodes has much fewer patterns in the list.
+ First NIL qualifier indicates the end in the list. */
+ if (empty_qualifier_sequence_p (qualifiers) == TRUE)
+ {
+ DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
+ if (i)
+ found = 0;
+ break;
+ }
+
+ for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
+ {
+ if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
+ {
+ /* Either the operand does not have qualifier, or the qualifier
+ for the operand needs to be deduced from the qualifier
+ sequence.
+ In the latter case, any constraint checking related with
+ the obtained qualifier should be done later in
+ operand_general_constraint_met_p. */
+ continue;
+ }
+ else if (*qualifiers != inst->operands[j].qualifier)
+ {
+ /* Unless the target qualifier can also qualify the operand
+ (which has already had a non-nil qualifier), non-equal
+ qualifiers are generally un-matched. */
+ if (operand_also_qualified_p (inst->operands + j, *qualifiers))
+ continue;
+ else
+ {
+ found = 0;
+ break;
+ }
+ }
+ else
+ continue; /* Equal qualifiers are certainly matched. */
+ }
+
+ /* Qualifiers established. */
+ if (found == 1)
+ break;
+ }
+
+ if (found == 1)
+ {
+ /* Fill the result in *RET. */
+ int j;
+ qualifiers = *qualifiers_list;
+
+ DEBUG_TRACE ("complete qualifiers using list %d", i);
+#ifdef DEBUG_AARCH64
+ if (debug_dump)
+ dump_qualifier_sequence (qualifiers);
+#endif
+
+ for (j = 0; j <= stop_at; ++j, ++qualifiers)
+ ret[j] = *qualifiers;
+ for (; j < AARCH64_MAX_OPND_NUM; ++j)
+ ret[j] = AARCH64_OPND_QLF_NIL;
+
+ DEBUG_TRACE ("SUCCESS");
+ return 1;
+ }
+
+ DEBUG_TRACE ("FAIL");
+ return 0;
+}
+
+/* Operand qualifier matching and resolving.
+
+ Return 1 if the operand qualifier(s) in *INST match one of the qualifier
+ sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
+
+ if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
+ succeeds. */
+
+static int
+match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
+{
+ int i;
+ aarch64_opnd_qualifier_seq_t qualifiers;
+
+ if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
+ qualifiers))
+ {
+ DEBUG_TRACE ("matching FAIL");
+ return 0;
+ }
+
+ /* Update the qualifiers. */
+ if (update_p == TRUE)
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ {
+ if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
+ break;
+ DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
+ "update %s with %s for operand %d",
+ aarch64_get_qualifier_name (inst->operands[i].qualifier),
+ aarch64_get_qualifier_name (qualifiers[i]), i);
+ inst->operands[i].qualifier = qualifiers[i];
+ }
+
+ DEBUG_TRACE ("matching SUCCESS");
+ return 1;
+}
+
+/* Return TRUE if VALUE is a wide constant that can be moved into a general
+ register by MOVZ.
+
+ IS32 indicates whether value is a 32-bit immediate or not.
+ If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
+ amount will be returned in *SHIFT_AMOUNT. */
+
+bfd_boolean
+aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
+{
+ int amount;
+
+ DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
+
+ if (is32)
+ {
+ /* Allow all zeros or all ones in top 32-bits, so that
+ 32-bit constant expressions like ~0x80000000 are
+ permitted. */
+ uint64_t ext = value;
+ if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
+ /* Immediate out of range. */
+ return FALSE;
+ value &= (int64_t) 0xffffffff;
+ }
+
+ /* first, try movz then movn */
+ amount = -1;
+ if ((value & ((int64_t) 0xffff << 0)) == value)
+ amount = 0;
+ else if ((value & ((int64_t) 0xffff << 16)) == value)
+ amount = 16;
+ else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
+ amount = 32;
+ else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
+ amount = 48;
+
+ if (amount == -1)
+ {
+ DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
+ return FALSE;
+ }
+
+ if (shift_amount != NULL)
+ *shift_amount = amount;
+
+ DEBUG_TRACE ("exit TRUE with amount %d", amount);
+
+ return TRUE;
+}
+
+/* Build the accepted values for immediate logical SIMD instructions.
+
+ The standard encodings of the immediate value are:
+ N imms immr SIMD size R S
+ 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
+ 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
+ 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
+ 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
+ 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
+ 0 11110s 00000r 2 UInt(r) UInt(s)
+ where all-ones value of S is reserved.
+
+ Let's call E the SIMD size.
+
+ The immediate value is: S+1 bits '1' rotated to the right by R.
+
+ The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
+ (remember S != E - 1). */
+
+#define TOTAL_IMM_NB 5334
+
+typedef struct
+{
+ uint64_t imm;
+ aarch64_insn encoding;
+} simd_imm_encoding;
+
+static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
+
+static int
+simd_imm_encoding_cmp(const void *i1, const void *i2)
+{
+ const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
+ const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
+
+ if (imm1->imm < imm2->imm)
+ return -1;
+ if (imm1->imm > imm2->imm)
+ return +1;
+ return 0;
+}
+
+/* immediate bitfield standard encoding
+ imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
+ 1 ssssss rrrrrr 64 rrrrrr ssssss
+ 0 0sssss 0rrrrr 32 rrrrr sssss
+ 0 10ssss 00rrrr 16 rrrr ssss
+ 0 110sss 000rrr 8 rrr sss
+ 0 1110ss 0000rr 4 rr ss
+ 0 11110s 00000r 2 r s */
+static inline int
+encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
+{
+ return (is64 << 12) | (r << 6) | s;
+}
+
+static void
+build_immediate_table (void)
+{
+ uint32_t log_e, e, s, r, s_mask;
+ uint64_t mask, imm;
+ int nb_imms;
+ int is64;
+
+ nb_imms = 0;
+ for (log_e = 1; log_e <= 6; log_e++)
+ {
+ /* Get element size. */
+ e = 1u << log_e;
+ if (log_e == 6)
+ {
+ is64 = 1;
+ mask = 0xffffffffffffffffull;
+ s_mask = 0;
+ }
+ else
+ {
+ is64 = 0;
+ mask = (1ull << e) - 1;
+ /* log_e s_mask
+ 1 ((1 << 4) - 1) << 2 = 111100
+ 2 ((1 << 3) - 1) << 3 = 111000
+ 3 ((1 << 2) - 1) << 4 = 110000
+ 4 ((1 << 1) - 1) << 5 = 100000
+ 5 ((1 << 0) - 1) << 6 = 000000 */
+ s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
+ }
+ for (s = 0; s < e - 1; s++)
+ for (r = 0; r < e; r++)
+ {
+ /* s+1 consecutive bits to 1 (s < 63) */
+ imm = (1ull << (s + 1)) - 1;
+ /* rotate right by r */
+ if (r != 0)
+ imm = (imm >> r) | ((imm << (e - r)) & mask);
+ /* replicate the constant depending on SIMD size */
+ switch (log_e)
+ {
+ case 1: imm = (imm << 2) | imm;
+ case 2: imm = (imm << 4) | imm;
+ case 3: imm = (imm << 8) | imm;
+ case 4: imm = (imm << 16) | imm;
+ case 5: imm = (imm << 32) | imm;
+ case 6: break;
+ default: abort ();
+ }
+ simd_immediates[nb_imms].imm = imm;
+ simd_immediates[nb_imms].encoding =
+ encode_immediate_bitfield(is64, s | s_mask, r);
+ nb_imms++;
+ }
+ }
+ assert (nb_imms == TOTAL_IMM_NB);
+ qsort(simd_immediates, nb_imms,
+ sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
+}
+
+/* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
+ be accepted by logical (immediate) instructions
+ e.g. ORR <Xd|SP>, <Xn>, #<imm>.
+
+ IS32 indicates whether or not VALUE is a 32-bit immediate.
+ If ENCODING is not NULL, on the return of TRUE, the standard encoding for
+ VALUE will be returned in *ENCODING. */
+
+bfd_boolean
+aarch64_logical_immediate_p (uint64_t value, int is32, aarch64_insn *encoding)
+{
+ simd_imm_encoding imm_enc;
+ const simd_imm_encoding *imm_encoding;
+ static bfd_boolean initialized = FALSE;
+
+ DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), is32: %d", value,
+ value, is32);
+
+ if (initialized == FALSE)
+ {
+ build_immediate_table ();
+ initialized = TRUE;
+ }
+
+ if (is32)
+ {
+ /* Allow all zeros or all ones in top 32-bits, so that
+ constant expressions like ~1 are permitted. */
+ if (value >> 32 != 0 && value >> 32 != 0xffffffff)
+ return 0xffffffff;
+ /* Replicate the 32 lower bits to the 32 upper bits. */
+ value &= 0xffffffff;
+ value |= value << 32;
+ }
+
+ imm_enc.imm = value;
+ imm_encoding = (const simd_imm_encoding *)
+ bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
+ sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
+ if (imm_encoding == NULL)
+ {
+ DEBUG_TRACE ("exit with FALSE");
+ return FALSE;
+ }
+ if (encoding != NULL)
+ *encoding = imm_encoding->encoding;
+ DEBUG_TRACE ("exit with TRUE");
+ return TRUE;
+}
+
+/* If 64-bit immediate IMM is in the format of
+ "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
+ where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
+ of value "abcdefgh". Otherwise return -1. */
+int
+aarch64_shrink_expanded_imm8 (uint64_t imm)
+{
+ int i, ret;
+ uint32_t byte;
+
+ ret = 0;
+ for (i = 0; i < 8; i++)
+ {
+ byte = (imm >> (8 * i)) & 0xff;
+ if (byte == 0xff)
+ ret |= 1 << i;
+ else if (byte != 0x00)
+ return -1;
+ }
+ return ret;
+}
+
+/* Utility inline functions for operand_general_constraint_met_p. */
+
+static inline void
+set_error (aarch64_operand_error *mismatch_detail,
+ enum aarch64_operand_error_kind kind, int idx,
+ const char* error)
+{
+ if (mismatch_detail == NULL)
+ return;
+ mismatch_detail->kind = kind;
+ mismatch_detail->index = idx;
+ mismatch_detail->error = error;
+}
+
+static inline void
+set_out_of_range_error (aarch64_operand_error *mismatch_detail,
+ int idx, int lower_bound, int upper_bound,
+ const char* error)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
+ mismatch_detail->data[0] = lower_bound;
+ mismatch_detail->data[1] = upper_bound;
+}
+
+static inline void
+set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
+ int idx, int lower_bound, int upper_bound)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
+ _("immediate value"));
+}
+
+static inline void
+set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
+ int idx, int lower_bound, int upper_bound)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
+ _("immediate offset"));
+}
+
+static inline void
+set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
+ int idx, int lower_bound, int upper_bound)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
+ _("register number"));
+}
+
+static inline void
+set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
+ int idx, int lower_bound, int upper_bound)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
+ _("register element index"));
+}
+
+static inline void
+set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
+ int idx, int lower_bound, int upper_bound)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
+ _("shift amount"));
+}
+
+static inline void
+set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
+ int alignment)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
+ mismatch_detail->data[0] = alignment;
+}
+
+static inline void
+set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
+ int expected_num)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
+ mismatch_detail->data[0] = expected_num;
+}
+
+static inline void
+set_other_error (aarch64_operand_error *mismatch_detail, int idx,
+ const char* error)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
+}
+
+/* General constraint checking based on operand code.
+
+ Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
+ as the IDXth operand of opcode OPCODE. Otherwise return 0.
+
+ This function has to be called after the qualifiers for all operands
+ have been resolved.
+
+ Mismatching error message is returned in *MISMATCH_DETAIL upon request,
+ i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
+ of error message during the disassembling where error message is not
+ wanted. We avoid the dynamic construction of strings of error messages
+ here (i.e. in libopcodes), as it is costly and complicated; instead, we
+ use a combination of error code, static string and some integer data to
+ represent an error. */
+
+static int
+operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
+ enum aarch64_opnd type,
+ const aarch64_opcode *opcode,
+ aarch64_operand_error *mismatch_detail)
+{
+ unsigned num;
+ unsigned char size;
+ int64_t imm;
+ const aarch64_opnd_info *opnd = opnds + idx;
+ aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
+
+ assert (opcode->operands[idx] == opnd->type && opnd->type == type);
+
+ switch (aarch64_operands[type].op_class)
+ {
+ case AARCH64_OPND_CLASS_INT_REG:
+ /* <Xt> may be optional in some IC and TLBI instructions. */
+ if (type == AARCH64_OPND_Rt_SYS)
+ {
+ assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
+ == AARCH64_OPND_CLASS_SYSTEM));
+ if (opnds[1].present && !opnds[0].sysins_op->has_xt)
+ {
+ set_other_error (mismatch_detail, idx, _("extraneous register"));
+ return 0;
+ }
+ if (!opnds[1].present && opnds[0].sysins_op->has_xt)
+ {
+ set_other_error (mismatch_detail, idx, _("missing register"));
+ return 0;
+ }
+ }
+ switch (qualifier)
+ {
+ case AARCH64_OPND_QLF_WSP:
+ case AARCH64_OPND_QLF_SP:
+ if (!aarch64_stack_pointer_p (opnd))
+ {
+ set_other_error (mismatch_detail, idx,
+ _("stack pointer register expected"));
+ return 0;
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case AARCH64_OPND_CLASS_ADDRESS:
+ /* Check writeback. */
+ switch (opcode->iclass)
+ {
+ case ldst_pos:
+ case ldst_unscaled:
+ case ldstnapair_offs:
+ case ldstpair_off:
+ case ldst_unpriv:
+ if (opnd->addr.writeback == 1)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("unexpected address writeback"));
+ return 0;
+ }
+ break;
+ case ldst_imm9:
+ case ldstpair_indexed:
+ case asisdlsep:
+ case asisdlsop:
+ if (opnd->addr.writeback == 0)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("address writeback expected"));
+ return 0;
+ }
+ break;
+ default:
+ assert (opnd->addr.writeback == 0);
+ break;
+ }
+ switch (type)
+ {
+ case AARCH64_OPND_ADDR_SIMM7:
+ /* Scaled signed 7 bits immediate offset. */
+ /* Get the size of the data element that is accessed, which may be
+ different from that of the source register size,
+ e.g. in strb/ldrb. */
+ size = aarch64_get_qualifier_esize (opnd->qualifier);
+ if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
+ {
+ set_offset_out_of_range_error (mismatch_detail, idx,
+ -64 * size, 63 * size);
+ return 0;
+ }
+ if (!value_aligned_p (opnd->addr.offset.imm, size))
+ {
+ set_unaligned_error (mismatch_detail, idx, size);
+ return 0;
+ }
+ break;
+ case AARCH64_OPND_ADDR_SIMM9:
+ /* Unscaled signed 9 bits immediate offset. */
+ if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
+ {
+ set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_ADDR_SIMM9_2:
+ /* Unscaled signed 9 bits immediate offset, which has to be negative
+ or unaligned. */
+ size = aarch64_get_qualifier_esize (qualifier);
+ if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
+ && !value_aligned_p (opnd->addr.offset.imm, size))
+ || value_in_range_p (opnd->addr.offset.imm, -256, -1))
+ return 1;
+ set_other_error (mismatch_detail, idx,
+ _("negative or unaligned offset expected"));
+ return 0;
+
+ case AARCH64_OPND_SIMD_ADDR_POST:
+ /* AdvSIMD load/store multiple structures, post-index. */
+ assert (idx == 1);
+ if (opnd->addr.offset.is_reg)
+ {
+ if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
+ return 1;
+ else
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid register offset"));
+ return 0;
+ }
+ }
+ else
+ {
+ const aarch64_opnd_info *prev = &opnds[idx-1];
+ unsigned num_bytes; /* total number of bytes transferred. */
+ /* The opcode dependent area stores the number of elements in
+ each structure to be loaded/stored. */
+ int is_ld1r = get_opcode_dependent_value (opcode) == 1;
+ if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
+ /* Special handling of loading single structure to all lane. */
+ num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
+ * aarch64_get_qualifier_esize (prev->qualifier);
+ else
+ num_bytes = prev->reglist.num_regs
+ * aarch64_get_qualifier_esize (prev->qualifier)
+ * aarch64_get_qualifier_nelem (prev->qualifier);
+ if ((int) num_bytes != opnd->addr.offset.imm)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid post-increment amount"));
+ return 0;
+ }
+ }
+ break;
+
+ case AARCH64_OPND_ADDR_REGOFF:
+ /* Get the size of the data element that is accessed, which may be
+ different from that of the source register size,
+ e.g. in strb/ldrb. */
+ size = aarch64_get_qualifier_esize (opnd->qualifier);
+ /* It is either no shift or shift by the binary logarithm of SIZE. */
+ if (opnd->shifter.amount != 0
+ && opnd->shifter.amount != (int)get_logsz (size))
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid shift amount"));
+ return 0;
+ }
+ /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
+ operators. */
+ switch (opnd->shifter.kind)
+ {
+ case AARCH64_MOD_UXTW:
+ case AARCH64_MOD_LSL:
+ case AARCH64_MOD_SXTW:
+ case AARCH64_MOD_SXTX: break;
+ default:
+ set_other_error (mismatch_detail, idx,
+ _("invalid extend/shift operator"));
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_ADDR_UIMM12:
+ imm = opnd->addr.offset.imm;
+ /* Get the size of the data element that is accessed, which may be
+ different from that of the source register size,
+ e.g. in strb/ldrb. */
+ size = aarch64_get_qualifier_esize (qualifier);
+ if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
+ {
+ set_offset_out_of_range_error (mismatch_detail, idx,
+ 0, 4095 * size);
+ return 0;
+ }
+ if (!value_aligned_p (opnd->shifter.amount, size))
+ {
+ set_unaligned_error (mismatch_detail, idx, size);
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_ADDR_PCREL14:
+ case AARCH64_OPND_ADDR_PCREL19:
+ case AARCH64_OPND_ADDR_PCREL21:
+ case AARCH64_OPND_ADDR_PCREL26:
+ imm = opnd->imm.value;
+ if (operand_need_shift_by_two (get_operand_from_code (type)))
+ {
+ /* The offset value in a PC-relative branch instruction is alway
+ 4-byte aligned and is encoded without the lowest 2 bits. */
+ if (!value_aligned_p (imm, 4))
+ {
+ set_unaligned_error (mismatch_detail, idx, 4);
+ return 0;
+ }
+ /* Right shift by 2 so that we can carry out the following check
+ canonically. */
+ imm >>= 2;
+ }
+ size = get_operand_fields_width (get_operand_from_code (type));
+ if (!value_fit_signed_field_p (imm, size))
+ {
+ set_other_error (mismatch_detail, idx,
+ _("immediate out of range"));
+ return 0;
+ }
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ case AARCH64_OPND_CLASS_SIMD_REGLIST:
+ /* The opcode dependent area stores the number of elements in
+ each structure to be loaded/stored. */
+ num = get_opcode_dependent_value (opcode);
+ switch (type)
+ {
+ case AARCH64_OPND_LVt:
+ assert (num >= 1 && num <= 4);
+ /* Unless LD1/ST1, the number of registers should be equal to that
+ of the structure elements. */
+ if (num != 1 && opnd->reglist.num_regs != num)
+ {
+ set_reg_list_error (mismatch_detail, idx, num);
+ return 0;
+ }
+ break;
+ case AARCH64_OPND_LVt_AL:
+ case AARCH64_OPND_LEt:
+ assert (num >= 1 && num <= 4);
+ /* The number of registers should be equal to that of the structure
+ elements. */
+ if (opnd->reglist.num_regs != num)
+ {
+ set_reg_list_error (mismatch_detail, idx, num);
+ return 0;
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case AARCH64_OPND_CLASS_IMMEDIATE:
+ /* Constraint check on immediate operand. */
+ imm = opnd->imm.value;
+ /* E.g. imm_0_31 constrains value to be 0..31. */
+ if (qualifier_value_in_range_constraint_p (qualifier)
+ && !value_in_range_p (imm, get_lower_bound (qualifier),
+ get_upper_bound (qualifier)))
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx,
+ get_lower_bound (qualifier),
+ get_upper_bound (qualifier));
+ return 0;
+ }
+
+ switch (type)
+ {
+ case AARCH64_OPND_AIMM:
+ if (opnd->shifter.kind != AARCH64_MOD_LSL)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid shift operator"));
+ return 0;
+ }
+ if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("shift amount expected to be 0 or 12"));
+ return 0;
+ }
+ if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
+ {
+ set_other_error (mismatch_detail, idx,
+ _("immediate out of range"));
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_HALF:
+ assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
+ if (opnd->shifter.kind != AARCH64_MOD_LSL)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid shift operator"));
+ return 0;
+ }
+ size = aarch64_get_qualifier_esize (opnds[0].qualifier);
+ if (!value_aligned_p (opnd->shifter.amount, 16))
+ {
+ set_other_error (mismatch_detail, idx,
+ _("shift amount should be a multiple of 16"));
+ return 0;
+ }
+ if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
+ {
+ set_sft_amount_out_of_range_error (mismatch_detail, idx,
+ 0, size * 8 - 16);
+ return 0;
+ }
+ if (opnd->imm.value < 0)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("negative immediate value not allowed"));
+ return 0;
+ }
+ if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
+ {
+ set_other_error (mismatch_detail, idx,
+ _("immediate out of range"));
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_IMM_MOV:
+ {
+ int is32 = aarch64_get_qualifier_esize (opnds[0].qualifier) == 4;
+ imm = opnd->imm.value;
+ assert (idx == 1);
+ switch (opcode->op)
+ {
+ case OP_MOV_IMM_WIDEN:
+ imm = ~imm;
+ /* Fall through... */
+ case OP_MOV_IMM_WIDE:
+ if (!aarch64_wide_constant_p (imm, is32, NULL))
+ {
+ set_other_error (mismatch_detail, idx,
+ _("immediate out of range"));
+ return 0;
+ }
+ break;
+ case OP_MOV_IMM_LOG:
+ if (!aarch64_logical_immediate_p (imm, is32, NULL))
+ {
+ set_other_error (mismatch_detail, idx,
+ _("immediate out of range"));
+ return 0;
+ }
+ break;
+ default:
+ assert (0);
+ return 0;
+ }
+ }
+ break;
+
+ case AARCH64_OPND_NZCV:
+ case AARCH64_OPND_CCMP_IMM:
+ case AARCH64_OPND_EXCEPTION:
+ case AARCH64_OPND_UIMM4:
+ case AARCH64_OPND_UIMM7:
+ case AARCH64_OPND_UIMM3_OP1:
+ case AARCH64_OPND_UIMM3_OP2:
+ size = get_operand_fields_width (get_operand_from_code (type));
+ assert (size < 32);
+ if (!value_fit_unsigned_field_p (opnd->imm.value, size))
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, 0,
+ (1 << size) - 1);
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_WIDTH:
+ assert (idx == 3 && opnds[idx-1].type == AARCH64_OPND_IMM
+ && opnds[0].type == AARCH64_OPND_Rd);
+ size = get_upper_bound (qualifier);
+ if (opnd->imm.value + opnds[idx-1].imm.value > size)
+ /* lsb+width <= reg.size */
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, 1,
+ size - opnds[idx-1].imm.value);
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_LIMM:
+ {
+ int is32 = opnds[0].qualifier == AARCH64_OPND_QLF_W;
+ uint64_t uimm = opnd->imm.value;
+ if (opcode->op == OP_BIC)
+ uimm = ~uimm;
+ if (aarch64_logical_immediate_p (uimm, is32, NULL) == FALSE)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("immediate out of range"));
+ return 0;
+ }
+ }
+ break;
+
+ case AARCH64_OPND_IMM0:
+ case AARCH64_OPND_FPIMM0:
+ if (opnd->imm.value != 0)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("immediate zero expected"));
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_SHLL_IMM:
+ assert (idx == 2);
+ size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
+ if (opnd->imm.value != size)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid shift amount"));
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_IMM_VLSL:
+ size = aarch64_get_qualifier_esize (qualifier);
+ if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, 0,
+ size * 8 - 1);
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_IMM_VLSR:
+ size = aarch64_get_qualifier_esize (qualifier);
+ if (!value_in_range_p (opnd->imm.value, 1, size * 8))
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_SIMD_IMM:
+ case AARCH64_OPND_SIMD_IMM_SFT:
+ /* Qualifier check. */
+ switch (qualifier)
+ {
+ case AARCH64_OPND_QLF_LSL:
+ if (opnd->shifter.kind != AARCH64_MOD_LSL)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid shift operator"));
+ return 0;
+ }
+ break;
+ case AARCH64_OPND_QLF_MSL:
+ if (opnd->shifter.kind != AARCH64_MOD_MSL)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid shift operator"));
+ return 0;
+ }
+ break;
+ case AARCH64_OPND_QLF_NIL:
+ if (opnd->shifter.kind != AARCH64_MOD_NONE)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("shift is not permitted"));
+ return 0;
+ }
+ break;
+ default:
+ assert (0);
+ return 0;
+ }
+ /* Is the immediate valid? */
+ assert (idx == 1);
+ if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
+ {
+ /* uimm8 */
+ if (!value_in_range_p (opnd->imm.value, 0, 255))
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, 0, 255);
+ return 0;
+ }
+ }
+ else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
+ {
+ /* uimm64 is not
+ 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
+ ffffffffgggggggghhhhhhhh'. */
+ set_other_error (mismatch_detail, idx,
+ _("invalid value for immediate"));
+ return 0;
+ }
+ /* Is the shift amount valid? */
+ switch (opnd->shifter.kind)
+ {
+ case AARCH64_MOD_LSL:
+ size = aarch64_get_qualifier_esize (opnds[0].qualifier);
+ if (!value_aligned_p (opnd->shifter.amount, 8))
+ {
+ set_unaligned_error (mismatch_detail, idx, 8);
+ return 0;
+ }
+ if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, 0,
+ (size - 1) * 8);
+ return 0;
+ }
+ break;
+ case AARCH64_MOD_MSL:
+ /* Only 8 and 16 are valid shift amount. */
+ if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("shift amount expected to be 0 or 16"));
+ return 0;
+ }
+ break;
+ default:
+ if (opnd->shifter.kind != AARCH64_MOD_NONE)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid shift operator"));
+ return 0;
+ }
+ break;
+ }
+ break;
+
+ case AARCH64_OPND_FPIMM:
+ case AARCH64_OPND_SIMD_FPIMM:
+ if (opnd->imm.is_fp == 0)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("floating-point immediate expected"));
+ return 0;
+ }
+ /* The value is expected to be an 8-bit floating-point constant with
+ sign, 3-bit exponent and normalized 4 bits of precision, encoded
+ in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
+ instruction). */
+ if (!value_in_range_p (opnd->imm.value, 0, 255))
+ {
+ set_other_error (mismatch_detail, idx,
+ _("immediate out of range"));
+ return 0;
+ }
+ if (opnd->shifter.kind != AARCH64_MOD_NONE)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid shift operator"));
+ return 0;
+ }
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ case AARCH64_OPND_CLASS_CP_REG:
+ /* Cn or Cm: 4-bit opcode field named for historical reasons.
+ valid range: C0 - C15. */
+ if (opnd->reg.regno > 15)
+ {
+ set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_CLASS_SYSTEM:
+ switch (type)
+ {
+ case AARCH64_OPND_PSTATEFIELD:
+ assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
+ /* MSR SPSel, #uimm4
+ Uses uimm4 as a control value to select the stack pointer: if
+ bit 0 is set it selects the current exception level's stack
+ pointer, if bit 0 is clear it selects shared EL0 stack pointer.
+ Bits 1 to 3 of uimm4 are reserved and should be zero. */
+ if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
+ return 0;
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case AARCH64_OPND_CLASS_SIMD_ELEMENT:
+ /* Get the upper bound for the element index. */
+ num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
+ /* Index out-of-range. */
+ if (!value_in_range_p (opnd->reglane.index, 0, num))
+ {
+ set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
+ return 0;
+ }
+ /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
+ <Vm> Is the vector register (V0-V31) or (V0-V15), whose
+ number is encoded in "size:M:Rm":
+ size <Vm>
+ 00 RESERVED
+ 01 0:Rm
+ 10 M:Rm
+ 11 RESERVED */
+ if (type == AARCH64_OPND_Em && qualifier == AARCH64_OPND_QLF_S_H
+ && !value_in_range_p (opnd->reglane.regno, 0, 15))
+ {
+ set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_CLASS_MODIFIED_REG:
+ assert (idx == 1 || idx == 2);
+ switch (type)
+ {
+ case AARCH64_OPND_Rm_EXT:
+ if (aarch64_extend_operator_p (opnd->shifter.kind) == FALSE
+ && opnd->shifter.kind != AARCH64_MOD_LSL)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("extend operator expected"));
+ return 0;
+ }
+ /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
+ (i.e. SP), in which case it defaults to LSL. The LSL alias is
+ only valid when "Rd" or "Rn" is '11111', and is preferred in that
+ case. */
+ if (!aarch64_stack_pointer_p (opnds + 0)
+ && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
+ {
+ if (!opnd->shifter.operator_present)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("missing extend operator"));
+ return 0;
+ }
+ else if (opnd->shifter.kind == AARCH64_MOD_LSL)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("'LSL' operator not allowed"));
+ return 0;
+ }
+ }
+ assert (opnd->shifter.operator_present /* Default to LSL. */
+ || opnd->shifter.kind == AARCH64_MOD_LSL);
+ if (!value_in_range_p (opnd->shifter.amount, 0, 4))
+ {
+ set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
+ return 0;
+ }
+ /* In the 64-bit form, the final register operand is written as Wm
+ for all but the (possibly omitted) UXTX/LSL and SXTX
+ operators.
+ N.B. GAS allows X register to be used with any operator as a
+ programming convenience. */
+ if (qualifier == AARCH64_OPND_QLF_X
+ && opnd->shifter.kind != AARCH64_MOD_LSL
+ && opnd->shifter.kind != AARCH64_MOD_UXTX
+ && opnd->shifter.kind != AARCH64_MOD_SXTX)
+ {
+ set_other_error (mismatch_detail, idx, _("W register expected"));
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_Rm_SFT:
+ /* ROR is not available to the shifted register operand in
+ arithmetic instructions. */
+ if (aarch64_shift_operator_p (opnd->shifter.kind) == FALSE)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("shift operator expected"));
+ return 0;
+ }
+ if (opnd->shifter.kind == AARCH64_MOD_ROR
+ && opcode->iclass != log_shift)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("'ROR' operator not allowed"));
+ return 0;
+ }
+ num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
+ if (!value_in_range_p (opnd->shifter.amount, 0, num))
+ {
+ set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
+ return 0;
+ }
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return 1;
+}
+
+/* Main entrypoint for the operand constraint checking.
+
+ Return 1 if operands of *INST meet the constraint applied by the operand
+ codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
+ not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
+ adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
+ with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
+ error kind when it is notified that an instruction does not pass the check).
+
+ Un-determined operand qualifiers may get established during the process. */
+
+int
+aarch64_match_operands_constraint (aarch64_inst *inst,
+ aarch64_operand_error *mismatch_detail)
+{
+ int i;
+
+ DEBUG_TRACE ("enter");
+
+ /* Match operands' qualifier.
+ *INST has already had qualifier establish for some, if not all, of
+ its operands; we need to find out whether these established
+ qualifiers match one of the qualifier sequence in
+ INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
+ with the corresponding qualifier in such a sequence.
+ Only basic operand constraint checking is done here; the more thorough
+ constraint checking will carried out by operand_general_constraint_met_p,
+ which has be to called after this in order to get all of the operands'
+ qualifiers established. */
+ if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
+ {
+ DEBUG_TRACE ("FAIL on operand qualifier matching");
+ if (mismatch_detail)
+ {
+ /* Return an error type to indicate that it is the qualifier
+ matching failure; we don't care about which operand as there
+ are enough information in the opcode table to reproduce it. */
+ mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
+ mismatch_detail->index = -1;
+ mismatch_detail->error = NULL;
+ }
+ return 0;
+ }
+
+ /* Match operands' constraint. */
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ {
+ enum aarch64_opnd type = inst->opcode->operands[i];
+ if (type == AARCH64_OPND_NIL)
+ break;
+ if (inst->operands[i].skip)
+ {
+ DEBUG_TRACE ("skip the incomplete operand %d", i);
+ continue;
+ }
+ if (operand_general_constraint_met_p (inst->operands, i, type,
+ inst->opcode, mismatch_detail) == 0)
+ {
+ DEBUG_TRACE ("FAIL on operand %d", i);
+ return 0;
+ }
+ }
+
+ DEBUG_TRACE ("PASS");
+
+ return 1;
+}
+
+/* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
+ Also updates the TYPE of each INST->OPERANDS with the corresponding
+ value of OPCODE->OPERANDS.
+
+ Note that some operand qualifiers may need to be manually cleared by
+ the caller before it further calls the aarch64_opcode_encode; by
+ doing this, it helps the qualifier matching facilities work
+ properly. */
+
+const aarch64_opcode*
+aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
+{
+ int i;
+ const aarch64_opcode *old = inst->opcode;
+
+ inst->opcode = opcode;
+
+ /* Update the operand types. */
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ {
+ inst->operands[i].type = opcode->operands[i];
+ if (opcode->operands[i] == AARCH64_OPND_NIL)
+ break;
+ }
+
+ DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
+
+ return old;
+}
+
+int
+aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
+{
+ int i;
+ for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+ if (operands[i] == operand)
+ return i;
+ else if (operands[i] == AARCH64_OPND_NIL)
+ break;
+ return -1;
+}
+\f
+/* [0][0] 32-bit integer regs with sp Wn
+ [0][1] 64-bit integer regs with sp Xn sf=1
+ [1][0] 32-bit integer regs with #0 Wn
+ [1][1] 64-bit integer regs with #0 Xn sf=1 */
+static const char *int_reg[2][2][32] = {
+#define R32 "w"
+#define R64 "x"
+ { { R32 "0", R32 "1", R32 "2", R32 "3", R32 "4", R32 "5", R32 "6", R32 "7",
+ R32 "8", R32 "9", R32 "10", R32 "11", R32 "12", R32 "13", R32 "14", R32 "15",
+ R32 "16", R32 "17", R32 "18", R32 "19", R32 "20", R32 "21", R32 "22", R32 "23",
+ R32 "24", R32 "25", R32 "26", R32 "27", R32 "28", R32 "29", R32 "30", "wsp" },
+ { R64 "0", R64 "1", R64 "2", R64 "3", R64 "4", R64 "5", R64 "6", R64 "7",
+ R64 "8", R64 "9", R64 "10", R64 "11", R64 "12", R64 "13", R64 "14", R64 "15",
+ R64 "16", R64 "17", R64 "18", R64 "19", R64 "20", R64 "21", R64 "22", R64 "23",
+ R64 "24", R64 "25", R64 "26", R64 "27", R64 "28", R64 "29", R64 "30", "sp" } },
+ { { R32 "0", R32 "1", R32 "2", R32 "3", R32 "4", R32 "5", R32 "6", R32 "7",
+ R32 "8", R32 "9", R32 "10", R32 "11", R32 "12", R32 "13", R32 "14", R32 "15",
+ R32 "16", R32 "17", R32 "18", R32 "19", R32 "20", R32 "21", R32 "22", R32 "23",
+ R32 "24", R32 "25", R32 "26", R32 "27", R32 "28", R32 "29", R32 "30", R32 "zr" },
+ { R64 "0", R64 "1", R64 "2", R64 "3", R64 "4", R64 "5", R64 "6", R64 "7",
+ R64 "8", R64 "9", R64 "10", R64 "11", R64 "12", R64 "13", R64 "14", R64 "15",
+ R64 "16", R64 "17", R64 "18", R64 "19", R64 "20", R64 "21", R64 "22", R64 "23",
+ R64 "24", R64 "25", R64 "26", R64 "27", R64 "28", R64 "29", R64 "30", R64 "zr" } }
+#undef R64
+#undef R32
+};
+
+/* Return the integer register name.
+ if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
+
+static inline const char *
+get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
+{
+ const int has_zr = sp_reg_p ? 0 : 1;
+ const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
+ return int_reg[has_zr][is_64][regno];
+}
+
+/* Like get_int_reg_name, but IS_64 is always 1. */
+
+static inline const char *
+get_64bit_int_reg_name (int regno, int sp_reg_p)
+{
+ const int has_zr = sp_reg_p ? 0 : 1;
+ return int_reg[has_zr][1][regno];
+}
+
+/* Types for expanding an encoded 8-bit value to a floating-point value. */
+
+typedef union
+{
+ uint64_t i;
+ double d;
+} double_conv_t;
+
+typedef union
+{
+ uint32_t i;
+ float f;
+} single_conv_t;
+
+/* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
+ normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
+ (depending on the type of the instruction). IMM8 will be expanded to a
+ single-precision floating-point value (IS_DP == 0) or a double-precision
+ floating-point value (IS_DP == 1). The expanded value is returned. */
+
+static uint64_t
+expand_fp_imm (int is_dp, uint32_t imm8)
+{
+ uint64_t imm;
+ uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
+
+ imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
+ imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
+ imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
+ imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
+ | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
+ if (is_dp)
+ {
+ imm = (imm8_7 << (63-32)) /* imm8<7> */
+ | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
+ | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
+ | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
+ | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
+ imm <<= 32;
+ }
+ else
+ {
+ imm = (imm8_7 << 31) /* imm8<7> */
+ | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
+ | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
+ | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
+ }
+
+ return imm;
+}
+
+/* Produce the string representation of the register list operand *OPND
+ in the buffer pointed by BUF of size SIZE. */
+static void
+print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd)
+{
+ const int num_regs = opnd->reglist.num_regs;
+ const int first_reg = opnd->reglist.first_regno;
+ const int last_reg = (first_reg + num_regs - 1) & 0x1f;
+ const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
+ char tb[8]; /* Temporary buffer. */
+
+ assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
+ assert (num_regs >= 1 && num_regs <= 4);
+
+ /* Prepare the index if any. */
+ if (opnd->reglist.has_index)
+ snprintf (tb, 8, "[%d]", opnd->reglist.index);
+ else
+ tb[0] = '\0';
+
+ /* The hyphenated form is preferred for disassembly if there are
+ more than two registers in the list, and the register numbers
+ are monotonically increasing in increments of one. */
+ if (num_regs > 2 && last_reg > first_reg)
+ snprintf (buf, size, "{v%d.%s-v%d.%s}%s", first_reg, qlf_name,
+ last_reg, qlf_name, tb);
+ else
+ {
+ const int reg0 = first_reg;
+ const int reg1 = (first_reg + 1) & 0x1f;
+ const int reg2 = (first_reg + 2) & 0x1f;
+ const int reg3 = (first_reg + 3) & 0x1f;
+
+ switch (num_regs)
+ {
+ case 1:
+ snprintf (buf, size, "{v%d.%s}%s", reg0, qlf_name, tb);
+ break;
+ case 2:
+ snprintf (buf, size, "{v%d.%s, v%d.%s}%s", reg0, qlf_name,
+ reg1, qlf_name, tb);
+ break;
+ case 3:
+ snprintf (buf, size, "{v%d.%s, v%d.%s, v%d.%s}%s", reg0, qlf_name,
+ reg1, qlf_name, reg2, qlf_name, tb);
+ break;
+ case 4:
+ snprintf (buf, size, "{v%d.%s, v%d.%s, v%d.%s, v%d.%s}%s",
+ reg0, qlf_name, reg1, qlf_name, reg2, qlf_name,
+ reg3, qlf_name, tb);
+ break;
+ }
+ }
+}
+
+/* Produce the string representation of the register offset address operand
+ *OPND in the buffer pointed by BUF of size SIZE. */
+static void
+print_register_offset_address (char *buf, size_t size,
+ const aarch64_opnd_info *opnd)
+{
+ const size_t tblen = 16;
+ char tb[tblen]; /* Temporary buffer. */
+ bfd_boolean lsl_p = FALSE; /* Is LSL shift operator? */
+ bfd_boolean wm_p = FALSE; /* Should Rm be Wm? */
+ bfd_boolean print_extend_p = TRUE;
+ bfd_boolean print_amount_p = TRUE;
+ const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
+
+ switch (opnd->shifter.kind)
+ {
+ case AARCH64_MOD_UXTW: wm_p = TRUE; break;
+ case AARCH64_MOD_LSL : lsl_p = TRUE; break;
+ case AARCH64_MOD_SXTW: wm_p = TRUE; break;
+ case AARCH64_MOD_SXTX: break;
+ default: assert (0);
+ }
+
+ if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
+ || !opnd->shifter.amount_present))
+ {
+ /* Not print the shift/extend amount when the amount is zero and
+ when it is not the special case of 8-bit load/store instruction. */
+ print_amount_p = FALSE;
+ /* Likewise, no need to print the shift operator LSL in such a
+ situation. */
+ if (lsl_p)
+ print_extend_p = FALSE;
+ }
+
+ /* Prepare for the extend/shift. */
+ if (print_extend_p)
+ {
+ if (print_amount_p)
+ snprintf (tb, tblen, ",%s #%d", shift_name, opnd->shifter.amount);
+ else
+ snprintf (tb, tblen, ",%s", shift_name);
+ }
+ else
+ tb[0] = '\0';
+
+ snprintf (buf, size, "[%s,%c%d%s]",
+ get_64bit_int_reg_name (opnd->addr.base_regno, 1),
+ wm_p ? 'w' : 'x', opnd->addr.offset.regno, tb);
+}
+
+/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
+ in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
+ PC, PCREL_P and ADDRESS are used to pass in and return information about
+ the PC-relative address calculation, where the PC value is passed in
+ PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
+ will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
+ calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
+
+ The function serves both the disassembler and the assembler diagnostics
+ issuer, which is the reason why it lives in this file. */
+
+void
+aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
+ const aarch64_opcode *opcode,
+ const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
+ bfd_vma *address)
+{
+ int i;
+ const char *name = NULL;
+ const aarch64_opnd_info *opnd = opnds + idx;
+ enum aarch64_modifier_kind kind;
+ uint64_t addr;
+
+ buf[0] = '\0';
+ if (pcrel_p)
+ *pcrel_p = 0;
+
+ switch (opnd->type)
+ {
+ case AARCH64_OPND_Rd:
+ case AARCH64_OPND_Rn:
+ case AARCH64_OPND_Rm:
+ case AARCH64_OPND_Rt:
+ case AARCH64_OPND_Rt2:
+ case AARCH64_OPND_Rs:
+ case AARCH64_OPND_Ra:
+ case AARCH64_OPND_Rt_SYS:
+ /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
+ the <ic_op>, therefore we we use opnd->present to override the
+ generic optional-ness information. */
+ if (opnd->type == AARCH64_OPND_Rt_SYS && !opnd->present)
+ break;
+ /* Omit the operand, e.g. RET. */
+ if (optional_operand_p (opcode, idx)
+ && opnd->reg.regno == get_optional_operand_default_value (opcode))
+ break;
+ assert (opnd->qualifier == AARCH64_OPND_QLF_W
+ || opnd->qualifier == AARCH64_OPND_QLF_X);
+ snprintf (buf, size, "%s",
+ get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
+ break;
+
+ case AARCH64_OPND_Rd_SP:
+ case AARCH64_OPND_Rn_SP:
+ assert (opnd->qualifier == AARCH64_OPND_QLF_W
+ || opnd->qualifier == AARCH64_OPND_QLF_WSP
+ || opnd->qualifier == AARCH64_OPND_QLF_X
+ || opnd->qualifier == AARCH64_OPND_QLF_SP);
+ snprintf (buf, size, "%s",
+ get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
+ break;
+
+ case AARCH64_OPND_Rm_EXT:
+ kind = opnd->shifter.kind;
+ assert (idx == 1 || idx == 2);
+ if ((aarch64_stack_pointer_p (opnds)
+ || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
+ && ((opnd->qualifier == AARCH64_OPND_QLF_W
+ && opnds[0].qualifier == AARCH64_OPND_QLF_W
+ && kind == AARCH64_MOD_UXTW)
+ || (opnd->qualifier == AARCH64_OPND_QLF_X
+ && kind == AARCH64_MOD_UXTX)))
+ {
+ /* 'LSL' is the preferred form in this case. */
+ kind = AARCH64_MOD_LSL;
+ if (opnd->shifter.amount == 0)
+ {
+ /* Shifter omitted. */
+ snprintf (buf, size, "%s",
+ get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
+ break;
+ }
+ }
+ if (opnd->shifter.amount)
+ snprintf (buf, size, "%s, %s #%d",
+ get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
+ aarch64_operand_modifiers[kind].name,
+ opnd->shifter.amount);
+ else
+ snprintf (buf, size, "%s, %s",
+ get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
+ aarch64_operand_modifiers[kind].name);
+ break;
+
+ case AARCH64_OPND_Rm_SFT:
+ assert (opnd->qualifier == AARCH64_OPND_QLF_W
+ || opnd->qualifier == AARCH64_OPND_QLF_X);
+ if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
+ snprintf (buf, size, "%s",
+ get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
+ else
+ snprintf (buf, size, "%s, %s #%d",
+ get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
+ aarch64_operand_modifiers[opnd->shifter.kind].name,
+ opnd->shifter.amount);
+ break;
+
+ case AARCH64_OPND_Fd:
+ case AARCH64_OPND_Fn:
+ case AARCH64_OPND_Fm:
+ case AARCH64_OPND_Fa:
+ case AARCH64_OPND_Ft:
+ case AARCH64_OPND_Ft2:
+ case AARCH64_OPND_Sd:
+ case AARCH64_OPND_Sn:
+ case AARCH64_OPND_Sm:
+ snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
+ opnd->reg.regno);
+ break;
+
+ case AARCH64_OPND_Vd:
+ case AARCH64_OPND_Vn:
+ case AARCH64_OPND_Vm:
+ snprintf (buf, size, "v%d.%s", opnd->reg.regno,
+ aarch64_get_qualifier_name (opnd->qualifier));
+ break;
+
+ case AARCH64_OPND_Ed:
+ case AARCH64_OPND_En:
+ case AARCH64_OPND_Em:
+ snprintf (buf, size, "v%d.%s[%d]", opnd->reglane.regno,
+ aarch64_get_qualifier_name (opnd->qualifier),
+ opnd->reglane.index);
+ break;
+
+ case AARCH64_OPND_VdD1:
+ case AARCH64_OPND_VnD1:
+ snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
+ break;
+
+ case AARCH64_OPND_LVn:
+ case AARCH64_OPND_LVt:
+ case AARCH64_OPND_LVt_AL:
+ case AARCH64_OPND_LEt:
+ print_register_list (buf, size, opnd);
+ break;
+
+ case AARCH64_OPND_Cn:
+ case AARCH64_OPND_Cm:
+ snprintf (buf, size, "C%d", opnd->reg.regno);
+ break;
+
+ case AARCH64_OPND_IDX:
+ case AARCH64_OPND_IMM:
+ case AARCH64_OPND_WIDTH:
+ case AARCH64_OPND_UIMM3_OP1:
+ case AARCH64_OPND_UIMM3_OP2:
+ case AARCH64_OPND_BIT_NUM:
+ case AARCH64_OPND_IMM_VLSL:
+ case AARCH64_OPND_IMM_VLSR:
+ case AARCH64_OPND_SHLL_IMM:
+ case AARCH64_OPND_IMM0:
+ case AARCH64_OPND_IMMR:
+ case AARCH64_OPND_IMMS:
+ case AARCH64_OPND_FBITS:
+ case AARCH64_OPND_IMM_MOV:
+ snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
+ break;
+
+ case AARCH64_OPND_FPIMM0:
+ snprintf (buf, size, "#0.0");
+ break;
+
+ case AARCH64_OPND_LIMM:
+ case AARCH64_OPND_AIMM:
+ case AARCH64_OPND_HALF:
+ if (opnd->shifter.amount)
+ snprintf (buf, size, "#0x%" PRIx64 ", lsl #%d", opnd->imm.value,
+ opnd->shifter.amount);
+ else
+ snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
+ break;
+
+ case AARCH64_OPND_SIMD_IMM:
+ case AARCH64_OPND_SIMD_IMM_SFT:
+ if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
+ || opnd->shifter.kind == AARCH64_MOD_NONE)
+ snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
+ else
+ snprintf (buf, size, "#0x%" PRIx64 ", %s #%d", opnd->imm.value,
+ aarch64_operand_modifiers[opnd->shifter.kind].name,
+ opnd->shifter.amount);
+ break;
+
+ case AARCH64_OPND_FPIMM:
+ case AARCH64_OPND_SIMD_FPIMM:
+ switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
+ {
+ case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
+ {
+ single_conv_t c;
+ c.i = expand_fp_imm (0, opnd->imm.value);
+ snprintf (buf, size, "#%.18e", c.f);
+ }
+ break;
+ case 8: /* e.g. FMOV <Sd>, #<imm>. */
+ {
+ double_conv_t c;
+ c.i = expand_fp_imm (1, opnd->imm.value);
+ snprintf (buf, size, "#%.18e", c.d);
+ }
+ break;
+ default: assert (0);
+ }
+ break;
+
+ case AARCH64_OPND_CCMP_IMM:
+ case AARCH64_OPND_NZCV:
+ case AARCH64_OPND_EXCEPTION:
+ case AARCH64_OPND_UIMM4:
+ case AARCH64_OPND_UIMM7:
+ if (optional_operand_p (opcode, idx) == TRUE
+ && (opnd->imm.value ==
+ (int64_t) get_optional_operand_default_value (opcode)))
+ /* Omit the operand, e.g. DCPS1. */
+ break;
+ snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
+ break;
+
+ case AARCH64_OPND_COND:
+ snprintf (buf, size, "%s", opnd->cond->names[0]);
+ break;
+
+ case AARCH64_OPND_ADDR_ADRP:
+ addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
+ + opnd->imm.value;
+ if (pcrel_p)
+ *pcrel_p = 1;
+ if (address)
+ *address = addr;
+ /* This is not necessary during the disassembling, as print_address_func
+ in the disassemble_info will take care of the printing. But some
+ other callers may be still interested in getting the string in *STR,
+ so here we do snprintf regardless. */
+ snprintf (buf, size, "#0x%" PRIx64, addr);
+ break;
+
+ case AARCH64_OPND_ADDR_PCREL14:
+ case AARCH64_OPND_ADDR_PCREL19:
+ case AARCH64_OPND_ADDR_PCREL21:
+ case AARCH64_OPND_ADDR_PCREL26:
+ addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
+ if (pcrel_p)
+ *pcrel_p = 1;
+ if (address)
+ *address = addr;
+ /* This is not necessary during the disassembling, as print_address_func
+ in the disassemble_info will take care of the printing. But some
+ other callers may be still interested in getting the string in *STR,
+ so here we do snprintf regardless. */
+ snprintf (buf, size, "#0x%" PRIx64, addr);
+ break;
+
+ case AARCH64_OPND_ADDR_SIMPLE:
+ case AARCH64_OPND_SIMD_ADDR_SIMPLE:
+ case AARCH64_OPND_SIMD_ADDR_POST:
+ name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
+ if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
+ {
+ if (opnd->addr.offset.is_reg)
+ snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
+ else
+ snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
+ }
+ else
+ snprintf (buf, size, "[%s]", name);
+ break;
+
+ case AARCH64_OPND_ADDR_REGOFF:
+ print_register_offset_address (buf, size, opnd);
+ break;
+
+ case AARCH64_OPND_ADDR_SIMM7:
+ case AARCH64_OPND_ADDR_SIMM9:
+ case AARCH64_OPND_ADDR_SIMM9_2:
+ name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
+ if (opnd->addr.writeback)
+ {
+ if (opnd->addr.preind)
+ snprintf (buf, size, "[%s,#%d]!", name, opnd->addr.offset.imm);
+ else
+ snprintf (buf, size, "[%s],#%d", name, opnd->addr.offset.imm);
+ }
+ else
+ {
+ if (opnd->addr.offset.imm)
+ snprintf (buf, size, "[%s,#%d]", name, opnd->addr.offset.imm);
+ else
+ snprintf (buf, size, "[%s]", name);
+ }
+ break;
+
+ case AARCH64_OPND_ADDR_UIMM12:
+ name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
+ if (opnd->addr.offset.imm)
+ snprintf (buf, size, "[%s,#%d]", name, opnd->addr.offset.imm);
+ else
+ snprintf (buf, size, "[%s]", name);
+ break;
+
+ case AARCH64_OPND_SYSREG:
+ for (i = 0; aarch64_sys_regs[i].name; ++i)
+ if (aarch64_sys_regs[i].value == opnd->sysreg)
+ break;
+ if (aarch64_sys_regs[i].name)
+ snprintf (buf, size, "%s", aarch64_sys_regs[i].name);
+ else
+ {
+ /* Implementation defined system register. */
+ unsigned int value = opnd->sysreg;
+ snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
+ (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
+ value & 0x7);
+ }
+ break;
+
+ case AARCH64_OPND_PSTATEFIELD:
+ for (i = 0; aarch64_pstatefields[i].name; ++i)
+ if (aarch64_pstatefields[i].value == opnd->pstatefield)
+ break;
+ assert (aarch64_pstatefields[i].name);
+ snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
+ break;
+
+ case AARCH64_OPND_SYSREG_AT:
+ case AARCH64_OPND_SYSREG_DC:
+ case AARCH64_OPND_SYSREG_IC:
+ case AARCH64_OPND_SYSREG_TLBI:
+ snprintf (buf, size, "%s", opnd->sysins_op->template);
+ break;
+
+ case AARCH64_OPND_BARRIER:
+ snprintf (buf, size, "%s", opnd->barrier->name);
+ break;
+
+ case AARCH64_OPND_BARRIER_ISB:
+ /* Operand can be omitted, e.g. in DCPS1. */
+ if (! optional_operand_p (opcode, idx)
+ || (opnd->barrier->value
+ != get_optional_operand_default_value (opcode)))
+ snprintf (buf, size, "#0x%x", opnd->barrier->value);
+ break;
+
+ case AARCH64_OPND_PRFOP:
+ snprintf (buf, size, "%s", opnd->prfop->name);
+ break;
+
+ default:
+ assert (0);
+ }
+}
+\f
+#define CPENC(op0,op1,crn,crm,op2) \
+ ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
+ /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
+#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
+ /* for 3.9.10 System Instructions */
+#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
+
+#define C0 0
+#define C1 1
+#define C2 2
+#define C3 3
+#define C4 4
+#define C5 5
+#define C6 6
+#define C7 7
+#define C8 8
+#define C9 9
+#define C10 10
+#define C11 11
+#define C12 12
+#define C13 13
+#define C14 14
+#define C15 15
+
+/* TODO there are two more issues need to be resolved
+ 1. handle read-only and write-only system registers
+ 2. handle cpu-implementation-defined system registers. */
+const struct aarch64_name_value_pair aarch64_sys_regs [] =
+{
+ { "spsr_el1", CPEN_(0,C0,0) }, /* = spsr_svc */
+ { "elr_el1", CPEN_(0,C0,1) },
+ { "sp_el0", CPEN_(0,C1,0) },
+ { "spsel", CPEN_(0,C2,0) },
+ { "daif", CPEN_(3,C2,1) },
+ { "currentel", CPEN_(0,C2,2) }, /* RO */
+ { "nzcv", CPEN_(3,C2,0) },
+ { "fpcr", CPEN_(3,C4,0) },
+ { "fpsr", CPEN_(3,C4,1) },
+ { "dspsr_el0", CPEN_(3,C5,0) },
+ { "dlr_el0", CPEN_(3,C5,1) },
+ { "spsr_el2", CPEN_(4,C0,0) }, /* = spsr_hyp */
+ { "elr_el2", CPEN_(4,C0,1) },
+ { "sp_el1", CPEN_(4,C1,0) },
+ { "spsr_irq", CPEN_(4,C3,0) },
+ { "spsr_abt", CPEN_(4,C3,1) },
+ { "spsr_und", CPEN_(4,C3,2) },
+ { "spsr_fiq", CPEN_(4,C3,3) },
+ { "spsr_el3", CPEN_(6,C0,0) },
+ { "elr_el3", CPEN_(6,C0,1) },
+ { "sp_el2", CPEN_(6,C1,0) },
+ { "spsr_svc", CPEN_(0,C0,0) }, /* = spsr_el1 */
+ { "spsr_hyp", CPEN_(4,C0,0) }, /* = spsr_el2 */
+ { "midr_el1", CPENC(3,0,C0,C0,0) }, /* RO */
+ { "ctr_el0", CPENC(3,3,C0,C0,1) }, /* RO */
+ { "mpidr_el1", CPENC(3,0,C0,C0,5) }, /* RO */
+ { "revidr_el1", CPENC(3,0,C0,C0,6) }, /* RO */
+ { "aidr_el1", CPENC(3,1,C0,C0,7) }, /* RO */
+ { "dczid_el0", CPENC(3,3,C0,C0,7) }, /* RO */
+ { "id_dfr0_el1", CPENC(3,0,C0,C1,2) }, /* RO */
+ { "id_pfr0_el1", CPENC(3,0,C0,C1,0) }, /* RO */
+ { "id_pfr1_el1", CPENC(3,0,C0,C1,1) }, /* RO */
+ { "id_afr0_el1", CPENC(3,0,C0,C1,3) }, /* RO */
+ { "id_mmfr0_el1", CPENC(3,0,C0,C1,4) }, /* RO */
+ { "id_mmfr1_el1", CPENC(3,0,C0,C1,5) }, /* RO */
+ { "id_mmfr2_el1", CPENC(3,0,C0,C1,6) }, /* RO */
+ { "id_mmfr3_el1", CPENC(3,0,C0,C1,7) }, /* RO */
+ { "id_isar0_el1", CPENC(3,0,C0,C2,0) }, /* RO */
+ { "id_isar1_el1", CPENC(3,0,C0,C2,1) }, /* RO */
+ { "id_isar2_el1", CPENC(3,0,C0,C2,2) }, /* RO */
+ { "id_isar3_el1", CPENC(3,0,C0,C2,3) }, /* RO */
+ { "id_isar4_el1", CPENC(3,0,C0,C2,4) }, /* RO */
+ { "id_isar5_el1", CPENC(3,0,C0,C2,5) }, /* RO */
+ { "mvfr0_el1", CPENC(3,0,C0,C3,0) }, /* RO */
+ { "mvfr1_el1", CPENC(3,0,C0,C3,1) }, /* RO */
+ { "mvfr2_el1", CPENC(3,0,C0,C3,2) }, /* RO */
+ { "ccsidr_el1", CPENC(3,1,C0,C0,0) }, /* RO */
+ { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0) }, /* RO */
+ { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1) }, /* RO */
+ { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0) }, /* RO */
+ { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1) }, /* RO */
+ { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0) }, /* RO */
+ { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1) }, /* RO */
+ { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0) }, /* RO */
+ { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1) }, /* RO */
+ { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4) }, /* RO */
+ { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5) }, /* RO */
+ { "clidr_el1", CPENC(3,1,C0,C0,1) }, /* RO */
+ { "csselr_el1", CPENC(3,2,C0,C0,0) }, /* RO */
+ { "vpidr_el2", CPENC(3,4,C0,C0,0) },
+ { "vmpidr_el2", CPENC(3,4,C0,C0,5) },
+ { "sctlr_el1", CPENC(3,0,C1,C0,0) },
+ { "sctlr_el2", CPENC(3,4,C1,C0,0) },
+ { "sctlr_el3", CPENC(3,6,C1,C0,0) },
+ { "actlr_el1", CPENC(3,0,C1,C0,1) },
+ { "actlr_el2", CPENC(3,4,C1,C0,1) },
+ { "actlr_el3", CPENC(3,6,C1,C0,1) },
+ { "cpacr_el1", CPENC(3,0,C1,C0,2) },
+ { "cptr_el2", CPENC(3,4,C1,C1,2) },
+ { "cptr_el3", CPENC(3,6,C1,C1,2) },
+ { "scr_el3", CPENC(3,6,C1,C1,0) },
+ { "hcr_el2", CPENC(3,4,C1,C1,0) },
+ { "mdcr_el2", CPENC(3,4,C1,C1,1) },
+ { "mdcr_el3", CPENC(3,6,C1,C3,1) },
+ { "hstr_el2", CPENC(3,4,C1,C1,3) },
+ { "hacr_el2", CPENC(3,4,C1,C1,7) },
+ { "ttbr0_el1", CPENC(3,0,C2,C0,0) },
+ { "ttbr1_el1", CPENC(3,0,C2,C0,1) },
+ { "ttbr0_el2", CPENC(3,4,C2,C0,0) },
+ { "ttbr0_el3", CPENC(3,6,C2,C0,0) },
+ { "vttbr_el2", CPENC(3,4,C2,C1,0) },
+ { "tcr_el1", CPENC(3,0,C2,C0,2) },
+ { "tcr_el2", CPENC(3,4,C2,C0,2) },
+ { "tcr_el3", CPENC(3,6,C2,C0,2) },
+ { "vtcr_el2", CPENC(3,4,C2,C1,2) },
+ { "afsr0_el1", CPENC(3,0,C5,C1,0) },
+ { "afsr1_el1", CPENC(3,0,C5,C1,1) },
+ { "afsr0_el2", CPENC(3,4,C5,C1,0) },
+ { "afsr1_el2", CPENC(3,4,C5,C1,1) },
+ { "afsr0_el3", CPENC(3,6,C5,C1,0) },
+ { "afsr1_el3", CPENC(3,6,C5,C1,1) },
+ { "esr_el1", CPENC(3,0,C5,C2,0) },
+ { "esr_el2", CPENC(3,4,C5,C2,0) },
+ { "esr_el3", CPENC(3,6,C5,C2,0) },
+ { "fpexc32_el2", CPENC(3,4,C5,C3,0) },
+ { "far_el1", CPENC(3,0,C6,C0,0) },
+ { "far_el2", CPENC(3,4,C6,C0,0) },
+ { "far_el3", CPENC(3,6,C6,C0,0) },
+ { "hpfar_el2", CPENC(3,4,C6,C0,4) },
+ { "par_el1", CPENC(3,0,C7,C4,0) },
+ { "mair_el1", CPENC(3,0,C10,C2,0) },
+ { "mair_el2", CPENC(3,4,C10,C2,0) },
+ { "mair_el3", CPENC(3,6,C10,C2,0) },
+ { "amair_el1", CPENC(3,0,C10,C3,0) },
+ { "amair_el2", CPENC(3,4,C10,C3,0) },
+ { "amair_el3", CPENC(3,6,C10,C3,0) },
+ { "vbar_el1", CPENC(3,0,C12,C0,0) },
+ { "vbar_el2", CPENC(3,4,C12,C0,0) },
+ { "vbar_el3", CPENC(3,6,C12,C0,0) },
+ { "rvbar_el1", CPENC(3,0,C12,C0,1) }, /* RO */
+ { "rvbar_el2", CPENC(3,4,C12,C0,1) }, /* RO */
+ { "rvbar_el3", CPENC(3,6,C12,C0,1) }, /* RO */
+ { "isr_el1", CPENC(3,0,C12,C1,0) }, /* RO */
+ { "contextidr_el1", CPENC(3,0,C13,C0,1) },
+ { "tpidr_el0", CPENC(3,3,C13,C0,2) },
+ { "tpidrro_el0", CPENC(3,3,C13,C0,3) }, /* RO */
+ { "tpidr_el1", CPENC(3,0,C13,C0,4) },
+ { "tpidr_el2", CPENC(3,4,C13,C0,2) },
+ { "tpidr_el3", CPENC(3,6,C13,C0,2) },
+ { "teecr32_el1", CPENC(2,2,C0, C0,0) }, /* See section 3.9.7.1 */
+ { "cntfrq_el0", CPENC(3,3,C14,C0,0) }, /* RO */
+ { "cntpct_el0", CPENC(3,3,C14,C0,1) }, /* RO */
+ { "cntvct_el0", CPENC(3,3,C14,C0,2) }, /* RO */
+ { "cntvoff_el2", CPENC(3,4,C14,C0,3) },
+ { "cntkctl_el1", CPENC(3,0,C14,C1,0) },
+ { "cnthctl_el2", CPENC(3,4,C14,C1,0) },
+ { "cntp_tval_el0", CPENC(3,3,C14,C2,0) },
+ { "cntp_ctl_el0", CPENC(3,3,C14,C2,1) },
+ { "cntp_cval_el0", CPENC(3,3,C14,C2,2) },
+ { "cntv_tval_el0", CPENC(3,3,C14,C3,0) },
+ { "cntv_ctl_el0", CPENC(3,3,C14,C3,1) },
+ { "cntv_cval_el0", CPENC(3,3,C14,C3,2) },
+ { "cnthp_tval_el2", CPENC(3,4,C14,C2,0) },
+ { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1) },
+ { "cnthp_cval_el2", CPENC(3,4,C14,C2,2) },
+ { "cntps_tval_el1", CPENC(3,7,C14,C2,0) },
+ { "cntps_ctl_el1", CPENC(3,7,C14,C2,1) },
+ { "cntps_cval_el1", CPENC(3,7,C14,C2,2) },
+ { "dacr32_el2", CPENC(3,4,C3,C0,0) },
+ { "ifsr32_el2", CPENC(3,4,C5,C0,1) },
+ { "teehbr32_el1", CPENC(2,2,C1,C0,0) },
+ { "sder32_el3", CPENC(3,6,C1,C1,1) },
+ { "mdscr_el1", CPENC(2,0,C0, C2, 2) },
+ { "mdccsr_el0", CPENC(2,3,C0, C1, 0) }, /* r */
+ { "mdccint_el1", CPENC(2,0,C0, C2, 0) },
+ { "dbgdtr_el0", CPENC(2,3,C0, C4, 0) },
+ { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0) }, /* r */
+ { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0) }, /* w */
+ { "osdtrrx_el1", CPENC(2,0,C0, C0, 2) }, /* r */
+ { "osdtrtx_el1", CPENC(2,0,C0, C3, 2) }, /* w */
+ { "oseccr_el1", CPENC(2,0,C0, C6, 2) },
+ { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0) },
+ { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4) },
+ { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4) },
+ { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4) },
+ { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4) },
+ { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4) },
+ { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4) },
+ { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4) },
+ { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4) },
+ { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4) },
+ { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4) },
+ { "dbgbvr10_el1", CPENC(2,0,C0, C10,4) },
+ { "dbgbvr11_el1", CPENC(2,0,C0, C11,4) },
+ { "dbgbvr12_el1", CPENC(2,0,C0, C12,4) },
+ { "dbgbvr13_el1", CPENC(2,0,C0, C13,4) },
+ { "dbgbvr14_el1", CPENC(2,0,C0, C14,4) },
+ { "dbgbvr15_el1", CPENC(2,0,C0, C15,4) },
+ { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5) },
+ { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5) },
+ { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5) },
+ { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5) },
+ { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5) },
+ { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5) },
+ { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5) },
+ { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5) },
+ { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5) },
+ { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5) },
+ { "dbgbcr10_el1", CPENC(2,0,C0, C10,5) },
+ { "dbgbcr11_el1", CPENC(2,0,C0, C11,5) },
+ { "dbgbcr12_el1", CPENC(2,0,C0, C12,5) },
+ { "dbgbcr13_el1", CPENC(2,0,C0, C13,5) },
+ { "dbgbcr14_el1", CPENC(2,0,C0, C14,5) },
+ { "dbgbcr15_el1", CPENC(2,0,C0, C15,5) },
+ { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6) },
+ { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6) },
+ { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6) },
+ { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6) },
+ { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6) },
+ { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6) },
+ { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6) },
+ { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6) },
+ { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6) },
+ { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6) },
+ { "dbgwvr10_el1", CPENC(2,0,C0, C10,6) },
+ { "dbgwvr11_el1", CPENC(2,0,C0, C11,6) },
+ { "dbgwvr12_el1", CPENC(2,0,C0, C12,6) },
+ { "dbgwvr13_el1", CPENC(2,0,C0, C13,6) },
+ { "dbgwvr14_el1", CPENC(2,0,C0, C14,6) },
+ { "dbgwvr15_el1", CPENC(2,0,C0, C15,6) },
+ { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7) },
+ { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7) },
+ { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7) },
+ { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7) },
+ { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7) },
+ { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7) },
+ { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7) },
+ { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7) },
+ { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7) },
+ { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7) },
+ { "dbgwcr10_el1", CPENC(2,0,C0, C10,7) },
+ { "dbgwcr11_el1", CPENC(2,0,C0, C11,7) },
+ { "dbgwcr12_el1", CPENC(2,0,C0, C12,7) },
+ { "dbgwcr13_el1", CPENC(2,0,C0, C13,7) },
+ { "dbgwcr14_el1", CPENC(2,0,C0, C14,7) },
+ { "dbgwcr15_el1", CPENC(2,0,C0, C15,7) },
+ { "mdrar_el1", CPENC(2,0,C1, C0, 0) }, /* r */
+ { "oslar_el1", CPENC(2,0,C1, C0, 4) }, /* w */
+ { "oslsr_el1", CPENC(2,0,C1, C1, 4) }, /* r */
+ { "osdlr_el1", CPENC(2,0,C1, C3, 4) },
+ { "dbgprcr_el1", CPENC(2,0,C1, C4, 4) },
+ { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6) },
+ { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6) },
+ { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6) }, /* r */
+
+ { "pmcr_el0", CPENC(3,3,C9,C12, 0) },
+ { "pmcntenset_el0", CPENC(3,3,C9,C12, 1) },
+ { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2) },
+ { "pmovsclr_el0", CPENC(3,3,C9,C12, 3) },
+ { "pmswinc_el0", CPENC(3,3,C9,C12, 4) }, /* w */
+ { "pmselr_el0", CPENC(3,3,C9,C12, 5) },
+ { "pmceid0_el0", CPENC(3,3,C9,C12, 6) }, /* r */
+ { "pmceid1_el0", CPENC(3,3,C9,C12, 7) }, /* r */
+ { "pmccntr_el0", CPENC(3,3,C9,C13, 0) },
+ { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1) },
+ { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2) },
+ { "pmuserenr_el0", CPENC(3,3,C9,C14, 0) },
+ { "pmintenset_el1", CPENC(3,0,C9,C14, 1) },
+ { "pmintenclr_el1", CPENC(3,0,C9,C14, 2) },
+ { "pmovsset_el0", CPENC(3,3,C9,C14, 3) },
+ { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0) },
+ { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1) },
+ { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2) },
+ { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3) },
+ { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4) },
+ { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5) },
+ { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6) },
+ { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7) },
+ { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0) },
+ { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1) },
+ { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2) },
+ { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3) },
+ { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4) },
+ { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5) },
+ { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6) },
+ { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7) },
+ { "pmevcntr16_el0", CPENC(3,3,C14,C10,0) },
+ { "pmevcntr17_el0", CPENC(3,3,C14,C10,1) },
+ { "pmevcntr18_el0", CPENC(3,3,C14,C10,2) },
+ { "pmevcntr19_el0", CPENC(3,3,C14,C10,3) },
+ { "pmevcntr20_el0", CPENC(3,3,C14,C10,4) },
+ { "pmevcntr21_el0", CPENC(3,3,C14,C10,5) },
+ { "pmevcntr22_el0", CPENC(3,3,C14,C10,6) },
+ { "pmevcntr23_el0", CPENC(3,3,C14,C10,7) },
+ { "pmevcntr24_el0", CPENC(3,3,C14,C11,0) },
+ { "pmevcntr25_el0", CPENC(3,3,C14,C11,1) },
+ { "pmevcntr26_el0", CPENC(3,3,C14,C11,2) },
+ { "pmevcntr27_el0", CPENC(3,3,C14,C11,3) },
+ { "pmevcntr28_el0", CPENC(3,3,C14,C11,4) },
+ { "pmevcntr29_el0", CPENC(3,3,C14,C11,5) },
+ { "pmevcntr30_el0", CPENC(3,3,C14,C11,6) },
+ { "pmevtyper0_el0", CPENC(3,3,C14,C12,0) },
+ { "pmevtyper1_el0", CPENC(3,3,C14,C12,1) },
+ { "pmevtyper2_el0", CPENC(3,3,C14,C12,2) },
+ { "pmevtyper3_el0", CPENC(3,3,C14,C12,3) },
+ { "pmevtyper4_el0", CPENC(3,3,C14,C12,4) },
+ { "pmevtyper5_el0", CPENC(3,3,C14,C12,5) },
+ { "pmevtyper6_el0", CPENC(3,3,C14,C12,6) },
+ { "pmevtyper7_el0", CPENC(3,3,C14,C12,7) },
+ { "pmevtyper8_el0", CPENC(3,3,C14,C13,0) },
+ { "pmevtyper9_el0", CPENC(3,3,C14,C13,1) },
+ { "pmevtyper10_el0", CPENC(3,3,C14,C13,2) },
+ { "pmevtyper11_el0", CPENC(3,3,C14,C13,3) },
+ { "pmevtyper12_el0", CPENC(3,3,C14,C13,4) },
+ { "pmevtyper13_el0", CPENC(3,3,C14,C13,5) },
+ { "pmevtyper14_el0", CPENC(3,3,C14,C13,6) },
+ { "pmevtyper15_el0", CPENC(3,3,C14,C13,7) },
+ { "pmevtyper16_el0", CPENC(3,3,C14,C14,0) },
+ { "pmevtyper17_el0", CPENC(3,3,C14,C14,1) },
+ { "pmevtyper18_el0", CPENC(3,3,C14,C14,2) },
+ { "pmevtyper19_el0", CPENC(3,3,C14,C14,3) },
+ { "pmevtyper20_el0", CPENC(3,3,C14,C14,4) },
+ { "pmevtyper21_el0", CPENC(3,3,C14,C14,5) },
+ { "pmevtyper22_el0", CPENC(3,3,C14,C14,6) },
+ { "pmevtyper23_el0", CPENC(3,3,C14,C14,7) },
+ { "pmevtyper24_el0", CPENC(3,3,C14,C15,0) },
+ { "pmevtyper25_el0", CPENC(3,3,C14,C15,1) },
+ { "pmevtyper26_el0", CPENC(3,3,C14,C15,2) },
+ { "pmevtyper27_el0", CPENC(3,3,C14,C15,3) },
+ { "pmevtyper28_el0", CPENC(3,3,C14,C15,4) },
+ { "pmevtyper29_el0", CPENC(3,3,C14,C15,5) },
+ { "pmevtyper30_el0", CPENC(3,3,C14,C15,6) },
+ { "pmccfiltr_el0", CPENC(3,3,C14,C15,7) },
+
+ { "daifset", CPENC(0,3,C4,C0,6) },
+ { "daifclr", CPENC(0,3,C4,C0,7) },
+
+ { 0, CPENC(0,0,0,0,0) },
+};
+
+const struct aarch64_name_value_pair aarch64_pstatefields [] =
+{
+ { "spsel", 0x05 },
+ { "daifset", 0x1e },
+ { "daifclr", 0x1f },
+ { 0, CPENC(0,0,0,0,0) },
+};
+
+const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
+{
+ { "ialluis", CPENS(0,C7,C1,0), 0 },
+ { "iallu", CPENS(0,C7,C5,0), 0 },
+ { "ivau", CPENS(3,C7,C5,1), 1 },
+ { 0, CPENS(0,0,0,0), 0 }
+};
+
+const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
+{
+ { "zva", CPENS(3,C7,C4,1), 1 },
+ { "ivac", CPENS(0,C7,C6,1), 1 },
+ { "isw", CPENS(0,C7,C6,2), 1 },
+ { "cvac", CPENS(3,C7,C10,1), 1 },
+ { "csw", CPENS(0,C7,C10,2), 1 },
+ { "cvau", CPENS(3,C7,C11,1), 1 },
+ { "civac", CPENS(3,C7,C14,1), 1 },
+ { "cisw", CPENS(0,C7,C14,2), 1 },
+ { 0, CPENS(0,0,0,0), 0 }
+};
+
+const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
+{
+ { "s1e1r", CPENS(0,C7,C8,0), 1 },
+ { "s1e1w", CPENS(0,C7,C8,1), 1 },
+ { "s1e0r", CPENS(0,C7,C8,2), 1 },
+ { "s1e0w", CPENS(0,C7,C8,3), 1 },
+ { "s12e1r", CPENS(4,C7,C8,4), 1 },
+ { "s12e1w", CPENS(4,C7,C8,5), 1 },
+ { "s12e0r", CPENS(4,C7,C8,6), 1 },
+ { "s12e0w", CPENS(4,C7,C8,7), 1 },
+ { "s1e2r", CPENS(4,C7,C8,0), 1 },
+ { "s1e2w", CPENS(4,C7,C8,1), 1 },
+ { "s1e3r", CPENS(6,C7,C8,0), 1 },
+ { "s1e3w", CPENS(6,C7,C8,1), 1 },
+ { 0, CPENS(0,0,0,0), 0 }
+};
+
+const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
+{
+ { "vmalle1", CPENS(0,C8,C7,0), 0 },
+ { "vae1", CPENS(0,C8,C7,1), 1 },
+ { "aside1", CPENS(0,C8,C7,2), 1 },
+ { "vaae1", CPENS(0,C8,C7,3), 1 },
+ { "vmalle1is", CPENS(0,C8,C3,0), 0 },
+ { "vae1is", CPENS(0,C8,C3,1), 1 },
+ { "aside1is", CPENS(0,C8,C3,2), 1 },
+ { "vaae1is", CPENS(0,C8,C3,3), 1 },
+ { "ipas2e1is", CPENS(4,C8,C0,1), 1 },
+ { "ipas2le1is",CPENS(4,C8,C0,5), 1 },
+ { "ipas2e1", CPENS(4,C8,C4,1), 1 },
+ { "ipas2le1", CPENS(4,C8,C4,5), 1 },
+ { "vae2", CPENS(4,C8,C7,1), 1 },
+ { "vae2is", CPENS(4,C8,C3,1), 1 },
+ { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
+ { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
+ { "vae3", CPENS(6,C8,C7,1), 1 },
+ { "vae3is", CPENS(6,C8,C3,1), 1 },
+ { "alle2", CPENS(4,C8,C7,0), 0 },
+ { "alle2is", CPENS(4,C8,C3,0), 0 },
+ { "alle1", CPENS(4,C8,C7,4), 0 },
+ { "alle1is", CPENS(4,C8,C3,4), 0 },
+ { "alle3", CPENS(6,C8,C7,0), 0 },
+ { "alle3is", CPENS(6,C8,C3,0), 0 },
+ { "vale1is", CPENS(0,C8,C3,5), 1 },
+ { "vale2is", CPENS(4,C8,C3,5), 1 },
+ { "vale3is", CPENS(6,C8,C3,5), 1 },
+ { "vaale1is", CPENS(0,C8,C3,7), 1 },
+ { "vale1", CPENS(0,C8,C7,5), 1 },
+ { "vale2", CPENS(4,C8,C7,5), 1 },
+ { "vale3", CPENS(6,C8,C7,5), 1 },
+ { "vaale1", CPENS(0,C8,C7,7), 1 },
+ { 0, CPENS(0,0,0,0), 0 }
+};
+
+#undef C0
+#undef C1
+#undef C2
+#undef C3
+#undef C4
+#undef C5
+#undef C6
+#undef C7
+#undef C8
+#undef C9
+#undef C10
+#undef C11
+#undef C12
+#undef C13
+#undef C14
+#undef C15
+
+/* Include the opcode description table as well as the operand description
+ table. */
+#include "aarch64-tbl.h"
--- /dev/null
+/* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
+ Copyright 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#ifndef OPCODES_AARCH64_OPC_H
+#define OPCODES_AARCH64_OPC_H
+
+#include <string.h>
+#include "opcode/aarch64.h"
+
+/* Instruction fields.
+ Keep synced with fields. */
+enum aarch64_field_kind
+{
+ FLD_NIL,
+ FLD_cond2,
+ FLD_nzcv,
+ FLD_defgh,
+ FLD_abc,
+ FLD_imm19,
+ FLD_immhi,
+ FLD_immlo,
+ FLD_size,
+ FLD_vldst_size,
+ FLD_op,
+ FLD_Q,
+ FLD_Rt,
+ FLD_Rd,
+ FLD_Rn,
+ FLD_Rt2,
+ FLD_Ra,
+ FLD_op2,
+ FLD_CRm,
+ FLD_CRn,
+ FLD_op1,
+ FLD_op0,
+ FLD_imm3,
+ FLD_cond,
+ FLD_opcode,
+ FLD_cmode,
+ FLD_asisdlso_opcode,
+ FLD_len,
+ FLD_Rm,
+ FLD_Rs,
+ FLD_option,
+ FLD_S,
+ FLD_hw,
+ FLD_opc,
+ FLD_opc1,
+ FLD_shift,
+ FLD_type,
+ FLD_ldst_size,
+ FLD_imm6,
+ FLD_imm4,
+ FLD_imm5,
+ FLD_imm7,
+ FLD_imm8,
+ FLD_imm9,
+ FLD_imm12,
+ FLD_imm14,
+ FLD_imm16,
+ FLD_imm26,
+ FLD_imms,
+ FLD_immr,
+ FLD_immb,
+ FLD_immh,
+ FLD_N,
+ FLD_index,
+ FLD_index2,
+ FLD_sf,
+ FLD_H,
+ FLD_L,
+ FLD_M,
+ FLD_b5,
+ FLD_b40,
+ FLD_scale,
+};
+
+/* Field description. */
+struct aarch64_field
+{
+ int lsb;
+ int width;
+};
+
+typedef struct aarch64_field aarch64_field;
+
+extern const aarch64_field fields[];
+\f
+/* Operand description. */
+
+struct aarch64_operand
+{
+ enum aarch64_operand_class op_class;
+
+ /* Name of the operand code; used mainly for the purpose of internal
+ debugging. */
+ const char *name;
+
+ unsigned int flags;
+
+ /* The associated instruction bit-fields; no operand has more than 4
+ bit-fields */
+ enum aarch64_field_kind fields[4];
+
+ /* Brief description */
+ const char *desc;
+};
+
+typedef struct aarch64_operand aarch64_operand;
+
+extern const aarch64_operand aarch64_operands[];
+
+/* Operand flags. */
+
+#define OPD_F_HAS_INSERTER 0x00000001
+#define OPD_F_HAS_EXTRACTOR 0x00000002
+#define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
+#define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
+ value by 2 to get the value
+ of an immediate operand. */
+#define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
+
+static inline bfd_boolean
+operand_has_inserter (const aarch64_operand *operand)
+{
+ return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
+operand_has_extractor (const aarch64_operand *operand)
+{
+ return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
+operand_need_sign_extension (const aarch64_operand *operand)
+{
+ return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
+operand_need_shift_by_two (const aarch64_operand *operand)
+{
+ return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
+operand_maybe_stack_pointer (const aarch64_operand *operand)
+{
+ return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
+}
+
+/* Return the total width of the operand *OPERAND. */
+static inline unsigned
+get_operand_fields_width (const aarch64_operand *operand)
+{
+ int i = 0;
+ unsigned width = 0;
+ while (operand->fields[i] != FLD_NIL)
+ width += fields[operand->fields[i++]].width;
+ assert (width > 0 && width < 32);
+ return width;
+}
+
+static inline const aarch64_operand *
+get_operand_from_code (enum aarch64_opnd code)
+{
+ return aarch64_operands + code;
+}
+\f
+/* Operand qualifier and operand constraint checking. */
+
+int aarch64_match_operands_constraint (aarch64_inst *,
+ aarch64_operand_error *);
+
+/* Operand qualifier related functions. */
+const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
+unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
+aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
+int aarch64_find_best_match (const aarch64_inst *,
+ const aarch64_opnd_qualifier_seq_t *,
+ int, aarch64_opnd_qualifier_t *);
+
+static inline void
+reset_operand_qualifier (aarch64_inst *inst, int idx)
+{
+ assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
+ inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
+}
+\f
+/* Inline functions operating on instruction bit-field(s). */
+
+/* Generate a mask that has WIDTH number of consecutive 1s. */
+
+static inline aarch64_insn
+gen_mask (int width)
+{
+ return ((aarch64_insn) 1 << width) - 1;;
+}
+
+/* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
+static inline int
+gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
+{
+ const aarch64_field *field = &fields[kind];
+ if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
+ return 0;
+ ret->lsb = field->lsb + lsb_rel;
+ ret->width = width;
+ return 1;
+}
+
+/* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
+ of the opcode. */
+
+static inline void
+insert_field_2 (const aarch64_field *field, aarch64_insn *code,
+ aarch64_insn value, aarch64_insn mask)
+{
+ assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
+ && field->lsb + field->width <= 32);
+ value &= gen_mask (field->width);
+ value <<= field->lsb;
+ /* In some opcodes, field can be part of the base opcode, e.g. the size
+ field in FADD. The following helps avoid corrupt the base opcode. */
+ value &= ~mask;
+ *code |= value;
+}
+
+/* Extract FIELD of CODE and return the value. MASK can be zero or the base
+ mask of the opcode. */
+
+static inline aarch64_insn
+extract_field_2 (const aarch64_field *field, aarch64_insn code,
+ aarch64_insn mask)
+{
+ aarch64_insn value;
+ /* Clear any bit that is a part of the base opcode. */
+ code &= ~mask;
+ value = (code >> field->lsb) & gen_mask (field->width);
+ return value;
+}
+
+/* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
+ of the opcode. */
+
+static inline void
+insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
+ aarch64_insn value, aarch64_insn mask)
+{
+ insert_field_2 (&fields[kind], code, value, mask);
+}
+
+/* Extract field KIND of CODE and return the value. MASK can be zero or the
+ base mask of the opcode. */
+
+static inline aarch64_insn
+extract_field (enum aarch64_field_kind kind, aarch64_insn code,
+ aarch64_insn mask)
+{
+ return extract_field_2 (&fields[kind], code, mask);
+}
+\f
+/* Inline functions selecting operand to do the encoding/decoding for a
+ certain instruction bit-field. */
+
+/* Select the operand to do the encoding/decoding of the 'sf' field.
+ The heuristic-based rule is that the result operand is respected more. */
+
+static inline int
+select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
+{
+ int idx = -1;
+ if (aarch64_get_operand_class (opcode->operands[0])
+ == AARCH64_OPND_CLASS_INT_REG)
+ /* normal case. */
+ idx = 0;
+ else if (aarch64_get_operand_class (opcode->operands[1])
+ == AARCH64_OPND_CLASS_INT_REG)
+ /* e.g. float2fix. */
+ idx = 1;
+ else
+ { assert (0); abort (); }
+ return idx;
+}
+
+/* Select the operand to do the encoding/decoding of the 'type' field in
+ the floating-point instructions.
+ The heuristic-based rule is that the source operand is respected more. */
+
+static inline int
+select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
+{
+ int idx;
+ if (aarch64_get_operand_class (opcode->operands[1])
+ == AARCH64_OPND_CLASS_FP_REG)
+ /* normal case. */
+ idx = 1;
+ else if (aarch64_get_operand_class (opcode->operands[0])
+ == AARCH64_OPND_CLASS_FP_REG)
+ /* e.g. float2fix. */
+ idx = 0;
+ else
+ { assert (0); abort (); }
+ return idx;
+}
+
+/* Select the operand to do the encoding/decoding of the 'size' field in
+ the AdvSIMD scalar instructions.
+ The heuristic-based rule is that the destination operand is respected
+ more. */
+
+static inline int
+select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
+{
+ int src_size = 0, dst_size = 0;
+ if (aarch64_get_operand_class (opcode->operands[0])
+ == AARCH64_OPND_CLASS_SISD_REG)
+ dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
+ if (aarch64_get_operand_class (opcode->operands[1])
+ == AARCH64_OPND_CLASS_SISD_REG)
+ src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
+ if (src_size == dst_size && src_size == 0)
+ { assert (0); abort (); }
+ /* When the result is not a sisd register or it is a long operantion. */
+ if (dst_size == 0 || dst_size == src_size << 1)
+ return 1;
+ else
+ return 0;
+}
+
+/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
+ the AdvSIMD instructions. */
+
+int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
+\f
+/* Miscellaneous. */
+
+aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
+enum aarch64_modifier_kind
+aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
+
+
+bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
+bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
+int aarch64_shrink_expanded_imm8 (uint64_t);
+
+/* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
+static inline void
+copy_operand_info (aarch64_inst *inst, int dst, int src)
+{
+ assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
+ && src < AARCH64_MAX_OPND_NUM);
+ memcpy (&inst->operands[dst], &inst->operands[src],
+ sizeof (aarch64_opnd_info));
+ inst->operands[dst].idx = dst;
+}
+
+/* A primitive log caculator. */
+
+static inline unsigned int
+get_logsz (unsigned int size)
+{
+ const unsigned char ls[16] =
+ {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
+ if (size > 16)
+ {
+ assert (0);
+ return -1;
+ }
+ assert (ls[size - 1] != (unsigned char)-1);
+ return ls[size - 1];
+}
+
+#endif /* OPCODES_AARCH64_OPC_H */
--- /dev/null
+/* aarch64-tbl.h -- AArch64 opcode description table and instruction
+ operand description table.
+ Copyright 2012 Free Software Foundation, Inc.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "aarch64-opc.h"
+
+/* Operand type. */
+
+#define OPND(x) AARCH64_OPND_##x
+#define OP0() {}
+#define OP1(a) {OPND(a)}
+#define OP2(a,b) {OPND(a), OPND(b)}
+#define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
+#define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)}
+#define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)}
+
+#define QLF(x) AARCH64_OPND_QLF_##x
+#define QLF1(a) {QLF(a)}
+#define QLF2(a,b) {QLF(a), QLF(b)}
+#define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)}
+#define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)}
+#define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)}
+
+/* Qualifiers list. */
+
+/* e.g. MSR <systemreg>, <Xt>. */
+#define QL_SRC_X \
+{ \
+ QLF2(NIL,X), \
+}
+
+/* e.g. MRS <Xt>, <systemreg>. */
+#define QL_DST_X \
+{ \
+ QLF2(X,NIL), \
+}
+
+/* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
+#define QL_SYS \
+{ \
+ QLF5(NIL,NIL,NIL,NIL,X), \
+}
+
+/* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */
+#define QL_SYSL \
+{ \
+ QLF5(X,NIL,NIL,NIL,NIL), \
+}
+
+/* e.g. ADRP <Xd>, <label>. */
+#define QL_ADRP \
+{ \
+ QLF2(X,NIL), \
+}
+
+/* e.g. B.<cond> <label>. */
+#define QL_PCREL_NIL \
+{ \
+ QLF1(NIL), \
+}
+
+/* e.g. TBZ <Xt>, #<imm>, <label>. */
+#define QL_PCREL_14 \
+{ \
+ QLF3(X,imm_0_63,NIL), \
+}
+
+/* e.g. BL <label>. */
+#define QL_PCREL_26 \
+{ \
+ QLF1(NIL), \
+}
+
+/* e.g. LDRSW <Xt>, <label>. */
+#define QL_X_PCREL \
+{ \
+ QLF2(X,NIL), \
+}
+
+/* e.g. LDR <Wt>, <label>. */
+#define QL_R_PCREL \
+{ \
+ QLF2(W,NIL), \
+ QLF2(X,NIL), \
+}
+
+/* e.g. LDR <Dt>, <label>. */
+#define QL_FP_PCREL \
+{ \
+ QLF2(S_S,NIL), \
+ QLF2(S_D,NIL), \
+ QLF2(S_Q,NIL), \
+}
+
+/* e.g. PRFM <prfop>, <label>. */
+#define QL_PRFM_PCREL \
+{ \
+ QLF2(NIL,NIL), \
+}
+
+/* e.g. BR <Xn>. */
+#define QL_I1X \
+{ \
+ QLF1(X), \
+}
+
+/* e.g. RBIT <Wd>, <Wn>. */
+#define QL_I2SAME \
+{ \
+ QLF2(W,W), \
+ QLF2(X,X), \
+}
+
+/* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */
+#define QL_I2_EXT \
+{ \
+ QLF2(W,W), \
+ QLF2(X,W), \
+ QLF2(X,X), \
+}
+
+/* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */
+#define QL_I2SP \
+{ \
+ QLF2(WSP,W), \
+ QLF2(W,WSP), \
+ QLF2(SP,X), \
+ QLF2(X,SP), \
+}
+
+/* e.g. REV <Wd>, <Wn>. */
+#define QL_I2SAMEW \
+{ \
+ QLF2(W,W), \
+}
+
+/* e.g. REV32 <Xd>, <Xn>. */
+#define QL_I2SAMEX \
+{ \
+ QLF2(X,X), \
+}
+
+#define QL_I2SAMER \
+{ \
+ QLF2(W,W), \
+ QLF2(X,X), \
+}
+
+/* e.g. SMULH <Xd>, <Xn>, <Xm>. */
+#define QL_I3SAMEX \
+{ \
+ QLF3(X,X,X), \
+}
+
+/* e.g. UDIV <Xd>, <Xn>, <Xm>. */
+#define QL_I3SAMER \
+{ \
+ QLF3(W,W,W), \
+ QLF3(X,X,X), \
+}
+
+/* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}. */
+#define QL_I3_EXT \
+{ \
+ QLF3(W,W,W), \
+ QLF3(X,X,W), \
+ QLF3(X,X,X), \
+}
+
+/* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>. */
+#define QL_I4SAMER \
+{ \
+ QLF4(W,W,W,W), \
+ QLF4(X,X,X,X), \
+}
+
+/* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */
+#define QL_I3SAMEL \
+{ \
+ QLF3(X,W,W), \
+}
+
+/* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */
+#define QL_I4SAMEL \
+{ \
+ QLF4(X,W,W,X), \
+}
+
+/* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>. */
+#define QL_CSEL \
+{ \
+ QLF4(W, W, W, NIL), \
+ QLF4(X, X, X, NIL), \
+}
+
+/* e.g. CSET <Wd>, <cond>. */
+#define QL_DST_R \
+{ \
+ QLF2(W, NIL), \
+ QLF2(X, NIL), \
+}
+
+/* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. */
+#define QL_BF \
+{ \
+ QLF4(W,W,imm_0_31,imm_0_31), \
+ QLF4(X,X,imm_0_63,imm_0_63), \
+}
+
+/* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */
+#define QL_BF2 \
+{ \
+ QLF4(W,W,imm_0_31,imm_1_32), \
+ QLF4(X,X,imm_0_63,imm_1_64), \
+}
+
+/* e.g. SCVTF <Sd>, <Xn>, #<fbits>. */
+#define QL_FIX2FP \
+{ \
+ QLF3(S_D,W,imm_1_32), \
+ QLF3(S_S,W,imm_1_32), \
+ QLF3(S_D,X,imm_1_64), \
+ QLF3(S_S,X,imm_1_64), \
+}
+
+/* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */
+#define QL_FP2FIX \
+{ \
+ QLF3(W,S_D,imm_1_32), \
+ QLF3(W,S_S,imm_1_32), \
+ QLF3(X,S_D,imm_1_64), \
+ QLF3(X,S_S,imm_1_64), \
+}
+
+/* e.g. SCVTF <Dd>, <Wn>. */
+#define QL_INT2FP \
+{ \
+ QLF2(S_D,W), \
+ QLF2(S_S,W), \
+ QLF2(S_D,X), \
+ QLF2(S_S,X), \
+}
+
+/* e.g. FCVTNS <Xd>, <Dn>. */
+#define QL_FP2INT \
+{ \
+ QLF2(W,S_D), \
+ QLF2(W,S_S), \
+ QLF2(X,S_D), \
+ QLF2(X,S_S), \
+}
+
+/* e.g. FMOV <Xd>, <Vn>.D[1]. */
+#define QL_XVD1 \
+{ \
+ QLF2(X,S_D), \
+}
+
+/* e.g. FMOV <Vd>.D[1], <Xn>. */
+#define QL_VD1X \
+{ \
+ QLF2(S_D,X), \
+}
+
+/* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>. */
+#define QL_EXTR \
+{ \
+ QLF4(W,W,W,imm_0_31), \
+ QLF4(X,X,X,imm_0_63), \
+}
+
+/* e.g. LSL <Wd>, <Wn>, #<uimm>. */
+#define QL_SHIFT \
+{ \
+ QLF3(W,W,imm_0_31), \
+ QLF3(X,X,imm_0_63), \
+}
+
+/* e.g. UXTH <Xd>, <Wn>. */
+#define QL_EXT \
+{ \
+ QLF2(W,W), \
+ QLF2(X,W), \
+}
+
+/* e.g. UXTW <Xd>, <Wn>. */
+#define QL_EXT_W \
+{ \
+ QLF2(X,W), \
+}
+
+/* e.g. SQSHL <V><d>, <V><n>, #<shift>. */
+#define QL_SSHIFT \
+{ \
+ QLF3(S_B , S_B , S_B ), \
+ QLF3(S_H , S_H , S_H ), \
+ QLF3(S_S , S_S , S_S ), \
+ QLF3(S_D , S_D , S_D ) \
+}
+
+/* e.g. SSHR <V><d>, <V><n>, #<shift>. */
+#define QL_SSHIFT_D \
+{ \
+ QLF3(S_D , S_D , S_D ) \
+}
+
+/* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
+#define QL_SSHIFT_SD \
+{ \
+ QLF3(S_S , S_S , S_S ), \
+ QLF3(S_D , S_D , S_D ) \
+}
+
+/* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */
+#define QL_SSHIFTN \
+{ \
+ QLF3(S_B , S_H , S_B ), \
+ QLF3(S_H , S_S , S_H ), \
+ QLF3(S_S , S_D , S_S ), \
+}
+
+/* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>.
+ The register operand variant qualifiers are deliberately used for the
+ immediate operand to ease the operand encoding/decoding and qualifier
+ sequence matching. */
+#define QL_VSHIFT \
+{ \
+ QLF3(V_8B , V_8B , V_8B ), \
+ QLF3(V_16B, V_16B, V_16B), \
+ QLF3(V_4H , V_4H , V_4H ), \
+ QLF3(V_8H , V_8H , V_8H ), \
+ QLF3(V_2S , V_2S , V_2S ), \
+ QLF3(V_4S , V_4S , V_4S ), \
+ QLF3(V_2D , V_2D , V_2D ) \
+}
+
+/* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
+#define QL_VSHIFT_SD \
+{ \
+ QLF3(V_2S , V_2S , V_2S ), \
+ QLF3(V_4S , V_4S , V_4S ), \
+ QLF3(V_2D , V_2D , V_2D ) \
+}
+
+/* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */
+#define QL_VSHIFTN \
+{ \
+ QLF3(V_8B , V_8H , V_8B ), \
+ QLF3(V_4H , V_4S , V_4H ), \
+ QLF3(V_2S , V_2D , V_2S ), \
+}
+
+/* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */
+#define QL_VSHIFTN2 \
+{ \
+ QLF3(V_16B, V_8H, V_16B), \
+ QLF3(V_8H , V_4S , V_8H ), \
+ QLF3(V_4S , V_2D , V_4S ), \
+}
+
+/* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>.
+ the 3rd qualifier is used to help the encoding. */
+#define QL_VSHIFTL \
+{ \
+ QLF3(V_8H , V_8B , V_8B ), \
+ QLF3(V_4S , V_4H , V_4H ), \
+ QLF3(V_2D , V_2S , V_2S ), \
+}
+
+/* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
+#define QL_VSHIFTL2 \
+{ \
+ QLF3(V_8H , V_16B, V_16B), \
+ QLF3(V_4S , V_8H , V_8H ), \
+ QLF3(V_2D , V_4S , V_4S ), \
+}
+
+/* e.g. TBL. */
+#define QL_TABLE \
+{ \
+ QLF3(V_8B , V_16B, V_8B ), \
+ QLF3(V_16B, V_16B, V_16B), \
+}
+
+/* e.g. SHA1H. */
+#define QL_2SAMES \
+{ \
+ QLF2(S_S, S_S), \
+}
+
+/* e.g. ABS <V><d>, <V><n>. */
+#define QL_2SAMED \
+{ \
+ QLF2(S_D, S_D), \
+}
+
+/* e.g. CMGT <V><d>, <V><n>, #0. */
+#define QL_SISD_CMP_0 \
+{ \
+ QLF3(S_D, S_D, NIL), \
+}
+
+/* e.g. FCMEQ <V><d>, <V><n>, #0. */
+#define QL_SISD_FCMP_0 \
+{ \
+ QLF3(S_S, S_S, NIL), \
+ QLF3(S_D, S_D, NIL), \
+}
+
+/* e.g. FMAXNMP <V><d>, <Vn>.<T>. */
+#define QL_SISD_PAIR \
+{ \
+ QLF2(S_S, V_2S), \
+ QLF2(S_D, V_2D), \
+}
+
+/* e.g. ADDP <V><d>, <Vn>.<T>. */
+#define QL_SISD_PAIR_D \
+{ \
+ QLF2(S_D, V_2D), \
+}
+
+/* e.g. DUP <V><d>, <Vn>.<T>[<index>]. */
+#define QL_S_2SAME \
+{ \
+ QLF2(S_B, S_B), \
+ QLF2(S_H, S_H), \
+ QLF2(S_S, S_S), \
+ QLF2(S_D, S_D), \
+}
+
+/* e.g. FCVTNS <V><d>, <V><n>. */
+#define QL_S_2SAMESD \
+{ \
+ QLF2(S_S, S_S), \
+ QLF2(S_D, S_D), \
+}
+
+/* e.g. SQXTN <Vb><d>, <Va><n>. */
+#define QL_SISD_NARROW \
+{ \
+ QLF2(S_B, S_H), \
+ QLF2(S_H, S_S), \
+ QLF2(S_S, S_D), \
+}
+
+/* e.g. FCVTXN <Vb><d>, <Va><n>. */
+#define QL_SISD_NARROW_S \
+{ \
+ QLF2(S_S, S_D), \
+}
+
+/* e.g. FCVT. */
+#define QL_FCVT \
+{ \
+ QLF2(S_S, S_H), \
+ QLF2(S_S, S_D), \
+ QLF2(S_D, S_H), \
+ QLF2(S_D, S_S), \
+ QLF2(S_H, S_S), \
+ QLF2(S_H, S_D), \
+}
+
+/* FMOV <Dd>, <Dn>. */
+#define QL_FP2 \
+{ \
+ QLF2(S_S, S_S), \
+ QLF2(S_D, S_D), \
+}
+
+/* e.g. SQADD <V><d>, <V><n>, <V><m>. */
+#define QL_S_3SAME \
+{ \
+ QLF3(S_B, S_B, S_B), \
+ QLF3(S_H, S_H, S_H), \
+ QLF3(S_S, S_S, S_S), \
+ QLF3(S_D, S_D, S_D), \
+}
+
+/* e.g. CMGE <V><d>, <V><n>, <V><m>. */
+#define QL_S_3SAMED \
+{ \
+ QLF3(S_D, S_D, S_D), \
+}
+
+/* e.g. SQDMULH <V><d>, <V><n>, <V><m>. */
+#define QL_SISD_HS \
+{ \
+ QLF3(S_H, S_H, S_H), \
+ QLF3(S_S, S_S, S_S), \
+}
+
+/* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>. */
+#define QL_SISDL_HS \
+{ \
+ QLF3(S_S, S_H, S_H), \
+ QLF3(S_D, S_S, S_S), \
+}
+
+/* FMUL <Sd>, <Sn>, <Sm>. */
+#define QL_FP3 \
+{ \
+ QLF3(S_S, S_S, S_S), \
+ QLF3(S_D, S_D, S_D), \
+}
+
+/* FMADD <Dd>, <Dn>, <Dm>, <Da>. */
+#define QL_FP4 \
+{ \
+ QLF4(S_S, S_S, S_S, S_S), \
+ QLF4(S_D, S_D, S_D, S_D), \
+}
+
+/* e.g. FCMP <Dn>, #0.0. */
+#define QL_DST_SD \
+{ \
+ QLF2(S_S, NIL), \
+ QLF2(S_D, NIL), \
+}
+
+/* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */
+#define QL_FP_COND \
+{ \
+ QLF4(S_S, S_S, S_S, NIL), \
+ QLF4(S_D, S_D, S_D, NIL), \
+}
+
+/* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */
+#define QL_CCMP \
+{ \
+ QLF4(W, W, NIL, NIL), \
+ QLF4(X, X, NIL, NIL), \
+}
+
+/* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>, */
+#define QL_CCMP_IMM \
+{ \
+ QLF4(W, NIL, NIL, NIL), \
+ QLF4(X, NIL, NIL, NIL), \
+}
+
+/* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */
+#define QL_FCCMP \
+{ \
+ QLF4(S_S, S_S, NIL, NIL), \
+ QLF4(S_D, S_D, NIL, NIL), \
+}
+
+/* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */
+#define QL_DUP_VX \
+{ \
+ QLF2(V_8B , S_B ), \
+ QLF2(V_16B, S_B ), \
+ QLF2(V_4H , S_H ), \
+ QLF2(V_8H , S_H ), \
+ QLF2(V_2S , S_S ), \
+ QLF2(V_4S , S_S ), \
+ QLF2(V_2D , S_D ), \
+}
+
+/* e.g. DUP <Vd>.<T>, <Wn>. */
+#define QL_DUP_VR \
+{ \
+ QLF2(V_8B , W ), \
+ QLF2(V_16B, W ), \
+ QLF2(V_4H , W ), \
+ QLF2(V_8H , W ), \
+ QLF2(V_2S , W ), \
+ QLF2(V_4S , W ), \
+ QLF2(V_2D , X ), \
+}
+
+/* e.g. INS <Vd>.<Ts>[<index>], <Wn>. */
+#define QL_INS_XR \
+{ \
+ QLF2(S_H , W ), \
+ QLF2(S_S , W ), \
+ QLF2(S_D , X ), \
+ QLF2(S_B , W ), \
+}
+
+/* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>]. */
+#define QL_SMOV \
+{ \
+ QLF2(W , S_H), \
+ QLF2(X , S_H), \
+ QLF2(X , S_S), \
+ QLF2(W , S_B), \
+ QLF2(X , S_B), \
+}
+
+/* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>]. */
+#define QL_UMOV \
+{ \
+ QLF2(W , S_H), \
+ QLF2(W , S_S), \
+ QLF2(X , S_D), \
+ QLF2(W , S_B), \
+}
+
+/* e.g. MOV <Wd>, <Vn>.<Ts>[<index>]. */
+#define QL_MOV \
+{ \
+ QLF2(W , S_S), \
+ QLF2(X , S_D), \
+}
+
+/* e.g. SUQADD <Vd>.<T>, <Vn>.<T>. */
+#define QL_V2SAME \
+{ \
+ QLF2(V_8B , V_8B ), \
+ QLF2(V_16B, V_16B), \
+ QLF2(V_4H , V_4H ), \
+ QLF2(V_8H , V_8H ), \
+ QLF2(V_2S , V_2S ), \
+ QLF2(V_4S , V_4S ), \
+ QLF2(V_2D , V_2D ), \
+}
+
+/* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>. */
+#define QL_V2SAMES \
+{ \
+ QLF2(V_2S , V_2S ), \
+ QLF2(V_4S , V_4S ), \
+}
+
+/* e.g. REV32 <Vd>.<T>, <Vn>.<T>. */
+#define QL_V2SAMEBH \
+{ \
+ QLF2(V_8B , V_8B ), \
+ QLF2(V_16B, V_16B), \
+ QLF2(V_4H , V_4H ), \
+ QLF2(V_8H , V_8H ), \
+}
+
+/* e.g. FRINTN <Vd>.<T>, <Vn>.<T>. */
+#define QL_V2SAMESD \
+{ \
+ QLF2(V_2S , V_2S ), \
+ QLF2(V_4S , V_4S ), \
+ QLF2(V_2D , V_2D ), \
+}
+
+/* e.g. REV64 <Vd>.<T>, <Vn>.<T>. */
+#define QL_V2SAMEBHS \
+{ \
+ QLF2(V_8B , V_8B ), \
+ QLF2(V_16B, V_16B), \
+ QLF2(V_4H , V_4H ), \
+ QLF2(V_8H , V_8H ), \
+ QLF2(V_2S , V_2S ), \
+ QLF2(V_4S , V_4S ), \
+}
+
+/* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */
+#define QL_V2SAMEB \
+{ \
+ QLF2(V_8B , V_8B ), \
+ QLF2(V_16B, V_16B), \
+}
+
+/* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>. */
+#define QL_V2PAIRWISELONGBHS \
+{ \
+ QLF2(V_4H , V_8B ), \
+ QLF2(V_8H , V_16B), \
+ QLF2(V_2S , V_4H ), \
+ QLF2(V_4S , V_8H ), \
+ QLF2(V_1D , V_2S ), \
+ QLF2(V_2D , V_4S ), \
+}
+
+/* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
+#define QL_V2LONGBHS \
+{ \
+ QLF2(V_8H , V_8B ), \
+ QLF2(V_4S , V_4H ), \
+ QLF2(V_2D , V_2S ), \
+}
+
+/* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
+#define QL_V2LONGBHS2 \
+{ \
+ QLF2(V_8H , V_16B), \
+ QLF2(V_4S , V_8H ), \
+ QLF2(V_2D , V_4S ), \
+}
+
+/* */
+#define QL_V3SAME \
+{ \
+ QLF3(V_8B , V_8B , V_8B ), \
+ QLF3(V_16B, V_16B, V_16B), \
+ QLF3(V_4H , V_4H , V_4H ), \
+ QLF3(V_8H , V_8H , V_8H ), \
+ QLF3(V_2S , V_2S , V_2S ), \
+ QLF3(V_4S , V_4S , V_4S ), \
+ QLF3(V_2D , V_2D , V_2D ) \
+}
+
+/* e.g. SHADD. */
+#define QL_V3SAMEBHS \
+{ \
+ QLF3(V_8B , V_8B , V_8B ), \
+ QLF3(V_16B, V_16B, V_16B), \
+ QLF3(V_4H , V_4H , V_4H ), \
+ QLF3(V_8H , V_8H , V_8H ), \
+ QLF3(V_2S , V_2S , V_2S ), \
+ QLF3(V_4S , V_4S , V_4S ), \
+}
+
+/* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
+#define QL_V2NARRS \
+{ \
+ QLF2(V_2S , V_2D ), \
+}
+
+/* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
+#define QL_V2NARRS2 \
+{ \
+ QLF2(V_4S , V_2D ), \
+}
+
+/* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
+#define QL_V2NARRHS \
+{ \
+ QLF2(V_4H , V_4S ), \
+ QLF2(V_2S , V_2D ), \
+}
+
+/* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
+#define QL_V2NARRHS2 \
+{ \
+ QLF2(V_8H , V_4S ), \
+ QLF2(V_4S , V_2D ), \
+}
+
+/* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
+#define QL_V2LONGHS \
+{ \
+ QLF2(V_4S , V_4H ), \
+ QLF2(V_2D , V_2S ), \
+}
+
+/* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
+#define QL_V2LONGHS2 \
+{ \
+ QLF2(V_4S , V_8H ), \
+ QLF2(V_2D , V_4S ), \
+}
+
+/* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
+#define QL_V2NARRBHS \
+{ \
+ QLF2(V_8B , V_8H ), \
+ QLF2(V_4H , V_4S ), \
+ QLF2(V_2S , V_2D ), \
+}
+
+/* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
+#define QL_V2NARRBHS2 \
+{ \
+ QLF2(V_16B, V_8H ), \
+ QLF2(V_8H , V_4S ), \
+ QLF2(V_4S , V_2D ), \
+}
+
+/* e.g. ORR. */
+#define QL_V2SAMEB \
+{ \
+ QLF2(V_8B , V_8B ), \
+ QLF2(V_16B, V_16B), \
+}
+
+/* e.g. AESE. */
+#define QL_V2SAME16B \
+{ \
+ QLF2(V_16B, V_16B), \
+}
+
+/* e.g. SHA1SU1. */
+#define QL_V2SAME4S \
+{ \
+ QLF2(V_4S, V_4S), \
+}
+
+/* e.g. SHA1SU0. */
+#define QL_V3SAME4S \
+{ \
+ QLF3(V_4S, V_4S, V_4S), \
+}
+
+/* e.g. SHADD. */
+#define QL_V3SAMEB \
+{ \
+ QLF3(V_8B , V_8B , V_8B ), \
+ QLF3(V_16B, V_16B, V_16B), \
+}
+
+/* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>. */
+#define QL_VEXT \
+{ \
+ QLF4(V_8B , V_8B , V_8B , imm_0_7), \
+ QLF4(V_16B, V_16B, V_16B, imm_0_15), \
+}
+
+/* e.g. . */
+#define QL_V3SAMEHS \
+{ \
+ QLF3(V_4H , V_4H , V_4H ), \
+ QLF3(V_8H , V_8H , V_8H ), \
+ QLF3(V_2S , V_2S , V_2S ), \
+ QLF3(V_4S , V_4S , V_4S ), \
+}
+
+/* */
+#define QL_V3SAMESD \
+{ \
+ QLF3(V_2S , V_2S , V_2S ), \
+ QLF3(V_4S , V_4S , V_4S ), \
+ QLF3(V_2D , V_2D , V_2D ) \
+}
+
+/* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
+#define QL_V3LONGHS \
+{ \
+ QLF3(V_4S , V_4H , V_4H ), \
+ QLF3(V_2D , V_2S , V_2S ), \
+}
+
+/* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
+#define QL_V3LONGHS2 \
+{ \
+ QLF3(V_4S , V_8H , V_8H ), \
+ QLF3(V_2D , V_4S , V_4S ), \
+}
+
+/* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
+#define QL_V3LONGBHS \
+{ \
+ QLF3(V_8H , V_8B , V_8B ), \
+ QLF3(V_4S , V_4H , V_4H ), \
+ QLF3(V_2D , V_2S , V_2S ), \
+}
+
+/* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
+#define QL_V3LONGBHS2 \
+{ \
+ QLF3(V_8H , V_16B , V_16B ), \
+ QLF3(V_4S , V_8H , V_8H ), \
+ QLF3(V_2D , V_4S , V_4S ), \
+}
+
+/* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */
+#define QL_V3WIDEBHS \
+{ \
+ QLF3(V_8H , V_8H , V_8B ), \
+ QLF3(V_4S , V_4S , V_4H ), \
+ QLF3(V_2D , V_2D , V_2S ), \
+}
+
+/* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */
+#define QL_V3WIDEBHS2 \
+{ \
+ QLF3(V_8H , V_8H , V_16B ), \
+ QLF3(V_4S , V_4S , V_8H ), \
+ QLF3(V_2D , V_2D , V_4S ), \
+}
+
+/* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */
+#define QL_V3NARRBHS \
+{ \
+ QLF3(V_8B , V_8H , V_8H ), \
+ QLF3(V_4H , V_4S , V_4S ), \
+ QLF3(V_2S , V_2D , V_2D ), \
+}
+
+/* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */
+#define QL_V3NARRBHS2 \
+{ \
+ QLF3(V_16B , V_8H , V_8H ), \
+ QLF3(V_8H , V_4S , V_4S ), \
+ QLF3(V_4S , V_2D , V_2D ), \
+}
+
+/* e.g. PMULL. */
+#define QL_V3LONGB \
+{ \
+ QLF3(V_8H , V_8B , V_8B ), \
+}
+
+/* e.g. PMULL crypto. */
+#define QL_V3LONGD \
+{ \
+ QLF3(V_1Q , V_1D , V_1D ), \
+}
+
+/* e.g. PMULL2. */
+#define QL_V3LONGB2 \
+{ \
+ QLF3(V_8H , V_16B, V_16B), \
+}
+
+/* e.g. PMULL2 crypto. */
+#define QL_V3LONGD2 \
+{ \
+ QLF3(V_1Q , V_2D , V_2D ), \
+}
+
+/* e.g. SHA1C. */
+#define QL_SHAUPT \
+{ \
+ QLF3(S_Q, S_S, V_4S), \
+}
+
+/* e.g. SHA256H2. */
+#define QL_SHA256UPT \
+{ \
+ QLF3(S_Q, S_Q, V_4S), \
+}
+
+/* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}]. */
+#define QL_W1_LDST_EXC \
+{ \
+ QLF2(W, NIL), \
+}
+
+/* e.g. LDXR <Xt>, [<Xn|SP>{,#0}]. */
+#define QL_R1NIL \
+{ \
+ QLF2(W, NIL), \
+ QLF2(X, NIL), \
+}
+
+/* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
+#define QL_W2_LDST_EXC \
+{ \
+ QLF3(W, W, NIL), \
+}
+
+/* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]. */
+#define QL_R2_LDST_EXC \
+{ \
+ QLF3(W, W, NIL), \
+ QLF3(W, X, NIL), \
+}
+
+/* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
+#define QL_R2NIL \
+{ \
+ QLF3(W, W, NIL), \
+ QLF3(X, X, NIL), \
+}
+
+/* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
+#define QL_R3_LDST_EXC \
+{ \
+ QLF4(W, W, W, NIL), \
+ QLF4(W, X, X, NIL), \
+}
+
+/* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+#define QL_LDST_FP \
+{ \
+ QLF2(S_B, S_B), \
+ QLF2(S_H, S_H), \
+ QLF2(S_S, S_S), \
+ QLF2(S_D, S_D), \
+ QLF2(S_Q, S_Q), \
+}
+
+/* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+#define QL_LDST_R \
+{ \
+ QLF2(W, S_S), \
+ QLF2(X, S_D), \
+}
+
+/* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+#define QL_LDST_W8 \
+{ \
+ QLF2(W, S_B), \
+}
+
+/* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+#define QL_LDST_R8 \
+{ \
+ QLF2(W, S_B), \
+ QLF2(X, S_B), \
+}
+
+/* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+#define QL_LDST_W16 \
+{ \
+ QLF2(W, S_H), \
+}
+
+/* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+#define QL_LDST_X32 \
+{ \
+ QLF2(X, S_S), \
+}
+
+/* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+#define QL_LDST_R16 \
+{ \
+ QLF2(W, S_H), \
+ QLF2(X, S_H), \
+}
+
+/* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
+#define QL_LDST_PRFM \
+{ \
+ QLF2(NIL, S_D), \
+}
+
+/* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */
+#define QL_LDST_PAIR_X32 \
+{ \
+ QLF3(X, X, S_S), \
+}
+
+/* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */
+#define QL_LDST_PAIR_R \
+{ \
+ QLF3(W, W, S_S), \
+ QLF3(X, X, S_D), \
+}
+
+/* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
+#define QL_LDST_PAIR_FP \
+{ \
+ QLF3(S_S, S_S, S_S), \
+ QLF3(S_D, S_D, S_D), \
+ QLF3(S_Q, S_Q, S_Q), \
+}
+
+/* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */
+#define QL_SIMD_LDST \
+{ \
+ QLF2(V_8B, NIL), \
+ QLF2(V_16B, NIL), \
+ QLF2(V_4H, NIL), \
+ QLF2(V_8H, NIL), \
+ QLF2(V_2S, NIL), \
+ QLF2(V_4S, NIL), \
+ QLF2(V_2D, NIL), \
+}
+
+/* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */
+#define QL_SIMD_LDST_ANY \
+{ \
+ QLF2(V_8B, NIL), \
+ QLF2(V_16B, NIL), \
+ QLF2(V_4H, NIL), \
+ QLF2(V_8H, NIL), \
+ QLF2(V_2S, NIL), \
+ QLF2(V_4S, NIL), \
+ QLF2(V_1D, NIL), \
+ QLF2(V_2D, NIL), \
+}
+
+/* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>]. */
+#define QL_SIMD_LDSTONE \
+{ \
+ QLF2(S_B, NIL), \
+ QLF2(S_H, NIL), \
+ QLF2(S_S, NIL), \
+ QLF2(S_D, NIL), \
+}
+
+/* e.g. ADDV <V><d>, <Vn>.<T>. */
+#define QL_XLANES \
+{ \
+ QLF2(S_B, V_8B), \
+ QLF2(S_B, V_16B), \
+ QLF2(S_H, V_4H), \
+ QLF2(S_H, V_8H), \
+ QLF2(S_S, V_4S), \
+}
+
+/* e.g. FMINV <V><d>, <Vn>.<T>. */
+#define QL_XLANES_FP \
+{ \
+ QLF2(S_S, V_4S), \
+}
+
+/* e.g. SADDLV <V><d>, <Vn>.<T>. */
+#define QL_XLANES_L \
+{ \
+ QLF2(S_H, V_8B), \
+ QLF2(S_H, V_16B), \
+ QLF2(S_S, V_4H), \
+ QLF2(S_S, V_8H), \
+ QLF2(S_D, V_4S), \
+}
+
+/* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]. */
+#define QL_ELEMENT \
+{ \
+ QLF3(V_4H, V_4H, S_H), \
+ QLF3(V_8H, V_8H, S_H), \
+ QLF3(V_2S, V_2S, S_S), \
+ QLF3(V_4S, V_4S, S_S), \
+}
+
+/* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */
+#define QL_ELEMENT_L \
+{ \
+ QLF3(V_4S, V_4H, S_H), \
+ QLF3(V_2D, V_2S, S_S), \
+}
+
+/* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */
+#define QL_ELEMENT_L2 \
+{ \
+ QLF3(V_4S, V_8H, S_H), \
+ QLF3(V_2D, V_4S, S_S), \
+}
+
+/* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */
+#define QL_ELEMENT_FP \
+{ \
+ QLF3(V_2S, V_2S, S_S), \
+ QLF3(V_4S, V_4S, S_S), \
+ QLF3(V_2D, V_2D, S_D), \
+}
+
+/* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */
+#define QL_SIMD_IMM_S0W \
+{ \
+ QLF2(V_2S, LSL), \
+ QLF2(V_4S, LSL), \
+}
+
+/* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>. */
+#define QL_SIMD_IMM_S1W \
+{ \
+ QLF2(V_2S, MSL), \
+ QLF2(V_4S, MSL), \
+}
+
+/* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */
+#define QL_SIMD_IMM_S0H \
+{ \
+ QLF2(V_4H, LSL), \
+ QLF2(V_8H, LSL), \
+}
+
+/* e.g. FMOV <Vd>.<T>, #<imm>. */
+#define QL_SIMD_IMM_S \
+{ \
+ QLF2(V_2S, NIL), \
+ QLF2(V_4S, NIL), \
+}
+
+/* e.g. MOVI <Vd>.8B, #<imm8>. */
+#define QL_SIMD_IMM_B \
+{ \
+ QLF2(V_8B, NIL), \
+ QLF2(V_16B, NIL), \
+}
+/* e.g. MOVI <Dd>, #<imm>. */
+#define QL_SIMD_IMM_D \
+{ \
+ QLF2(S_D, NIL), \
+}
+
+/* e.g. MOVI <Vd>.2D, #<imm>. */
+#define QL_SIMD_IMM_V2D \
+{ \
+ QLF2(V_2D, NIL), \
+}
+\f
+/* Opcode table. */
+
+static const aarch64_feature_set aarch64_feature_v8 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8, 0);
+static const aarch64_feature_set aarch64_feature_fp =
+ AARCH64_FEATURE (AARCH64_FEATURE_FP, 0);
+static const aarch64_feature_set aarch64_feature_simd =
+ AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0);
+static const aarch64_feature_set aarch64_feature_crypto =
+ AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0);
+
+#define CORE &aarch64_feature_v8
+#define FP &aarch64_feature_fp
+#define SIMD &aarch64_feature_simd
+#define CRYPTO &aarch64_feature_crypto
+
+struct aarch64_opcode aarch64_opcode_table[] =
+{
+ /* Add/subtract (with carry). */
+ {"adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
+ {"adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
+ {"sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
+ {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
+ {"sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
+ {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
+ /* Add/subtract (extended register). */
+ {"add", 0x0b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
+ {"adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
+ {"cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
+ {"sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
+ {"subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
+ {"cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
+ /* Add/subtract (immediate). */
+ {"add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
+ {"mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, CORE, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF},
+ {"adds", 0x31000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
+ {"cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
+ {"sub", 0x51000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF},
+ {"subs", 0x71000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
+ {"cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
+ /* Add/subtract (shifted register). */
+ {"add", 0xb000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
+ {"adds", 0x2b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
+ {"cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
+ {"sub", 0x4b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
+ {"neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
+ {"subs", 0x6b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
+ {"cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
+ {"negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
+ /* AdvSIMD across lanes. */
+ {"saddlv", 0xe303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ},
+ {"smaxv", 0xe30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
+ {"sminv", 0xe31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
+ {"addv", 0xe31b800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
+ {"uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ},
+ {"umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
+ {"uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
+ {"fmaxnmv", 0x2e30c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
+ {"fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
+ {"fminnmv", 0x2eb0c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
+ {"fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
+ /* AdvSIMD three different. */
+ {"saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
+ {"saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
+ {"ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
+ {"ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
+ {"addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
+ {"addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
+ {"sabal", 0x0e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"sabal2", 0x4e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"subhn", 0x0e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
+ {"subhn2", 0x4e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
+ {"sabdl", 0x0e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"sabdl2", 0x4e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"smlal", 0x0e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"smlal2", 0x4e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
+ {"sqdmlal2", 0x4e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
+ {"smlsl", 0x0e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
+ {"sqdmlsl2", 0x4e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
+ {"smull", 0x0e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"smull2", 0x4e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
+ {"sqdmull2", 0x4e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
+ {"pmull", 0x0e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0},
+ {"pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0},
+ {"pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0},
+ {"pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0},
+ {"uaddl", 0x2e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"uaddl2", 0x6e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"uaddw", 0x2e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
+ {"uaddw2", 0x6e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
+ {"usubl", 0x2e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"usubl2", 0x6e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"usubw", 0x2e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
+ {"usubw2", 0x6e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
+ {"raddhn", 0x2e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
+ {"raddhn2", 0x6e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
+ {"uabal", 0x2e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"uabal2", 0x6e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
+ {"rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
+ {"uabdl", 0x2e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"uabdl2", 0x6e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"umlal", 0x2e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"umlal2", 0x6e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"umlsl", 0x2e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ {"umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
+ {"umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ /* AdvSIMD vector x indexed element. */
+ {"smlal", 0x0f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
+ {"smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
+ {"sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
+ {"sqdmlal2", 0x4f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
+ {"smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
+ {"smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
+ {"sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
+ {"sqdmlsl2", 0x4f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
+ {"mul", 0xf008000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
+ {"smull", 0x0f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
+ {"smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
+ {"sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
+ {"sqdmull2", 0x4f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
+ {"sqdmulh", 0xf00c000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
+ {"sqrdmulh", 0xf00d000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
+ {"fmla", 0xf801000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
+ {"fmls", 0xf805000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
+ {"fmul", 0xf809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
+ {"mla", 0x2f000000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
+ {"umlal", 0x2f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
+ {"umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
+ {"mls", 0x2f004000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
+ {"umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
+ {"umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
+ {"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
+ {"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
+ {"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
+ /* AdvSIMD EXT. */
+ {"ext", 0x2e000000, 0xbfe0c400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
+ /* AdvSIMD modified immediate. */
+ {"movi", 0xf000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
+ {"orr", 0xf001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
+ {"movi", 0xf008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
+ {"orr", 0xf009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
+ {"movi", 0xf00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
+ {"movi", 0xf00e400, 0xbff8fc00, asimdimm, OP_V_MOVI_B, SIMD, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_B, F_SIZEQ},
+ {"fmov", 0xf00f400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ},
+ {"mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
+ {"bic", 0x2f001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
+ {"mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
+ {"bic", 0x2f009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
+ {"mvni", 0x2f00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
+ {"movi", 0x2f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ},
+ {"movi", 0x6f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ},
+ {"fmov", 0x6f00f400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ},
+ /* AdvSIMD copy. */
+ {"dup", 0xe000400, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, En), QL_DUP_VX, F_T},
+ {"dup", 0xe000c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, Rn), QL_DUP_VR, F_T},
+ {"smov", 0xe002c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q},
+ {"umov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q},
+ {"mov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q},
+ {"ins", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS},
+ {"mov", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS},
+ {"ins", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS},
+ {"mov", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_ALIAS},
+ /* AdvSIMD two-reg misc. */
+ {"rev64", 0xe200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
+ {"rev16", 0xe201800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
+ {"saddlp", 0xe202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
+ {"suqadd", 0xe203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
+ {"cls", 0xe204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
+ {"cnt", 0xe205800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
+ {"sadalp", 0xe206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
+ {"sqabs", 0xe207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
+ {"cmgt", 0xe208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
+ {"cmeq", 0xe209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
+ {"cmlt", 0xe20a800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
+ {"abs", 0xe20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
+ {"xtn", 0xe212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
+ {"xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
+ {"sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
+ {"sqxtn2", 0x4e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
+ {"fcvtn", 0xe216800, 0xffbffc00, asimdmisc, OP_FCVTN, SIMD, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC},
+ {"fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, SIMD, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC},
+ {"fcvtl", 0xe217800, 0xffbffc00, asimdmisc, OP_FCVTL, SIMD, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC},
+ {"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC},
+ {"frintn", 0xe218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frintm", 0xe219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtns", 0xe21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtms", 0xe21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtas", 0xe21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"scvtf", 0xe21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAMESD, F_SIZEQ},
+ {"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAMESD, F_SIZEQ},
+ {"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAMESD, F_SIZEQ},
+ {"fabs", 0xea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frintp", 0xea18800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frintz", 0xea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtps", 0xea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtzs", 0xea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"urecpe", 0xea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
+ {"frecpe", 0xea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ},
+ {"uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
+ {"usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
+ {"clz", 0x2e204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
+ {"uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
+ {"sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
+ {"cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
+ {"cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
+ {"neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
+ {"sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
+ {"sqxtun2", 0x6e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
+ {"shll", 0x2e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ},
+ {"shll2", 0x6e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ},
+ {"uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
+ {"uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
+ {"fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS, 0},
+ {"fcvtxn2", 0x6e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS2, 0},
+ {"frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"not", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS},
+ {"mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS},
+ {"rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
+ {"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAMESD, F_SIZEQ},
+ {"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAMESD, F_SIZEQ},
+ {"fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"ursqrte", 0x2ea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
+ {"frsqrte", 0x2ea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ /* AdvSIMD ZIP/UZP/TRN. */
+ {"uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"zip1", 0xe003800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"uzp2", 0xe005800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"trn2", 0xe006800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"zip2", 0xe007800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ /* AdvSIMD three same. */
+ {"shadd", 0xe200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"sqadd", 0xe200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"srhadd", 0xe201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"shsub", 0xe202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"sqsub", 0xe202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"cmgt", 0xe203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"cmge", 0xe203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"sshl", 0xe204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"sqshl", 0xe204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"srshl", 0xe205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"smax", 0xe206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"smin", 0xe206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"sabd", 0xe207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"saba", 0xe207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"add", 0xe208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"cmtst", 0xe208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"mla", 0xe209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"mul", 0xe209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"smaxp", 0xe20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"sminp", 0xe20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
+ {"addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ {"bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ {"fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ},
+ {"mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV},
+ {"orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ {"uhadd", 0x2e200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"urhadd", 0x2e201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"uhsub", 0x2e202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"cmhi", 0x2e203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"ushl", 0x2e204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"urshl", 0x2e205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"umax", 0x2e206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"umin", 0x2e206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"uabd", 0x2e207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"uaba", 0x2e207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"sub", 0x2e208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ {"mls", 0x2e209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"pmul", 0x2e209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ {"umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
+ {"sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
+ {"fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ {"bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ {"fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+ {"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ {"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ /* AdvSIMD shift by immediate. */
+ {"sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
+ {"ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
+ {"srshr", 0xf002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
+ {"srsra", 0xf003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
+ {"shl", 0xf005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
+ {"sqshl", 0xf007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
+ {"shrn", 0xf008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
+ {"shrn2", 0x4f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
+ {"rshrn", 0xf008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
+ {"rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
+ {"sqshrn", 0xf009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
+ {"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
+ {"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
+ {"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
+ {"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, 0},
+ {"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, 0},
+ {"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
+ {"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
+ {"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
+ {"usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
+ {"urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
+ {"ursra", 0x2f003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
+ {"sri", 0x2f004400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
+ {"sli", 0x2f005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
+ {"sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
+ {"uqshl", 0x2f007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
+ {"sqshrun", 0x2f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
+ {"sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
+ {"sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
+ {"sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
+ {"uqshrn", 0x2f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
+ {"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
+ {"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
+ {"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
+ {"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, 0},
+ {"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, 0},
+ {"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
+ {"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
+ /* AdvSIMD TBL/TBX. */
+ {"tbl", 0xe000000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ},
+ {"tbx", 0xe001000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ},
+ /* AdvSIMD scalar three different. */
+ {"sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
+ {"sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
+ {"sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
+ /* AdvSIMD scalar x indexed element. */
+ {"sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
+ {"sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
+ {"sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
+ {"sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
+ {"sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
+ {"fmla", 0x5f801000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
+ {"fmls", 0x5f805000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
+ {"fmul", 0x5f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
+ {"fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
+ /* AdvSIMD load/store multiple structures. */
+ {"st4", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
+ {"st1", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
+ {"st2", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
+ {"st3", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
+ {"ld4", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
+ {"ld1", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
+ {"ld2", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
+ {"ld3", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
+ /* AdvSIMD load/store multiple structures (post-indexed). */
+ {"st4", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
+ {"st1", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
+ {"st2", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
+ {"st3", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
+ {"ld4", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
+ {"ld1", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
+ {"ld2", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
+ {"ld3", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
+ /* AdvSIMD load/store single structure. */
+ {"st1", 0xd000000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)},
+ {"st3", 0xd002000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)},
+ {"st2", 0xd200000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)},
+ {"st4", 0xd202000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)},
+ {"ld1", 0xd400000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)},
+ {"ld3", 0xd402000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)},
+ {"ld1r", 0xd40c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
+ {"ld3r", 0xd40e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)},
+ {"ld2", 0xd600000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)},
+ {"ld4", 0xd602000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)},
+ {"ld2r", 0xd60c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)},
+ {"ld4r", 0xd60e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)},
+ /* AdvSIMD load/store single structure (post-indexed). */
+ {"st1", 0xd800000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)},
+ {"st3", 0xd802000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)},
+ {"st2", 0xda00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)},
+ {"st4", 0xda02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)},
+ {"ld1", 0xdc00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)},
+ {"ld3", 0xdc02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)},
+ {"ld1r", 0xdc0c000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
+ {"ld3r", 0xdc0e000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)},
+ {"ld2", 0xde00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)},
+ {"ld4", 0xde02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)},
+ {"ld2r", 0xde0c000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)},
+ {"ld4r", 0xde0e000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)},
+ /* AdvSIMD scalar two-reg misc. */
+ {"suqadd", 0x5e203800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
+ {"sqabs", 0x5e207800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
+ {"cmgt", 0x5e208800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
+ {"cmeq", 0x5e209800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
+ {"cmlt", 0x5e20a800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
+ {"abs", 0x5e20b800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE},
+ {"sqxtn", 0x5e214800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
+ {"fcvtns", 0x5e21a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"scvtf", 0x5e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_FCMP_0, F_SSIZE},
+ {"fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_FCMP_0, F_SSIZE},
+ {"fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_FCMP_0, F_SSIZE},
+ {"fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"frecpx", 0x5ea1f800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"usqadd", 0x7e203800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
+ {"sqneg", 0x7e207800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
+ {"cmge", 0x7e208800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
+ {"cmle", 0x7e209800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
+ {"neg", 0x7e20b800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE},
+ {"sqxtun", 0x7e212800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
+ {"uqxtn", 0x7e214800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
+ {"fcvtxn", 0x7e216800, 0xffbffc00, asisdmisc, OP_FCVTXN_S, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW_S, F_MISC},
+ {"fcvtnu", 0x7e21a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_FCMP_0, F_SSIZE},
+ {"fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_FCMP_0, F_SSIZE},
+ {"fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ {"frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
+ /* AdvSIMD scalar copy. */
+ {"dup", 0x5e000400, 0xffe0fc00, asisdone, 0, SIMD, OP2 (Sd, En), QL_S_2SAME, F_HAS_ALIAS},
+ {"mov", 0x5e000400, 0xffe0fc00, asisdone, 0, SIMD, OP2 (Sd, En), QL_S_2SAME, F_ALIAS},
+ /* AdvSIMD scalar pairwise. */
+ {"addp", 0x5e31b800, 0xff3ffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR_D, F_SIZEQ},
+ {"fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
+ {"faddp", 0x7e30d800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
+ {"fmaxp", 0x7e30f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
+ {"fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
+ {"fminp", 0x7eb0f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
+ /* AdvSIMD scalar three same. */
+ {"sqadd", 0x5e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
+ {"sqsub", 0x5e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
+ {"sqshl", 0x5e204c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
+ {"sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
+ {"sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
+ {"fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+ {"fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+ {"frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+ {"frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+ {"cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"sshl", 0x5ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"srshl", 0x5ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"add", 0x5ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"cmtst", 0x5ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"uqadd", 0x7e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
+ {"uqsub", 0x7e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
+ {"uqshl", 0x7e204c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
+ {"uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
+ {"sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
+ {"fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+ {"facge", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+ {"fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+ {"fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+ {"facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+ {"cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"ushl", 0x7ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ {"cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ /* AdvSIMD scalar shift by immediate. */
+ {"sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
+ {"ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
+ {"srshr", 0x5f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
+ {"srsra", 0x5f003400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
+ {"shl", 0x5f005400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0},
+ {"sqshl", 0x5f007400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
+ {"sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
+ {"sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
+ {"scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
+ {"fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
+ {"ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
+ {"usra", 0x7f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
+ {"urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
+ {"ursra", 0x7f003400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
+ {"sri", 0x7f004400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
+ {"sli", 0x7f005400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0},
+ {"sqshlu", 0x7f006400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
+ {"uqshl", 0x7f007400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
+ {"sqshrun", 0x7f008400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
+ {"sqrshrun", 0x7f008c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
+ {"uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
+ {"uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
+ {"ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
+ {"fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
+ /* Bitfield. */
+ {"sbfm", 0x13000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
+ {"sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
+ {"sbfx", 0x13000000, 0x7f800000, bitfield, OP_SBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
+ {"sxtb", 0x13001c00, 0x7fbffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N},
+ {"sxth", 0x13003c00, 0x7fbffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N},
+ {"sxtw", 0x93407c00, 0xfffffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT_W, F_ALIAS | F_P3},
+ {"asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
+ {"bfm", 0x33000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
+ {"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
+ {"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
+ {"ubfm", 0x53000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
+ {"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
+ {"ubfx", 0x53000000, 0x7f800000, bitfield, OP_UBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
+ {"uxtb", 0x53001c00, 0xfffffc00, bitfield, OP_UXTB, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3},
+ {"uxth", 0x53003c00, 0xfffffc00, bitfield, OP_UXTH, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3},
+ {"lsl", 0x53000000, 0x7f800000, bitfield, OP_LSL_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
+ {"lsr", 0x53000000, 0x7f800000, bitfield, OP_LSR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
+ /* Unconditional branch (immediate). */
+ {"b", 0x14000000, 0xfc000000, branch_imm, OP_B, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0},
+ {"bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0},
+ /* Unconditional branch (register). */
+ {"br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, 0},
+ {"blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, 0},
+ {"ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)},
+ {"eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, CORE, OP0 (), {}, 0},
+ {"drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, CORE, OP0 (), {}, 0},
+ /* Compare & branch (immediate). */
+ {"cbz", 0x34000000, 0x7f000000, compbranch, 0, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF},
+ {"cbnz", 0x35000000, 0x7f000000, compbranch, 0, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF},
+ /* Conditional branch (immediate). */
+ {"b.c", 0x54000000, 0xff000010, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND},
+ /* Conditional compare (immediate). */
+ {"ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF},
+ {"ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF},
+ /* Conditional compare (register). */
+ {"ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF},
+ {"ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF},
+ /* Conditional select. */
+ {"csel", 0x1a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF},
+ {"csinc", 0x1a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
+ {"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
+ {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
+ {"csinv", 0x5a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
+ {"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
+ {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
+ {"csneg", 0x5a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
+ {"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
+ /* Crypto AES. */
+ {"aese", 0x4e284800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
+ {"aesd", 0x4e285800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
+ {"aesmc", 0x4e286800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
+ {"aesimc", 0x4e287800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
+ /* Crypto two-reg SHA. */
+ {"sha1h", 0x5e280800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Fd, Fn), QL_2SAMES, 0},
+ {"sha1su1", 0x5e281800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME4S, 0},
+ {"sha256su0", 0x5e282800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME4S, 0},
+ /* Crypto three-reg SHA. */
+ {"sha1c", 0x5e000000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
+ {"sha1p", 0x5e001000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
+ {"sha1m", 0x5e002000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
+ {"sha1su0", 0x5e003000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0},
+ {"sha256h", 0x5e004000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0},
+ {"sha256h2", 0x5e005000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0},
+ {"sha256su1", 0x5e006000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0},
+ /* Data-processing (1 source). */
+ {"rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
+ {"rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
+ {"rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEW, 0},
+ {"rev", 0xdac00c00, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0},
+ {"clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
+ {"cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
+ {"rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0},
+ /* Data-processing (2 source). */
+ {"udiv", 0x1ac00800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
+ {"sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
+ {"lslv", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
+ {"lsl", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
+ {"lsrv", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
+ {"lsr", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
+ {"asrv", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
+ {"asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
+ {"rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
+ {"ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
+ /* Data-processing (3 source). */
+ {"madd", 0x1b000000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF},
+ {"mul", 0x1b007c00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF},
+ {"msub", 0x1b008000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF},
+ {"mneg", 0x1b00fc00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF},
+ {"smaddl", 0x9b200000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
+ {"smull", 0x9b207c00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
+ {"smsubl", 0x9b208000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
+ {"smnegl", 0x9b20fc00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
+ {"smulh", 0x9b407c00, 0xffe08000, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0},
+ {"umaddl", 0x9ba00000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
+ {"umull", 0x9ba07c00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
+ {"umsubl", 0x9ba08000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
+ {"umnegl", 0x9ba0fc00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
+ {"umulh", 0x9bc07c00, 0xffe08000, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0},
+ /* Excep'n generation. */
+ {"svc", 0xd4000001, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
+ {"hvc", 0xd4000002, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
+ {"smc", 0xd4000003, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
+ {"brk", 0xd4200000, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
+ {"hlt", 0xd4400000, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
+ {"dcps1", 0xd4a00001, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
+ {"dcps2", 0xd4a00002, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
+ {"dcps3", 0xd4a00003, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
+ /* Extract. */
+ {"extr", 0x13800000, 0x7fa00000, extract, 0, CORE, OP4 (Rd, Rn, Rm, IMMS), QL_EXTR, F_HAS_ALIAS | F_SF | F_N},
+ {"ror", 0x13800000, 0x7fa00000, extract, OP_ROR_IMM, CORE, OP3 (Rd, Rm, IMMS), QL_SHIFT, F_ALIAS | F_CONV},
+ /* Floating-point<->fixed-point conversions. */
+ {"scvtf", 0x1e020000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF},
+ {"ucvtf", 0x1e030000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF},
+ {"fcvtzs", 0x1e180000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF},
+ {"fcvtzu", 0x1e190000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF},
+ /* Floating-point<->integer conversions. */
+ {"fcvtns", 0x1e200000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtnu", 0x1e210000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
+ {"ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
+ {"fcvtas", 0x1e240000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtau", 0x1e250000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
+ {"fcvtps", 0x1e280000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtpu", 0x1e290000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtms", 0x1e300000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtmu", 0x1e310000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtzs", 0x1e380000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtzu", 0x1e390000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fmov", 0x9eae0000, 0xfffffc00, float2int, 0, FP, OP2 (Rd, VnD1), QL_XVD1, 0},
+ {"fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, FP, OP2 (VdD1, Rn), QL_VD1X, 0},
+ /* Floating-point conditional compare. */
+ {"fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
+ {"fccmpe", 0x1e200410, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
+ /* Floating-point compare. */
+ {"fcmp", 0x1e202000, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE},
+ {"fcmpe", 0x1e202010, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE},
+ {"fcmp", 0x1e202008, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE},
+ {"fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE},
+ /* Floating-point data-processing (1 source). */
+ {"fmov", 0x1e204000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"fabs", 0x1e20c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"fneg", 0x1e214000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"fcvt", 0x1e224000, 0xff3e7c00, floatdp1, OP_FCVT, FP, OP2 (Fd, Fn), QL_FCVT, F_FPTYPE | F_MISC},
+ {"frintn", 0x1e244000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frintp", 0x1e24c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frintm", 0x1e254000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frintz", 0x1e25c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frinta", 0x1e264000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frintx", 0x1e274000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frinti", 0x1e27c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ /* Floating-point data-processing (2 source). */
+ {"fmul", 0x1e200800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fdiv", 0x1e201800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fadd", 0x1e202800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fsub", 0x1e203800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fmax", 0x1e204800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fmin", 0x1e205800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fmaxnm", 0x1e206800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fminnm", 0x1e207800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fnmul", 0x1e208800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ /* Floating-point data-processing (3 source). */
+ {"fmadd", 0x1f000000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
+ {"fmsub", 0x1f008000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
+ {"fnmadd", 0x1f200000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
+ {"fnmsub", 0x1f208000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
+ /* Floating-point immediate. */
+ {"fmov", 0x1e201000, 0xff201fe0, floatimm, 0, FP, OP2 (Fd, FPIMM), QL_DST_SD, F_FPTYPE},
+ /* Floating-point conditional select. */
+ {"fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, FP, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE},
+ /* Load/store register (immediate indexed). */
+ {"strb", 0x38000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
+ {"ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
+ {"ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
+ {"str", 0x3c000400, 0x3f600400, ldst_imm9, 0, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
+ {"ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
+ {"strh", 0x78000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
+ {"ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
+ {"ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
+ {"str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
+ {"ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
+ {"ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
+ /* Load/store register (unsigned immediate). */
+ {"strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0},
+ {"ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0},
+ {"ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE},
+ {"str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0},
+ {"ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0},
+ {"strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0},
+ {"ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0},
+ {"ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE},
+ {"str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q},
+ {"ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q},
+ {"ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0},
+ {"prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, CORE, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0},
+ /* Load/store register (register offset). */
+ {"strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0},
+ {"ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0},
+ {"ldrsb", 0x38a00800, 0xffa00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R8, F_LDS_SIZE},
+ {"str", 0x3c200800, 0x3f600c00, ldst_regoff, 0, CORE, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0},
+ {"ldr", 0x3c600800, 0x3f600c00, ldst_regoff, 0, CORE, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0},
+ {"strh", 0x78200800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0},
+ {"ldrh", 0x78600800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0},
+ {"ldrsh", 0x78a00800, 0xffa00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R16, F_LDS_SIZE},
+ {"str", 0xb8200800, 0xbfe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q},
+ {"ldr", 0xb8600800, 0xbfe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q},
+ {"ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0},
+ {"prfm", 0xf8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (PRFOP, ADDR_REGOFF), QL_LDST_PRFM, 0},
+ /* Load/store register (unprivileged). */
+ {"sttrb", 0x38000800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
+ {"ldtrb", 0x38400800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
+ {"ldtrsb", 0x38800800, 0xffa00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
+ {"sttrh", 0x78000800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
+ {"ldtrh", 0x78400800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
+ {"ldtrsh", 0x78800800, 0xffa00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
+ {"sttr", 0xb8000800, 0xbfe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
+ {"ldtr", 0xb8400800, 0xbfe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
+ {"ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
+ /* Load/store register (unscaled immediate). */
+ {"sturb", 0x38000000, 0xffe00c00, ldst_unscaled, OP_STURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, F_HAS_ALIAS},
+ {"ldurb", 0x38400000, 0xffe00c00, ldst_unscaled, OP_LDURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, F_HAS_ALIAS},
+ {"strb", 0x38000000, 0xffe00c00, ldst_unscaled, 0, CORE, OP2 (Rt, ADDR_SIMM9_2), QL_LDST_W8, F_ALIAS},
+ {"ldrb", 0x38400000, 0xffe00c00, ldst_unscaled, 0, CORE, OP2 (Rt, ADDR_SIMM9_2), QL_LDST_W8, F_ALIAS},
+ {"ldursb", 0x38800000, 0xffa00c00, ldst_unscaled, OP_LDURSB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_HAS_ALIAS | F_LDS_SIZE},
+ {"ldrsb", 0x38800000, 0xffa00c00, ldst_unscaled, 0, CORE, OP2 (Rt, ADDR_SIMM9_2), QL_LDST_R8, F_ALIAS | F_LDS_SIZE},
+ {"stur", 0x3c000000, 0x3f600c00, ldst_unscaled, OP_STURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, F_HAS_ALIAS},
+ {"ldur", 0x3c400000, 0x3f600c00, ldst_unscaled, OP_LDURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, F_HAS_ALIAS},
+ {"str", 0x3c000000, 0x3f600c00, ldst_unscaled, 0, CORE, OP2 (Ft, ADDR_SIMM9_2), QL_LDST_FP, F_ALIAS},
+ {"ldr", 0x3c400000, 0x3f600c00, ldst_unscaled, 0, CORE, OP2 (Ft, ADDR_SIMM9_2), QL_LDST_FP, F_ALIAS},
+ {"sturh", 0x78000000, 0xffe00c00, ldst_unscaled, OP_STURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, F_HAS_ALIAS},
+ {"ldurh", 0x78400000, 0xffe00c00, ldst_unscaled, OP_LDURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, F_HAS_ALIAS},
+ {"strh", 0x78000000, 0xffe00c00, ldst_unscaled, 0, CORE, OP2 (Rt, ADDR_SIMM9_2), QL_LDST_W16, F_ALIAS},
+ {"ldrh", 0x78400000, 0xffe00c00, ldst_unscaled, 0, CORE, OP2 (Rt, ADDR_SIMM9_2), QL_LDST_W16, F_ALIAS},
+ {"ldursh", 0x78800000, 0xffa00c00, ldst_unscaled, OP_LDURSH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_HAS_ALIAS | F_LDS_SIZE},
+ {"ldrsh", 0x78800000, 0xffa00c00, ldst_unscaled, 0, CORE, OP2 (Rt, ADDR_SIMM9_2), QL_LDST_R16, F_ALIAS | F_LDS_SIZE},
+ {"stur", 0xb8000000, 0xbfe00c00, ldst_unscaled, OP_STUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_HAS_ALIAS | F_GPRSIZE_IN_Q},
+ {"ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_HAS_ALIAS | F_GPRSIZE_IN_Q},
+ {"str", 0xb8000000, 0xbfe00c00, ldst_unscaled, 0, CORE, OP2 (Rt, ADDR_SIMM9_2), QL_LDST_R, F_ALIAS | F_GPRSIZE_IN_Q},
+ {"ldr", 0xb8400000, 0xbfe00c00, ldst_unscaled, 0, CORE, OP2 (Rt, ADDR_SIMM9_2), QL_LDST_R, F_ALIAS | F_GPRSIZE_IN_Q},
+ {"ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, F_HAS_ALIAS},
+ {"ldrsw", 0xb8800000, 0xffe00c00, ldst_unscaled, 0, CORE, OP2 (Rt, ADDR_SIMM9_2), QL_LDST_X32, F_ALIAS},
+ {"prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, CORE, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, F_HAS_ALIAS},
+ {"prfm", 0xf8800000, 0xffe00c00, ldst_unscaled, 0, CORE, OP2 (PRFOP, ADDR_SIMM9_2), QL_LDST_PRFM, F_ALIAS},
+ /* Load/store exclusive. */
+ {"stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldxrb", 0x85f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"stlrb", 0x89ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"ldarb", 0x8dffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"ldarh", 0x48dffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q},
+ {"stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q},
+ {"stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q},
+ {"stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q},
+ {"ldxr", 0x885f7c00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ {"ldaxr", 0x885ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ {"ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
+ {"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
+ {"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ {"ldar", 0x88dffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ /* Load/store no-allocate pair (offset). */
+ {"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
+ {"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
+ {"stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
+ {"ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
+ /* Load/store register pair (offset). */
+ {"stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
+ {"ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
+ {"stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
+ {"ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
+ {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0},
+ /* Load/store register pair (indexed). */
+ {"stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
+ {"ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
+ {"stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
+ {"ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
+ {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0},
+ /* Load register (literal). */
+ {"ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q},
+ {"ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, CORE, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0},
+ {"ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0},
+ {"prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, CORE, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0},
+ /* Logical (immediate). */
+ {"and", 0x12000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
+ {"bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF},
+ {"orr", 0x32000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
+ {"mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, CORE, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_PSEUDO | F_P1 | F_SF | F_CONV},
+ {"eor", 0x52000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF},
+ {"ands", 0x72000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
+ {"tst", 0x7200001f, 0x7f80001f, log_imm, 0, CORE, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF},
+ /* Logical (shifted register). */
+ {"and", 0xa000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
+ {"bic", 0xa200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
+ {"orr", 0x2a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
+ {"mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm), QL_I2SAMER, F_ALIAS | F_SF},
+ {"uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, CORE, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO},
+ {"orn", 0x2a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
+ {"mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
+ {"eor", 0x4a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
+ {"eon", 0x4a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
+ {"ands", 0x6a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
+ {"tst", 0x6a00001f, 0x7f20001f, log_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
+ {"bics", 0x6a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
+ /* Move wide (immediate). */
+ {"movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
+ {"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_PSEUDO | F_CONV},
+ {"movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
+ {"mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_PSEUDO | F_CONV},
+ {"movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF},
+ /* PC-rel. addressing. */
+ {"adr", 0x10000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0},
+ {"adrp", 0x90000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0},
+ /* System. */
+ {"msr", 0xd500401f, 0xfff8f01f, ic_system, 0, CORE, OP2 (PSTATEFIELD, UIMM4), {}, 0},
+ {"hint", 0xd503201f, 0xfffff01f, ic_system, 0, CORE, OP1 (UIMM7), {}, F_HAS_ALIAS},
+ {"nop", 0xd503201f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
+ {"yield", 0xd503203f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
+ {"wfe", 0xd503205f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
+ {"wfi", 0xd503207f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
+ {"sev", 0xd503209f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
+ {"sevl", 0xd50320bf, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
+ {"clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, CORE, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
+ {"dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
+ {"dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
+ {"isb", 0xd50330df, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
+ {"sys", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP5 (UIMM3_OP1, Cn, Cm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)},
+ {"at", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS},
+ {"dc", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS},
+ {"ic", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
+ {"tlbi", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
+ {"msr", 0xd5100000, 0xfff00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0},
+ {"sysl", 0xd5280000, 0xfff80000, ic_system, 0, CORE, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0},
+ {"mrs", 0xd5300000, 0xfff00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0},
+ /* Test & branch (immediate). */
+ {"tbz", 0x36000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
+ {"tbnz", 0x37000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
+ /* The old UAL conditional branch mnemonics (to aid portability). */
+ {"beq", 0x54000000, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bne", 0x54000001, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bcs", 0x54000002, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bhs", 0x54000002, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bcc", 0x54000003, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"blo", 0x54000003, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bmi", 0x54000004, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bpl", 0x54000005, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bvs", 0x54000006, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bvc", 0x54000007, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bhi", 0x54000008, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bls", 0x54000009, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bge", 0x5400000a, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"blt", 0x5400000b, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"bgt", 0x5400000c, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+ {"ble", 0x5400000d, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+
+ {0, 0, 0, 0, 0, 0, {}, {}, 0},
+};
+
+#ifdef AARCH64_OPERANDS
+#undef AARCH64_OPERANDS
+#endif
+
+/* Macro-based operand decription; this will be fed into aarch64-gen for it
+ to generate the structure aarch64_operands and the function
+ aarch64_insert_operand and aarch64_extract_operand.
+
+ These inserters and extracters in the description execute the conversion
+ between the aarch64_opnd_info and value in the operand-related instruction
+ field(s). */
+
+/* Y expects arguments (left to right) to be operand class, inserter/extractor
+ name suffix, operand name, flags, related bitfield(s) and description.
+ X only differs from Y by having the operand inserter and extractor names
+ listed separately. */
+
+#define AARCH64_OPERANDS \
+ Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register") \
+ Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \
+ Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \
+ Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \
+ Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \
+ Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \
+ Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
+ X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \
+ "an integer register") \
+ Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd), \
+ "an integer or stack pointer register") \
+ Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \
+ "an integer or stack pointer register") \
+ Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \
+ "an integer register with optional extension") \
+ Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \
+ "an integer register with optional shift") \
+ Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \
+ Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \
+ Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \
+ Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register") \
+ Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register") \
+ Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \
+ Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \
+ Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \
+ Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \
+ Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \
+ Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \
+ Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \
+ Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd), \
+ "the top half of a 128-bit FP/SIMD register") \
+ Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn), \
+ "the top half of a 128-bit FP/SIMD register") \
+ Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd), \
+ "a SIMD vector element") \
+ Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn), \
+ "a SIMD vector element") \
+ Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \
+ "a SIMD vector element") \
+ Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \
+ "a SIMD vector register list") \
+ Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \
+ "a SIMD vector register list") \
+ Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(), \
+ "a SIMD vector register list") \
+ Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(), \
+ "a SIMD vector element list") \
+ Y(CP_REG, regno, "Cn", 0, F(FLD_CRn), \
+ "a 4-bit opcode field named for historical reasons C0 - C15") \
+ Y(CP_REG, regno, "Cm", 0, F(FLD_CRm), \
+ "a 4-bit opcode field named for historical reasons C0 - C15") \
+ Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \
+ "an immediate as the index of the least significant byte") \
+ Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \
+ "a left shift amount for an AdvSIMD register") \
+ Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(), \
+ "a right shift amount for an AdvSIMD register") \
+ Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM", 0, F(), \
+ "an immediate") \
+ Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM_SFT", 0, F(), \
+ "an 8-bit unsigned immediate with optional shift") \
+ Y(IMMEDIATE, advsimd_imm_modified, "SIMD_FPIMM", 0, F(), \
+ "an 8-bit floating-point constant") \
+ X(IMMEDIATE, 0, ext_shll_imm, "SHLL_IMM", 0, F(), \
+ "an immediate shift amount of 8, 16 or 32") \
+ X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0") \
+ X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0") \
+ Y(IMMEDIATE, imm, "FPIMM", 0, F(FLD_imm8), \
+ "an 8-bit floating-point constant") \
+ Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \
+ "the right rotate amount") \
+ Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6), \
+ "the leftmost bit number to be moved from the source") \
+ Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \
+ "the width of the bit-field") \
+ Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \
+ Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \
+ "a 3-bit unsigned immediate") \
+ Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \
+ "a 3-bit unsigned immediate") \
+ Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \
+ "a 4-bit unsigned immediate") \
+ Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \
+ "a 7-bit unsigned immediate") \
+ Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \
+ "the bit number to be tested") \
+ Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \
+ "a 16-bit unsigned immediate") \
+ Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \
+ "a 5-bit unsigned immediate") \
+ Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \
+ "a flag bit specifier giving an alternative value for each flag") \
+ Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \
+ "Logical immediate") \
+ Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \
+ "a 12-bit unsigned immediate with optional left shift of 12 bits")\
+ Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16), \
+ "a 16-bit immediate with optional left shift") \
+ Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \
+ "the number of bits after the binary point in the fixed-point value")\
+ X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \
+ Y(NIL, cond, "COND", 0, F(), "a condition") \
+ X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\
+ "21-bit PC-relative address of a 4KB page") \
+ Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
+ F(FLD_imm14), "14-bit PC-relative address") \
+ Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
+ F(FLD_imm19), "19-bit PC-relative address") \
+ Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \
+ "21-bit PC-relative address") \
+ Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
+ F(FLD_imm26), "26-bit PC-relative address") \
+ Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \
+ "an address with base register (no offset)") \
+ Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \
+ "an address with register offset") \
+ Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \
+ "an address with 7-bit signed immediate offset") \
+ Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \
+ "an address with 9-bit signed immediate offset") \
+ Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \
+ "an address with 9-bit negative or unaligned immediate offset") \
+ Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \
+ "an address with scaled, unsigned immediate offset") \
+ Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \
+ "an address with base register (no offset)") \
+ Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \
+ "a post-indexed address with immediate or register increment") \
+ Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \
+ Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \
+ "a PSTATE field name") \
+ Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \
+ "an address translation operation specifier") \
+ Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(), \
+ "a data cache maintenance operation specifier") \
+ Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(), \
+ "an instructin cache maintenance operation specifier") \
+ Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \
+ "a TBL invalidation operation specifier") \
+ Y(SYSTEM, barrier, "BARRIER", 0, F(), \
+ "a barrier option name") \
+ Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \
+ "the ISB option name SY or an optional 4-bit unsigned immediate") \
+ Y(SYSTEM, prfop, "PRFOP", 0, F(), \
+ "an prefetch operation specifier")
ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g`
archdefs="$archdefs -DARCH_$ad"
case "$arch" in
+ bfd_aarch64_arch) ta="$ta aarch64-asm.lo aarch64-dis.lo aarch64-opc.lo aarch64-asm-2.lo aarch64-dis-2.lo aarch64-opc-2.lo" ;;
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g`
archdefs="$archdefs -DARCH_$ad"
case "$arch" in
+ bfd_aarch64_arch) ta="$ta aarch64-asm.lo aarch64-dis.lo aarch64-opc.lo aarch64-asm-2.lo aarch64-dis-2.lo aarch64-opc-2.lo" ;;
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
#include "dis-asm.h"
#ifdef ARCH_all
+#define ARCH_aarch64
#define ARCH_alpha
#define ARCH_arc
#define ARCH_arm
{
/* If you add a case to this table, also add it to the
ARCH_all definition right above this function. */
+#ifdef ARCH_aarch64
+ case bfd_arch_aarch64:
+ disassemble = print_insn_aarch64;
+ break;
+#endif
#ifdef ARCH_alpha
case bfd_arch_alpha:
disassemble = print_insn_alpha;
disassembler_usage (stream)
FILE * stream ATTRIBUTE_UNUSED;
{
+#ifdef ARCH_aarch64
+ print_aarch64_disassembler_options (stream);
+#endif
#ifdef ARCH_arm
print_arm_disassembler_options (stream);
#endif
switch (info->arch)
{
+#ifdef ARCH_aarch64
+ case bfd_arch_aarch64:
+ info->symbol_is_valid = aarch64_symbol_is_valid;
+ info->disassembler_needs_relocs = TRUE;
+ break;
+#endif
#ifdef ARCH_arm
case bfd_arch_arm:
info->symbol_is_valid = arm_symbol_is_valid;
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