add PredicateBaseRM decode to CR Ops Simple mode as well as ff=3-bit

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 5712f5cab09f80c2e9c3059c401bd54cc8e82c3d..4345ac4185dfcc96d0bc4a08293590b9e2514365 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1715,7 +1715,7 @@ class CROpBaseRM(BaseRM):
     SNZ: BaseRM[7]
 
 
-class CROpSimpleRM(DZBaseRM, SZBaseRM, CROpBaseRM):
+class CROpSimpleRM(PredicateBaseRM, DZBaseRM, SZBaseRM, CROpBaseRM):
     """cr_op: simple mode"""
     RG: BaseRM[20]
     dz: BaseRM[22]
@@ -1734,7 +1734,7 @@ class CROpMRRM(MRBaseRM, DZBaseRM, SZBaseRM, CROpBaseRM):
     sz: BaseRM[23]
 
 
-class CROpFF3RM(VLiBaseRM, ZZBaseRM, CROpBaseRM):
+class CROpFF3RM(FFPRRc1BaseRM, VLiBaseRM, ZZBaseRM, PredicateBaseRM, CROpBaseRM):
     """cr_op: ffirst 3-bit mode"""
     VLi: BaseRM[20]
     inv: BaseRM[21]

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 45f212c2e06a7b8c5da52eedd0a656c5be6ff209..6c87f6d804504364ff1d3a4394cb1bd30dc31ead 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1385,7 +1385,7 @@ class SVP64Asm:
                 else:
                     assert dst_zero == src_zero, "dz must equal sz in ffirst BO"
                     mode |= (failfirst << SVP64MODE.BO_LSB)  # set BO
-                    svp64_rm.crops.zz = dst_zero
+                    svp64_rm.cr_op.zz = dst_zero
                 if vli:
                     sv_mode |= 1 # set VLI in LSB of 2-bit mode
                     #svp64_rm.cr_op.vli = 1

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index e76819b4d9ef916a745b2aea9920aebf0ad8d0f0..a335651d45435104b60c08307b0562d7a4d7bf21 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -67,6 +67,12 @@ class SVSTATETestCase(unittest.TestCase):
         expected = [
                     'sv.crand *16,*2,*33',
                     'sv.crand 12,2,33',
+                    'sv.crand/ff=eq/m=r10 12,2,33',
+                    'sv.crand/m=r10 12,2,33',
+                    'sv.crand/m=r10/sz 12,2,33',
+                    # XXX dz/sz is not the canonical way, must be zz
+                    'sv.crand/dz/m=r10/sz 12,2,33', # NOT OK
+                    'sv.crand/m=r10/zz 12,2,33',    # SHOULD PASS
                         ]
         self._do_tst(expected)