Merge branch 'mesa_7_7_branch'

Conflicts:
	src/gallium/state_trackers/xorg/xorg_xv.c
	src/mesa/drivers/dri/intel/intel_span.c

diff --cc src/gallium/drivers/svga/svga_screen_texture.c
index 3e2cb1a16d240063eab8e0d6a400126cdc0e9779,1eb03db2806b182ce1c8f3e4b2a9819f931f3546..3700a80bf169d248e94f824ede8fbc9e2efee856
--- 1/src/gallium/drivers/svga/svga_screen_texture.c
--- 2/src/gallium/drivers/svga/svga_screen_texture.c
+++ b/src/gallium/drivers/svga/svga_screen_texture.c
@@@ -970,12 -971,12 +970,12 @@@ svga_get_tex_sampler_view(struct pipe_c
                 "svga: Sampler view: no %p, mips %u..%u, nr %u, size (%ux%ux%u), last %u\n",
                 pt, min_lod, max_lod,
                 max_lod - min_lod + 1,
 -               pt->width[0],
 -               pt->height[0],
 -               pt->depth[0],
 +               pt->width0,
 +               pt->height0,
 +               pt->depth0,
                 pt->last_level);
        sv->key.cachable = 0;
-       sws->surface_reference(sws, &sv->handle, tex->handle);
+       sv->handle = tex->handle;
        return sv;
     }
  

diff --cc src/gallium/drivers/svga/svga_screen_texture.h
Simple merge

diff --cc src/gallium/drivers/svga/svga_state_constants.c
Simple merge

diff --cc src/gallium/state_trackers/xorg/xorg_crtc.c
Simple merge

diff --cc src/gallium/state_trackers/xorg/xorg_xv.c
Simple merge

diff --cc src/mesa/drivers/dri/i915/i830_texstate.c
Simple merge

diff --cc src/mesa/drivers/dri/i915/i830_vtbl.c
Simple merge

diff --cc src/mesa/drivers/dri/i915/i915_texstate.c
Simple merge

diff --cc src/mesa/drivers/dri/i915/i915_vtbl.c
Simple merge

diff --cc src/mesa/drivers/dri/intel/intel_blit.c
index f14854602b677b0b2bb3abab2aada0370a7b1637,9f638b0ef985c41a116fa0851db4e7151dbba057..cdf1408cd3314c1b86094398d09a632816c7c446
--- 1/src/mesa/drivers/dri/intel/intel_blit.c
--- 2/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@@ -496,14 -496,13 +496,14 @@@ intelClearWithBlit(GLcontext *ctx, GLbi
                  CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
                  CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
  
-                 switch (irb->texformat) {
+                 switch (irb->Base.Format) {
                  case MESA_FORMAT_ARGB8888:
                  case MESA_FORMAT_XRGB8888:
 -                   clearVal = intel->ClearColor8888;
 +                   clearVal = PACK_COLOR_8888(clear[3], clear[0],
 +                                              clear[1], clear[2]);
                     break;
                  case MESA_FORMAT_RGB565:
 -                   clearVal = intel->ClearColor565;
 +                   clearVal = PACK_COLOR_565(clear[0], clear[1], clear[2]);
                     break;
                  case MESA_FORMAT_ARGB4444:
                     clearVal = PACK_COLOR_4444(clear[3], clear[0],

diff --cc src/mesa/drivers/dri/intel/intel_span.c
index 2c89a66a95fda430a09a683cf3888c506575fe7e,34c3d9df74c99db401c4dae8adbe712b32924f9f..d1681e9088a36aa0a613e8258f836820355dabdc
--- 1/src/mesa/drivers/dri/intel/intel_span.c
--- 2/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@@ -613,10 -613,18 +613,10 @@@ intel_set_span_functions(struct intel_c
                         struct gl_renderbuffer *rb)
  {
     struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 -   uint32_t tiling;
 -
 -   /* If in GEM mode, we need to do the tile address swizzling ourselves,
 -    * instead of the fence registers handling it.
 -    */
 -   if (intel->ttm)
 -      tiling = irb->region->tiling;
 -   else
 -      tiling = I915_TILING_NONE;
 +   uint32_t tiling = irb->region->tiling;
  
     if (intel->intelScreen->kernel_exec_fencing) {
-       switch (irb->texformat) {
+       switch (irb->Base.Format) {
        case MESA_FORMAT_RGB565:
         intel_gttmap_InitPointers_RGB565(rb);
         break;
@@@ -665,10 -667,7 +659,10 @@@
        return;
     }
  
-    switch (irb->texformat) {
 +   /* If in GEM mode, we need to do the tile address swizzling ourselves,
 +    * instead of the fence registers handling it.
 +    */
+    switch (irb->Base.Format) {
     case MESA_FORMAT_RGB565:
        switch (tiling) {
        case I915_TILING_NONE:

diff --cc src/mesa/drivers/dri/r600/r700_chip.c
Simple merge

diff --cc src/mesa/main/context.c
Simple merge

diff --cc src/mesa/main/get.c
Simple merge

diff --cc src/mesa/main/get_gen.py
Simple merge

diff --cc src/mesa/main/mtypes.h
Simple merge

diff --cc src/mesa/main/texobj.c
Simple merge