i965: Reissue PIPELINE_POINTERS and BINDING_TABLE_POINTERS on SBA change.

This was a requirement we didn't run into until we started using
STATE_BASE_ADDRESS for instruction data.

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 559dc6886524af5247e3198026bc3f8d64ba5551..a8e2b80280315931dc9b970a5b83d69d26d70132 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -144,6 +144,7 @@ enum brw_state_id {
    BRW_STATE_VS_CONSTBUF,
    BRW_STATE_WM_CONSTBUF,
    BRW_STATE_PROGRAM_CACHE,
+   BRW_STATE_STATE_BASE_ADDRESS,
 };
 
 #define BRW_NEW_URB_FENCE               (1 << BRW_STATE_URB_FENCE)
@@ -174,6 +175,7 @@ enum brw_state_id {
 #define BRW_NEW_VS_CONSTBUF            (1 << BRW_STATE_VS_CONSTBUF)
 #define BRW_NEW_WM_CONSTBUF            (1 << BRW_STATE_WM_CONSTBUF)
 #define BRW_NEW_PROGRAM_CACHE          (1 << BRW_STATE_PROGRAM_CACHE)
+#define BRW_NEW_STATE_BASE_ADDRESS     (1 << BRW_STATE_STATE_BASE_ADDRESS)
 
 struct brw_state_flags {
    /** State update flags signalled by mesa internals */

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index ea2e6013de60e82ea615389e7b1caa0fb92b303c..033c77cd32150c9a461fe3ff01613801e33854eb 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -87,10 +87,11 @@ static void upload_binding_table_pointers(struct brw_context *brw)
 const struct brw_tracked_state brw_binding_table_pointers = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_BATCH
-          | BRW_NEW_VS_BINDING_TABLE
-          | BRW_NEW_GS_BINDING_TABLE
-          | BRW_NEW_PS_BINDING_TABLE,
+      .brw = (BRW_NEW_BATCH |
+             BRW_NEW_STATE_BASE_ADDRESS |
+             BRW_NEW_VS_BINDING_TABLE |
+             BRW_NEW_GS_BINDING_TABLE |
+             BRW_NEW_PS_BINDING_TABLE),
       .cache = 0,
    },
    .emit = upload_binding_table_pointers,
@@ -122,10 +123,11 @@ static void upload_gen6_binding_table_pointers(struct brw_context *brw)
 const struct brw_tracked_state gen6_binding_table_pointers = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_BATCH
-          | BRW_NEW_VS_BINDING_TABLE
-          | BRW_NEW_GS_BINDING_TABLE
-          | BRW_NEW_PS_BINDING_TABLE,
+      .brw = (BRW_NEW_BATCH |
+             BRW_NEW_STATE_BASE_ADDRESS |
+             BRW_NEW_VS_BINDING_TABLE |
+             BRW_NEW_GS_BINDING_TABLE |
+             BRW_NEW_PS_BINDING_TABLE),
       .cache = 0,
    },
    .emit = upload_gen6_binding_table_pointers,
@@ -180,7 +182,9 @@ static void upload_psp_urb_cbs(struct brw_context *brw )
 const struct brw_tracked_state brw_psp_urb_cbs = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_URB_FENCE | BRW_NEW_BATCH,
+      .brw = (BRW_NEW_URB_FENCE |
+             BRW_NEW_BATCH |
+             BRW_NEW_STATE_BASE_ADDRESS),
       .cache = (CACHE_NEW_VS_UNIT | 
                CACHE_NEW_GS_UNIT | 
                CACHE_NEW_GS_PROG | 
@@ -708,6 +712,15 @@ static void upload_state_base_address( struct brw_context *brw )
 {
    struct intel_context *intel = &brw->intel;
 
+   /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
+    * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
+    * programmed prior to STATE_BASE_ADDRESS.
+    *
+    * However, given that the instruction SBA (general state base
+    * address) on this chipset is always set to 0 across X and GL,
+    * maybe this isn't required for us in particular.
+    */
+
    if (intel->gen >= 6) {
       if (intel->gen == 6)
         intel_emit_post_sync_nonzero_flush(intel);
@@ -767,6 +780,30 @@ static void upload_state_base_address( struct brw_context *brw )
        OUT_BATCH(1); /* Indirect object upper bound */
        ADVANCE_BATCH();
    }
+
+   /* According to section 3.6.1 of VOL1 of the 965 PRM,
+    * STATE_BASE_ADDRESS updates require a reissue of:
+    *
+    * 3DSTATE_PIPELINE_POINTERS
+    * 3DSTATE_BINDING_TABLE_POINTERS
+    * MEDIA_STATE_POINTERS
+    *
+    * and this continues through Ironlake.  The Sandy Bridge PRM, vol
+    * 1 part 1 says that the folowing packets must be reissued:
+    *
+    * 3DSTATE_CC_POINTERS
+    * 3DSTATE_BINDING_TABLE_POINTERS
+    * 3DSTATE_SAMPLER_STATE_POINTERS
+    * 3DSTATE_VIEWPORT_STATE_POINTERS
+    * MEDIA_STATE_POINTERS
+    *
+    * Those are always reissued following SBA updates anyway (new
+    * batch time), except in the case of the program cache BO
+    * changing.  Having a separate state flag makes the sequence more
+    * obvious.
+    */
+
+   brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;
 }
 
 const struct brw_tracked_state brw_state_base_address = {

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 50ab490f339fcda744a9851e0bc8588794445cdf..76ffa0daefe7a9e9d78a26d16354ac6e3f575737 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -379,6 +379,7 @@ static struct dirty_bit_map brw_bits[] = {
    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
+   DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
    {0, 0, 0}
 };
 

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 2b16d6cdc019b2a9f509c3dd975b6f753ded13c1..294d5a5e6446c8ca0f27c75d305ed168697efcf4 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -183,7 +183,8 @@ static void upload_cc_state_pointers(struct brw_context *brw)
 const struct brw_tracked_state gen6_cc_state_pointers = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_BATCH,
+      .brw = (BRW_NEW_BATCH |
+             BRW_NEW_STATE_BASE_ADDRESS),
       .cache = (CACHE_NEW_BLEND_STATE |
                CACHE_NEW_COLOR_CALC_STATE |
                CACHE_NEW_DEPTH_STENCIL_STATE)

diff --git a/src/mesa/drivers/dri/i965/gen6_sampler_state.c b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
index 4cdec699df6d044edc995c0574e36ec22d5a9265..89326872faa90cfb13c93deedf5022e66b79cdee 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
@@ -50,7 +50,8 @@ upload_sampler_state_pointers(struct brw_context *brw)
 const struct brw_tracked_state gen6_sampler_state = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_BATCH,
+      .brw = (BRW_NEW_BATCH |
+             BRW_NEW_STATE_BASE_ADDRESS),
       .cache = CACHE_NEW_SAMPLER
    },
    .emit = upload_sampler_state_pointers,

diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
index 4116bdb96dece5140da4e4b21ea027125b621bb6..c6c55c926c7b0ee94c9fd5ea5a007af437457555 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -122,7 +122,8 @@ static void upload_viewport_state_pointers(struct brw_context *brw)
 const struct brw_tracked_state gen6_viewport_state = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_BATCH,
+      .brw = (BRW_NEW_BATCH |
+             BRW_NEW_STATE_BASE_ADDRESS),
       .cache = (CACHE_NEW_CLIP_VP |
                CACHE_NEW_SF_VP |
                CACHE_NEW_CC_VP)