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diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index ac7c8da875cdcb83dbc1f788ed402c90905054a9..5498a92e040627e3b41853cd23b175cf90cd4235 100644 (file)
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -59,11 +59,12 @@ Notes:
   loading instruction.
 2. There is no need for Special Registers (FP Flags) because this
   is an immediate loading instruction.  No FPR Load Operations
-  alter `FPSCR` and neither does `lxvkq`
+  alter `FPSCR`, neither does `lxvkq`, and on that basis neither
+  should these instructions.
 3. EXT001 Variants which also save similar Data-Load and Data-TLB
   lookups are mentioned for completeness but not included as part
-  of this RFC. Another Stakeholder may wish to consider submitting
-  them.
+  of this RFC. Another Stakeholder with a vested interest in 64-bit
+  Prefixed instructions may wish to consider submitting them.
 4. `fishmv` as a Read-Modify-Write saves five unnecessary bits, making
   the difference between a VA/DX-Form and requiring an entire Major
   Opcode.