re PR inline-asm/93202 ([RISCV] ICE when using inline asm 'h' operand modifier)

	PR inline-asm/93202
	* config/riscv/riscv.c (riscv_print_operand_reloc): Use
	output_operand_lossage instead of gcc_unreachable.
	* doc/md.texi (riscv f constraint): Fix typo.

	* gcc.target/riscv/pr93202.c: New test.

From-SVN: r280030

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2756a97c47611500429db0d8112398b7fbb31675..1fda5d1fc39a3acd2abdcaf420ea457db2600dc4 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
 2020-01-09  Jakub Jelinek  <jakub@redhat.com>
 
+       PR inline-asm/93202
+       * config/riscv/riscv.c (riscv_print_operand_reloc): Use
+       output_operand_lossage instead of gcc_unreachable.
+       * doc/md.texi (riscv f constraint): Fix typo.
+
        PR target/93141
        * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of
        SWI.  Use <general_hilo_operand> instead of <general_operand>.  Use

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 4ba811126feb866f39ab4cf0a26bf4cb550d3ed3..320a70b9c863625d50da2571d322bdb0f4ab1cc9 100644 (file)
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3191,7 +3191,8 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc)
        break;
 
       default:
-       gcc_unreachable ();
+       output_operand_lossage ("invalid use of '%%%c'", hi_reloc ? 'h' : 'R');
+       return;
     }
 
   fprintf (file, "%s(", reloc);

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index cc4a2927a1de42c18dd3ad5adc4b98ebf8260c8e..cec74ea78eae4f76cd0442a85501a4e9d68db44d 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3518,7 +3518,7 @@ The @code{X} register.
 @table @code
 
 @item f
-A floating-point register (if availiable).
+A floating-point register (if available).
 
 @item I
 An I-type 12-bit signed immediate.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 53766afc0c6566417caee9c41893a17620fc81e8..b4e4f83f4e70f7b46b085ed893fc54de15573f46 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,8 @@
 2020-01-09  Jakub Jelinek  <jakub@redhat.com>
 
+       PR inline-asm/93202
+       * gcc.target/riscv/pr93202.c: New test.
+
        PR target/93141
        * gcc.target/i386/pr93141-1.c: Add tests with constants that have MSB
        of the low half of the constant set.

diff --git a/gcc/testsuite/gcc.target/riscv/pr93202.c b/gcc/testsuite/gcc.target/riscv/pr93202.c
new file mode 100644 (file)
index 0000000..d8091b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr93202.c
@@ -0,0 +1,10 @@
+/* PR inline-asm/93202 */
+/* { dg-do compile { target fpic } } */
+/* { dg-options "-fpic" } */
+
+void
+foo (void)
+{
+  asm volatile ("%h0" :: "i" (&foo));  /* { dg-error "invalid use of '%h'" } */
+  asm volatile ("%R0" :: "i" (&foo));  /* { dg-error "invalid use of '%R'" } */
+}