'prefix': 'i686',
},
'xtensa-lx60': {
- 'conditions': ['BR2_xtensa', 'BR2_xtensa_fsf'],
+ 'conditions': ['BR2_xtensa', 'BR2_XTENSA_CUSTOM', 'BR2_XTENSA_LITTLE_ENDIAN'],
'prefix': 'xtensa',
},
}
class TestExternalToolchainBootlinXtensalx60UclibcBleedingEdge(TestExternalToolchain):
config = """
BR2_xtensa=y
- BR2_xtensa_fsf=y
+ BR2_XTENSA_CUSTOM=y
+ BR2_XTENSA_LITTLE_ENDIAN=y
BR2_TOOLCHAIN_EXTERNAL=y
BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_XTENSA_LX60_UCLIBC_BLEEDING_EDGE=y
class TestExternalToolchainBootlinXtensalx60UclibcStable(TestExternalToolchain):
config = """
BR2_xtensa=y
- BR2_xtensa_fsf=y
+ BR2_XTENSA_CUSTOM=y
+ BR2_XTENSA_LITTLE_ENDIAN=y
BR2_TOOLCHAIN_EXTERNAL=y
BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y
BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_XTENSA_LX60_UCLIBC_STABLE=y
default y if BR2_x86_64 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3 && BR2_X86_CPU_HAS_SSE4 && BR2_X86_CPU_HAS_SSE42
default y if BR2_i386 && BR2_X86_CPU_HAS_MMX && BR2_X86_CPU_HAS_SSE && BR2_X86_CPU_HAS_SSE2 && BR2_X86_CPU_HAS_SSE3 && BR2_X86_CPU_HAS_SSSE3
default y if BR2_i386 && !BR2_x86_i486 && !BR2_x86_i586 && !BR2_x86_x1000
- default y if BR2_xtensa && BR2_xtensa_fsf
+ default y if BR2_xtensa && BR2_XTENSA_CUSTOM && BR2_XTENSA_LITTLE_ENDIAN
if BR2_TOOLCHAIN_EXTERNAL_BOOTLIN
config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_XTENSA_LX60_UCLIBC_BLEEDING_EDGE
bool "xtensa-lx60 uclibc bleeding-edge 2020.08-1"
depends on BR2_xtensa
- depends on BR2_xtensa_fsf
+ depends on BR2_XTENSA_CUSTOM
+ depends on BR2_XTENSA_LITTLE_ENDIAN
select BR2_TOOLCHAIN_GCC_AT_LEAST_10
select BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4
select BR2_USE_WCHAR
config BR2_TOOLCHAIN_EXTERNAL_BOOTLIN_XTENSA_LX60_UCLIBC_STABLE
bool "xtensa-lx60 uclibc stable 2020.08-1"
depends on BR2_xtensa
- depends on BR2_xtensa_fsf
+ depends on BR2_XTENSA_CUSTOM
+ depends on BR2_XTENSA_LITTLE_ENDIAN
select BR2_TOOLCHAIN_GCC_AT_LEAST_9
select BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_9
select BR2_USE_WCHAR