Handle misaligned TFmode load/store.

gcc/

2011-05-30  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/49168
	* config/i386/i386.md (*movtf_internal): Handle misaligned
	load/store.

gcc/testsuite/

2011-05-30  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/49168
	 * gcc.target/i386/pr49168-1.c: New.

From-SVN: r174451

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5e9badfde866bc63f4f21bdd7dc42a7b03efc91a..45212c0dfe0793deacf60c6e894bfd15627ec922 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-05-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/49168
+       * config/i386/i386.md (*movtf_internal): Handle misaligned
+       load/store.
+
 2011-05-30  Jakub Jelinek  <jakub@redhat.com>
 
        * dwarf2out.c (modified_type_die, gen_reference_type_die): Use

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 89e11730faa087c8f28b64c1f7602da4ab7c081d..6d3ae803998c59d3b5219cd0bcbe927c33ee03de 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2842,10 +2842,23 @@
     {
     case 0:
     case 1:
-      if (get_attr_mode (insn) == MODE_V4SF)
-       return "%vmovaps\t{%1, %0|%0, %1}";
+      /* Handle misaligned load/store since we don't have movmisaligntf
+        pattern. */
+      if (misaligned_operand (operands[0], TFmode)
+         || misaligned_operand (operands[1], TFmode))
+       {
+         if (get_attr_mode (insn) == MODE_V4SF)
+           return "%vmovups\t{%1, %0|%0, %1}";
+         else
+           return "%vmovdqu\t{%1, %0|%0, %1}";
+       }
       else
-       return "%vmovdqa\t{%1, %0|%0, %1}";
+       {
+         if (get_attr_mode (insn) == MODE_V4SF)
+           return "%vmovaps\t{%1, %0|%0, %1}";
+         else
+           return "%vmovdqa\t{%1, %0|%0, %1}";
+       }
 
     case 2:
       return standard_sse_constant_opcode (insn, operands[1]);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e80c1b2c9b2450bf4bade4bc9ab09a31a92dd92d..d8b0ef5446d90cd70097cd98ad888647586f5bb2 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2011-05-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/49168
+        * gcc.target/i386/pr49168-1.c: New.
+
 2011-05-30  Jakub Jelinek  <jakub@redhat.com>
            Eric Botcazou  <ebotcazou@adacore.com>
 

diff --git a/gcc/testsuite/gcc.target/i386/pr49168-1.c b/gcc/testsuite/gcc.target/i386/pr49168-1.c
new file mode 100644 (file)
index 0000000..9676dc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr49168-1.c
@@ -0,0 +1,11 @@
+/* PR target/49168  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movdqa\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */
+/* { dg-final { scan-assembler "movdqu\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */
+
+void
+flt128_va (void *mem, __float128 d)
+{ 
+  __builtin_memcpy (mem, &d, sizeof (d));
+}