M_LOAD(ld_cubemap_coords);
M_LOAD(ld_compute_id);
-static midgard_instruction
-v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
-{
- midgard_branch_cond branch = {
- .op = op,
- .dest_tag = tag,
- .offset = offset,
- .cond = cond
- };
-
- uint16_t compact;
- memcpy(&compact, &branch, sizeof(branch));
-
- midgard_instruction ins = {
- .type = TAG_ALU_4,
- .unit = ALU_ENAB_BR_COMPACT,
- .prepacked_branch = true,
- .compact_branch = true,
- .br_compact = compact,
- .dest = ~0,
- .src = { ~0, ~0, ~0, ~0 },
- };
-
- if (op == midgard_jmp_writeout_op_writeout)
- ins.writeout = true;
-
- return ins;
-}
-
static midgard_instruction
v_branch(bool conditional, bool invert)
{
mir_foreach_instr_in_block(block, ins) {
if (ins->type != TAG_ALU_4) continue;
if (!ins->compact_branch) continue;
- if (ins->prepacked_branch) continue;
/* We found a branch -- check the type to see if we need to do anything */
if (ins->branch.target_type != TARGET_BREAK) continue;
if (!midgard_is_branch_unit(ins->unit)) continue;
- if (ins->prepacked_branch) continue;
-
/* Parse some basic branch info */
bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
bool is_conditional = ins->branch.conditional;
midgard_instruction *ins = bundle->instructions[i];
/* Check if this instruction has registers */
- if (ins->compact_branch || ins->prepacked_branch) continue;
+ if (ins->compact_branch) continue;
/* Otherwise, just emit the registers */
uint16_t reg_word = 0;
"goto", "break", "continue", "discard"
};
- if (ins->compact_branch && !ins->prepacked_branch)
+ if (ins->compact_branch)
name = branch_target_names[ins->branch.target_type];
if (ins->unit)
assert(0);
}
- if (ins->invert || (ins->compact_branch && !ins->prepacked_branch && ins->branch.invert_conditional))
+ if (ins->invert || (ins->compact_branch && ins->branch.invert_conditional))
printf(".not");
printf(" ");
continue;
bool conditional = alu && !branch && OP_IS_CSEL(instructions[i]->alu.op);
- conditional |= (branch && !instructions[i]->prepacked_branch && instructions[i]->branch.conditional);
+ conditional |= (branch && instructions[i]->branch.conditional);
if (conditional && no_cond)
continue;
mir_update_worklist(worklist, len, instructions, branch);
bool writeout = branch && branch->writeout;
- if (branch && !branch->prepacked_branch && branch->branch.conditional) {
+ if (branch && branch->branch.conditional) {
midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, branch);
if (cond->unit == UNIT_VADD)