host: add support for various csr_data width (8 & 32 tested, but should work with...

diff --git a/miscope/host/regs.py b/miscope/host/regs.py
index 3b5cdb3b8b9d60dba4c63f790c5c963a70aa5f7d..0eaef44431af58c57907beac4e1b29fdb7c643dd 100644 (file)
--- a/miscope/host/regs.py
+++ b/miscope/host/regs.py
@@ -1,11 +1,12 @@
 import csv
 
 class MappedReg:
-       def __init__(self, readfn, writefn, name, addr, length, mode):
+       def __init__(self, readfn, writefn, name, addr, length, busword, mode):
                self.readfn = readfn
                self.writefn = writefn
                self.addr = addr
                self.length = length
+               self.busword = busword
                self.mode = mode
 
        def read(self):
@@ -15,14 +16,14 @@ class MappedReg:
                for i in range(self.length):
                        r |= self.readfn(self.addr + 4*i)
                        if i != (self.length-1):
-                               r <<= 8
+                               r <<= self.busword
                return r
 
        def write(self, value):
                if self.mode not in ["rw", "wo"]:
                        raise KeyError(name + "register not writable")
                for i in range(self.length):
-                       dat = (value >> ((self.length-1-i)*8)) & 0xff
+                       dat = (value >> ((self.length-1-i)*self.busword)) & (2**self.busword-1)
                        self.writefn(self.addr + 4*i, dat)
 
 class MappedRegs:
@@ -37,12 +38,12 @@ class MappedRegs:
 
                raise KeyError("No such register " + attr)
 
-def    build_map(addrmap, readfn, writefn):
+def    build_map(addrmap, busword, readfn, writefn):
        csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
        d = {}
        for item in csv_reader:
                name, addr, length, mode = item
                addr = int(addr.replace("0x", ""), 16)
                length = int(length)
-               d[name] = MappedReg(readfn, writefn, name, addr, length, mode)
+               d[name] = MappedReg(readfn, writefn, name, addr, length, busword, mode)
        return MappedRegs(d)
\ No newline at end of file

diff --git a/miscope/host/uart2wishbone.py b/miscope/host/uart2wishbone.py
index ebed0614905fb9a6a08643303824d851d6f536cb..01fa0103e2bc8f94d08956c3edcf000016a7fcb8 100644 (file)
--- a/miscope/host/uart2wishbone.py
+++ b/miscope/host/uart2wishbone.py
@@ -10,12 +10,12 @@ def write_b(uart, data):
 class Uart2Wishbone:
        WRITE_CMD  = 0x01
        READ_CMD   = 0x02
-       def __init__(self, port, baudrate=115200, addrmap=None, debug=False):
+       def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
                self.port = port
                self.baudrate = str(baudrate)
                self.debug = debug
                self.uart = serial.Serial(port, baudrate, timeout=0.25)
-               self.regs = build_map(addrmap, self.read, self.write)
+               self.regs = build_map(addrmap, busword, self.read, self.write)
 
        def open(self):
                self.uart.flushOutput()